1//=== A15SDOptimizerPass.cpp - Optimize DPR and SPR register accesses on A15==//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// The Cortex-A15 processor employs a tracking scheme in its register renaming
11// in order to process each instruction's micro-ops speculatively and
12// out-of-order with appropriate forwarding. The ARM architecture allows VFP
13// instructions to read and write 32-bit S-registers.  Each S-register
14// corresponds to one half (upper or lower) of an overlaid 64-bit D-register.
15//
16// There are several instruction patterns which can be used to provide this
17// capability which can provide higher performance than other, potentially more
18// direct patterns, specifically around when one micro-op reads a D-register
19// operand that has recently been written as one or more S-register results.
20//
21// This file defines a pre-regalloc pass which looks for SPR producers which
22// are going to be used by a DPR (or QPR) consumers and creates the more
23// optimized access pattern.
24//
25//===----------------------------------------------------------------------===//
26
27#include "ARM.h"
28#include "ARMBaseInstrInfo.h"
29#include "ARMBaseRegisterInfo.h"
30#include "llvm/ADT/Statistic.h"
31#include "llvm/CodeGen/MachineFunctionPass.h"
32#include "llvm/CodeGen/MachineInstr.h"
33#include "llvm/CodeGen/MachineInstrBuilder.h"
34#include "llvm/CodeGen/MachineRegisterInfo.h"
35#include "llvm/Support/Debug.h"
36#include "llvm/Target/TargetRegisterInfo.h"
37#include <set>
38
39using namespace llvm;
40
41#define DEBUG_TYPE "a15-sd-optimizer"
42
43namespace {
44  struct A15SDOptimizer : public MachineFunctionPass {
45    static char ID;
46    A15SDOptimizer() : MachineFunctionPass(ID) {}
47
48    bool runOnMachineFunction(MachineFunction &Fn) override;
49
50    const char *getPassName() const override {
51      return "ARM A15 S->D optimizer";
52    }
53
54  private:
55    const ARMBaseInstrInfo *TII;
56    const TargetRegisterInfo *TRI;
57    MachineRegisterInfo *MRI;
58
59    bool runOnInstruction(MachineInstr *MI);
60
61    //
62    // Instruction builder helpers
63    //
64    unsigned createDupLane(MachineBasicBlock &MBB,
65                           MachineBasicBlock::iterator InsertBefore,
66                           DebugLoc DL,
67                           unsigned Reg, unsigned Lane,
68                           bool QPR=false);
69
70    unsigned createExtractSubreg(MachineBasicBlock &MBB,
71                                 MachineBasicBlock::iterator InsertBefore,
72                                 DebugLoc DL,
73                                 unsigned DReg, unsigned Lane,
74                                 const TargetRegisterClass *TRC);
75
76    unsigned createVExt(MachineBasicBlock &MBB,
77                        MachineBasicBlock::iterator InsertBefore,
78                        DebugLoc DL,
79                        unsigned Ssub0, unsigned Ssub1);
80
81    unsigned createRegSequence(MachineBasicBlock &MBB,
82                               MachineBasicBlock::iterator InsertBefore,
83                               DebugLoc DL,
84                               unsigned Reg1, unsigned Reg2);
85
86    unsigned createInsertSubreg(MachineBasicBlock &MBB,
87                                MachineBasicBlock::iterator InsertBefore,
88                                DebugLoc DL, unsigned DReg, unsigned Lane,
89                                unsigned ToInsert);
90
91    unsigned createImplicitDef(MachineBasicBlock &MBB,
92                               MachineBasicBlock::iterator InsertBefore,
93                               DebugLoc DL);
94
95    //
96    // Various property checkers
97    //
98    bool usesRegClass(MachineOperand &MO, const TargetRegisterClass *TRC);
99    bool hasPartialWrite(MachineInstr *MI);
100    SmallVector<unsigned, 8> getReadDPRs(MachineInstr *MI);
101    unsigned getDPRLaneFromSPR(unsigned SReg);
102
103    //
104    // Methods used for getting the definitions of partial registers
105    //
106
107    MachineInstr *elideCopies(MachineInstr *MI);
108    void elideCopiesAndPHIs(MachineInstr *MI,
109                            SmallVectorImpl<MachineInstr*> &Outs);
110
111    //
112    // Pattern optimization methods
113    //
114    unsigned optimizeAllLanesPattern(MachineInstr *MI, unsigned Reg);
115    unsigned optimizeSDPattern(MachineInstr *MI);
116    unsigned getPrefSPRLane(unsigned SReg);
117
118    //
119    // Sanitizing method - used to make sure if don't leave dead code around.
120    //
121    void eraseInstrWithNoUses(MachineInstr *MI);
122
123    //
124    // A map used to track the changes done by this pass.
125    //
126    std::map<MachineInstr*, unsigned> Replacements;
127    std::set<MachineInstr *> DeadInstr;
128  };
129  char A15SDOptimizer::ID = 0;
130} // end anonymous namespace
131
132// Returns true if this is a use of a SPR register.
133bool A15SDOptimizer::usesRegClass(MachineOperand &MO,
134                                  const TargetRegisterClass *TRC) {
135  if (!MO.isReg())
136    return false;
137  unsigned Reg = MO.getReg();
138
139  if (TargetRegisterInfo::isVirtualRegister(Reg))
140    return MRI->getRegClass(Reg)->hasSuperClassEq(TRC);
141  else
142    return TRC->contains(Reg);
143}
144
145unsigned A15SDOptimizer::getDPRLaneFromSPR(unsigned SReg) {
146  unsigned DReg = TRI->getMatchingSuperReg(SReg, ARM::ssub_1,
147                                           &ARM::DPRRegClass);
148  if (DReg != ARM::NoRegister) return ARM::ssub_1;
149  return ARM::ssub_0;
150}
151
152// Get the subreg type that is most likely to be coalesced
153// for an SPR register that will be used in VDUP32d pseudo.
154unsigned A15SDOptimizer::getPrefSPRLane(unsigned SReg) {
155  if (!TRI->isVirtualRegister(SReg))
156    return getDPRLaneFromSPR(SReg);
157
158  MachineInstr *MI = MRI->getVRegDef(SReg);
159  if (!MI) return ARM::ssub_0;
160  MachineOperand *MO = MI->findRegisterDefOperand(SReg);
161
162  assert(MO->isReg() && "Non-register operand found!");
163  if (!MO) return ARM::ssub_0;
164
165  if (MI->isCopy() && usesRegClass(MI->getOperand(1),
166                                    &ARM::SPRRegClass)) {
167    SReg = MI->getOperand(1).getReg();
168  }
169
170  if (TargetRegisterInfo::isVirtualRegister(SReg)) {
171    if (MO->getSubReg() == ARM::ssub_1) return ARM::ssub_1;
172    return ARM::ssub_0;
173  }
174  return getDPRLaneFromSPR(SReg);
175}
176
177// MI is known to be dead. Figure out what instructions
178// are also made dead by this and mark them for removal.
179void A15SDOptimizer::eraseInstrWithNoUses(MachineInstr *MI) {
180  SmallVector<MachineInstr *, 8> Front;
181  DeadInstr.insert(MI);
182
183  DEBUG(dbgs() << "Deleting base instruction " << *MI << "\n");
184  Front.push_back(MI);
185
186  while (Front.size() != 0) {
187    MI = Front.back();
188    Front.pop_back();
189
190    // MI is already known to be dead. We need to see
191    // if other instructions can also be removed.
192    for (unsigned int i = 0; i < MI->getNumOperands(); ++i) {
193      MachineOperand &MO = MI->getOperand(i);
194      if ((!MO.isReg()) || (!MO.isUse()))
195        continue;
196      unsigned Reg = MO.getReg();
197      if (!TRI->isVirtualRegister(Reg))
198        continue;
199      MachineOperand *Op = MI->findRegisterDefOperand(Reg);
200
201      if (!Op)
202        continue;
203
204      MachineInstr *Def = Op->getParent();
205
206      // We don't need to do anything if we have already marked
207      // this instruction as being dead.
208      if (DeadInstr.find(Def) != DeadInstr.end())
209        continue;
210
211      // Check if all the uses of this instruction are marked as
212      // dead. If so, we can also mark this instruction as being
213      // dead.
214      bool IsDead = true;
215      for (unsigned int j = 0; j < Def->getNumOperands(); ++j) {
216        MachineOperand &MODef = Def->getOperand(j);
217        if ((!MODef.isReg()) || (!MODef.isDef()))
218          continue;
219        unsigned DefReg = MODef.getReg();
220        if (!TRI->isVirtualRegister(DefReg)) {
221          IsDead = false;
222          break;
223        }
224        for (MachineRegisterInfo::use_instr_iterator
225             II = MRI->use_instr_begin(Reg), EE = MRI->use_instr_end();
226             II != EE; ++II) {
227          // We don't care about self references.
228          if (&*II == Def)
229            continue;
230          if (DeadInstr.find(&*II) == DeadInstr.end()) {
231            IsDead = false;
232            break;
233          }
234        }
235      }
236
237      if (!IsDead) continue;
238
239      DEBUG(dbgs() << "Deleting instruction " << *Def << "\n");
240      DeadInstr.insert(Def);
241    }
242  }
243}
244
245// Creates the more optimized patterns and generally does all the code
246// transformations in this pass.
247unsigned A15SDOptimizer::optimizeSDPattern(MachineInstr *MI) {
248  if (MI->isCopy()) {
249    return optimizeAllLanesPattern(MI, MI->getOperand(1).getReg());
250  }
251
252  if (MI->isInsertSubreg()) {
253    unsigned DPRReg = MI->getOperand(1).getReg();
254    unsigned SPRReg = MI->getOperand(2).getReg();
255
256    if (TRI->isVirtualRegister(DPRReg) && TRI->isVirtualRegister(SPRReg)) {
257      MachineInstr *DPRMI = MRI->getVRegDef(MI->getOperand(1).getReg());
258      MachineInstr *SPRMI = MRI->getVRegDef(MI->getOperand(2).getReg());
259
260      if (DPRMI && SPRMI) {
261        // See if the first operand of this insert_subreg is IMPLICIT_DEF
262        MachineInstr *ECDef = elideCopies(DPRMI);
263        if (ECDef && ECDef->isImplicitDef()) {
264          // Another corner case - if we're inserting something that is purely
265          // a subreg copy of a DPR, just use that DPR.
266
267          MachineInstr *EC = elideCopies(SPRMI);
268          // Is it a subreg copy of ssub_0?
269          if (EC && EC->isCopy() &&
270              EC->getOperand(1).getSubReg() == ARM::ssub_0) {
271            DEBUG(dbgs() << "Found a subreg copy: " << *SPRMI);
272
273            // Find the thing we're subreg copying out of - is it of the same
274            // regclass as DPRMI? (i.e. a DPR or QPR).
275            unsigned FullReg = SPRMI->getOperand(1).getReg();
276            const TargetRegisterClass *TRC =
277              MRI->getRegClass(MI->getOperand(1).getReg());
278            if (TRC->hasSuperClassEq(MRI->getRegClass(FullReg))) {
279              DEBUG(dbgs() << "Subreg copy is compatible - returning ");
280              DEBUG(dbgs() << PrintReg(FullReg) << "\n");
281              eraseInstrWithNoUses(MI);
282              return FullReg;
283            }
284          }
285
286          return optimizeAllLanesPattern(MI, MI->getOperand(2).getReg());
287        }
288      }
289    }
290    return optimizeAllLanesPattern(MI, MI->getOperand(0).getReg());
291  }
292
293  if (MI->isRegSequence() && usesRegClass(MI->getOperand(1),
294                                          &ARM::SPRRegClass)) {
295    // See if all bar one of the operands are IMPLICIT_DEF and insert the
296    // optimizer pattern accordingly.
297    unsigned NumImplicit = 0, NumTotal = 0;
298    unsigned NonImplicitReg = ~0U;
299
300    for (unsigned I = 1; I < MI->getNumExplicitOperands(); ++I) {
301      if (!MI->getOperand(I).isReg())
302        continue;
303      ++NumTotal;
304      unsigned OpReg = MI->getOperand(I).getReg();
305
306      if (!TRI->isVirtualRegister(OpReg))
307        break;
308
309      MachineInstr *Def = MRI->getVRegDef(OpReg);
310      if (!Def)
311        break;
312      if (Def->isImplicitDef())
313        ++NumImplicit;
314      else
315        NonImplicitReg = MI->getOperand(I).getReg();
316    }
317
318    if (NumImplicit == NumTotal - 1)
319      return optimizeAllLanesPattern(MI, NonImplicitReg);
320    else
321      return optimizeAllLanesPattern(MI, MI->getOperand(0).getReg());
322  }
323
324  llvm_unreachable("Unhandled update pattern!");
325}
326
327// Return true if this MachineInstr inserts a scalar (SPR) value into
328// a D or Q register.
329bool A15SDOptimizer::hasPartialWrite(MachineInstr *MI) {
330  // The only way we can do a partial register update is through a COPY,
331  // INSERT_SUBREG or REG_SEQUENCE.
332  if (MI->isCopy() && usesRegClass(MI->getOperand(1), &ARM::SPRRegClass))
333    return true;
334
335  if (MI->isInsertSubreg() && usesRegClass(MI->getOperand(2),
336                                           &ARM::SPRRegClass))
337    return true;
338
339  if (MI->isRegSequence() && usesRegClass(MI->getOperand(1), &ARM::SPRRegClass))
340    return true;
341
342  return false;
343}
344
345// Looks through full copies to get the instruction that defines the input
346// operand for MI.
347MachineInstr *A15SDOptimizer::elideCopies(MachineInstr *MI) {
348  if (!MI->isFullCopy())
349    return MI;
350  if (!TRI->isVirtualRegister(MI->getOperand(1).getReg()))
351    return nullptr;
352  MachineInstr *Def = MRI->getVRegDef(MI->getOperand(1).getReg());
353  if (!Def)
354    return nullptr;
355  return elideCopies(Def);
356}
357
358// Look through full copies and PHIs to get the set of non-copy MachineInstrs
359// that can produce MI.
360void A15SDOptimizer::elideCopiesAndPHIs(MachineInstr *MI,
361                                        SmallVectorImpl<MachineInstr*> &Outs) {
362   // Looking through PHIs may create loops so we need to track what
363   // instructions we have visited before.
364   std::set<MachineInstr *> Reached;
365   SmallVector<MachineInstr *, 8> Front;
366   Front.push_back(MI);
367   while (Front.size() != 0) {
368     MI = Front.back();
369     Front.pop_back();
370
371     // If we have already explored this MachineInstr, ignore it.
372     if (Reached.find(MI) != Reached.end())
373       continue;
374     Reached.insert(MI);
375     if (MI->isPHI()) {
376       for (unsigned I = 1, E = MI->getNumOperands(); I != E; I += 2) {
377         unsigned Reg = MI->getOperand(I).getReg();
378         if (!TRI->isVirtualRegister(Reg)) {
379           continue;
380         }
381         MachineInstr *NewMI = MRI->getVRegDef(Reg);
382         if (!NewMI)
383           continue;
384         Front.push_back(NewMI);
385       }
386     } else if (MI->isFullCopy()) {
387       if (!TRI->isVirtualRegister(MI->getOperand(1).getReg()))
388         continue;
389       MachineInstr *NewMI = MRI->getVRegDef(MI->getOperand(1).getReg());
390       if (!NewMI)
391         continue;
392       Front.push_back(NewMI);
393     } else {
394       DEBUG(dbgs() << "Found partial copy" << *MI <<"\n");
395       Outs.push_back(MI);
396     }
397   }
398}
399
400// Return the DPR virtual registers that are read by this machine instruction
401// (if any).
402SmallVector<unsigned, 8> A15SDOptimizer::getReadDPRs(MachineInstr *MI) {
403  if (MI->isCopyLike() || MI->isInsertSubreg() || MI->isRegSequence() ||
404      MI->isKill())
405    return SmallVector<unsigned, 8>();
406
407  SmallVector<unsigned, 8> Defs;
408  for (unsigned i = 0; i < MI->getNumOperands(); ++i) {
409    MachineOperand &MO = MI->getOperand(i);
410
411    if (!MO.isReg() || !MO.isUse())
412      continue;
413    if (!usesRegClass(MO, &ARM::DPRRegClass) &&
414        !usesRegClass(MO, &ARM::QPRRegClass) &&
415        !usesRegClass(MO, &ARM::DPairRegClass)) // Treat DPair as QPR
416      continue;
417
418    Defs.push_back(MO.getReg());
419  }
420  return Defs;
421}
422
423// Creates a DPR register from an SPR one by using a VDUP.
424unsigned
425A15SDOptimizer::createDupLane(MachineBasicBlock &MBB,
426                              MachineBasicBlock::iterator InsertBefore,
427                              DebugLoc DL,
428                              unsigned Reg, unsigned Lane, bool QPR) {
429  unsigned Out = MRI->createVirtualRegister(QPR ? &ARM::QPRRegClass :
430                                                  &ARM::DPRRegClass);
431  AddDefaultPred(BuildMI(MBB,
432                         InsertBefore,
433                         DL,
434                         TII->get(QPR ? ARM::VDUPLN32q : ARM::VDUPLN32d),
435                         Out)
436                   .addReg(Reg)
437                   .addImm(Lane));
438
439  return Out;
440}
441
442// Creates a SPR register from a DPR by copying the value in lane 0.
443unsigned
444A15SDOptimizer::createExtractSubreg(MachineBasicBlock &MBB,
445                                    MachineBasicBlock::iterator InsertBefore,
446                                    DebugLoc DL,
447                                    unsigned DReg, unsigned Lane,
448                                    const TargetRegisterClass *TRC) {
449  unsigned Out = MRI->createVirtualRegister(TRC);
450  BuildMI(MBB,
451          InsertBefore,
452          DL,
453          TII->get(TargetOpcode::COPY), Out)
454    .addReg(DReg, 0, Lane);
455
456  return Out;
457}
458
459// Takes two SPR registers and creates a DPR by using a REG_SEQUENCE.
460unsigned
461A15SDOptimizer::createRegSequence(MachineBasicBlock &MBB,
462                                  MachineBasicBlock::iterator InsertBefore,
463                                  DebugLoc DL,
464                                  unsigned Reg1, unsigned Reg2) {
465  unsigned Out = MRI->createVirtualRegister(&ARM::QPRRegClass);
466  BuildMI(MBB,
467          InsertBefore,
468          DL,
469          TII->get(TargetOpcode::REG_SEQUENCE), Out)
470    .addReg(Reg1)
471    .addImm(ARM::dsub_0)
472    .addReg(Reg2)
473    .addImm(ARM::dsub_1);
474  return Out;
475}
476
477// Takes two DPR registers that have previously been VDUPed (Ssub0 and Ssub1)
478// and merges them into one DPR register.
479unsigned
480A15SDOptimizer::createVExt(MachineBasicBlock &MBB,
481                           MachineBasicBlock::iterator InsertBefore,
482                           DebugLoc DL,
483                           unsigned Ssub0, unsigned Ssub1) {
484  unsigned Out = MRI->createVirtualRegister(&ARM::DPRRegClass);
485  AddDefaultPred(BuildMI(MBB,
486                         InsertBefore,
487                         DL,
488                         TII->get(ARM::VEXTd32), Out)
489                   .addReg(Ssub0)
490                   .addReg(Ssub1)
491                   .addImm(1));
492  return Out;
493}
494
495unsigned
496A15SDOptimizer::createInsertSubreg(MachineBasicBlock &MBB,
497                                   MachineBasicBlock::iterator InsertBefore,
498                                   DebugLoc DL, unsigned DReg, unsigned Lane,
499                                   unsigned ToInsert) {
500  unsigned Out = MRI->createVirtualRegister(&ARM::DPR_VFP2RegClass);
501  BuildMI(MBB,
502          InsertBefore,
503          DL,
504          TII->get(TargetOpcode::INSERT_SUBREG), Out)
505    .addReg(DReg)
506    .addReg(ToInsert)
507    .addImm(Lane);
508
509  return Out;
510}
511
512unsigned
513A15SDOptimizer::createImplicitDef(MachineBasicBlock &MBB,
514                                  MachineBasicBlock::iterator InsertBefore,
515                                  DebugLoc DL) {
516  unsigned Out = MRI->createVirtualRegister(&ARM::DPRRegClass);
517  BuildMI(MBB,
518          InsertBefore,
519          DL,
520          TII->get(TargetOpcode::IMPLICIT_DEF), Out);
521  return Out;
522}
523
524// This function inserts instructions in order to optimize interactions between
525// SPR registers and DPR/QPR registers. It does so by performing VDUPs on all
526// lanes, and the using VEXT instructions to recompose the result.
527unsigned
528A15SDOptimizer::optimizeAllLanesPattern(MachineInstr *MI, unsigned Reg) {
529  MachineBasicBlock::iterator InsertPt(MI);
530  DebugLoc DL = MI->getDebugLoc();
531  MachineBasicBlock &MBB = *MI->getParent();
532  InsertPt++;
533  unsigned Out;
534
535  // DPair has the same length as QPR and also has two DPRs as subreg.
536  // Treat DPair as QPR.
537  if (MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::QPRRegClass) ||
538      MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::DPairRegClass)) {
539    unsigned DSub0 = createExtractSubreg(MBB, InsertPt, DL, Reg,
540                                         ARM::dsub_0, &ARM::DPRRegClass);
541    unsigned DSub1 = createExtractSubreg(MBB, InsertPt, DL, Reg,
542                                         ARM::dsub_1, &ARM::DPRRegClass);
543
544    unsigned Out1 = createDupLane(MBB, InsertPt, DL, DSub0, 0);
545    unsigned Out2 = createDupLane(MBB, InsertPt, DL, DSub0, 1);
546    Out = createVExt(MBB, InsertPt, DL, Out1, Out2);
547
548    unsigned Out3 = createDupLane(MBB, InsertPt, DL, DSub1, 0);
549    unsigned Out4 = createDupLane(MBB, InsertPt, DL, DSub1, 1);
550    Out2 = createVExt(MBB, InsertPt, DL, Out3, Out4);
551
552    Out = createRegSequence(MBB, InsertPt, DL, Out, Out2);
553
554  } else if (MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::DPRRegClass)) {
555    unsigned Out1 = createDupLane(MBB, InsertPt, DL, Reg, 0);
556    unsigned Out2 = createDupLane(MBB, InsertPt, DL, Reg, 1);
557    Out = createVExt(MBB, InsertPt, DL, Out1, Out2);
558
559  } else {
560    assert(MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::SPRRegClass) &&
561           "Found unexpected regclass!");
562
563    unsigned PrefLane = getPrefSPRLane(Reg);
564    unsigned Lane;
565    switch (PrefLane) {
566      case ARM::ssub_0: Lane = 0; break;
567      case ARM::ssub_1: Lane = 1; break;
568      default: llvm_unreachable("Unknown preferred lane!");
569    }
570
571    // Treat DPair as QPR
572    bool UsesQPR = usesRegClass(MI->getOperand(0), &ARM::QPRRegClass) ||
573                   usesRegClass(MI->getOperand(0), &ARM::DPairRegClass);
574
575    Out = createImplicitDef(MBB, InsertPt, DL);
576    Out = createInsertSubreg(MBB, InsertPt, DL, Out, PrefLane, Reg);
577    Out = createDupLane(MBB, InsertPt, DL, Out, Lane, UsesQPR);
578    eraseInstrWithNoUses(MI);
579  }
580  return Out;
581}
582
583bool A15SDOptimizer::runOnInstruction(MachineInstr *MI) {
584  // We look for instructions that write S registers that are then read as
585  // D/Q registers. These can only be caused by COPY, INSERT_SUBREG and
586  // REG_SEQUENCE pseudos that insert an SPR value into a DPR register or
587  // merge two SPR values to form a DPR register.  In order avoid false
588  // positives we make sure that there is an SPR producer so we look past
589  // COPY and PHI nodes to find it.
590  //
591  // The best code pattern for when an SPR producer is going to be used by a
592  // DPR or QPR consumer depends on whether the other lanes of the
593  // corresponding DPR/QPR are currently defined.
594  //
595  // We can handle these efficiently, depending on the type of
596  // pseudo-instruction that is producing the pattern
597  //
598  //   * COPY:          * VDUP all lanes and merge the results together
599  //                      using VEXTs.
600  //
601  //   * INSERT_SUBREG: * If the SPR value was originally in another DPR/QPR
602  //                      lane, and the other lane(s) of the DPR/QPR register
603  //                      that we are inserting in are undefined, use the
604  //                      original DPR/QPR value.
605  //                    * Otherwise, fall back on the same stategy as COPY.
606  //
607  //   * REG_SEQUENCE:  * If all except one of the input operands are
608  //                      IMPLICIT_DEFs, insert the VDUP pattern for just the
609  //                      defined input operand
610  //                    * Otherwise, fall back on the same stategy as COPY.
611  //
612
613  // First, get all the reads of D-registers done by this instruction.
614  SmallVector<unsigned, 8> Defs = getReadDPRs(MI);
615  bool Modified = false;
616
617  for (SmallVectorImpl<unsigned>::iterator I = Defs.begin(), E = Defs.end();
618     I != E; ++I) {
619    // Follow the def-use chain for this DPR through COPYs, and also through
620    // PHIs (which are essentially multi-way COPYs). It is because of PHIs that
621    // we can end up with multiple defs of this DPR.
622
623    SmallVector<MachineInstr *, 8> DefSrcs;
624    if (!TRI->isVirtualRegister(*I))
625      continue;
626    MachineInstr *Def = MRI->getVRegDef(*I);
627    if (!Def)
628      continue;
629
630    elideCopiesAndPHIs(Def, DefSrcs);
631
632    for (SmallVectorImpl<MachineInstr *>::iterator II = DefSrcs.begin(),
633      EE = DefSrcs.end(); II != EE; ++II) {
634      MachineInstr *MI = *II;
635
636      // If we've already analyzed and replaced this operand, don't do
637      // anything.
638      if (Replacements.find(MI) != Replacements.end())
639        continue;
640
641      // Now, work out if the instruction causes a SPR->DPR dependency.
642      if (!hasPartialWrite(MI))
643        continue;
644
645      // Collect all the uses of this MI's DPR def for updating later.
646      SmallVector<MachineOperand*, 8> Uses;
647      unsigned DPRDefReg = MI->getOperand(0).getReg();
648      for (MachineRegisterInfo::use_iterator I = MRI->use_begin(DPRDefReg),
649             E = MRI->use_end(); I != E; ++I)
650        Uses.push_back(&*I);
651
652      // We can optimize this.
653      unsigned NewReg = optimizeSDPattern(MI);
654
655      if (NewReg != 0) {
656        Modified = true;
657        for (SmallVectorImpl<MachineOperand *>::const_iterator I = Uses.begin(),
658               E = Uses.end(); I != E; ++I) {
659          // Make sure to constrain the register class of the new register to
660          // match what we're replacing. Otherwise we can optimize a DPR_VFP2
661          // reference into a plain DPR, and that will end poorly. NewReg is
662          // always virtual here, so there will always be a matching subclass
663          // to find.
664          MRI->constrainRegClass(NewReg, MRI->getRegClass((*I)->getReg()));
665
666          DEBUG(dbgs() << "Replacing operand "
667                       << **I << " with "
668                       << PrintReg(NewReg) << "\n");
669          (*I)->substVirtReg(NewReg, 0, *TRI);
670        }
671      }
672      Replacements[MI] = NewReg;
673    }
674  }
675  return Modified;
676}
677
678bool A15SDOptimizer::runOnMachineFunction(MachineFunction &Fn) {
679  TII = static_cast<const ARMBaseInstrInfo*>(Fn.getTarget().getInstrInfo());
680  TRI = Fn.getTarget().getRegisterInfo();
681  MRI = &Fn.getRegInfo();
682  bool Modified = false;
683
684  DEBUG(dbgs() << "Running on function " << Fn.getName()<< "\n");
685
686  DeadInstr.clear();
687  Replacements.clear();
688
689  for (MachineFunction::iterator MFI = Fn.begin(), E = Fn.end(); MFI != E;
690       ++MFI) {
691
692    for (MachineBasicBlock::iterator MI = MFI->begin(), ME = MFI->end();
693      MI != ME;) {
694      Modified |= runOnInstruction(MI++);
695    }
696
697  }
698
699  for (std::set<MachineInstr *>::iterator I = DeadInstr.begin(),
700                                            E = DeadInstr.end();
701                                            I != E; ++I) {
702    (*I)->eraseFromParent();
703  }
704
705  return Modified;
706}
707
708FunctionPass *llvm::createA15SDOptimizerPass() {
709  return new A15SDOptimizer();
710}
711