ARM.td revision 20bd5296cec8d8d597ab9db2aca7346a88e580c8 
1//===-- ARM.td - Describe the ARM Target Machine -----------*- tablegen -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10//
11//===----------------------------------------------------------------------===//
12
13//===----------------------------------------------------------------------===//
14// Target-independent interfaces which we are implementing
15//===----------------------------------------------------------------------===//
16
17include "llvm/Target/Target.td"
18
19//===----------------------------------------------------------------------===//
20// ARM Subtarget state.
21//
22
23def ModeThumb  : SubtargetFeature<"thumb-mode", "InThumbMode", "true",
24                                  "Thumb mode">;
25
26//===----------------------------------------------------------------------===//
27// ARM Subtarget features.
28//
29
30def FeatureVFP2 : SubtargetFeature<"vfp2", "HasVFPv2", "true",
31                                   "Enable VFP2 instructions">;
32def FeatureVFP3 : SubtargetFeature<"vfp3", "HasVFPv3", "true",
33                                   "Enable VFP3 instructions",
34                                   [FeatureVFP2]>;
35def FeatureVFP4 : SubtargetFeature<"vfp4", "HasVFPv4", "true",
36                                   "Enable VFP4 instructions",
37                                   [FeatureVFP3]>;
38def FeatureNEON : SubtargetFeature<"neon", "HasNEON", "true",
39                                   "Enable NEON instructions",
40                                   [FeatureVFP3]>;
41def FeatureNEONVFP4 : SubtargetFeature<"neon-vfpv4", "HasNEONVFPv4", "true",
42                                       "Enable NEON-VFP4 instructions",
43                                       [FeatureVFP4, FeatureNEON]>;
44def FeatureThumb2 : SubtargetFeature<"thumb2", "HasThumb2", "true",
45                                     "Enable Thumb2 instructions">;
46def FeatureNoARM  : SubtargetFeature<"noarm", "NoARM", "true",
47                                     "Does not support ARM mode execution">;
48def FeatureFP16   : SubtargetFeature<"fp16", "HasFP16", "true",
49                                     "Enable half-precision floating point">;
50def FeatureD16    : SubtargetFeature<"d16", "HasD16", "true",
51                                     "Restrict VFP3 to 16 double registers">;
52def FeatureHWDiv  : SubtargetFeature<"hwdiv", "HasHardwareDivide", "true",
53                                     "Enable divide instructions">;
54def FeatureT2XtPk : SubtargetFeature<"t2xtpk", "HasT2ExtractPack", "true",
55                                 "Enable Thumb2 extract and pack instructions">;
56def FeatureDB     : SubtargetFeature<"db", "HasDataBarrier", "true",
57                                   "Has data barrier (dmb / dsb) instructions">;
58def FeatureSlowFPBrcc : SubtargetFeature<"slow-fp-brcc", "SlowFPBrcc", "true",
59                                         "FP compare + branch is slow">;
60def FeatureVFPOnlySP : SubtargetFeature<"fp-only-sp", "FPOnlySP", "true",
61                          "Floating point unit supports single precision only">;
62
63// Some processors have FP multiply-accumulate instructions that don't
64// play nicely with other VFP / NEON instructions, and it's generally better
65// to just not use them.
66def FeatureHasSlowFPVMLx : SubtargetFeature<"slowfpvmlx", "SlowFPVMLx", "true",
67                                         "Disable VFP / NEON MAC instructions">;
68
69// Cortex-A8 / A9 Advanced SIMD has multiplier accumulator forwarding.
70def FeatureVMLxForwarding : SubtargetFeature<"vmlx-forwarding",
71                                       "HasVMLxForwarding", "true",
72                                       "Has multiplier accumulator forwarding">;
73
74// Some processors benefit from using NEON instructions for scalar
75// single-precision FP operations.
76def FeatureNEONForFP : SubtargetFeature<"neonfp", "UseNEONForSinglePrecisionFP",
77                                        "true",
78                                        "Use NEON for single precision FP">;
79
80// Disable 32-bit to 16-bit narrowing for experimentation.
81def FeaturePref32BitThumb : SubtargetFeature<"32bit", "Pref32BitThumb", "true",
82                                             "Prefer 32-bit Thumb instrs">;
83
84/// Some instructions update CPSR partially, which can add false dependency for
85/// out-of-order implementation, e.g. Cortex-A9, unless each individual bit is
86/// mapped to a separate physical register. Avoid partial CPSR update for these
87/// processors.
88def FeatureAvoidPartialCPSR : SubtargetFeature<"avoid-partial-cpsr",
89                                               "AvoidCPSRPartialUpdate", "true",
90                                 "Avoid CPSR partial update for OOO execution">;
91
92/// Some M architectures don't have the DSP extension (v7E-M vs. v7M)
93def FeatureDSPThumb2 : SubtargetFeature<"t2dsp", "Thumb2DSP", "true",
94                                 "Supports v7 DSP instructions in Thumb2">;
95
96// Multiprocessing extension.
97def FeatureMP : SubtargetFeature<"mp", "HasMPExtension", "true",
98                                 "Supports Multiprocessing extension">;
99
100// M-series ISA?
101def FeatureMClass : SubtargetFeature<"mclass", "IsMClass", "true",
102                                     "Is microcontroller profile ('M' series)">;
103
104// ARM ISAs.
105def HasV4TOps   : SubtargetFeature<"v4t", "HasV4TOps", "true",
106                                   "Support ARM v4T instructions">;
107def HasV5TOps   : SubtargetFeature<"v5t", "HasV5TOps", "true",
108                                   "Support ARM v5T instructions",
109                                   [HasV4TOps]>;
110def HasV5TEOps  : SubtargetFeature<"v5te", "HasV5TEOps", "true",
111                             "Support ARM v5TE, v5TEj, and v5TExp instructions",
112                                   [HasV5TOps]>;
113def HasV6Ops    : SubtargetFeature<"v6", "HasV6Ops", "true",
114                                   "Support ARM v6 instructions",
115                                   [HasV5TEOps]>;
116def HasV6T2Ops  : SubtargetFeature<"v6t2", "HasV6T2Ops", "true",
117                                   "Support ARM v6t2 instructions",
118                                   [HasV6Ops, FeatureThumb2]>;
119def HasV7Ops    : SubtargetFeature<"v7", "HasV7Ops", "true",
120                                   "Support ARM v7 instructions",
121                                   [HasV6T2Ops]>;
122
123//===----------------------------------------------------------------------===//
124// ARM Processors supported.
125//
126
127include "ARMSchedule.td"
128
129// ARM processor families.
130def ProcA8      : SubtargetFeature<"a8", "ARMProcFamily", "CortexA8",
131                                   "Cortex-A8 ARM processors",
132                                   [FeatureSlowFPBrcc, FeatureNEONForFP,
133                                    FeatureHasSlowFPVMLx, FeatureVMLxForwarding,
134                                    FeatureT2XtPk]>;
135def ProcA9      : SubtargetFeature<"a9", "ARMProcFamily", "CortexA9",
136                                   "Cortex-A9 ARM processors",
137                                   [FeatureVMLxForwarding,
138                                    FeatureT2XtPk, FeatureFP16,
139                                    FeatureAvoidPartialCPSR]>;
140
141class ProcNoItin<string Name, list<SubtargetFeature> Features>
142 : Processor<Name, GenericItineraries, Features>;
143
144// V4 Processors.
145def : ProcNoItin<"generic",         []>;
146def : ProcNoItin<"arm8",            []>;
147def : ProcNoItin<"arm810",          []>;
148def : ProcNoItin<"strongarm",       []>;
149def : ProcNoItin<"strongarm110",    []>;
150def : ProcNoItin<"strongarm1100",   []>;
151def : ProcNoItin<"strongarm1110",   []>;
152
153// V4T Processors.
154def : ProcNoItin<"arm7tdmi",        [HasV4TOps]>;
155def : ProcNoItin<"arm7tdmi-s",      [HasV4TOps]>;
156def : ProcNoItin<"arm710t",         [HasV4TOps]>;
157def : ProcNoItin<"arm720t",         [HasV4TOps]>;
158def : ProcNoItin<"arm9",            [HasV4TOps]>;
159def : ProcNoItin<"arm9tdmi",        [HasV4TOps]>;
160def : ProcNoItin<"arm920",          [HasV4TOps]>;
161def : ProcNoItin<"arm920t",         [HasV4TOps]>;
162def : ProcNoItin<"arm922t",         [HasV4TOps]>;
163def : ProcNoItin<"arm940t",         [HasV4TOps]>;
164def : ProcNoItin<"ep9312",          [HasV4TOps]>;
165
166// V5T Processors.
167def : ProcNoItin<"arm10tdmi",       [HasV5TOps]>;
168def : ProcNoItin<"arm1020t",        [HasV5TOps]>;
169
170// V5TE Processors.
171def : ProcNoItin<"arm9e",           [HasV5TEOps]>;
172def : ProcNoItin<"arm926ej-s",      [HasV5TEOps]>;
173def : ProcNoItin<"arm946e-s",       [HasV5TEOps]>;
174def : ProcNoItin<"arm966e-s",       [HasV5TEOps]>;
175def : ProcNoItin<"arm968e-s",       [HasV5TEOps]>;
176def : ProcNoItin<"arm10e",          [HasV5TEOps]>;
177def : ProcNoItin<"arm1020e",        [HasV5TEOps]>;
178def : ProcNoItin<"arm1022e",        [HasV5TEOps]>;
179def : ProcNoItin<"xscale",          [HasV5TEOps]>;
180def : ProcNoItin<"iwmmxt",          [HasV5TEOps]>;
181
182// V6 Processors.
183def : Processor<"arm1136j-s",       ARMV6Itineraries, [HasV6Ops]>;
184def : Processor<"arm1136jf-s",      ARMV6Itineraries, [HasV6Ops, FeatureVFP2,
185                                                       FeatureHasSlowFPVMLx]>;
186def : Processor<"arm1176jz-s",      ARMV6Itineraries, [HasV6Ops]>;
187def : Processor<"arm1176jzf-s",     ARMV6Itineraries, [HasV6Ops, FeatureVFP2,
188                                                       FeatureHasSlowFPVMLx]>;
189def : Processor<"mpcorenovfp",      ARMV6Itineraries, [HasV6Ops]>;
190def : Processor<"mpcore",           ARMV6Itineraries, [HasV6Ops, FeatureVFP2,
191                                                       FeatureHasSlowFPVMLx]>;
192
193// V6M Processors.
194def : Processor<"cortex-m0",        ARMV6Itineraries, [HasV6Ops, FeatureNoARM,
195                                                       FeatureDB, FeatureMClass]>;
196
197// V6T2 Processors.
198def : Processor<"arm1156t2-s",      ARMV6Itineraries, [HasV6T2Ops,
199                                                       FeatureDSPThumb2]>;
200def : Processor<"arm1156t2f-s",     ARMV6Itineraries, [HasV6T2Ops, FeatureVFP2,
201                                                       FeatureHasSlowFPVMLx,
202                                                       FeatureDSPThumb2]>;
203
204// V7a Processors.
205def : Processor<"cortex-a8",        CortexA8Itineraries,
206                                    [ProcA8, HasV7Ops, FeatureNEON, FeatureDB,
207                                     FeatureDSPThumb2]>;
208def : Processor<"cortex-a9",        CortexA9Itineraries,
209                                    [ProcA9, HasV7Ops, FeatureNEON, FeatureDB,
210                                     FeatureDSPThumb2]>;
211def : Processor<"cortex-a9-mp",     CortexA9Itineraries,
212                                    [ProcA9, HasV7Ops, FeatureNEON, FeatureDB,
213                                     FeatureDSPThumb2, FeatureMP]>;
214
215// V7M Processors.
216def : ProcNoItin<"cortex-m3",       [HasV7Ops,
217                                     FeatureThumb2, FeatureNoARM, FeatureDB,
218                                     FeatureHWDiv, FeatureMClass]>;
219
220// V7EM Processors.
221def : ProcNoItin<"cortex-m4",       [HasV7Ops,
222                                     FeatureThumb2, FeatureNoARM, FeatureDB,
223                                     FeatureHWDiv, FeatureDSPThumb2,
224                                     FeatureT2XtPk, FeatureVFP2,
225                                     FeatureVFPOnlySP, FeatureMClass]>;
226
227//===----------------------------------------------------------------------===//
228// Register File Description
229//===----------------------------------------------------------------------===//
230
231include "ARMRegisterInfo.td"
232
233include "ARMCallingConv.td"
234
235//===----------------------------------------------------------------------===//
236// Instruction Descriptions
237//===----------------------------------------------------------------------===//
238
239include "ARMInstrInfo.td"
240
241def ARMInstrInfo : InstrInfo;
242
243
244//===----------------------------------------------------------------------===//
245// Assembly printer
246//===----------------------------------------------------------------------===//
247// ARM Uses the MC printer for asm output, so make sure the TableGen
248// AsmWriter bits get associated with the correct class.
249def ARMAsmWriter : AsmWriter {
250  string AsmWriterClassName  = "InstPrinter";
251  bit isMCAsmWriter = 1;
252}
253
254//===----------------------------------------------------------------------===//
255// Declare the target which we are implementing
256//===----------------------------------------------------------------------===//
257
258def ARM : Target {
259  // Pull in Instruction Info:
260  let InstructionSet = ARMInstrInfo;
261
262  let AssemblyWriters = [ARMAsmWriter];
263}
264