ARM.td revision b1dc393bd56365ad8fabb51f22c2f3ace707c39a 
1//===- ARM.td - Describe the ARM Target Machine -----------------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10//
11//===----------------------------------------------------------------------===//
12
13//===----------------------------------------------------------------------===//
14// Target-independent interfaces which we are implementing
15//===----------------------------------------------------------------------===//
16
17include "llvm/Target/Target.td"
18
19//===----------------------------------------------------------------------===//
20// ARM Subtarget features.
21//
22
23def ArchV4T     : SubtargetFeature<"v4t", "ARMArchVersion", "V4T",
24                                   "ARM v4T">;
25def ArchV5T     : SubtargetFeature<"v5t", "ARMArchVersion", "V5T",
26                                   "ARM v5T">;
27def ArchV5TE    : SubtargetFeature<"v5te", "ARMArchVersion", "V5TE",
28                                   "ARM v5TE, v5TEj, v5TExp">;
29def ArchV6      : SubtargetFeature<"v6", "ARMArchVersion", "V6",
30                                   "ARM v6">;
31def ArchV6T2    : SubtargetFeature<"v6t2", "ARMArchVersion", "V6T2",
32                                   "ARM v6t2">;
33def ArchV7A     : SubtargetFeature<"v7a", "ARMArchVersion", "V7A",
34                                   "ARM v7A">;
35def ArchV7M     : SubtargetFeature<"v7m", "ARMArchVersion", "V7M",
36                                   "ARM v7M">;
37def FeatureVFP2 : SubtargetFeature<"vfp2", "ARMFPUType", "VFPv2",
38                                   "Enable VFP2 instructions">;
39def FeatureVFP3 : SubtargetFeature<"vfp3", "ARMFPUType", "VFPv3",
40                                   "Enable VFP3 instructions">;
41def FeatureNEON : SubtargetFeature<"neon", "ARMFPUType", "NEON",
42                                   "Enable NEON instructions">;
43def FeatureThumb2 : SubtargetFeature<"thumb2", "ThumbMode", "Thumb2",
44                                     "Enable Thumb2 instructions">;
45def FeatureFP16   : SubtargetFeature<"fp16", "HasFP16", "true",
46                                     "Enable half-precision floating point">;
47
48// Some processors have multiply-accumulate instructions that don't
49// play nicely with other VFP instructions, and it's generally better
50// to just not use them.
51// FIXME: Currently, this is only flagged for Cortex-A8. It may be true for
52// others as well. We should do more benchmarking and confirm one way or
53// the other.
54def FeatureHasSlowVMLx   : SubtargetFeature<"vmlx", "SlowVMLx", "true",
55                                            "Disable VFP MAC instructions">;
56// Some processors benefit from using NEON instructions for scalar
57// single-precision FP operations.
58def FeatureNEONForFP : SubtargetFeature<"neonfp", "UseNEONForSinglePrecisionFP",
59                                        "true",
60                                        "Use NEON for single precision FP">;
61
62
63//===----------------------------------------------------------------------===//
64// ARM Processors supported.
65//
66
67include "ARMSchedule.td"
68
69class ProcNoItin<string Name, list<SubtargetFeature> Features>
70 : Processor<Name, GenericItineraries, Features>;
71
72// V4 Processors.
73def : ProcNoItin<"generic",         []>;
74def : ProcNoItin<"arm8",            []>;
75def : ProcNoItin<"arm810",          []>;
76def : ProcNoItin<"strongarm",       []>;
77def : ProcNoItin<"strongarm110",    []>;
78def : ProcNoItin<"strongarm1100",   []>;
79def : ProcNoItin<"strongarm1110",   []>;
80
81// V4T Processors.
82def : ProcNoItin<"arm7tdmi",        [ArchV4T]>;
83def : ProcNoItin<"arm7tdmi-s",      [ArchV4T]>;
84def : ProcNoItin<"arm710t",         [ArchV4T]>;
85def : ProcNoItin<"arm720t",         [ArchV4T]>;
86def : ProcNoItin<"arm9",            [ArchV4T]>;
87def : ProcNoItin<"arm9tdmi",        [ArchV4T]>;
88def : ProcNoItin<"arm920",          [ArchV4T]>;
89def : ProcNoItin<"arm920t",         [ArchV4T]>;
90def : ProcNoItin<"arm922t",         [ArchV4T]>;
91def : ProcNoItin<"arm940t",         [ArchV4T]>;
92def : ProcNoItin<"ep9312",          [ArchV4T]>;
93
94// V5T Processors.
95def : ProcNoItin<"arm10tdmi",       [ArchV5T]>;
96def : ProcNoItin<"arm1020t",        [ArchV5T]>;
97
98// V5TE Processors.
99def : ProcNoItin<"arm9e",           [ArchV5TE]>;
100def : ProcNoItin<"arm926ej-s",      [ArchV5TE]>;
101def : ProcNoItin<"arm946e-s",       [ArchV5TE]>;
102def : ProcNoItin<"arm966e-s",       [ArchV5TE]>;
103def : ProcNoItin<"arm968e-s",       [ArchV5TE]>;
104def : ProcNoItin<"arm10e",          [ArchV5TE]>;
105def : ProcNoItin<"arm1020e",        [ArchV5TE]>;
106def : ProcNoItin<"arm1022e",        [ArchV5TE]>;
107def : ProcNoItin<"xscale",          [ArchV5TE]>;
108def : ProcNoItin<"iwmmxt",          [ArchV5TE]>;
109
110// V6 Processors.
111def : Processor<"arm1136j-s",       ARMV6Itineraries, [ArchV6]>;
112def : Processor<"arm1136jf-s",      ARMV6Itineraries, [ArchV6, FeatureVFP2,
113                                                       FeatureHasSlowVMLx]>;
114def : Processor<"arm1176jz-s",      ARMV6Itineraries, [ArchV6]>;
115def : Processor<"arm1176jzf-s",     ARMV6Itineraries, [ArchV6, FeatureVFP2]>;
116def : Processor<"mpcorenovfp",      ARMV6Itineraries, [ArchV6]>;
117def : Processor<"mpcore",           ARMV6Itineraries, [ArchV6, FeatureVFP2]>;
118
119// V6T2 Processors.
120def : Processor<"arm1156t2-s",     ARMV6Itineraries,
121                 [ArchV6T2, FeatureThumb2]>;
122def : Processor<"arm1156t2f-s",    ARMV6Itineraries,
123                 [ArchV6T2, FeatureThumb2, FeatureVFP2]>;
124
125// V7 Processors.
126def : Processor<"cortex-a8",        CortexA8Itineraries,
127                [ArchV7A, FeatureThumb2, FeatureNEON, FeatureHasSlowVMLx,
128                 FeatureNEONForFP]>;
129def : Processor<"cortex-a9",        CortexA9Itineraries,
130                [ArchV7A, FeatureThumb2, FeatureNEON]>;
131def : ProcNoItin<"cortex-m3",       [ArchV7M, FeatureThumb2]>;
132
133//===----------------------------------------------------------------------===//
134// Register File Description
135//===----------------------------------------------------------------------===//
136
137include "ARMRegisterInfo.td"
138
139include "ARMCallingConv.td"
140
141//===----------------------------------------------------------------------===//
142// Instruction Descriptions
143//===----------------------------------------------------------------------===//
144
145include "ARMInstrInfo.td"
146
147def ARMInstrInfo : InstrInfo;
148
149//===----------------------------------------------------------------------===//
150// Declare the target which we are implementing
151//===----------------------------------------------------------------------===//
152
153def ARM : Target {
154  // Pull in Instruction Info:
155  let InstructionSet = ARMInstrInfo;
156}
157