ARMAsmPrinter.cpp revision ec52aaa12f57896fc806e849fa21a61603050ac4 
1//===-- ARMAsmPrinter.cpp - Print machine code to an ARM .s file ----------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains a printer that converts from our internal representation
11// of machine-dependent LLVM code to GAS-format ARM assembly language.
12//
13//===----------------------------------------------------------------------===//
14
15#define DEBUG_TYPE "asm-printer"
16#include "ARM.h"
17#include "ARMAsmPrinter.h"
18#include "ARMBuildAttrs.h"
19#include "ARMBaseRegisterInfo.h"
20#include "ARMConstantPoolValue.h"
21#include "ARMMachineFunctionInfo.h"
22#include "ARMTargetMachine.h"
23#include "ARMTargetObjectFile.h"
24#include "InstPrinter/ARMInstPrinter.h"
25#include "MCTargetDesc/ARMAddressingModes.h"
26#include "MCTargetDesc/ARMMCExpr.h"
27#include "llvm/Analysis/DebugInfo.h"
28#include "llvm/Constants.h"
29#include "llvm/Module.h"
30#include "llvm/Type.h"
31#include "llvm/Assembly/Writer.h"
32#include "llvm/CodeGen/MachineModuleInfoImpls.h"
33#include "llvm/CodeGen/MachineFunctionPass.h"
34#include "llvm/CodeGen/MachineJumpTableInfo.h"
35#include "llvm/MC/MCAsmInfo.h"
36#include "llvm/MC/MCAssembler.h"
37#include "llvm/MC/MCContext.h"
38#include "llvm/MC/MCExpr.h"
39#include "llvm/MC/MCInst.h"
40#include "llvm/MC/MCSectionMachO.h"
41#include "llvm/MC/MCObjectStreamer.h"
42#include "llvm/MC/MCStreamer.h"
43#include "llvm/MC/MCSymbol.h"
44#include "llvm/Target/Mangler.h"
45#include "llvm/Target/TargetData.h"
46#include "llvm/Target/TargetMachine.h"
47#include "llvm/Target/TargetOptions.h"
48#include "llvm/ADT/SmallPtrSet.h"
49#include "llvm/ADT/SmallString.h"
50#include "llvm/Support/CommandLine.h"
51#include "llvm/Support/Debug.h"
52#include "llvm/Support/ErrorHandling.h"
53#include "llvm/Support/TargetRegistry.h"
54#include "llvm/Support/raw_ostream.h"
55#include <cctype>
56using namespace llvm;
57
58namespace {
59
60  // Per section and per symbol attributes are not supported.
61  // To implement them we would need the ability to delay this emission
62  // until the assembly file is fully parsed/generated as only then do we
63  // know the symbol and section numbers.
64  class AttributeEmitter {
65  public:
66    virtual void MaybeSwitchVendor(StringRef Vendor) = 0;
67    virtual void EmitAttribute(unsigned Attribute, unsigned Value) = 0;
68    virtual void EmitTextAttribute(unsigned Attribute, StringRef String) = 0;
69    virtual void Finish() = 0;
70    virtual ~AttributeEmitter() {}
71  };
72
73  class AsmAttributeEmitter : public AttributeEmitter {
74    MCStreamer &Streamer;
75
76  public:
77    AsmAttributeEmitter(MCStreamer &Streamer_) : Streamer(Streamer_) {}
78    void MaybeSwitchVendor(StringRef Vendor) { }
79
80    void EmitAttribute(unsigned Attribute, unsigned Value) {
81      Streamer.EmitRawText("\t.eabi_attribute " +
82                           Twine(Attribute) + ", " + Twine(Value));
83    }
84
85    void EmitTextAttribute(unsigned Attribute, StringRef String) {
86      switch (Attribute) {
87      default: llvm_unreachable("Unsupported Text attribute in ASM Mode");
88      case ARMBuildAttrs::CPU_name:
89        Streamer.EmitRawText(StringRef("\t.cpu ") + String.lower());
90        break;
91      /* GAS requires .fpu to be emitted regardless of EABI attribute */
92      case ARMBuildAttrs::Advanced_SIMD_arch:
93      case ARMBuildAttrs::VFP_arch:
94        Streamer.EmitRawText(StringRef("\t.fpu ") + String.lower());
95        break;
96      }
97    }
98    void Finish() { }
99  };
100
101  class ObjectAttributeEmitter : public AttributeEmitter {
102    // This structure holds all attributes, accounting for
103    // their string/numeric value, so we can later emmit them
104    // in declaration order, keeping all in the same vector
105    struct AttributeItemType {
106      enum {
107        HiddenAttribute = 0,
108        NumericAttribute,
109        TextAttribute
110      } Type;
111      unsigned Tag;
112      unsigned IntValue;
113      StringRef StringValue;
114    } AttributeItem;
115
116    MCObjectStreamer &Streamer;
117    StringRef CurrentVendor;
118    SmallVector<AttributeItemType, 64> Contents;
119
120    // Account for the ULEB/String size of each item,
121    // not just the number of items
122    size_t ContentsSize;
123    // FIXME: this should be in a more generic place, but
124    // getULEBSize() is in MCAsmInfo and will be moved to MCDwarf
125    size_t getULEBSize(int Value) {
126      size_t Size = 0;
127      do {
128        Value >>= 7;
129        Size += sizeof(int8_t); // Is this really necessary?
130      } while (Value);
131      return Size;
132    }
133
134  public:
135    ObjectAttributeEmitter(MCObjectStreamer &Streamer_) :
136      Streamer(Streamer_), CurrentVendor(""), ContentsSize(0) { }
137
138    void MaybeSwitchVendor(StringRef Vendor) {
139      assert(!Vendor.empty() && "Vendor cannot be empty.");
140
141      if (CurrentVendor.empty())
142        CurrentVendor = Vendor;
143      else if (CurrentVendor == Vendor)
144        return;
145      else
146        Finish();
147
148      CurrentVendor = Vendor;
149
150      assert(Contents.size() == 0);
151    }
152
153    void EmitAttribute(unsigned Attribute, unsigned Value) {
154      AttributeItemType attr = {
155        AttributeItemType::NumericAttribute,
156        Attribute,
157        Value,
158        StringRef("")
159      };
160      ContentsSize += getULEBSize(Attribute);
161      ContentsSize += getULEBSize(Value);
162      Contents.push_back(attr);
163    }
164
165    void EmitTextAttribute(unsigned Attribute, StringRef String) {
166      AttributeItemType attr = {
167        AttributeItemType::TextAttribute,
168        Attribute,
169        0,
170        String
171      };
172      ContentsSize += getULEBSize(Attribute);
173      // String + \0
174      ContentsSize += String.size()+1;
175
176      Contents.push_back(attr);
177    }
178
179    void Finish() {
180      // Vendor size + Vendor name + '\0'
181      const size_t VendorHeaderSize = 4 + CurrentVendor.size() + 1;
182
183      // Tag + Tag Size
184      const size_t TagHeaderSize = 1 + 4;
185
186      Streamer.EmitIntValue(VendorHeaderSize + TagHeaderSize + ContentsSize, 4);
187      Streamer.EmitBytes(CurrentVendor, 0);
188      Streamer.EmitIntValue(0, 1); // '\0'
189
190      Streamer.EmitIntValue(ARMBuildAttrs::File, 1);
191      Streamer.EmitIntValue(TagHeaderSize + ContentsSize, 4);
192
193      // Size should have been accounted for already, now
194      // emit each field as its type (ULEB or String)
195      for (unsigned int i=0; i<Contents.size(); ++i) {
196        AttributeItemType item = Contents[i];
197        Streamer.EmitULEB128IntValue(item.Tag, 0);
198        switch (item.Type) {
199        default: llvm_unreachable("Invalid attribute type");
200        case AttributeItemType::NumericAttribute:
201          Streamer.EmitULEB128IntValue(item.IntValue, 0);
202          break;
203        case AttributeItemType::TextAttribute:
204          Streamer.EmitBytes(item.StringValue.upper(), 0);
205          Streamer.EmitIntValue(0, 1); // '\0'
206          break;
207        }
208      }
209
210      Contents.clear();
211    }
212  };
213
214} // end of anonymous namespace
215
216MachineLocation ARMAsmPrinter::
217getDebugValueLocation(const MachineInstr *MI) const {
218  MachineLocation Location;
219  assert(MI->getNumOperands() == 4 && "Invalid no. of machine operands!");
220  // Frame address.  Currently handles register +- offset only.
221  if (MI->getOperand(0).isReg() && MI->getOperand(1).isImm())
222    Location.set(MI->getOperand(0).getReg(), MI->getOperand(1).getImm());
223  else {
224    DEBUG(dbgs() << "DBG_VALUE instruction ignored! " << *MI << "\n");
225  }
226  return Location;
227}
228
229/// EmitDwarfRegOp - Emit dwarf register operation.
230void ARMAsmPrinter::EmitDwarfRegOp(const MachineLocation &MLoc) const {
231  const TargetRegisterInfo *RI = TM.getRegisterInfo();
232  if (RI->getDwarfRegNum(MLoc.getReg(), false) != -1)
233    AsmPrinter::EmitDwarfRegOp(MLoc);
234  else {
235    unsigned Reg = MLoc.getReg();
236    if (Reg >= ARM::S0 && Reg <= ARM::S31) {
237      assert(ARM::S0 + 31 == ARM::S31 && "Unexpected ARM S register numbering");
238      // S registers are described as bit-pieces of a register
239      // S[2x] = DW_OP_regx(256 + (x>>1)) DW_OP_bit_piece(32, 0)
240      // S[2x+1] = DW_OP_regx(256 + (x>>1)) DW_OP_bit_piece(32, 32)
241
242      unsigned SReg = Reg - ARM::S0;
243      bool odd = SReg & 0x1;
244      unsigned Rx = 256 + (SReg >> 1);
245
246      OutStreamer.AddComment("DW_OP_regx for S register");
247      EmitInt8(dwarf::DW_OP_regx);
248
249      OutStreamer.AddComment(Twine(SReg));
250      EmitULEB128(Rx);
251
252      if (odd) {
253        OutStreamer.AddComment("DW_OP_bit_piece 32 32");
254        EmitInt8(dwarf::DW_OP_bit_piece);
255        EmitULEB128(32);
256        EmitULEB128(32);
257      } else {
258        OutStreamer.AddComment("DW_OP_bit_piece 32 0");
259        EmitInt8(dwarf::DW_OP_bit_piece);
260        EmitULEB128(32);
261        EmitULEB128(0);
262      }
263    } else if (Reg >= ARM::Q0 && Reg <= ARM::Q15) {
264      assert(ARM::Q0 + 15 == ARM::Q15 && "Unexpected ARM Q register numbering");
265      // Q registers Q0-Q15 are described by composing two D registers together.
266      // Qx = DW_OP_regx(256+2x) DW_OP_piece(8) DW_OP_regx(256+2x+1)
267      // DW_OP_piece(8)
268
269      unsigned QReg = Reg - ARM::Q0;
270      unsigned D1 = 256 + 2 * QReg;
271      unsigned D2 = D1 + 1;
272
273      OutStreamer.AddComment("DW_OP_regx for Q register: D1");
274      EmitInt8(dwarf::DW_OP_regx);
275      EmitULEB128(D1);
276      OutStreamer.AddComment("DW_OP_piece 8");
277      EmitInt8(dwarf::DW_OP_piece);
278      EmitULEB128(8);
279
280      OutStreamer.AddComment("DW_OP_regx for Q register: D2");
281      EmitInt8(dwarf::DW_OP_regx);
282      EmitULEB128(D2);
283      OutStreamer.AddComment("DW_OP_piece 8");
284      EmitInt8(dwarf::DW_OP_piece);
285      EmitULEB128(8);
286    }
287  }
288}
289
290void ARMAsmPrinter::EmitFunctionEntryLabel() {
291  OutStreamer.ForceCodeRegion();
292
293  if (AFI->isThumbFunction()) {
294    OutStreamer.EmitAssemblerFlag(MCAF_Code16);
295    OutStreamer.EmitThumbFunc(CurrentFnSym);
296  }
297
298  OutStreamer.EmitLabel(CurrentFnSym);
299}
300
301void ARMAsmPrinter::EmitXXStructor(const Constant *CV) {
302  uint64_t Size = TM.getTargetData()->getTypeAllocSize(CV->getType());
303  assert(Size && "C++ constructor pointer had zero size!");
304
305  const GlobalValue *GV = dyn_cast<GlobalValue>(CV->stripPointerCasts());
306  assert(GV && "C++ constructor pointer was not a GlobalValue!");
307
308  const MCExpr *E = MCSymbolRefExpr::Create(Mang->getSymbol(GV),
309                                            (Subtarget->isTargetDarwin()
310                                             ? MCSymbolRefExpr::VK_None
311                                             : MCSymbolRefExpr::VK_ARM_TARGET1),
312                                            OutContext);
313
314  OutStreamer.EmitValue(E, Size);
315}
316
317/// runOnMachineFunction - This uses the EmitInstruction()
318/// method to print assembly for each instruction.
319///
320bool ARMAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
321  AFI = MF.getInfo<ARMFunctionInfo>();
322  MCP = MF.getConstantPool();
323
324  return AsmPrinter::runOnMachineFunction(MF);
325}
326
327void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
328                                 raw_ostream &O, const char *Modifier) {
329  const MachineOperand &MO = MI->getOperand(OpNum);
330  unsigned TF = MO.getTargetFlags();
331
332  switch (MO.getType()) {
333  default: llvm_unreachable("<unknown operand type>");
334  case MachineOperand::MO_Register: {
335    unsigned Reg = MO.getReg();
336    assert(TargetRegisterInfo::isPhysicalRegister(Reg));
337    assert(!MO.getSubReg() && "Subregs should be eliminated!");
338    O << ARMInstPrinter::getRegisterName(Reg);
339    break;
340  }
341  case MachineOperand::MO_Immediate: {
342    int64_t Imm = MO.getImm();
343    O << '#';
344    if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
345        (TF == ARMII::MO_LO16))
346      O << ":lower16:";
347    else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
348             (TF == ARMII::MO_HI16))
349      O << ":upper16:";
350    O << Imm;
351    break;
352  }
353  case MachineOperand::MO_MachineBasicBlock:
354    O << *MO.getMBB()->getSymbol();
355    return;
356  case MachineOperand::MO_GlobalAddress: {
357    const GlobalValue *GV = MO.getGlobal();
358    if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
359        (TF & ARMII::MO_LO16))
360      O << ":lower16:";
361    else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
362             (TF & ARMII::MO_HI16))
363      O << ":upper16:";
364    O << *Mang->getSymbol(GV);
365
366    printOffset(MO.getOffset(), O);
367    if (TF == ARMII::MO_PLT)
368      O << "(PLT)";
369    break;
370  }
371  case MachineOperand::MO_ExternalSymbol: {
372    O << *GetExternalSymbolSymbol(MO.getSymbolName());
373    if (TF == ARMII::MO_PLT)
374      O << "(PLT)";
375    break;
376  }
377  case MachineOperand::MO_ConstantPoolIndex:
378    O << *GetCPISymbol(MO.getIndex());
379    break;
380  case MachineOperand::MO_JumpTableIndex:
381    O << *GetJTISymbol(MO.getIndex());
382    break;
383  }
384}
385
386//===--------------------------------------------------------------------===//
387
388MCSymbol *ARMAsmPrinter::
389GetARMSetPICJumpTableLabel2(unsigned uid, unsigned uid2,
390                            const MachineBasicBlock *MBB) const {
391  SmallString<60> Name;
392  raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix()
393    << getFunctionNumber() << '_' << uid << '_' << uid2
394    << "_set_" << MBB->getNumber();
395  return OutContext.GetOrCreateSymbol(Name.str());
396}
397
398MCSymbol *ARMAsmPrinter::
399GetARMJTIPICJumpTableLabel2(unsigned uid, unsigned uid2) const {
400  SmallString<60> Name;
401  raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix() << "JTI"
402    << getFunctionNumber() << '_' << uid << '_' << uid2;
403  return OutContext.GetOrCreateSymbol(Name.str());
404}
405
406
407MCSymbol *ARMAsmPrinter::GetARMSJLJEHLabel(void) const {
408  SmallString<60> Name;
409  raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix() << "SJLJEH"
410    << getFunctionNumber();
411  return OutContext.GetOrCreateSymbol(Name.str());
412}
413
414bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
415                                    unsigned AsmVariant, const char *ExtraCode,
416                                    raw_ostream &O) {
417  // Does this asm operand have a single letter operand modifier?
418  if (ExtraCode && ExtraCode[0]) {
419    if (ExtraCode[1] != 0) return true; // Unknown modifier.
420
421    switch (ExtraCode[0]) {
422    default: return true;  // Unknown modifier.
423    case 'a': // Print as a memory address.
424      if (MI->getOperand(OpNum).isReg()) {
425        O << "["
426          << ARMInstPrinter::getRegisterName(MI->getOperand(OpNum).getReg())
427          << "]";
428        return false;
429      }
430      // Fallthrough
431    case 'c': // Don't print "#" before an immediate operand.
432      if (!MI->getOperand(OpNum).isImm())
433        return true;
434      O << MI->getOperand(OpNum).getImm();
435      return false;
436    case 'P': // Print a VFP double precision register.
437    case 'q': // Print a NEON quad precision register.
438      printOperand(MI, OpNum, O);
439      return false;
440    case 'y': // Print a VFP single precision register as indexed double.
441      // This uses the ordering of the alias table to get the first 'd' register
442      // that overlaps the 's' register. Also, s0 is an odd register, hence the
443      // odd modulus check below.
444      if (MI->getOperand(OpNum).isReg()) {
445        unsigned Reg = MI->getOperand(OpNum).getReg();
446        const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo();
447        O << ARMInstPrinter::getRegisterName(TRI->getAliasSet(Reg)[0]) <<
448        (((Reg % 2) == 1) ? "[0]" : "[1]");
449        return false;
450      }
451      return true;
452    case 'B': // Bitwise inverse of integer or symbol without a preceding #.
453      if (!MI->getOperand(OpNum).isImm())
454        return true;
455      O << ~(MI->getOperand(OpNum).getImm());
456      return false;
457    case 'L': // The low 16 bits of an immediate constant.
458      if (!MI->getOperand(OpNum).isImm())
459        return true;
460      O << (MI->getOperand(OpNum).getImm() & 0xffff);
461      return false;
462    case 'M': { // A register range suitable for LDM/STM.
463      if (!MI->getOperand(OpNum).isReg())
464        return true;
465      const MachineOperand &MO = MI->getOperand(OpNum);
466      unsigned RegBegin = MO.getReg();
467      // This takes advantage of the 2 operand-ness of ldm/stm and that we've
468      // already got the operands in registers that are operands to the
469      // inline asm statement.
470
471      O << "{" << ARMInstPrinter::getRegisterName(RegBegin);
472
473      // FIXME: The register allocator not only may not have given us the
474      // registers in sequence, but may not be in ascending registers. This
475      // will require changes in the register allocator that'll need to be
476      // propagated down here if the operands change.
477      unsigned RegOps = OpNum + 1;
478      while (MI->getOperand(RegOps).isReg()) {
479        O << ", "
480          << ARMInstPrinter::getRegisterName(MI->getOperand(RegOps).getReg());
481        RegOps++;
482      }
483
484      O << "}";
485
486      return false;
487    }
488    case 'R': // The most significant register of a pair.
489    case 'Q': { // The least significant register of a pair.
490      if (OpNum == 0)
491        return true;
492      const MachineOperand &FlagsOP = MI->getOperand(OpNum - 1);
493      if (!FlagsOP.isImm())
494        return true;
495      unsigned Flags = FlagsOP.getImm();
496      unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
497      if (NumVals != 2)
498        return true;
499      unsigned RegOp = ExtraCode[0] == 'Q' ? OpNum : OpNum + 1;
500      if (RegOp >= MI->getNumOperands())
501        return true;
502      const MachineOperand &MO = MI->getOperand(RegOp);
503      if (!MO.isReg())
504        return true;
505      unsigned Reg = MO.getReg();
506      O << ARMInstPrinter::getRegisterName(Reg);
507      return false;
508    }
509
510    case 'e': // The low doubleword register of a NEON quad register.
511    case 'f': { // The high doubleword register of a NEON quad register.
512      if (!MI->getOperand(OpNum).isReg())
513        return true;
514      unsigned Reg = MI->getOperand(OpNum).getReg();
515      if (!ARM::QPRRegClass.contains(Reg))
516        return true;
517      const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo();
518      unsigned SubReg = TRI->getSubReg(Reg, ExtraCode[0] == 'e' ?
519                                       ARM::dsub_0 : ARM::dsub_1);
520      O << ARMInstPrinter::getRegisterName(SubReg);
521      return false;
522    }
523
524    // These modifiers are not yet supported.
525    case 'h': // A range of VFP/NEON registers suitable for VLD1/VST1.
526    case 'H': // The highest-numbered register of a pair.
527      return true;
528    }
529  }
530
531  printOperand(MI, OpNum, O);
532  return false;
533}
534
535bool ARMAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
536                                          unsigned OpNum, unsigned AsmVariant,
537                                          const char *ExtraCode,
538                                          raw_ostream &O) {
539  // Does this asm operand have a single letter operand modifier?
540  if (ExtraCode && ExtraCode[0]) {
541    if (ExtraCode[1] != 0) return true; // Unknown modifier.
542
543    switch (ExtraCode[0]) {
544      case 'A': // A memory operand for a VLD1/VST1 instruction.
545      default: return true;  // Unknown modifier.
546      case 'm': // The base register of a memory operand.
547        if (!MI->getOperand(OpNum).isReg())
548          return true;
549        O << ARMInstPrinter::getRegisterName(MI->getOperand(OpNum).getReg());
550        return false;
551    }
552  }
553
554  const MachineOperand &MO = MI->getOperand(OpNum);
555  assert(MO.isReg() && "unexpected inline asm memory operand");
556  O << "[" << ARMInstPrinter::getRegisterName(MO.getReg()) << "]";
557  return false;
558}
559
560void ARMAsmPrinter::EmitStartOfAsmFile(Module &M) {
561  if (Subtarget->isTargetDarwin()) {
562    Reloc::Model RelocM = TM.getRelocationModel();
563    if (RelocM == Reloc::PIC_ || RelocM == Reloc::DynamicNoPIC) {
564      // Declare all the text sections up front (before the DWARF sections
565      // emitted by AsmPrinter::doInitialization) so the assembler will keep
566      // them together at the beginning of the object file.  This helps
567      // avoid out-of-range branches that are due a fundamental limitation of
568      // the way symbol offsets are encoded with the current Darwin ARM
569      // relocations.
570      const TargetLoweringObjectFileMachO &TLOFMacho =
571        static_cast<const TargetLoweringObjectFileMachO &>(
572          getObjFileLowering());
573      OutStreamer.SwitchSection(TLOFMacho.getTextSection());
574      OutStreamer.SwitchSection(TLOFMacho.getTextCoalSection());
575      OutStreamer.SwitchSection(TLOFMacho.getConstTextCoalSection());
576      if (RelocM == Reloc::DynamicNoPIC) {
577        const MCSection *sect =
578          OutContext.getMachOSection("__TEXT", "__symbol_stub4",
579                                     MCSectionMachO::S_SYMBOL_STUBS,
580                                     12, SectionKind::getText());
581        OutStreamer.SwitchSection(sect);
582      } else {
583        const MCSection *sect =
584          OutContext.getMachOSection("__TEXT", "__picsymbolstub4",
585                                     MCSectionMachO::S_SYMBOL_STUBS,
586                                     16, SectionKind::getText());
587        OutStreamer.SwitchSection(sect);
588      }
589      const MCSection *StaticInitSect =
590        OutContext.getMachOSection("__TEXT", "__StaticInit",
591                                   MCSectionMachO::S_REGULAR |
592                                   MCSectionMachO::S_ATTR_PURE_INSTRUCTIONS,
593                                   SectionKind::getText());
594      OutStreamer.SwitchSection(StaticInitSect);
595    }
596  }
597
598  // Use unified assembler syntax.
599  OutStreamer.EmitAssemblerFlag(MCAF_SyntaxUnified);
600
601  // Emit ARM Build Attributes
602  if (Subtarget->isTargetELF())
603    emitAttributes();
604}
605
606
607void ARMAsmPrinter::EmitEndOfAsmFile(Module &M) {
608  if (Subtarget->isTargetDarwin()) {
609    // All darwin targets use mach-o.
610    const TargetLoweringObjectFileMachO &TLOFMacho =
611      static_cast<const TargetLoweringObjectFileMachO &>(getObjFileLowering());
612    MachineModuleInfoMachO &MMIMacho =
613      MMI->getObjFileInfo<MachineModuleInfoMachO>();
614
615    // Output non-lazy-pointers for external and common global variables.
616    MachineModuleInfoMachO::SymbolListTy Stubs = MMIMacho.GetGVStubList();
617
618    if (!Stubs.empty()) {
619      // Switch with ".non_lazy_symbol_pointer" directive.
620      OutStreamer.SwitchSection(TLOFMacho.getNonLazySymbolPointerSection());
621      EmitAlignment(2);
622      for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
623        // L_foo$stub:
624        OutStreamer.EmitLabel(Stubs[i].first);
625        //   .indirect_symbol _foo
626        MachineModuleInfoImpl::StubValueTy &MCSym = Stubs[i].second;
627        OutStreamer.EmitSymbolAttribute(MCSym.getPointer(),MCSA_IndirectSymbol);
628
629        if (MCSym.getInt())
630          // External to current translation unit.
631          OutStreamer.EmitIntValue(0, 4/*size*/, 0/*addrspace*/);
632        else
633          // Internal to current translation unit.
634          //
635          // When we place the LSDA into the TEXT section, the type info
636          // pointers need to be indirect and pc-rel. We accomplish this by
637          // using NLPs; however, sometimes the types are local to the file.
638          // We need to fill in the value for the NLP in those cases.
639          OutStreamer.EmitValue(MCSymbolRefExpr::Create(MCSym.getPointer(),
640                                                        OutContext),
641                                4/*size*/, 0/*addrspace*/);
642      }
643
644      Stubs.clear();
645      OutStreamer.AddBlankLine();
646    }
647
648    Stubs = MMIMacho.GetHiddenGVStubList();
649    if (!Stubs.empty()) {
650      OutStreamer.SwitchSection(getObjFileLowering().getDataSection());
651      EmitAlignment(2);
652      for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
653        // L_foo$stub:
654        OutStreamer.EmitLabel(Stubs[i].first);
655        //   .long _foo
656        OutStreamer.EmitValue(MCSymbolRefExpr::
657                              Create(Stubs[i].second.getPointer(),
658                                     OutContext),
659                              4/*size*/, 0/*addrspace*/);
660      }
661
662      Stubs.clear();
663      OutStreamer.AddBlankLine();
664    }
665
666    // Funny Darwin hack: This flag tells the linker that no global symbols
667    // contain code that falls through to other global symbols (e.g. the obvious
668    // implementation of multiple entry points).  If this doesn't occur, the
669    // linker can safely perform dead code stripping.  Since LLVM never
670    // generates code that does this, it is always safe to set.
671    OutStreamer.EmitAssemblerFlag(MCAF_SubsectionsViaSymbols);
672  }
673}
674
675//===----------------------------------------------------------------------===//
676// Helper routines for EmitStartOfAsmFile() and EmitEndOfAsmFile()
677// FIXME:
678// The following seem like one-off assembler flags, but they actually need
679// to appear in the .ARM.attributes section in ELF.
680// Instead of subclassing the MCELFStreamer, we do the work here.
681
682void ARMAsmPrinter::emitAttributes() {
683
684  emitARMAttributeSection();
685
686  /* GAS expect .fpu to be emitted, regardless of VFP build attribute */
687  bool emitFPU = false;
688  AttributeEmitter *AttrEmitter;
689  if (OutStreamer.hasRawTextSupport()) {
690    AttrEmitter = new AsmAttributeEmitter(OutStreamer);
691    emitFPU = true;
692  } else {
693    MCObjectStreamer &O = static_cast<MCObjectStreamer&>(OutStreamer);
694    AttrEmitter = new ObjectAttributeEmitter(O);
695  }
696
697  AttrEmitter->MaybeSwitchVendor("aeabi");
698
699  std::string CPUString = Subtarget->getCPUString();
700
701  if (CPUString == "cortex-a8" ||
702      Subtarget->isCortexA8()) {
703    AttrEmitter->EmitTextAttribute(ARMBuildAttrs::CPU_name, "cortex-a8");
704    AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v7);
705    AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch_profile,
706                               ARMBuildAttrs::ApplicationProfile);
707    AttrEmitter->EmitAttribute(ARMBuildAttrs::ARM_ISA_use,
708                               ARMBuildAttrs::Allowed);
709    AttrEmitter->EmitAttribute(ARMBuildAttrs::THUMB_ISA_use,
710                               ARMBuildAttrs::AllowThumb32);
711    // Fixme: figure out when this is emitted.
712    //AttrEmitter->EmitAttribute(ARMBuildAttrs::WMMX_arch,
713    //                           ARMBuildAttrs::AllowWMMXv1);
714    //
715
716    /// ADD additional Else-cases here!
717  } else if (CPUString == "xscale") {
718    AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v5TEJ);
719    AttrEmitter->EmitAttribute(ARMBuildAttrs::ARM_ISA_use,
720                               ARMBuildAttrs::Allowed);
721    AttrEmitter->EmitAttribute(ARMBuildAttrs::THUMB_ISA_use,
722                               ARMBuildAttrs::Allowed);
723  } else if (CPUString == "generic") {
724    // FIXME: Why these defaults?
725    AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v4T);
726    AttrEmitter->EmitAttribute(ARMBuildAttrs::ARM_ISA_use,
727                               ARMBuildAttrs::Allowed);
728    AttrEmitter->EmitAttribute(ARMBuildAttrs::THUMB_ISA_use,
729                               ARMBuildAttrs::Allowed);
730  }
731
732  if (Subtarget->hasNEON() && emitFPU) {
733    /* NEON is not exactly a VFP architecture, but GAS emit one of
734     * neon/neon-vfpv4/vfpv3/vfpv2 for .fpu parameters */
735    if (Subtarget->hasNEONVFP4())
736      AttrEmitter->EmitTextAttribute(ARMBuildAttrs::Advanced_SIMD_arch, "neon-vfpv4");
737    else
738     AttrEmitter->EmitTextAttribute(ARMBuildAttrs::Advanced_SIMD_arch, "neon");
739    /* If emitted for NEON, omit from VFP below, since you can have both
740     * NEON and VFP in build attributes but only one .fpu */
741    emitFPU = false;
742  }
743
744  /* VFPv4 + .fpu */
745  if (Subtarget->hasVFP4()) {
746    AttrEmitter->EmitAttribute(ARMBuildAttrs::VFP_arch,
747                               ARMBuildAttrs::AllowFPv4A);
748    if (emitFPU)
749      AttrEmitter->EmitTextAttribute(ARMBuildAttrs::VFP_arch, "vfpv4");
750
751  /* VFPv3 + .fpu */
752  } else if (Subtarget->hasVFP3()) {
753    AttrEmitter->EmitAttribute(ARMBuildAttrs::VFP_arch,
754                               ARMBuildAttrs::AllowFPv3A);
755    if (emitFPU)
756      AttrEmitter->EmitTextAttribute(ARMBuildAttrs::VFP_arch, "vfpv3");
757
758  /* VFPv2 + .fpu */
759  } else if (Subtarget->hasVFP2()) {
760    AttrEmitter->EmitAttribute(ARMBuildAttrs::VFP_arch,
761                               ARMBuildAttrs::AllowFPv2);
762    if (emitFPU)
763      AttrEmitter->EmitTextAttribute(ARMBuildAttrs::VFP_arch, "vfpv2");
764  }
765
766  /* TODO: ARMBuildAttrs::Allowed is not completely accurate,
767   * since NEON can have 1 (allowed) or 2 (MAC operations) */
768  if (Subtarget->hasNEON()) {
769    AttrEmitter->EmitAttribute(ARMBuildAttrs::Advanced_SIMD_arch,
770                               ARMBuildAttrs::Allowed);
771  }
772
773  // Signal various FP modes.
774  if (!TM.Options.UnsafeFPMath) {
775    AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_denormal,
776                               ARMBuildAttrs::Allowed);
777    AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_exceptions,
778                               ARMBuildAttrs::Allowed);
779  }
780
781  if (TM.Options.NoInfsFPMath && TM.Options.NoNaNsFPMath)
782    AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_number_model,
783                               ARMBuildAttrs::Allowed);
784  else
785    AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_number_model,
786                               ARMBuildAttrs::AllowIEE754);
787
788  // FIXME: add more flags to ARMBuildAttrs.h
789  // 8-bytes alignment stuff.
790  AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_align8_needed, 1);
791  AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_align8_preserved, 1);
792
793  // Hard float.  Use both S and D registers and conform to AAPCS-VFP.
794  if (Subtarget->isAAPCS_ABI() && TM.Options.FloatABIType == FloatABI::Hard) {
795    AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_HardFP_use, 3);
796    AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_VFP_args, 1);
797  }
798  // FIXME: Should we signal R9 usage?
799
800  if (Subtarget->hasDivide())
801    AttrEmitter->EmitAttribute(ARMBuildAttrs::DIV_use, 1);
802
803  AttrEmitter->Finish();
804  delete AttrEmitter;
805}
806
807void ARMAsmPrinter::emitARMAttributeSection() {
808  // <format-version>
809  // [ <section-length> "vendor-name"
810  // [ <file-tag> <size> <attribute>*
811  //   | <section-tag> <size> <section-number>* 0 <attribute>*
812  //   | <symbol-tag> <size> <symbol-number>* 0 <attribute>*
813  //   ]+
814  // ]*
815
816  if (OutStreamer.hasRawTextSupport())
817    return;
818
819  const ARMElfTargetObjectFile &TLOFELF =
820    static_cast<const ARMElfTargetObjectFile &>
821    (getObjFileLowering());
822
823  OutStreamer.SwitchSection(TLOFELF.getAttributesSection());
824
825  // Format version
826  OutStreamer.EmitIntValue(0x41, 1);
827}
828
829//===----------------------------------------------------------------------===//
830
831static MCSymbol *getPICLabel(const char *Prefix, unsigned FunctionNumber,
832                             unsigned LabelId, MCContext &Ctx) {
833
834  MCSymbol *Label = Ctx.GetOrCreateSymbol(Twine(Prefix)
835                       + "PC" + Twine(FunctionNumber) + "_" + Twine(LabelId));
836  return Label;
837}
838
839static MCSymbolRefExpr::VariantKind
840getModifierVariantKind(ARMCP::ARMCPModifier Modifier) {
841  switch (Modifier) {
842  case ARMCP::no_modifier: return MCSymbolRefExpr::VK_None;
843  case ARMCP::TLSGD:       return MCSymbolRefExpr::VK_ARM_TLSGD;
844  case ARMCP::TPOFF:       return MCSymbolRefExpr::VK_ARM_TPOFF;
845  case ARMCP::GOTTPOFF:    return MCSymbolRefExpr::VK_ARM_GOTTPOFF;
846  case ARMCP::GOT:         return MCSymbolRefExpr::VK_ARM_GOT;
847  case ARMCP::GOTOFF:      return MCSymbolRefExpr::VK_ARM_GOTOFF;
848  }
849  llvm_unreachable("Invalid ARMCPModifier!");
850}
851
852MCSymbol *ARMAsmPrinter::GetARMGVSymbol(const GlobalValue *GV) {
853  bool isIndirect = Subtarget->isTargetDarwin() &&
854    Subtarget->GVIsIndirectSymbol(GV, TM.getRelocationModel());
855  if (!isIndirect)
856    return Mang->getSymbol(GV);
857
858  // FIXME: Remove this when Darwin transition to @GOT like syntax.
859  MCSymbol *MCSym = GetSymbolWithGlobalValueBase(GV, "$non_lazy_ptr");
860  MachineModuleInfoMachO &MMIMachO =
861    MMI->getObjFileInfo<MachineModuleInfoMachO>();
862  MachineModuleInfoImpl::StubValueTy &StubSym =
863    GV->hasHiddenVisibility() ? MMIMachO.getHiddenGVStubEntry(MCSym) :
864    MMIMachO.getGVStubEntry(MCSym);
865  if (StubSym.getPointer() == 0)
866    StubSym = MachineModuleInfoImpl::
867      StubValueTy(Mang->getSymbol(GV), !GV->hasInternalLinkage());
868  return MCSym;
869}
870
871void ARMAsmPrinter::
872EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) {
873  int Size = TM.getTargetData()->getTypeAllocSize(MCPV->getType());
874
875  ARMConstantPoolValue *ACPV = static_cast<ARMConstantPoolValue*>(MCPV);
876
877  MCSymbol *MCSym;
878  if (ACPV->isLSDA()) {
879    SmallString<128> Str;
880    raw_svector_ostream OS(Str);
881    OS << MAI->getPrivateGlobalPrefix() << "_LSDA_" << getFunctionNumber();
882    MCSym = OutContext.GetOrCreateSymbol(OS.str());
883  } else if (ACPV->isBlockAddress()) {
884    const BlockAddress *BA =
885      cast<ARMConstantPoolConstant>(ACPV)->getBlockAddress();
886    MCSym = GetBlockAddressSymbol(BA);
887  } else if (ACPV->isGlobalValue()) {
888    const GlobalValue *GV = cast<ARMConstantPoolConstant>(ACPV)->getGV();
889    MCSym = GetARMGVSymbol(GV);
890  } else if (ACPV->isMachineBasicBlock()) {
891    const MachineBasicBlock *MBB = cast<ARMConstantPoolMBB>(ACPV)->getMBB();
892    MCSym = MBB->getSymbol();
893  } else {
894    assert(ACPV->isExtSymbol() && "unrecognized constant pool value");
895    const char *Sym = cast<ARMConstantPoolSymbol>(ACPV)->getSymbol();
896    MCSym = GetExternalSymbolSymbol(Sym);
897  }
898
899  // Create an MCSymbol for the reference.
900  const MCExpr *Expr =
901    MCSymbolRefExpr::Create(MCSym, getModifierVariantKind(ACPV->getModifier()),
902                            OutContext);
903
904  if (ACPV->getPCAdjustment()) {
905    MCSymbol *PCLabel = getPICLabel(MAI->getPrivateGlobalPrefix(),
906                                    getFunctionNumber(),
907                                    ACPV->getLabelId(),
908                                    OutContext);
909    const MCExpr *PCRelExpr = MCSymbolRefExpr::Create(PCLabel, OutContext);
910    PCRelExpr =
911      MCBinaryExpr::CreateAdd(PCRelExpr,
912                              MCConstantExpr::Create(ACPV->getPCAdjustment(),
913                                                     OutContext),
914                              OutContext);
915    if (ACPV->mustAddCurrentAddress()) {
916      // We want "(<expr> - .)", but MC doesn't have a concept of the '.'
917      // label, so just emit a local label end reference that instead.
918      MCSymbol *DotSym = OutContext.CreateTempSymbol();
919      OutStreamer.EmitLabel(DotSym);
920      const MCExpr *DotExpr = MCSymbolRefExpr::Create(DotSym, OutContext);
921      PCRelExpr = MCBinaryExpr::CreateSub(PCRelExpr, DotExpr, OutContext);
922    }
923    Expr = MCBinaryExpr::CreateSub(Expr, PCRelExpr, OutContext);
924  }
925  OutStreamer.EmitValue(Expr, Size);
926}
927
928void ARMAsmPrinter::EmitJumpTable(const MachineInstr *MI) {
929  unsigned Opcode = MI->getOpcode();
930  int OpNum = 1;
931  if (Opcode == ARM::BR_JTadd)
932    OpNum = 2;
933  else if (Opcode == ARM::BR_JTm)
934    OpNum = 3;
935
936  const MachineOperand &MO1 = MI->getOperand(OpNum);
937  const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
938  unsigned JTI = MO1.getIndex();
939
940  // Tag the jump table appropriately for precise disassembly.
941  OutStreamer.EmitJumpTable32Region();
942
943  // Emit a label for the jump table.
944  MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
945  OutStreamer.EmitLabel(JTISymbol);
946
947  // Emit each entry of the table.
948  const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
949  const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
950  const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
951
952  for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
953    MachineBasicBlock *MBB = JTBBs[i];
954    // Construct an MCExpr for the entry. We want a value of the form:
955    // (BasicBlockAddr - TableBeginAddr)
956    //
957    // For example, a table with entries jumping to basic blocks BB0 and BB1
958    // would look like:
959    // LJTI_0_0:
960    //    .word (LBB0 - LJTI_0_0)
961    //    .word (LBB1 - LJTI_0_0)
962    const MCExpr *Expr = MCSymbolRefExpr::Create(MBB->getSymbol(), OutContext);
963
964    if (TM.getRelocationModel() == Reloc::PIC_)
965      Expr = MCBinaryExpr::CreateSub(Expr, MCSymbolRefExpr::Create(JTISymbol,
966                                                                   OutContext),
967                                     OutContext);
968    // If we're generating a table of Thumb addresses in static relocation
969    // model, we need to add one to keep interworking correctly.
970    else if (AFI->isThumbFunction())
971      Expr = MCBinaryExpr::CreateAdd(Expr, MCConstantExpr::Create(1,OutContext),
972                                     OutContext);
973    OutStreamer.EmitValue(Expr, 4);
974  }
975}
976
977void ARMAsmPrinter::EmitJump2Table(const MachineInstr *MI) {
978  unsigned Opcode = MI->getOpcode();
979  int OpNum = (Opcode == ARM::t2BR_JT) ? 2 : 1;
980  const MachineOperand &MO1 = MI->getOperand(OpNum);
981  const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
982  unsigned JTI = MO1.getIndex();
983
984  // Emit a label for the jump table.
985  if (MI->getOpcode() == ARM::t2TBB_JT) {
986    OutStreamer.EmitJumpTable8Region();
987  } else if (MI->getOpcode() == ARM::t2TBH_JT) {
988    OutStreamer.EmitJumpTable16Region();
989  } else {
990    OutStreamer.EmitJumpTable32Region();
991  }
992
993  MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
994  OutStreamer.EmitLabel(JTISymbol);
995
996  // Emit each entry of the table.
997  const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
998  const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
999  const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
1000  unsigned OffsetWidth = 4;
1001  if (MI->getOpcode() == ARM::t2TBB_JT)
1002    OffsetWidth = 1;
1003  else if (MI->getOpcode() == ARM::t2TBH_JT)
1004    OffsetWidth = 2;
1005
1006  for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
1007    MachineBasicBlock *MBB = JTBBs[i];
1008    const MCExpr *MBBSymbolExpr = MCSymbolRefExpr::Create(MBB->getSymbol(),
1009                                                      OutContext);
1010    // If this isn't a TBB or TBH, the entries are direct branch instructions.
1011    if (OffsetWidth == 4) {
1012      MCInst BrInst;
1013      BrInst.setOpcode(ARM::t2B);
1014      BrInst.addOperand(MCOperand::CreateExpr(MBBSymbolExpr));
1015      BrInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1016      BrInst.addOperand(MCOperand::CreateReg(0));
1017      OutStreamer.EmitInstruction(BrInst);
1018      continue;
1019    }
1020    // Otherwise it's an offset from the dispatch instruction. Construct an
1021    // MCExpr for the entry. We want a value of the form:
1022    // (BasicBlockAddr - TableBeginAddr) / 2
1023    //
1024    // For example, a TBB table with entries jumping to basic blocks BB0 and BB1
1025    // would look like:
1026    // LJTI_0_0:
1027    //    .byte (LBB0 - LJTI_0_0) / 2
1028    //    .byte (LBB1 - LJTI_0_0) / 2
1029    const MCExpr *Expr =
1030      MCBinaryExpr::CreateSub(MBBSymbolExpr,
1031                              MCSymbolRefExpr::Create(JTISymbol, OutContext),
1032                              OutContext);
1033    Expr = MCBinaryExpr::CreateDiv(Expr, MCConstantExpr::Create(2, OutContext),
1034                                   OutContext);
1035    OutStreamer.EmitValue(Expr, OffsetWidth);
1036  }
1037}
1038
1039void ARMAsmPrinter::PrintDebugValueComment(const MachineInstr *MI,
1040                                           raw_ostream &OS) {
1041  unsigned NOps = MI->getNumOperands();
1042  assert(NOps==4);
1043  OS << '\t' << MAI->getCommentString() << "DEBUG_VALUE: ";
1044  // cast away const; DIetc do not take const operands for some reason.
1045  DIVariable V(const_cast<MDNode *>(MI->getOperand(NOps-1).getMetadata()));
1046  OS << V.getName();
1047  OS << " <- ";
1048  // Frame address.  Currently handles register +- offset only.
1049  assert(MI->getOperand(0).isReg() && MI->getOperand(1).isImm());
1050  OS << '['; printOperand(MI, 0, OS); OS << '+'; printOperand(MI, 1, OS);
1051  OS << ']';
1052  OS << "+";
1053  printOperand(MI, NOps-2, OS);
1054}
1055
1056static void populateADROperands(MCInst &Inst, unsigned Dest,
1057                                const MCSymbol *Label,
1058                                unsigned pred, unsigned ccreg,
1059                                MCContext &Ctx) {
1060  const MCExpr *SymbolExpr = MCSymbolRefExpr::Create(Label, Ctx);
1061  Inst.addOperand(MCOperand::CreateReg(Dest));
1062  Inst.addOperand(MCOperand::CreateExpr(SymbolExpr));
1063  // Add predicate operands.
1064  Inst.addOperand(MCOperand::CreateImm(pred));
1065  Inst.addOperand(MCOperand::CreateReg(ccreg));
1066}
1067
1068void ARMAsmPrinter::EmitPatchedInstruction(const MachineInstr *MI,
1069                                           unsigned Opcode) {
1070  MCInst TmpInst;
1071
1072  // Emit the instruction as usual, just patch the opcode.
1073  LowerARMMachineInstrToMCInst(MI, TmpInst, *this);
1074  TmpInst.setOpcode(Opcode);
1075  OutStreamer.EmitInstruction(TmpInst);
1076}
1077
1078void ARMAsmPrinter::EmitUnwindingInstruction(const MachineInstr *MI) {
1079  assert(MI->getFlag(MachineInstr::FrameSetup) &&
1080      "Only instruction which are involved into frame setup code are allowed");
1081
1082  const MachineFunction &MF = *MI->getParent()->getParent();
1083  const TargetRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo();
1084  const ARMFunctionInfo &AFI = *MF.getInfo<ARMFunctionInfo>();
1085
1086  unsigned FramePtr = RegInfo->getFrameRegister(MF);
1087  unsigned Opc = MI->getOpcode();
1088  unsigned SrcReg, DstReg;
1089
1090  if (Opc == ARM::tPUSH || Opc == ARM::tLDRpci) {
1091    // Two special cases:
1092    // 1) tPUSH does not have src/dst regs.
1093    // 2) for Thumb1 code we sometimes materialize the constant via constpool
1094    // load. Yes, this is pretty fragile, but for now I don't see better
1095    // way... :(
1096    SrcReg = DstReg = ARM::SP;
1097  } else {
1098    SrcReg = MI->getOperand(1).getReg();
1099    DstReg = MI->getOperand(0).getReg();
1100  }
1101
1102  // Try to figure out the unwinding opcode out of src / dst regs.
1103  if (MI->mayStore()) {
1104    // Register saves.
1105    assert(DstReg == ARM::SP &&
1106           "Only stack pointer as a destination reg is supported");
1107
1108    SmallVector<unsigned, 4> RegList;
1109    // Skip src & dst reg, and pred ops.
1110    unsigned StartOp = 2 + 2;
1111    // Use all the operands.
1112    unsigned NumOffset = 0;
1113
1114    switch (Opc) {
1115    default:
1116      MI->dump();
1117      llvm_unreachable("Unsupported opcode for unwinding information");
1118    case ARM::tPUSH:
1119      // Special case here: no src & dst reg, but two extra imp ops.
1120      StartOp = 2; NumOffset = 2;
1121    case ARM::STMDB_UPD:
1122    case ARM::t2STMDB_UPD:
1123    case ARM::VSTMDDB_UPD:
1124      assert(SrcReg == ARM::SP &&
1125             "Only stack pointer as a source reg is supported");
1126      for (unsigned i = StartOp, NumOps = MI->getNumOperands() - NumOffset;
1127           i != NumOps; ++i)
1128        RegList.push_back(MI->getOperand(i).getReg());
1129      break;
1130    case ARM::STR_PRE_IMM:
1131    case ARM::STR_PRE_REG:
1132    case ARM::t2STR_PRE:
1133      assert(MI->getOperand(2).getReg() == ARM::SP &&
1134             "Only stack pointer as a source reg is supported");
1135      RegList.push_back(SrcReg);
1136      break;
1137    }
1138    OutStreamer.EmitRegSave(RegList, Opc == ARM::VSTMDDB_UPD);
1139  } else {
1140    // Changes of stack / frame pointer.
1141    if (SrcReg == ARM::SP) {
1142      int64_t Offset = 0;
1143      switch (Opc) {
1144      default:
1145        MI->dump();
1146        llvm_unreachable("Unsupported opcode for unwinding information");
1147      case ARM::MOVr:
1148      case ARM::tMOVr:
1149        Offset = 0;
1150        break;
1151      case ARM::ADDri:
1152        Offset = -MI->getOperand(2).getImm();
1153        break;
1154      case ARM::SUBri:
1155      case ARM::t2SUBri:
1156        Offset = MI->getOperand(2).getImm();
1157        break;
1158      case ARM::tSUBspi:
1159        Offset = MI->getOperand(2).getImm()*4;
1160        break;
1161      case ARM::tADDspi:
1162      case ARM::tADDrSPi:
1163        Offset = -MI->getOperand(2).getImm()*4;
1164        break;
1165      case ARM::tLDRpci: {
1166        // Grab the constpool index and check, whether it corresponds to
1167        // original or cloned constpool entry.
1168        unsigned CPI = MI->getOperand(1).getIndex();
1169        const MachineConstantPool *MCP = MF.getConstantPool();
1170        if (CPI >= MCP->getConstants().size())
1171          CPI = AFI.getOriginalCPIdx(CPI);
1172        assert(CPI != -1U && "Invalid constpool index");
1173
1174        // Derive the actual offset.
1175        const MachineConstantPoolEntry &CPE = MCP->getConstants()[CPI];
1176        assert(!CPE.isMachineConstantPoolEntry() && "Invalid constpool entry");
1177        // FIXME: Check for user, it should be "add" instruction!
1178        Offset = -cast<ConstantInt>(CPE.Val.ConstVal)->getSExtValue();
1179        break;
1180      }
1181      }
1182
1183      if (DstReg == FramePtr && FramePtr != ARM::SP)
1184        // Set-up of the frame pointer. Positive values correspond to "add"
1185        // instruction.
1186        OutStreamer.EmitSetFP(FramePtr, ARM::SP, -Offset);
1187      else if (DstReg == ARM::SP) {
1188        // Change of SP by an offset. Positive values correspond to "sub"
1189        // instruction.
1190        OutStreamer.EmitPad(Offset);
1191      } else {
1192        MI->dump();
1193        llvm_unreachable("Unsupported opcode for unwinding information");
1194      }
1195    } else if (DstReg == ARM::SP) {
1196      // FIXME: .movsp goes here
1197      MI->dump();
1198      llvm_unreachable("Unsupported opcode for unwinding information");
1199    }
1200    else {
1201      MI->dump();
1202      llvm_unreachable("Unsupported opcode for unwinding information");
1203    }
1204  }
1205}
1206
1207extern cl::opt<bool> EnableARMEHABI;
1208
1209// Simple pseudo-instructions have their lowering (with expansion to real
1210// instructions) auto-generated.
1211#include "ARMGenMCPseudoLowering.inc"
1212
1213void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) {
1214  if (MI->getOpcode() != ARM::CONSTPOOL_ENTRY)
1215    OutStreamer.EmitCodeRegion();
1216
1217  // Emit unwinding stuff for frame-related instructions
1218  if (EnableARMEHABI && MI->getFlag(MachineInstr::FrameSetup))
1219    EmitUnwindingInstruction(MI);
1220
1221  // Do any auto-generated pseudo lowerings.
1222  if (emitPseudoExpansionLowering(OutStreamer, MI))
1223    return;
1224
1225  assert(!convertAddSubFlagsOpcode(MI->getOpcode()) &&
1226         "Pseudo flag setting opcode should be expanded early");
1227
1228  // Check for manual lowerings.
1229  unsigned Opc = MI->getOpcode();
1230  switch (Opc) {
1231  case ARM::t2MOVi32imm: llvm_unreachable("Should be lowered by thumb2it pass");
1232  case ARM::DBG_VALUE: {
1233    if (isVerbose() && OutStreamer.hasRawTextSupport()) {
1234      SmallString<128> TmpStr;
1235      raw_svector_ostream OS(TmpStr);
1236      PrintDebugValueComment(MI, OS);
1237      OutStreamer.EmitRawText(StringRef(OS.str()));
1238    }
1239    return;
1240  }
1241  case ARM::LEApcrel:
1242  case ARM::tLEApcrel:
1243  case ARM::t2LEApcrel: {
1244    // FIXME: Need to also handle globals and externals
1245    MCInst TmpInst;
1246    TmpInst.setOpcode(MI->getOpcode() == ARM::t2LEApcrel ? ARM::t2ADR
1247                      : (MI->getOpcode() == ARM::tLEApcrel ? ARM::tADR
1248                         : ARM::ADR));
1249    populateADROperands(TmpInst, MI->getOperand(0).getReg(),
1250                        GetCPISymbol(MI->getOperand(1).getIndex()),
1251                        MI->getOperand(2).getImm(), MI->getOperand(3).getReg(),
1252                        OutContext);
1253    OutStreamer.EmitInstruction(TmpInst);
1254    return;
1255  }
1256  case ARM::LEApcrelJT:
1257  case ARM::tLEApcrelJT:
1258  case ARM::t2LEApcrelJT: {
1259    MCInst TmpInst;
1260    TmpInst.setOpcode(MI->getOpcode() == ARM::t2LEApcrelJT ? ARM::t2ADR
1261                      : (MI->getOpcode() == ARM::tLEApcrelJT ? ARM::tADR
1262                         : ARM::ADR));
1263    populateADROperands(TmpInst, MI->getOperand(0).getReg(),
1264                      GetARMJTIPICJumpTableLabel2(MI->getOperand(1).getIndex(),
1265                                                  MI->getOperand(2).getImm()),
1266                      MI->getOperand(3).getImm(), MI->getOperand(4).getReg(),
1267                      OutContext);
1268    OutStreamer.EmitInstruction(TmpInst);
1269    return;
1270  }
1271  // Darwin call instructions are just normal call instructions with different
1272  // clobber semantics (they clobber R9).
1273  case ARM::BXr9_CALL:
1274  case ARM::BX_CALL: {
1275    {
1276      MCInst TmpInst;
1277      TmpInst.setOpcode(ARM::MOVr);
1278      TmpInst.addOperand(MCOperand::CreateReg(ARM::LR));
1279      TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1280      // Add predicate operands.
1281      TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1282      TmpInst.addOperand(MCOperand::CreateReg(0));
1283      // Add 's' bit operand (always reg0 for this)
1284      TmpInst.addOperand(MCOperand::CreateReg(0));
1285      OutStreamer.EmitInstruction(TmpInst);
1286    }
1287    {
1288      MCInst TmpInst;
1289      TmpInst.setOpcode(ARM::BX);
1290      TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1291      OutStreamer.EmitInstruction(TmpInst);
1292    }
1293    return;
1294  }
1295  case ARM::tBXr9_CALL:
1296  case ARM::tBX_CALL: {
1297    {
1298      MCInst TmpInst;
1299      TmpInst.setOpcode(ARM::tMOVr);
1300      TmpInst.addOperand(MCOperand::CreateReg(ARM::LR));
1301      TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1302      // Add predicate operands.
1303      TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1304      TmpInst.addOperand(MCOperand::CreateReg(0));
1305      OutStreamer.EmitInstruction(TmpInst);
1306    }
1307    {
1308      MCInst TmpInst;
1309      TmpInst.setOpcode(ARM::tBX);
1310      TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1311      // Add predicate operands.
1312      TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1313      TmpInst.addOperand(MCOperand::CreateReg(0));
1314      OutStreamer.EmitInstruction(TmpInst);
1315    }
1316    return;
1317  }
1318  case ARM::BMOVPCRXr9_CALL:
1319  case ARM::BMOVPCRX_CALL: {
1320    {
1321      MCInst TmpInst;
1322      TmpInst.setOpcode(ARM::MOVr);
1323      TmpInst.addOperand(MCOperand::CreateReg(ARM::LR));
1324      TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1325      // Add predicate operands.
1326      TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1327      TmpInst.addOperand(MCOperand::CreateReg(0));
1328      // Add 's' bit operand (always reg0 for this)
1329      TmpInst.addOperand(MCOperand::CreateReg(0));
1330      OutStreamer.EmitInstruction(TmpInst);
1331    }
1332    {
1333      MCInst TmpInst;
1334      TmpInst.setOpcode(ARM::MOVr);
1335      TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1336      TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1337      // Add predicate operands.
1338      TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1339      TmpInst.addOperand(MCOperand::CreateReg(0));
1340      // Add 's' bit operand (always reg0 for this)
1341      TmpInst.addOperand(MCOperand::CreateReg(0));
1342      OutStreamer.EmitInstruction(TmpInst);
1343    }
1344    return;
1345  }
1346  case ARM::BMOVPCBr9_CALL:
1347  case ARM::BMOVPCB_CALL: {
1348    {
1349      MCInst TmpInst;
1350      TmpInst.setOpcode(ARM::MOVr);
1351      TmpInst.addOperand(MCOperand::CreateReg(ARM::LR));
1352      TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1353      // Add predicate operands.
1354      TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1355      TmpInst.addOperand(MCOperand::CreateReg(0));
1356      // Add 's' bit operand (always reg0 for this)
1357      TmpInst.addOperand(MCOperand::CreateReg(0));
1358      OutStreamer.EmitInstruction(TmpInst);
1359    }
1360    {
1361      MCInst TmpInst;
1362      TmpInst.setOpcode(ARM::Bcc);
1363      const GlobalValue *GV = MI->getOperand(0).getGlobal();
1364      MCSymbol *GVSym = Mang->getSymbol(GV);
1365      const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
1366      TmpInst.addOperand(MCOperand::CreateExpr(GVSymExpr));
1367      // Add predicate operands.
1368      TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1369      TmpInst.addOperand(MCOperand::CreateReg(0));
1370      OutStreamer.EmitInstruction(TmpInst);
1371    }
1372    return;
1373  }
1374  case ARM::t2BMOVPCBr9_CALL:
1375  case ARM::t2BMOVPCB_CALL: {
1376    {
1377      MCInst TmpInst;
1378      TmpInst.setOpcode(ARM::tMOVr);
1379      TmpInst.addOperand(MCOperand::CreateReg(ARM::LR));
1380      TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1381      // Add predicate operands.
1382      TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1383      TmpInst.addOperand(MCOperand::CreateReg(0));
1384      OutStreamer.EmitInstruction(TmpInst);
1385    }
1386    {
1387      MCInst TmpInst;
1388      TmpInst.setOpcode(ARM::t2B);
1389      const GlobalValue *GV = MI->getOperand(0).getGlobal();
1390      MCSymbol *GVSym = Mang->getSymbol(GV);
1391      const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
1392      TmpInst.addOperand(MCOperand::CreateExpr(GVSymExpr));
1393      // Add predicate operands.
1394      TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1395      TmpInst.addOperand(MCOperand::CreateReg(0));
1396      OutStreamer.EmitInstruction(TmpInst);
1397    }
1398    return;
1399  }
1400  case ARM::MOVi16_ga_pcrel:
1401  case ARM::t2MOVi16_ga_pcrel: {
1402    MCInst TmpInst;
1403    TmpInst.setOpcode(Opc == ARM::MOVi16_ga_pcrel? ARM::MOVi16 : ARM::t2MOVi16);
1404    TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1405
1406    unsigned TF = MI->getOperand(1).getTargetFlags();
1407    bool isPIC = TF == ARMII::MO_LO16_NONLAZY_PIC;
1408    const GlobalValue *GV = MI->getOperand(1).getGlobal();
1409    MCSymbol *GVSym = GetARMGVSymbol(GV);
1410    const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
1411    if (isPIC) {
1412      MCSymbol *LabelSym = getPICLabel(MAI->getPrivateGlobalPrefix(),
1413                                       getFunctionNumber(),
1414                                       MI->getOperand(2).getImm(), OutContext);
1415      const MCExpr *LabelSymExpr= MCSymbolRefExpr::Create(LabelSym, OutContext);
1416      unsigned PCAdj = (Opc == ARM::MOVi16_ga_pcrel) ? 8 : 4;
1417      const MCExpr *PCRelExpr =
1418        ARMMCExpr::CreateLower16(MCBinaryExpr::CreateSub(GVSymExpr,
1419                                  MCBinaryExpr::CreateAdd(LabelSymExpr,
1420                                      MCConstantExpr::Create(PCAdj, OutContext),
1421                                          OutContext), OutContext), OutContext);
1422      TmpInst.addOperand(MCOperand::CreateExpr(PCRelExpr));
1423    } else {
1424      const MCExpr *RefExpr= ARMMCExpr::CreateLower16(GVSymExpr, OutContext);
1425      TmpInst.addOperand(MCOperand::CreateExpr(RefExpr));
1426    }
1427
1428    // Add predicate operands.
1429    TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1430    TmpInst.addOperand(MCOperand::CreateReg(0));
1431    // Add 's' bit operand (always reg0 for this)
1432    TmpInst.addOperand(MCOperand::CreateReg(0));
1433    OutStreamer.EmitInstruction(TmpInst);
1434    return;
1435  }
1436  case ARM::MOVTi16_ga_pcrel:
1437  case ARM::t2MOVTi16_ga_pcrel: {
1438    MCInst TmpInst;
1439    TmpInst.setOpcode(Opc == ARM::MOVTi16_ga_pcrel
1440                      ? ARM::MOVTi16 : ARM::t2MOVTi16);
1441    TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1442    TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1443
1444    unsigned TF = MI->getOperand(2).getTargetFlags();
1445    bool isPIC = TF == ARMII::MO_HI16_NONLAZY_PIC;
1446    const GlobalValue *GV = MI->getOperand(2).getGlobal();
1447    MCSymbol *GVSym = GetARMGVSymbol(GV);
1448    const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
1449    if (isPIC) {
1450      MCSymbol *LabelSym = getPICLabel(MAI->getPrivateGlobalPrefix(),
1451                                       getFunctionNumber(),
1452                                       MI->getOperand(3).getImm(), OutContext);
1453      const MCExpr *LabelSymExpr= MCSymbolRefExpr::Create(LabelSym, OutContext);
1454      unsigned PCAdj = (Opc == ARM::MOVTi16_ga_pcrel) ? 8 : 4;
1455      const MCExpr *PCRelExpr =
1456        ARMMCExpr::CreateUpper16(MCBinaryExpr::CreateSub(GVSymExpr,
1457                                   MCBinaryExpr::CreateAdd(LabelSymExpr,
1458                                      MCConstantExpr::Create(PCAdj, OutContext),
1459                                          OutContext), OutContext), OutContext);
1460      TmpInst.addOperand(MCOperand::CreateExpr(PCRelExpr));
1461    } else {
1462      const MCExpr *RefExpr= ARMMCExpr::CreateUpper16(GVSymExpr, OutContext);
1463      TmpInst.addOperand(MCOperand::CreateExpr(RefExpr));
1464    }
1465    // Add predicate operands.
1466    TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1467    TmpInst.addOperand(MCOperand::CreateReg(0));
1468    // Add 's' bit operand (always reg0 for this)
1469    TmpInst.addOperand(MCOperand::CreateReg(0));
1470    OutStreamer.EmitInstruction(TmpInst);
1471    return;
1472  }
1473  case ARM::tPICADD: {
1474    // This is a pseudo op for a label + instruction sequence, which looks like:
1475    // LPC0:
1476    //     add r0, pc
1477    // This adds the address of LPC0 to r0.
1478
1479    // Emit the label.
1480    OutStreamer.EmitLabel(getPICLabel(MAI->getPrivateGlobalPrefix(),
1481                          getFunctionNumber(), MI->getOperand(2).getImm(),
1482                          OutContext));
1483
1484    // Form and emit the add.
1485    MCInst AddInst;
1486    AddInst.setOpcode(ARM::tADDhirr);
1487    AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1488    AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1489    AddInst.addOperand(MCOperand::CreateReg(ARM::PC));
1490    // Add predicate operands.
1491    AddInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1492    AddInst.addOperand(MCOperand::CreateReg(0));
1493    OutStreamer.EmitInstruction(AddInst);
1494    return;
1495  }
1496  case ARM::PICADD: {
1497    // This is a pseudo op for a label + instruction sequence, which looks like:
1498    // LPC0:
1499    //     add r0, pc, r0
1500    // This adds the address of LPC0 to r0.
1501
1502    // Emit the label.
1503    OutStreamer.EmitLabel(getPICLabel(MAI->getPrivateGlobalPrefix(),
1504                          getFunctionNumber(), MI->getOperand(2).getImm(),
1505                          OutContext));
1506
1507    // Form and emit the add.
1508    MCInst AddInst;
1509    AddInst.setOpcode(ARM::ADDrr);
1510    AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1511    AddInst.addOperand(MCOperand::CreateReg(ARM::PC));
1512    AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1513    // Add predicate operands.
1514    AddInst.addOperand(MCOperand::CreateImm(MI->getOperand(3).getImm()));
1515    AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(4).getReg()));
1516    // Add 's' bit operand (always reg0 for this)
1517    AddInst.addOperand(MCOperand::CreateReg(0));
1518    OutStreamer.EmitInstruction(AddInst);
1519    return;
1520  }
1521  case ARM::PICSTR:
1522  case ARM::PICSTRB:
1523  case ARM::PICSTRH:
1524  case ARM::PICLDR:
1525  case ARM::PICLDRB:
1526  case ARM::PICLDRH:
1527  case ARM::PICLDRSB:
1528  case ARM::PICLDRSH: {
1529    // This is a pseudo op for a label + instruction sequence, which looks like:
1530    // LPC0:
1531    //     OP r0, [pc, r0]
1532    // The LCP0 label is referenced by a constant pool entry in order to get
1533    // a PC-relative address at the ldr instruction.
1534
1535    // Emit the label.
1536    OutStreamer.EmitLabel(getPICLabel(MAI->getPrivateGlobalPrefix(),
1537                          getFunctionNumber(), MI->getOperand(2).getImm(),
1538                          OutContext));
1539
1540    // Form and emit the load
1541    unsigned Opcode;
1542    switch (MI->getOpcode()) {
1543    default:
1544      llvm_unreachable("Unexpected opcode!");
1545    case ARM::PICSTR:   Opcode = ARM::STRrs; break;
1546    case ARM::PICSTRB:  Opcode = ARM::STRBrs; break;
1547    case ARM::PICSTRH:  Opcode = ARM::STRH; break;
1548    case ARM::PICLDR:   Opcode = ARM::LDRrs; break;
1549    case ARM::PICLDRB:  Opcode = ARM::LDRBrs; break;
1550    case ARM::PICLDRH:  Opcode = ARM::LDRH; break;
1551    case ARM::PICLDRSB: Opcode = ARM::LDRSB; break;
1552    case ARM::PICLDRSH: Opcode = ARM::LDRSH; break;
1553    }
1554    MCInst LdStInst;
1555    LdStInst.setOpcode(Opcode);
1556    LdStInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1557    LdStInst.addOperand(MCOperand::CreateReg(ARM::PC));
1558    LdStInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1559    LdStInst.addOperand(MCOperand::CreateImm(0));
1560    // Add predicate operands.
1561    LdStInst.addOperand(MCOperand::CreateImm(MI->getOperand(3).getImm()));
1562    LdStInst.addOperand(MCOperand::CreateReg(MI->getOperand(4).getReg()));
1563    OutStreamer.EmitInstruction(LdStInst);
1564
1565    return;
1566  }
1567  case ARM::CONSTPOOL_ENTRY: {
1568    /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool
1569    /// in the function.  The first operand is the ID# for this instruction, the
1570    /// second is the index into the MachineConstantPool that this is, the third
1571    /// is the size in bytes of this constant pool entry.
1572    /// The required alignment is specified on the basic block holding this MI.
1573    unsigned LabelId = (unsigned)MI->getOperand(0).getImm();
1574    unsigned CPIdx   = (unsigned)MI->getOperand(1).getIndex();
1575
1576    // Mark the constant pool entry as data if we're not already in a data
1577    // region.
1578    OutStreamer.EmitDataRegion();
1579    OutStreamer.EmitLabel(GetCPISymbol(LabelId));
1580
1581    const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPIdx];
1582    if (MCPE.isMachineConstantPoolEntry())
1583      EmitMachineConstantPoolValue(MCPE.Val.MachineCPVal);
1584    else
1585      EmitGlobalConstant(MCPE.Val.ConstVal);
1586    return;
1587  }
1588  case ARM::t2BR_JT: {
1589    // Lower and emit the instruction itself, then the jump table following it.
1590    MCInst TmpInst;
1591    TmpInst.setOpcode(ARM::tMOVr);
1592    TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1593    TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1594    // Add predicate operands.
1595    TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1596    TmpInst.addOperand(MCOperand::CreateReg(0));
1597    OutStreamer.EmitInstruction(TmpInst);
1598    // Output the data for the jump table itself
1599    EmitJump2Table(MI);
1600    return;
1601  }
1602  case ARM::t2TBB_JT: {
1603    // Lower and emit the instruction itself, then the jump table following it.
1604    MCInst TmpInst;
1605
1606    TmpInst.setOpcode(ARM::t2TBB);
1607    TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1608    TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1609    // Add predicate operands.
1610    TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1611    TmpInst.addOperand(MCOperand::CreateReg(0));
1612    OutStreamer.EmitInstruction(TmpInst);
1613    // Output the data for the jump table itself
1614    EmitJump2Table(MI);
1615    // Make sure the next instruction is 2-byte aligned.
1616    EmitAlignment(1);
1617    return;
1618  }
1619  case ARM::t2TBH_JT: {
1620    // Lower and emit the instruction itself, then the jump table following it.
1621    MCInst TmpInst;
1622
1623    TmpInst.setOpcode(ARM::t2TBH);
1624    TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1625    TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1626    // Add predicate operands.
1627    TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1628    TmpInst.addOperand(MCOperand::CreateReg(0));
1629    OutStreamer.EmitInstruction(TmpInst);
1630    // Output the data for the jump table itself
1631    EmitJump2Table(MI);
1632    return;
1633  }
1634  case ARM::tBR_JTr:
1635  case ARM::BR_JTr: {
1636    // Lower and emit the instruction itself, then the jump table following it.
1637    // mov pc, target
1638    MCInst TmpInst;
1639    unsigned Opc = MI->getOpcode() == ARM::BR_JTr ?
1640      ARM::MOVr : ARM::tMOVr;
1641    TmpInst.setOpcode(Opc);
1642    TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1643    TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1644    // Add predicate operands.
1645    TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1646    TmpInst.addOperand(MCOperand::CreateReg(0));
1647    // Add 's' bit operand (always reg0 for this)
1648    if (Opc == ARM::MOVr)
1649      TmpInst.addOperand(MCOperand::CreateReg(0));
1650    OutStreamer.EmitInstruction(TmpInst);
1651
1652    // Make sure the Thumb jump table is 4-byte aligned.
1653    if (Opc == ARM::tMOVr)
1654      EmitAlignment(2);
1655
1656    // Output the data for the jump table itself
1657    EmitJumpTable(MI);
1658    return;
1659  }
1660  case ARM::BR_JTm: {
1661    // Lower and emit the instruction itself, then the jump table following it.
1662    // ldr pc, target
1663    MCInst TmpInst;
1664    if (MI->getOperand(1).getReg() == 0) {
1665      // literal offset
1666      TmpInst.setOpcode(ARM::LDRi12);
1667      TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1668      TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1669      TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
1670    } else {
1671      TmpInst.setOpcode(ARM::LDRrs);
1672      TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1673      TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1674      TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1675      TmpInst.addOperand(MCOperand::CreateImm(0));
1676    }
1677    // Add predicate operands.
1678    TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1679    TmpInst.addOperand(MCOperand::CreateReg(0));
1680    OutStreamer.EmitInstruction(TmpInst);
1681
1682    // Output the data for the jump table itself
1683    EmitJumpTable(MI);
1684    return;
1685  }
1686  case ARM::BR_JTadd: {
1687    // Lower and emit the instruction itself, then the jump table following it.
1688    // add pc, target, idx
1689    MCInst TmpInst;
1690    TmpInst.setOpcode(ARM::ADDrr);
1691    TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1692    TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1693    TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1694    // Add predicate operands.
1695    TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1696    TmpInst.addOperand(MCOperand::CreateReg(0));
1697    // Add 's' bit operand (always reg0 for this)
1698    TmpInst.addOperand(MCOperand::CreateReg(0));
1699    OutStreamer.EmitInstruction(TmpInst);
1700
1701    // Output the data for the jump table itself
1702    EmitJumpTable(MI);
1703    return;
1704  }
1705  case ARM::TRAP: {
1706    // Non-Darwin binutils don't yet support the "trap" mnemonic.
1707    // FIXME: Remove this special case when they do.
1708    if (!Subtarget->isTargetDarwin()) {
1709      //.long 0xe7ffdefe @ trap
1710      uint32_t Val = 0xe7ffdefeUL;
1711      OutStreamer.AddComment("trap");
1712      OutStreamer.EmitIntValue(Val, 4);
1713      return;
1714    }
1715    break;
1716  }
1717  case ARM::tTRAP: {
1718    // Non-Darwin binutils don't yet support the "trap" mnemonic.
1719    // FIXME: Remove this special case when they do.
1720    if (!Subtarget->isTargetDarwin()) {
1721      //.short 57086 @ trap
1722      uint16_t Val = 0xdefe;
1723      OutStreamer.AddComment("trap");
1724      OutStreamer.EmitIntValue(Val, 2);
1725      return;
1726    }
1727    break;
1728  }
1729  case ARM::t2Int_eh_sjlj_setjmp:
1730  case ARM::t2Int_eh_sjlj_setjmp_nofp:
1731  case ARM::tInt_eh_sjlj_setjmp: {
1732    // Two incoming args: GPR:$src, GPR:$val
1733    // mov $val, pc
1734    // adds $val, #7
1735    // str $val, [$src, #4]
1736    // movs r0, #0
1737    // b 1f
1738    // movs r0, #1
1739    // 1:
1740    unsigned SrcReg = MI->getOperand(0).getReg();
1741    unsigned ValReg = MI->getOperand(1).getReg();
1742    MCSymbol *Label = GetARMSJLJEHLabel();
1743    {
1744      MCInst TmpInst;
1745      TmpInst.setOpcode(ARM::tMOVr);
1746      TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1747      TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1748      // Predicate.
1749      TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1750      TmpInst.addOperand(MCOperand::CreateReg(0));
1751      OutStreamer.AddComment("eh_setjmp begin");
1752      OutStreamer.EmitInstruction(TmpInst);
1753    }
1754    {
1755      MCInst TmpInst;
1756      TmpInst.setOpcode(ARM::tADDi3);
1757      TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1758      // 's' bit operand
1759      TmpInst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1760      TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1761      TmpInst.addOperand(MCOperand::CreateImm(7));
1762      // Predicate.
1763      TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1764      TmpInst.addOperand(MCOperand::CreateReg(0));
1765      OutStreamer.EmitInstruction(TmpInst);
1766    }
1767    {
1768      MCInst TmpInst;
1769      TmpInst.setOpcode(ARM::tSTRi);
1770      TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1771      TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1772      // The offset immediate is #4. The operand value is scaled by 4 for the
1773      // tSTR instruction.
1774      TmpInst.addOperand(MCOperand::CreateImm(1));
1775      // Predicate.
1776      TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1777      TmpInst.addOperand(MCOperand::CreateReg(0));
1778      OutStreamer.EmitInstruction(TmpInst);
1779    }
1780    {
1781      MCInst TmpInst;
1782      TmpInst.setOpcode(ARM::tMOVi8);
1783      TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
1784      TmpInst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1785      TmpInst.addOperand(MCOperand::CreateImm(0));
1786      // Predicate.
1787      TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1788      TmpInst.addOperand(MCOperand::CreateReg(0));
1789      OutStreamer.EmitInstruction(TmpInst);
1790    }
1791    {
1792      const MCExpr *SymbolExpr = MCSymbolRefExpr::Create(Label, OutContext);
1793      MCInst TmpInst;
1794      TmpInst.setOpcode(ARM::tB);
1795      TmpInst.addOperand(MCOperand::CreateExpr(SymbolExpr));
1796      TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1797      TmpInst.addOperand(MCOperand::CreateReg(0));
1798      OutStreamer.EmitInstruction(TmpInst);
1799    }
1800    {
1801      MCInst TmpInst;
1802      TmpInst.setOpcode(ARM::tMOVi8);
1803      TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
1804      TmpInst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1805      TmpInst.addOperand(MCOperand::CreateImm(1));
1806      // Predicate.
1807      TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1808      TmpInst.addOperand(MCOperand::CreateReg(0));
1809      OutStreamer.AddComment("eh_setjmp end");
1810      OutStreamer.EmitInstruction(TmpInst);
1811    }
1812    OutStreamer.EmitLabel(Label);
1813    return;
1814  }
1815
1816  case ARM::Int_eh_sjlj_setjmp_nofp:
1817  case ARM::Int_eh_sjlj_setjmp: {
1818    // Two incoming args: GPR:$src, GPR:$val
1819    // add $val, pc, #8
1820    // str $val, [$src, #+4]
1821    // mov r0, #0
1822    // add pc, pc, #0
1823    // mov r0, #1
1824    unsigned SrcReg = MI->getOperand(0).getReg();
1825    unsigned ValReg = MI->getOperand(1).getReg();
1826
1827    {
1828      MCInst TmpInst;
1829      TmpInst.setOpcode(ARM::ADDri);
1830      TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1831      TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1832      TmpInst.addOperand(MCOperand::CreateImm(8));
1833      // Predicate.
1834      TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1835      TmpInst.addOperand(MCOperand::CreateReg(0));
1836      // 's' bit operand (always reg0 for this).
1837      TmpInst.addOperand(MCOperand::CreateReg(0));
1838      OutStreamer.AddComment("eh_setjmp begin");
1839      OutStreamer.EmitInstruction(TmpInst);
1840    }
1841    {
1842      MCInst TmpInst;
1843      TmpInst.setOpcode(ARM::STRi12);
1844      TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1845      TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1846      TmpInst.addOperand(MCOperand::CreateImm(4));
1847      // Predicate.
1848      TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1849      TmpInst.addOperand(MCOperand::CreateReg(0));
1850      OutStreamer.EmitInstruction(TmpInst);
1851    }
1852    {
1853      MCInst TmpInst;
1854      TmpInst.setOpcode(ARM::MOVi);
1855      TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
1856      TmpInst.addOperand(MCOperand::CreateImm(0));
1857      // Predicate.
1858      TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1859      TmpInst.addOperand(MCOperand::CreateReg(0));
1860      // 's' bit operand (always reg0 for this).
1861      TmpInst.addOperand(MCOperand::CreateReg(0));
1862      OutStreamer.EmitInstruction(TmpInst);
1863    }
1864    {
1865      MCInst TmpInst;
1866      TmpInst.setOpcode(ARM::ADDri);
1867      TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1868      TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1869      TmpInst.addOperand(MCOperand::CreateImm(0));
1870      // Predicate.
1871      TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1872      TmpInst.addOperand(MCOperand::CreateReg(0));
1873      // 's' bit operand (always reg0 for this).
1874      TmpInst.addOperand(MCOperand::CreateReg(0));
1875      OutStreamer.EmitInstruction(TmpInst);
1876    }
1877    {
1878      MCInst TmpInst;
1879      TmpInst.setOpcode(ARM::MOVi);
1880      TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
1881      TmpInst.addOperand(MCOperand::CreateImm(1));
1882      // Predicate.
1883      TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1884      TmpInst.addOperand(MCOperand::CreateReg(0));
1885      // 's' bit operand (always reg0 for this).
1886      TmpInst.addOperand(MCOperand::CreateReg(0));
1887      OutStreamer.AddComment("eh_setjmp end");
1888      OutStreamer.EmitInstruction(TmpInst);
1889    }
1890    return;
1891  }
1892  case ARM::Int_eh_sjlj_longjmp: {
1893    // ldr sp, [$src, #8]
1894    // ldr $scratch, [$src, #4]
1895    // ldr r7, [$src]
1896    // bx $scratch
1897    unsigned SrcReg = MI->getOperand(0).getReg();
1898    unsigned ScratchReg = MI->getOperand(1).getReg();
1899    {
1900      MCInst TmpInst;
1901      TmpInst.setOpcode(ARM::LDRi12);
1902      TmpInst.addOperand(MCOperand::CreateReg(ARM::SP));
1903      TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1904      TmpInst.addOperand(MCOperand::CreateImm(8));
1905      // Predicate.
1906      TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1907      TmpInst.addOperand(MCOperand::CreateReg(0));
1908      OutStreamer.EmitInstruction(TmpInst);
1909    }
1910    {
1911      MCInst TmpInst;
1912      TmpInst.setOpcode(ARM::LDRi12);
1913      TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1914      TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1915      TmpInst.addOperand(MCOperand::CreateImm(4));
1916      // Predicate.
1917      TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1918      TmpInst.addOperand(MCOperand::CreateReg(0));
1919      OutStreamer.EmitInstruction(TmpInst);
1920    }
1921    {
1922      MCInst TmpInst;
1923      TmpInst.setOpcode(ARM::LDRi12);
1924      TmpInst.addOperand(MCOperand::CreateReg(ARM::R7));
1925      TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1926      TmpInst.addOperand(MCOperand::CreateImm(0));
1927      // Predicate.
1928      TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1929      TmpInst.addOperand(MCOperand::CreateReg(0));
1930      OutStreamer.EmitInstruction(TmpInst);
1931    }
1932    {
1933      MCInst TmpInst;
1934      TmpInst.setOpcode(ARM::BX);
1935      TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1936      // Predicate.
1937      TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1938      TmpInst.addOperand(MCOperand::CreateReg(0));
1939      OutStreamer.EmitInstruction(TmpInst);
1940    }
1941    return;
1942  }
1943  case ARM::tInt_eh_sjlj_longjmp: {
1944    // ldr $scratch, [$src, #8]
1945    // mov sp, $scratch
1946    // ldr $scratch, [$src, #4]
1947    // ldr r7, [$src]
1948    // bx $scratch
1949    unsigned SrcReg = MI->getOperand(0).getReg();
1950    unsigned ScratchReg = MI->getOperand(1).getReg();
1951    {
1952      MCInst TmpInst;
1953      TmpInst.setOpcode(ARM::tLDRi);
1954      TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1955      TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1956      // The offset immediate is #8. The operand value is scaled by 4 for the
1957      // tLDR instruction.
1958      TmpInst.addOperand(MCOperand::CreateImm(2));
1959      // Predicate.
1960      TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1961      TmpInst.addOperand(MCOperand::CreateReg(0));
1962      OutStreamer.EmitInstruction(TmpInst);
1963    }
1964    {
1965      MCInst TmpInst;
1966      TmpInst.setOpcode(ARM::tMOVr);
1967      TmpInst.addOperand(MCOperand::CreateReg(ARM::SP));
1968      TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1969      // Predicate.
1970      TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1971      TmpInst.addOperand(MCOperand::CreateReg(0));
1972      OutStreamer.EmitInstruction(TmpInst);
1973    }
1974    {
1975      MCInst TmpInst;
1976      TmpInst.setOpcode(ARM::tLDRi);
1977      TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1978      TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1979      TmpInst.addOperand(MCOperand::CreateImm(1));
1980      // Predicate.
1981      TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1982      TmpInst.addOperand(MCOperand::CreateReg(0));
1983      OutStreamer.EmitInstruction(TmpInst);
1984    }
1985    {
1986      MCInst TmpInst;
1987      TmpInst.setOpcode(ARM::tLDRr);
1988      TmpInst.addOperand(MCOperand::CreateReg(ARM::R7));
1989      TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1990      TmpInst.addOperand(MCOperand::CreateReg(0));
1991      // Predicate.
1992      TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1993      TmpInst.addOperand(MCOperand::CreateReg(0));
1994      OutStreamer.EmitInstruction(TmpInst);
1995    }
1996    {
1997      MCInst TmpInst;
1998      TmpInst.setOpcode(ARM::tBX);
1999      TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
2000      // Predicate.
2001      TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
2002      TmpInst.addOperand(MCOperand::CreateReg(0));
2003      OutStreamer.EmitInstruction(TmpInst);
2004    }
2005    return;
2006  }
2007  }
2008
2009  MCInst TmpInst;
2010  LowerARMMachineInstrToMCInst(MI, TmpInst, *this);
2011
2012  OutStreamer.EmitInstruction(TmpInst);
2013}
2014
2015//===----------------------------------------------------------------------===//
2016// Target Registry Stuff
2017//===----------------------------------------------------------------------===//
2018
2019// Force static initialization.
2020extern "C" void LLVMInitializeARMAsmPrinter() {
2021  RegisterAsmPrinter<ARMAsmPrinter> X(TheARMTarget);
2022  RegisterAsmPrinter<ARMAsmPrinter> Y(TheThumbTarget);
2023}
2024