ARMAsmPrinter.cpp revision fc3dc102e0bef8ecb7cd13ceab77dc130175f792
1//===-- ARMAsmPrinter.cpp - Print machine code to an ARM .s file ----------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains a printer that converts from our internal representation 11// of machine-dependent LLVM code to GAS-format ARM assembly language. 12// 13//===----------------------------------------------------------------------===// 14 15#define DEBUG_TYPE "asm-printer" 16#include "ARMAsmPrinter.h" 17#include "ARM.h" 18#include "ARMBuildAttrs.h" 19#include "ARMConstantPoolValue.h" 20#include "ARMMachineFunctionInfo.h" 21#include "ARMTargetMachine.h" 22#include "ARMTargetObjectFile.h" 23#include "InstPrinter/ARMInstPrinter.h" 24#include "MCTargetDesc/ARMAddressingModes.h" 25#include "MCTargetDesc/ARMMCExpr.h" 26#include "llvm/ADT/SetVector.h" 27#include "llvm/ADT/SmallString.h" 28#include "llvm/Assembly/Writer.h" 29#include "llvm/CodeGen/MachineFunctionPass.h" 30#include "llvm/CodeGen/MachineJumpTableInfo.h" 31#include "llvm/CodeGen/MachineModuleInfoImpls.h" 32#include "llvm/DebugInfo.h" 33#include "llvm/IR/Constants.h" 34#include "llvm/IR/DataLayout.h" 35#include "llvm/IR/Module.h" 36#include "llvm/IR/Type.h" 37#include "llvm/MC/MCAsmInfo.h" 38#include "llvm/MC/MCAssembler.h" 39#include "llvm/MC/MCContext.h" 40#include "llvm/MC/MCELFStreamer.h" 41#include "llvm/MC/MCInst.h" 42#include "llvm/MC/MCInstBuilder.h" 43#include "llvm/MC/MCObjectStreamer.h" 44#include "llvm/MC/MCSectionMachO.h" 45#include "llvm/MC/MCStreamer.h" 46#include "llvm/MC/MCSymbol.h" 47#include "llvm/Support/CommandLine.h" 48#include "llvm/Support/Debug.h" 49#include "llvm/Support/ELF.h" 50#include "llvm/Support/ErrorHandling.h" 51#include "llvm/Support/TargetRegistry.h" 52#include "llvm/Support/raw_ostream.h" 53#include "llvm/Target/Mangler.h" 54#include "llvm/Target/TargetMachine.h" 55#include <cctype> 56using namespace llvm; 57 58namespace { 59 60 // Per section and per symbol attributes are not supported. 61 // To implement them we would need the ability to delay this emission 62 // until the assembly file is fully parsed/generated as only then do we 63 // know the symbol and section numbers. 64 class AttributeEmitter { 65 public: 66 virtual void MaybeSwitchVendor(StringRef Vendor) = 0; 67 virtual void EmitAttribute(unsigned Attribute, unsigned Value) = 0; 68 virtual void EmitTextAttribute(unsigned Attribute, StringRef String) = 0; 69 virtual void Finish() = 0; 70 virtual ~AttributeEmitter() {} 71 }; 72 73 class AsmAttributeEmitter : public AttributeEmitter { 74 MCStreamer &Streamer; 75 76 public: 77 AsmAttributeEmitter(MCStreamer &Streamer_) : Streamer(Streamer_) {} 78 void MaybeSwitchVendor(StringRef Vendor) { } 79 80 void EmitAttribute(unsigned Attribute, unsigned Value) { 81 Streamer.EmitRawText("\t.eabi_attribute " + 82 Twine(Attribute) + ", " + Twine(Value)); 83 } 84 85 void EmitTextAttribute(unsigned Attribute, StringRef String) { 86 switch (Attribute) { 87 default: llvm_unreachable("Unsupported Text attribute in ASM Mode"); 88 case ARMBuildAttrs::CPU_name: 89 Streamer.EmitRawText(StringRef("\t.cpu ") + String.lower()); 90 break; 91 /* GAS requires .fpu to be emitted regardless of EABI attribute */ 92 case ARMBuildAttrs::Advanced_SIMD_arch: 93 case ARMBuildAttrs::VFP_arch: 94 Streamer.EmitRawText(StringRef("\t.fpu ") + String.lower()); 95 break; 96 } 97 } 98 void Finish() { } 99 }; 100 101 class ObjectAttributeEmitter : public AttributeEmitter { 102 // This structure holds all attributes, accounting for 103 // their string/numeric value, so we can later emmit them 104 // in declaration order, keeping all in the same vector 105 struct AttributeItemType { 106 enum { 107 HiddenAttribute = 0, 108 NumericAttribute, 109 TextAttribute 110 } Type; 111 unsigned Tag; 112 unsigned IntValue; 113 StringRef StringValue; 114 }; 115 116 MCObjectStreamer &Streamer; 117 StringRef CurrentVendor; 118 SmallVector<AttributeItemType, 64> Contents; 119 120 // Account for the ULEB/String size of each item, 121 // not just the number of items 122 size_t ContentsSize; 123 // FIXME: this should be in a more generic place, but 124 // getULEBSize() is in MCAsmInfo and will be moved to MCDwarf 125 size_t getULEBSize(int Value) { 126 size_t Size = 0; 127 do { 128 Value >>= 7; 129 Size += sizeof(int8_t); // Is this really necessary? 130 } while (Value); 131 return Size; 132 } 133 134 public: 135 ObjectAttributeEmitter(MCObjectStreamer &Streamer_) : 136 Streamer(Streamer_), CurrentVendor(""), ContentsSize(0) { } 137 138 void MaybeSwitchVendor(StringRef Vendor) { 139 assert(!Vendor.empty() && "Vendor cannot be empty."); 140 141 if (CurrentVendor.empty()) 142 CurrentVendor = Vendor; 143 else if (CurrentVendor == Vendor) 144 return; 145 else 146 Finish(); 147 148 CurrentVendor = Vendor; 149 150 assert(Contents.size() == 0); 151 } 152 153 void EmitAttribute(unsigned Attribute, unsigned Value) { 154 AttributeItemType attr = { 155 AttributeItemType::NumericAttribute, 156 Attribute, 157 Value, 158 StringRef("") 159 }; 160 ContentsSize += getULEBSize(Attribute); 161 ContentsSize += getULEBSize(Value); 162 Contents.push_back(attr); 163 } 164 165 void EmitTextAttribute(unsigned Attribute, StringRef String) { 166 AttributeItemType attr = { 167 AttributeItemType::TextAttribute, 168 Attribute, 169 0, 170 String 171 }; 172 ContentsSize += getULEBSize(Attribute); 173 // String + \0 174 ContentsSize += String.size()+1; 175 176 Contents.push_back(attr); 177 } 178 179 void Finish() { 180 // Vendor size + Vendor name + '\0' 181 const size_t VendorHeaderSize = 4 + CurrentVendor.size() + 1; 182 183 // Tag + Tag Size 184 const size_t TagHeaderSize = 1 + 4; 185 186 Streamer.EmitIntValue(VendorHeaderSize + TagHeaderSize + ContentsSize, 4); 187 Streamer.EmitBytes(CurrentVendor); 188 Streamer.EmitIntValue(0, 1); // '\0' 189 190 Streamer.EmitIntValue(ARMBuildAttrs::File, 1); 191 Streamer.EmitIntValue(TagHeaderSize + ContentsSize, 4); 192 193 // Size should have been accounted for already, now 194 // emit each field as its type (ULEB or String) 195 for (unsigned int i=0; i<Contents.size(); ++i) { 196 AttributeItemType item = Contents[i]; 197 Streamer.EmitULEB128IntValue(item.Tag); 198 switch (item.Type) { 199 default: llvm_unreachable("Invalid attribute type"); 200 case AttributeItemType::NumericAttribute: 201 Streamer.EmitULEB128IntValue(item.IntValue); 202 break; 203 case AttributeItemType::TextAttribute: 204 Streamer.EmitBytes(item.StringValue.upper()); 205 Streamer.EmitIntValue(0, 1); // '\0' 206 break; 207 } 208 } 209 210 Contents.clear(); 211 } 212 }; 213 214} // end of anonymous namespace 215 216/// EmitDwarfRegOp - Emit dwarf register operation. 217void ARMAsmPrinter::EmitDwarfRegOp(const MachineLocation &MLoc, 218 bool Indirect) const { 219 const TargetRegisterInfo *RI = TM.getRegisterInfo(); 220 if (RI->getDwarfRegNum(MLoc.getReg(), false) != -1) { 221 AsmPrinter::EmitDwarfRegOp(MLoc, Indirect); 222 return; 223 } 224 assert(MLoc.isReg() && !Indirect && 225 "This doesn't support offset/indirection - implement it if needed"); 226 unsigned Reg = MLoc.getReg(); 227 if (Reg >= ARM::S0 && Reg <= ARM::S31) { 228 assert(ARM::S0 + 31 == ARM::S31 && "Unexpected ARM S register numbering"); 229 // S registers are described as bit-pieces of a register 230 // S[2x] = DW_OP_regx(256 + (x>>1)) DW_OP_bit_piece(32, 0) 231 // S[2x+1] = DW_OP_regx(256 + (x>>1)) DW_OP_bit_piece(32, 32) 232 233 unsigned SReg = Reg - ARM::S0; 234 bool odd = SReg & 0x1; 235 unsigned Rx = 256 + (SReg >> 1); 236 237 OutStreamer.AddComment("DW_OP_regx for S register"); 238 EmitInt8(dwarf::DW_OP_regx); 239 240 OutStreamer.AddComment(Twine(SReg)); 241 EmitULEB128(Rx); 242 243 if (odd) { 244 OutStreamer.AddComment("DW_OP_bit_piece 32 32"); 245 EmitInt8(dwarf::DW_OP_bit_piece); 246 EmitULEB128(32); 247 EmitULEB128(32); 248 } else { 249 OutStreamer.AddComment("DW_OP_bit_piece 32 0"); 250 EmitInt8(dwarf::DW_OP_bit_piece); 251 EmitULEB128(32); 252 EmitULEB128(0); 253 } 254 } else if (Reg >= ARM::Q0 && Reg <= ARM::Q15) { 255 assert(ARM::Q0 + 15 == ARM::Q15 && "Unexpected ARM Q register numbering"); 256 // Q registers Q0-Q15 are described by composing two D registers together. 257 // Qx = DW_OP_regx(256+2x) DW_OP_piece(8) DW_OP_regx(256+2x+1) 258 // DW_OP_piece(8) 259 260 unsigned QReg = Reg - ARM::Q0; 261 unsigned D1 = 256 + 2 * QReg; 262 unsigned D2 = D1 + 1; 263 264 OutStreamer.AddComment("DW_OP_regx for Q register: D1"); 265 EmitInt8(dwarf::DW_OP_regx); 266 EmitULEB128(D1); 267 OutStreamer.AddComment("DW_OP_piece 8"); 268 EmitInt8(dwarf::DW_OP_piece); 269 EmitULEB128(8); 270 271 OutStreamer.AddComment("DW_OP_regx for Q register: D2"); 272 EmitInt8(dwarf::DW_OP_regx); 273 EmitULEB128(D2); 274 OutStreamer.AddComment("DW_OP_piece 8"); 275 EmitInt8(dwarf::DW_OP_piece); 276 EmitULEB128(8); 277 } 278} 279 280void ARMAsmPrinter::EmitFunctionBodyEnd() { 281 // Make sure to terminate any constant pools that were at the end 282 // of the function. 283 if (!InConstantPool) 284 return; 285 InConstantPool = false; 286 OutStreamer.EmitDataRegion(MCDR_DataRegionEnd); 287} 288 289void ARMAsmPrinter::EmitFunctionEntryLabel() { 290 if (AFI->isThumbFunction()) { 291 OutStreamer.EmitAssemblerFlag(MCAF_Code16); 292 OutStreamer.EmitThumbFunc(CurrentFnSym); 293 } 294 295 OutStreamer.EmitLabel(CurrentFnSym); 296} 297 298void ARMAsmPrinter::EmitXXStructor(const Constant *CV) { 299 uint64_t Size = TM.getDataLayout()->getTypeAllocSize(CV->getType()); 300 assert(Size && "C++ constructor pointer had zero size!"); 301 302 const GlobalValue *GV = dyn_cast<GlobalValue>(CV->stripPointerCasts()); 303 assert(GV && "C++ constructor pointer was not a GlobalValue!"); 304 305 const MCExpr *E = MCSymbolRefExpr::Create(Mang->getSymbol(GV), 306 (Subtarget->isTargetDarwin() 307 ? MCSymbolRefExpr::VK_None 308 : MCSymbolRefExpr::VK_ARM_TARGET1), 309 OutContext); 310 311 OutStreamer.EmitValue(E, Size); 312} 313 314/// runOnMachineFunction - This uses the EmitInstruction() 315/// method to print assembly for each instruction. 316/// 317bool ARMAsmPrinter::runOnMachineFunction(MachineFunction &MF) { 318 AFI = MF.getInfo<ARMFunctionInfo>(); 319 MCP = MF.getConstantPool(); 320 321 return AsmPrinter::runOnMachineFunction(MF); 322} 323 324void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum, 325 raw_ostream &O, const char *Modifier) { 326 const MachineOperand &MO = MI->getOperand(OpNum); 327 unsigned TF = MO.getTargetFlags(); 328 329 switch (MO.getType()) { 330 default: llvm_unreachable("<unknown operand type>"); 331 case MachineOperand::MO_Register: { 332 unsigned Reg = MO.getReg(); 333 assert(TargetRegisterInfo::isPhysicalRegister(Reg)); 334 assert(!MO.getSubReg() && "Subregs should be eliminated!"); 335 if(ARM::GPRPairRegClass.contains(Reg)) { 336 const MachineFunction &MF = *MI->getParent()->getParent(); 337 const TargetRegisterInfo *TRI = MF.getTarget().getRegisterInfo(); 338 Reg = TRI->getSubReg(Reg, ARM::gsub_0); 339 } 340 O << ARMInstPrinter::getRegisterName(Reg); 341 break; 342 } 343 case MachineOperand::MO_Immediate: { 344 int64_t Imm = MO.getImm(); 345 O << '#'; 346 if ((Modifier && strcmp(Modifier, "lo16") == 0) || 347 (TF == ARMII::MO_LO16)) 348 O << ":lower16:"; 349 else if ((Modifier && strcmp(Modifier, "hi16") == 0) || 350 (TF == ARMII::MO_HI16)) 351 O << ":upper16:"; 352 O << Imm; 353 break; 354 } 355 case MachineOperand::MO_MachineBasicBlock: 356 O << *MO.getMBB()->getSymbol(); 357 return; 358 case MachineOperand::MO_GlobalAddress: { 359 const GlobalValue *GV = MO.getGlobal(); 360 if ((Modifier && strcmp(Modifier, "lo16") == 0) || 361 (TF & ARMII::MO_LO16)) 362 O << ":lower16:"; 363 else if ((Modifier && strcmp(Modifier, "hi16") == 0) || 364 (TF & ARMII::MO_HI16)) 365 O << ":upper16:"; 366 O << *Mang->getSymbol(GV); 367 368 printOffset(MO.getOffset(), O); 369 if (TF == ARMII::MO_PLT) 370 O << "(PLT)"; 371 break; 372 } 373 case MachineOperand::MO_ExternalSymbol: { 374 O << *GetExternalSymbolSymbol(MO.getSymbolName()); 375 if (TF == ARMII::MO_PLT) 376 O << "(PLT)"; 377 break; 378 } 379 case MachineOperand::MO_ConstantPoolIndex: 380 O << *GetCPISymbol(MO.getIndex()); 381 break; 382 case MachineOperand::MO_JumpTableIndex: 383 O << *GetJTISymbol(MO.getIndex()); 384 break; 385 } 386} 387 388//===--------------------------------------------------------------------===// 389 390MCSymbol *ARMAsmPrinter:: 391GetARMJTIPICJumpTableLabel2(unsigned uid, unsigned uid2) const { 392 SmallString<60> Name; 393 raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix() << "JTI" 394 << getFunctionNumber() << '_' << uid << '_' << uid2; 395 return OutContext.GetOrCreateSymbol(Name.str()); 396} 397 398 399MCSymbol *ARMAsmPrinter::GetARMSJLJEHLabel() const { 400 SmallString<60> Name; 401 raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix() << "SJLJEH" 402 << getFunctionNumber(); 403 return OutContext.GetOrCreateSymbol(Name.str()); 404} 405 406bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum, 407 unsigned AsmVariant, const char *ExtraCode, 408 raw_ostream &O) { 409 // Does this asm operand have a single letter operand modifier? 410 if (ExtraCode && ExtraCode[0]) { 411 if (ExtraCode[1] != 0) return true; // Unknown modifier. 412 413 switch (ExtraCode[0]) { 414 default: 415 // See if this is a generic print operand 416 return AsmPrinter::PrintAsmOperand(MI, OpNum, AsmVariant, ExtraCode, O); 417 case 'a': // Print as a memory address. 418 if (MI->getOperand(OpNum).isReg()) { 419 O << "[" 420 << ARMInstPrinter::getRegisterName(MI->getOperand(OpNum).getReg()) 421 << "]"; 422 return false; 423 } 424 // Fallthrough 425 case 'c': // Don't print "#" before an immediate operand. 426 if (!MI->getOperand(OpNum).isImm()) 427 return true; 428 O << MI->getOperand(OpNum).getImm(); 429 return false; 430 case 'P': // Print a VFP double precision register. 431 case 'q': // Print a NEON quad precision register. 432 printOperand(MI, OpNum, O); 433 return false; 434 case 'y': // Print a VFP single precision register as indexed double. 435 if (MI->getOperand(OpNum).isReg()) { 436 unsigned Reg = MI->getOperand(OpNum).getReg(); 437 const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo(); 438 // Find the 'd' register that has this 's' register as a sub-register, 439 // and determine the lane number. 440 for (MCSuperRegIterator SR(Reg, TRI); SR.isValid(); ++SR) { 441 if (!ARM::DPRRegClass.contains(*SR)) 442 continue; 443 bool Lane0 = TRI->getSubReg(*SR, ARM::ssub_0) == Reg; 444 O << ARMInstPrinter::getRegisterName(*SR) << (Lane0 ? "[0]" : "[1]"); 445 return false; 446 } 447 } 448 return true; 449 case 'B': // Bitwise inverse of integer or symbol without a preceding #. 450 if (!MI->getOperand(OpNum).isImm()) 451 return true; 452 O << ~(MI->getOperand(OpNum).getImm()); 453 return false; 454 case 'L': // The low 16 bits of an immediate constant. 455 if (!MI->getOperand(OpNum).isImm()) 456 return true; 457 O << (MI->getOperand(OpNum).getImm() & 0xffff); 458 return false; 459 case 'M': { // A register range suitable for LDM/STM. 460 if (!MI->getOperand(OpNum).isReg()) 461 return true; 462 const MachineOperand &MO = MI->getOperand(OpNum); 463 unsigned RegBegin = MO.getReg(); 464 // This takes advantage of the 2 operand-ness of ldm/stm and that we've 465 // already got the operands in registers that are operands to the 466 // inline asm statement. 467 O << "{"; 468 if (ARM::GPRPairRegClass.contains(RegBegin)) { 469 const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo(); 470 unsigned Reg0 = TRI->getSubReg(RegBegin, ARM::gsub_0); 471 O << ARMInstPrinter::getRegisterName(Reg0) << ", ";; 472 RegBegin = TRI->getSubReg(RegBegin, ARM::gsub_1); 473 } 474 O << ARMInstPrinter::getRegisterName(RegBegin); 475 476 // FIXME: The register allocator not only may not have given us the 477 // registers in sequence, but may not be in ascending registers. This 478 // will require changes in the register allocator that'll need to be 479 // propagated down here if the operands change. 480 unsigned RegOps = OpNum + 1; 481 while (MI->getOperand(RegOps).isReg()) { 482 O << ", " 483 << ARMInstPrinter::getRegisterName(MI->getOperand(RegOps).getReg()); 484 RegOps++; 485 } 486 487 O << "}"; 488 489 return false; 490 } 491 case 'R': // The most significant register of a pair. 492 case 'Q': { // The least significant register of a pair. 493 if (OpNum == 0) 494 return true; 495 const MachineOperand &FlagsOP = MI->getOperand(OpNum - 1); 496 if (!FlagsOP.isImm()) 497 return true; 498 unsigned Flags = FlagsOP.getImm(); 499 500 // This operand may not be the one that actually provides the register. If 501 // it's tied to a previous one then we should refer instead to that one 502 // for registers and their classes. 503 unsigned TiedIdx; 504 if (InlineAsm::isUseOperandTiedToDef(Flags, TiedIdx)) { 505 for (OpNum = InlineAsm::MIOp_FirstOperand; TiedIdx; --TiedIdx) { 506 unsigned OpFlags = MI->getOperand(OpNum).getImm(); 507 OpNum += InlineAsm::getNumOperandRegisters(OpFlags) + 1; 508 } 509 Flags = MI->getOperand(OpNum).getImm(); 510 511 // Later code expects OpNum to be pointing at the register rather than 512 // the flags. 513 OpNum += 1; 514 } 515 516 unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags); 517 unsigned RC; 518 InlineAsm::hasRegClassConstraint(Flags, RC); 519 if (RC == ARM::GPRPairRegClassID) { 520 if (NumVals != 1) 521 return true; 522 const MachineOperand &MO = MI->getOperand(OpNum); 523 if (!MO.isReg()) 524 return true; 525 const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo(); 526 unsigned Reg = TRI->getSubReg(MO.getReg(), ExtraCode[0] == 'Q' ? 527 ARM::gsub_0 : ARM::gsub_1); 528 O << ARMInstPrinter::getRegisterName(Reg); 529 return false; 530 } 531 if (NumVals != 2) 532 return true; 533 unsigned RegOp = ExtraCode[0] == 'Q' ? OpNum : OpNum + 1; 534 if (RegOp >= MI->getNumOperands()) 535 return true; 536 const MachineOperand &MO = MI->getOperand(RegOp); 537 if (!MO.isReg()) 538 return true; 539 unsigned Reg = MO.getReg(); 540 O << ARMInstPrinter::getRegisterName(Reg); 541 return false; 542 } 543 544 case 'e': // The low doubleword register of a NEON quad register. 545 case 'f': { // The high doubleword register of a NEON quad register. 546 if (!MI->getOperand(OpNum).isReg()) 547 return true; 548 unsigned Reg = MI->getOperand(OpNum).getReg(); 549 if (!ARM::QPRRegClass.contains(Reg)) 550 return true; 551 const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo(); 552 unsigned SubReg = TRI->getSubReg(Reg, ExtraCode[0] == 'e' ? 553 ARM::dsub_0 : ARM::dsub_1); 554 O << ARMInstPrinter::getRegisterName(SubReg); 555 return false; 556 } 557 558 // This modifier is not yet supported. 559 case 'h': // A range of VFP/NEON registers suitable for VLD1/VST1. 560 return true; 561 case 'H': { // The highest-numbered register of a pair. 562 const MachineOperand &MO = MI->getOperand(OpNum); 563 if (!MO.isReg()) 564 return true; 565 const MachineFunction &MF = *MI->getParent()->getParent(); 566 const TargetRegisterInfo *TRI = MF.getTarget().getRegisterInfo(); 567 unsigned Reg = MO.getReg(); 568 if(!ARM::GPRPairRegClass.contains(Reg)) 569 return false; 570 Reg = TRI->getSubReg(Reg, ARM::gsub_1); 571 O << ARMInstPrinter::getRegisterName(Reg); 572 return false; 573 } 574 } 575 } 576 577 printOperand(MI, OpNum, O); 578 return false; 579} 580 581bool ARMAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI, 582 unsigned OpNum, unsigned AsmVariant, 583 const char *ExtraCode, 584 raw_ostream &O) { 585 // Does this asm operand have a single letter operand modifier? 586 if (ExtraCode && ExtraCode[0]) { 587 if (ExtraCode[1] != 0) return true; // Unknown modifier. 588 589 switch (ExtraCode[0]) { 590 case 'A': // A memory operand for a VLD1/VST1 instruction. 591 default: return true; // Unknown modifier. 592 case 'm': // The base register of a memory operand. 593 if (!MI->getOperand(OpNum).isReg()) 594 return true; 595 O << ARMInstPrinter::getRegisterName(MI->getOperand(OpNum).getReg()); 596 return false; 597 } 598 } 599 600 const MachineOperand &MO = MI->getOperand(OpNum); 601 assert(MO.isReg() && "unexpected inline asm memory operand"); 602 O << "[" << ARMInstPrinter::getRegisterName(MO.getReg()) << "]"; 603 return false; 604} 605 606void ARMAsmPrinter::EmitStartOfAsmFile(Module &M) { 607 if (Subtarget->isTargetDarwin()) { 608 Reloc::Model RelocM = TM.getRelocationModel(); 609 if (RelocM == Reloc::PIC_ || RelocM == Reloc::DynamicNoPIC) { 610 // Declare all the text sections up front (before the DWARF sections 611 // emitted by AsmPrinter::doInitialization) so the assembler will keep 612 // them together at the beginning of the object file. This helps 613 // avoid out-of-range branches that are due a fundamental limitation of 614 // the way symbol offsets are encoded with the current Darwin ARM 615 // relocations. 616 const TargetLoweringObjectFileMachO &TLOFMacho = 617 static_cast<const TargetLoweringObjectFileMachO &>( 618 getObjFileLowering()); 619 620 // Collect the set of sections our functions will go into. 621 SetVector<const MCSection *, SmallVector<const MCSection *, 8>, 622 SmallPtrSet<const MCSection *, 8> > TextSections; 623 // Default text section comes first. 624 TextSections.insert(TLOFMacho.getTextSection()); 625 // Now any user defined text sections from function attributes. 626 for (Module::iterator F = M.begin(), e = M.end(); F != e; ++F) 627 if (!F->isDeclaration() && !F->hasAvailableExternallyLinkage()) 628 TextSections.insert(TLOFMacho.SectionForGlobal(F, Mang, TM)); 629 // Now the coalescable sections. 630 TextSections.insert(TLOFMacho.getTextCoalSection()); 631 TextSections.insert(TLOFMacho.getConstTextCoalSection()); 632 633 // Emit the sections in the .s file header to fix the order. 634 for (unsigned i = 0, e = TextSections.size(); i != e; ++i) 635 OutStreamer.SwitchSection(TextSections[i]); 636 637 if (RelocM == Reloc::DynamicNoPIC) { 638 const MCSection *sect = 639 OutContext.getMachOSection("__TEXT", "__symbol_stub4", 640 MCSectionMachO::S_SYMBOL_STUBS, 641 12, SectionKind::getText()); 642 OutStreamer.SwitchSection(sect); 643 } else { 644 const MCSection *sect = 645 OutContext.getMachOSection("__TEXT", "__picsymbolstub4", 646 MCSectionMachO::S_SYMBOL_STUBS, 647 16, SectionKind::getText()); 648 OutStreamer.SwitchSection(sect); 649 } 650 const MCSection *StaticInitSect = 651 OutContext.getMachOSection("__TEXT", "__StaticInit", 652 MCSectionMachO::S_REGULAR | 653 MCSectionMachO::S_ATTR_PURE_INSTRUCTIONS, 654 SectionKind::getText()); 655 OutStreamer.SwitchSection(StaticInitSect); 656 } 657 } 658 659 // Use unified assembler syntax. 660 OutStreamer.EmitAssemblerFlag(MCAF_SyntaxUnified); 661 662 // Emit ARM Build Attributes 663 if (Subtarget->isTargetELF()) 664 emitAttributes(); 665} 666 667 668void ARMAsmPrinter::EmitEndOfAsmFile(Module &M) { 669 if (Subtarget->isTargetDarwin()) { 670 // All darwin targets use mach-o. 671 const TargetLoweringObjectFileMachO &TLOFMacho = 672 static_cast<const TargetLoweringObjectFileMachO &>(getObjFileLowering()); 673 MachineModuleInfoMachO &MMIMacho = 674 MMI->getObjFileInfo<MachineModuleInfoMachO>(); 675 676 // Output non-lazy-pointers for external and common global variables. 677 MachineModuleInfoMachO::SymbolListTy Stubs = MMIMacho.GetGVStubList(); 678 679 if (!Stubs.empty()) { 680 // Switch with ".non_lazy_symbol_pointer" directive. 681 OutStreamer.SwitchSection(TLOFMacho.getNonLazySymbolPointerSection()); 682 EmitAlignment(2); 683 for (unsigned i = 0, e = Stubs.size(); i != e; ++i) { 684 // L_foo$stub: 685 OutStreamer.EmitLabel(Stubs[i].first); 686 // .indirect_symbol _foo 687 MachineModuleInfoImpl::StubValueTy &MCSym = Stubs[i].second; 688 OutStreamer.EmitSymbolAttribute(MCSym.getPointer(),MCSA_IndirectSymbol); 689 690 if (MCSym.getInt()) 691 // External to current translation unit. 692 OutStreamer.EmitIntValue(0, 4/*size*/); 693 else 694 // Internal to current translation unit. 695 // 696 // When we place the LSDA into the TEXT section, the type info 697 // pointers need to be indirect and pc-rel. We accomplish this by 698 // using NLPs; however, sometimes the types are local to the file. 699 // We need to fill in the value for the NLP in those cases. 700 OutStreamer.EmitValue(MCSymbolRefExpr::Create(MCSym.getPointer(), 701 OutContext), 702 4/*size*/); 703 } 704 705 Stubs.clear(); 706 OutStreamer.AddBlankLine(); 707 } 708 709 Stubs = MMIMacho.GetHiddenGVStubList(); 710 if (!Stubs.empty()) { 711 OutStreamer.SwitchSection(getObjFileLowering().getDataSection()); 712 EmitAlignment(2); 713 for (unsigned i = 0, e = Stubs.size(); i != e; ++i) { 714 // L_foo$stub: 715 OutStreamer.EmitLabel(Stubs[i].first); 716 // .long _foo 717 OutStreamer.EmitValue(MCSymbolRefExpr:: 718 Create(Stubs[i].second.getPointer(), 719 OutContext), 720 4/*size*/); 721 } 722 723 Stubs.clear(); 724 OutStreamer.AddBlankLine(); 725 } 726 727 // Funny Darwin hack: This flag tells the linker that no global symbols 728 // contain code that falls through to other global symbols (e.g. the obvious 729 // implementation of multiple entry points). If this doesn't occur, the 730 // linker can safely perform dead code stripping. Since LLVM never 731 // generates code that does this, it is always safe to set. 732 OutStreamer.EmitAssemblerFlag(MCAF_SubsectionsViaSymbols); 733 } 734} 735 736//===----------------------------------------------------------------------===// 737// Helper routines for EmitStartOfAsmFile() and EmitEndOfAsmFile() 738// FIXME: 739// The following seem like one-off assembler flags, but they actually need 740// to appear in the .ARM.attributes section in ELF. 741// Instead of subclassing the MCELFStreamer, we do the work here. 742 743static ARMBuildAttrs::CPUArch getArchForCPU(StringRef CPU, 744 const ARMSubtarget *Subtarget) { 745 if (CPU == "xscale") 746 return ARMBuildAttrs::v5TEJ; 747 748 if (Subtarget->hasV8Ops()) 749 return ARMBuildAttrs::v8; 750 else if (Subtarget->hasV7Ops()) { 751 if (Subtarget->isMClass() && Subtarget->hasThumb2DSP()) 752 return ARMBuildAttrs::v7E_M; 753 return ARMBuildAttrs::v7; 754 } else if (Subtarget->hasV6T2Ops()) 755 return ARMBuildAttrs::v6T2; 756 else if (Subtarget->hasV6MOps()) 757 return ARMBuildAttrs::v6S_M; 758 else if (Subtarget->hasV6Ops()) 759 return ARMBuildAttrs::v6; 760 else if (Subtarget->hasV5TEOps()) 761 return ARMBuildAttrs::v5TE; 762 else if (Subtarget->hasV5TOps()) 763 return ARMBuildAttrs::v5T; 764 else if (Subtarget->hasV4TOps()) 765 return ARMBuildAttrs::v4T; 766 else 767 return ARMBuildAttrs::v4; 768} 769 770void ARMAsmPrinter::emitAttributes() { 771 772 emitARMAttributeSection(); 773 774 /* GAS expect .fpu to be emitted, regardless of VFP build attribute */ 775 bool emitFPU = false; 776 AttributeEmitter *AttrEmitter; 777 if (OutStreamer.hasRawTextSupport()) { 778 AttrEmitter = new AsmAttributeEmitter(OutStreamer); 779 emitFPU = true; 780 } else { 781 MCObjectStreamer &O = static_cast<MCObjectStreamer&>(OutStreamer); 782 AttrEmitter = new ObjectAttributeEmitter(O); 783 } 784 785 AttrEmitter->MaybeSwitchVendor("aeabi"); 786 787 std::string CPUString = Subtarget->getCPUString(); 788 789 if (CPUString != "generic") 790 AttrEmitter->EmitTextAttribute(ARMBuildAttrs::CPU_name, CPUString); 791 792 AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, 793 getArchForCPU(CPUString, Subtarget)); 794 795 if (Subtarget->isAClass()) { 796 AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch_profile, 797 ARMBuildAttrs::ApplicationProfile); 798 } else if (Subtarget->isRClass()) { 799 AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch_profile, 800 ARMBuildAttrs::RealTimeProfile); 801 } else if (Subtarget->isMClass()){ 802 AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch_profile, 803 ARMBuildAttrs::MicroControllerProfile); 804 } 805 806 AttrEmitter->EmitAttribute(ARMBuildAttrs::ARM_ISA_use, Subtarget->hasARMOps() ? 807 ARMBuildAttrs::Allowed : ARMBuildAttrs::Not_Allowed); 808 if (Subtarget->isThumb1Only()) { 809 AttrEmitter->EmitAttribute(ARMBuildAttrs::THUMB_ISA_use, 810 ARMBuildAttrs::Allowed); 811 } else if (Subtarget->hasThumb2()) { 812 AttrEmitter->EmitAttribute(ARMBuildAttrs::THUMB_ISA_use, 813 ARMBuildAttrs::AllowThumb32); 814 } 815 816 if (Subtarget->hasNEON() && emitFPU) { 817 /* NEON is not exactly a VFP architecture, but GAS emit one of 818 * neon/neon-fp-armv8/neon-vfpv4/vfpv3/vfpv2 for .fpu parameters */ 819 if (Subtarget->hasFPARMv8()) { 820 if (Subtarget->hasCrypto()) 821 AttrEmitter->EmitTextAttribute(ARMBuildAttrs::Advanced_SIMD_arch, 822 "crypto-neon-fp-armv8"); 823 else 824 AttrEmitter->EmitTextAttribute(ARMBuildAttrs::Advanced_SIMD_arch, 825 "neon-fp-armv8"); 826 } 827 else if (Subtarget->hasVFP4()) 828 AttrEmitter->EmitTextAttribute(ARMBuildAttrs::Advanced_SIMD_arch, 829 "neon-vfpv4"); 830 else 831 AttrEmitter->EmitTextAttribute(ARMBuildAttrs::Advanced_SIMD_arch, "neon"); 832 /* If emitted for NEON, omit from VFP below, since you can have both 833 * NEON and VFP in build attributes but only one .fpu */ 834 emitFPU = false; 835 } 836 837 /* FPARMv8 + .fpu */ 838 if (Subtarget->hasFPARMv8()) { 839 AttrEmitter->EmitAttribute(ARMBuildAttrs::VFP_arch, 840 ARMBuildAttrs::AllowFPARMv8A); 841 if (emitFPU) 842 AttrEmitter->EmitTextAttribute(ARMBuildAttrs::VFP_arch, "fp-armv8"); 843 /* VFPv4 + .fpu */ 844 } else if (Subtarget->hasVFP4()) { 845 AttrEmitter->EmitAttribute(ARMBuildAttrs::VFP_arch, 846 Subtarget->isFPOnlySP() ? ARMBuildAttrs::AllowFPv4B : 847 ARMBuildAttrs::AllowFPv4A); 848 if (emitFPU) 849 AttrEmitter->EmitTextAttribute(ARMBuildAttrs::VFP_arch, "vfpv4"); 850 851 /* VFPv3 + .fpu */ 852 } else if (Subtarget->hasVFP3()) { 853 AttrEmitter->EmitAttribute(ARMBuildAttrs::VFP_arch, 854 Subtarget->isFPOnlySP() ? ARMBuildAttrs::AllowFPv3B : 855 ARMBuildAttrs::AllowFPv3A); 856 if (emitFPU) 857 AttrEmitter->EmitTextAttribute(ARMBuildAttrs::VFP_arch, "vfpv3"); 858 859 /* VFPv2 + .fpu */ 860 } else if (Subtarget->hasVFP2()) { 861 AttrEmitter->EmitAttribute(ARMBuildAttrs::VFP_arch, 862 ARMBuildAttrs::AllowFPv2); 863 if (emitFPU) 864 AttrEmitter->EmitTextAttribute(ARMBuildAttrs::VFP_arch, "vfpv2"); 865 } 866 867 /* TODO: ARMBuildAttrs::Allowed is not completely accurate, 868 * since NEON can have 1 (allowed) or 2 (MAC operations) */ 869 if (Subtarget->hasNEON()) { 870 if (Subtarget->hasV8Ops()) 871 AttrEmitter->EmitAttribute(ARMBuildAttrs::Advanced_SIMD_arch, 872 ARMBuildAttrs::AllowedNeonV8); 873 else 874 AttrEmitter->EmitAttribute(ARMBuildAttrs::Advanced_SIMD_arch, 875 ARMBuildAttrs::Allowed); 876 } 877 878 // Signal various FP modes. 879 if (!TM.Options.UnsafeFPMath) { 880 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_denormal, 881 ARMBuildAttrs::Allowed); 882 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_exceptions, 883 ARMBuildAttrs::Allowed); 884 } 885 886 if (TM.Options.NoInfsFPMath && TM.Options.NoNaNsFPMath) 887 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_number_model, 888 ARMBuildAttrs::Allowed); 889 else 890 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_number_model, 891 ARMBuildAttrs::AllowIEE754); 892 893 // FIXME: add more flags to ARMBuildAttrs.h 894 // 8-bytes alignment stuff. 895 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_align8_needed, 1); 896 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_align8_preserved, 1); 897 898 // Hard float. Use both S and D registers and conform to AAPCS-VFP. 899 if (Subtarget->isAAPCS_ABI() && TM.Options.FloatABIType == FloatABI::Hard) { 900 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_HardFP_use, 3); 901 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_VFP_args, 1); 902 } 903 // FIXME: Should we signal R9 usage? 904 905 if (Subtarget->hasDivide()) { 906 // Check if hardware divide is only available in thumb2 or ARM as well. 907 AttrEmitter->EmitAttribute(ARMBuildAttrs::DIV_use, 908 Subtarget->hasDivideInARMMode() ? ARMBuildAttrs::AllowDIVExt : 909 ARMBuildAttrs::AllowDIVIfExists); 910 } 911 912 AttrEmitter->Finish(); 913 delete AttrEmitter; 914} 915 916void ARMAsmPrinter::emitARMAttributeSection() { 917 // <format-version> 918 // [ <section-length> "vendor-name" 919 // [ <file-tag> <size> <attribute>* 920 // | <section-tag> <size> <section-number>* 0 <attribute>* 921 // | <symbol-tag> <size> <symbol-number>* 0 <attribute>* 922 // ]+ 923 // ]* 924 925 if (OutStreamer.hasRawTextSupport()) 926 return; 927 928 const ARMElfTargetObjectFile &TLOFELF = 929 static_cast<const ARMElfTargetObjectFile &> 930 (getObjFileLowering()); 931 932 OutStreamer.SwitchSection(TLOFELF.getAttributesSection()); 933 934 // Format version 935 OutStreamer.EmitIntValue(0x41, 1); 936} 937 938//===----------------------------------------------------------------------===// 939 940static MCSymbol *getPICLabel(const char *Prefix, unsigned FunctionNumber, 941 unsigned LabelId, MCContext &Ctx) { 942 943 MCSymbol *Label = Ctx.GetOrCreateSymbol(Twine(Prefix) 944 + "PC" + Twine(FunctionNumber) + "_" + Twine(LabelId)); 945 return Label; 946} 947 948static MCSymbolRefExpr::VariantKind 949getModifierVariantKind(ARMCP::ARMCPModifier Modifier) { 950 switch (Modifier) { 951 case ARMCP::no_modifier: return MCSymbolRefExpr::VK_None; 952 case ARMCP::TLSGD: return MCSymbolRefExpr::VK_ARM_TLSGD; 953 case ARMCP::TPOFF: return MCSymbolRefExpr::VK_ARM_TPOFF; 954 case ARMCP::GOTTPOFF: return MCSymbolRefExpr::VK_ARM_GOTTPOFF; 955 case ARMCP::GOT: return MCSymbolRefExpr::VK_ARM_GOT; 956 case ARMCP::GOTOFF: return MCSymbolRefExpr::VK_ARM_GOTOFF; 957 } 958 llvm_unreachable("Invalid ARMCPModifier!"); 959} 960 961MCSymbol *ARMAsmPrinter::GetARMGVSymbol(const GlobalValue *GV) { 962 bool isIndirect = Subtarget->isTargetDarwin() && 963 Subtarget->GVIsIndirectSymbol(GV, TM.getRelocationModel()); 964 if (!isIndirect) 965 return Mang->getSymbol(GV); 966 967 // FIXME: Remove this when Darwin transition to @GOT like syntax. 968 MCSymbol *MCSym = GetSymbolWithGlobalValueBase(GV, "$non_lazy_ptr"); 969 MachineModuleInfoMachO &MMIMachO = 970 MMI->getObjFileInfo<MachineModuleInfoMachO>(); 971 MachineModuleInfoImpl::StubValueTy &StubSym = 972 GV->hasHiddenVisibility() ? MMIMachO.getHiddenGVStubEntry(MCSym) : 973 MMIMachO.getGVStubEntry(MCSym); 974 if (StubSym.getPointer() == 0) 975 StubSym = MachineModuleInfoImpl:: 976 StubValueTy(Mang->getSymbol(GV), !GV->hasInternalLinkage()); 977 return MCSym; 978} 979 980void ARMAsmPrinter:: 981EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) { 982 int Size = TM.getDataLayout()->getTypeAllocSize(MCPV->getType()); 983 984 ARMConstantPoolValue *ACPV = static_cast<ARMConstantPoolValue*>(MCPV); 985 986 MCSymbol *MCSym; 987 if (ACPV->isLSDA()) { 988 SmallString<128> Str; 989 raw_svector_ostream OS(Str); 990 OS << MAI->getPrivateGlobalPrefix() << "_LSDA_" << getFunctionNumber(); 991 MCSym = OutContext.GetOrCreateSymbol(OS.str()); 992 } else if (ACPV->isBlockAddress()) { 993 const BlockAddress *BA = 994 cast<ARMConstantPoolConstant>(ACPV)->getBlockAddress(); 995 MCSym = GetBlockAddressSymbol(BA); 996 } else if (ACPV->isGlobalValue()) { 997 const GlobalValue *GV = cast<ARMConstantPoolConstant>(ACPV)->getGV(); 998 MCSym = GetARMGVSymbol(GV); 999 } else if (ACPV->isMachineBasicBlock()) { 1000 const MachineBasicBlock *MBB = cast<ARMConstantPoolMBB>(ACPV)->getMBB(); 1001 MCSym = MBB->getSymbol(); 1002 } else { 1003 assert(ACPV->isExtSymbol() && "unrecognized constant pool value"); 1004 const char *Sym = cast<ARMConstantPoolSymbol>(ACPV)->getSymbol(); 1005 MCSym = GetExternalSymbolSymbol(Sym); 1006 } 1007 1008 // Create an MCSymbol for the reference. 1009 const MCExpr *Expr = 1010 MCSymbolRefExpr::Create(MCSym, getModifierVariantKind(ACPV->getModifier()), 1011 OutContext); 1012 1013 if (ACPV->getPCAdjustment()) { 1014 MCSymbol *PCLabel = getPICLabel(MAI->getPrivateGlobalPrefix(), 1015 getFunctionNumber(), 1016 ACPV->getLabelId(), 1017 OutContext); 1018 const MCExpr *PCRelExpr = MCSymbolRefExpr::Create(PCLabel, OutContext); 1019 PCRelExpr = 1020 MCBinaryExpr::CreateAdd(PCRelExpr, 1021 MCConstantExpr::Create(ACPV->getPCAdjustment(), 1022 OutContext), 1023 OutContext); 1024 if (ACPV->mustAddCurrentAddress()) { 1025 // We want "(<expr> - .)", but MC doesn't have a concept of the '.' 1026 // label, so just emit a local label end reference that instead. 1027 MCSymbol *DotSym = OutContext.CreateTempSymbol(); 1028 OutStreamer.EmitLabel(DotSym); 1029 const MCExpr *DotExpr = MCSymbolRefExpr::Create(DotSym, OutContext); 1030 PCRelExpr = MCBinaryExpr::CreateSub(PCRelExpr, DotExpr, OutContext); 1031 } 1032 Expr = MCBinaryExpr::CreateSub(Expr, PCRelExpr, OutContext); 1033 } 1034 OutStreamer.EmitValue(Expr, Size); 1035} 1036 1037void ARMAsmPrinter::EmitJumpTable(const MachineInstr *MI) { 1038 unsigned Opcode = MI->getOpcode(); 1039 int OpNum = 1; 1040 if (Opcode == ARM::BR_JTadd) 1041 OpNum = 2; 1042 else if (Opcode == ARM::BR_JTm) 1043 OpNum = 3; 1044 1045 const MachineOperand &MO1 = MI->getOperand(OpNum); 1046 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id 1047 unsigned JTI = MO1.getIndex(); 1048 1049 // Emit a label for the jump table. 1050 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm()); 1051 OutStreamer.EmitLabel(JTISymbol); 1052 1053 // Mark the jump table as data-in-code. 1054 OutStreamer.EmitDataRegion(MCDR_DataRegionJT32); 1055 1056 // Emit each entry of the table. 1057 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo(); 1058 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables(); 1059 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs; 1060 1061 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) { 1062 MachineBasicBlock *MBB = JTBBs[i]; 1063 // Construct an MCExpr for the entry. We want a value of the form: 1064 // (BasicBlockAddr - TableBeginAddr) 1065 // 1066 // For example, a table with entries jumping to basic blocks BB0 and BB1 1067 // would look like: 1068 // LJTI_0_0: 1069 // .word (LBB0 - LJTI_0_0) 1070 // .word (LBB1 - LJTI_0_0) 1071 const MCExpr *Expr = MCSymbolRefExpr::Create(MBB->getSymbol(), OutContext); 1072 1073 if (TM.getRelocationModel() == Reloc::PIC_) 1074 Expr = MCBinaryExpr::CreateSub(Expr, MCSymbolRefExpr::Create(JTISymbol, 1075 OutContext), 1076 OutContext); 1077 // If we're generating a table of Thumb addresses in static relocation 1078 // model, we need to add one to keep interworking correctly. 1079 else if (AFI->isThumbFunction()) 1080 Expr = MCBinaryExpr::CreateAdd(Expr, MCConstantExpr::Create(1,OutContext), 1081 OutContext); 1082 OutStreamer.EmitValue(Expr, 4); 1083 } 1084 // Mark the end of jump table data-in-code region. 1085 OutStreamer.EmitDataRegion(MCDR_DataRegionEnd); 1086} 1087 1088void ARMAsmPrinter::EmitJump2Table(const MachineInstr *MI) { 1089 unsigned Opcode = MI->getOpcode(); 1090 int OpNum = (Opcode == ARM::t2BR_JT) ? 2 : 1; 1091 const MachineOperand &MO1 = MI->getOperand(OpNum); 1092 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id 1093 unsigned JTI = MO1.getIndex(); 1094 1095 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm()); 1096 OutStreamer.EmitLabel(JTISymbol); 1097 1098 // Emit each entry of the table. 1099 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo(); 1100 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables(); 1101 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs; 1102 unsigned OffsetWidth = 4; 1103 if (MI->getOpcode() == ARM::t2TBB_JT) { 1104 OffsetWidth = 1; 1105 // Mark the jump table as data-in-code. 1106 OutStreamer.EmitDataRegion(MCDR_DataRegionJT8); 1107 } else if (MI->getOpcode() == ARM::t2TBH_JT) { 1108 OffsetWidth = 2; 1109 // Mark the jump table as data-in-code. 1110 OutStreamer.EmitDataRegion(MCDR_DataRegionJT16); 1111 } 1112 1113 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) { 1114 MachineBasicBlock *MBB = JTBBs[i]; 1115 const MCExpr *MBBSymbolExpr = MCSymbolRefExpr::Create(MBB->getSymbol(), 1116 OutContext); 1117 // If this isn't a TBB or TBH, the entries are direct branch instructions. 1118 if (OffsetWidth == 4) { 1119 OutStreamer.EmitInstruction(MCInstBuilder(ARM::t2B) 1120 .addExpr(MBBSymbolExpr) 1121 .addImm(ARMCC::AL) 1122 .addReg(0)); 1123 continue; 1124 } 1125 // Otherwise it's an offset from the dispatch instruction. Construct an 1126 // MCExpr for the entry. We want a value of the form: 1127 // (BasicBlockAddr - TableBeginAddr) / 2 1128 // 1129 // For example, a TBB table with entries jumping to basic blocks BB0 and BB1 1130 // would look like: 1131 // LJTI_0_0: 1132 // .byte (LBB0 - LJTI_0_0) / 2 1133 // .byte (LBB1 - LJTI_0_0) / 2 1134 const MCExpr *Expr = 1135 MCBinaryExpr::CreateSub(MBBSymbolExpr, 1136 MCSymbolRefExpr::Create(JTISymbol, OutContext), 1137 OutContext); 1138 Expr = MCBinaryExpr::CreateDiv(Expr, MCConstantExpr::Create(2, OutContext), 1139 OutContext); 1140 OutStreamer.EmitValue(Expr, OffsetWidth); 1141 } 1142 // Mark the end of jump table data-in-code region. 32-bit offsets use 1143 // actual branch instructions here, so we don't mark those as a data-region 1144 // at all. 1145 if (OffsetWidth != 4) 1146 OutStreamer.EmitDataRegion(MCDR_DataRegionEnd); 1147} 1148 1149void ARMAsmPrinter::EmitUnwindingInstruction(const MachineInstr *MI) { 1150 assert(MI->getFlag(MachineInstr::FrameSetup) && 1151 "Only instruction which are involved into frame setup code are allowed"); 1152 1153 MCTargetStreamer &TS = OutStreamer.getTargetStreamer(); 1154 ARMTargetStreamer &ATS = static_cast<ARMTargetStreamer &>(TS); 1155 const MachineFunction &MF = *MI->getParent()->getParent(); 1156 const TargetRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo(); 1157 const ARMFunctionInfo &AFI = *MF.getInfo<ARMFunctionInfo>(); 1158 1159 unsigned FramePtr = RegInfo->getFrameRegister(MF); 1160 unsigned Opc = MI->getOpcode(); 1161 unsigned SrcReg, DstReg; 1162 1163 if (Opc == ARM::tPUSH || Opc == ARM::tLDRpci) { 1164 // Two special cases: 1165 // 1) tPUSH does not have src/dst regs. 1166 // 2) for Thumb1 code we sometimes materialize the constant via constpool 1167 // load. Yes, this is pretty fragile, but for now I don't see better 1168 // way... :( 1169 SrcReg = DstReg = ARM::SP; 1170 } else { 1171 SrcReg = MI->getOperand(1).getReg(); 1172 DstReg = MI->getOperand(0).getReg(); 1173 } 1174 1175 // Try to figure out the unwinding opcode out of src / dst regs. 1176 if (MI->mayStore()) { 1177 // Register saves. 1178 assert(DstReg == ARM::SP && 1179 "Only stack pointer as a destination reg is supported"); 1180 1181 SmallVector<unsigned, 4> RegList; 1182 // Skip src & dst reg, and pred ops. 1183 unsigned StartOp = 2 + 2; 1184 // Use all the operands. 1185 unsigned NumOffset = 0; 1186 1187 switch (Opc) { 1188 default: 1189 MI->dump(); 1190 llvm_unreachable("Unsupported opcode for unwinding information"); 1191 case ARM::tPUSH: 1192 // Special case here: no src & dst reg, but two extra imp ops. 1193 StartOp = 2; NumOffset = 2; 1194 case ARM::STMDB_UPD: 1195 case ARM::t2STMDB_UPD: 1196 case ARM::VSTMDDB_UPD: 1197 assert(SrcReg == ARM::SP && 1198 "Only stack pointer as a source reg is supported"); 1199 for (unsigned i = StartOp, NumOps = MI->getNumOperands() - NumOffset; 1200 i != NumOps; ++i) { 1201 const MachineOperand &MO = MI->getOperand(i); 1202 // Actually, there should never be any impdef stuff here. Skip it 1203 // temporary to workaround PR11902. 1204 if (MO.isImplicit()) 1205 continue; 1206 RegList.push_back(MO.getReg()); 1207 } 1208 break; 1209 case ARM::STR_PRE_IMM: 1210 case ARM::STR_PRE_REG: 1211 case ARM::t2STR_PRE: 1212 assert(MI->getOperand(2).getReg() == ARM::SP && 1213 "Only stack pointer as a source reg is supported"); 1214 RegList.push_back(SrcReg); 1215 break; 1216 } 1217 ATS.emitRegSave(RegList, Opc == ARM::VSTMDDB_UPD); 1218 } else { 1219 // Changes of stack / frame pointer. 1220 if (SrcReg == ARM::SP) { 1221 int64_t Offset = 0; 1222 switch (Opc) { 1223 default: 1224 MI->dump(); 1225 llvm_unreachable("Unsupported opcode for unwinding information"); 1226 case ARM::MOVr: 1227 case ARM::tMOVr: 1228 Offset = 0; 1229 break; 1230 case ARM::ADDri: 1231 Offset = -MI->getOperand(2).getImm(); 1232 break; 1233 case ARM::SUBri: 1234 case ARM::t2SUBri: 1235 Offset = MI->getOperand(2).getImm(); 1236 break; 1237 case ARM::tSUBspi: 1238 Offset = MI->getOperand(2).getImm()*4; 1239 break; 1240 case ARM::tADDspi: 1241 case ARM::tADDrSPi: 1242 Offset = -MI->getOperand(2).getImm()*4; 1243 break; 1244 case ARM::tLDRpci: { 1245 // Grab the constpool index and check, whether it corresponds to 1246 // original or cloned constpool entry. 1247 unsigned CPI = MI->getOperand(1).getIndex(); 1248 const MachineConstantPool *MCP = MF.getConstantPool(); 1249 if (CPI >= MCP->getConstants().size()) 1250 CPI = AFI.getOriginalCPIdx(CPI); 1251 assert(CPI != -1U && "Invalid constpool index"); 1252 1253 // Derive the actual offset. 1254 const MachineConstantPoolEntry &CPE = MCP->getConstants()[CPI]; 1255 assert(!CPE.isMachineConstantPoolEntry() && "Invalid constpool entry"); 1256 // FIXME: Check for user, it should be "add" instruction! 1257 Offset = -cast<ConstantInt>(CPE.Val.ConstVal)->getSExtValue(); 1258 break; 1259 } 1260 } 1261 1262 if (DstReg == FramePtr && FramePtr != ARM::SP) 1263 // Set-up of the frame pointer. Positive values correspond to "add" 1264 // instruction. 1265 ATS.emitSetFP(FramePtr, ARM::SP, -Offset); 1266 else if (DstReg == ARM::SP) { 1267 // Change of SP by an offset. Positive values correspond to "sub" 1268 // instruction. 1269 ATS.emitPad(Offset); 1270 } else { 1271 MI->dump(); 1272 llvm_unreachable("Unsupported opcode for unwinding information"); 1273 } 1274 } else if (DstReg == ARM::SP) { 1275 // FIXME: .movsp goes here 1276 MI->dump(); 1277 llvm_unreachable("Unsupported opcode for unwinding information"); 1278 } 1279 else { 1280 MI->dump(); 1281 llvm_unreachable("Unsupported opcode for unwinding information"); 1282 } 1283 } 1284} 1285 1286extern cl::opt<bool> EnableARMEHABI; 1287 1288// Simple pseudo-instructions have their lowering (with expansion to real 1289// instructions) auto-generated. 1290#include "ARMGenMCPseudoLowering.inc" 1291 1292void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) { 1293 // If we just ended a constant pool, mark it as such. 1294 if (InConstantPool && MI->getOpcode() != ARM::CONSTPOOL_ENTRY) { 1295 OutStreamer.EmitDataRegion(MCDR_DataRegionEnd); 1296 InConstantPool = false; 1297 } 1298 1299 // Emit unwinding stuff for frame-related instructions 1300 if (EnableARMEHABI && MI->getFlag(MachineInstr::FrameSetup)) 1301 EmitUnwindingInstruction(MI); 1302 1303 // Do any auto-generated pseudo lowerings. 1304 if (emitPseudoExpansionLowering(OutStreamer, MI)) 1305 return; 1306 1307 assert(!convertAddSubFlagsOpcode(MI->getOpcode()) && 1308 "Pseudo flag setting opcode should be expanded early"); 1309 1310 // Check for manual lowerings. 1311 unsigned Opc = MI->getOpcode(); 1312 switch (Opc) { 1313 case ARM::t2MOVi32imm: llvm_unreachable("Should be lowered by thumb2it pass"); 1314 case ARM::DBG_VALUE: llvm_unreachable("Should be handled by generic printing"); 1315 case ARM::LEApcrel: 1316 case ARM::tLEApcrel: 1317 case ARM::t2LEApcrel: { 1318 // FIXME: Need to also handle globals and externals 1319 MCSymbol *CPISymbol = GetCPISymbol(MI->getOperand(1).getIndex()); 1320 OutStreamer.EmitInstruction(MCInstBuilder(MI->getOpcode() == 1321 ARM::t2LEApcrel ? ARM::t2ADR 1322 : (MI->getOpcode() == ARM::tLEApcrel ? ARM::tADR 1323 : ARM::ADR)) 1324 .addReg(MI->getOperand(0).getReg()) 1325 .addExpr(MCSymbolRefExpr::Create(CPISymbol, OutContext)) 1326 // Add predicate operands. 1327 .addImm(MI->getOperand(2).getImm()) 1328 .addReg(MI->getOperand(3).getReg())); 1329 return; 1330 } 1331 case ARM::LEApcrelJT: 1332 case ARM::tLEApcrelJT: 1333 case ARM::t2LEApcrelJT: { 1334 MCSymbol *JTIPICSymbol = 1335 GetARMJTIPICJumpTableLabel2(MI->getOperand(1).getIndex(), 1336 MI->getOperand(2).getImm()); 1337 OutStreamer.EmitInstruction(MCInstBuilder(MI->getOpcode() == 1338 ARM::t2LEApcrelJT ? ARM::t2ADR 1339 : (MI->getOpcode() == ARM::tLEApcrelJT ? ARM::tADR 1340 : ARM::ADR)) 1341 .addReg(MI->getOperand(0).getReg()) 1342 .addExpr(MCSymbolRefExpr::Create(JTIPICSymbol, OutContext)) 1343 // Add predicate operands. 1344 .addImm(MI->getOperand(3).getImm()) 1345 .addReg(MI->getOperand(4).getReg())); 1346 return; 1347 } 1348 // Darwin call instructions are just normal call instructions with different 1349 // clobber semantics (they clobber R9). 1350 case ARM::BX_CALL: { 1351 OutStreamer.EmitInstruction(MCInstBuilder(ARM::MOVr) 1352 .addReg(ARM::LR) 1353 .addReg(ARM::PC) 1354 // Add predicate operands. 1355 .addImm(ARMCC::AL) 1356 .addReg(0) 1357 // Add 's' bit operand (always reg0 for this) 1358 .addReg(0)); 1359 1360 OutStreamer.EmitInstruction(MCInstBuilder(ARM::BX) 1361 .addReg(MI->getOperand(0).getReg())); 1362 return; 1363 } 1364 case ARM::tBX_CALL: { 1365 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tMOVr) 1366 .addReg(ARM::LR) 1367 .addReg(ARM::PC) 1368 // Add predicate operands. 1369 .addImm(ARMCC::AL) 1370 .addReg(0)); 1371 1372 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tBX) 1373 .addReg(MI->getOperand(0).getReg()) 1374 // Add predicate operands. 1375 .addImm(ARMCC::AL) 1376 .addReg(0)); 1377 return; 1378 } 1379 case ARM::BMOVPCRX_CALL: { 1380 OutStreamer.EmitInstruction(MCInstBuilder(ARM::MOVr) 1381 .addReg(ARM::LR) 1382 .addReg(ARM::PC) 1383 // Add predicate operands. 1384 .addImm(ARMCC::AL) 1385 .addReg(0) 1386 // Add 's' bit operand (always reg0 for this) 1387 .addReg(0)); 1388 1389 OutStreamer.EmitInstruction(MCInstBuilder(ARM::MOVr) 1390 .addReg(ARM::PC) 1391 .addReg(MI->getOperand(0).getReg()) 1392 // Add predicate operands. 1393 .addImm(ARMCC::AL) 1394 .addReg(0) 1395 // Add 's' bit operand (always reg0 for this) 1396 .addReg(0)); 1397 return; 1398 } 1399 case ARM::BMOVPCB_CALL: { 1400 OutStreamer.EmitInstruction(MCInstBuilder(ARM::MOVr) 1401 .addReg(ARM::LR) 1402 .addReg(ARM::PC) 1403 // Add predicate operands. 1404 .addImm(ARMCC::AL) 1405 .addReg(0) 1406 // Add 's' bit operand (always reg0 for this) 1407 .addReg(0)); 1408 1409 const GlobalValue *GV = MI->getOperand(0).getGlobal(); 1410 MCSymbol *GVSym = Mang->getSymbol(GV); 1411 const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext); 1412 OutStreamer.EmitInstruction(MCInstBuilder(ARM::Bcc) 1413 .addExpr(GVSymExpr) 1414 // Add predicate operands. 1415 .addImm(ARMCC::AL) 1416 .addReg(0)); 1417 return; 1418 } 1419 case ARM::MOVi16_ga_pcrel: 1420 case ARM::t2MOVi16_ga_pcrel: { 1421 MCInst TmpInst; 1422 TmpInst.setOpcode(Opc == ARM::MOVi16_ga_pcrel? ARM::MOVi16 : ARM::t2MOVi16); 1423 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg())); 1424 1425 unsigned TF = MI->getOperand(1).getTargetFlags(); 1426 bool isPIC = TF == ARMII::MO_LO16_NONLAZY_PIC; 1427 const GlobalValue *GV = MI->getOperand(1).getGlobal(); 1428 MCSymbol *GVSym = GetARMGVSymbol(GV); 1429 const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext); 1430 if (isPIC) { 1431 MCSymbol *LabelSym = getPICLabel(MAI->getPrivateGlobalPrefix(), 1432 getFunctionNumber(), 1433 MI->getOperand(2).getImm(), OutContext); 1434 const MCExpr *LabelSymExpr= MCSymbolRefExpr::Create(LabelSym, OutContext); 1435 unsigned PCAdj = (Opc == ARM::MOVi16_ga_pcrel) ? 8 : 4; 1436 const MCExpr *PCRelExpr = 1437 ARMMCExpr::CreateLower16(MCBinaryExpr::CreateSub(GVSymExpr, 1438 MCBinaryExpr::CreateAdd(LabelSymExpr, 1439 MCConstantExpr::Create(PCAdj, OutContext), 1440 OutContext), OutContext), OutContext); 1441 TmpInst.addOperand(MCOperand::CreateExpr(PCRelExpr)); 1442 } else { 1443 const MCExpr *RefExpr= ARMMCExpr::CreateLower16(GVSymExpr, OutContext); 1444 TmpInst.addOperand(MCOperand::CreateExpr(RefExpr)); 1445 } 1446 1447 // Add predicate operands. 1448 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL)); 1449 TmpInst.addOperand(MCOperand::CreateReg(0)); 1450 // Add 's' bit operand (always reg0 for this) 1451 TmpInst.addOperand(MCOperand::CreateReg(0)); 1452 OutStreamer.EmitInstruction(TmpInst); 1453 return; 1454 } 1455 case ARM::MOVTi16_ga_pcrel: 1456 case ARM::t2MOVTi16_ga_pcrel: { 1457 MCInst TmpInst; 1458 TmpInst.setOpcode(Opc == ARM::MOVTi16_ga_pcrel 1459 ? ARM::MOVTi16 : ARM::t2MOVTi16); 1460 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg())); 1461 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg())); 1462 1463 unsigned TF = MI->getOperand(2).getTargetFlags(); 1464 bool isPIC = TF == ARMII::MO_HI16_NONLAZY_PIC; 1465 const GlobalValue *GV = MI->getOperand(2).getGlobal(); 1466 MCSymbol *GVSym = GetARMGVSymbol(GV); 1467 const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext); 1468 if (isPIC) { 1469 MCSymbol *LabelSym = getPICLabel(MAI->getPrivateGlobalPrefix(), 1470 getFunctionNumber(), 1471 MI->getOperand(3).getImm(), OutContext); 1472 const MCExpr *LabelSymExpr= MCSymbolRefExpr::Create(LabelSym, OutContext); 1473 unsigned PCAdj = (Opc == ARM::MOVTi16_ga_pcrel) ? 8 : 4; 1474 const MCExpr *PCRelExpr = 1475 ARMMCExpr::CreateUpper16(MCBinaryExpr::CreateSub(GVSymExpr, 1476 MCBinaryExpr::CreateAdd(LabelSymExpr, 1477 MCConstantExpr::Create(PCAdj, OutContext), 1478 OutContext), OutContext), OutContext); 1479 TmpInst.addOperand(MCOperand::CreateExpr(PCRelExpr)); 1480 } else { 1481 const MCExpr *RefExpr= ARMMCExpr::CreateUpper16(GVSymExpr, OutContext); 1482 TmpInst.addOperand(MCOperand::CreateExpr(RefExpr)); 1483 } 1484 // Add predicate operands. 1485 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL)); 1486 TmpInst.addOperand(MCOperand::CreateReg(0)); 1487 // Add 's' bit operand (always reg0 for this) 1488 TmpInst.addOperand(MCOperand::CreateReg(0)); 1489 OutStreamer.EmitInstruction(TmpInst); 1490 return; 1491 } 1492 case ARM::tPICADD: { 1493 // This is a pseudo op for a label + instruction sequence, which looks like: 1494 // LPC0: 1495 // add r0, pc 1496 // This adds the address of LPC0 to r0. 1497 1498 // Emit the label. 1499 OutStreamer.EmitLabel(getPICLabel(MAI->getPrivateGlobalPrefix(), 1500 getFunctionNumber(), MI->getOperand(2).getImm(), 1501 OutContext)); 1502 1503 // Form and emit the add. 1504 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tADDhirr) 1505 .addReg(MI->getOperand(0).getReg()) 1506 .addReg(MI->getOperand(0).getReg()) 1507 .addReg(ARM::PC) 1508 // Add predicate operands. 1509 .addImm(ARMCC::AL) 1510 .addReg(0)); 1511 return; 1512 } 1513 case ARM::PICADD: { 1514 // This is a pseudo op for a label + instruction sequence, which looks like: 1515 // LPC0: 1516 // add r0, pc, r0 1517 // This adds the address of LPC0 to r0. 1518 1519 // Emit the label. 1520 OutStreamer.EmitLabel(getPICLabel(MAI->getPrivateGlobalPrefix(), 1521 getFunctionNumber(), MI->getOperand(2).getImm(), 1522 OutContext)); 1523 1524 // Form and emit the add. 1525 OutStreamer.EmitInstruction(MCInstBuilder(ARM::ADDrr) 1526 .addReg(MI->getOperand(0).getReg()) 1527 .addReg(ARM::PC) 1528 .addReg(MI->getOperand(1).getReg()) 1529 // Add predicate operands. 1530 .addImm(MI->getOperand(3).getImm()) 1531 .addReg(MI->getOperand(4).getReg()) 1532 // Add 's' bit operand (always reg0 for this) 1533 .addReg(0)); 1534 return; 1535 } 1536 case ARM::PICSTR: 1537 case ARM::PICSTRB: 1538 case ARM::PICSTRH: 1539 case ARM::PICLDR: 1540 case ARM::PICLDRB: 1541 case ARM::PICLDRH: 1542 case ARM::PICLDRSB: 1543 case ARM::PICLDRSH: { 1544 // This is a pseudo op for a label + instruction sequence, which looks like: 1545 // LPC0: 1546 // OP r0, [pc, r0] 1547 // The LCP0 label is referenced by a constant pool entry in order to get 1548 // a PC-relative address at the ldr instruction. 1549 1550 // Emit the label. 1551 OutStreamer.EmitLabel(getPICLabel(MAI->getPrivateGlobalPrefix(), 1552 getFunctionNumber(), MI->getOperand(2).getImm(), 1553 OutContext)); 1554 1555 // Form and emit the load 1556 unsigned Opcode; 1557 switch (MI->getOpcode()) { 1558 default: 1559 llvm_unreachable("Unexpected opcode!"); 1560 case ARM::PICSTR: Opcode = ARM::STRrs; break; 1561 case ARM::PICSTRB: Opcode = ARM::STRBrs; break; 1562 case ARM::PICSTRH: Opcode = ARM::STRH; break; 1563 case ARM::PICLDR: Opcode = ARM::LDRrs; break; 1564 case ARM::PICLDRB: Opcode = ARM::LDRBrs; break; 1565 case ARM::PICLDRH: Opcode = ARM::LDRH; break; 1566 case ARM::PICLDRSB: Opcode = ARM::LDRSB; break; 1567 case ARM::PICLDRSH: Opcode = ARM::LDRSH; break; 1568 } 1569 OutStreamer.EmitInstruction(MCInstBuilder(Opcode) 1570 .addReg(MI->getOperand(0).getReg()) 1571 .addReg(ARM::PC) 1572 .addReg(MI->getOperand(1).getReg()) 1573 .addImm(0) 1574 // Add predicate operands. 1575 .addImm(MI->getOperand(3).getImm()) 1576 .addReg(MI->getOperand(4).getReg())); 1577 1578 return; 1579 } 1580 case ARM::CONSTPOOL_ENTRY: { 1581 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool 1582 /// in the function. The first operand is the ID# for this instruction, the 1583 /// second is the index into the MachineConstantPool that this is, the third 1584 /// is the size in bytes of this constant pool entry. 1585 /// The required alignment is specified on the basic block holding this MI. 1586 unsigned LabelId = (unsigned)MI->getOperand(0).getImm(); 1587 unsigned CPIdx = (unsigned)MI->getOperand(1).getIndex(); 1588 1589 // If this is the first entry of the pool, mark it. 1590 if (!InConstantPool) { 1591 OutStreamer.EmitDataRegion(MCDR_DataRegion); 1592 InConstantPool = true; 1593 } 1594 1595 OutStreamer.EmitLabel(GetCPISymbol(LabelId)); 1596 1597 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPIdx]; 1598 if (MCPE.isMachineConstantPoolEntry()) 1599 EmitMachineConstantPoolValue(MCPE.Val.MachineCPVal); 1600 else 1601 EmitGlobalConstant(MCPE.Val.ConstVal); 1602 return; 1603 } 1604 case ARM::t2BR_JT: { 1605 // Lower and emit the instruction itself, then the jump table following it. 1606 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tMOVr) 1607 .addReg(ARM::PC) 1608 .addReg(MI->getOperand(0).getReg()) 1609 // Add predicate operands. 1610 .addImm(ARMCC::AL) 1611 .addReg(0)); 1612 1613 // Output the data for the jump table itself 1614 EmitJump2Table(MI); 1615 return; 1616 } 1617 case ARM::t2TBB_JT: { 1618 // Lower and emit the instruction itself, then the jump table following it. 1619 OutStreamer.EmitInstruction(MCInstBuilder(ARM::t2TBB) 1620 .addReg(ARM::PC) 1621 .addReg(MI->getOperand(0).getReg()) 1622 // Add predicate operands. 1623 .addImm(ARMCC::AL) 1624 .addReg(0)); 1625 1626 // Output the data for the jump table itself 1627 EmitJump2Table(MI); 1628 // Make sure the next instruction is 2-byte aligned. 1629 EmitAlignment(1); 1630 return; 1631 } 1632 case ARM::t2TBH_JT: { 1633 // Lower and emit the instruction itself, then the jump table following it. 1634 OutStreamer.EmitInstruction(MCInstBuilder(ARM::t2TBH) 1635 .addReg(ARM::PC) 1636 .addReg(MI->getOperand(0).getReg()) 1637 // Add predicate operands. 1638 .addImm(ARMCC::AL) 1639 .addReg(0)); 1640 1641 // Output the data for the jump table itself 1642 EmitJump2Table(MI); 1643 return; 1644 } 1645 case ARM::tBR_JTr: 1646 case ARM::BR_JTr: { 1647 // Lower and emit the instruction itself, then the jump table following it. 1648 // mov pc, target 1649 MCInst TmpInst; 1650 unsigned Opc = MI->getOpcode() == ARM::BR_JTr ? 1651 ARM::MOVr : ARM::tMOVr; 1652 TmpInst.setOpcode(Opc); 1653 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC)); 1654 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg())); 1655 // Add predicate operands. 1656 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL)); 1657 TmpInst.addOperand(MCOperand::CreateReg(0)); 1658 // Add 's' bit operand (always reg0 for this) 1659 if (Opc == ARM::MOVr) 1660 TmpInst.addOperand(MCOperand::CreateReg(0)); 1661 OutStreamer.EmitInstruction(TmpInst); 1662 1663 // Make sure the Thumb jump table is 4-byte aligned. 1664 if (Opc == ARM::tMOVr) 1665 EmitAlignment(2); 1666 1667 // Output the data for the jump table itself 1668 EmitJumpTable(MI); 1669 return; 1670 } 1671 case ARM::BR_JTm: { 1672 // Lower and emit the instruction itself, then the jump table following it. 1673 // ldr pc, target 1674 MCInst TmpInst; 1675 if (MI->getOperand(1).getReg() == 0) { 1676 // literal offset 1677 TmpInst.setOpcode(ARM::LDRi12); 1678 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC)); 1679 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg())); 1680 TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm())); 1681 } else { 1682 TmpInst.setOpcode(ARM::LDRrs); 1683 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC)); 1684 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg())); 1685 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg())); 1686 TmpInst.addOperand(MCOperand::CreateImm(0)); 1687 } 1688 // Add predicate operands. 1689 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL)); 1690 TmpInst.addOperand(MCOperand::CreateReg(0)); 1691 OutStreamer.EmitInstruction(TmpInst); 1692 1693 // Output the data for the jump table itself 1694 EmitJumpTable(MI); 1695 return; 1696 } 1697 case ARM::BR_JTadd: { 1698 // Lower and emit the instruction itself, then the jump table following it. 1699 // add pc, target, idx 1700 OutStreamer.EmitInstruction(MCInstBuilder(ARM::ADDrr) 1701 .addReg(ARM::PC) 1702 .addReg(MI->getOperand(0).getReg()) 1703 .addReg(MI->getOperand(1).getReg()) 1704 // Add predicate operands. 1705 .addImm(ARMCC::AL) 1706 .addReg(0) 1707 // Add 's' bit operand (always reg0 for this) 1708 .addReg(0)); 1709 1710 // Output the data for the jump table itself 1711 EmitJumpTable(MI); 1712 return; 1713 } 1714 case ARM::TRAP: { 1715 // Non-Darwin binutils don't yet support the "trap" mnemonic. 1716 // FIXME: Remove this special case when they do. 1717 if (!Subtarget->isTargetDarwin()) { 1718 //.long 0xe7ffdefe @ trap 1719 uint32_t Val = 0xe7ffdefeUL; 1720 OutStreamer.AddComment("trap"); 1721 OutStreamer.EmitIntValue(Val, 4); 1722 return; 1723 } 1724 break; 1725 } 1726 case ARM::TRAPNaCl: { 1727 //.long 0xe7fedef0 @ trap 1728 uint32_t Val = 0xe7fedef0UL; 1729 OutStreamer.AddComment("trap"); 1730 OutStreamer.EmitIntValue(Val, 4); 1731 return; 1732 } 1733 case ARM::tTRAP: { 1734 // Non-Darwin binutils don't yet support the "trap" mnemonic. 1735 // FIXME: Remove this special case when they do. 1736 if (!Subtarget->isTargetDarwin()) { 1737 //.short 57086 @ trap 1738 uint16_t Val = 0xdefe; 1739 OutStreamer.AddComment("trap"); 1740 OutStreamer.EmitIntValue(Val, 2); 1741 return; 1742 } 1743 break; 1744 } 1745 case ARM::t2Int_eh_sjlj_setjmp: 1746 case ARM::t2Int_eh_sjlj_setjmp_nofp: 1747 case ARM::tInt_eh_sjlj_setjmp: { 1748 // Two incoming args: GPR:$src, GPR:$val 1749 // mov $val, pc 1750 // adds $val, #7 1751 // str $val, [$src, #4] 1752 // movs r0, #0 1753 // b 1f 1754 // movs r0, #1 1755 // 1: 1756 unsigned SrcReg = MI->getOperand(0).getReg(); 1757 unsigned ValReg = MI->getOperand(1).getReg(); 1758 MCSymbol *Label = GetARMSJLJEHLabel(); 1759 OutStreamer.AddComment("eh_setjmp begin"); 1760 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tMOVr) 1761 .addReg(ValReg) 1762 .addReg(ARM::PC) 1763 // Predicate. 1764 .addImm(ARMCC::AL) 1765 .addReg(0)); 1766 1767 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tADDi3) 1768 .addReg(ValReg) 1769 // 's' bit operand 1770 .addReg(ARM::CPSR) 1771 .addReg(ValReg) 1772 .addImm(7) 1773 // Predicate. 1774 .addImm(ARMCC::AL) 1775 .addReg(0)); 1776 1777 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tSTRi) 1778 .addReg(ValReg) 1779 .addReg(SrcReg) 1780 // The offset immediate is #4. The operand value is scaled by 4 for the 1781 // tSTR instruction. 1782 .addImm(1) 1783 // Predicate. 1784 .addImm(ARMCC::AL) 1785 .addReg(0)); 1786 1787 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tMOVi8) 1788 .addReg(ARM::R0) 1789 .addReg(ARM::CPSR) 1790 .addImm(0) 1791 // Predicate. 1792 .addImm(ARMCC::AL) 1793 .addReg(0)); 1794 1795 const MCExpr *SymbolExpr = MCSymbolRefExpr::Create(Label, OutContext); 1796 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tB) 1797 .addExpr(SymbolExpr) 1798 .addImm(ARMCC::AL) 1799 .addReg(0)); 1800 1801 OutStreamer.AddComment("eh_setjmp end"); 1802 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tMOVi8) 1803 .addReg(ARM::R0) 1804 .addReg(ARM::CPSR) 1805 .addImm(1) 1806 // Predicate. 1807 .addImm(ARMCC::AL) 1808 .addReg(0)); 1809 1810 OutStreamer.EmitLabel(Label); 1811 return; 1812 } 1813 1814 case ARM::Int_eh_sjlj_setjmp_nofp: 1815 case ARM::Int_eh_sjlj_setjmp: { 1816 // Two incoming args: GPR:$src, GPR:$val 1817 // add $val, pc, #8 1818 // str $val, [$src, #+4] 1819 // mov r0, #0 1820 // add pc, pc, #0 1821 // mov r0, #1 1822 unsigned SrcReg = MI->getOperand(0).getReg(); 1823 unsigned ValReg = MI->getOperand(1).getReg(); 1824 1825 OutStreamer.AddComment("eh_setjmp begin"); 1826 OutStreamer.EmitInstruction(MCInstBuilder(ARM::ADDri) 1827 .addReg(ValReg) 1828 .addReg(ARM::PC) 1829 .addImm(8) 1830 // Predicate. 1831 .addImm(ARMCC::AL) 1832 .addReg(0) 1833 // 's' bit operand (always reg0 for this). 1834 .addReg(0)); 1835 1836 OutStreamer.EmitInstruction(MCInstBuilder(ARM::STRi12) 1837 .addReg(ValReg) 1838 .addReg(SrcReg) 1839 .addImm(4) 1840 // Predicate. 1841 .addImm(ARMCC::AL) 1842 .addReg(0)); 1843 1844 OutStreamer.EmitInstruction(MCInstBuilder(ARM::MOVi) 1845 .addReg(ARM::R0) 1846 .addImm(0) 1847 // Predicate. 1848 .addImm(ARMCC::AL) 1849 .addReg(0) 1850 // 's' bit operand (always reg0 for this). 1851 .addReg(0)); 1852 1853 OutStreamer.EmitInstruction(MCInstBuilder(ARM::ADDri) 1854 .addReg(ARM::PC) 1855 .addReg(ARM::PC) 1856 .addImm(0) 1857 // Predicate. 1858 .addImm(ARMCC::AL) 1859 .addReg(0) 1860 // 's' bit operand (always reg0 for this). 1861 .addReg(0)); 1862 1863 OutStreamer.AddComment("eh_setjmp end"); 1864 OutStreamer.EmitInstruction(MCInstBuilder(ARM::MOVi) 1865 .addReg(ARM::R0) 1866 .addImm(1) 1867 // Predicate. 1868 .addImm(ARMCC::AL) 1869 .addReg(0) 1870 // 's' bit operand (always reg0 for this). 1871 .addReg(0)); 1872 return; 1873 } 1874 case ARM::Int_eh_sjlj_longjmp: { 1875 // ldr sp, [$src, #8] 1876 // ldr $scratch, [$src, #4] 1877 // ldr r7, [$src] 1878 // bx $scratch 1879 unsigned SrcReg = MI->getOperand(0).getReg(); 1880 unsigned ScratchReg = MI->getOperand(1).getReg(); 1881 OutStreamer.EmitInstruction(MCInstBuilder(ARM::LDRi12) 1882 .addReg(ARM::SP) 1883 .addReg(SrcReg) 1884 .addImm(8) 1885 // Predicate. 1886 .addImm(ARMCC::AL) 1887 .addReg(0)); 1888 1889 OutStreamer.EmitInstruction(MCInstBuilder(ARM::LDRi12) 1890 .addReg(ScratchReg) 1891 .addReg(SrcReg) 1892 .addImm(4) 1893 // Predicate. 1894 .addImm(ARMCC::AL) 1895 .addReg(0)); 1896 1897 OutStreamer.EmitInstruction(MCInstBuilder(ARM::LDRi12) 1898 .addReg(ARM::R7) 1899 .addReg(SrcReg) 1900 .addImm(0) 1901 // Predicate. 1902 .addImm(ARMCC::AL) 1903 .addReg(0)); 1904 1905 OutStreamer.EmitInstruction(MCInstBuilder(ARM::BX) 1906 .addReg(ScratchReg) 1907 // Predicate. 1908 .addImm(ARMCC::AL) 1909 .addReg(0)); 1910 return; 1911 } 1912 case ARM::tInt_eh_sjlj_longjmp: { 1913 // ldr $scratch, [$src, #8] 1914 // mov sp, $scratch 1915 // ldr $scratch, [$src, #4] 1916 // ldr r7, [$src] 1917 // bx $scratch 1918 unsigned SrcReg = MI->getOperand(0).getReg(); 1919 unsigned ScratchReg = MI->getOperand(1).getReg(); 1920 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tLDRi) 1921 .addReg(ScratchReg) 1922 .addReg(SrcReg) 1923 // The offset immediate is #8. The operand value is scaled by 4 for the 1924 // tLDR instruction. 1925 .addImm(2) 1926 // Predicate. 1927 .addImm(ARMCC::AL) 1928 .addReg(0)); 1929 1930 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tMOVr) 1931 .addReg(ARM::SP) 1932 .addReg(ScratchReg) 1933 // Predicate. 1934 .addImm(ARMCC::AL) 1935 .addReg(0)); 1936 1937 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tLDRi) 1938 .addReg(ScratchReg) 1939 .addReg(SrcReg) 1940 .addImm(1) 1941 // Predicate. 1942 .addImm(ARMCC::AL) 1943 .addReg(0)); 1944 1945 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tLDRi) 1946 .addReg(ARM::R7) 1947 .addReg(SrcReg) 1948 .addImm(0) 1949 // Predicate. 1950 .addImm(ARMCC::AL) 1951 .addReg(0)); 1952 1953 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tBX) 1954 .addReg(ScratchReg) 1955 // Predicate. 1956 .addImm(ARMCC::AL) 1957 .addReg(0)); 1958 return; 1959 } 1960 } 1961 1962 MCInst TmpInst; 1963 LowerARMMachineInstrToMCInst(MI, TmpInst, *this); 1964 1965 OutStreamer.EmitInstruction(TmpInst); 1966} 1967 1968//===----------------------------------------------------------------------===// 1969// Target Registry Stuff 1970//===----------------------------------------------------------------------===// 1971 1972// Force static initialization. 1973extern "C" void LLVMInitializeARMAsmPrinter() { 1974 RegisterAsmPrinter<ARMAsmPrinter> X(TheARMTarget); 1975 RegisterAsmPrinter<ARMAsmPrinter> Y(TheThumbTarget); 1976} 1977