131d157ae1ac2cd9c787dc3c1d28e64c682803844Jia Liu//===-- ARMBaseInstrInfo.cpp - ARM Instruction Information ----------------===// 2334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// 3334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// The LLVM Compiler Infrastructure 4334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// 5334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// This file is distributed under the University of Illinois Open Source 6334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// License. See LICENSE.TXT for details. 7334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// 8334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin//===----------------------------------------------------------------------===// 9334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// 10334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// This file contains the Base ARM implementation of the TargetInstrInfo class. 11334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// 12334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin//===----------------------------------------------------------------------===// 13334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 14334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "ARM.h" 156eef361b73b457896b310d411251aedd5e72476aAmara Emerson#include "ARMBaseInstrInfo.h" 160e5233a9e5ee9385c6a940e3985194d77bee0bbbCraig Topper#include "ARMBaseRegisterInfo.h" 17d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng#include "ARMConstantPoolValue.h" 186eef361b73b457896b310d411251aedd5e72476aAmara Emerson#include "ARMFeatures.h" 1948575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng#include "ARMHazardRecognizer.h" 20334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "ARMMachineFunctionInfo.h" 21ee04a6d3a40c3017124e3fd89a0db473a2824498Evan Cheng#include "MCTargetDesc/ARMAddressingModes.h" 22d04a8d4b33ff316ca4cf961e06c9e312eff8e64fChandler Carruth#include "llvm/ADT/STLExtras.h" 23334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "llvm/CodeGen/LiveVariables.h" 24d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng#include "llvm/CodeGen/MachineConstantPool.h" 25334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "llvm/CodeGen/MachineFrameInfo.h" 26334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "llvm/CodeGen/MachineInstrBuilder.h" 27334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "llvm/CodeGen/MachineJumpTableInfo.h" 28249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov#include "llvm/CodeGen/MachineMemOperand.h" 292457f2c66184e978d4ed8fa9e2128effff26cb0bEvan Cheng#include "llvm/CodeGen/MachineRegisterInfo.h" 30ee04a6d3a40c3017124e3fd89a0db473a2824498Evan Cheng#include "llvm/CodeGen/SelectionDAGNodes.h" 310b8c9a80f20772c3793201ab5b251d3520b9cea3Chandler Carruth#include "llvm/IR/Constants.h" 320b8c9a80f20772c3793201ab5b251d3520b9cea3Chandler Carruth#include "llvm/IR/Function.h" 330b8c9a80f20772c3793201ab5b251d3520b9cea3Chandler Carruth#include "llvm/IR/GlobalValue.h" 34af76e592c7f9deff0e55c13dbb4a34f07f1c7f64Chris Lattner#include "llvm/MC/MCAsmInfo.h" 35cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen Hines#include "llvm/MC/MCExpr.h" 36f81b7f6069b27c0a515070dcb392f6828437412fJakub Staszak#include "llvm/Support/BranchProbability.h" 37334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "llvm/Support/CommandLine.h" 38f95215f551949d5e5adfbf4753aa833b9009b77aAnton Korobeynikov#include "llvm/Support/Debug.h" 39c25e7581b9b8088910da31702d4ca21c4734c6d7Torok Edwin#include "llvm/Support/ErrorHandling.h" 4022fee2dff4c43b551aefa44a96ca74fcade6bfacEvan Cheng 41dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hinesusing namespace llvm; 42dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines 43dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines#define DEBUG_TYPE "arm-instrinfo" 44dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines 45354362524a72b3fa43a6c09380b7ae3b2380cbbaJuergen Ributzka#define GET_INSTRINFO_CTOR_DTOR 4622fee2dff4c43b551aefa44a96ca74fcade6bfacEvan Cheng#include "ARMGenInstrInfo.inc" 4722fee2dff4c43b551aefa44a96ca74fcade6bfacEvan Cheng 48334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinstatic cl::opt<bool> 49334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinEnableARM3Addr("enable-arm-3-addr-conv", cl::Hidden, 50334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin cl::desc("Enable ARM 2-addr to 3-addr conv")); 51334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 5261545829832ba0375249c42c84843d0b62c8f55fJakob Stoklund Olesenstatic cl::opt<bool> 533805d85e38c29d9106c758b63851eb847201f315Jakob Stoklund OlesenWidenVMOVS("widen-vmovs", cl::Hidden, cl::init(true), 5461545829832ba0375249c42c84843d0b62c8f55fJakob Stoklund Olesen cl::desc("Widen ARM vmovs to vmovd when possible")); 5561545829832ba0375249c42c84843d0b62c8f55fJakob Stoklund Olesen 56eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilsonstatic cl::opt<unsigned> 57eb1641d54a7eda7717304bc4d55d059208d8ebedBob WilsonSwiftPartialUpdateClearance("swift-partial-update-clearance", 58eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson cl::Hidden, cl::init(12), 59eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson cl::desc("Clearance before partial register updates")); 60eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson 6148575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng/// ARM_MLxEntry - Record information about MLA / MLS instructions. 6248575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Chengstruct ARM_MLxEntry { 63cd2859eef83708c00330c94f6842499b48d5ed02Craig Topper uint16_t MLxOpc; // MLA / MLS opcode 64cd2859eef83708c00330c94f6842499b48d5ed02Craig Topper uint16_t MulOpc; // Expanded multiplication opcode 65cd2859eef83708c00330c94f6842499b48d5ed02Craig Topper uint16_t AddSubOpc; // Expanded add / sub opcode 6648575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng bool NegAcc; // True if the acc is negated before the add / sub. 6748575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng bool HasLane; // True if instruction has an extra "lane" operand. 6848575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng}; 6948575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng 7048575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Chengstatic const ARM_MLxEntry ARM_MLxTable[] = { 7148575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng // MLxOpc, MulOpc, AddSubOpc, NegAcc, HasLane 7248575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng // fp scalar ops 7348575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng { ARM::VMLAS, ARM::VMULS, ARM::VADDS, false, false }, 7448575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng { ARM::VMLSS, ARM::VMULS, ARM::VSUBS, false, false }, 7548575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng { ARM::VMLAD, ARM::VMULD, ARM::VADDD, false, false }, 7648575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng { ARM::VMLSD, ARM::VMULD, ARM::VSUBD, false, false }, 7748575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng { ARM::VNMLAS, ARM::VNMULS, ARM::VSUBS, true, false }, 7848575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng { ARM::VNMLSS, ARM::VMULS, ARM::VSUBS, true, false }, 7948575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng { ARM::VNMLAD, ARM::VNMULD, ARM::VSUBD, true, false }, 8048575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng { ARM::VNMLSD, ARM::VMULD, ARM::VSUBD, true, false }, 8148575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng 8248575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng // fp SIMD ops 8348575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng { ARM::VMLAfd, ARM::VMULfd, ARM::VADDfd, false, false }, 8448575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng { ARM::VMLSfd, ARM::VMULfd, ARM::VSUBfd, false, false }, 8548575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng { ARM::VMLAfq, ARM::VMULfq, ARM::VADDfq, false, false }, 8648575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng { ARM::VMLSfq, ARM::VMULfq, ARM::VSUBfq, false, false }, 8748575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng { ARM::VMLAslfd, ARM::VMULslfd, ARM::VADDfd, false, true }, 8848575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng { ARM::VMLSslfd, ARM::VMULslfd, ARM::VSUBfd, false, true }, 8948575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng { ARM::VMLAslfq, ARM::VMULslfq, ARM::VADDfq, false, true }, 9048575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng { ARM::VMLSslfq, ARM::VMULslfq, ARM::VSUBfq, false, true }, 9148575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng}; 9248575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng 93f95215f551949d5e5adfbf4753aa833b9009b77aAnton KorobeynikovARMBaseInstrInfo::ARMBaseInstrInfo(const ARMSubtarget& STI) 944db3cffe94a5285239cc0056f939c6b74a5ca0b6Evan Cheng : ARMGenInstrInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP), 95f95215f551949d5e5adfbf4753aa833b9009b77aAnton Korobeynikov Subtarget(STI) { 9648575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng for (unsigned i = 0, e = array_lengthof(ARM_MLxTable); i != e; ++i) { 9748575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng if (!MLxEntryMap.insert(std::make_pair(ARM_MLxTable[i].MLxOpc, i)).second) 9848575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng assert(false && "Duplicated entries?"); 9948575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng MLxHazardOpcodes.insert(ARM_MLxTable[i].AddSubOpc); 10048575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng MLxHazardOpcodes.insert(ARM_MLxTable[i].MulOpc); 10148575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng } 10248575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng} 10348575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng 1042da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick// Use a ScoreboardHazardRecognizer for prepass ARM scheduling. TargetInstrImpl 1052da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick// currently defaults to no prepass hazard recognizer. 106cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen HinesScheduleHazardRecognizer * 107cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen HinesARMBaseInstrInfo::CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI, 108cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen Hines const ScheduleDAG *DAG) const { 109c8bfd1d78ff9a307d1d4cb57cce4549b538e60f4Andrew Trick if (usePreRAHazardRecognizer()) { 110cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen Hines const InstrItineraryData *II = 111cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen Hines &static_cast<const ARMSubtarget *>(STI)->getInstrItineraryData(); 1122da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick return new ScoreboardHazardRecognizer(II, DAG, "pre-RA-sched"); 1132da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick } 114cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen Hines return TargetInstrInfo::CreateTargetHazardRecognizer(STI, DAG); 1152da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick} 1162da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick 1172da8bc8a5f7705ac131184cd247f48500da0d74eAndrew TrickScheduleHazardRecognizer *ARMBaseInstrInfo:: 1182da8bc8a5f7705ac131184cd247f48500da0d74eAndrew TrickCreateTargetPostRAHazardRecognizer(const InstrItineraryData *II, 1192da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick const ScheduleDAG *DAG) const { 12048575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng if (Subtarget.isThumb2() || Subtarget.hasVFP2()) 12157148c166ab232191098492633c924fad9c44ef3Bill Wendling return (ScheduleHazardRecognizer *)new ARMHazardRecognizer(II, DAG); 122a9fa4fd9736f7d1066223f32fa54efbe86c0fcebJakob Stoklund Olesen return TargetInstrInfo::CreateTargetPostRAHazardRecognizer(II, DAG); 123334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 124334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 125334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinMachineInstr * 126334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinARMBaseInstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI, 127334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineBasicBlock::iterator &MBBI, 128334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin LiveVariables *LV) const { 12978703ddafe3d037f75d8ca188e4829d238289ac3Evan Cheng // FIXME: Thumb2 support. 13078703ddafe3d037f75d8ca188e4829d238289ac3Evan Cheng 131334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (!EnableARM3Addr) 132dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines return nullptr; 133334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 134334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineInstr *MI = MBBI; 135334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineFunction &MF = *MI->getParent()->getParent(); 13699405df044f2c584242e711cc9023ec90356da82Bruno Cardoso Lopes uint64_t TSFlags = MI->getDesc().TSFlags; 137334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool isPre = false; 138334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin switch ((TSFlags & ARMII::IndexModeMask) >> ARMII::IndexModeShift) { 139dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines default: return nullptr; 140334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMII::IndexModePre: 141334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin isPre = true; 142334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin break; 143334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMII::IndexModePost: 144334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin break; 145334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 146334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 147334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Try splitting an indexed load/store to an un-indexed one plus an add/sub 148334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // operation. 149334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned MemOpc = getUnindexedOpcode(MI->getOpcode()); 150334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (MemOpc == 0) 151dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines return nullptr; 152334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 153dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines MachineInstr *UpdateMI = nullptr; 154dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines MachineInstr *MemMI = nullptr; 155334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned AddrMode = (TSFlags & ARMII::AddrModeMask); 156e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng const MCInstrDesc &MCID = MI->getDesc(); 157e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng unsigned NumOps = MCID.getNumOperands(); 1585a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng bool isLoad = !MI->mayStore(); 159334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const MachineOperand &WB = isLoad ? MI->getOperand(1) : MI->getOperand(0); 160334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const MachineOperand &Base = MI->getOperand(2); 161334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const MachineOperand &Offset = MI->getOperand(NumOps-3); 162334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned WBReg = WB.getReg(); 163334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned BaseReg = Base.getReg(); 164334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned OffReg = Offset.getReg(); 165334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned OffImm = MI->getOperand(NumOps-2).getImm(); 166334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin ARMCC::CondCodes Pred = (ARMCC::CondCodes)MI->getOperand(NumOps-1).getImm(); 167334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin switch (AddrMode) { 168bc2198133a1836598b54b943420748e75d5dea94Craig Topper default: llvm_unreachable("Unknown indexed op!"); 169334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMII::AddrMode2: { 170334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool isSub = ARM_AM::getAM2Op(OffImm) == ARM_AM::sub; 171334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned Amt = ARM_AM::getAM2Offset(OffImm); 172334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (OffReg == 0) { 173e7cbe4118b7ddf05032ff8772a98c51e1637bb5cEvan Cheng if (ARM_AM::getSOImmVal(Amt) == -1) 174334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Can't encode it in a so_imm operand. This transformation will 175334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // add more than 1 instruction. Abandon! 176dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines return nullptr; 177334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin UpdateMI = BuildMI(MF, MI->getDebugLoc(), 17878703ddafe3d037f75d8ca188e4829d238289ac3Evan Cheng get(isSub ? ARM::SUBri : ARM::ADDri), WBReg) 179e7cbe4118b7ddf05032ff8772a98c51e1637bb5cEvan Cheng .addReg(BaseReg).addImm(Amt) 180334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addImm(Pred).addReg(0).addReg(0); 181334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } else if (Amt != 0) { 182334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin ARM_AM::ShiftOpc ShOpc = ARM_AM::getAM2ShiftOpc(OffImm); 183334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned SOOpc = ARM_AM::getSORegOpc(ShOpc, Amt); 184334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin UpdateMI = BuildMI(MF, MI->getDebugLoc(), 18592a202213bb4c20301abf6ab64e46df3695e60bfOwen Anderson get(isSub ? ARM::SUBrsi : ARM::ADDrsi), WBReg) 186334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(BaseReg).addReg(OffReg).addReg(0).addImm(SOOpc) 187334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addImm(Pred).addReg(0).addReg(0); 188334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } else 189334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin UpdateMI = BuildMI(MF, MI->getDebugLoc(), 19078703ddafe3d037f75d8ca188e4829d238289ac3Evan Cheng get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg) 191334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(BaseReg).addReg(OffReg) 192334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addImm(Pred).addReg(0).addReg(0); 193334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin break; 194334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 195334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMII::AddrMode3 : { 196334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool isSub = ARM_AM::getAM3Op(OffImm) == ARM_AM::sub; 197334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned Amt = ARM_AM::getAM3Offset(OffImm); 198334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (OffReg == 0) 199334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Immediate is 8-bits. It's guaranteed to fit in a so_imm operand. 200334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin UpdateMI = BuildMI(MF, MI->getDebugLoc(), 20178703ddafe3d037f75d8ca188e4829d238289ac3Evan Cheng get(isSub ? ARM::SUBri : ARM::ADDri), WBReg) 202334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(BaseReg).addImm(Amt) 203334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addImm(Pred).addReg(0).addReg(0); 204334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin else 205334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin UpdateMI = BuildMI(MF, MI->getDebugLoc(), 20678703ddafe3d037f75d8ca188e4829d238289ac3Evan Cheng get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg) 207334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(BaseReg).addReg(OffReg) 208334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addImm(Pred).addReg(0).addReg(0); 209334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin break; 210334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 211334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 212334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 213334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin std::vector<MachineInstr*> NewMIs; 214334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (isPre) { 215334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (isLoad) 216334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MemMI = BuildMI(MF, MI->getDebugLoc(), 217334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin get(MemOpc), MI->getOperand(0).getReg()) 2183e5561247202bae994dd259a2d8dc4eff8f799f3Jim Grosbach .addReg(WBReg).addImm(0).addImm(Pred); 219334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin else 220334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MemMI = BuildMI(MF, MI->getDebugLoc(), 221334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin get(MemOpc)).addReg(MI->getOperand(1).getReg()) 222334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(WBReg).addReg(0).addImm(0).addImm(Pred); 223334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin NewMIs.push_back(MemMI); 224334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin NewMIs.push_back(UpdateMI); 225334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } else { 226334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (isLoad) 227334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MemMI = BuildMI(MF, MI->getDebugLoc(), 228334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin get(MemOpc), MI->getOperand(0).getReg()) 2293e5561247202bae994dd259a2d8dc4eff8f799f3Jim Grosbach .addReg(BaseReg).addImm(0).addImm(Pred); 230334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin else 231334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MemMI = BuildMI(MF, MI->getDebugLoc(), 232334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin get(MemOpc)).addReg(MI->getOperand(1).getReg()) 233334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred); 234334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (WB.isDead()) 235334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin UpdateMI->getOperand(0).setIsDead(); 236334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin NewMIs.push_back(UpdateMI); 237334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin NewMIs.push_back(MemMI); 238334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 239334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 240334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Transfer LiveVariables states, kill / dead info. 241334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (LV) { 242334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 243334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineOperand &MO = MI->getOperand(i); 244c9df025e33ac435adb3b3318d237c36ca7cec659Jakob Stoklund Olesen if (MO.isReg() && TargetRegisterInfo::isVirtualRegister(MO.getReg())) { 245334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned Reg = MO.getReg(); 246334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 247334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin LiveVariables::VarInfo &VI = LV->getVarInfo(Reg); 248334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (MO.isDef()) { 249334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineInstr *NewMI = (Reg == WBReg) ? UpdateMI : MemMI; 250334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (MO.isDead()) 251334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin LV->addVirtualRegisterDead(Reg, NewMI); 252334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 253334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (MO.isUse() && MO.isKill()) { 254334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin for (unsigned j = 0; j < 2; ++j) { 255334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Look at the two new MI's in reverse order. 256334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineInstr *NewMI = NewMIs[j]; 257334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (!NewMI->readsRegister(Reg)) 258334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin continue; 259334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin LV->addVirtualRegisterKilled(Reg, NewMI); 260334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (VI.removeKill(MI)) 261334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin VI.Kills.push_back(NewMI); 262334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin break; 263334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 264334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 265334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 266334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 267334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 268334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 269334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MFI->insert(MBBI, NewMIs[1]); 270334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MFI->insert(MBBI, NewMIs[0]); 271334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return NewMIs[0]; 272334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 273334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 274334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// Branch analysis. 275334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinbool 276334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinARMBaseInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB, 277334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineBasicBlock *&FBB, 278334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin SmallVectorImpl<MachineOperand> &Cond, 279334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool AllowModify) const { 280dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines TBB = nullptr; 281dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines FBB = nullptr; 2827b61a701932d850d2777fafda1fea5ec841d893bLang Hames 283334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineBasicBlock::iterator I = MBB.end(); 28493d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen if (I == MBB.begin()) 2857b61a701932d850d2777fafda1fea5ec841d893bLang Hames return false; // Empty blocks are easy. 28693d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen --I; 287334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 2887b61a701932d850d2777fafda1fea5ec841d893bLang Hames // Walk backwards from the end of the basic block until the branch is 2897b61a701932d850d2777fafda1fea5ec841d893bLang Hames // analyzed or we give up. 29036b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines while (isPredicated(I) || I->isTerminator() || I->isDebugValue()) { 2910553e1efcd3f8ccd8b45302e033924d9f85a5d2fEvan Cheng 2927b61a701932d850d2777fafda1fea5ec841d893bLang Hames // Flag to be raised on unanalyzeable instructions. This is useful in cases 2937b61a701932d850d2777fafda1fea5ec841d893bLang Hames // where we want to clean up on the end of the basic block before we bail 2947b61a701932d850d2777fafda1fea5ec841d893bLang Hames // out. 2957b61a701932d850d2777fafda1fea5ec841d893bLang Hames bool CantAnalyze = false; 2960553e1efcd3f8ccd8b45302e033924d9f85a5d2fEvan Cheng 2977b61a701932d850d2777fafda1fea5ec841d893bLang Hames // Skip over DEBUG values and predicated nonterminators. 2987b61a701932d850d2777fafda1fea5ec841d893bLang Hames while (I->isDebugValue() || !I->isTerminator()) { 2997b61a701932d850d2777fafda1fea5ec841d893bLang Hames if (I == MBB.begin()) 3007b61a701932d850d2777fafda1fea5ec841d893bLang Hames return false; 3017b61a701932d850d2777fafda1fea5ec841d893bLang Hames --I; 302334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 3037b61a701932d850d2777fafda1fea5ec841d893bLang Hames 3047b61a701932d850d2777fafda1fea5ec841d893bLang Hames if (isIndirectBranchOpcode(I->getOpcode()) || 3057b61a701932d850d2777fafda1fea5ec841d893bLang Hames isJumpTableBranchOpcode(I->getOpcode())) { 3067b61a701932d850d2777fafda1fea5ec841d893bLang Hames // Indirect branches and jump tables can't be analyzed, but we still want 3077b61a701932d850d2777fafda1fea5ec841d893bLang Hames // to clean up any instructions at the tail of the basic block. 3087b61a701932d850d2777fafda1fea5ec841d893bLang Hames CantAnalyze = true; 3097b61a701932d850d2777fafda1fea5ec841d893bLang Hames } else if (isUncondBranchOpcode(I->getOpcode())) { 3107b61a701932d850d2777fafda1fea5ec841d893bLang Hames TBB = I->getOperand(0).getMBB(); 3117b61a701932d850d2777fafda1fea5ec841d893bLang Hames } else if (isCondBranchOpcode(I->getOpcode())) { 3127b61a701932d850d2777fafda1fea5ec841d893bLang Hames // Bail out if we encounter multiple conditional branches. 3137b61a701932d850d2777fafda1fea5ec841d893bLang Hames if (!Cond.empty()) 3147b61a701932d850d2777fafda1fea5ec841d893bLang Hames return true; 3157b61a701932d850d2777fafda1fea5ec841d893bLang Hames 3167b61a701932d850d2777fafda1fea5ec841d893bLang Hames assert(!FBB && "FBB should have been null."); 3177b61a701932d850d2777fafda1fea5ec841d893bLang Hames FBB = TBB; 3187b61a701932d850d2777fafda1fea5ec841d893bLang Hames TBB = I->getOperand(0).getMBB(); 3197b61a701932d850d2777fafda1fea5ec841d893bLang Hames Cond.push_back(I->getOperand(1)); 3207b61a701932d850d2777fafda1fea5ec841d893bLang Hames Cond.push_back(I->getOperand(2)); 3217b61a701932d850d2777fafda1fea5ec841d893bLang Hames } else if (I->isReturn()) { 3227b61a701932d850d2777fafda1fea5ec841d893bLang Hames // Returns can't be analyzed, but we should run cleanup. 3237b61a701932d850d2777fafda1fea5ec841d893bLang Hames CantAnalyze = !isPredicated(I); 3247b61a701932d850d2777fafda1fea5ec841d893bLang Hames } else { 3257b61a701932d850d2777fafda1fea5ec841d893bLang Hames // We encountered other unrecognized terminator. Bail out immediately. 3267b61a701932d850d2777fafda1fea5ec841d893bLang Hames return true; 327334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 328334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 3297b61a701932d850d2777fafda1fea5ec841d893bLang Hames // Cleanup code - to be run for unpredicated unconditional branches and 3307b61a701932d850d2777fafda1fea5ec841d893bLang Hames // returns. 3317b61a701932d850d2777fafda1fea5ec841d893bLang Hames if (!isPredicated(I) && 3327b61a701932d850d2777fafda1fea5ec841d893bLang Hames (isUncondBranchOpcode(I->getOpcode()) || 3337b61a701932d850d2777fafda1fea5ec841d893bLang Hames isIndirectBranchOpcode(I->getOpcode()) || 3347b61a701932d850d2777fafda1fea5ec841d893bLang Hames isJumpTableBranchOpcode(I->getOpcode()) || 3357b61a701932d850d2777fafda1fea5ec841d893bLang Hames I->isReturn())) { 3367b61a701932d850d2777fafda1fea5ec841d893bLang Hames // Forget any previous condition branch information - it no longer applies. 3377b61a701932d850d2777fafda1fea5ec841d893bLang Hames Cond.clear(); 338dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines FBB = nullptr; 3397b61a701932d850d2777fafda1fea5ec841d893bLang Hames 3407b61a701932d850d2777fafda1fea5ec841d893bLang Hames // If we can modify the function, delete everything below this 3417b61a701932d850d2777fafda1fea5ec841d893bLang Hames // unconditional branch. 3427b61a701932d850d2777fafda1fea5ec841d893bLang Hames if (AllowModify) { 34336b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines MachineBasicBlock::iterator DI = std::next(I); 3447b61a701932d850d2777fafda1fea5ec841d893bLang Hames while (DI != MBB.end()) { 3457b61a701932d850d2777fafda1fea5ec841d893bLang Hames MachineInstr *InstToDelete = DI; 3467b61a701932d850d2777fafda1fea5ec841d893bLang Hames ++DI; 3477b61a701932d850d2777fafda1fea5ec841d893bLang Hames InstToDelete->eraseFromParent(); 3487b61a701932d850d2777fafda1fea5ec841d893bLang Hames } 349108c8724663354050dc09bb1262c3e4511adf82fEvan Cheng } 350108c8724663354050dc09bb1262c3e4511adf82fEvan Cheng } 351334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 3527b61a701932d850d2777fafda1fea5ec841d893bLang Hames if (CantAnalyze) 3537b61a701932d850d2777fafda1fea5ec841d893bLang Hames return true; 354334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 3557b61a701932d850d2777fafda1fea5ec841d893bLang Hames if (I == MBB.begin()) 3567b61a701932d850d2777fafda1fea5ec841d893bLang Hames return false; 357334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 3587b61a701932d850d2777fafda1fea5ec841d893bLang Hames --I; 359334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 360334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 3617b61a701932d850d2777fafda1fea5ec841d893bLang Hames // We made it past the terminators without bailing out - we must have 3627b61a701932d850d2777fafda1fea5ec841d893bLang Hames // analyzed this branch successfully. 3637b61a701932d850d2777fafda1fea5ec841d893bLang Hames return false; 364334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 365334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 366334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 367334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinunsigned ARMBaseInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const { 368334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineBasicBlock::iterator I = MBB.end(); 369334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (I == MBB.begin()) return 0; 370334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin --I; 37193d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen while (I->isDebugValue()) { 37293d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen if (I == MBB.begin()) 37393d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen return 0; 37493d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen --I; 37593d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen } 3765ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng if (!isUncondBranchOpcode(I->getOpcode()) && 3775ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng !isCondBranchOpcode(I->getOpcode())) 378334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 0; 379334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 380334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Remove the branch. 381334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin I->eraseFromParent(); 382334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 383334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin I = MBB.end(); 384334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 385334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (I == MBB.begin()) return 1; 386334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin --I; 3875ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng if (!isCondBranchOpcode(I->getOpcode())) 388334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 1; 389334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 390334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Remove the branch. 391334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin I->eraseFromParent(); 392334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 2; 393334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 394334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 395334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinunsigned 396334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinARMBaseInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 3973bf912593301152b65accb9d9c37a95172f1df5aStuart Hastings MachineBasicBlock *FBB, 3983bf912593301152b65accb9d9c37a95172f1df5aStuart Hastings const SmallVectorImpl<MachineOperand> &Cond, 3993bf912593301152b65accb9d9c37a95172f1df5aStuart Hastings DebugLoc DL) const { 4006495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ARMFunctionInfo *AFI = MBB.getParent()->getInfo<ARMFunctionInfo>(); 4016495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng int BOpc = !AFI->isThumbFunction() 4026495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ? ARM::B : (AFI->isThumb2Function() ? ARM::t2B : ARM::tB); 4036495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng int BccOpc = !AFI->isThumbFunction() 4046495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ? ARM::Bcc : (AFI->isThumb2Function() ? ARM::t2Bcc : ARM::tBcc); 40551f6a7abf27fc92c3d8904c2334feab8b498e8e9Owen Anderson bool isThumb = AFI->isThumbFunction() || AFI->isThumb2Function(); 406e23dc9c0ef50b0a1934c04c1786f3a0478d62f41Andrew Trick 407334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Shouldn't be a fall through. 408334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin assert(TBB && "InsertBranch must not be told to insert a fallthrough"); 409334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin assert((Cond.size() == 2 || Cond.size() == 0) && 410334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin "ARM branch conditions have two components!"); 411334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 412dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines if (!FBB) { 413112fb73502d54dd7dd61ae2de24c92d4df181294Owen Anderson if (Cond.empty()) { // Unconditional branch? 41451f6a7abf27fc92c3d8904c2334feab8b498e8e9Owen Anderson if (isThumb) 41551f6a7abf27fc92c3d8904c2334feab8b498e8e9Owen Anderson BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB).addImm(ARMCC::AL).addReg(0); 41651f6a7abf27fc92c3d8904c2334feab8b498e8e9Owen Anderson else 41751f6a7abf27fc92c3d8904c2334feab8b498e8e9Owen Anderson BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB); 418112fb73502d54dd7dd61ae2de24c92d4df181294Owen Anderson } else 4193bf912593301152b65accb9d9c37a95172f1df5aStuart Hastings BuildMI(&MBB, DL, get(BccOpc)).addMBB(TBB) 420334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()); 421334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 1; 422334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 423334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 424334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Two-way conditional branch. 4253bf912593301152b65accb9d9c37a95172f1df5aStuart Hastings BuildMI(&MBB, DL, get(BccOpc)).addMBB(TBB) 426334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()); 42751f6a7abf27fc92c3d8904c2334feab8b498e8e9Owen Anderson if (isThumb) 42851f6a7abf27fc92c3d8904c2334feab8b498e8e9Owen Anderson BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB).addImm(ARMCC::AL).addReg(0); 42951f6a7abf27fc92c3d8904c2334feab8b498e8e9Owen Anderson else 43051f6a7abf27fc92c3d8904c2334feab8b498e8e9Owen Anderson BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB); 431334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 2; 432334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 433334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 434334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinbool ARMBaseInstrInfo:: 435334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const { 436334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin ARMCC::CondCodes CC = (ARMCC::CondCodes)(int)Cond[0].getImm(); 437334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin Cond[0].setImm(ARMCC::getOppositeCondition(CC)); 438334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 439334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 440334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 441ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Chengbool ARMBaseInstrInfo::isPredicated(const MachineInstr *MI) const { 442ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng if (MI->isBundle()) { 443ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng MachineBasicBlock::const_instr_iterator I = MI; 444ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end(); 445ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng while (++I != E && I->isInsideBundle()) { 446ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng int PIdx = I->findFirstPredOperandIdx(); 447ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng if (PIdx != -1 && I->getOperand(PIdx).getImm() != ARMCC::AL) 448ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng return true; 449ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng } 450ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng return false; 451ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng } 452ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng 453ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng int PIdx = MI->findFirstPredOperandIdx(); 454ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng return PIdx != -1 && MI->getOperand(PIdx).getImm() != ARMCC::AL; 455ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng} 456ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng 457334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinbool ARMBaseInstrInfo:: 458334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinPredicateInstruction(MachineInstr *MI, 459334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const SmallVectorImpl<MachineOperand> &Pred) const { 460334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned Opc = MI->getOpcode(); 4615ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng if (isUncondBranchOpcode(Opc)) { 4625ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng MI->setDesc(get(getMatchingCondBranchOpcode(Opc))); 463b9efafe54d61e85ca5209c4043aa814f89785195Jakob Stoklund Olesen MachineInstrBuilder(*MI->getParent()->getParent(), MI) 464b9efafe54d61e85ca5209c4043aa814f89785195Jakob Stoklund Olesen .addImm(Pred[0].getImm()) 465b9efafe54d61e85ca5209c4043aa814f89785195Jakob Stoklund Olesen .addReg(Pred[1].getReg()); 466334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; 467334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 468334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 469334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin int PIdx = MI->findFirstPredOperandIdx(); 470334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (PIdx != -1) { 471334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineOperand &PMO = MI->getOperand(PIdx); 472334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin PMO.setImm(Pred[0].getImm()); 473334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI->getOperand(PIdx+1).setReg(Pred[1].getReg()); 474334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; 475334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 476334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 477334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 478334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 479334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinbool ARMBaseInstrInfo:: 480334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinSubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1, 481334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const SmallVectorImpl<MachineOperand> &Pred2) const { 482334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (Pred1.size() > 2 || Pred2.size() > 2) 483334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 484334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 485334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin ARMCC::CondCodes CC1 = (ARMCC::CondCodes)Pred1[0].getImm(); 486334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin ARMCC::CondCodes CC2 = (ARMCC::CondCodes)Pred2[0].getImm(); 487334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (CC1 == CC2) 488334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; 489334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 490334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin switch (CC1) { 491334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin default: 492334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 493334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMCC::AL: 494334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; 495334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMCC::HS: 496334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return CC2 == ARMCC::HI; 497334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMCC::LS: 498334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return CC2 == ARMCC::LO || CC2 == ARMCC::EQ; 499334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMCC::GE: 500334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return CC2 == ARMCC::GT; 501334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMCC::LE: 502334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return CC2 == ARMCC::LT; 503334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 504334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 505334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 506334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinbool ARMBaseInstrInfo::DefinesPredicate(MachineInstr *MI, 507334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin std::vector<MachineOperand> &Pred) const { 508334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool Found = false; 509334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 510334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const MachineOperand &MO = MI->getOperand(i); 5112420b558de5d291d8503c1339004e5b5bf99a48aJakob Stoklund Olesen if ((MO.isRegMask() && MO.clobbersPhysReg(ARM::CPSR)) || 5122420b558de5d291d8503c1339004e5b5bf99a48aJakob Stoklund Olesen (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR)) { 513334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin Pred.push_back(MO); 514334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin Found = true; 515334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 516334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 517334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 518334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return Found; 519334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 520334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 521ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng/// isPredicable - Return true if the specified instruction can be predicated. 522ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng/// By default, this returns true for every instruction with a 523ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng/// PredicateOperand. 524ac0869dc8a7986855c5557cc67d4709600158ef5Evan Chengbool ARMBaseInstrInfo::isPredicable(MachineInstr *MI) const { 5255a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng if (!MI->isPredicable()) 526ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng return false; 527ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng 528b57d99694b87326a2eea26d76becf67bf5784b49Joey Gouly ARMFunctionInfo *AFI = 529b57d99694b87326a2eea26d76becf67bf5784b49Joey Gouly MI->getParent()->getParent()->getInfo<ARMFunctionInfo>(); 530b57d99694b87326a2eea26d76becf67bf5784b49Joey Gouly 531b57d99694b87326a2eea26d76becf67bf5784b49Joey Gouly if (AFI->isThumb2Function()) { 532929bdb23794b615dc6b0cc59db21f0450c3ce33bWeiming Zhao if (getSubtarget().restrictIT()) 533b57d99694b87326a2eea26d76becf67bf5784b49Joey Gouly return isV8EligibleForIT(MI); 534b57d99694b87326a2eea26d76becf67bf5784b49Joey Gouly } else { // non-Thumb 535b57d99694b87326a2eea26d76becf67bf5784b49Joey Gouly if ((MI->getDesc().TSFlags & ARMII::DomainMask) == ARMII::DomainNEON) 536b57d99694b87326a2eea26d76becf67bf5784b49Joey Gouly return false; 537ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng } 538b57d99694b87326a2eea26d76becf67bf5784b49Joey Gouly 539ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng return true; 540ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng} 541334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 542dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hinesnamespace llvm { 543dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hinestemplate <> bool IsCPSRDead<MachineInstr>(MachineInstr *MI) { 54436b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 54536b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines const MachineOperand &MO = MI->getOperand(i); 54636b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines if (!MO.isReg() || MO.isUndef() || MO.isUse()) 54736b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines continue; 54836b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines if (MO.getReg() != ARM::CPSR) 54936b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines continue; 55036b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines if (!MO.isDead()) 55136b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines return false; 55236b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines } 55336b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines // all definitions of CPSR are dead 55436b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines return true; 55536b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines} 556dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines} 55736b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines 55856856b1f46ec1f073ceef4e826c544b8b1691608Chris Lattner/// FIXME: Works around a gcc miscompilation with -fstrict-aliasing. 55919e57025d458d3cb50804fd821fd89b868a819bdChandler CarruthLLVM_ATTRIBUTE_NOINLINE 560334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinstatic unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT, 56156856b1f46ec1f073ceef4e826c544b8b1691608Chris Lattner unsigned JTI); 562334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinstatic unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT, 563334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned JTI) { 56456856b1f46ec1f073ceef4e826c544b8b1691608Chris Lattner assert(JTI < JT.size()); 565334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return JT[JTI].MBBs.size(); 566334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 567334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 568334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin/// GetInstSize - Return the size of the specified MachineInstr. 569334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin/// 570334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinunsigned ARMBaseInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const { 571334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const MachineBasicBlock &MBB = *MI->getParent(); 572334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const MachineFunction *MF = MBB.getParent(); 57333adcfb4d217f5f23d9bde8ba02b8e48f9605fc5Chris Lattner const MCAsmInfo *MAI = MF->getTarget().getMCAsmInfo(); 574334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 575e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng const MCInstrDesc &MCID = MI->getDesc(); 57616884415db751c75f2133bd04921393c792b1158Owen Anderson if (MCID.getSize()) 57716884415db751c75f2133bd04921393c792b1158Owen Anderson return MCID.getSize(); 578334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 5794d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie // If this machine instr is an inline asm, measure it. 5804d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie if (MI->getOpcode() == ARM::INLINEASM) 5814d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie return getInlineAsmLength(MI->getOperand(0).getSymbolName(), *MAI); 5824d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie unsigned Opc = MI->getOpcode(); 5834d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie switch (Opc) { 58436b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines default: 58536b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines // pseudo-instruction sizes are zero. 5864d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie return 0; 5874d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie case TargetOpcode::BUNDLE: 5884d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie return getInstBundleLength(MI); 5894d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie case ARM::MOVi16_ga_pcrel: 5904d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie case ARM::MOVTi16_ga_pcrel: 5914d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie case ARM::t2MOVi16_ga_pcrel: 5924d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie case ARM::t2MOVTi16_ga_pcrel: 5934d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie return 4; 5944d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie case ARM::MOVi32imm: 5954d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie case ARM::t2MOVi32imm: 5964d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie return 8; 5974d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie case ARM::CONSTPOOL_ENTRY: 5984d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie // If this machine instr is a constant pool entry, its size is recorded as 5994d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie // operand #2. 6004d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie return MI->getOperand(2).getImm(); 6014d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie case ARM::Int_eh_sjlj_longjmp: 6024d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie return 16; 6034d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie case ARM::tInt_eh_sjlj_longjmp: 6044d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie return 10; 6054d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie case ARM::Int_eh_sjlj_setjmp: 6064d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie case ARM::Int_eh_sjlj_setjmp_nofp: 6074d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie return 20; 6084d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie case ARM::tInt_eh_sjlj_setjmp: 6094d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie case ARM::t2Int_eh_sjlj_setjmp: 6104d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie case ARM::t2Int_eh_sjlj_setjmp_nofp: 6114d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie return 12; 6124d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie case ARM::BR_JTr: 6134d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie case ARM::BR_JTm: 6144d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie case ARM::BR_JTadd: 6154d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie case ARM::tBR_JTr: 6164d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie case ARM::t2BR_JT: 6174d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie case ARM::t2TBB_JT: 6184d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie case ARM::t2TBH_JT: { 6194d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie // These are jumptable branches, i.e. a branch followed by an inlined 6204d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie // jumptable. The size is 4 + 4 * number of entries. For TBB, each 6214d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie // entry is one byte; TBH two byte each. 6224d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie unsigned EntrySize = (Opc == ARM::t2TBB_JT) 6234d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie ? 1 : ((Opc == ARM::t2TBH_JT) ? 2 : 4); 6244d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie unsigned NumOps = MCID.getNumOperands(); 6254d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie MachineOperand JTOP = 6264d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie MI->getOperand(NumOps - (MI->isPredicable() ? 3 : 2)); 6274d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie unsigned JTI = JTOP.getIndex(); 6284d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo(); 629dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines assert(MJTI != nullptr); 6304d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables(); 6314d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie assert(JTI < JT.size()); 6324d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie // Thumb instructions are 2 byte aligned, but JT entries are 4 byte 6334d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie // 4 aligned. The assembler / linker may add 2 byte padding just before 6344d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie // the JT entries. The size does not include this padding; the 6354d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie // constant islands pass does separate bookkeeping for it. 6364d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie // FIXME: If we know the size of the function is less than (1 << 16) *2 6374d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie // bytes, we can use 16-bit entries instead. Then there won't be an 6384d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie // alignment issue. 6394d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie unsigned InstSize = (Opc == ARM::tBR_JTr || Opc == ARM::t2BR_JT) ? 2 : 4; 6404d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie unsigned NumEntries = getNumJTEntries(JT, JTI); 6414d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie if (Opc == ARM::t2TBB_JT && (NumEntries & 1)) 6424d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie // Make sure the instruction that follows TBB is 2-byte aligned. 6434d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie // FIXME: Constant island pass should insert an "ALIGN" instruction 6444d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie // instead. 6454d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie ++NumEntries; 6464d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie return NumEntries * EntrySize + InstSize; 6474d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie } 6484d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie } 649334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 650334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 651ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Chengunsigned ARMBaseInstrInfo::getInstBundleLength(const MachineInstr *MI) const { 652ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng unsigned Size = 0; 653ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng MachineBasicBlock::const_instr_iterator I = MI; 654ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end(); 655ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng while (++I != E && I->isInsideBundle()) { 656ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng assert(!I->isBundle() && "No nested bundle!"); 657ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng Size += GetInstSizeInBytes(&*I); 658ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng } 659ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng return Size; 660ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng} 661ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng 662ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesenvoid ARMBaseInstrInfo::copyPhysReg(MachineBasicBlock &MBB, 663ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen MachineBasicBlock::iterator I, DebugLoc DL, 664ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen unsigned DestReg, unsigned SrcReg, 665ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen bool KillSrc) const { 666ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen bool GPRDest = ARM::GPRRegClass.contains(DestReg); 6676c28682963e96699e7e0ab15282319c152bd6373Jim Grosbach bool GPRSrc = ARM::GPRRegClass.contains(SrcReg); 668ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen 669ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen if (GPRDest && GPRSrc) { 670ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen AddDefaultCC(AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::MOVr), DestReg) 6716c28682963e96699e7e0ab15282319c152bd6373Jim Grosbach .addReg(SrcReg, getKillRegState(KillSrc)))); 672ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen return; 6737bfdca0206f51132b26094c6f83a5ac97ee0f943David Goodwin } 674334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 675ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen bool SPRDest = ARM::SPRRegClass.contains(DestReg); 6766c28682963e96699e7e0ab15282319c152bd6373Jim Grosbach bool SPRSrc = ARM::SPRRegClass.contains(SrcReg); 677ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen 678e5038e191db82d4d92fdeec1b5bce5cae21f6d8fChad Rosier unsigned Opc = 0; 679142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen if (SPRDest && SPRSrc) 680ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen Opc = ARM::VMOVS; 681142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen else if (GPRDest && SPRSrc) 682ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen Opc = ARM::VMOVRS; 683ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen else if (SPRDest && GPRSrc) 684ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen Opc = ARM::VMOVSR; 685ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen else if (ARM::DPRRegClass.contains(DestReg, SrcReg)) 686ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen Opc = ARM::VMOVD; 687ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen else if (ARM::QPRRegClass.contains(DestReg, SrcReg)) 68843967a97cf9a296623e1cf5ed643e2f40b7e5766Owen Anderson Opc = ARM::VORRq; 689e5038e191db82d4d92fdeec1b5bce5cae21f6d8fChad Rosier 690e5038e191db82d4d92fdeec1b5bce5cae21f6d8fChad Rosier if (Opc) { 691e5038e191db82d4d92fdeec1b5bce5cae21f6d8fChad Rosier MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc), DestReg); 69243967a97cf9a296623e1cf5ed643e2f40b7e5766Owen Anderson MIB.addReg(SrcReg, getKillRegState(KillSrc)); 693e5038e191db82d4d92fdeec1b5bce5cae21f6d8fChad Rosier if (Opc == ARM::VORRq) 694e5038e191db82d4d92fdeec1b5bce5cae21f6d8fChad Rosier MIB.addReg(SrcReg, getKillRegState(KillSrc)); 695fea95c6bade86fcfa5bd07efdda9bd902f53be8cChad Rosier AddDefaultPred(MIB); 696e5038e191db82d4d92fdeec1b5bce5cae21f6d8fChad Rosier return; 697e5038e191db82d4d92fdeec1b5bce5cae21f6d8fChad Rosier } 698e5038e191db82d4d92fdeec1b5bce5cae21f6d8fChad Rosier 69985bdf2e76a0351468f231f48069c64bc6938f140Jakob Stoklund Olesen // Handle register classes that require multiple instructions. 70085bdf2e76a0351468f231f48069c64bc6938f140Jakob Stoklund Olesen unsigned BeginIdx = 0; 70185bdf2e76a0351468f231f48069c64bc6938f140Jakob Stoklund Olesen unsigned SubRegs = 0; 7027611a88b58e0a6960cdb5c72dc18a6c93e44cdc2Andrew Trick int Spacing = 1; 70385bdf2e76a0351468f231f48069c64bc6938f140Jakob Stoklund Olesen 70485bdf2e76a0351468f231f48069c64bc6938f140Jakob Stoklund Olesen // Use VORRq when possible. 7056c28682963e96699e7e0ab15282319c152bd6373Jim Grosbach if (ARM::QQPRRegClass.contains(DestReg, SrcReg)) { 7066c28682963e96699e7e0ab15282319c152bd6373Jim Grosbach Opc = ARM::VORRq; 7076c28682963e96699e7e0ab15282319c152bd6373Jim Grosbach BeginIdx = ARM::qsub_0; 7086c28682963e96699e7e0ab15282319c152bd6373Jim Grosbach SubRegs = 2; 7096c28682963e96699e7e0ab15282319c152bd6373Jim Grosbach } else if (ARM::QQQQPRRegClass.contains(DestReg, SrcReg)) { 7106c28682963e96699e7e0ab15282319c152bd6373Jim Grosbach Opc = ARM::VORRq; 7116c28682963e96699e7e0ab15282319c152bd6373Jim Grosbach BeginIdx = ARM::qsub_0; 7126c28682963e96699e7e0ab15282319c152bd6373Jim Grosbach SubRegs = 4; 71385bdf2e76a0351468f231f48069c64bc6938f140Jakob Stoklund Olesen // Fall back to VMOVD. 7146c28682963e96699e7e0ab15282319c152bd6373Jim Grosbach } else if (ARM::DPairRegClass.contains(DestReg, SrcReg)) { 7156c28682963e96699e7e0ab15282319c152bd6373Jim Grosbach Opc = ARM::VMOVD; 7166c28682963e96699e7e0ab15282319c152bd6373Jim Grosbach BeginIdx = ARM::dsub_0; 7176c28682963e96699e7e0ab15282319c152bd6373Jim Grosbach SubRegs = 2; 7186c28682963e96699e7e0ab15282319c152bd6373Jim Grosbach } else if (ARM::DTripleRegClass.contains(DestReg, SrcReg)) { 7196c28682963e96699e7e0ab15282319c152bd6373Jim Grosbach Opc = ARM::VMOVD; 7206c28682963e96699e7e0ab15282319c152bd6373Jim Grosbach BeginIdx = ARM::dsub_0; 7216c28682963e96699e7e0ab15282319c152bd6373Jim Grosbach SubRegs = 3; 7226c28682963e96699e7e0ab15282319c152bd6373Jim Grosbach } else if (ARM::DQuadRegClass.contains(DestReg, SrcReg)) { 7236c28682963e96699e7e0ab15282319c152bd6373Jim Grosbach Opc = ARM::VMOVD; 7246c28682963e96699e7e0ab15282319c152bd6373Jim Grosbach BeginIdx = ARM::dsub_0; 7256c28682963e96699e7e0ab15282319c152bd6373Jim Grosbach SubRegs = 4; 7266c28682963e96699e7e0ab15282319c152bd6373Jim Grosbach } else if (ARM::GPRPairRegClass.contains(DestReg, SrcReg)) { 7275b46ad4faf3216b4faaf30fa3a32f0af06f1ae36Jim Grosbach Opc = Subtarget.isThumb2() ? ARM::tMOVr : ARM::MOVr; 7286c28682963e96699e7e0ab15282319c152bd6373Jim Grosbach BeginIdx = ARM::gsub_0; 7296c28682963e96699e7e0ab15282319c152bd6373Jim Grosbach SubRegs = 2; 7306c28682963e96699e7e0ab15282319c152bd6373Jim Grosbach } else if (ARM::DPairSpcRegClass.contains(DestReg, SrcReg)) { 7316c28682963e96699e7e0ab15282319c152bd6373Jim Grosbach Opc = ARM::VMOVD; 7326c28682963e96699e7e0ab15282319c152bd6373Jim Grosbach BeginIdx = ARM::dsub_0; 7336c28682963e96699e7e0ab15282319c152bd6373Jim Grosbach SubRegs = 2; 7346c28682963e96699e7e0ab15282319c152bd6373Jim Grosbach Spacing = 2; 7356c28682963e96699e7e0ab15282319c152bd6373Jim Grosbach } else if (ARM::DTripleSpcRegClass.contains(DestReg, SrcReg)) { 7366c28682963e96699e7e0ab15282319c152bd6373Jim Grosbach Opc = ARM::VMOVD; 7376c28682963e96699e7e0ab15282319c152bd6373Jim Grosbach BeginIdx = ARM::dsub_0; 7386c28682963e96699e7e0ab15282319c152bd6373Jim Grosbach SubRegs = 3; 7396c28682963e96699e7e0ab15282319c152bd6373Jim Grosbach Spacing = 2; 7406c28682963e96699e7e0ab15282319c152bd6373Jim Grosbach } else if (ARM::DQuadSpcRegClass.contains(DestReg, SrcReg)) { 7416c28682963e96699e7e0ab15282319c152bd6373Jim Grosbach Opc = ARM::VMOVD; 7426c28682963e96699e7e0ab15282319c152bd6373Jim Grosbach BeginIdx = ARM::dsub_0; 7436c28682963e96699e7e0ab15282319c152bd6373Jim Grosbach SubRegs = 4; 7446c28682963e96699e7e0ab15282319c152bd6373Jim Grosbach Spacing = 2; 7456c28682963e96699e7e0ab15282319c152bd6373Jim Grosbach } 74685bdf2e76a0351468f231f48069c64bc6938f140Jakob Stoklund Olesen 7477611a88b58e0a6960cdb5c72dc18a6c93e44cdc2Andrew Trick assert(Opc && "Impossible reg-to-reg copy"); 748d79dedd458c1de07fbc568ea8c3b4194e94df48eAndrew Trick 749d79dedd458c1de07fbc568ea8c3b4194e94df48eAndrew Trick const TargetRegisterInfo *TRI = &getRegisterInfo(); 750d79dedd458c1de07fbc568ea8c3b4194e94df48eAndrew Trick MachineInstrBuilder Mov; 751f26e43df26bb7b0c7bf4853477e36611e2c90deaAndrew Trick 752f26e43df26bb7b0c7bf4853477e36611e2c90deaAndrew Trick // Copy register tuples backward when the first Dest reg overlaps with SrcReg. 753f26e43df26bb7b0c7bf4853477e36611e2c90deaAndrew Trick if (TRI->regsOverlap(SrcReg, TRI->getSubReg(DestReg, BeginIdx))) { 7546c28682963e96699e7e0ab15282319c152bd6373Jim Grosbach BeginIdx = BeginIdx + ((SubRegs - 1) * Spacing); 755f26e43df26bb7b0c7bf4853477e36611e2c90deaAndrew Trick Spacing = -Spacing; 756f26e43df26bb7b0c7bf4853477e36611e2c90deaAndrew Trick } 757f26e43df26bb7b0c7bf4853477e36611e2c90deaAndrew Trick#ifndef NDEBUG 758f26e43df26bb7b0c7bf4853477e36611e2c90deaAndrew Trick SmallSet<unsigned, 4> DstRegs; 759f26e43df26bb7b0c7bf4853477e36611e2c90deaAndrew Trick#endif 760d79dedd458c1de07fbc568ea8c3b4194e94df48eAndrew Trick for (unsigned i = 0; i != SubRegs; ++i) { 7616c28682963e96699e7e0ab15282319c152bd6373Jim Grosbach unsigned Dst = TRI->getSubReg(DestReg, BeginIdx + i * Spacing); 7626c28682963e96699e7e0ab15282319c152bd6373Jim Grosbach unsigned Src = TRI->getSubReg(SrcReg, BeginIdx + i * Spacing); 763d79dedd458c1de07fbc568ea8c3b4194e94df48eAndrew Trick assert(Dst && Src && "Bad sub-register"); 764f26e43df26bb7b0c7bf4853477e36611e2c90deaAndrew Trick#ifndef NDEBUG 765f26e43df26bb7b0c7bf4853477e36611e2c90deaAndrew Trick assert(!DstRegs.count(Src) && "destructive vector copy"); 7667611a88b58e0a6960cdb5c72dc18a6c93e44cdc2Andrew Trick DstRegs.insert(Dst); 767f26e43df26bb7b0c7bf4853477e36611e2c90deaAndrew Trick#endif 7686c28682963e96699e7e0ab15282319c152bd6373Jim Grosbach Mov = BuildMI(MBB, I, I->getDebugLoc(), get(Opc), Dst).addReg(Src); 769d79dedd458c1de07fbc568ea8c3b4194e94df48eAndrew Trick // VORR takes two source operands. 770d79dedd458c1de07fbc568ea8c3b4194e94df48eAndrew Trick if (Opc == ARM::VORRq) 771d79dedd458c1de07fbc568ea8c3b4194e94df48eAndrew Trick Mov.addReg(Src); 772d79dedd458c1de07fbc568ea8c3b4194e94df48eAndrew Trick Mov = AddDefaultPred(Mov); 7731b6f5a29ab62fd3e763983f31200b4cc69fa752bJF Bastien // MOVr can set CC. 7741b6f5a29ab62fd3e763983f31200b4cc69fa752bJF Bastien if (Opc == ARM::MOVr) 7751b6f5a29ab62fd3e763983f31200b4cc69fa752bJF Bastien Mov = AddDefaultCC(Mov); 776e5038e191db82d4d92fdeec1b5bce5cae21f6d8fChad Rosier } 777d79dedd458c1de07fbc568ea8c3b4194e94df48eAndrew Trick // Add implicit super-register defs and kills to the last instruction. 778d79dedd458c1de07fbc568ea8c3b4194e94df48eAndrew Trick Mov->addRegisterDefined(DestReg, TRI); 779d79dedd458c1de07fbc568ea8c3b4194e94df48eAndrew Trick if (KillSrc) 780d79dedd458c1de07fbc568ea8c3b4194e94df48eAndrew Trick Mov->addRegisterKilled(SrcReg, TRI); 781334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 782334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 7834cc1407b84dc6dbbc0d62b1d1b8db7c0ddec86ccTim Northoverconst MachineInstrBuilder & 7844cc1407b84dc6dbbc0d62b1d1b8db7c0ddec86ccTim NorthoverARMBaseInstrInfo::AddDReg(MachineInstrBuilder &MIB, unsigned Reg, 7854cc1407b84dc6dbbc0d62b1d1b8db7c0ddec86ccTim Northover unsigned SubIdx, unsigned State, 7864cc1407b84dc6dbbc0d62b1d1b8db7c0ddec86ccTim Northover const TargetRegisterInfo *TRI) const { 787c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Cheng if (!SubIdx) 788c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Cheng return MIB.addReg(Reg, State); 789c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Cheng 790c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Cheng if (TargetRegisterInfo::isPhysicalRegister(Reg)) 791c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Cheng return MIB.addReg(TRI->getSubReg(Reg, SubIdx), State); 792c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Cheng return MIB.addReg(Reg, State, SubIdx); 793c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Cheng} 794c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Cheng 795334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinvoid ARMBaseInstrInfo:: 796334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinstoreRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 797334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned SrcReg, bool isKill, int FI, 798746ad69e088176819981b4b2c5ac8dcd49f5e60eEvan Cheng const TargetRegisterClass *RC, 799746ad69e088176819981b4b2c5ac8dcd49f5e60eEvan Cheng const TargetRegisterInfo *TRI) const { 800c7f3ace20c325521c68335a1689645b43b06ddf0Chris Lattner DebugLoc DL; 801334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (I != MBB.end()) DL = I->getDebugLoc(); 802249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MachineFunction &MF = *MBB.getParent(); 803249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MachineFrameInfo &MFI = *MF.getFrameInfo(); 80431bc849123011b8eae6bb3c79876d9a3c26a6a1dJim Grosbach unsigned Align = MFI.getObjectAlignment(FI); 805249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov 806249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MachineMemOperand *MMO = 807978e0dfe46e481bfb1281e683aa308329e879e95Jay Foad MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FI), 80859db5496f4fc2ef6111569e542f8b65480ef14c1Chris Lattner MachineMemOperand::MOStore, 809249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MFI.getObjectSize(FI), 81031bc849123011b8eae6bb3c79876d9a3c26a6a1dJim Grosbach Align); 811334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 812e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson switch (RC->getSize()) { 813e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson case 4: 814e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson if (ARM::GPRRegClass.hasSubClassEq(RC)) { 815e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::STRi12)) 816334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(SrcReg, getKillRegState(isKill)) 8177e3383c007f53b3a00675af225e428cb66ddf404Jim Grosbach .addFrameIndex(FI).addImm(0).addMemOperand(MMO)); 818e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson } else if (ARM::SPRRegClass.hasSubClassEq(RC)) { 819e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTRS)) 820d31c5496d7e1580058b5c6fbc8fd537a641ea590Evan Cheng .addReg(SrcReg, getKillRegState(isKill)) 821d31c5496d7e1580058b5c6fbc8fd537a641ea590Evan Cheng .addFrameIndex(FI).addImm(0).addMemOperand(MMO)); 822e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson } else 823e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson llvm_unreachable("Unknown reg class!"); 824e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson break; 825e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson case 8: 826e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson if (ARM::DPRRegClass.hasSubClassEq(RC)) { 827e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTRD)) 828334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(SrcReg, getKillRegState(isKill)) 829249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov .addFrameIndex(FI).addImm(0).addMemOperand(MMO)); 830cd275f5687799e63956beabe35fc1718dc022f70Jakob Stoklund Olesen } else if (ARM::GPRPairRegClass.hasSubClassEq(RC)) { 8314cc1407b84dc6dbbc0d62b1d1b8db7c0ddec86ccTim Northover if (Subtarget.hasV5TEOps()) { 8324cc1407b84dc6dbbc0d62b1d1b8db7c0ddec86ccTim Northover MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::STRD)); 8334cc1407b84dc6dbbc0d62b1d1b8db7c0ddec86ccTim Northover AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill), TRI); 8344cc1407b84dc6dbbc0d62b1d1b8db7c0ddec86ccTim Northover AddDReg(MIB, SrcReg, ARM::gsub_1, 0, TRI); 8354cc1407b84dc6dbbc0d62b1d1b8db7c0ddec86ccTim Northover MIB.addFrameIndex(FI).addReg(0).addImm(0).addMemOperand(MMO); 8364cc1407b84dc6dbbc0d62b1d1b8db7c0ddec86ccTim Northover 8374cc1407b84dc6dbbc0d62b1d1b8db7c0ddec86ccTim Northover AddDefaultPred(MIB); 8384cc1407b84dc6dbbc0d62b1d1b8db7c0ddec86ccTim Northover } else { 8394cc1407b84dc6dbbc0d62b1d1b8db7c0ddec86ccTim Northover // Fallback to STM instruction, which has existed since the dawn of 8404cc1407b84dc6dbbc0d62b1d1b8db7c0ddec86ccTim Northover // time. 8414cc1407b84dc6dbbc0d62b1d1b8db7c0ddec86ccTim Northover MachineInstrBuilder MIB = 8424cc1407b84dc6dbbc0d62b1d1b8db7c0ddec86ccTim Northover AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::STMIA)) 8434cc1407b84dc6dbbc0d62b1d1b8db7c0ddec86ccTim Northover .addFrameIndex(FI).addMemOperand(MMO)); 8444cc1407b84dc6dbbc0d62b1d1b8db7c0ddec86ccTim Northover AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill), TRI); 8454cc1407b84dc6dbbc0d62b1d1b8db7c0ddec86ccTim Northover AddDReg(MIB, SrcReg, ARM::gsub_1, 0, TRI); 8464cc1407b84dc6dbbc0d62b1d1b8db7c0ddec86ccTim Northover } 847e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson } else 848e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson llvm_unreachable("Unknown reg class!"); 849e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson break; 850e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson case 16: 8515b2f9136644c58ae32e00d8317540692a697d1c9Jakob Stoklund Olesen if (ARM::DPairRegClass.hasSubClassEq(RC)) { 8527255a4e1332ccb69918ebe041dff05f9e4e5815dJakob Stoklund Olesen // Use aligned spills if the stack can be realigned. 8537255a4e1332ccb69918ebe041dff05f9e4e5815dJakob Stoklund Olesen if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) { 85428f08c93e75d291695ea89b9004145103292e85bJim Grosbach AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1q64)) 855f967ca0eaf30325cabe3c1971bf0dba16cf1b027Bob Wilson .addFrameIndex(FI).addImm(16) 85669b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng .addReg(SrcReg, getKillRegState(isKill)) 85769b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng .addMemOperand(MMO)); 858e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson } else { 859e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMQIA)) 86069b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng .addReg(SrcReg, getKillRegState(isKill)) 86169b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng .addFrameIndex(FI) 86269b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng .addMemOperand(MMO)); 863e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson } 864e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson } else 865e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson llvm_unreachable("Unknown reg class!"); 866e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson break; 867b58d7d03125526c152ade0c75be302b3c9eab997Anton Korobeynikov case 24: 868b58d7d03125526c152ade0c75be302b3c9eab997Anton Korobeynikov if (ARM::DTripleRegClass.hasSubClassEq(RC)) { 869b58d7d03125526c152ade0c75be302b3c9eab997Anton Korobeynikov // Use aligned spills if the stack can be realigned. 870b58d7d03125526c152ade0c75be302b3c9eab997Anton Korobeynikov if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) { 871b58d7d03125526c152ade0c75be302b3c9eab997Anton Korobeynikov AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1d64TPseudo)) 872b58d7d03125526c152ade0c75be302b3c9eab997Anton Korobeynikov .addFrameIndex(FI).addImm(16) 873b58d7d03125526c152ade0c75be302b3c9eab997Anton Korobeynikov .addReg(SrcReg, getKillRegState(isKill)) 874b58d7d03125526c152ade0c75be302b3c9eab997Anton Korobeynikov .addMemOperand(MMO)); 875b58d7d03125526c152ade0c75be302b3c9eab997Anton Korobeynikov } else { 876b58d7d03125526c152ade0c75be302b3c9eab997Anton Korobeynikov MachineInstrBuilder MIB = 877b58d7d03125526c152ade0c75be302b3c9eab997Anton Korobeynikov AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMDIA)) 878b58d7d03125526c152ade0c75be302b3c9eab997Anton Korobeynikov .addFrameIndex(FI)) 879b58d7d03125526c152ade0c75be302b3c9eab997Anton Korobeynikov .addMemOperand(MMO); 880b58d7d03125526c152ade0c75be302b3c9eab997Anton Korobeynikov MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI); 881b58d7d03125526c152ade0c75be302b3c9eab997Anton Korobeynikov MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI); 882b58d7d03125526c152ade0c75be302b3c9eab997Anton Korobeynikov AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI); 883b58d7d03125526c152ade0c75be302b3c9eab997Anton Korobeynikov } 884b58d7d03125526c152ade0c75be302b3c9eab997Anton Korobeynikov } else 885b58d7d03125526c152ade0c75be302b3c9eab997Anton Korobeynikov llvm_unreachable("Unknown reg class!"); 886b58d7d03125526c152ade0c75be302b3c9eab997Anton Korobeynikov break; 887e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson case 32: 888b58d7d03125526c152ade0c75be302b3c9eab997Anton Korobeynikov if (ARM::QQPRRegClass.hasSubClassEq(RC) || ARM::DQuadRegClass.hasSubClassEq(RC)) { 889e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) { 890e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson // FIXME: It's possible to only store part of the QQ register if the 891e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson // spilled def has a sub-register index. 892e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1d64QPseudo)) 893168f382dc67e5940cabdb28dc933c4f91cdd3137Bob Wilson .addFrameIndex(FI).addImm(16) 894168f382dc67e5940cabdb28dc933c4f91cdd3137Bob Wilson .addReg(SrcReg, getKillRegState(isKill)) 895168f382dc67e5940cabdb28dc933c4f91cdd3137Bob Wilson .addMemOperand(MMO)); 896e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson } else { 897e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson MachineInstrBuilder MIB = 898e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMDIA)) 89973fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling .addFrameIndex(FI)) 900e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson .addMemOperand(MMO); 901e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI); 902e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI); 903e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI); 904e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI); 905e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson } 906e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson } else 907e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson llvm_unreachable("Unknown reg class!"); 908e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson break; 909e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson case 64: 910e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson if (ARM::QQQQPRRegClass.hasSubClassEq(RC)) { 911e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson MachineInstrBuilder MIB = 912e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMDIA)) 913e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson .addFrameIndex(FI)) 914e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson .addMemOperand(MMO); 915e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI); 916e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI); 917e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI); 918e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson MIB = AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI); 919e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson MIB = AddDReg(MIB, SrcReg, ARM::dsub_4, 0, TRI); 920e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson MIB = AddDReg(MIB, SrcReg, ARM::dsub_5, 0, TRI); 921e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson MIB = AddDReg(MIB, SrcReg, ARM::dsub_6, 0, TRI); 922e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson AddDReg(MIB, SrcReg, ARM::dsub_7, 0, TRI); 923e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson } else 924e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson llvm_unreachable("Unknown reg class!"); 925e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson break; 926e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson default: 927e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson llvm_unreachable("Unknown reg class!"); 928334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 929334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 930334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 93134327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesenunsigned 93234327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund OlesenARMBaseInstrInfo::isStoreToStackSlot(const MachineInstr *MI, 93334327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen int &FrameIndex) const { 93434327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen switch (MI->getOpcode()) { 93534327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen default: break; 9367e3383c007f53b3a00675af225e428cb66ddf404Jim Grosbach case ARM::STRrs: 93734327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen case ARM::t2STRs: // FIXME: don't use t2STRs to access frame. 93834327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen if (MI->getOperand(1).isFI() && 93934327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen MI->getOperand(2).isReg() && 94034327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen MI->getOperand(3).isImm() && 94134327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen MI->getOperand(2).getReg() == 0 && 94234327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen MI->getOperand(3).getImm() == 0) { 94334327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen FrameIndex = MI->getOperand(1).getIndex(); 94434327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen return MI->getOperand(0).getReg(); 94534327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen } 94634327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen break; 9477e3383c007f53b3a00675af225e428cb66ddf404Jim Grosbach case ARM::STRi12: 94834327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen case ARM::t2STRi12: 94974472b4bf963c424da04f42dffdb94c85ef964bcJim Grosbach case ARM::tSTRspi: 95034327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen case ARM::VSTRD: 95134327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen case ARM::VSTRS: 95234327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen if (MI->getOperand(1).isFI() && 95334327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen MI->getOperand(2).isImm() && 95434327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen MI->getOperand(2).getImm() == 0) { 95534327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen FrameIndex = MI->getOperand(1).getIndex(); 95634327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen return MI->getOperand(0).getReg(); 95734327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen } 95834327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen break; 95928f08c93e75d291695ea89b9004145103292e85bJim Grosbach case ARM::VST1q64: 960161474d198d44ab505861c1ec55f022b27314b35Anton Korobeynikov case ARM::VST1d64TPseudo: 961161474d198d44ab505861c1ec55f022b27314b35Anton Korobeynikov case ARM::VST1d64QPseudo: 962d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen if (MI->getOperand(0).isFI() && 963d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen MI->getOperand(2).getSubReg() == 0) { 964d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen FrameIndex = MI->getOperand(0).getIndex(); 965d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen return MI->getOperand(2).getReg(); 966d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen } 96731bbc51ac9245bc82c933c9db8358ca9bb558ac5Jakob Stoklund Olesen break; 96873fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMQIA: 969d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen if (MI->getOperand(1).isFI() && 970d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen MI->getOperand(0).getSubReg() == 0) { 971d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen FrameIndex = MI->getOperand(1).getIndex(); 972d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen return MI->getOperand(0).getReg(); 973d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen } 974d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen break; 97534327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen } 97634327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen 97734327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen return 0; 97834327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen} 97934327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen 98036ee0e640554b8cc6ad1658fc3049e05d9967160Jakob Stoklund Olesenunsigned ARMBaseInstrInfo::isStoreToStackSlotPostFE(const MachineInstr *MI, 98136ee0e640554b8cc6ad1658fc3049e05d9967160Jakob Stoklund Olesen int &FrameIndex) const { 98236ee0e640554b8cc6ad1658fc3049e05d9967160Jakob Stoklund Olesen const MachineMemOperand *Dummy; 9835a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng return MI->mayStore() && hasStoreToStackSlot(MI, Dummy, FrameIndex); 98436ee0e640554b8cc6ad1658fc3049e05d9967160Jakob Stoklund Olesen} 98536ee0e640554b8cc6ad1658fc3049e05d9967160Jakob Stoklund Olesen 986334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinvoid ARMBaseInstrInfo:: 987334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinloadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 988334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned DestReg, int FI, 989746ad69e088176819981b4b2c5ac8dcd49f5e60eEvan Cheng const TargetRegisterClass *RC, 990746ad69e088176819981b4b2c5ac8dcd49f5e60eEvan Cheng const TargetRegisterInfo *TRI) const { 991c7f3ace20c325521c68335a1689645b43b06ddf0Chris Lattner DebugLoc DL; 992334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (I != MBB.end()) DL = I->getDebugLoc(); 993249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MachineFunction &MF = *MBB.getParent(); 994249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MachineFrameInfo &MFI = *MF.getFrameInfo(); 99531bc849123011b8eae6bb3c79876d9a3c26a6a1dJim Grosbach unsigned Align = MFI.getObjectAlignment(FI); 996249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MachineMemOperand *MMO = 99759db5496f4fc2ef6111569e542f8b65480ef14c1Chris Lattner MF.getMachineMemOperand( 998978e0dfe46e481bfb1281e683aa308329e879e95Jay Foad MachinePointerInfo::getFixedStack(FI), 99959db5496f4fc2ef6111569e542f8b65480ef14c1Chris Lattner MachineMemOperand::MOLoad, 1000249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MFI.getObjectSize(FI), 100131bc849123011b8eae6bb3c79876d9a3c26a6a1dJim Grosbach Align); 1002334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 1003e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson switch (RC->getSize()) { 1004e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson case 4: 1005e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson if (ARM::GPRRegClass.hasSubClassEq(RC)) { 1006e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::LDRi12), DestReg) 10073e5561247202bae994dd259a2d8dc4eff8f799f3Jim Grosbach .addFrameIndex(FI).addImm(0).addMemOperand(MMO)); 1008e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson 1009e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson } else if (ARM::SPRRegClass.hasSubClassEq(RC)) { 1010e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRS), DestReg) 1011d31c5496d7e1580058b5c6fbc8fd537a641ea590Evan Cheng .addFrameIndex(FI).addImm(0).addMemOperand(MMO)); 1012e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson } else 1013e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson llvm_unreachable("Unknown reg class!"); 1014ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson break; 1015e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson case 8: 1016e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson if (ARM::DPRRegClass.hasSubClassEq(RC)) { 1017e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRD), DestReg) 1018249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov .addFrameIndex(FI).addImm(0).addMemOperand(MMO)); 1019cd275f5687799e63956beabe35fc1718dc022f70Jakob Stoklund Olesen } else if (ARM::GPRPairRegClass.hasSubClassEq(RC)) { 10204cc1407b84dc6dbbc0d62b1d1b8db7c0ddec86ccTim Northover MachineInstrBuilder MIB; 10214cc1407b84dc6dbbc0d62b1d1b8db7c0ddec86ccTim Northover 10224cc1407b84dc6dbbc0d62b1d1b8db7c0ddec86ccTim Northover if (Subtarget.hasV5TEOps()) { 10234cc1407b84dc6dbbc0d62b1d1b8db7c0ddec86ccTim Northover MIB = BuildMI(MBB, I, DL, get(ARM::LDRD)); 10244cc1407b84dc6dbbc0d62b1d1b8db7c0ddec86ccTim Northover AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI); 10254cc1407b84dc6dbbc0d62b1d1b8db7c0ddec86ccTim Northover AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI); 10264cc1407b84dc6dbbc0d62b1d1b8db7c0ddec86ccTim Northover MIB.addFrameIndex(FI).addReg(0).addImm(0).addMemOperand(MMO); 10274cc1407b84dc6dbbc0d62b1d1b8db7c0ddec86ccTim Northover 10284cc1407b84dc6dbbc0d62b1d1b8db7c0ddec86ccTim Northover AddDefaultPred(MIB); 10294cc1407b84dc6dbbc0d62b1d1b8db7c0ddec86ccTim Northover } else { 10304cc1407b84dc6dbbc0d62b1d1b8db7c0ddec86ccTim Northover // Fallback to LDM instruction, which has existed since the dawn of 10314cc1407b84dc6dbbc0d62b1d1b8db7c0ddec86ccTim Northover // time. 10324cc1407b84dc6dbbc0d62b1d1b8db7c0ddec86ccTim Northover MIB = AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::LDMIA)) 10334cc1407b84dc6dbbc0d62b1d1b8db7c0ddec86ccTim Northover .addFrameIndex(FI).addMemOperand(MMO)); 10344cc1407b84dc6dbbc0d62b1d1b8db7c0ddec86ccTim Northover MIB = AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI); 10354cc1407b84dc6dbbc0d62b1d1b8db7c0ddec86ccTim Northover MIB = AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI); 10364cc1407b84dc6dbbc0d62b1d1b8db7c0ddec86ccTim Northover } 10374cc1407b84dc6dbbc0d62b1d1b8db7c0ddec86ccTim Northover 1038cd275f5687799e63956beabe35fc1718dc022f70Jakob Stoklund Olesen if (TargetRegisterInfo::isPhysicalRegister(DestReg)) 1039cd275f5687799e63956beabe35fc1718dc022f70Jakob Stoklund Olesen MIB.addReg(DestReg, RegState::ImplicitDefine); 1040e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson } else 1041e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson llvm_unreachable("Unknown reg class!"); 1042ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson break; 1043e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson case 16: 10445b2f9136644c58ae32e00d8317540692a697d1c9Jakob Stoklund Olesen if (ARM::DPairRegClass.hasSubClassEq(RC)) { 10457255a4e1332ccb69918ebe041dff05f9e4e5815dJakob Stoklund Olesen if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) { 104628f08c93e75d291695ea89b9004145103292e85bJim Grosbach AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1q64), DestReg) 1047f967ca0eaf30325cabe3c1971bf0dba16cf1b027Bob Wilson .addFrameIndex(FI).addImm(16) 104869b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng .addMemOperand(MMO)); 1049e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson } else { 1050e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMQIA), DestReg) 1051e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson .addFrameIndex(FI) 1052e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson .addMemOperand(MMO)); 1053e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson } 1054e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson } else 1055e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson llvm_unreachable("Unknown reg class!"); 1056ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson break; 1057b58d7d03125526c152ade0c75be302b3c9eab997Anton Korobeynikov case 24: 1058b58d7d03125526c152ade0c75be302b3c9eab997Anton Korobeynikov if (ARM::DTripleRegClass.hasSubClassEq(RC)) { 1059b58d7d03125526c152ade0c75be302b3c9eab997Anton Korobeynikov if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) { 1060b58d7d03125526c152ade0c75be302b3c9eab997Anton Korobeynikov AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1d64TPseudo), DestReg) 1061b58d7d03125526c152ade0c75be302b3c9eab997Anton Korobeynikov .addFrameIndex(FI).addImm(16) 1062b58d7d03125526c152ade0c75be302b3c9eab997Anton Korobeynikov .addMemOperand(MMO)); 1063b58d7d03125526c152ade0c75be302b3c9eab997Anton Korobeynikov } else { 1064b58d7d03125526c152ade0c75be302b3c9eab997Anton Korobeynikov MachineInstrBuilder MIB = 1065b58d7d03125526c152ade0c75be302b3c9eab997Anton Korobeynikov AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMDIA)) 1066b58d7d03125526c152ade0c75be302b3c9eab997Anton Korobeynikov .addFrameIndex(FI) 1067b58d7d03125526c152ade0c75be302b3c9eab997Anton Korobeynikov .addMemOperand(MMO)); 1068b58d7d03125526c152ade0c75be302b3c9eab997Anton Korobeynikov MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI); 1069b58d7d03125526c152ade0c75be302b3c9eab997Anton Korobeynikov MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI); 1070b58d7d03125526c152ade0c75be302b3c9eab997Anton Korobeynikov MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI); 1071b58d7d03125526c152ade0c75be302b3c9eab997Anton Korobeynikov if (TargetRegisterInfo::isPhysicalRegister(DestReg)) 1072b58d7d03125526c152ade0c75be302b3c9eab997Anton Korobeynikov MIB.addReg(DestReg, RegState::ImplicitDefine); 1073b58d7d03125526c152ade0c75be302b3c9eab997Anton Korobeynikov } 1074b58d7d03125526c152ade0c75be302b3c9eab997Anton Korobeynikov } else 1075b58d7d03125526c152ade0c75be302b3c9eab997Anton Korobeynikov llvm_unreachable("Unknown reg class!"); 1076b58d7d03125526c152ade0c75be302b3c9eab997Anton Korobeynikov break; 1077b58d7d03125526c152ade0c75be302b3c9eab997Anton Korobeynikov case 32: 1078b58d7d03125526c152ade0c75be302b3c9eab997Anton Korobeynikov if (ARM::QQPRRegClass.hasSubClassEq(RC) || ARM::DQuadRegClass.hasSubClassEq(RC)) { 1079e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) { 1080e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1d64QPseudo), DestReg) 1081168f382dc67e5940cabdb28dc933c4f91cdd3137Bob Wilson .addFrameIndex(FI).addImm(16) 1082168f382dc67e5940cabdb28dc933c4f91cdd3137Bob Wilson .addMemOperand(MMO)); 1083e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson } else { 1084e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson MachineInstrBuilder MIB = 108573fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMDIA)) 108673fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling .addFrameIndex(FI)) 1087e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson .addMemOperand(MMO); 1088fce711cb65716f86b4e150f42cbb597bbecf7dbeJakob Stoklund Olesen MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI); 1089fce711cb65716f86b4e150f42cbb597bbecf7dbeJakob Stoklund Olesen MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI); 1090fce711cb65716f86b4e150f42cbb597bbecf7dbeJakob Stoklund Olesen MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI); 1091fce711cb65716f86b4e150f42cbb597bbecf7dbeJakob Stoklund Olesen MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::DefineNoRead, TRI); 10923247af294996ff8588077c06505b64966ad41542Jakob Stoklund Olesen if (TargetRegisterInfo::isPhysicalRegister(DestReg)) 10933247af294996ff8588077c06505b64966ad41542Jakob Stoklund Olesen MIB.addReg(DestReg, RegState::ImplicitDefine); 1094e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson } 1095e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson } else 1096e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson llvm_unreachable("Unknown reg class!"); 1097ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson break; 1098e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson case 64: 1099e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson if (ARM::QQQQPRRegClass.hasSubClassEq(RC)) { 1100e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson MachineInstrBuilder MIB = 110173fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMDIA)) 110273fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling .addFrameIndex(FI)) 1103e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson .addMemOperand(MMO); 1104fce711cb65716f86b4e150f42cbb597bbecf7dbeJakob Stoklund Olesen MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI); 1105fce711cb65716f86b4e150f42cbb597bbecf7dbeJakob Stoklund Olesen MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI); 1106fce711cb65716f86b4e150f42cbb597bbecf7dbeJakob Stoklund Olesen MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI); 1107fce711cb65716f86b4e150f42cbb597bbecf7dbeJakob Stoklund Olesen MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::DefineNoRead, TRI); 1108fce711cb65716f86b4e150f42cbb597bbecf7dbeJakob Stoklund Olesen MIB = AddDReg(MIB, DestReg, ARM::dsub_4, RegState::DefineNoRead, TRI); 1109fce711cb65716f86b4e150f42cbb597bbecf7dbeJakob Stoklund Olesen MIB = AddDReg(MIB, DestReg, ARM::dsub_5, RegState::DefineNoRead, TRI); 1110fce711cb65716f86b4e150f42cbb597bbecf7dbeJakob Stoklund Olesen MIB = AddDReg(MIB, DestReg, ARM::dsub_6, RegState::DefineNoRead, TRI); 1111fce711cb65716f86b4e150f42cbb597bbecf7dbeJakob Stoklund Olesen MIB = AddDReg(MIB, DestReg, ARM::dsub_7, RegState::DefineNoRead, TRI); 11123247af294996ff8588077c06505b64966ad41542Jakob Stoklund Olesen if (TargetRegisterInfo::isPhysicalRegister(DestReg)) 11133247af294996ff8588077c06505b64966ad41542Jakob Stoklund Olesen MIB.addReg(DestReg, RegState::ImplicitDefine); 1114e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson } else 1115e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson llvm_unreachable("Unknown reg class!"); 1116ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson break; 1117ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson default: 1118ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson llvm_unreachable("Unknown regclass!"); 1119334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 1120334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 1121334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 112234327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesenunsigned 112334327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund OlesenARMBaseInstrInfo::isLoadFromStackSlot(const MachineInstr *MI, 112434327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen int &FrameIndex) const { 112534327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen switch (MI->getOpcode()) { 112634327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen default: break; 11273e5561247202bae994dd259a2d8dc4eff8f799f3Jim Grosbach case ARM::LDRrs: 112834327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen case ARM::t2LDRs: // FIXME: don't use t2LDRs to access frame. 112934327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen if (MI->getOperand(1).isFI() && 113034327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen MI->getOperand(2).isReg() && 113134327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen MI->getOperand(3).isImm() && 113234327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen MI->getOperand(2).getReg() == 0 && 113334327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen MI->getOperand(3).getImm() == 0) { 113434327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen FrameIndex = MI->getOperand(1).getIndex(); 113534327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen return MI->getOperand(0).getReg(); 113634327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen } 113734327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen break; 11383e5561247202bae994dd259a2d8dc4eff8f799f3Jim Grosbach case ARM::LDRi12: 113934327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen case ARM::t2LDRi12: 114074472b4bf963c424da04f42dffdb94c85ef964bcJim Grosbach case ARM::tLDRspi: 114134327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen case ARM::VLDRD: 114234327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen case ARM::VLDRS: 114334327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen if (MI->getOperand(1).isFI() && 114434327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen MI->getOperand(2).isImm() && 114534327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen MI->getOperand(2).getImm() == 0) { 114634327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen FrameIndex = MI->getOperand(1).getIndex(); 1147d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen return MI->getOperand(0).getReg(); 1148d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen } 1149d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen break; 115028f08c93e75d291695ea89b9004145103292e85bJim Grosbach case ARM::VLD1q64: 1151161474d198d44ab505861c1ec55f022b27314b35Anton Korobeynikov case ARM::VLD1d64TPseudo: 1152161474d198d44ab505861c1ec55f022b27314b35Anton Korobeynikov case ARM::VLD1d64QPseudo: 1153d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen if (MI->getOperand(1).isFI() && 1154d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen MI->getOperand(0).getSubReg() == 0) { 1155d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen FrameIndex = MI->getOperand(1).getIndex(); 115606f264e504d75f0426eea55b9f9e36c780d8a4fcJakob Stoklund Olesen return MI->getOperand(0).getReg(); 115706f264e504d75f0426eea55b9f9e36c780d8a4fcJakob Stoklund Olesen } 115806f264e504d75f0426eea55b9f9e36c780d8a4fcJakob Stoklund Olesen break; 115973fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMQIA: 116006f264e504d75f0426eea55b9f9e36c780d8a4fcJakob Stoklund Olesen if (MI->getOperand(1).isFI() && 116106f264e504d75f0426eea55b9f9e36c780d8a4fcJakob Stoklund Olesen MI->getOperand(0).getSubReg() == 0) { 116206f264e504d75f0426eea55b9f9e36c780d8a4fcJakob Stoklund Olesen FrameIndex = MI->getOperand(1).getIndex(); 116334327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen return MI->getOperand(0).getReg(); 116434327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen } 116534327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen break; 116634327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen } 116734327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen 116834327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen return 0; 116934327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen} 117034327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen 117136ee0e640554b8cc6ad1658fc3049e05d9967160Jakob Stoklund Olesenunsigned ARMBaseInstrInfo::isLoadFromStackSlotPostFE(const MachineInstr *MI, 117236ee0e640554b8cc6ad1658fc3049e05d9967160Jakob Stoklund Olesen int &FrameIndex) const { 117336ee0e640554b8cc6ad1658fc3049e05d9967160Jakob Stoklund Olesen const MachineMemOperand *Dummy; 11745a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng return MI->mayLoad() && hasLoadFromStackSlot(MI, Dummy, FrameIndex); 117536ee0e640554b8cc6ad1658fc3049e05d9967160Jakob Stoklund Olesen} 117636ee0e640554b8cc6ad1658fc3049e05d9967160Jakob Stoklund Olesen 1177142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesenbool ARMBaseInstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const{ 1178142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen // This hook gets to expand COPY instructions before they become 1179142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen // copyPhysReg() calls. Look for VMOVS instructions that can legally be 1180142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen // widened to VMOVD. We prefer the VMOVD when possible because it may be 1181142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen // changed into a VORR that can go down the NEON pipeline. 1182bcbf3fddef46f1f6e2f2408064c4b75e4b6c90f5Silviu Baranga if (!WidenVMOVS || !MI->isCopy() || Subtarget.isCortexA15()) 1183142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen return false; 1184142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen 1185142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen // Look for a copy between even S-registers. That is where we keep floats 1186142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen // when using NEON v2f32 instructions for f32 arithmetic. 1187142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen unsigned DstRegS = MI->getOperand(0).getReg(); 1188142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen unsigned SrcRegS = MI->getOperand(1).getReg(); 1189142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen if (!ARM::SPRRegClass.contains(DstRegS, SrcRegS)) 1190142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen return false; 1191142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen 1192142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen const TargetRegisterInfo *TRI = &getRegisterInfo(); 1193142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen unsigned DstRegD = TRI->getMatchingSuperReg(DstRegS, ARM::ssub_0, 1194142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen &ARM::DPRRegClass); 1195142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen unsigned SrcRegD = TRI->getMatchingSuperReg(SrcRegS, ARM::ssub_0, 1196142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen &ARM::DPRRegClass); 1197142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen if (!DstRegD || !SrcRegD) 1198142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen return false; 1199142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen 1200142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen // We want to widen this into a DstRegD = VMOVD SrcRegD copy. This is only 1201142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen // legal if the COPY already defines the full DstRegD, and it isn't a 1202142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen // sub-register insertion. 1203142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen if (!MI->definesRegister(DstRegD, TRI) || MI->readsRegister(DstRegD, TRI)) 1204142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen return false; 1205142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen 12061c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen // A dead copy shouldn't show up here, but reject it just in case. 12071c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen if (MI->getOperand(0).isDead()) 12081c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen return false; 12091c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen 12101c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen // All clear, widen the COPY. 1211142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen DEBUG(dbgs() << "widening: " << *MI); 121237a942cd52725b1d390989a8267a764b42fcb5d3Jakob Stoklund Olesen MachineInstrBuilder MIB(*MI->getParent()->getParent(), MI); 12131c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen 12141c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen // Get rid of the old <imp-def> of DstRegD. Leave it if it defines a Q-reg 12151c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen // or some other super-register. 12161c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen int ImpDefIdx = MI->findRegisterDefOperandIdx(DstRegD); 12171c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen if (ImpDefIdx != -1) 12181c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen MI->RemoveOperand(ImpDefIdx); 12191c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen 12201c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen // Change the opcode and operands. 1221142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen MI->setDesc(get(ARM::VMOVD)); 1222142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen MI->getOperand(0).setReg(DstRegD); 1223142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen MI->getOperand(1).setReg(SrcRegD); 122437a942cd52725b1d390989a8267a764b42fcb5d3Jakob Stoklund Olesen AddDefaultPred(MIB); 12251c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen 12261c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen // We are now reading SrcRegD instead of SrcRegS. This may upset the 12271c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen // register scavenger and machine verifier, so we need to indicate that we 12281c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen // are reading an undefined value from SrcRegD, but a proper value from 12291c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen // SrcRegS. 12301c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen MI->getOperand(1).setIsUndef(); 123137a942cd52725b1d390989a8267a764b42fcb5d3Jakob Stoklund Olesen MIB.addReg(SrcRegS, RegState::Implicit); 12321c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen 12331c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen // SrcRegD may actually contain an unrelated value in the ssub_1 12341c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen // sub-register. Don't kill it. Only kill the ssub_0 sub-register. 12351c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen if (MI->getOperand(1).isKill()) { 12361c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen MI->getOperand(1).setIsKill(false); 12371c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen MI->addRegisterKilled(SrcRegS, TRI, true); 12381c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen } 12391c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen 1240142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen DEBUG(dbgs() << "replaced by: " << *MI); 1241142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen return true; 1242142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen} 1243142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen 124430ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen/// Create a copy of a const pool value. Update CPI to the new index and return 124530ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen/// the label UID. 124630ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesenstatic unsigned duplicateCPV(MachineFunction &MF, unsigned &CPI) { 124730ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen MachineConstantPool *MCP = MF.getConstantPool(); 124830ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 124930ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen 125030ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPI]; 125130ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen assert(MCPE.isMachineConstantPoolEntry() && 125230ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen "Expecting a machine constantpool entry!"); 125330ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen ARMConstantPoolValue *ACPV = 125430ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal); 125530ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen 12565de5d4b6d0eb3fd379fa571d82f6fa764460b3b8Evan Cheng unsigned PCLabelId = AFI->createPICLabelUId(); 1257dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines ARMConstantPoolValue *NewCPV = nullptr; 125836b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines 125951f5b67395780b8421f4aa6ee998ed51b23dae9dJim Grosbach // FIXME: The below assumes PIC relocation model and that the function 126051f5b67395780b8421f4aa6ee998ed51b23dae9dJim Grosbach // is Thumb mode (t1 or t2). PCAdjustment would be 8 for ARM mode PIC, and 126151f5b67395780b8421f4aa6ee998ed51b23dae9dJim Grosbach // zero for non-PIC in ARM or Thumb. The callers are all of thumb LDR 126251f5b67395780b8421f4aa6ee998ed51b23dae9dJim Grosbach // instructions, so that's probably OK, but is PIC always correct when 126351f5b67395780b8421f4aa6ee998ed51b23dae9dJim Grosbach // we get here? 126430ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen if (ACPV->isGlobalValue()) 12655bb779976a7d8e48408051ec2289fe69206dc072Bill Wendling NewCPV = ARMConstantPoolConstant:: 12665bb779976a7d8e48408051ec2289fe69206dc072Bill Wendling Create(cast<ARMConstantPoolConstant>(ACPV)->getGV(), PCLabelId, 12675bb779976a7d8e48408051ec2289fe69206dc072Bill Wendling ARMCP::CPValue, 4); 126830ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen else if (ACPV->isExtSymbol()) 1269fe31e673506ef9a1080eaa684b43b34178c6f447Bill Wendling NewCPV = ARMConstantPoolSymbol:: 1270fe31e673506ef9a1080eaa684b43b34178c6f447Bill Wendling Create(MF.getFunction()->getContext(), 1271fe31e673506ef9a1080eaa684b43b34178c6f447Bill Wendling cast<ARMConstantPoolSymbol>(ACPV)->getSymbol(), PCLabelId, 4); 127230ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen else if (ACPV->isBlockAddress()) 12735bb779976a7d8e48408051ec2289fe69206dc072Bill Wendling NewCPV = ARMConstantPoolConstant:: 12745bb779976a7d8e48408051ec2289fe69206dc072Bill Wendling Create(cast<ARMConstantPoolConstant>(ACPV)->getBlockAddress(), PCLabelId, 12755bb779976a7d8e48408051ec2289fe69206dc072Bill Wendling ARMCP::CPBlockAddress, 4); 127651f5b67395780b8421f4aa6ee998ed51b23dae9dJim Grosbach else if (ACPV->isLSDA()) 12775bb779976a7d8e48408051ec2289fe69206dc072Bill Wendling NewCPV = ARMConstantPoolConstant::Create(MF.getFunction(), PCLabelId, 12785bb779976a7d8e48408051ec2289fe69206dc072Bill Wendling ARMCP::CPLSDA, 4); 1279e00897c5a91febe90ba21082fc636be892bf9bf1Bill Wendling else if (ACPV->isMachineBasicBlock()) 12803320f2a3bfd4daec23ba7ceb50525140cc6316daBill Wendling NewCPV = ARMConstantPoolMBB:: 12813320f2a3bfd4daec23ba7ceb50525140cc6316daBill Wendling Create(MF.getFunction()->getContext(), 12823320f2a3bfd4daec23ba7ceb50525140cc6316daBill Wendling cast<ARMConstantPoolMBB>(ACPV)->getMBB(), PCLabelId, 4); 128330ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen else 128430ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen llvm_unreachable("Unexpected ARM constantpool value type!!"); 128530ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen CPI = MCP->getConstantPoolIndex(NewCPV, MCPE.getAlignment()); 128630ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen return PCLabelId; 128730ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen} 128830ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen 1289fdc834046efd427d474e3b899ec69354c05071e0Evan Chengvoid ARMBaseInstrInfo:: 1290fdc834046efd427d474e3b899ec69354c05071e0Evan ChengreMaterialize(MachineBasicBlock &MBB, 1291fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng MachineBasicBlock::iterator I, 1292fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng unsigned DestReg, unsigned SubIdx, 1293d57cdd5683ea926e489067364fb7ffe5fd5d35eeEvan Cheng const MachineInstr *Orig, 12949edf7deb37f0f97664f279040fa15d89f32e23d9Jakob Stoklund Olesen const TargetRegisterInfo &TRI) const { 1295fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng unsigned Opcode = Orig->getOpcode(); 1296fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng switch (Opcode) { 1297fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng default: { 1298fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig); 12999edf7deb37f0f97664f279040fa15d89f32e23d9Jakob Stoklund Olesen MI->substituteRegister(Orig->getOperand(0).getReg(), DestReg, SubIdx, TRI); 1300fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng MBB.insert(I, MI); 1301fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng break; 1302fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng } 1303fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng case ARM::tLDRpci_pic: 1304fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng case ARM::t2LDRpci_pic: { 1305fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng MachineFunction &MF = *MBB.getParent(); 1306fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng unsigned CPI = Orig->getOperand(1).getIndex(); 130730ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen unsigned PCLabelId = duplicateCPV(MF, CPI); 1308fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng MachineInstrBuilder MIB = BuildMI(MBB, I, Orig->getDebugLoc(), get(Opcode), 1309fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng DestReg) 1310fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng .addConstantPoolIndex(CPI).addImm(PCLabelId); 1311d7d030a44796adc73a6eaa939cd17e52047734c1Chris Lattner MIB->setMemRefs(Orig->memoperands_begin(), Orig->memoperands_end()); 1312fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng break; 1313fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng } 1314fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng } 1315fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng} 1316fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng 131730ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund OlesenMachineInstr * 131830ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund OlesenARMBaseInstrInfo::duplicate(MachineInstr *Orig, MachineFunction &MF) const { 1319a9fa4fd9736f7d1066223f32fa54efbe86c0fcebJakob Stoklund Olesen MachineInstr *MI = TargetInstrInfo::duplicate(Orig, MF); 132030ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen switch(Orig->getOpcode()) { 132130ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen case ARM::tLDRpci_pic: 132230ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen case ARM::t2LDRpci_pic: { 132330ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen unsigned CPI = Orig->getOperand(1).getIndex(); 132430ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen unsigned PCLabelId = duplicateCPV(MF, CPI); 132530ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen Orig->getOperand(1).setIndex(CPI); 132630ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen Orig->getOperand(2).setImm(PCLabelId); 132730ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen break; 132830ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen } 132930ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen } 133030ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen return MI; 133130ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen} 133230ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen 1333506049f29f4f202a8e45feb916cc0264440a7f6dEvan Chengbool ARMBaseInstrInfo::produceSameValue(const MachineInstr *MI0, 13349fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng const MachineInstr *MI1, 13359fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng const MachineRegisterInfo *MRI) const { 1336d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng int Opcode = MI0->getOpcode(); 1337d7e3cc840b81b0438e47f05d9664137a198876dfEvan Cheng if (Opcode == ARM::t2LDRpci || 13389b82425cb0105fd5704f6b9bcd5e7693b05b1759Evan Cheng Opcode == ARM::t2LDRpci_pic || 13399b82425cb0105fd5704f6b9bcd5e7693b05b1759Evan Cheng Opcode == ARM::tLDRpci || 13409fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng Opcode == ARM::tLDRpci_pic || 134136b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines Opcode == ARM::LDRLIT_ga_pcrel || 134236b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines Opcode == ARM::LDRLIT_ga_pcrel_ldr || 134336b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines Opcode == ARM::tLDRLIT_ga_pcrel || 134453519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng Opcode == ARM::MOV_ga_pcrel || 134553519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng Opcode == ARM::MOV_ga_pcrel_ldr || 134653519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng Opcode == ARM::t2MOV_ga_pcrel) { 1347d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng if (MI1->getOpcode() != Opcode) 1348d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng return false; 1349d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng if (MI0->getNumOperands() != MI1->getNumOperands()) 1350d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng return false; 1351d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng 1352d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng const MachineOperand &MO0 = MI0->getOperand(1); 1353d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng const MachineOperand &MO1 = MI1->getOperand(1); 1354d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng if (MO0.getOffset() != MO1.getOffset()) 1355d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng return false; 1356d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng 135736b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines if (Opcode == ARM::LDRLIT_ga_pcrel || 135836b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines Opcode == ARM::LDRLIT_ga_pcrel_ldr || 135936b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines Opcode == ARM::tLDRLIT_ga_pcrel || 136053519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng Opcode == ARM::MOV_ga_pcrel || 136153519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng Opcode == ARM::MOV_ga_pcrel_ldr || 136253519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng Opcode == ARM::t2MOV_ga_pcrel) 13639fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng // Ignore the PC labels. 13649fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng return MO0.getGlobal() == MO1.getGlobal(); 13659fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng 1366d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng const MachineFunction *MF = MI0->getParent()->getParent(); 1367d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng const MachineConstantPool *MCP = MF->getConstantPool(); 1368d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng int CPI0 = MO0.getIndex(); 1369d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng int CPI1 = MO1.getIndex(); 1370d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng const MachineConstantPoolEntry &MCPE0 = MCP->getConstants()[CPI0]; 1371d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng const MachineConstantPoolEntry &MCPE1 = MCP->getConstants()[CPI1]; 1372d700617193f3d11deb83cd56c4ababbc8e0ea19fEvan Cheng bool isARMCP0 = MCPE0.isMachineConstantPoolEntry(); 1373d700617193f3d11deb83cd56c4ababbc8e0ea19fEvan Cheng bool isARMCP1 = MCPE1.isMachineConstantPoolEntry(); 1374d700617193f3d11deb83cd56c4ababbc8e0ea19fEvan Cheng if (isARMCP0 && isARMCP1) { 1375d700617193f3d11deb83cd56c4ababbc8e0ea19fEvan Cheng ARMConstantPoolValue *ACPV0 = 1376d700617193f3d11deb83cd56c4ababbc8e0ea19fEvan Cheng static_cast<ARMConstantPoolValue*>(MCPE0.Val.MachineCPVal); 1377d700617193f3d11deb83cd56c4ababbc8e0ea19fEvan Cheng ARMConstantPoolValue *ACPV1 = 1378d700617193f3d11deb83cd56c4ababbc8e0ea19fEvan Cheng static_cast<ARMConstantPoolValue*>(MCPE1.Val.MachineCPVal); 1379d700617193f3d11deb83cd56c4ababbc8e0ea19fEvan Cheng return ACPV0->hasSameValue(ACPV1); 1380d700617193f3d11deb83cd56c4ababbc8e0ea19fEvan Cheng } else if (!isARMCP0 && !isARMCP1) { 1381d700617193f3d11deb83cd56c4ababbc8e0ea19fEvan Cheng return MCPE0.Val.ConstVal == MCPE1.Val.ConstVal; 1382d700617193f3d11deb83cd56c4ababbc8e0ea19fEvan Cheng } 1383d700617193f3d11deb83cd56c4ababbc8e0ea19fEvan Cheng return false; 13849fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng } else if (Opcode == ARM::PICLDR) { 13859fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng if (MI1->getOpcode() != Opcode) 13869fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng return false; 13879fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng if (MI0->getNumOperands() != MI1->getNumOperands()) 13889fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng return false; 13899fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng 13909fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng unsigned Addr0 = MI0->getOperand(1).getReg(); 13919fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng unsigned Addr1 = MI1->getOperand(1).getReg(); 13929fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng if (Addr0 != Addr1) { 13939fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng if (!MRI || 13949fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng !TargetRegisterInfo::isVirtualRegister(Addr0) || 13959fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng !TargetRegisterInfo::isVirtualRegister(Addr1)) 13969fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng return false; 13979fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng 13989fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng // This assumes SSA form. 13999fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng MachineInstr *Def0 = MRI->getVRegDef(Addr0); 14009fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng MachineInstr *Def1 = MRI->getVRegDef(Addr1); 14019fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng // Check if the loaded value, e.g. a constantpool of a global address, are 14029fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng // the same. 14039fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng if (!produceSameValue(Def0, Def1, MRI)) 14049fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng return false; 14059fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng } 14069fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng 14079fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng for (unsigned i = 3, e = MI0->getNumOperands(); i != e; ++i) { 14089fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng // %vreg12<def> = PICLDR %vreg11, 0, pred:14, pred:%noreg 14099fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng const MachineOperand &MO0 = MI0->getOperand(i); 14109fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng const MachineOperand &MO1 = MI1->getOperand(i); 14119fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng if (!MO0.isIdenticalTo(MO1)) 14129fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng return false; 14139fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng } 14149fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng return true; 1415d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng } 1416d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng 1417506049f29f4f202a8e45feb916cc0264440a7f6dEvan Cheng return MI0->isIdenticalTo(MI1, MachineInstr::IgnoreVRegDefs); 1418d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng} 1419d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng 14204b722108e2cf8e77157e0879a23789cd44829933Bill Wendling/// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to 14214b722108e2cf8e77157e0879a23789cd44829933Bill Wendling/// determine if two loads are loading from the same base address. It should 14224b722108e2cf8e77157e0879a23789cd44829933Bill Wendling/// only return true if the base pointers are the same and the only differences 14234b722108e2cf8e77157e0879a23789cd44829933Bill Wendling/// between the two addresses is the offset. It also returns the offsets by 14244b722108e2cf8e77157e0879a23789cd44829933Bill Wendling/// reference. 14259b5caaa9c452f262a52dd5ac7ebbc722da5a63deAndrew Trick/// 14269b5caaa9c452f262a52dd5ac7ebbc722da5a63deAndrew Trick/// FIXME: remove this in favor of the MachineInstr interface once pre-RA-sched 14279b5caaa9c452f262a52dd5ac7ebbc722da5a63deAndrew Trick/// is permanently disabled. 14284b722108e2cf8e77157e0879a23789cd44829933Bill Wendlingbool ARMBaseInstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, 14294b722108e2cf8e77157e0879a23789cd44829933Bill Wendling int64_t &Offset1, 14304b722108e2cf8e77157e0879a23789cd44829933Bill Wendling int64_t &Offset2) const { 14314b722108e2cf8e77157e0879a23789cd44829933Bill Wendling // Don't worry about Thumb: just ARM and Thumb2. 14324b722108e2cf8e77157e0879a23789cd44829933Bill Wendling if (Subtarget.isThumb1Only()) return false; 14334b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 14344b722108e2cf8e77157e0879a23789cd44829933Bill Wendling if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode()) 14354b722108e2cf8e77157e0879a23789cd44829933Bill Wendling return false; 14364b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 14374b722108e2cf8e77157e0879a23789cd44829933Bill Wendling switch (Load1->getMachineOpcode()) { 14384b722108e2cf8e77157e0879a23789cd44829933Bill Wendling default: 14394b722108e2cf8e77157e0879a23789cd44829933Bill Wendling return false; 14403e5561247202bae994dd259a2d8dc4eff8f799f3Jim Grosbach case ARM::LDRi12: 1441c1d30212e911d1e55ff6b25bffefb503708883c3Jim Grosbach case ARM::LDRBi12: 14424b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::LDRD: 14434b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::LDRH: 14444b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::LDRSB: 14454b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::LDRSH: 14464b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::VLDRD: 14474b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::VLDRS: 14484b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::t2LDRi8: 1449dd34dc99fdf66edc52b5fc2ddf8132ebaa134aeeRenato Golin case ARM::t2LDRBi8: 14504b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::t2LDRDi8: 14514b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::t2LDRSHi8: 14524b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::t2LDRi12: 1453dd34dc99fdf66edc52b5fc2ddf8132ebaa134aeeRenato Golin case ARM::t2LDRBi12: 14544b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::t2LDRSHi12: 14554b722108e2cf8e77157e0879a23789cd44829933Bill Wendling break; 14564b722108e2cf8e77157e0879a23789cd44829933Bill Wendling } 14574b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 14584b722108e2cf8e77157e0879a23789cd44829933Bill Wendling switch (Load2->getMachineOpcode()) { 14594b722108e2cf8e77157e0879a23789cd44829933Bill Wendling default: 14604b722108e2cf8e77157e0879a23789cd44829933Bill Wendling return false; 14613e5561247202bae994dd259a2d8dc4eff8f799f3Jim Grosbach case ARM::LDRi12: 1462c1d30212e911d1e55ff6b25bffefb503708883c3Jim Grosbach case ARM::LDRBi12: 14634b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::LDRD: 14644b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::LDRH: 14654b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::LDRSB: 14664b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::LDRSH: 14674b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::VLDRD: 14684b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::VLDRS: 14694b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::t2LDRi8: 1470dd34dc99fdf66edc52b5fc2ddf8132ebaa134aeeRenato Golin case ARM::t2LDRBi8: 14714b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::t2LDRSHi8: 14724b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::t2LDRi12: 1473dd34dc99fdf66edc52b5fc2ddf8132ebaa134aeeRenato Golin case ARM::t2LDRBi12: 14744b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::t2LDRSHi12: 14754b722108e2cf8e77157e0879a23789cd44829933Bill Wendling break; 14764b722108e2cf8e77157e0879a23789cd44829933Bill Wendling } 14774b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 14784b722108e2cf8e77157e0879a23789cd44829933Bill Wendling // Check if base addresses and chain operands match. 14794b722108e2cf8e77157e0879a23789cd44829933Bill Wendling if (Load1->getOperand(0) != Load2->getOperand(0) || 14804b722108e2cf8e77157e0879a23789cd44829933Bill Wendling Load1->getOperand(4) != Load2->getOperand(4)) 14814b722108e2cf8e77157e0879a23789cd44829933Bill Wendling return false; 14824b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 14834b722108e2cf8e77157e0879a23789cd44829933Bill Wendling // Index should be Reg0. 14844b722108e2cf8e77157e0879a23789cd44829933Bill Wendling if (Load1->getOperand(3) != Load2->getOperand(3)) 14854b722108e2cf8e77157e0879a23789cd44829933Bill Wendling return false; 14864b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 14874b722108e2cf8e77157e0879a23789cd44829933Bill Wendling // Determine the offsets. 14884b722108e2cf8e77157e0879a23789cd44829933Bill Wendling if (isa<ConstantSDNode>(Load1->getOperand(1)) && 14894b722108e2cf8e77157e0879a23789cd44829933Bill Wendling isa<ConstantSDNode>(Load2->getOperand(1))) { 14904b722108e2cf8e77157e0879a23789cd44829933Bill Wendling Offset1 = cast<ConstantSDNode>(Load1->getOperand(1))->getSExtValue(); 14914b722108e2cf8e77157e0879a23789cd44829933Bill Wendling Offset2 = cast<ConstantSDNode>(Load2->getOperand(1))->getSExtValue(); 14924b722108e2cf8e77157e0879a23789cd44829933Bill Wendling return true; 14934b722108e2cf8e77157e0879a23789cd44829933Bill Wendling } 14944b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 14954b722108e2cf8e77157e0879a23789cd44829933Bill Wendling return false; 14964b722108e2cf8e77157e0879a23789cd44829933Bill Wendling} 14974b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 14984b722108e2cf8e77157e0879a23789cd44829933Bill Wendling/// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to 14997a2bdde0a0eebcd2125055e0eacaca040f0b766cChris Lattner/// determine (in conjunction with areLoadsFromSameBasePtr) if two loads should 15004b722108e2cf8e77157e0879a23789cd44829933Bill Wendling/// be scheduled togther. On some targets if two loads are loading from 15014b722108e2cf8e77157e0879a23789cd44829933Bill Wendling/// addresses in the same cache line, it's better if they are scheduled 15024b722108e2cf8e77157e0879a23789cd44829933Bill Wendling/// together. This function takes two integers that represent the load offsets 15034b722108e2cf8e77157e0879a23789cd44829933Bill Wendling/// from the common base address. It returns true if it decides it's desirable 15044b722108e2cf8e77157e0879a23789cd44829933Bill Wendling/// to schedule the two loads together. "NumLoads" is the number of loads that 15054b722108e2cf8e77157e0879a23789cd44829933Bill Wendling/// have already been scheduled after Load1. 15069b5caaa9c452f262a52dd5ac7ebbc722da5a63deAndrew Trick/// 15079b5caaa9c452f262a52dd5ac7ebbc722da5a63deAndrew Trick/// FIXME: remove this in favor of the MachineInstr interface once pre-RA-sched 15089b5caaa9c452f262a52dd5ac7ebbc722da5a63deAndrew Trick/// is permanently disabled. 15094b722108e2cf8e77157e0879a23789cd44829933Bill Wendlingbool ARMBaseInstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, 15104b722108e2cf8e77157e0879a23789cd44829933Bill Wendling int64_t Offset1, int64_t Offset2, 15114b722108e2cf8e77157e0879a23789cd44829933Bill Wendling unsigned NumLoads) const { 15124b722108e2cf8e77157e0879a23789cd44829933Bill Wendling // Don't worry about Thumb: just ARM and Thumb2. 15134b722108e2cf8e77157e0879a23789cd44829933Bill Wendling if (Subtarget.isThumb1Only()) return false; 15144b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 15154b722108e2cf8e77157e0879a23789cd44829933Bill Wendling assert(Offset2 > Offset1); 15164b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 15174b722108e2cf8e77157e0879a23789cd44829933Bill Wendling if ((Offset2 - Offset1) / 8 > 64) 15184b722108e2cf8e77157e0879a23789cd44829933Bill Wendling return false; 15194b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 1520dd34dc99fdf66edc52b5fc2ddf8132ebaa134aeeRenato Golin // Check if the machine opcodes are different. If they are different 1521dd34dc99fdf66edc52b5fc2ddf8132ebaa134aeeRenato Golin // then we consider them to not be of the same base address, 1522dd34dc99fdf66edc52b5fc2ddf8132ebaa134aeeRenato Golin // EXCEPT in the case of Thumb2 byte loads where one is LDRBi8 and the other LDRBi12. 1523dd34dc99fdf66edc52b5fc2ddf8132ebaa134aeeRenato Golin // In this case, they are considered to be the same because they are different 1524dd34dc99fdf66edc52b5fc2ddf8132ebaa134aeeRenato Golin // encoding forms of the same basic instruction. 1525dd34dc99fdf66edc52b5fc2ddf8132ebaa134aeeRenato Golin if ((Load1->getMachineOpcode() != Load2->getMachineOpcode()) && 1526dd34dc99fdf66edc52b5fc2ddf8132ebaa134aeeRenato Golin !((Load1->getMachineOpcode() == ARM::t2LDRBi8 && 1527dd34dc99fdf66edc52b5fc2ddf8132ebaa134aeeRenato Golin Load2->getMachineOpcode() == ARM::t2LDRBi12) || 1528dd34dc99fdf66edc52b5fc2ddf8132ebaa134aeeRenato Golin (Load1->getMachineOpcode() == ARM::t2LDRBi12 && 1529dd34dc99fdf66edc52b5fc2ddf8132ebaa134aeeRenato Golin Load2->getMachineOpcode() == ARM::t2LDRBi8))) 15304b722108e2cf8e77157e0879a23789cd44829933Bill Wendling return false; // FIXME: overly conservative? 15314b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 15324b722108e2cf8e77157e0879a23789cd44829933Bill Wendling // Four loads in a row should be sufficient. 15334b722108e2cf8e77157e0879a23789cd44829933Bill Wendling if (NumLoads >= 3) 15344b722108e2cf8e77157e0879a23789cd44829933Bill Wendling return false; 15354b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 15364b722108e2cf8e77157e0879a23789cd44829933Bill Wendling return true; 15374b722108e2cf8e77157e0879a23789cd44829933Bill Wendling} 15384b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 153986050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Chengbool ARMBaseInstrInfo::isSchedulingBoundary(const MachineInstr *MI, 154086050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng const MachineBasicBlock *MBB, 154186050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng const MachineFunction &MF) const { 154257bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach // Debug info is never a scheduling boundary. It's necessary to be explicit 154357bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach // due to the special treatment of IT instructions below, otherwise a 154457bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach // dbg_value followed by an IT will result in the IT instruction being 154557bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach // considered a scheduling hazard, which is wrong. It should be the actual 154657bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach // instruction preceding the dbg_value instruction(s), just like it is 154757bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach // when debug info is not present. 154857bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach if (MI->isDebugValue()) 154957bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach return false; 155057bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach 155186050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // Terminators and labels can't be scheduled around. 155236b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines if (MI->isTerminator() || MI->isPosition()) 155386050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng return true; 155486050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng 155586050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // Treat the start of the IT block as a scheduling boundary, but schedule 155686050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // t2IT along with all instructions following it. 155786050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // FIXME: This is a big hammer. But the alternative is to add all potential 155886050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // true and anti dependencies to IT block instructions as implicit operands 155986050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // to the t2IT instruction. The added compile time and complexity does not 156086050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // seem worth it. 156186050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng MachineBasicBlock::const_iterator I = MI; 156257bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach // Make sure to skip any dbg_value instructions 156357bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach while (++I != MBB->end() && I->isDebugValue()) 156457bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach ; 156557bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach if (I != MBB->end() && I->getOpcode() == ARM::t2IT) 156686050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng return true; 156786050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng 156886050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // Don't attempt to schedule around any instruction that defines 156986050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // a stack-oriented pointer, as it's unlikely to be profitable. This 157086050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // saves compile time, because it doesn't require every single 157186050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // stack slot reference to depend on the instruction that does the 157286050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // modification. 1573a1aa8db51715bdd21770fbe4f7d7abf2c5d28829Jakob Stoklund Olesen // Calls don't actually change the stack pointer, even if they have imp-defs. 1574209600bb8830036f981238494ab0188c25364837Jakob Stoklund Olesen // No ARM calling conventions change the stack pointer. (X86 calling 1575209600bb8830036f981238494ab0188c25364837Jakob Stoklund Olesen // conventions sometimes do). 1576a1aa8db51715bdd21770fbe4f7d7abf2c5d28829Jakob Stoklund Olesen if (!MI->isCall() && MI->definesRegister(ARM::SP)) 157786050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng return true; 157886050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng 157986050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng return false; 158086050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng} 158186050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng 1582f81b7f6069b27c0a515070dcb392f6828437412fJakub Staszakbool ARMBaseInstrInfo:: 1583f81b7f6069b27c0a515070dcb392f6828437412fJakub StaszakisProfitableToIfCvt(MachineBasicBlock &MBB, 1584f81b7f6069b27c0a515070dcb392f6828437412fJakub Staszak unsigned NumCycles, unsigned ExtraPredCycles, 1585f81b7f6069b27c0a515070dcb392f6828437412fJakub Staszak const BranchProbability &Probability) const { 15865876db7a66fcc4ec4444a9f3e387c1cdc8baf9e5Cameron Zwarich if (!NumCycles) 158713151432edace19ee867a93b5c14573df4f75d24Evan Cheng return false; 15882bbb76909126db5bed6bde84b16d94ab5de4d372Michael J. Spencer 1589b20b85168c0e9819e6545f08281e9b83c82108f0Owen Anderson // Attempt to estimate the relative costs of predication versus branching. 1590f81b7f6069b27c0a515070dcb392f6828437412fJakub Staszak unsigned UnpredCost = Probability.getNumerator() * NumCycles; 1591f81b7f6069b27c0a515070dcb392f6828437412fJakub Staszak UnpredCost /= Probability.getDenominator(); 1592f81b7f6069b27c0a515070dcb392f6828437412fJakub Staszak UnpredCost += 1; // The branch itself 1593f81b7f6069b27c0a515070dcb392f6828437412fJakub Staszak UnpredCost += Subtarget.getMispredictionPenalty() / 10; 15942bbb76909126db5bed6bde84b16d94ab5de4d372Michael J. Spencer 1595f81b7f6069b27c0a515070dcb392f6828437412fJakub Staszak return (NumCycles + ExtraPredCycles) <= UnpredCost; 159613151432edace19ee867a93b5c14573df4f75d24Evan Cheng} 15972bbb76909126db5bed6bde84b16d94ab5de4d372Michael J. Spencer 159813151432edace19ee867a93b5c14573df4f75d24Evan Chengbool ARMBaseInstrInfo:: 15998239daf7c83a65a189c352cce3191cdc3bbfe151Evan ChengisProfitableToIfCvt(MachineBasicBlock &TMBB, 16008239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng unsigned TCycles, unsigned TExtra, 16018239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng MachineBasicBlock &FMBB, 16028239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng unsigned FCycles, unsigned FExtra, 1603f81b7f6069b27c0a515070dcb392f6828437412fJakub Staszak const BranchProbability &Probability) const { 16048239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng if (!TCycles || !FCycles) 1605b20b85168c0e9819e6545f08281e9b83c82108f0Owen Anderson return false; 16062bbb76909126db5bed6bde84b16d94ab5de4d372Michael J. Spencer 1607b20b85168c0e9819e6545f08281e9b83c82108f0Owen Anderson // Attempt to estimate the relative costs of predication versus branching. 1608f81b7f6069b27c0a515070dcb392f6828437412fJakub Staszak unsigned TUnpredCost = Probability.getNumerator() * TCycles; 1609f81b7f6069b27c0a515070dcb392f6828437412fJakub Staszak TUnpredCost /= Probability.getDenominator(); 1610e23dc9c0ef50b0a1934c04c1786f3a0478d62f41Andrew Trick 1611f81b7f6069b27c0a515070dcb392f6828437412fJakub Staszak uint32_t Comp = Probability.getDenominator() - Probability.getNumerator(); 1612f81b7f6069b27c0a515070dcb392f6828437412fJakub Staszak unsigned FUnpredCost = Comp * FCycles; 1613f81b7f6069b27c0a515070dcb392f6828437412fJakub Staszak FUnpredCost /= Probability.getDenominator(); 1614f81b7f6069b27c0a515070dcb392f6828437412fJakub Staszak 1615f81b7f6069b27c0a515070dcb392f6828437412fJakub Staszak unsigned UnpredCost = TUnpredCost + FUnpredCost; 1616f81b7f6069b27c0a515070dcb392f6828437412fJakub Staszak UnpredCost += 1; // The branch itself 1617f81b7f6069b27c0a515070dcb392f6828437412fJakub Staszak UnpredCost += Subtarget.getMispredictionPenalty() / 10; 1618f81b7f6069b27c0a515070dcb392f6828437412fJakub Staszak 1619f81b7f6069b27c0a515070dcb392f6828437412fJakub Staszak return (TCycles + FCycles + TExtra + FExtra) <= UnpredCost; 162013151432edace19ee867a93b5c14573df4f75d24Evan Cheng} 162113151432edace19ee867a93b5c14573df4f75d24Evan Cheng 1622eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilsonbool 1623eb1641d54a7eda7717304bc4d55d059208d8ebedBob WilsonARMBaseInstrInfo::isProfitableToUnpredicate(MachineBasicBlock &TMBB, 1624eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson MachineBasicBlock &FMBB) const { 1625eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson // Reduce false anti-dependencies to let Swift's out-of-order execution 1626eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson // engine do its thing. 1627eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson return Subtarget.isSwift(); 1628eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson} 1629eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson 16308fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng/// getInstrPredicate - If instruction is predicated, returns its predicate 16318fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng/// condition, otherwise returns AL. It also returns the condition code 16328fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng/// register by reference. 16335adb66a646e2ec32265263739f5b01c3f50c176aEvan ChengARMCC::CondCodes 16345adb66a646e2ec32265263739f5b01c3f50c176aEvan Chengllvm::getInstrPredicate(const MachineInstr *MI, unsigned &PredReg) { 16358fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng int PIdx = MI->findFirstPredOperandIdx(); 16368fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng if (PIdx == -1) { 16378fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng PredReg = 0; 16388fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng return ARMCC::AL; 16398fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng } 16408fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng 16418fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng PredReg = MI->getOperand(PIdx+1).getReg(); 16428fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng return (ARMCC::CondCodes)MI->getOperand(PIdx).getImm(); 16438fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng} 16448fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng 16458fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng 16466495f63945e8dbde81f03a1dc2ab421993b9a495Evan Chengint llvm::getMatchingCondBranchOpcode(int Opc) { 16475ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng if (Opc == ARM::B) 16485ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng return ARM::Bcc; 16494d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie if (Opc == ARM::tB) 16505ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng return ARM::tBcc; 16514d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie if (Opc == ARM::t2B) 16524d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie return ARM::t2Bcc; 16535ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng 16545ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng llvm_unreachable("Unknown unconditional branch opcode!"); 16555ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng} 16565ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng 1657c5041cac7d3aeaa7350abadf2a7ada92e8da27dcJakob Stoklund Olesen/// commuteInstruction - Handle commutable instructions. 1658c5041cac7d3aeaa7350abadf2a7ada92e8da27dcJakob Stoklund OlesenMachineInstr * 1659c5041cac7d3aeaa7350abadf2a7ada92e8da27dcJakob Stoklund OlesenARMBaseInstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const { 1660c5041cac7d3aeaa7350abadf2a7ada92e8da27dcJakob Stoklund Olesen switch (MI->getOpcode()) { 1661c5041cac7d3aeaa7350abadf2a7ada92e8da27dcJakob Stoklund Olesen case ARM::MOVCCr: 1662c5041cac7d3aeaa7350abadf2a7ada92e8da27dcJakob Stoklund Olesen case ARM::t2MOVCCr: { 1663c5041cac7d3aeaa7350abadf2a7ada92e8da27dcJakob Stoklund Olesen // MOVCC can be commuted by inverting the condition. 1664c5041cac7d3aeaa7350abadf2a7ada92e8da27dcJakob Stoklund Olesen unsigned PredReg = 0; 1665c5041cac7d3aeaa7350abadf2a7ada92e8da27dcJakob Stoklund Olesen ARMCC::CondCodes CC = getInstrPredicate(MI, PredReg); 1666c5041cac7d3aeaa7350abadf2a7ada92e8da27dcJakob Stoklund Olesen // MOVCC AL can't be inverted. Shouldn't happen. 1667c5041cac7d3aeaa7350abadf2a7ada92e8da27dcJakob Stoklund Olesen if (CC == ARMCC::AL || PredReg != ARM::CPSR) 1668dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines return nullptr; 1669a9fa4fd9736f7d1066223f32fa54efbe86c0fcebJakob Stoklund Olesen MI = TargetInstrInfo::commuteInstruction(MI, NewMI); 1670c5041cac7d3aeaa7350abadf2a7ada92e8da27dcJakob Stoklund Olesen if (!MI) 1671dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines return nullptr; 1672c5041cac7d3aeaa7350abadf2a7ada92e8da27dcJakob Stoklund Olesen // After swapping the MOVCC operands, also invert the condition. 1673c5041cac7d3aeaa7350abadf2a7ada92e8da27dcJakob Stoklund Olesen MI->getOperand(MI->findFirstPredOperandIdx()) 1674c5041cac7d3aeaa7350abadf2a7ada92e8da27dcJakob Stoklund Olesen .setImm(ARMCC::getOppositeCondition(CC)); 1675c5041cac7d3aeaa7350abadf2a7ada92e8da27dcJakob Stoklund Olesen return MI; 1676c5041cac7d3aeaa7350abadf2a7ada92e8da27dcJakob Stoklund Olesen } 1677c5041cac7d3aeaa7350abadf2a7ada92e8da27dcJakob Stoklund Olesen } 1678a9fa4fd9736f7d1066223f32fa54efbe86c0fcebJakob Stoklund Olesen return TargetInstrInfo::commuteInstruction(MI, NewMI); 1679c5041cac7d3aeaa7350abadf2a7ada92e8da27dcJakob Stoklund Olesen} 16806495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 16812860b7ea3a1d60213ee7228bd274bc4f8b170772Jakob Stoklund Olesen/// Identify instructions that can be folded into a MOVCC instruction, and 1682098c6a547fe540b3bbace4c3d4713f400c67b8a9Jakob Stoklund Olesen/// return the defining instruction. 1683098c6a547fe540b3bbace4c3d4713f400c67b8a9Jakob Stoklund Olesenstatic MachineInstr *canFoldIntoMOVCC(unsigned Reg, 1684098c6a547fe540b3bbace4c3d4713f400c67b8a9Jakob Stoklund Olesen const MachineRegisterInfo &MRI, 1685098c6a547fe540b3bbace4c3d4713f400c67b8a9Jakob Stoklund Olesen const TargetInstrInfo *TII) { 16862860b7ea3a1d60213ee7228bd274bc4f8b170772Jakob Stoklund Olesen if (!TargetRegisterInfo::isVirtualRegister(Reg)) 1687dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines return nullptr; 16882860b7ea3a1d60213ee7228bd274bc4f8b170772Jakob Stoklund Olesen if (!MRI.hasOneNonDBGUse(Reg)) 1689dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines return nullptr; 1690098c6a547fe540b3bbace4c3d4713f400c67b8a9Jakob Stoklund Olesen MachineInstr *MI = MRI.getVRegDef(Reg); 16912860b7ea3a1d60213ee7228bd274bc4f8b170772Jakob Stoklund Olesen if (!MI) 1692dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines return nullptr; 1693098c6a547fe540b3bbace4c3d4713f400c67b8a9Jakob Stoklund Olesen // MI is folded into the MOVCC by predicating it. 1694098c6a547fe540b3bbace4c3d4713f400c67b8a9Jakob Stoklund Olesen if (!MI->isPredicable()) 1695dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines return nullptr; 16962860b7ea3a1d60213ee7228bd274bc4f8b170772Jakob Stoklund Olesen // Check if MI has any non-dead defs or physreg uses. This also detects 16972860b7ea3a1d60213ee7228bd274bc4f8b170772Jakob Stoklund Olesen // predicated instructions which will be reading CPSR. 16982860b7ea3a1d60213ee7228bd274bc4f8b170772Jakob Stoklund Olesen for (unsigned i = 1, e = MI->getNumOperands(); i != e; ++i) { 16992860b7ea3a1d60213ee7228bd274bc4f8b170772Jakob Stoklund Olesen const MachineOperand &MO = MI->getOperand(i); 1700a7fb3f68047556a7355e1f1080fb3d1ca9eb7078Jakob Stoklund Olesen // Reject frame index operands, PEI can't handle the predicated pseudos. 1701a7fb3f68047556a7355e1f1080fb3d1ca9eb7078Jakob Stoklund Olesen if (MO.isFI() || MO.isCPI() || MO.isJTI()) 1702dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines return nullptr; 17032860b7ea3a1d60213ee7228bd274bc4f8b170772Jakob Stoklund Olesen if (!MO.isReg()) 17042860b7ea3a1d60213ee7228bd274bc4f8b170772Jakob Stoklund Olesen continue; 1705098c6a547fe540b3bbace4c3d4713f400c67b8a9Jakob Stoklund Olesen // MI can't have any tied operands, that would conflict with predication. 1706098c6a547fe540b3bbace4c3d4713f400c67b8a9Jakob Stoklund Olesen if (MO.isTied()) 1707dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines return nullptr; 17082860b7ea3a1d60213ee7228bd274bc4f8b170772Jakob Stoklund Olesen if (TargetRegisterInfo::isPhysicalRegister(MO.getReg())) 1709dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines return nullptr; 17102860b7ea3a1d60213ee7228bd274bc4f8b170772Jakob Stoklund Olesen if (MO.isDef() && !MO.isDead()) 1711dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines return nullptr; 17122860b7ea3a1d60213ee7228bd274bc4f8b170772Jakob Stoklund Olesen } 1713098c6a547fe540b3bbace4c3d4713f400c67b8a9Jakob Stoklund Olesen bool DontMoveAcrossStores = true; 1714dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines if (!MI->isSafeToMove(TII, /* AliasAnalysis = */ nullptr, 1715dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines DontMoveAcrossStores)) 1716dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines return nullptr; 1717098c6a547fe540b3bbace4c3d4713f400c67b8a9Jakob Stoklund Olesen return MI; 17182860b7ea3a1d60213ee7228bd274bc4f8b170772Jakob Stoklund Olesen} 17192860b7ea3a1d60213ee7228bd274bc4f8b170772Jakob Stoklund Olesen 1720053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesenbool ARMBaseInstrInfo::analyzeSelect(const MachineInstr *MI, 1721053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen SmallVectorImpl<MachineOperand> &Cond, 1722053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen unsigned &TrueOp, unsigned &FalseOp, 1723053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen bool &Optimizable) const { 1724053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen assert((MI->getOpcode() == ARM::MOVCCr || MI->getOpcode() == ARM::t2MOVCCr) && 1725053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen "Unknown select instruction"); 1726053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen // MOVCC operands: 1727053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen // 0: Def. 1728053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen // 1: True use. 1729053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen // 2: False use. 1730053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen // 3: Condition code. 1731053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen // 4: CPSR use. 1732053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen TrueOp = 1; 1733053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen FalseOp = 2; 1734053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen Cond.push_back(MI->getOperand(3)); 1735053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen Cond.push_back(MI->getOperand(4)); 1736053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen // We can always fold a def. 1737053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen Optimizable = true; 1738053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen return false; 1739053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen} 1740053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen 1741053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund OlesenMachineInstr *ARMBaseInstrInfo::optimizeSelect(MachineInstr *MI, 1742053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen bool PreferFalse) const { 1743053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen assert((MI->getOpcode() == ARM::MOVCCr || MI->getOpcode() == ARM::t2MOVCCr) && 1744053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen "Unknown select instruction"); 1745d1bd8d904c5adbe14f700be02f1e6479b5a6d04bMatthias Braun MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo(); 1746098c6a547fe540b3bbace4c3d4713f400c67b8a9Jakob Stoklund Olesen MachineInstr *DefMI = canFoldIntoMOVCC(MI->getOperand(2).getReg(), MRI, this); 1747098c6a547fe540b3bbace4c3d4713f400c67b8a9Jakob Stoklund Olesen bool Invert = !DefMI; 1748098c6a547fe540b3bbace4c3d4713f400c67b8a9Jakob Stoklund Olesen if (!DefMI) 1749098c6a547fe540b3bbace4c3d4713f400c67b8a9Jakob Stoklund Olesen DefMI = canFoldIntoMOVCC(MI->getOperand(1).getReg(), MRI, this); 1750098c6a547fe540b3bbace4c3d4713f400c67b8a9Jakob Stoklund Olesen if (!DefMI) 1751dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines return nullptr; 1752053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen 1753d1bd8d904c5adbe14f700be02f1e6479b5a6d04bMatthias Braun // Find new register class to use. 1754d1bd8d904c5adbe14f700be02f1e6479b5a6d04bMatthias Braun MachineOperand FalseReg = MI->getOperand(Invert ? 2 : 1); 1755d1bd8d904c5adbe14f700be02f1e6479b5a6d04bMatthias Braun unsigned DestReg = MI->getOperand(0).getReg(); 1756d1bd8d904c5adbe14f700be02f1e6479b5a6d04bMatthias Braun const TargetRegisterClass *PreviousClass = MRI.getRegClass(FalseReg.getReg()); 1757d1bd8d904c5adbe14f700be02f1e6479b5a6d04bMatthias Braun if (!MRI.constrainRegClass(DestReg, PreviousClass)) 1758dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines return nullptr; 1759d1bd8d904c5adbe14f700be02f1e6479b5a6d04bMatthias Braun 1760053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen // Create a new predicated version of DefMI. 1761053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen // Rfalse is the first use. 1762053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen MachineInstrBuilder NewMI = BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), 1763d1bd8d904c5adbe14f700be02f1e6479b5a6d04bMatthias Braun DefMI->getDesc(), DestReg); 1764053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen 1765053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen // Copy all the DefMI operands, excluding its (null) predicate. 1766053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen const MCInstrDesc &DefDesc = DefMI->getDesc(); 1767053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen for (unsigned i = 1, e = DefDesc.getNumOperands(); 1768053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen i != e && !DefDesc.OpInfo[i].isPredicate(); ++i) 1769053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen NewMI.addOperand(DefMI->getOperand(i)); 1770053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen 1771053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen unsigned CondCode = MI->getOperand(3).getImm(); 1772053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen if (Invert) 1773053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen NewMI.addImm(ARMCC::getOppositeCondition(ARMCC::CondCodes(CondCode))); 1774053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen else 1775053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen NewMI.addImm(CondCode); 1776053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen NewMI.addOperand(MI->getOperand(4)); 1777053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen 1778053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen // DefMI is not the -S version that sets CPSR, so add an optional %noreg. 1779053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen if (NewMI->hasOptionalDef()) 1780053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen AddDefaultCC(NewMI); 1781053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen 1782098c6a547fe540b3bbace4c3d4713f400c67b8a9Jakob Stoklund Olesen // The output register value when the predicate is false is an implicit 1783098c6a547fe540b3bbace4c3d4713f400c67b8a9Jakob Stoklund Olesen // register operand tied to the first def. 1784098c6a547fe540b3bbace4c3d4713f400c67b8a9Jakob Stoklund Olesen // The tie makes the register allocator ensure the FalseReg is allocated the 1785098c6a547fe540b3bbace4c3d4713f400c67b8a9Jakob Stoklund Olesen // same register as operand 0. 1786098c6a547fe540b3bbace4c3d4713f400c67b8a9Jakob Stoklund Olesen FalseReg.setImplicit(); 1787b9efafe54d61e85ca5209c4043aa814f89785195Jakob Stoklund Olesen NewMI.addOperand(FalseReg); 1788098c6a547fe540b3bbace4c3d4713f400c67b8a9Jakob Stoklund Olesen NewMI->tieOperands(0, NewMI->getNumOperands() - 1); 1789098c6a547fe540b3bbace4c3d4713f400c67b8a9Jakob Stoklund Olesen 1790053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen // The caller will erase MI, but not DefMI. 1791053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen DefMI->eraseFromParent(); 1792053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen return NewMI; 1793053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen} 1794053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen 17953be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick/// Map pseudo instructions that imply an 'S' bit onto real opcodes. Whether the 17963be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick/// instruction is encoded with an 'S' bit is determined by the optional CPSR 17973be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick/// def operand. 17983be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick/// 17993be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick/// This will go away once we can teach tblgen how to set the optional CPSR def 18003be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick/// operand itself. 18013be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trickstruct AddSubFlagsOpcodePair { 1802cd2859eef83708c00330c94f6842499b48d5ed02Craig Topper uint16_t PseudoOpc; 1803cd2859eef83708c00330c94f6842499b48d5ed02Craig Topper uint16_t MachineOpc; 18043be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick}; 18053be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick 1806cd2859eef83708c00330c94f6842499b48d5ed02Craig Topperstatic const AddSubFlagsOpcodePair AddSubFlagsOpcodeMap[] = { 18073be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick {ARM::ADDSri, ARM::ADDri}, 18083be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick {ARM::ADDSrr, ARM::ADDrr}, 18093be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick {ARM::ADDSrsi, ARM::ADDrsi}, 18103be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick {ARM::ADDSrsr, ARM::ADDrsr}, 18113be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick 18123be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick {ARM::SUBSri, ARM::SUBri}, 18133be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick {ARM::SUBSrr, ARM::SUBrr}, 18143be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick {ARM::SUBSrsi, ARM::SUBrsi}, 18153be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick {ARM::SUBSrsr, ARM::SUBrsr}, 18163be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick 18173be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick {ARM::RSBSri, ARM::RSBri}, 18183be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick {ARM::RSBSrsi, ARM::RSBrsi}, 18193be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick {ARM::RSBSrsr, ARM::RSBrsr}, 18203be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick 18213be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick {ARM::t2ADDSri, ARM::t2ADDri}, 18223be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick {ARM::t2ADDSrr, ARM::t2ADDrr}, 18233be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick {ARM::t2ADDSrs, ARM::t2ADDrs}, 18243be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick 18253be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick {ARM::t2SUBSri, ARM::t2SUBri}, 18263be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick {ARM::t2SUBSrr, ARM::t2SUBrr}, 18273be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick {ARM::t2SUBSrs, ARM::t2SUBrs}, 18283be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick 18293be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick {ARM::t2RSBSri, ARM::t2RSBri}, 18303be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick {ARM::t2RSBSrs, ARM::t2RSBrs}, 18313be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick}; 18323be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick 18333be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trickunsigned llvm::convertAddSubFlagsOpcode(unsigned OldOpc) { 1834cd2859eef83708c00330c94f6842499b48d5ed02Craig Topper for (unsigned i = 0, e = array_lengthof(AddSubFlagsOpcodeMap); i != e; ++i) 1835cd2859eef83708c00330c94f6842499b48d5ed02Craig Topper if (OldOpc == AddSubFlagsOpcodeMap[i].PseudoOpc) 1836cd2859eef83708c00330c94f6842499b48d5ed02Craig Topper return AddSubFlagsOpcodeMap[i].MachineOpc; 18373be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick return 0; 18383be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick} 18393be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick 18406495f63945e8dbde81f03a1dc2ab421993b9a495Evan Chengvoid llvm::emitARMRegPlusImmediate(MachineBasicBlock &MBB, 18416495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MachineBasicBlock::iterator &MBBI, DebugLoc dl, 18426495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned DestReg, unsigned BaseReg, int NumBytes, 18436495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ARMCC::CondCodes Pred, unsigned PredReg, 184457caad7a33ff145b71545f10dcfbbf2fd0f595d3Anton Korobeynikov const ARMBaseInstrInfo &TII, unsigned MIFlags) { 1845e53abc20724ddde4e91467671328b531361a734fTim Northover if (NumBytes == 0 && DestReg != BaseReg) { 1846e53abc20724ddde4e91467671328b531361a734fTim Northover BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), DestReg) 1847e53abc20724ddde4e91467671328b531361a734fTim Northover .addReg(BaseReg, RegState::Kill) 1848e53abc20724ddde4e91467671328b531361a734fTim Northover .addImm((unsigned)Pred).addReg(PredReg).addReg(0) 1849e53abc20724ddde4e91467671328b531361a734fTim Northover .setMIFlags(MIFlags); 1850e53abc20724ddde4e91467671328b531361a734fTim Northover return; 1851e53abc20724ddde4e91467671328b531361a734fTim Northover } 1852e53abc20724ddde4e91467671328b531361a734fTim Northover 18536495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng bool isSub = NumBytes < 0; 18546495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (isSub) NumBytes = -NumBytes; 18556495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 18566495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng while (NumBytes) { 18576495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned RotAmt = ARM_AM::getSOImmValRotate(NumBytes); 18586495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned ThisVal = NumBytes & ARM_AM::rotr32(0xFF, RotAmt); 18596495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng assert(ThisVal && "Didn't extract field correctly"); 18606495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 18616495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // We will handle these bits from offset, clear them. 18626495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng NumBytes &= ~ThisVal; 18636495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 18646495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng assert(ARM_AM::getSOImmVal(ThisVal) != -1 && "Bit extraction didn't work?"); 18656495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 18666495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Build the new ADD / SUB. 18676495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned Opc = isSub ? ARM::SUBri : ARM::ADDri; 18686495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg) 18696495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng .addReg(BaseReg, RegState::Kill).addImm(ThisVal) 187057caad7a33ff145b71545f10dcfbbf2fd0f595d3Anton Korobeynikov .addImm((unsigned)Pred).addReg(PredReg).addReg(0) 187157caad7a33ff145b71545f10dcfbbf2fd0f595d3Anton Korobeynikov .setMIFlags(MIFlags); 18726495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng BaseReg = DestReg; 18736495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 18746495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng} 18756495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 187636b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hinesstatic bool isAnySubRegLive(unsigned Reg, const TargetRegisterInfo *TRI, 187736b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines MachineInstr *MI) { 187836b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines for (MCSubRegIterator Subreg(Reg, TRI, /* IncludeSelf */ true); 187936b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines Subreg.isValid(); ++Subreg) 188036b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines if (MI->getParent()->computeRegisterLiveness(TRI, *Subreg, MI) != 188136b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines MachineBasicBlock::LQR_Dead) 188236b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines return true; 188336b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines return false; 188436b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines} 188536b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hinesbool llvm::tryFoldSPUpdateIntoPushPop(const ARMSubtarget &Subtarget, 188636b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines MachineFunction &MF, MachineInstr *MI, 1887323ac85d6ad7ba5d9593d8e151d879bd91d82e08Tim Northover unsigned NumBytes) { 1888323ac85d6ad7ba5d9593d8e151d879bd91d82e08Tim Northover // This optimisation potentially adds lots of load and store 1889323ac85d6ad7ba5d9593d8e151d879bd91d82e08Tim Northover // micro-operations, it's only really a great benefit to code-size. 1890cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen Hines if (!MF.getFunction()->getAttributes().hasAttribute( 1891cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen Hines AttributeSet::FunctionIndex, Attribute::MinSize)) 1892323ac85d6ad7ba5d9593d8e151d879bd91d82e08Tim Northover return false; 1893323ac85d6ad7ba5d9593d8e151d879bd91d82e08Tim Northover 1894323ac85d6ad7ba5d9593d8e151d879bd91d82e08Tim Northover // If only one register is pushed/popped, LLVM can use an LDR/STR 1895323ac85d6ad7ba5d9593d8e151d879bd91d82e08Tim Northover // instead. We can't modify those so make sure we're dealing with an 1896323ac85d6ad7ba5d9593d8e151d879bd91d82e08Tim Northover // instruction we understand. 1897323ac85d6ad7ba5d9593d8e151d879bd91d82e08Tim Northover bool IsPop = isPopOpcode(MI->getOpcode()); 1898323ac85d6ad7ba5d9593d8e151d879bd91d82e08Tim Northover bool IsPush = isPushOpcode(MI->getOpcode()); 1899323ac85d6ad7ba5d9593d8e151d879bd91d82e08Tim Northover if (!IsPush && !IsPop) 1900323ac85d6ad7ba5d9593d8e151d879bd91d82e08Tim Northover return false; 1901323ac85d6ad7ba5d9593d8e151d879bd91d82e08Tim Northover 1902323ac85d6ad7ba5d9593d8e151d879bd91d82e08Tim Northover bool IsVFPPushPop = MI->getOpcode() == ARM::VSTMDDB_UPD || 1903323ac85d6ad7ba5d9593d8e151d879bd91d82e08Tim Northover MI->getOpcode() == ARM::VLDMDIA_UPD; 1904323ac85d6ad7ba5d9593d8e151d879bd91d82e08Tim Northover bool IsT1PushPop = MI->getOpcode() == ARM::tPUSH || 1905323ac85d6ad7ba5d9593d8e151d879bd91d82e08Tim Northover MI->getOpcode() == ARM::tPOP || 1906323ac85d6ad7ba5d9593d8e151d879bd91d82e08Tim Northover MI->getOpcode() == ARM::tPOP_RET; 1907323ac85d6ad7ba5d9593d8e151d879bd91d82e08Tim Northover 1908323ac85d6ad7ba5d9593d8e151d879bd91d82e08Tim Northover assert((IsT1PushPop || (MI->getOperand(0).getReg() == ARM::SP && 1909323ac85d6ad7ba5d9593d8e151d879bd91d82e08Tim Northover MI->getOperand(1).getReg() == ARM::SP)) && 1910323ac85d6ad7ba5d9593d8e151d879bd91d82e08Tim Northover "trying to fold sp update into non-sp-updating push/pop"); 1911323ac85d6ad7ba5d9593d8e151d879bd91d82e08Tim Northover 1912323ac85d6ad7ba5d9593d8e151d879bd91d82e08Tim Northover // The VFP push & pop act on D-registers, so we can only fold an adjustment 1913323ac85d6ad7ba5d9593d8e151d879bd91d82e08Tim Northover // by a multiple of 8 bytes in correctly. Similarly rN is 4-bytes. Don't try 1914323ac85d6ad7ba5d9593d8e151d879bd91d82e08Tim Northover // if this is violated. 1915323ac85d6ad7ba5d9593d8e151d879bd91d82e08Tim Northover if (NumBytes % (IsVFPPushPop ? 8 : 4) != 0) 1916323ac85d6ad7ba5d9593d8e151d879bd91d82e08Tim Northover return false; 1917323ac85d6ad7ba5d9593d8e151d879bd91d82e08Tim Northover 1918323ac85d6ad7ba5d9593d8e151d879bd91d82e08Tim Northover // ARM and Thumb2 push/pop insts have explicit "sp, sp" operands (+ 1919323ac85d6ad7ba5d9593d8e151d879bd91d82e08Tim Northover // pred) so the list starts at 4. Thumb1 starts after the predicate. 1920323ac85d6ad7ba5d9593d8e151d879bd91d82e08Tim Northover int RegListIdx = IsT1PushPop ? 2 : 4; 1921323ac85d6ad7ba5d9593d8e151d879bd91d82e08Tim Northover 1922323ac85d6ad7ba5d9593d8e151d879bd91d82e08Tim Northover // Calculate the space we'll need in terms of registers. 1923323ac85d6ad7ba5d9593d8e151d879bd91d82e08Tim Northover unsigned FirstReg = MI->getOperand(RegListIdx).getReg(); 1924323ac85d6ad7ba5d9593d8e151d879bd91d82e08Tim Northover unsigned RD0Reg, RegsNeeded; 1925323ac85d6ad7ba5d9593d8e151d879bd91d82e08Tim Northover if (IsVFPPushPop) { 1926323ac85d6ad7ba5d9593d8e151d879bd91d82e08Tim Northover RD0Reg = ARM::D0; 1927323ac85d6ad7ba5d9593d8e151d879bd91d82e08Tim Northover RegsNeeded = NumBytes / 8; 1928323ac85d6ad7ba5d9593d8e151d879bd91d82e08Tim Northover } else { 1929323ac85d6ad7ba5d9593d8e151d879bd91d82e08Tim Northover RD0Reg = ARM::R0; 1930323ac85d6ad7ba5d9593d8e151d879bd91d82e08Tim Northover RegsNeeded = NumBytes / 4; 1931323ac85d6ad7ba5d9593d8e151d879bd91d82e08Tim Northover } 1932323ac85d6ad7ba5d9593d8e151d879bd91d82e08Tim Northover 1933323ac85d6ad7ba5d9593d8e151d879bd91d82e08Tim Northover // We're going to have to strip all list operands off before 1934323ac85d6ad7ba5d9593d8e151d879bd91d82e08Tim Northover // re-adding them since the order matters, so save the existing ones 1935323ac85d6ad7ba5d9593d8e151d879bd91d82e08Tim Northover // for later. 1936323ac85d6ad7ba5d9593d8e151d879bd91d82e08Tim Northover SmallVector<MachineOperand, 4> RegList; 1937323ac85d6ad7ba5d9593d8e151d879bd91d82e08Tim Northover for (int i = MI->getNumOperands() - 1; i >= RegListIdx; --i) 1938323ac85d6ad7ba5d9593d8e151d879bd91d82e08Tim Northover RegList.push_back(MI->getOperand(i)); 1939323ac85d6ad7ba5d9593d8e151d879bd91d82e08Tim Northover 1940323ac85d6ad7ba5d9593d8e151d879bd91d82e08Tim Northover const TargetRegisterInfo *TRI = MF.getRegInfo().getTargetRegisterInfo(); 19411b26fdbf1f01e90b803cc035b6b932cd95c76830Bill Wendling const MCPhysReg *CSRegs = TRI->getCalleeSavedRegs(&MF); 1942323ac85d6ad7ba5d9593d8e151d879bd91d82e08Tim Northover 1943323ac85d6ad7ba5d9593d8e151d879bd91d82e08Tim Northover // Now try to find enough space in the reglist to allocate NumBytes. 1944323ac85d6ad7ba5d9593d8e151d879bd91d82e08Tim Northover for (unsigned CurReg = FirstReg - 1; CurReg >= RD0Reg && RegsNeeded; 19451b26fdbf1f01e90b803cc035b6b932cd95c76830Bill Wendling --CurReg) { 1946323ac85d6ad7ba5d9593d8e151d879bd91d82e08Tim Northover if (!IsPop) { 1947323ac85d6ad7ba5d9593d8e151d879bd91d82e08Tim Northover // Pushing any register is completely harmless, mark the 1948323ac85d6ad7ba5d9593d8e151d879bd91d82e08Tim Northover // register involved as undef since we don't care about it in 1949323ac85d6ad7ba5d9593d8e151d879bd91d82e08Tim Northover // the slightest. 1950323ac85d6ad7ba5d9593d8e151d879bd91d82e08Tim Northover RegList.push_back(MachineOperand::CreateReg(CurReg, false, false, 1951323ac85d6ad7ba5d9593d8e151d879bd91d82e08Tim Northover false, false, true)); 19521b26fdbf1f01e90b803cc035b6b932cd95c76830Bill Wendling --RegsNeeded; 1953323ac85d6ad7ba5d9593d8e151d879bd91d82e08Tim Northover continue; 1954323ac85d6ad7ba5d9593d8e151d879bd91d82e08Tim Northover } 1955323ac85d6ad7ba5d9593d8e151d879bd91d82e08Tim Northover 19561b26fdbf1f01e90b803cc035b6b932cd95c76830Bill Wendling // However, we can only pop an extra register if it's not live. For 19571b26fdbf1f01e90b803cc035b6b932cd95c76830Bill Wendling // registers live within the function we might clobber a return value 19581b26fdbf1f01e90b803cc035b6b932cd95c76830Bill Wendling // register; the other way a register can be live here is if it's 19591b26fdbf1f01e90b803cc035b6b932cd95c76830Bill Wendling // callee-saved. 196036b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines // TODO: Currently, computeRegisterLiveness() does not report "live" if a 196136b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines // sub reg is live. When computeRegisterLiveness() works for sub reg, it 196236b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines // can replace isAnySubRegLive(). 19631b26fdbf1f01e90b803cc035b6b932cd95c76830Bill Wendling if (isCalleeSavedRegister(CurReg, CSRegs) || 196436b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines isAnySubRegLive(CurReg, TRI, MI)) { 19651b26fdbf1f01e90b803cc035b6b932cd95c76830Bill Wendling // VFP pops don't allow holes in the register list, so any skip is fatal 19661b26fdbf1f01e90b803cc035b6b932cd95c76830Bill Wendling // for our transformation. GPR pops do, so we should just keep looking. 19671b26fdbf1f01e90b803cc035b6b932cd95c76830Bill Wendling if (IsVFPPushPop) 19681b26fdbf1f01e90b803cc035b6b932cd95c76830Bill Wendling return false; 19691b26fdbf1f01e90b803cc035b6b932cd95c76830Bill Wendling else 19701b26fdbf1f01e90b803cc035b6b932cd95c76830Bill Wendling continue; 19711b26fdbf1f01e90b803cc035b6b932cd95c76830Bill Wendling } 1972323ac85d6ad7ba5d9593d8e151d879bd91d82e08Tim Northover 1973323ac85d6ad7ba5d9593d8e151d879bd91d82e08Tim Northover // Mark the unimportant registers as <def,dead> in the POP. 19743d238de4d54eb0b16afd96a57f49f92b2f7748e0Bill Wendling RegList.push_back(MachineOperand::CreateReg(CurReg, true, false, false, 19753d238de4d54eb0b16afd96a57f49f92b2f7748e0Bill Wendling true)); 19761b26fdbf1f01e90b803cc035b6b932cd95c76830Bill Wendling --RegsNeeded; 1977323ac85d6ad7ba5d9593d8e151d879bd91d82e08Tim Northover } 1978323ac85d6ad7ba5d9593d8e151d879bd91d82e08Tim Northover 1979323ac85d6ad7ba5d9593d8e151d879bd91d82e08Tim Northover if (RegsNeeded > 0) 1980323ac85d6ad7ba5d9593d8e151d879bd91d82e08Tim Northover return false; 1981323ac85d6ad7ba5d9593d8e151d879bd91d82e08Tim Northover 1982323ac85d6ad7ba5d9593d8e151d879bd91d82e08Tim Northover // Finally we know we can profitably perform the optimisation so go 1983323ac85d6ad7ba5d9593d8e151d879bd91d82e08Tim Northover // ahead: strip all existing registers off and add them back again 1984323ac85d6ad7ba5d9593d8e151d879bd91d82e08Tim Northover // in the right order. 1985323ac85d6ad7ba5d9593d8e151d879bd91d82e08Tim Northover for (int i = MI->getNumOperands() - 1; i >= RegListIdx; --i) 1986323ac85d6ad7ba5d9593d8e151d879bd91d82e08Tim Northover MI->RemoveOperand(i); 1987323ac85d6ad7ba5d9593d8e151d879bd91d82e08Tim Northover 1988323ac85d6ad7ba5d9593d8e151d879bd91d82e08Tim Northover // Add the complete list back in. 1989323ac85d6ad7ba5d9593d8e151d879bd91d82e08Tim Northover MachineInstrBuilder MIB(MF, &*MI); 1990323ac85d6ad7ba5d9593d8e151d879bd91d82e08Tim Northover for (int i = RegList.size() - 1; i >= 0; --i) 1991323ac85d6ad7ba5d9593d8e151d879bd91d82e08Tim Northover MIB.addOperand(RegList[i]); 1992323ac85d6ad7ba5d9593d8e151d879bd91d82e08Tim Northover 1993323ac85d6ad7ba5d9593d8e151d879bd91d82e08Tim Northover return true; 1994323ac85d6ad7ba5d9593d8e151d879bd91d82e08Tim Northover} 1995323ac85d6ad7ba5d9593d8e151d879bd91d82e08Tim Northover 1996cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Chengbool llvm::rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx, 1997cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng unsigned FrameReg, int &Offset, 1998cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng const ARMBaseInstrInfo &TII) { 19996495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned Opcode = MI.getOpcode(); 2000e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng const MCInstrDesc &Desc = MI.getDesc(); 20016495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask); 20026495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng bool isSub = false; 2003764ab52dd80310a205c9888bf166d09dab858f90Jim Grosbach 20046495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Memory operands in inline assembly always use AddrMode2. 20056495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (Opcode == ARM::INLINEASM) 20066495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng AddrMode = ARMII::AddrMode2; 2007764ab52dd80310a205c9888bf166d09dab858f90Jim Grosbach 20086495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (Opcode == ARM::ADDri) { 20096495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng Offset += MI.getOperand(FrameRegIdx+1).getImm(); 20106495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (Offset == 0) { 20116495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Turn it into a move. 20126495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MI.setDesc(TII.get(ARM::MOVr)); 20136495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false); 20146495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MI.RemoveOperand(FrameRegIdx+1); 2015cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng Offset = 0; 2016cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng return true; 20176495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } else if (Offset < 0) { 20186495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng Offset = -Offset; 20196495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng isSub = true; 20206495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MI.setDesc(TII.get(ARM::SUBri)); 20216495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 20226495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 20236495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Common case: small offset, fits into instruction. 20246495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (ARM_AM::getSOImmVal(Offset) != -1) { 20256495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Replace the FrameIndex with sp / fp 20266495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false); 20276495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset); 2028cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng Offset = 0; 2029cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng return true; 20306495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 20316495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 20326495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Otherwise, pull as much of the immedidate into this ADDri/SUBri 20336495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // as possible. 20346495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned RotAmt = ARM_AM::getSOImmValRotate(Offset); 20356495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xFF, RotAmt); 20366495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 20376495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // We will handle these bits from offset, clear them. 20386495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng Offset &= ~ThisImmVal; 20396495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 20406495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Get the properly encoded SOImmVal field. 20416495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng assert(ARM_AM::getSOImmVal(ThisImmVal) != -1 && 20426495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng "Bit extraction didn't work?"); 20436495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MI.getOperand(FrameRegIdx+1).ChangeToImmediate(ThisImmVal); 20446495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } else { 20456495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned ImmIdx = 0; 20466495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng int InstrOffs = 0; 20476495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned NumBits = 0; 20486495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned Scale = 1; 20496495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng switch (AddrMode) { 20503e5561247202bae994dd259a2d8dc4eff8f799f3Jim Grosbach case ARMII::AddrMode_i12: { 20513e5561247202bae994dd259a2d8dc4eff8f799f3Jim Grosbach ImmIdx = FrameRegIdx + 1; 20523e5561247202bae994dd259a2d8dc4eff8f799f3Jim Grosbach InstrOffs = MI.getOperand(ImmIdx).getImm(); 20533e5561247202bae994dd259a2d8dc4eff8f799f3Jim Grosbach NumBits = 12; 20543e5561247202bae994dd259a2d8dc4eff8f799f3Jim Grosbach break; 20553e5561247202bae994dd259a2d8dc4eff8f799f3Jim Grosbach } 20566495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng case ARMII::AddrMode2: { 20576495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ImmIdx = FrameRegIdx+2; 20586495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng InstrOffs = ARM_AM::getAM2Offset(MI.getOperand(ImmIdx).getImm()); 20596495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (ARM_AM::getAM2Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub) 20606495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng InstrOffs *= -1; 20616495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng NumBits = 12; 20626495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng break; 20636495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 20646495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng case ARMII::AddrMode3: { 20656495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ImmIdx = FrameRegIdx+2; 20666495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng InstrOffs = ARM_AM::getAM3Offset(MI.getOperand(ImmIdx).getImm()); 20676495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (ARM_AM::getAM3Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub) 20686495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng InstrOffs *= -1; 20696495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng NumBits = 8; 20706495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng break; 20716495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 2072baf31088f1472f48ea5ae81f0b93636cc44ca444Anton Korobeynikov case ARMII::AddrMode4: 2073a44321776ecd96fa0344335d3027758be3386e45Jim Grosbach case ARMII::AddrMode6: 2074cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng // Can't fold any offset even if it's zero. 2075cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng return false; 20766495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng case ARMII::AddrMode5: { 20776495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ImmIdx = FrameRegIdx+1; 20786495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng InstrOffs = ARM_AM::getAM5Offset(MI.getOperand(ImmIdx).getImm()); 20796495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (ARM_AM::getAM5Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub) 20806495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng InstrOffs *= -1; 20816495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng NumBits = 8; 20826495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng Scale = 4; 20836495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng break; 20846495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 20856495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng default: 20866495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng llvm_unreachable("Unsupported addressing mode!"); 20876495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 20886495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 20896495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng Offset += InstrOffs * Scale; 20906495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!"); 20916495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (Offset < 0) { 20926495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng Offset = -Offset; 20936495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng isSub = true; 20946495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 20956495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 20966495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Attempt to fold address comp. if opcode has offset bits 20976495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (NumBits > 0) { 20986495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Common case: small offset, fits into instruction. 20996495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MachineOperand &ImmOp = MI.getOperand(ImmIdx); 21006495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng int ImmedOffset = Offset / Scale; 21016495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned Mask = (1 << NumBits) - 1; 21026495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if ((unsigned)Offset <= Mask * Scale) { 21036495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Replace the FrameIndex with sp 21046495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false); 210577aee8e22c36257716c2df2f275724765704f20cJim Grosbach // FIXME: When addrmode2 goes away, this will simplify (like the 210677aee8e22c36257716c2df2f275724765704f20cJim Grosbach // T2 version), as the LDR.i12 versions don't need the encoding 210777aee8e22c36257716c2df2f275724765704f20cJim Grosbach // tricks for the offset value. 210877aee8e22c36257716c2df2f275724765704f20cJim Grosbach if (isSub) { 210977aee8e22c36257716c2df2f275724765704f20cJim Grosbach if (AddrMode == ARMII::AddrMode_i12) 211077aee8e22c36257716c2df2f275724765704f20cJim Grosbach ImmedOffset = -ImmedOffset; 211177aee8e22c36257716c2df2f275724765704f20cJim Grosbach else 211277aee8e22c36257716c2df2f275724765704f20cJim Grosbach ImmedOffset |= 1 << NumBits; 211377aee8e22c36257716c2df2f275724765704f20cJim Grosbach } 21146495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ImmOp.ChangeToImmediate(ImmedOffset); 2115cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng Offset = 0; 2116cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng return true; 21176495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 2118764ab52dd80310a205c9888bf166d09dab858f90Jim Grosbach 21196495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Otherwise, it didn't fit. Pull in what we can to simplify the immed. 21206495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ImmedOffset = ImmedOffset & Mask; 2121063efbf569e46776093ddf50099c98fdbb362167Jim Grosbach if (isSub) { 2122063efbf569e46776093ddf50099c98fdbb362167Jim Grosbach if (AddrMode == ARMII::AddrMode_i12) 2123063efbf569e46776093ddf50099c98fdbb362167Jim Grosbach ImmedOffset = -ImmedOffset; 2124063efbf569e46776093ddf50099c98fdbb362167Jim Grosbach else 2125063efbf569e46776093ddf50099c98fdbb362167Jim Grosbach ImmedOffset |= 1 << NumBits; 2126063efbf569e46776093ddf50099c98fdbb362167Jim Grosbach } 21276495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ImmOp.ChangeToImmediate(ImmedOffset); 21286495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng Offset &= ~(Mask*Scale); 21296495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 21306495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 21316495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 2132cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng Offset = (isSub) ? -Offset : Offset; 2133cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng return Offset == 0; 21346495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng} 2135e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling 2136de7266c611b37ec050efb53b73166081a98cea13Manman Ren/// analyzeCompare - For a comparison instruction, return the source registers 2137de7266c611b37ec050efb53b73166081a98cea13Manman Ren/// in SrcReg and SrcReg2 if having two register operands, and the value it 2138de7266c611b37ec050efb53b73166081a98cea13Manman Ren/// compares against in CmpValue. Return true if the comparison instruction 2139de7266c611b37ec050efb53b73166081a98cea13Manman Ren/// can be analyzed. 2140e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendlingbool ARMBaseInstrInfo:: 2141de7266c611b37ec050efb53b73166081a98cea13Manman RenanalyzeCompare(const MachineInstr *MI, unsigned &SrcReg, unsigned &SrcReg2, 2142de7266c611b37ec050efb53b73166081a98cea13Manman Ren int &CmpMask, int &CmpValue) const { 2143e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling switch (MI->getOpcode()) { 2144e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling default: break; 214538ae997e63e3e1bb2c8679e01ea74cf8fd0be893Bill Wendling case ARM::CMPri: 2146e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling case ARM::t2CMPri: 2147e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling SrcReg = MI->getOperand(0).getReg(); 2148de7266c611b37ec050efb53b73166081a98cea13Manman Ren SrcReg2 = 0; 214904ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif CmpMask = ~0; 2150e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling CmpValue = MI->getOperand(1).getImm(); 2151e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling return true; 2152247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren case ARM::CMPrr: 2153247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren case ARM::t2CMPrr: 2154247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren SrcReg = MI->getOperand(0).getReg(); 2155de7266c611b37ec050efb53b73166081a98cea13Manman Ren SrcReg2 = MI->getOperand(1).getReg(); 2156247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren CmpMask = ~0; 2157247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren CmpValue = 0; 2158247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren return true; 215904ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif case ARM::TSTri: 216004ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif case ARM::t2TSTri: 216104ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif SrcReg = MI->getOperand(0).getReg(); 2162de7266c611b37ec050efb53b73166081a98cea13Manman Ren SrcReg2 = 0; 216304ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif CmpMask = MI->getOperand(1).getImm(); 216404ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif CmpValue = 0; 216504ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif return true; 216604ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif } 216704ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif 216804ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif return false; 216904ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif} 217004ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif 217105642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif/// isSuitableForMask - Identify a suitable 'and' instruction that 217205642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif/// operates on the given source register and applies the same mask 217305642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif/// as a 'tst' instruction. Provide a limited look-through for copies. 217405642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif/// When successful, MI will hold the found instruction. 217505642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greifstatic bool isSuitableForMask(MachineInstr *&MI, unsigned SrcReg, 21768ff9bb189ce188452e6cae6ed65cb2745814126cGabor Greif int CmpMask, bool CommonUse) { 217705642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif switch (MI->getOpcode()) { 217804ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif case ARM::ANDri: 217904ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif case ARM::t2ANDri: 218005642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif if (CmpMask != MI->getOperand(2).getImm()) 21818ff9bb189ce188452e6cae6ed65cb2745814126cGabor Greif return false; 218205642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif if (SrcReg == MI->getOperand(CommonUse ? 1 : 0).getReg()) 218304ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif return true; 218404ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif break; 218505642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif case ARM::COPY: { 218605642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif // Walk down one instruction which is potentially an 'and'. 218705642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif const MachineInstr &Copy = *MI; 2188f000a7a212590bfd45e23c05bff5e1b683d25dd6Michael J. Spencer MachineBasicBlock::iterator AND( 218936b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines std::next(MachineBasicBlock::iterator(MI))); 219005642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif if (AND == MI->getParent()->end()) return false; 219105642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif MI = AND; 219205642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif return isSuitableForMask(MI, Copy.getOperand(0).getReg(), 219305642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif CmpMask, true); 219405642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif } 2195e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling } 2196e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling 2197e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling return false; 2198e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling} 2199e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling 220076c6ccbd4cee0637c961e32435177ab89e931fedManman Ren/// getSwappedCondition - assume the flags are set by MI(a,b), return 220176c6ccbd4cee0637c961e32435177ab89e931fedManman Ren/// the condition code if we modify the instructions such that flags are 220276c6ccbd4cee0637c961e32435177ab89e931fedManman Ren/// set by MI(b,a). 220376c6ccbd4cee0637c961e32435177ab89e931fedManman Reninline static ARMCC::CondCodes getSwappedCondition(ARMCC::CondCodes CC) { 220476c6ccbd4cee0637c961e32435177ab89e931fedManman Ren switch (CC) { 220576c6ccbd4cee0637c961e32435177ab89e931fedManman Ren default: return ARMCC::AL; 220676c6ccbd4cee0637c961e32435177ab89e931fedManman Ren case ARMCC::EQ: return ARMCC::EQ; 220776c6ccbd4cee0637c961e32435177ab89e931fedManman Ren case ARMCC::NE: return ARMCC::NE; 220876c6ccbd4cee0637c961e32435177ab89e931fedManman Ren case ARMCC::HS: return ARMCC::LS; 220976c6ccbd4cee0637c961e32435177ab89e931fedManman Ren case ARMCC::LO: return ARMCC::HI; 221076c6ccbd4cee0637c961e32435177ab89e931fedManman Ren case ARMCC::HI: return ARMCC::LO; 221176c6ccbd4cee0637c961e32435177ab89e931fedManman Ren case ARMCC::LS: return ARMCC::HS; 221276c6ccbd4cee0637c961e32435177ab89e931fedManman Ren case ARMCC::GE: return ARMCC::LE; 221376c6ccbd4cee0637c961e32435177ab89e931fedManman Ren case ARMCC::LT: return ARMCC::GT; 221476c6ccbd4cee0637c961e32435177ab89e931fedManman Ren case ARMCC::GT: return ARMCC::LT; 221576c6ccbd4cee0637c961e32435177ab89e931fedManman Ren case ARMCC::LE: return ARMCC::GE; 221676c6ccbd4cee0637c961e32435177ab89e931fedManman Ren } 221776c6ccbd4cee0637c961e32435177ab89e931fedManman Ren} 221876c6ccbd4cee0637c961e32435177ab89e931fedManman Ren 221976c6ccbd4cee0637c961e32435177ab89e931fedManman Ren/// isRedundantFlagInstr - check whether the first instruction, whose only 222076c6ccbd4cee0637c961e32435177ab89e931fedManman Ren/// purpose is to update flags, can be made redundant. 222176c6ccbd4cee0637c961e32435177ab89e931fedManman Ren/// CMPrr can be made redundant by SUBrr if the operands are the same. 222276c6ccbd4cee0637c961e32435177ab89e931fedManman Ren/// CMPri can be made redundant by SUBri if the operands are the same. 222376c6ccbd4cee0637c961e32435177ab89e931fedManman Ren/// This function can be extended later on. 222476c6ccbd4cee0637c961e32435177ab89e931fedManman Reninline static bool isRedundantFlagInstr(MachineInstr *CmpI, unsigned SrcReg, 222576c6ccbd4cee0637c961e32435177ab89e931fedManman Ren unsigned SrcReg2, int ImmValue, 222676c6ccbd4cee0637c961e32435177ab89e931fedManman Ren MachineInstr *OI) { 222776c6ccbd4cee0637c961e32435177ab89e931fedManman Ren if ((CmpI->getOpcode() == ARM::CMPrr || 222876c6ccbd4cee0637c961e32435177ab89e931fedManman Ren CmpI->getOpcode() == ARM::t2CMPrr) && 222976c6ccbd4cee0637c961e32435177ab89e931fedManman Ren (OI->getOpcode() == ARM::SUBrr || 223076c6ccbd4cee0637c961e32435177ab89e931fedManman Ren OI->getOpcode() == ARM::t2SUBrr) && 223176c6ccbd4cee0637c961e32435177ab89e931fedManman Ren ((OI->getOperand(1).getReg() == SrcReg && 223276c6ccbd4cee0637c961e32435177ab89e931fedManman Ren OI->getOperand(2).getReg() == SrcReg2) || 223376c6ccbd4cee0637c961e32435177ab89e931fedManman Ren (OI->getOperand(1).getReg() == SrcReg2 && 223476c6ccbd4cee0637c961e32435177ab89e931fedManman Ren OI->getOperand(2).getReg() == SrcReg))) 223576c6ccbd4cee0637c961e32435177ab89e931fedManman Ren return true; 223676c6ccbd4cee0637c961e32435177ab89e931fedManman Ren 223776c6ccbd4cee0637c961e32435177ab89e931fedManman Ren if ((CmpI->getOpcode() == ARM::CMPri || 223876c6ccbd4cee0637c961e32435177ab89e931fedManman Ren CmpI->getOpcode() == ARM::t2CMPri) && 223976c6ccbd4cee0637c961e32435177ab89e931fedManman Ren (OI->getOpcode() == ARM::SUBri || 224076c6ccbd4cee0637c961e32435177ab89e931fedManman Ren OI->getOpcode() == ARM::t2SUBri) && 224176c6ccbd4cee0637c961e32435177ab89e931fedManman Ren OI->getOperand(1).getReg() == SrcReg && 224276c6ccbd4cee0637c961e32435177ab89e931fedManman Ren OI->getOperand(2).getImm() == ImmValue) 224376c6ccbd4cee0637c961e32435177ab89e931fedManman Ren return true; 224476c6ccbd4cee0637c961e32435177ab89e931fedManman Ren return false; 224576c6ccbd4cee0637c961e32435177ab89e931fedManman Ren} 224676c6ccbd4cee0637c961e32435177ab89e931fedManman Ren 2247de7266c611b37ec050efb53b73166081a98cea13Manman Ren/// optimizeCompareInstr - Convert the instruction supplying the argument to the 2248de7266c611b37ec050efb53b73166081a98cea13Manman Ren/// comparison into one that sets the zero bit in the flags register; 2249de7266c611b37ec050efb53b73166081a98cea13Manman Ren/// Remove a redundant Compare instruction if an earlier instruction can set the 2250de7266c611b37ec050efb53b73166081a98cea13Manman Ren/// flags in the same way as Compare. 2251de7266c611b37ec050efb53b73166081a98cea13Manman Ren/// E.g. SUBrr(r1,r2) and CMPrr(r1,r2). We also handle the case where two 2252de7266c611b37ec050efb53b73166081a98cea13Manman Ren/// operands are swapped: SUBrr(r1,r2) and CMPrr(r2,r1), by updating the 2253de7266c611b37ec050efb53b73166081a98cea13Manman Ren/// condition code of instructions which use the flags. 2254e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendlingbool ARMBaseInstrInfo:: 2255de7266c611b37ec050efb53b73166081a98cea13Manman RenoptimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, unsigned SrcReg2, 2256de7266c611b37ec050efb53b73166081a98cea13Manman Ren int CmpMask, int CmpValue, 2257de7266c611b37ec050efb53b73166081a98cea13Manman Ren const MachineRegisterInfo *MRI) const { 225876c6ccbd4cee0637c961e32435177ab89e931fedManman Ren // Get the unique definition of SrcReg. 225976c6ccbd4cee0637c961e32435177ab89e931fedManman Ren MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg); 226076c6ccbd4cee0637c961e32435177ab89e931fedManman Ren if (!MI) return false; 226192ad57f066e9f256e4e3d72febf152e68caa80c7Bill Wendling 226204ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif // Masked compares sometimes use the same register as the corresponding 'and'. 226304ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif if (CmpMask != ~0) { 2264519daf5d2dd80614ac4e529b199e6f3e595bfc80Jakob Stoklund Olesen if (!isSuitableForMask(MI, SrcReg, CmpMask, false) || isPredicated(MI)) { 2265dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines MI = nullptr; 226636b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines for (MachineRegisterInfo::use_instr_iterator 226736b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines UI = MRI->use_instr_begin(SrcReg), UE = MRI->use_instr_end(); 226836b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines UI != UE; ++UI) { 226904ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif if (UI->getParent() != CmpInstr->getParent()) continue; 227005642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif MachineInstr *PotentialAND = &*UI; 2271519daf5d2dd80614ac4e529b199e6f3e595bfc80Jakob Stoklund Olesen if (!isSuitableForMask(PotentialAND, SrcReg, CmpMask, true) || 2272519daf5d2dd80614ac4e529b199e6f3e595bfc80Jakob Stoklund Olesen isPredicated(PotentialAND)) 227304ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif continue; 227405642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif MI = PotentialAND; 227504ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif break; 227604ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif } 227704ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif if (!MI) return false; 227804ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif } 227904ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif } 228004ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif 2281247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren // Get ready to iterate backward from CmpInstr. 2282247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren MachineBasicBlock::iterator I = CmpInstr, E = MI, 2283247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren B = CmpInstr->getParent()->begin(); 22840aa38b9381a5be42abd4f5ca5baa8c2930d148d3Bill Wendling 22850aa38b9381a5be42abd4f5ca5baa8c2930d148d3Bill Wendling // Early exit if CmpInstr is at the beginning of the BB. 22860aa38b9381a5be42abd4f5ca5baa8c2930d148d3Bill Wendling if (I == B) return false; 22870aa38b9381a5be42abd4f5ca5baa8c2930d148d3Bill Wendling 2288247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren // There are two possible candidates which can be changed to set CPSR: 2289247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren // One is MI, the other is a SUB instruction. 2290247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren // For CMPrr(r1,r2), we are looking for SUB(r1,r2) or SUB(r2,r1). 2291247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren // For CMPri(r1, CmpValue), we are looking for SUBri(r1, CmpValue). 2292dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines MachineInstr *Sub = nullptr; 2293de7266c611b37ec050efb53b73166081a98cea13Manman Ren if (SrcReg2 != 0) 2294247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren // MI is not a candidate for CMPrr. 2295dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines MI = nullptr; 2296de7266c611b37ec050efb53b73166081a98cea13Manman Ren else if (MI->getParent() != CmpInstr->getParent() || CmpValue != 0) { 2297247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren // Conservatively refuse to convert an instruction which isn't in the same 2298247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren // BB as the comparison. 2299247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren // For CMPri, we need to check Sub, thus we can't return here. 23004949e98cccb98abb0ba3f67c22be757d446ab108Manman Ren if (CmpInstr->getOpcode() == ARM::CMPri || 2301247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren CmpInstr->getOpcode() == ARM::t2CMPri) 2302dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines MI = nullptr; 2303247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren else 2304247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren return false; 2305247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren } 2306247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren 2307247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren // Check that CPSR isn't set between the comparison instruction and the one we 2308247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren // want to change. At the same time, search for Sub. 230976c6ccbd4cee0637c961e32435177ab89e931fedManman Ren const TargetRegisterInfo *TRI = &getRegisterInfo(); 2310e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling --I; 2311e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling for (; I != E; --I) { 2312e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling const MachineInstr &Instr = *I; 2313e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling 231476c6ccbd4cee0637c961e32435177ab89e931fedManman Ren if (Instr.modifiesRegister(ARM::CPSR, TRI) || 231576c6ccbd4cee0637c961e32435177ab89e931fedManman Ren Instr.readsRegister(ARM::CPSR, TRI)) 231640a5eb18b031fa1a5e9697e21e251e613d441cc5Bill Wendling // This instruction modifies or uses CPSR after the one we want to 231740a5eb18b031fa1a5e9697e21e251e613d441cc5Bill Wendling // change. We can't do this transformation. 231876c6ccbd4cee0637c961e32435177ab89e931fedManman Ren return false; 2319247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren 232076c6ccbd4cee0637c961e32435177ab89e931fedManman Ren // Check whether CmpInstr can be made redundant by the current instruction. 232176c6ccbd4cee0637c961e32435177ab89e931fedManman Ren if (isRedundantFlagInstr(CmpInstr, SrcReg, SrcReg2, CmpValue, &*I)) { 2322247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren Sub = &*I; 2323247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren break; 2324247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren } 2325247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren 2326691e64a54ce899409abe7c131d15ed75e3c1fef5Evan Cheng if (I == B) 2327691e64a54ce899409abe7c131d15ed75e3c1fef5Evan Cheng // The 'and' is below the comparison instruction. 2328691e64a54ce899409abe7c131d15ed75e3c1fef5Evan Cheng return false; 2329e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling } 2330e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling 2331247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren // Return false if no candidates exist. 2332247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren if (!MI && !Sub) 2333247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren return false; 2334247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren 2335247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren // The single candidate is called MI. 2336247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren if (!MI) MI = Sub; 2337247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren 2338519daf5d2dd80614ac4e529b199e6f3e595bfc80Jakob Stoklund Olesen // We can't use a predicated instruction - it doesn't always write the flags. 2339519daf5d2dd80614ac4e529b199e6f3e595bfc80Jakob Stoklund Olesen if (isPredicated(MI)) 2340519daf5d2dd80614ac4e529b199e6f3e595bfc80Jakob Stoklund Olesen return false; 2341519daf5d2dd80614ac4e529b199e6f3e595bfc80Jakob Stoklund Olesen 2342e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling switch (MI->getOpcode()) { 2343e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling default: break; 2344ca3f6a3925e9a6e91022aa211bdc1b6e3f2ff41fCameron Zwarich case ARM::RSBrr: 2345df298c9ea64eb335f63fc075d8ef6306682ffe75Owen Anderson case ARM::RSBri: 2346ca3f6a3925e9a6e91022aa211bdc1b6e3f2ff41fCameron Zwarich case ARM::RSCrr: 2347df298c9ea64eb335f63fc075d8ef6306682ffe75Owen Anderson case ARM::RSCri: 2348ca3f6a3925e9a6e91022aa211bdc1b6e3f2ff41fCameron Zwarich case ARM::ADDrr: 234938ae997e63e3e1bb2c8679e01ea74cf8fd0be893Bill Wendling case ARM::ADDri: 2350ca3f6a3925e9a6e91022aa211bdc1b6e3f2ff41fCameron Zwarich case ARM::ADCrr: 2351df298c9ea64eb335f63fc075d8ef6306682ffe75Owen Anderson case ARM::ADCri: 2352ca3f6a3925e9a6e91022aa211bdc1b6e3f2ff41fCameron Zwarich case ARM::SUBrr: 235338ae997e63e3e1bb2c8679e01ea74cf8fd0be893Bill Wendling case ARM::SUBri: 2354ca3f6a3925e9a6e91022aa211bdc1b6e3f2ff41fCameron Zwarich case ARM::SBCrr: 2355df298c9ea64eb335f63fc075d8ef6306682ffe75Owen Anderson case ARM::SBCri: 2356df298c9ea64eb335f63fc075d8ef6306682ffe75Owen Anderson case ARM::t2RSBri: 2357ca3f6a3925e9a6e91022aa211bdc1b6e3f2ff41fCameron Zwarich case ARM::t2ADDrr: 235838ae997e63e3e1bb2c8679e01ea74cf8fd0be893Bill Wendling case ARM::t2ADDri: 2359ca3f6a3925e9a6e91022aa211bdc1b6e3f2ff41fCameron Zwarich case ARM::t2ADCrr: 2360df298c9ea64eb335f63fc075d8ef6306682ffe75Owen Anderson case ARM::t2ADCri: 2361ca3f6a3925e9a6e91022aa211bdc1b6e3f2ff41fCameron Zwarich case ARM::t2SUBrr: 2362df298c9ea64eb335f63fc075d8ef6306682ffe75Owen Anderson case ARM::t2SUBri: 2363ca3f6a3925e9a6e91022aa211bdc1b6e3f2ff41fCameron Zwarich case ARM::t2SBCrr: 2364b485de5d8c3fe0c62c0b07f63f64bd10f6803c17Cameron Zwarich case ARM::t2SBCri: 2365b485de5d8c3fe0c62c0b07f63f64bd10f6803c17Cameron Zwarich case ARM::ANDrr: 2366b485de5d8c3fe0c62c0b07f63f64bd10f6803c17Cameron Zwarich case ARM::ANDri: 2367b485de5d8c3fe0c62c0b07f63f64bd10f6803c17Cameron Zwarich case ARM::t2ANDrr: 23680cb11ac32fc09c5db42fb801db242ac9fb51f6b1Cameron Zwarich case ARM::t2ANDri: 23690cb11ac32fc09c5db42fb801db242ac9fb51f6b1Cameron Zwarich case ARM::ORRrr: 23700cb11ac32fc09c5db42fb801db242ac9fb51f6b1Cameron Zwarich case ARM::ORRri: 23710cb11ac32fc09c5db42fb801db242ac9fb51f6b1Cameron Zwarich case ARM::t2ORRrr: 23720cb11ac32fc09c5db42fb801db242ac9fb51f6b1Cameron Zwarich case ARM::t2ORRri: 23730cb11ac32fc09c5db42fb801db242ac9fb51f6b1Cameron Zwarich case ARM::EORrr: 23740cb11ac32fc09c5db42fb801db242ac9fb51f6b1Cameron Zwarich case ARM::EORri: 23750cb11ac32fc09c5db42fb801db242ac9fb51f6b1Cameron Zwarich case ARM::t2EORrr: 23760cb11ac32fc09c5db42fb801db242ac9fb51f6b1Cameron Zwarich case ARM::t2EORri: { 2377247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren // Scan forward for the use of CPSR 2378247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren // When checking against MI: if it's a conditional code requires 237945ed19499b8f7025d9acf91cc37fbf6ea63abc4fManman Ren // checking of V bit, then this is not safe to do. 238045ed19499b8f7025d9acf91cc37fbf6ea63abc4fManman Ren // It is safe to remove CmpInstr if CPSR is redefined or killed. 238145ed19499b8f7025d9acf91cc37fbf6ea63abc4fManman Ren // If we are done with the basic block, we need to check whether CPSR is 238245ed19499b8f7025d9acf91cc37fbf6ea63abc4fManman Ren // live-out. 238376c6ccbd4cee0637c961e32435177ab89e931fedManman Ren SmallVector<std::pair<MachineOperand*, ARMCC::CondCodes>, 4> 238476c6ccbd4cee0637c961e32435177ab89e931fedManman Ren OperandsToUpdate; 23852c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng bool isSafe = false; 23862c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng I = CmpInstr; 2387247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren E = CmpInstr->getParent()->end(); 23882c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng while (!isSafe && ++I != E) { 23892c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng const MachineInstr &Instr = *I; 23902c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng for (unsigned IO = 0, EO = Instr.getNumOperands(); 23912c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng !isSafe && IO != EO; ++IO) { 23922c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng const MachineOperand &MO = Instr.getOperand(IO); 23932420b558de5d291d8503c1339004e5b5bf99a48aJakob Stoklund Olesen if (MO.isRegMask() && MO.clobbersPhysReg(ARM::CPSR)) { 23942420b558de5d291d8503c1339004e5b5bf99a48aJakob Stoklund Olesen isSafe = true; 23952420b558de5d291d8503c1339004e5b5bf99a48aJakob Stoklund Olesen break; 23962420b558de5d291d8503c1339004e5b5bf99a48aJakob Stoklund Olesen } 23972c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng if (!MO.isReg() || MO.getReg() != ARM::CPSR) 23982c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng continue; 23992c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng if (MO.isDef()) { 24002c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng isSafe = true; 24012c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng break; 24022c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng } 24032bdc0dd2db145591eb3fdc01fa0b2a3d831f334bBill Wendling // Condition code is after the operand before CPSR except for VSELs. 24042bdc0dd2db145591eb3fdc01fa0b2a3d831f334bBill Wendling ARMCC::CondCodes CC; 24052bdc0dd2db145591eb3fdc01fa0b2a3d831f334bBill Wendling bool IsInstrVSel = true; 24062bdc0dd2db145591eb3fdc01fa0b2a3d831f334bBill Wendling switch (Instr.getOpcode()) { 24072bdc0dd2db145591eb3fdc01fa0b2a3d831f334bBill Wendling default: 24082bdc0dd2db145591eb3fdc01fa0b2a3d831f334bBill Wendling IsInstrVSel = false; 24092bdc0dd2db145591eb3fdc01fa0b2a3d831f334bBill Wendling CC = (ARMCC::CondCodes)Instr.getOperand(IO - 1).getImm(); 24102bdc0dd2db145591eb3fdc01fa0b2a3d831f334bBill Wendling break; 24112bdc0dd2db145591eb3fdc01fa0b2a3d831f334bBill Wendling case ARM::VSELEQD: 24122bdc0dd2db145591eb3fdc01fa0b2a3d831f334bBill Wendling case ARM::VSELEQS: 24132bdc0dd2db145591eb3fdc01fa0b2a3d831f334bBill Wendling CC = ARMCC::EQ; 24142bdc0dd2db145591eb3fdc01fa0b2a3d831f334bBill Wendling break; 24152bdc0dd2db145591eb3fdc01fa0b2a3d831f334bBill Wendling case ARM::VSELGTD: 24162bdc0dd2db145591eb3fdc01fa0b2a3d831f334bBill Wendling case ARM::VSELGTS: 24172bdc0dd2db145591eb3fdc01fa0b2a3d831f334bBill Wendling CC = ARMCC::GT; 24182bdc0dd2db145591eb3fdc01fa0b2a3d831f334bBill Wendling break; 24192bdc0dd2db145591eb3fdc01fa0b2a3d831f334bBill Wendling case ARM::VSELGED: 24202bdc0dd2db145591eb3fdc01fa0b2a3d831f334bBill Wendling case ARM::VSELGES: 24212bdc0dd2db145591eb3fdc01fa0b2a3d831f334bBill Wendling CC = ARMCC::GE; 24222bdc0dd2db145591eb3fdc01fa0b2a3d831f334bBill Wendling break; 24232bdc0dd2db145591eb3fdc01fa0b2a3d831f334bBill Wendling case ARM::VSELVSS: 24242bdc0dd2db145591eb3fdc01fa0b2a3d831f334bBill Wendling case ARM::VSELVSD: 24252bdc0dd2db145591eb3fdc01fa0b2a3d831f334bBill Wendling CC = ARMCC::VS; 24262bdc0dd2db145591eb3fdc01fa0b2a3d831f334bBill Wendling break; 24272bdc0dd2db145591eb3fdc01fa0b2a3d831f334bBill Wendling } 24282bdc0dd2db145591eb3fdc01fa0b2a3d831f334bBill Wendling 242976c6ccbd4cee0637c961e32435177ab89e931fedManman Ren if (Sub) { 243076c6ccbd4cee0637c961e32435177ab89e931fedManman Ren ARMCC::CondCodes NewCC = getSwappedCondition(CC); 243176c6ccbd4cee0637c961e32435177ab89e931fedManman Ren if (NewCC == ARMCC::AL) 2432247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren return false; 243376c6ccbd4cee0637c961e32435177ab89e931fedManman Ren // If we have SUB(r1, r2) and CMP(r2, r1), the condition code based 243476c6ccbd4cee0637c961e32435177ab89e931fedManman Ren // on CMP needs to be updated to be based on SUB. 243576c6ccbd4cee0637c961e32435177ab89e931fedManman Ren // Push the condition code operands to OperandsToUpdate. 243676c6ccbd4cee0637c961e32435177ab89e931fedManman Ren // If it is safe to remove CmpInstr, the condition code of these 243776c6ccbd4cee0637c961e32435177ab89e931fedManman Ren // operands will be modified. 243876c6ccbd4cee0637c961e32435177ab89e931fedManman Ren if (SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 && 24392bdc0dd2db145591eb3fdc01fa0b2a3d831f334bBill Wendling Sub->getOperand(2).getReg() == SrcReg) { 24402bdc0dd2db145591eb3fdc01fa0b2a3d831f334bBill Wendling // VSel doesn't support condition code update. 24412bdc0dd2db145591eb3fdc01fa0b2a3d831f334bBill Wendling if (IsInstrVSel) 24422bdc0dd2db145591eb3fdc01fa0b2a3d831f334bBill Wendling return false; 24432bdc0dd2db145591eb3fdc01fa0b2a3d831f334bBill Wendling OperandsToUpdate.push_back( 24442bdc0dd2db145591eb3fdc01fa0b2a3d831f334bBill Wendling std::make_pair(&((*I).getOperand(IO - 1)), NewCC)); 24452bdc0dd2db145591eb3fdc01fa0b2a3d831f334bBill Wendling } 24462bdc0dd2db145591eb3fdc01fa0b2a3d831f334bBill Wendling } else 2447247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren switch (CC) { 2448247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren default: 24499af64303fa887a3d9b75e715787ba587c3f18139Manman Ren // CPSR can be used multiple times, we should continue. 2450247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren break; 2451247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren case ARMCC::VS: 2452247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren case ARMCC::VC: 2453247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren case ARMCC::GE: 2454247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren case ARMCC::LT: 2455247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren case ARMCC::GT: 2456247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren case ARMCC::LE: 2457247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren return false; 2458247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren } 24592c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng } 24602c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng } 24612c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng 246245ed19499b8f7025d9acf91cc37fbf6ea63abc4fManman Ren // If CPSR is not killed nor re-defined, we should check whether it is 246345ed19499b8f7025d9acf91cc37fbf6ea63abc4fManman Ren // live-out. If it is live-out, do not optimize. 246445ed19499b8f7025d9acf91cc37fbf6ea63abc4fManman Ren if (!isSafe) { 246545ed19499b8f7025d9acf91cc37fbf6ea63abc4fManman Ren MachineBasicBlock *MBB = CmpInstr->getParent(); 246645ed19499b8f7025d9acf91cc37fbf6ea63abc4fManman Ren for (MachineBasicBlock::succ_iterator SI = MBB->succ_begin(), 246745ed19499b8f7025d9acf91cc37fbf6ea63abc4fManman Ren SE = MBB->succ_end(); SI != SE; ++SI) 246845ed19499b8f7025d9acf91cc37fbf6ea63abc4fManman Ren if ((*SI)->isLiveIn(ARM::CPSR)) 246945ed19499b8f7025d9acf91cc37fbf6ea63abc4fManman Ren return false; 247045ed19499b8f7025d9acf91cc37fbf6ea63abc4fManman Ren } 24712c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng 24723642e64c114e636548888c72c21ae023ee0121a7Evan Cheng // Toggle the optional operand to CPSR. 24733642e64c114e636548888c72c21ae023ee0121a7Evan Cheng MI->getOperand(5).setReg(ARM::CPSR); 24743642e64c114e636548888c72c21ae023ee0121a7Evan Cheng MI->getOperand(5).setIsDef(true); 2475519daf5d2dd80614ac4e529b199e6f3e595bfc80Jakob Stoklund Olesen assert(!isPredicated(MI) && "Can't use flags from predicated instruction"); 2476e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling CmpInstr->eraseFromParent(); 2477247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren 2478247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren // Modify the condition code of operands in OperandsToUpdate. 2479247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren // Since we have SUB(r1, r2) and CMP(r2, r1), the condition code needs to 2480247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren // be changed from r2 > r1 to r1 < r2, from r2 < r1 to r1 > r2, etc. 248176c6ccbd4cee0637c961e32435177ab89e931fedManman Ren for (unsigned i = 0, e = OperandsToUpdate.size(); i < e; i++) 248276c6ccbd4cee0637c961e32435177ab89e931fedManman Ren OperandsToUpdate[i].first->setImm(OperandsToUpdate[i].second); 2483e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling return true; 2484e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling } 2485b485de5d8c3fe0c62c0b07f63f64bd10f6803c17Cameron Zwarich } 2486e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling 2487e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling return false; 2488e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling} 24895f54ce347368105260be2cec497b6a4199dc5789Evan Cheng 2490c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Chengbool ARMBaseInstrInfo::FoldImmediate(MachineInstr *UseMI, 2491c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng MachineInstr *DefMI, unsigned Reg, 2492c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng MachineRegisterInfo *MRI) const { 2493c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng // Fold large immediates into add, sub, or, xor. 2494c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng unsigned DefOpc = DefMI->getOpcode(); 2495c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng if (DefOpc != ARM::t2MOVi32imm && DefOpc != ARM::MOVi32imm) 2496c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng return false; 2497c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng if (!DefMI->getOperand(1).isImm()) 2498c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng // Could be t2MOVi32imm <ga:xx> 2499c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng return false; 2500c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng 2501c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng if (!MRI->hasOneNonDBGUse(Reg)) 2502c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng return false; 2503c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng 2504e279f5953e9c3d934248cd4d2f24b6179ad9d2e6Evan Cheng const MCInstrDesc &DefMCID = DefMI->getDesc(); 2505e279f5953e9c3d934248cd4d2f24b6179ad9d2e6Evan Cheng if (DefMCID.hasOptionalDef()) { 2506e279f5953e9c3d934248cd4d2f24b6179ad9d2e6Evan Cheng unsigned NumOps = DefMCID.getNumOperands(); 2507e279f5953e9c3d934248cd4d2f24b6179ad9d2e6Evan Cheng const MachineOperand &MO = DefMI->getOperand(NumOps-1); 2508e279f5953e9c3d934248cd4d2f24b6179ad9d2e6Evan Cheng if (MO.getReg() == ARM::CPSR && !MO.isDead()) 2509e279f5953e9c3d934248cd4d2f24b6179ad9d2e6Evan Cheng // If DefMI defines CPSR and it is not dead, it's obviously not safe 2510e279f5953e9c3d934248cd4d2f24b6179ad9d2e6Evan Cheng // to delete DefMI. 2511e279f5953e9c3d934248cd4d2f24b6179ad9d2e6Evan Cheng return false; 2512e279f5953e9c3d934248cd4d2f24b6179ad9d2e6Evan Cheng } 2513e279f5953e9c3d934248cd4d2f24b6179ad9d2e6Evan Cheng 2514e279f5953e9c3d934248cd4d2f24b6179ad9d2e6Evan Cheng const MCInstrDesc &UseMCID = UseMI->getDesc(); 2515e279f5953e9c3d934248cd4d2f24b6179ad9d2e6Evan Cheng if (UseMCID.hasOptionalDef()) { 2516e279f5953e9c3d934248cd4d2f24b6179ad9d2e6Evan Cheng unsigned NumOps = UseMCID.getNumOperands(); 2517e279f5953e9c3d934248cd4d2f24b6179ad9d2e6Evan Cheng if (UseMI->getOperand(NumOps-1).getReg() == ARM::CPSR) 2518e279f5953e9c3d934248cd4d2f24b6179ad9d2e6Evan Cheng // If the instruction sets the flag, do not attempt this optimization 2519e279f5953e9c3d934248cd4d2f24b6179ad9d2e6Evan Cheng // since it may change the semantics of the code. 2520e279f5953e9c3d934248cd4d2f24b6179ad9d2e6Evan Cheng return false; 2521e279f5953e9c3d934248cd4d2f24b6179ad9d2e6Evan Cheng } 2522e279f5953e9c3d934248cd4d2f24b6179ad9d2e6Evan Cheng 2523c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng unsigned UseOpc = UseMI->getOpcode(); 25245c71c7a13715ed6f5bfdd5497172ddec316b68b0Evan Cheng unsigned NewUseOpc = 0; 2525c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng uint32_t ImmVal = (uint32_t)DefMI->getOperand(1).getImm(); 25265c71c7a13715ed6f5bfdd5497172ddec316b68b0Evan Cheng uint32_t SOImmValV1 = 0, SOImmValV2 = 0; 2527c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng bool Commute = false; 2528c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng switch (UseOpc) { 2529c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng default: return false; 2530c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::SUBrr: 2531c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::ADDrr: 2532c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::ORRrr: 2533c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::EORrr: 2534c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::t2SUBrr: 2535c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::t2ADDrr: 2536c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::t2ORRrr: 2537c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::t2EORrr: { 2538c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng Commute = UseMI->getOperand(2).getReg() != Reg; 2539c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng switch (UseOpc) { 2540c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng default: break; 2541c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::SUBrr: { 2542c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng if (Commute) 2543c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng return false; 2544c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng ImmVal = -ImmVal; 2545c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng NewUseOpc = ARM::SUBri; 2546c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng // Fallthrough 2547c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng } 2548c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::ADDrr: 2549c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::ORRrr: 2550c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::EORrr: { 2551c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng if (!ARM_AM::isSOImmTwoPartVal(ImmVal)) 2552c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng return false; 2553c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng SOImmValV1 = (uint32_t)ARM_AM::getSOImmTwoPartFirst(ImmVal); 2554c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng SOImmValV2 = (uint32_t)ARM_AM::getSOImmTwoPartSecond(ImmVal); 2555c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng switch (UseOpc) { 2556c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng default: break; 2557c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::ADDrr: NewUseOpc = ARM::ADDri; break; 2558c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::ORRrr: NewUseOpc = ARM::ORRri; break; 2559c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::EORrr: NewUseOpc = ARM::EORri; break; 2560c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng } 2561c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng break; 2562c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng } 2563c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::t2SUBrr: { 2564c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng if (Commute) 2565c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng return false; 2566c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng ImmVal = -ImmVal; 2567c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng NewUseOpc = ARM::t2SUBri; 2568c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng // Fallthrough 2569c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng } 2570c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::t2ADDrr: 2571c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::t2ORRrr: 2572c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::t2EORrr: { 2573c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng if (!ARM_AM::isT2SOImmTwoPartVal(ImmVal)) 2574c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng return false; 2575c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng SOImmValV1 = (uint32_t)ARM_AM::getT2SOImmTwoPartFirst(ImmVal); 2576c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng SOImmValV2 = (uint32_t)ARM_AM::getT2SOImmTwoPartSecond(ImmVal); 2577c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng switch (UseOpc) { 2578c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng default: break; 2579c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::t2ADDrr: NewUseOpc = ARM::t2ADDri; break; 2580c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::t2ORRrr: NewUseOpc = ARM::t2ORRri; break; 2581c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::t2EORrr: NewUseOpc = ARM::t2EORri; break; 2582c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng } 2583c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng break; 2584c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng } 2585c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng } 2586c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng } 2587c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng } 2588c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng 2589c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng unsigned OpIdx = Commute ? 2 : 1; 2590c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng unsigned Reg1 = UseMI->getOperand(OpIdx).getReg(); 2591c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng bool isKill = UseMI->getOperand(OpIdx).isKill(); 2592c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng unsigned NewReg = MRI->createVirtualRegister(MRI->getRegClass(Reg)); 2593c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng AddDefaultCC(AddDefaultPred(BuildMI(*UseMI->getParent(), 2594ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng UseMI, UseMI->getDebugLoc(), 2595c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng get(NewUseOpc), NewReg) 2596c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng .addReg(Reg1, getKillRegState(isKill)) 2597c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng .addImm(SOImmValV1))); 2598c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng UseMI->setDesc(get(NewUseOpc)); 2599c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng UseMI->getOperand(1).setReg(NewReg); 2600c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng UseMI->getOperand(1).setIsKill(); 2601c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng UseMI->getOperand(2).ChangeToImmediate(SOImmValV2); 2602c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng DefMI->eraseFromParent(); 2603c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng return true; 2604c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng} 2605c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng 2606eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilsonstatic unsigned getNumMicroOpsSwiftLdSt(const InstrItineraryData *ItinData, 2607eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson const MachineInstr *MI) { 2608eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson switch (MI->getOpcode()) { 2609eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson default: { 2610eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson const MCInstrDesc &Desc = MI->getDesc(); 2611eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson int UOps = ItinData->getNumMicroOps(Desc.getSchedClass()); 2612eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson assert(UOps >= 0 && "bad # UOps"); 2613eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson return UOps; 2614eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson } 2615eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson 2616eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::LDRrs: 2617eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::LDRBrs: 2618eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::STRrs: 2619eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::STRBrs: { 2620eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson unsigned ShOpVal = MI->getOperand(3).getImm(); 2621eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson bool isSub = ARM_AM::getAM2Op(ShOpVal) == ARM_AM::sub; 2622eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal); 2623eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson if (!isSub && 2624eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson (ShImm == 0 || 2625eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson ((ShImm == 1 || ShImm == 2 || ShImm == 3) && 2626eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl))) 2627eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson return 1; 2628eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson return 2; 2629eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson } 2630eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson 2631eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::LDRH: 2632eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::STRH: { 2633eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson if (!MI->getOperand(2).getReg()) 2634eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson return 1; 2635eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson 2636eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson unsigned ShOpVal = MI->getOperand(3).getImm(); 2637eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson bool isSub = ARM_AM::getAM2Op(ShOpVal) == ARM_AM::sub; 2638eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal); 2639eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson if (!isSub && 2640eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson (ShImm == 0 || 2641eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson ((ShImm == 1 || ShImm == 2 || ShImm == 3) && 2642eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl))) 2643eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson return 1; 2644eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson return 2; 2645eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson } 2646eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson 2647eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::LDRSB: 2648eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::LDRSH: 2649eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson return (ARM_AM::getAM3Op(MI->getOperand(3).getImm()) == ARM_AM::sub) ? 3:2; 2650eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson 2651eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::LDRSB_POST: 2652eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::LDRSH_POST: { 2653eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson unsigned Rt = MI->getOperand(0).getReg(); 2654eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson unsigned Rm = MI->getOperand(3).getReg(); 2655eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson return (Rt == Rm) ? 4 : 3; 2656eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson } 2657eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson 2658eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::LDR_PRE_REG: 2659eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::LDRB_PRE_REG: { 2660eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson unsigned Rt = MI->getOperand(0).getReg(); 2661eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson unsigned Rm = MI->getOperand(3).getReg(); 2662eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson if (Rt == Rm) 2663eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson return 3; 2664eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson unsigned ShOpVal = MI->getOperand(4).getImm(); 2665eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson bool isSub = ARM_AM::getAM2Op(ShOpVal) == ARM_AM::sub; 2666eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal); 2667eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson if (!isSub && 2668eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson (ShImm == 0 || 2669eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson ((ShImm == 1 || ShImm == 2 || ShImm == 3) && 2670eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl))) 2671eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson return 2; 2672eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson return 3; 2673eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson } 2674eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson 2675eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::STR_PRE_REG: 2676eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::STRB_PRE_REG: { 2677eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson unsigned ShOpVal = MI->getOperand(4).getImm(); 2678eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson bool isSub = ARM_AM::getAM2Op(ShOpVal) == ARM_AM::sub; 2679eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal); 2680eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson if (!isSub && 2681eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson (ShImm == 0 || 2682eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson ((ShImm == 1 || ShImm == 2 || ShImm == 3) && 2683eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl))) 2684eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson return 2; 2685eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson return 3; 2686eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson } 2687eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson 2688eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::LDRH_PRE: 2689eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::STRH_PRE: { 2690eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson unsigned Rt = MI->getOperand(0).getReg(); 2691eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson unsigned Rm = MI->getOperand(3).getReg(); 2692eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson if (!Rm) 2693eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson return 2; 2694eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson if (Rt == Rm) 2695eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson return 3; 2696eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson return (ARM_AM::getAM3Op(MI->getOperand(4).getImm()) == ARM_AM::sub) 2697eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson ? 3 : 2; 2698eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson } 2699eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson 2700eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::LDR_POST_REG: 2701eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::LDRB_POST_REG: 2702eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::LDRH_POST: { 2703eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson unsigned Rt = MI->getOperand(0).getReg(); 2704eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson unsigned Rm = MI->getOperand(3).getReg(); 2705eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson return (Rt == Rm) ? 3 : 2; 2706eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson } 2707eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson 2708eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::LDR_PRE_IMM: 2709eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::LDRB_PRE_IMM: 2710eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::LDR_POST_IMM: 2711eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::LDRB_POST_IMM: 2712eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::STRB_POST_IMM: 2713eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::STRB_POST_REG: 2714eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::STRB_PRE_IMM: 2715eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::STRH_POST: 2716eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::STR_POST_IMM: 2717eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::STR_POST_REG: 2718eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::STR_PRE_IMM: 2719eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson return 2; 2720eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson 2721eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::LDRSB_PRE: 2722eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::LDRSH_PRE: { 2723eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson unsigned Rm = MI->getOperand(3).getReg(); 2724eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson if (Rm == 0) 2725eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson return 3; 2726eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson unsigned Rt = MI->getOperand(0).getReg(); 2727eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson if (Rt == Rm) 2728eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson return 4; 2729eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson unsigned ShOpVal = MI->getOperand(4).getImm(); 2730eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson bool isSub = ARM_AM::getAM2Op(ShOpVal) == ARM_AM::sub; 2731eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal); 2732eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson if (!isSub && 2733eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson (ShImm == 0 || 2734eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson ((ShImm == 1 || ShImm == 2 || ShImm == 3) && 2735eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl))) 2736eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson return 3; 2737eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson return 4; 2738eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson } 2739eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson 2740eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::LDRD: { 2741eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson unsigned Rt = MI->getOperand(0).getReg(); 2742eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson unsigned Rn = MI->getOperand(2).getReg(); 2743eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson unsigned Rm = MI->getOperand(3).getReg(); 2744eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson if (Rm) 2745eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson return (ARM_AM::getAM3Op(MI->getOperand(4).getImm()) == ARM_AM::sub) ?4:3; 2746eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson return (Rt == Rn) ? 3 : 2; 2747eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson } 2748eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson 2749eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::STRD: { 2750eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson unsigned Rm = MI->getOperand(3).getReg(); 2751eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson if (Rm) 2752eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson return (ARM_AM::getAM3Op(MI->getOperand(4).getImm()) == ARM_AM::sub) ?4:3; 2753eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson return 2; 2754eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson } 2755eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson 2756eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::LDRD_POST: 2757eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::t2LDRD_POST: 2758eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson return 3; 2759eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson 2760eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::STRD_POST: 2761eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::t2STRD_POST: 2762eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson return 4; 2763eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson 2764eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::LDRD_PRE: { 2765eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson unsigned Rt = MI->getOperand(0).getReg(); 2766eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson unsigned Rn = MI->getOperand(3).getReg(); 2767eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson unsigned Rm = MI->getOperand(4).getReg(); 2768eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson if (Rm) 2769eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson return (ARM_AM::getAM3Op(MI->getOperand(5).getImm()) == ARM_AM::sub) ?5:4; 2770eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson return (Rt == Rn) ? 4 : 3; 2771eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson } 2772eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson 2773eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::t2LDRD_PRE: { 2774eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson unsigned Rt = MI->getOperand(0).getReg(); 2775eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson unsigned Rn = MI->getOperand(3).getReg(); 2776eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson return (Rt == Rn) ? 4 : 3; 2777eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson } 2778eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson 2779eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::STRD_PRE: { 2780eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson unsigned Rm = MI->getOperand(4).getReg(); 2781eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson if (Rm) 2782eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson return (ARM_AM::getAM3Op(MI->getOperand(5).getImm()) == ARM_AM::sub) ?5:4; 2783eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson return 3; 2784eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson } 2785eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson 2786eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::t2STRD_PRE: 2787eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson return 3; 2788eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson 2789eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::t2LDR_POST: 2790eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::t2LDRB_POST: 2791eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::t2LDRB_PRE: 2792eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::t2LDRSBi12: 2793eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::t2LDRSBi8: 2794eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::t2LDRSBpci: 2795eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::t2LDRSBs: 2796eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::t2LDRH_POST: 2797eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::t2LDRH_PRE: 2798eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::t2LDRSBT: 2799eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::t2LDRSB_POST: 2800eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::t2LDRSB_PRE: 2801eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::t2LDRSH_POST: 2802eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::t2LDRSH_PRE: 2803eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::t2LDRSHi12: 2804eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::t2LDRSHi8: 2805eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::t2LDRSHpci: 2806eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::t2LDRSHs: 2807eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson return 2; 2808eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson 2809eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::t2LDRDi8: { 2810eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson unsigned Rt = MI->getOperand(0).getReg(); 2811eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson unsigned Rn = MI->getOperand(2).getReg(); 2812eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson return (Rt == Rn) ? 3 : 2; 2813eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson } 2814eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson 2815eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::t2STRB_POST: 2816eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::t2STRB_PRE: 2817eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::t2STRBs: 2818eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::t2STRDi8: 2819eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::t2STRH_POST: 2820eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::t2STRH_PRE: 2821eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::t2STRHs: 2822eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::t2STR_POST: 2823eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::t2STR_PRE: 2824eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::t2STRs: 2825eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson return 2; 2826eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson } 2827eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson} 2828eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson 28299eed53379f19f836769a0c4a14042eeb1b587769Andrew Trick// Return the number of 32-bit words loaded by LDM or stored by STM. If this 28309eed53379f19f836769a0c4a14042eeb1b587769Andrew Trick// can't be easily determined return 0 (missing MachineMemOperand). 28319eed53379f19f836769a0c4a14042eeb1b587769Andrew Trick// 28329eed53379f19f836769a0c4a14042eeb1b587769Andrew Trick// FIXME: The current MachineInstr design does not support relying on machine 28339eed53379f19f836769a0c4a14042eeb1b587769Andrew Trick// mem operands to determine the width of a memory access. Instead, we expect 28349eed53379f19f836769a0c4a14042eeb1b587769Andrew Trick// the target to provide this information based on the instruction opcode and 28359eed53379f19f836769a0c4a14042eeb1b587769Andrew Trick// operands. However, using MachineMemOperand is a the best solution now for 28369eed53379f19f836769a0c4a14042eeb1b587769Andrew Trick// two reasons: 28379eed53379f19f836769a0c4a14042eeb1b587769Andrew Trick// 28389eed53379f19f836769a0c4a14042eeb1b587769Andrew Trick// 1) getNumMicroOps tries to infer LDM memory width from the total number of MI 28399eed53379f19f836769a0c4a14042eeb1b587769Andrew Trick// operands. This is much more dangerous than using the MachineMemOperand 28409eed53379f19f836769a0c4a14042eeb1b587769Andrew Trick// sizes because CodeGen passes can insert/remove optional machine operands. In 28419eed53379f19f836769a0c4a14042eeb1b587769Andrew Trick// fact, it's totally incorrect for preRA passes and appears to be wrong for 28429eed53379f19f836769a0c4a14042eeb1b587769Andrew Trick// postRA passes as well. 28439eed53379f19f836769a0c4a14042eeb1b587769Andrew Trick// 28449eed53379f19f836769a0c4a14042eeb1b587769Andrew Trick// 2) getNumLDMAddresses is only used by the scheduling machine model and any 28459eed53379f19f836769a0c4a14042eeb1b587769Andrew Trick// machine model that calls this should handle the unknown (zero size) case. 28469eed53379f19f836769a0c4a14042eeb1b587769Andrew Trick// 28479eed53379f19f836769a0c4a14042eeb1b587769Andrew Trick// Long term, we should require a target hook that verifies MachineMemOperand 28489eed53379f19f836769a0c4a14042eeb1b587769Andrew Trick// sizes during MC lowering. That target hook should be local to MC lowering 28499eed53379f19f836769a0c4a14042eeb1b587769Andrew Trick// because we can't ensure that it is aware of other MI forms. Doing this will 28509eed53379f19f836769a0c4a14042eeb1b587769Andrew Trick// ensure that MachineMemOperands are correctly propagated through all passes. 28519eed53379f19f836769a0c4a14042eeb1b587769Andrew Trickunsigned ARMBaseInstrInfo::getNumLDMAddresses(const MachineInstr *MI) const { 28529eed53379f19f836769a0c4a14042eeb1b587769Andrew Trick unsigned Size = 0; 28539eed53379f19f836769a0c4a14042eeb1b587769Andrew Trick for (MachineInstr::mmo_iterator I = MI->memoperands_begin(), 28549eed53379f19f836769a0c4a14042eeb1b587769Andrew Trick E = MI->memoperands_end(); I != E; ++I) { 28559eed53379f19f836769a0c4a14042eeb1b587769Andrew Trick Size += (*I)->getSize(); 28569eed53379f19f836769a0c4a14042eeb1b587769Andrew Trick } 28579eed53379f19f836769a0c4a14042eeb1b587769Andrew Trick return Size / 4; 28589eed53379f19f836769a0c4a14042eeb1b587769Andrew Trick} 28599eed53379f19f836769a0c4a14042eeb1b587769Andrew Trick 28605f54ce347368105260be2cec497b6a4199dc5789Evan Chengunsigned 28618239daf7c83a65a189c352cce3191cdc3bbfe151Evan ChengARMBaseInstrInfo::getNumMicroOps(const InstrItineraryData *ItinData, 28628239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng const MachineInstr *MI) const { 28633ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng if (!ItinData || ItinData->isEmpty()) 28645f54ce347368105260be2cec497b6a4199dc5789Evan Cheng return 1; 28655f54ce347368105260be2cec497b6a4199dc5789Evan Cheng 2866e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng const MCInstrDesc &Desc = MI->getDesc(); 28675f54ce347368105260be2cec497b6a4199dc5789Evan Cheng unsigned Class = Desc.getSchedClass(); 2868218ee74a011c0d350099c452810da0bd57a15047Andrew Trick int ItinUOps = ItinData->getNumMicroOps(Class); 2869eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson if (ItinUOps >= 0) { 2870eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson if (Subtarget.isSwift() && (Desc.mayLoad() || Desc.mayStore())) 2871eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson return getNumMicroOpsSwiftLdSt(ItinData, MI); 2872eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson 2873218ee74a011c0d350099c452810da0bd57a15047Andrew Trick return ItinUOps; 2874eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson } 28755f54ce347368105260be2cec497b6a4199dc5789Evan Cheng 28765f54ce347368105260be2cec497b6a4199dc5789Evan Cheng unsigned Opc = MI->getOpcode(); 28775f54ce347368105260be2cec497b6a4199dc5789Evan Cheng switch (Opc) { 28785f54ce347368105260be2cec497b6a4199dc5789Evan Cheng default: 28795f54ce347368105260be2cec497b6a4199dc5789Evan Cheng llvm_unreachable("Unexpected multi-uops instruction!"); 288073fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMQIA: 288173fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMQIA: 28825f54ce347368105260be2cec497b6a4199dc5789Evan Cheng return 2; 28835f54ce347368105260be2cec497b6a4199dc5789Evan Cheng 28845f54ce347368105260be2cec497b6a4199dc5789Evan Cheng // The number of uOps for load / store multiple are determined by the number 28855f54ce347368105260be2cec497b6a4199dc5789Evan Cheng // registers. 28866e8f4c404825b79f9b9176483653f1aa927dfbdeAndrew Trick // 28873ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng // On Cortex-A8, each pair of register loads / stores can be scheduled on the 28883ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng // same cycle. The scheduling for the first load / store must be done 2889c8e41c591741b3da1077f7000274ad040bef8002Sylvestre Ledru // separately by assuming the address is not 64-bit aligned. 289073fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling // 28913ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng // On Cortex-A9, the formula is simply (#reg / 2) + (#reg % 2). If the address 289273fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling // is not 64-bit aligned, then AGU would take an extra cycle. For VFP / NEON 289373fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling // load / store multiple, the formula is (#reg / 2) + (#reg % 2) + 1. 289473fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMDIA: 289573fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMDIA_UPD: 289673fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMDDB_UPD: 289773fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMSIA: 289873fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMSIA_UPD: 289973fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMSDB_UPD: 290073fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMDIA: 290173fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMDIA_UPD: 290273fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMDDB_UPD: 290373fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMSIA: 290473fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMSIA_UPD: 290573fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMSDB_UPD: { 29065f54ce347368105260be2cec497b6a4199dc5789Evan Cheng unsigned NumRegs = MI->getNumOperands() - Desc.getNumOperands(); 29075f54ce347368105260be2cec497b6a4199dc5789Evan Cheng return (NumRegs / 2) + (NumRegs % 2) + 1; 29085f54ce347368105260be2cec497b6a4199dc5789Evan Cheng } 290973fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling 291073fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMIA_RET: 291173fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMIA: 291273fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMDA: 291373fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMDB: 291473fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMIB: 291573fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMIA_UPD: 291673fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMDA_UPD: 291773fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMDB_UPD: 291873fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMIB_UPD: 291973fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::STMIA: 292073fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::STMDA: 292173fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::STMDB: 292273fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::STMIB: 292373fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::STMIA_UPD: 292473fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::STMDA_UPD: 292573fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::STMDB_UPD: 292673fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::STMIB_UPD: 292773fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::tLDMIA: 292873fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::tLDMIA_UPD: 292973fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::tSTMIA_UPD: 29305f54ce347368105260be2cec497b6a4199dc5789Evan Cheng case ARM::tPOP_RET: 29315f54ce347368105260be2cec497b6a4199dc5789Evan Cheng case ARM::tPOP: 29325f54ce347368105260be2cec497b6a4199dc5789Evan Cheng case ARM::tPUSH: 293373fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2LDMIA_RET: 293473fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2LDMIA: 293573fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2LDMDB: 293673fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2LDMIA_UPD: 293773fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2LDMDB_UPD: 293873fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2STMIA: 293973fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2STMDB: 294073fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2STMIA_UPD: 294173fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2STMDB_UPD: { 29423ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng unsigned NumRegs = MI->getNumOperands() - Desc.getNumOperands() + 1; 2943eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson if (Subtarget.isSwift()) { 2944eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson int UOps = 1 + NumRegs; // One for address computation, one for each ld / st. 2945eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson switch (Opc) { 2946eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson default: break; 2947eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::VLDMDIA_UPD: 2948eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::VLDMDDB_UPD: 2949eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::VLDMSIA_UPD: 2950eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::VLDMSDB_UPD: 2951eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::VSTMDIA_UPD: 2952eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::VSTMDDB_UPD: 2953eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::VSTMSIA_UPD: 2954eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::VSTMSDB_UPD: 2955eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::LDMIA_UPD: 2956eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::LDMDA_UPD: 2957eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::LDMDB_UPD: 2958eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::LDMIB_UPD: 2959eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::STMIA_UPD: 2960eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::STMDA_UPD: 2961eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::STMDB_UPD: 2962eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::STMIB_UPD: 2963eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::tLDMIA_UPD: 2964eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::tSTMIA_UPD: 2965eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::t2LDMIA_UPD: 2966eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::t2LDMDB_UPD: 2967eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::t2STMIA_UPD: 2968eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::t2STMDB_UPD: 2969eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson ++UOps; // One for base register writeback. 2970eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson break; 2971eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::LDMIA_RET: 2972eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::tPOP_RET: 2973eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::t2LDMIA_RET: 2974eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson UOps += 2; // One for base reg wb, one for write to pc. 2975eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson break; 2976eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson } 2977eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson return UOps; 297836b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines } else if (Subtarget.isCortexA8() || Subtarget.isCortexA7()) { 29798239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng if (NumRegs < 4) 29808239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng return 2; 29818239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng // 4 registers would be issued: 2, 2. 29828239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng // 5 registers would be issued: 2, 2, 1. 2983218ee74a011c0d350099c452810da0bd57a15047Andrew Trick int A8UOps = (NumRegs / 2); 29848239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng if (NumRegs % 2) 2985218ee74a011c0d350099c452810da0bd57a15047Andrew Trick ++A8UOps; 2986218ee74a011c0d350099c452810da0bd57a15047Andrew Trick return A8UOps; 2987eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson } else if (Subtarget.isLikeA9() || Subtarget.isSwift()) { 2988218ee74a011c0d350099c452810da0bd57a15047Andrew Trick int A9UOps = (NumRegs / 2); 29893ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng // If there are odd number of registers or if it's not 64-bit aligned, 29903ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng // then it takes an extra AGU (Address Generation Unit) cycle. 29913ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng if ((NumRegs % 2) || 29923ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng !MI->hasOneMemOperand() || 29933ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng (*MI->memoperands_begin())->getAlignment() < 8) 2994218ee74a011c0d350099c452810da0bd57a15047Andrew Trick ++A9UOps; 2995218ee74a011c0d350099c452810da0bd57a15047Andrew Trick return A9UOps; 29963ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng } else { 29973ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng // Assume the worst. 29983ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng return NumRegs; 29992bbb76909126db5bed6bde84b16d94ab5de4d372Michael J. Spencer } 30005f54ce347368105260be2cec497b6a4199dc5789Evan Cheng } 30015f54ce347368105260be2cec497b6a4199dc5789Evan Cheng } 30025f54ce347368105260be2cec497b6a4199dc5789Evan Cheng} 3003a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng 3004a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Chengint 3005344d9db97062736cd66da6c07baa9108b6cfa419Evan ChengARMBaseInstrInfo::getVLDMDefCycle(const InstrItineraryData *ItinData, 3006e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng const MCInstrDesc &DefMCID, 3007344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng unsigned DefClass, 3008344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng unsigned DefIdx, unsigned DefAlign) const { 3009e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng int RegNo = (int)(DefIdx+1) - DefMCID.getNumOperands() + 1; 3010344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng if (RegNo <= 0) 3011344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // Def is the address writeback. 3012344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng return ItinData->getOperandCycle(DefClass, DefIdx); 3013344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng 3014344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng int DefCycle; 301536b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines if (Subtarget.isCortexA8() || Subtarget.isCortexA7()) { 3016344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // (regno / 2) + (regno % 2) + 1 3017344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng DefCycle = RegNo / 2 + 1; 3018344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng if (RegNo % 2) 3019344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng ++DefCycle; 3020eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson } else if (Subtarget.isLikeA9() || Subtarget.isSwift()) { 3021344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng DefCycle = RegNo; 3022344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng bool isSLoad = false; 302373fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling 3024e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng switch (DefMCID.getOpcode()) { 3025344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng default: break; 302673fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMSIA: 302773fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMSIA_UPD: 302873fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMSDB_UPD: 3029344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng isSLoad = true; 3030344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng break; 3031344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng } 303273fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling 3033344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // If there are odd number of 'S' registers or if it's not 64-bit aligned, 3034344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // then it takes an extra cycle. 3035344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng if ((isSLoad && (RegNo % 2)) || DefAlign < 8) 3036344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng ++DefCycle; 3037344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng } else { 3038344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // Assume the worst. 3039344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng DefCycle = RegNo + 2; 3040344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng } 3041344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng 3042344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng return DefCycle; 3043344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng} 3044344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng 3045344d9db97062736cd66da6c07baa9108b6cfa419Evan Chengint 3046344d9db97062736cd66da6c07baa9108b6cfa419Evan ChengARMBaseInstrInfo::getLDMDefCycle(const InstrItineraryData *ItinData, 3047e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng const MCInstrDesc &DefMCID, 3048344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng unsigned DefClass, 3049344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng unsigned DefIdx, unsigned DefAlign) const { 3050e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng int RegNo = (int)(DefIdx+1) - DefMCID.getNumOperands() + 1; 3051344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng if (RegNo <= 0) 3052344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // Def is the address writeback. 3053344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng return ItinData->getOperandCycle(DefClass, DefIdx); 3054344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng 3055344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng int DefCycle; 305636b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines if (Subtarget.isCortexA8() || Subtarget.isCortexA7()) { 3057344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // 4 registers would be issued: 1, 2, 1. 3058344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // 5 registers would be issued: 1, 2, 2. 3059344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng DefCycle = RegNo / 2; 3060344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng if (DefCycle < 1) 3061344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng DefCycle = 1; 3062344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // Result latency is issue cycle + 2: E2. 3063344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng DefCycle += 2; 3064eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson } else if (Subtarget.isLikeA9() || Subtarget.isSwift()) { 3065344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng DefCycle = (RegNo / 2); 3066344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // If there are odd number of registers or if it's not 64-bit aligned, 3067344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // then it takes an extra AGU (Address Generation Unit) cycle. 3068344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng if ((RegNo % 2) || DefAlign < 8) 3069344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng ++DefCycle; 3070344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // Result latency is AGU cycles + 2. 3071344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng DefCycle += 2; 3072344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng } else { 3073344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // Assume the worst. 3074344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng DefCycle = RegNo + 2; 3075344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng } 3076344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng 3077344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng return DefCycle; 3078344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng} 3079344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng 3080344d9db97062736cd66da6c07baa9108b6cfa419Evan Chengint 3081344d9db97062736cd66da6c07baa9108b6cfa419Evan ChengARMBaseInstrInfo::getVSTMUseCycle(const InstrItineraryData *ItinData, 3082e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng const MCInstrDesc &UseMCID, 3083344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng unsigned UseClass, 3084344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng unsigned UseIdx, unsigned UseAlign) const { 3085e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng int RegNo = (int)(UseIdx+1) - UseMCID.getNumOperands() + 1; 3086344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng if (RegNo <= 0) 3087344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng return ItinData->getOperandCycle(UseClass, UseIdx); 3088344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng 3089344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng int UseCycle; 309036b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines if (Subtarget.isCortexA8() || Subtarget.isCortexA7()) { 3091344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // (regno / 2) + (regno % 2) + 1 3092344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng UseCycle = RegNo / 2 + 1; 3093344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng if (RegNo % 2) 3094344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng ++UseCycle; 3095eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson } else if (Subtarget.isLikeA9() || Subtarget.isSwift()) { 3096344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng UseCycle = RegNo; 3097344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng bool isSStore = false; 309873fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling 3099e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng switch (UseMCID.getOpcode()) { 3100344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng default: break; 310173fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMSIA: 310273fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMSIA_UPD: 310373fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMSDB_UPD: 3104344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng isSStore = true; 3105344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng break; 3106344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng } 310773fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling 3108344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // If there are odd number of 'S' registers or if it's not 64-bit aligned, 3109344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // then it takes an extra cycle. 3110344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng if ((isSStore && (RegNo % 2)) || UseAlign < 8) 3111344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng ++UseCycle; 3112344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng } else { 3113344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // Assume the worst. 3114344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng UseCycle = RegNo + 2; 3115344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng } 3116344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng 3117344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng return UseCycle; 3118344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng} 3119344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng 3120344d9db97062736cd66da6c07baa9108b6cfa419Evan Chengint 3121344d9db97062736cd66da6c07baa9108b6cfa419Evan ChengARMBaseInstrInfo::getSTMUseCycle(const InstrItineraryData *ItinData, 3122e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng const MCInstrDesc &UseMCID, 3123344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng unsigned UseClass, 3124344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng unsigned UseIdx, unsigned UseAlign) const { 3125e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng int RegNo = (int)(UseIdx+1) - UseMCID.getNumOperands() + 1; 3126344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng if (RegNo <= 0) 3127344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng return ItinData->getOperandCycle(UseClass, UseIdx); 3128344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng 3129344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng int UseCycle; 313036b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines if (Subtarget.isCortexA8() || Subtarget.isCortexA7()) { 3131344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng UseCycle = RegNo / 2; 3132344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng if (UseCycle < 2) 3133344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng UseCycle = 2; 3134344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // Read in E3. 3135344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng UseCycle += 2; 3136eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson } else if (Subtarget.isLikeA9() || Subtarget.isSwift()) { 3137344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng UseCycle = (RegNo / 2); 3138344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // If there are odd number of registers or if it's not 64-bit aligned, 3139344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // then it takes an extra AGU (Address Generation Unit) cycle. 3140344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng if ((RegNo % 2) || UseAlign < 8) 3141344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng ++UseCycle; 3142344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng } else { 3143344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // Assume the worst. 3144344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng UseCycle = 1; 3145344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng } 3146344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng return UseCycle; 3147344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng} 3148344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng 3149344d9db97062736cd66da6c07baa9108b6cfa419Evan Chengint 3150a0792de66c8364d47b0a688c7f408efb7b10f31bEvan ChengARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData, 3151e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng const MCInstrDesc &DefMCID, 3152a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng unsigned DefIdx, unsigned DefAlign, 3153e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng const MCInstrDesc &UseMCID, 3154a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng unsigned UseIdx, unsigned UseAlign) const { 3155e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng unsigned DefClass = DefMCID.getSchedClass(); 3156e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng unsigned UseClass = UseMCID.getSchedClass(); 3157a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng 3158e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng if (DefIdx < DefMCID.getNumDefs() && UseIdx < UseMCID.getNumOperands()) 3159a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx); 3160a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng 3161a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng // This may be a def / use of a variable_ops instruction, the operand 3162a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng // latency might be determinable dynamically. Let the target try to 3163a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng // figure it out. 31649e08ee5d16b596078e20787f0b5f36121f099333Evan Cheng int DefCycle = -1; 31657e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng bool LdmBypass = false; 3166e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng switch (DefMCID.getOpcode()) { 3167a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng default: 3168a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng DefCycle = ItinData->getOperandCycle(DefClass, DefIdx); 3169a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng break; 317073fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling 317173fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMDIA: 317273fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMDIA_UPD: 317373fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMDDB_UPD: 317473fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMSIA: 317573fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMSIA_UPD: 317673fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMSDB_UPD: 3177e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng DefCycle = getVLDMDefCycle(ItinData, DefMCID, DefClass, DefIdx, DefAlign); 31785a50ceeaea980962c1982ad535226c7ab06c971cEvan Cheng break; 317973fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling 318073fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMIA_RET: 318173fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMIA: 318273fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMDA: 318373fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMDB: 318473fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMIB: 318573fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMIA_UPD: 318673fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMDA_UPD: 318773fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMDB_UPD: 318873fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMIB_UPD: 318973fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::tLDMIA: 319073fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::tLDMIA_UPD: 3191a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng case ARM::tPUSH: 319273fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2LDMIA_RET: 319373fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2LDMIA: 319473fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2LDMDB: 319573fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2LDMIA_UPD: 319673fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2LDMDB_UPD: 3197a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng LdmBypass = 1; 3198e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng DefCycle = getLDMDefCycle(ItinData, DefMCID, DefClass, DefIdx, DefAlign); 3199344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng break; 3200a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng } 3201a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng 3202a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng if (DefCycle == -1) 3203a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng // We can't seem to determine the result latency of the def, assume it's 2. 3204a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng DefCycle = 2; 3205a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng 3206a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng int UseCycle = -1; 3207e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng switch (UseMCID.getOpcode()) { 3208a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng default: 3209a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng UseCycle = ItinData->getOperandCycle(UseClass, UseIdx); 3210a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng break; 321173fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling 321273fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMDIA: 321373fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMDIA_UPD: 321473fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMDDB_UPD: 321573fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMSIA: 321673fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMSIA_UPD: 321773fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMSDB_UPD: 3218e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng UseCycle = getVSTMUseCycle(ItinData, UseMCID, UseClass, UseIdx, UseAlign); 32195a50ceeaea980962c1982ad535226c7ab06c971cEvan Cheng break; 322073fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling 322173fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::STMIA: 322273fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::STMDA: 322373fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::STMDB: 322473fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::STMIB: 322573fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::STMIA_UPD: 322673fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::STMDA_UPD: 322773fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::STMDB_UPD: 322873fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::STMIB_UPD: 322973fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::tSTMIA_UPD: 3230a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng case ARM::tPOP_RET: 3231a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng case ARM::tPOP: 323273fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2STMIA: 323373fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2STMDB: 323473fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2STMIA_UPD: 323573fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2STMDB_UPD: 3236e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng UseCycle = getSTMUseCycle(ItinData, UseMCID, UseClass, UseIdx, UseAlign); 32375a50ceeaea980962c1982ad535226c7ab06c971cEvan Cheng break; 3238a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng } 3239a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng 3240a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng if (UseCycle == -1) 3241a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng // Assume it's read in the first stage. 3242a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng UseCycle = 1; 3243a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng 3244a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng UseCycle = DefCycle - UseCycle + 1; 3245a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng if (UseCycle > 0) { 3246a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng if (LdmBypass) { 3247a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng // It's a variable_ops instruction so we can't use DefIdx here. Just use 3248a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng // first def operand. 3249e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng if (ItinData->hasPipelineForwarding(DefClass, DefMCID.getNumOperands()-1, 3250a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng UseClass, UseIdx)) 3251a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng --UseCycle; 3252a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng } else if (ItinData->hasPipelineForwarding(DefClass, DefIdx, 325373fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling UseClass, UseIdx)) { 3254a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng --UseCycle; 325573fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling } 3256a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng } 3257a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng 3258a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng return UseCycle; 3259a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng} 3260a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng 3261ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Chengstatic const MachineInstr *getBundledDefMI(const TargetRegisterInfo *TRI, 3262020f4106f820648fd7e91956859844a80de13974Evan Cheng const MachineInstr *MI, unsigned Reg, 3263ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng unsigned &DefIdx, unsigned &Dist) { 3264ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng Dist = 0; 3265ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng 3266ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng MachineBasicBlock::const_iterator I = MI; ++I; 326736b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines MachineBasicBlock::const_instr_iterator II = std::prev(I.getInstrIterator()); 3268ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng assert(II->isInsideBundle() && "Empty bundle?"); 3269ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng 3270ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng int Idx = -1; 3271ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng while (II->isInsideBundle()) { 3272ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng Idx = II->findRegisterDefOperandIdx(Reg, false, true, TRI); 3273ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng if (Idx != -1) 3274ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng break; 3275ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng --II; 3276ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng ++Dist; 3277ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng } 3278ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng 3279ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng assert(Idx != -1 && "Cannot find bundled definition!"); 3280ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng DefIdx = Idx; 3281ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng return II; 3282ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng} 3283ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng 3284ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Chengstatic const MachineInstr *getBundledUseMI(const TargetRegisterInfo *TRI, 3285020f4106f820648fd7e91956859844a80de13974Evan Cheng const MachineInstr *MI, unsigned Reg, 3286ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng unsigned &UseIdx, unsigned &Dist) { 3287ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng Dist = 0; 3288ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng 3289ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng MachineBasicBlock::const_instr_iterator II = MI; ++II; 3290ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng assert(II->isInsideBundle() && "Empty bundle?"); 3291ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end(); 3292ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng 3293ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng // FIXME: This doesn't properly handle multiple uses. 3294ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng int Idx = -1; 3295ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng while (II != E && II->isInsideBundle()) { 3296ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng Idx = II->findRegisterUseOperandIdx(Reg, false, TRI); 3297ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng if (Idx != -1) 3298ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng break; 3299ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng if (II->getOpcode() != ARM::t2IT) 3300ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng ++Dist; 3301ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng ++II; 3302ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng } 3303ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng 3304020f4106f820648fd7e91956859844a80de13974Evan Cheng if (Idx == -1) { 3305020f4106f820648fd7e91956859844a80de13974Evan Cheng Dist = 0; 3306dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines return nullptr; 3307020f4106f820648fd7e91956859844a80de13974Evan Cheng } 3308020f4106f820648fd7e91956859844a80de13974Evan Cheng 3309ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng UseIdx = Idx; 3310ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng return II; 3311ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng} 3312ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng 331368b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick/// Return the number of cycles to add to (or subtract from) the static 331468b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick/// itinerary based on the def opcode and alignment. The caller will ensure that 331568b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick/// adjusted latency is at least one cycle. 331668b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trickstatic int adjustDefLatency(const ARMSubtarget &Subtarget, 331768b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick const MachineInstr *DefMI, 331868b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick const MCInstrDesc *DefMCID, unsigned DefAlign) { 331968b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick int Adjust = 0; 332036b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines if (Subtarget.isCortexA8() || Subtarget.isLikeA9() || Subtarget.isCortexA7()) { 33217e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng // FIXME: Shifter op hack: no shift (i.e. [r +/- r]) or [r + r << 2] 33227e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng // variants are one cycle cheaper. 3323ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng switch (DefMCID->getOpcode()) { 33247e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng default: break; 3325cff9baa95273bc279bf5fadb9e27afbd25cca20bJakob Stoklund Olesen case ARM::LDRrs: 3326cff9baa95273bc279bf5fadb9e27afbd25cca20bJakob Stoklund Olesen case ARM::LDRBrs: { 33277e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng unsigned ShOpVal = DefMI->getOperand(3).getImm(); 33287e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal); 33297e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng if (ShImm == 0 || 33307e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng (ShImm == 2 && ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl)) 333168b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick --Adjust; 33327e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng break; 33337e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng } 3334cff9baa95273bc279bf5fadb9e27afbd25cca20bJakob Stoklund Olesen case ARM::t2LDRs: 3335cff9baa95273bc279bf5fadb9e27afbd25cca20bJakob Stoklund Olesen case ARM::t2LDRBs: 3336cff9baa95273bc279bf5fadb9e27afbd25cca20bJakob Stoklund Olesen case ARM::t2LDRHs: 33377e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng case ARM::t2LDRSHs: { 33387e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng // Thumb2 mode: lsl only. 33397e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng unsigned ShAmt = DefMI->getOperand(3).getImm(); 33407e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng if (ShAmt == 0 || ShAmt == 2) 334168b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick --Adjust; 33427e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng break; 33437e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng } 33447e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng } 3345eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson } else if (Subtarget.isSwift()) { 3346eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson // FIXME: Properly handle all of the latency adjustments for address 3347eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson // writeback. 3348eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson switch (DefMCID->getOpcode()) { 3349eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson default: break; 3350eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::LDRrs: 3351eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::LDRBrs: { 3352eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson unsigned ShOpVal = DefMI->getOperand(3).getImm(); 3353eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson bool isSub = ARM_AM::getAM2Op(ShOpVal) == ARM_AM::sub; 3354eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal); 3355eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson if (!isSub && 3356eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson (ShImm == 0 || 3357eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson ((ShImm == 1 || ShImm == 2 || ShImm == 3) && 3358eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl))) 3359eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson Adjust -= 2; 3360eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson else if (!isSub && 3361eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson ShImm == 1 && ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsr) 3362eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson --Adjust; 3363eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson break; 3364eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson } 3365eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::t2LDRs: 3366eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::t2LDRBs: 3367eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::t2LDRHs: 3368eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::t2LDRSHs: { 3369eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson // Thumb2 mode: lsl only. 3370eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson unsigned ShAmt = DefMI->getOperand(3).getImm(); 3371eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson if (ShAmt == 0 || ShAmt == 1 || ShAmt == 2 || ShAmt == 3) 3372eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson Adjust -= 2; 3373eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson break; 3374eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson } 3375eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson } 33767e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng } 33777e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng 3378616471d4bfe4717fa86259ff4534703357b3b723Silviu Baranga if (DefAlign < 8 && Subtarget.isLikeA9()) { 3379ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng switch (DefMCID->getOpcode()) { 338075b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng default: break; 338175b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1q8: 338275b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1q16: 338375b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1q32: 338475b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1q64: 338510b90a9bbf7dcae1568c03a03f9606f5395f2144Jim Grosbach case ARM::VLD1q8wb_fixed: 338610b90a9bbf7dcae1568c03a03f9606f5395f2144Jim Grosbach case ARM::VLD1q16wb_fixed: 338710b90a9bbf7dcae1568c03a03f9606f5395f2144Jim Grosbach case ARM::VLD1q32wb_fixed: 338810b90a9bbf7dcae1568c03a03f9606f5395f2144Jim Grosbach case ARM::VLD1q64wb_fixed: 338910b90a9bbf7dcae1568c03a03f9606f5395f2144Jim Grosbach case ARM::VLD1q8wb_register: 339010b90a9bbf7dcae1568c03a03f9606f5395f2144Jim Grosbach case ARM::VLD1q16wb_register: 339110b90a9bbf7dcae1568c03a03f9606f5395f2144Jim Grosbach case ARM::VLD1q32wb_register: 339210b90a9bbf7dcae1568c03a03f9606f5395f2144Jim Grosbach case ARM::VLD1q64wb_register: 339375b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2d8: 339475b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2d16: 339575b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2d32: 339675b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2q8: 339775b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2q16: 339875b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2q32: 3399a4e3c7fc4ba2d55695b0484480685698132eba20Jim Grosbach case ARM::VLD2d8wb_fixed: 3400a4e3c7fc4ba2d55695b0484480685698132eba20Jim Grosbach case ARM::VLD2d16wb_fixed: 3401a4e3c7fc4ba2d55695b0484480685698132eba20Jim Grosbach case ARM::VLD2d32wb_fixed: 3402a4e3c7fc4ba2d55695b0484480685698132eba20Jim Grosbach case ARM::VLD2q8wb_fixed: 3403a4e3c7fc4ba2d55695b0484480685698132eba20Jim Grosbach case ARM::VLD2q16wb_fixed: 3404a4e3c7fc4ba2d55695b0484480685698132eba20Jim Grosbach case ARM::VLD2q32wb_fixed: 3405a4e3c7fc4ba2d55695b0484480685698132eba20Jim Grosbach case ARM::VLD2d8wb_register: 3406a4e3c7fc4ba2d55695b0484480685698132eba20Jim Grosbach case ARM::VLD2d16wb_register: 3407a4e3c7fc4ba2d55695b0484480685698132eba20Jim Grosbach case ARM::VLD2d32wb_register: 3408a4e3c7fc4ba2d55695b0484480685698132eba20Jim Grosbach case ARM::VLD2q8wb_register: 3409a4e3c7fc4ba2d55695b0484480685698132eba20Jim Grosbach case ARM::VLD2q16wb_register: 3410a4e3c7fc4ba2d55695b0484480685698132eba20Jim Grosbach case ARM::VLD2q32wb_register: 341175b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3d8: 341275b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3d16: 341375b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3d32: 341475b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1d64T: 341575b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3d8_UPD: 341675b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3d16_UPD: 341775b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3d32_UPD: 34185921675ff5ea632ab1e6d7aa5d1f263b858bbafaJim Grosbach case ARM::VLD1d64Twb_fixed: 34195921675ff5ea632ab1e6d7aa5d1f263b858bbafaJim Grosbach case ARM::VLD1d64Twb_register: 342075b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3q8_UPD: 342175b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3q16_UPD: 342275b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3q32_UPD: 342375b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4d8: 342475b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4d16: 342575b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4d32: 342675b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1d64Q: 342775b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4d8_UPD: 342875b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4d16_UPD: 342975b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4d32_UPD: 3430399cdca4d201f7232126c3a0643669971ede780aJim Grosbach case ARM::VLD1d64Qwb_fixed: 3431399cdca4d201f7232126c3a0643669971ede780aJim Grosbach case ARM::VLD1d64Qwb_register: 343275b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4q8_UPD: 343375b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4q16_UPD: 343475b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4q32_UPD: 343575b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1DUPq8: 343675b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1DUPq16: 343775b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1DUPq32: 3438096334e25ea68ac970942ecb680a82fbb8ad206cJim Grosbach case ARM::VLD1DUPq8wb_fixed: 3439096334e25ea68ac970942ecb680a82fbb8ad206cJim Grosbach case ARM::VLD1DUPq16wb_fixed: 3440096334e25ea68ac970942ecb680a82fbb8ad206cJim Grosbach case ARM::VLD1DUPq32wb_fixed: 3441096334e25ea68ac970942ecb680a82fbb8ad206cJim Grosbach case ARM::VLD1DUPq8wb_register: 3442096334e25ea68ac970942ecb680a82fbb8ad206cJim Grosbach case ARM::VLD1DUPq16wb_register: 3443096334e25ea68ac970942ecb680a82fbb8ad206cJim Grosbach case ARM::VLD1DUPq32wb_register: 344475b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2DUPd8: 344575b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2DUPd16: 344675b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2DUPd32: 3447e6949b13997e6d31aa4719a0e80c4b6b405e42a9Jim Grosbach case ARM::VLD2DUPd8wb_fixed: 3448e6949b13997e6d31aa4719a0e80c4b6b405e42a9Jim Grosbach case ARM::VLD2DUPd16wb_fixed: 3449e6949b13997e6d31aa4719a0e80c4b6b405e42a9Jim Grosbach case ARM::VLD2DUPd32wb_fixed: 3450e6949b13997e6d31aa4719a0e80c4b6b405e42a9Jim Grosbach case ARM::VLD2DUPd8wb_register: 3451e6949b13997e6d31aa4719a0e80c4b6b405e42a9Jim Grosbach case ARM::VLD2DUPd16wb_register: 3452e6949b13997e6d31aa4719a0e80c4b6b405e42a9Jim Grosbach case ARM::VLD2DUPd32wb_register: 345375b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4DUPd8: 345475b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4DUPd16: 345575b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4DUPd32: 345675b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4DUPd8_UPD: 345775b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4DUPd16_UPD: 345875b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4DUPd32_UPD: 345975b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1LNd8: 346075b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1LNd16: 346175b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1LNd32: 346275b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1LNd8_UPD: 346375b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1LNd16_UPD: 346475b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1LNd32_UPD: 346575b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2LNd8: 346675b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2LNd16: 346775b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2LNd32: 346875b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2LNq16: 346975b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2LNq32: 347075b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2LNd8_UPD: 347175b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2LNd16_UPD: 347275b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2LNd32_UPD: 347375b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2LNq16_UPD: 347475b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2LNq32_UPD: 347575b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4LNd8: 347675b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4LNd16: 347775b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4LNd32: 347875b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4LNq16: 347975b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4LNq32: 348075b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4LNd8_UPD: 348175b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4LNd16_UPD: 348275b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4LNd32_UPD: 348375b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4LNq16_UPD: 348475b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4LNq32_UPD: 348575b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng // If the address is not 64-bit aligned, the latencies of these 348675b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng // instructions increases by one. 348768b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick ++Adjust; 348875b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng break; 348975b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng } 349068b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick } 349168b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick return Adjust; 349268b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick} 349368b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick 349475b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng 349568b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick 349668b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trickint 349768b16541cc58411c7b0607ca4c0fb497222b668dAndrew TrickARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData, 349868b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick const MachineInstr *DefMI, unsigned DefIdx, 349968b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick const MachineInstr *UseMI, 350068b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick unsigned UseIdx) const { 350168b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick // No operand latency. The caller may fall back to getInstrLatency. 350268b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick if (!ItinData || ItinData->isEmpty()) 350368b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick return -1; 350468b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick 350568b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick const MachineOperand &DefMO = DefMI->getOperand(DefIdx); 350668b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick unsigned Reg = DefMO.getReg(); 350768b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick const MCInstrDesc *DefMCID = &DefMI->getDesc(); 350868b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick const MCInstrDesc *UseMCID = &UseMI->getDesc(); 350968b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick 351068b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick unsigned DefAdj = 0; 351168b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick if (DefMI->isBundle()) { 351268b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick DefMI = getBundledDefMI(&getRegisterInfo(), DefMI, Reg, DefIdx, DefAdj); 351368b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick DefMCID = &DefMI->getDesc(); 351468b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick } 351568b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick if (DefMI->isCopyLike() || DefMI->isInsertSubreg() || 351668b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick DefMI->isRegSequence() || DefMI->isImplicitDef()) { 351768b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick return 1; 351868b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick } 351968b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick 352068b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick unsigned UseAdj = 0; 352168b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick if (UseMI->isBundle()) { 352268b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick unsigned NewUseIdx; 352368b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick const MachineInstr *NewUseMI = getBundledUseMI(&getRegisterInfo(), UseMI, 352468b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick Reg, NewUseIdx, UseAdj); 3525e2b32bb20ee76f24708b3c9e19b6fbc651c25637Andrew Trick if (!NewUseMI) 3526e2b32bb20ee76f24708b3c9e19b6fbc651c25637Andrew Trick return -1; 3527e2b32bb20ee76f24708b3c9e19b6fbc651c25637Andrew Trick 3528e2b32bb20ee76f24708b3c9e19b6fbc651c25637Andrew Trick UseMI = NewUseMI; 3529e2b32bb20ee76f24708b3c9e19b6fbc651c25637Andrew Trick UseIdx = NewUseIdx; 3530e2b32bb20ee76f24708b3c9e19b6fbc651c25637Andrew Trick UseMCID = &UseMI->getDesc(); 353168b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick } 353268b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick 353368b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick if (Reg == ARM::CPSR) { 353468b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick if (DefMI->getOpcode() == ARM::FMSTAT) { 353568b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick // fpscr -> cpsr stalls over 20 cycles on A8 (and earlier?) 3536616471d4bfe4717fa86259ff4534703357b3b723Silviu Baranga return Subtarget.isLikeA9() ? 1 : 20; 353768b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick } 353868b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick 353968b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick // CPSR set and branch can be paired in the same cycle. 354068b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick if (UseMI->isBranch()) 354168b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick return 0; 354268b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick 354368b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick // Otherwise it takes the instruction latency (generally one). 354468b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick unsigned Latency = getInstrLatency(ItinData, DefMI); 354568b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick 354668b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick // For Thumb2 and -Os, prefer scheduling CPSR setting instruction close to 354768b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick // its uses. Instructions which are otherwise scheduled between them may 354868b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick // incur a code size penalty (not able to use the CPSR setting 16-bit 354968b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick // instructions). 355068b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick if (Latency > 0 && Subtarget.isThumb2()) { 355168b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick const MachineFunction *MF = DefMI->getParent()->getParent(); 3552831737d329a727f53a1fb0572f7b7a8127208881Bill Wendling if (MF->getFunction()->getAttributes(). 3553831737d329a727f53a1fb0572f7b7a8127208881Bill Wendling hasAttribute(AttributeSet::FunctionIndex, 3554831737d329a727f53a1fb0572f7b7a8127208881Bill Wendling Attribute::OptimizeForSize)) 355568b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick --Latency; 355668b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick } 355768b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick return Latency; 355868b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick } 355968b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick 3560e2b32bb20ee76f24708b3c9e19b6fbc651c25637Andrew Trick if (DefMO.isImplicit() || UseMI->getOperand(UseIdx).isImplicit()) 3561e2b32bb20ee76f24708b3c9e19b6fbc651c25637Andrew Trick return -1; 3562e2b32bb20ee76f24708b3c9e19b6fbc651c25637Andrew Trick 356368b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick unsigned DefAlign = DefMI->hasOneMemOperand() 356468b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick ? (*DefMI->memoperands_begin())->getAlignment() : 0; 356568b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick unsigned UseAlign = UseMI->hasOneMemOperand() 356668b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick ? (*UseMI->memoperands_begin())->getAlignment() : 0; 356768b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick 356868b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick // Get the itinerary's latency if possible, and handle variable_ops. 356968b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick int Latency = getOperandLatency(ItinData, *DefMCID, DefIdx, DefAlign, 357068b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick *UseMCID, UseIdx, UseAlign); 357168b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick // Unable to find operand latency. The caller may resort to getInstrLatency. 357268b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick if (Latency < 0) 357368b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick return Latency; 357468b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick 357568b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick // Adjust for IT block position. 357668b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick int Adj = DefAdj + UseAdj; 357768b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick 357868b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick // Adjust for dynamic def-side opcode variants not captured by the itinerary. 357968b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick Adj += adjustDefLatency(Subtarget, DefMI, DefMCID, DefAlign); 358068b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick if (Adj >= 0 || (int)Latency > -Adj) { 358168b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick return Latency + Adj; 358268b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick } 358368b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick // Return the itinerary latency, which may be zero but not less than zero. 35847e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng return Latency; 3585a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng} 3586a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng 3587a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Chengint 3588a0792de66c8364d47b0a688c7f408efb7b10f31bEvan ChengARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData, 3589a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng SDNode *DefNode, unsigned DefIdx, 3590a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng SDNode *UseNode, unsigned UseIdx) const { 3591a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng if (!DefNode->isMachineOpcode()) 3592a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng return 1; 3593a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng 3594e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng const MCInstrDesc &DefMCID = get(DefNode->getMachineOpcode()); 3595c8bfd1d78ff9a307d1d4cb57cce4549b538e60f4Andrew Trick 3596e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng if (isZeroCost(DefMCID.Opcode)) 3597c8bfd1d78ff9a307d1d4cb57cce4549b538e60f4Andrew Trick return 0; 3598c8bfd1d78ff9a307d1d4cb57cce4549b538e60f4Andrew Trick 3599a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng if (!ItinData || ItinData->isEmpty()) 3600e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng return DefMCID.mayLoad() ? 3 : 1; 3601a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng 3602089751535d6e9adf65842e2ca5867bf9a70e1e95Evan Cheng if (!UseNode->isMachineOpcode()) { 3603e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng int Latency = ItinData->getOperandCycle(DefMCID.getSchedClass(), DefIdx); 3604eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson if (Subtarget.isLikeA9() || Subtarget.isSwift()) 3605089751535d6e9adf65842e2ca5867bf9a70e1e95Evan Cheng return Latency <= 2 ? 1 : Latency - 1; 3606089751535d6e9adf65842e2ca5867bf9a70e1e95Evan Cheng else 3607089751535d6e9adf65842e2ca5867bf9a70e1e95Evan Cheng return Latency <= 3 ? 1 : Latency - 2; 3608089751535d6e9adf65842e2ca5867bf9a70e1e95Evan Cheng } 3609a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng 3610e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng const MCInstrDesc &UseMCID = get(UseNode->getMachineOpcode()); 3611a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng const MachineSDNode *DefMN = dyn_cast<MachineSDNode>(DefNode); 3612a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng unsigned DefAlign = !DefMN->memoperands_empty() 3613a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng ? (*DefMN->memoperands_begin())->getAlignment() : 0; 3614a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng const MachineSDNode *UseMN = dyn_cast<MachineSDNode>(UseNode); 3615a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng unsigned UseAlign = !UseMN->memoperands_empty() 3616a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng ? (*UseMN->memoperands_begin())->getAlignment() : 0; 3617e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng int Latency = getOperandLatency(ItinData, DefMCID, DefIdx, DefAlign, 3618e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng UseMCID, UseIdx, UseAlign); 36197e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng 36207e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng if (Latency > 1 && 362136b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines (Subtarget.isCortexA8() || Subtarget.isLikeA9() || 362236b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines Subtarget.isCortexA7())) { 36237e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng // FIXME: Shifter op hack: no shift (i.e. [r +/- r]) or [r + r << 2] 36247e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng // variants are one cycle cheaper. 3625e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng switch (DefMCID.getOpcode()) { 36267e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng default: break; 3627cff9baa95273bc279bf5fadb9e27afbd25cca20bJakob Stoklund Olesen case ARM::LDRrs: 3628cff9baa95273bc279bf5fadb9e27afbd25cca20bJakob Stoklund Olesen case ARM::LDRBrs: { 36297e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng unsigned ShOpVal = 36307e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng cast<ConstantSDNode>(DefNode->getOperand(2))->getZExtValue(); 36317e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal); 36327e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng if (ShImm == 0 || 36337e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng (ShImm == 2 && ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl)) 36347e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng --Latency; 36357e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng break; 36367e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng } 3637cff9baa95273bc279bf5fadb9e27afbd25cca20bJakob Stoklund Olesen case ARM::t2LDRs: 3638cff9baa95273bc279bf5fadb9e27afbd25cca20bJakob Stoklund Olesen case ARM::t2LDRBs: 3639cff9baa95273bc279bf5fadb9e27afbd25cca20bJakob Stoklund Olesen case ARM::t2LDRHs: 36407e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng case ARM::t2LDRSHs: { 36417e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng // Thumb2 mode: lsl only. 36427e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng unsigned ShAmt = 36437e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng cast<ConstantSDNode>(DefNode->getOperand(2))->getZExtValue(); 36447e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng if (ShAmt == 0 || ShAmt == 2) 36457e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng --Latency; 36467e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng break; 36477e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng } 36487e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng } 3649eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson } else if (DefIdx == 0 && Latency > 2 && Subtarget.isSwift()) { 3650eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson // FIXME: Properly handle all of the latency adjustments for address 3651eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson // writeback. 3652eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson switch (DefMCID.getOpcode()) { 3653eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson default: break; 3654eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::LDRrs: 3655eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::LDRBrs: { 3656eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson unsigned ShOpVal = 3657eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson cast<ConstantSDNode>(DefNode->getOperand(2))->getZExtValue(); 3658eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal); 3659eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson if (ShImm == 0 || 3660eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson ((ShImm == 1 || ShImm == 2 || ShImm == 3) && 3661eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl)) 3662eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson Latency -= 2; 3663eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson else if (ShImm == 1 && ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsr) 3664eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson --Latency; 3665eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson break; 3666eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson } 3667eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::t2LDRs: 3668eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::t2LDRBs: 3669eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::t2LDRHs: 3670eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::t2LDRSHs: { 3671eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson // Thumb2 mode: lsl 0-3 only. 3672eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson Latency -= 2; 3673eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson break; 3674eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson } 3675eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson } 36767e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng } 36777e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng 3678616471d4bfe4717fa86259ff4534703357b3b723Silviu Baranga if (DefAlign < 8 && Subtarget.isLikeA9()) 3679e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng switch (DefMCID.getOpcode()) { 368075b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng default: break; 368128f08c93e75d291695ea89b9004145103292e85bJim Grosbach case ARM::VLD1q8: 368228f08c93e75d291695ea89b9004145103292e85bJim Grosbach case ARM::VLD1q16: 368328f08c93e75d291695ea89b9004145103292e85bJim Grosbach case ARM::VLD1q32: 368428f08c93e75d291695ea89b9004145103292e85bJim Grosbach case ARM::VLD1q64: 368528f08c93e75d291695ea89b9004145103292e85bJim Grosbach case ARM::VLD1q8wb_register: 368628f08c93e75d291695ea89b9004145103292e85bJim Grosbach case ARM::VLD1q16wb_register: 368728f08c93e75d291695ea89b9004145103292e85bJim Grosbach case ARM::VLD1q32wb_register: 368828f08c93e75d291695ea89b9004145103292e85bJim Grosbach case ARM::VLD1q64wb_register: 368928f08c93e75d291695ea89b9004145103292e85bJim Grosbach case ARM::VLD1q8wb_fixed: 369028f08c93e75d291695ea89b9004145103292e85bJim Grosbach case ARM::VLD1q16wb_fixed: 369128f08c93e75d291695ea89b9004145103292e85bJim Grosbach case ARM::VLD1q32wb_fixed: 369228f08c93e75d291695ea89b9004145103292e85bJim Grosbach case ARM::VLD1q64wb_fixed: 369328f08c93e75d291695ea89b9004145103292e85bJim Grosbach case ARM::VLD2d8: 369428f08c93e75d291695ea89b9004145103292e85bJim Grosbach case ARM::VLD2d16: 369528f08c93e75d291695ea89b9004145103292e85bJim Grosbach case ARM::VLD2d32: 369675b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2q8Pseudo: 369775b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2q16Pseudo: 369875b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2q32Pseudo: 369928f08c93e75d291695ea89b9004145103292e85bJim Grosbach case ARM::VLD2d8wb_fixed: 370028f08c93e75d291695ea89b9004145103292e85bJim Grosbach case ARM::VLD2d16wb_fixed: 370128f08c93e75d291695ea89b9004145103292e85bJim Grosbach case ARM::VLD2d32wb_fixed: 3702a4e3c7fc4ba2d55695b0484480685698132eba20Jim Grosbach case ARM::VLD2q8PseudoWB_fixed: 3703a4e3c7fc4ba2d55695b0484480685698132eba20Jim Grosbach case ARM::VLD2q16PseudoWB_fixed: 3704a4e3c7fc4ba2d55695b0484480685698132eba20Jim Grosbach case ARM::VLD2q32PseudoWB_fixed: 370528f08c93e75d291695ea89b9004145103292e85bJim Grosbach case ARM::VLD2d8wb_register: 370628f08c93e75d291695ea89b9004145103292e85bJim Grosbach case ARM::VLD2d16wb_register: 370728f08c93e75d291695ea89b9004145103292e85bJim Grosbach case ARM::VLD2d32wb_register: 3708a4e3c7fc4ba2d55695b0484480685698132eba20Jim Grosbach case ARM::VLD2q8PseudoWB_register: 3709a4e3c7fc4ba2d55695b0484480685698132eba20Jim Grosbach case ARM::VLD2q16PseudoWB_register: 3710a4e3c7fc4ba2d55695b0484480685698132eba20Jim Grosbach case ARM::VLD2q32PseudoWB_register: 371175b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3d8Pseudo: 371275b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3d16Pseudo: 371375b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3d32Pseudo: 371475b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1d64TPseudo: 371536b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines case ARM::VLD1d64TPseudoWB_fixed: 371675b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3d8Pseudo_UPD: 371775b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3d16Pseudo_UPD: 371875b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3d32Pseudo_UPD: 371975b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3q8Pseudo_UPD: 372075b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3q16Pseudo_UPD: 372175b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3q32Pseudo_UPD: 372275b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3q8oddPseudo: 372375b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3q16oddPseudo: 372475b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3q32oddPseudo: 372575b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3q8oddPseudo_UPD: 372675b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3q16oddPseudo_UPD: 372775b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3q32oddPseudo_UPD: 372875b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4d8Pseudo: 372975b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4d16Pseudo: 373075b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4d32Pseudo: 373175b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1d64QPseudo: 373236b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines case ARM::VLD1d64QPseudoWB_fixed: 373375b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4d8Pseudo_UPD: 373475b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4d16Pseudo_UPD: 373575b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4d32Pseudo_UPD: 373675b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4q8Pseudo_UPD: 373775b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4q16Pseudo_UPD: 373875b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4q32Pseudo_UPD: 373975b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4q8oddPseudo: 374075b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4q16oddPseudo: 374175b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4q32oddPseudo: 374275b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4q8oddPseudo_UPD: 374375b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4q16oddPseudo_UPD: 374475b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4q32oddPseudo_UPD: 3745c0fc450f0754508871bc70f21e528bf2f1520da1Jim Grosbach case ARM::VLD1DUPq8: 3746c0fc450f0754508871bc70f21e528bf2f1520da1Jim Grosbach case ARM::VLD1DUPq16: 3747c0fc450f0754508871bc70f21e528bf2f1520da1Jim Grosbach case ARM::VLD1DUPq32: 3748c0fc450f0754508871bc70f21e528bf2f1520da1Jim Grosbach case ARM::VLD1DUPq8wb_fixed: 3749c0fc450f0754508871bc70f21e528bf2f1520da1Jim Grosbach case ARM::VLD1DUPq16wb_fixed: 3750c0fc450f0754508871bc70f21e528bf2f1520da1Jim Grosbach case ARM::VLD1DUPq32wb_fixed: 3751c0fc450f0754508871bc70f21e528bf2f1520da1Jim Grosbach case ARM::VLD1DUPq8wb_register: 3752c0fc450f0754508871bc70f21e528bf2f1520da1Jim Grosbach case ARM::VLD1DUPq16wb_register: 3753c0fc450f0754508871bc70f21e528bf2f1520da1Jim Grosbach case ARM::VLD1DUPq32wb_register: 3754c0fc450f0754508871bc70f21e528bf2f1520da1Jim Grosbach case ARM::VLD2DUPd8: 3755c0fc450f0754508871bc70f21e528bf2f1520da1Jim Grosbach case ARM::VLD2DUPd16: 3756c0fc450f0754508871bc70f21e528bf2f1520da1Jim Grosbach case ARM::VLD2DUPd32: 3757c0fc450f0754508871bc70f21e528bf2f1520da1Jim Grosbach case ARM::VLD2DUPd8wb_fixed: 3758c0fc450f0754508871bc70f21e528bf2f1520da1Jim Grosbach case ARM::VLD2DUPd16wb_fixed: 3759c0fc450f0754508871bc70f21e528bf2f1520da1Jim Grosbach case ARM::VLD2DUPd32wb_fixed: 3760c0fc450f0754508871bc70f21e528bf2f1520da1Jim Grosbach case ARM::VLD2DUPd8wb_register: 3761c0fc450f0754508871bc70f21e528bf2f1520da1Jim Grosbach case ARM::VLD2DUPd16wb_register: 3762c0fc450f0754508871bc70f21e528bf2f1520da1Jim Grosbach case ARM::VLD2DUPd32wb_register: 376375b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4DUPd8Pseudo: 376475b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4DUPd16Pseudo: 376575b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4DUPd32Pseudo: 376675b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4DUPd8Pseudo_UPD: 376775b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4DUPd16Pseudo_UPD: 376875b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4DUPd32Pseudo_UPD: 376975b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1LNq8Pseudo: 377075b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1LNq16Pseudo: 377175b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1LNq32Pseudo: 377275b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1LNq8Pseudo_UPD: 377375b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1LNq16Pseudo_UPD: 377475b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1LNq32Pseudo_UPD: 377575b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2LNd8Pseudo: 377675b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2LNd16Pseudo: 377775b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2LNd32Pseudo: 377875b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2LNq16Pseudo: 377975b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2LNq32Pseudo: 378075b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2LNd8Pseudo_UPD: 378175b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2LNd16Pseudo_UPD: 378275b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2LNd32Pseudo_UPD: 378375b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2LNq16Pseudo_UPD: 378475b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2LNq32Pseudo_UPD: 378575b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4LNd8Pseudo: 378675b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4LNd16Pseudo: 378775b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4LNd32Pseudo: 378875b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4LNq16Pseudo: 378975b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4LNq32Pseudo: 379075b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4LNd8Pseudo_UPD: 379175b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4LNd16Pseudo_UPD: 379275b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4LNd32Pseudo_UPD: 379375b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4LNq16Pseudo_UPD: 379475b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4LNq32Pseudo_UPD: 379575b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng // If the address is not 64-bit aligned, the latencies of these 379675b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng // instructions increases by one. 379775b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng ++Latency; 379875b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng break; 379975b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng } 380075b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng 38017e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng return Latency; 3802a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng} 38032312842de0c641107dd04d7e056d02491cc781caEvan Cheng 3804d42730dc712026cbfb1322a979e0ac72cd31a19eArnold Schwaighoferunsigned ARMBaseInstrInfo::getPredicationCost(const MachineInstr *MI) const { 3805d42730dc712026cbfb1322a979e0ac72cd31a19eArnold Schwaighofer if (MI->isCopyLike() || MI->isInsertSubreg() || 3806d42730dc712026cbfb1322a979e0ac72cd31a19eArnold Schwaighofer MI->isRegSequence() || MI->isImplicitDef()) 3807d42730dc712026cbfb1322a979e0ac72cd31a19eArnold Schwaighofer return 0; 3808d42730dc712026cbfb1322a979e0ac72cd31a19eArnold Schwaighofer 3809d42730dc712026cbfb1322a979e0ac72cd31a19eArnold Schwaighofer if (MI->isBundle()) 3810d42730dc712026cbfb1322a979e0ac72cd31a19eArnold Schwaighofer return 0; 3811d42730dc712026cbfb1322a979e0ac72cd31a19eArnold Schwaighofer 3812d42730dc712026cbfb1322a979e0ac72cd31a19eArnold Schwaighofer const MCInstrDesc &MCID = MI->getDesc(); 3813d42730dc712026cbfb1322a979e0ac72cd31a19eArnold Schwaighofer 3814d42730dc712026cbfb1322a979e0ac72cd31a19eArnold Schwaighofer if (MCID.isCall() || MCID.hasImplicitDefOfPhysReg(ARM::CPSR)) { 3815d42730dc712026cbfb1322a979e0ac72cd31a19eArnold Schwaighofer // When predicated, CPSR is an additional source operand for CPSR updating 3816d42730dc712026cbfb1322a979e0ac72cd31a19eArnold Schwaighofer // instructions, this apparently increases their latencies. 3817d42730dc712026cbfb1322a979e0ac72cd31a19eArnold Schwaighofer return 1; 3818d42730dc712026cbfb1322a979e0ac72cd31a19eArnold Schwaighofer } 3819d42730dc712026cbfb1322a979e0ac72cd31a19eArnold Schwaighofer return 0; 3820d42730dc712026cbfb1322a979e0ac72cd31a19eArnold Schwaighofer} 3821d42730dc712026cbfb1322a979e0ac72cd31a19eArnold Schwaighofer 3822b7e0289fb320c8440ba5eed121a8b932dbd806a2Andrew Trickunsigned ARMBaseInstrInfo::getInstrLatency(const InstrItineraryData *ItinData, 3823b7e0289fb320c8440ba5eed121a8b932dbd806a2Andrew Trick const MachineInstr *MI, 3824b7e0289fb320c8440ba5eed121a8b932dbd806a2Andrew Trick unsigned *PredCost) const { 38258239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng if (MI->isCopyLike() || MI->isInsertSubreg() || 38268239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng MI->isRegSequence() || MI->isImplicitDef()) 38278239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng return 1; 38288239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng 3829ed7a51e69209af87f3749d5f95740f69a1dc7711Andrew Trick // An instruction scheduler typically runs on unbundled instructions, however 3830ed7a51e69209af87f3749d5f95740f69a1dc7711Andrew Trick // other passes may query the latency of a bundled instruction. 3831ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng if (MI->isBundle()) { 3832ed7a51e69209af87f3749d5f95740f69a1dc7711Andrew Trick unsigned Latency = 0; 3833ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng MachineBasicBlock::const_instr_iterator I = MI; 3834ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end(); 3835ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng while (++I != E && I->isInsideBundle()) { 3836ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng if (I->getOpcode() != ARM::t2IT) 3837ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng Latency += getInstrLatency(ItinData, I, PredCost); 3838ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng } 3839ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng return Latency; 3840ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng } 3841ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng 3842e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng const MCInstrDesc &MCID = MI->getDesc(); 3843ed7a51e69209af87f3749d5f95740f69a1dc7711Andrew Trick if (PredCost && (MCID.isCall() || MCID.hasImplicitDefOfPhysReg(ARM::CPSR))) { 38448239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng // When predicated, CPSR is an additional source operand for CPSR updating 38458239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng // instructions, this apparently increases their latencies. 38468239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng *PredCost = 1; 3847ed7a51e69209af87f3749d5f95740f69a1dc7711Andrew Trick } 3848ed7a51e69209af87f3749d5f95740f69a1dc7711Andrew Trick // Be sure to call getStageLatency for an empty itinerary in case it has a 3849ed7a51e69209af87f3749d5f95740f69a1dc7711Andrew Trick // valid MinLatency property. 3850ed7a51e69209af87f3749d5f95740f69a1dc7711Andrew Trick if (!ItinData) 3851ed7a51e69209af87f3749d5f95740f69a1dc7711Andrew Trick return MI->mayLoad() ? 3 : 1; 3852ed7a51e69209af87f3749d5f95740f69a1dc7711Andrew Trick 3853ed7a51e69209af87f3749d5f95740f69a1dc7711Andrew Trick unsigned Class = MCID.getSchedClass(); 3854ed7a51e69209af87f3749d5f95740f69a1dc7711Andrew Trick 3855ed7a51e69209af87f3749d5f95740f69a1dc7711Andrew Trick // For instructions with variable uops, use uops as latency. 385614ccc7b963861a856b593cc4fff62decd8ce248aAndrew Trick if (!ItinData->isEmpty() && ItinData->getNumMicroOps(Class) < 0) 3857ed7a51e69209af87f3749d5f95740f69a1dc7711Andrew Trick return getNumMicroOps(ItinData, MI); 385814ccc7b963861a856b593cc4fff62decd8ce248aAndrew Trick 3859ed7a51e69209af87f3749d5f95740f69a1dc7711Andrew Trick // For the common case, fall back on the itinerary's latency. 386068b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick unsigned Latency = ItinData->getStageLatency(Class); 386168b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick 386268b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick // Adjust for dynamic def-side opcode variants not captured by the itinerary. 386368b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick unsigned DefAlign = MI->hasOneMemOperand() 386468b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick ? (*MI->memoperands_begin())->getAlignment() : 0; 386568b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick int Adj = adjustDefLatency(Subtarget, MI, &MCID, DefAlign); 386668b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick if (Adj >= 0 || (int)Latency > -Adj) { 386768b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick return Latency + Adj; 386868b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick } 386968b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick return Latency; 38708239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng} 38718239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng 38728239daf7c83a65a189c352cce3191cdc3bbfe151Evan Chengint ARMBaseInstrInfo::getInstrLatency(const InstrItineraryData *ItinData, 38738239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng SDNode *Node) const { 38748239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng if (!Node->isMachineOpcode()) 38758239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng return 1; 38768239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng 38778239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng if (!ItinData || ItinData->isEmpty()) 38788239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng return 1; 38798239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng 38808239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng unsigned Opcode = Node->getMachineOpcode(); 38818239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng switch (Opcode) { 38828239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng default: 38838239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng return ItinData->getStageLatency(get(Opcode).getSchedClass()); 388473fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMQIA: 388573fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMQIA: 38868239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng return 2; 38878b3ca6216d62bf3f729c2e122dcfeb7c4d7500dcEric Christopher } 38888239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng} 38898239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng 38902312842de0c641107dd04d7e056d02491cc781caEvan Chengbool ARMBaseInstrInfo:: 38912312842de0c641107dd04d7e056d02491cc781caEvan ChenghasHighOperandLatency(const InstrItineraryData *ItinData, 38922312842de0c641107dd04d7e056d02491cc781caEvan Cheng const MachineRegisterInfo *MRI, 38932312842de0c641107dd04d7e056d02491cc781caEvan Cheng const MachineInstr *DefMI, unsigned DefIdx, 38942312842de0c641107dd04d7e056d02491cc781caEvan Cheng const MachineInstr *UseMI, unsigned UseIdx) const { 38952312842de0c641107dd04d7e056d02491cc781caEvan Cheng unsigned DDomain = DefMI->getDesc().TSFlags & ARMII::DomainMask; 38962312842de0c641107dd04d7e056d02491cc781caEvan Cheng unsigned UDomain = UseMI->getDesc().TSFlags & ARMII::DomainMask; 38972312842de0c641107dd04d7e056d02491cc781caEvan Cheng if (Subtarget.isCortexA8() && 38982312842de0c641107dd04d7e056d02491cc781caEvan Cheng (DDomain == ARMII::DomainVFP || UDomain == ARMII::DomainVFP)) 38992312842de0c641107dd04d7e056d02491cc781caEvan Cheng // CortexA8 VFP instructions are not pipelined. 39002312842de0c641107dd04d7e056d02491cc781caEvan Cheng return true; 39012312842de0c641107dd04d7e056d02491cc781caEvan Cheng 39022312842de0c641107dd04d7e056d02491cc781caEvan Cheng // Hoist VFP / NEON instructions with 4 or higher latency. 3903b86a0cdb674549d8493043331cecd9cbf53b80daAndrew Trick int Latency = computeOperandLatency(ItinData, DefMI, DefIdx, UseMI, UseIdx); 3904f377071bf8393d35797107c753da3e84aea94ebeAndrew Trick if (Latency < 0) 3905f377071bf8393d35797107c753da3e84aea94ebeAndrew Trick Latency = getInstrLatency(ItinData, DefMI); 39062312842de0c641107dd04d7e056d02491cc781caEvan Cheng if (Latency <= 3) 39072312842de0c641107dd04d7e056d02491cc781caEvan Cheng return false; 39082312842de0c641107dd04d7e056d02491cc781caEvan Cheng return DDomain == ARMII::DomainVFP || DDomain == ARMII::DomainNEON || 39092312842de0c641107dd04d7e056d02491cc781caEvan Cheng UDomain == ARMII::DomainVFP || UDomain == ARMII::DomainNEON; 39102312842de0c641107dd04d7e056d02491cc781caEvan Cheng} 3911c8141dfc7f983cb04e65d8acd6bcbdc8e4b8a0aeEvan Cheng 3912c8141dfc7f983cb04e65d8acd6bcbdc8e4b8a0aeEvan Chengbool ARMBaseInstrInfo:: 3913c8141dfc7f983cb04e65d8acd6bcbdc8e4b8a0aeEvan ChenghasLowDefLatency(const InstrItineraryData *ItinData, 3914c8141dfc7f983cb04e65d8acd6bcbdc8e4b8a0aeEvan Cheng const MachineInstr *DefMI, unsigned DefIdx) const { 3915c8141dfc7f983cb04e65d8acd6bcbdc8e4b8a0aeEvan Cheng if (!ItinData || ItinData->isEmpty()) 3916c8141dfc7f983cb04e65d8acd6bcbdc8e4b8a0aeEvan Cheng return false; 3917c8141dfc7f983cb04e65d8acd6bcbdc8e4b8a0aeEvan Cheng 3918c8141dfc7f983cb04e65d8acd6bcbdc8e4b8a0aeEvan Cheng unsigned DDomain = DefMI->getDesc().TSFlags & ARMII::DomainMask; 3919c8141dfc7f983cb04e65d8acd6bcbdc8e4b8a0aeEvan Cheng if (DDomain == ARMII::DomainGeneral) { 3920c8141dfc7f983cb04e65d8acd6bcbdc8e4b8a0aeEvan Cheng unsigned DefClass = DefMI->getDesc().getSchedClass(); 3921c8141dfc7f983cb04e65d8acd6bcbdc8e4b8a0aeEvan Cheng int DefCycle = ItinData->getOperandCycle(DefClass, DefIdx); 3922c8141dfc7f983cb04e65d8acd6bcbdc8e4b8a0aeEvan Cheng return (DefCycle != -1 && DefCycle <= 2); 3923c8141dfc7f983cb04e65d8acd6bcbdc8e4b8a0aeEvan Cheng } 3924c8141dfc7f983cb04e65d8acd6bcbdc8e4b8a0aeEvan Cheng return false; 3925c8141dfc7f983cb04e65d8acd6bcbdc8e4b8a0aeEvan Cheng} 392648575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng 39273be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trickbool ARMBaseInstrInfo::verifyInstruction(const MachineInstr *MI, 39283be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick StringRef &ErrInfo) const { 39293be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick if (convertAddSubFlagsOpcode(MI->getOpcode())) { 39303be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick ErrInfo = "Pseudo flag setting opcodes only exist in Selection DAG"; 39313be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick return false; 39323be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick } 39333be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick return true; 39343be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick} 39353be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick 393648575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Chengbool 393748575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan ChengARMBaseInstrInfo::isFpMLxInstruction(unsigned Opcode, unsigned &MulOpc, 393848575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng unsigned &AddSubOpc, 393948575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng bool &NegAcc, bool &HasLane) const { 394048575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng DenseMap<unsigned, unsigned>::const_iterator I = MLxEntryMap.find(Opcode); 394148575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng if (I == MLxEntryMap.end()) 394248575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng return false; 394348575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng 394448575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng const ARM_MLxEntry &Entry = ARM_MLxTable[I->second]; 394548575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng MulOpc = Entry.MulOpc; 394648575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng AddSubOpc = Entry.AddSubOpc; 394748575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng NegAcc = Entry.NegAcc; 394848575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng HasLane = Entry.HasLane; 394948575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng return true; 395048575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng} 395113fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen 395213fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen//===----------------------------------------------------------------------===// 395313fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen// Execution domains. 395413fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen//===----------------------------------------------------------------------===// 395513fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen// 395613fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen// Some instructions go down the NEON pipeline, some go down the VFP pipeline, 395713fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen// and some can go down both. The vmov instructions go down the VFP pipeline, 395813fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen// but they can be changed to vorr equivalents that are executed by the NEON 395913fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen// pipeline. 396013fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen// 396113fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen// We use the following execution domain numbering: 396213fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen// 39638bb3d3cb30df06bdcb3ef5a208e3e59f4eeb4868Jakob Stoklund Olesenenum ARMExeDomain { 39648bb3d3cb30df06bdcb3ef5a208e3e59f4eeb4868Jakob Stoklund Olesen ExeGeneric = 0, 39658bb3d3cb30df06bdcb3ef5a208e3e59f4eeb4868Jakob Stoklund Olesen ExeVFP = 1, 39668bb3d3cb30df06bdcb3ef5a208e3e59f4eeb4868Jakob Stoklund Olesen ExeNEON = 2 39678bb3d3cb30df06bdcb3ef5a208e3e59f4eeb4868Jakob Stoklund Olesen}; 396813fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen// 396913fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen// Also see ARMInstrFormats.td and Domain* enums in ARMBaseInfo.h 397013fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen// 397113fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesenstd::pair<uint16_t, uint16_t> 397213fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund OlesenARMBaseInstrInfo::getExecutionDomain(const MachineInstr *MI) const { 39733c8ad92455ff06c8e69085702ef1f13944eab4ddTim Northover // VMOVD, VMOVRS and VMOVSR are VFP instructions, but can be changed to NEON 39743c8ad92455ff06c8e69085702ef1f13944eab4ddTim Northover // if they are not predicated. 397513fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen if (MI->getOpcode() == ARM::VMOVD && !isPredicated(MI)) 39768bb3d3cb30df06bdcb3ef5a208e3e59f4eeb4868Jakob Stoklund Olesen return std::make_pair(ExeVFP, (1<<ExeVFP) | (1<<ExeNEON)); 397713fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen 3978a210db781f17b5ab8e2b71d53276153a9d15eeadSilviu Baranga // CortexA9 is particularly picky about mixing the two and wants these 39793c8ad92455ff06c8e69085702ef1f13944eab4ddTim Northover // converted. 3980a210db781f17b5ab8e2b71d53276153a9d15eeadSilviu Baranga if (Subtarget.isCortexA9() && !isPredicated(MI) && 39813c8ad92455ff06c8e69085702ef1f13944eab4ddTim Northover (MI->getOpcode() == ARM::VMOVRS || 3982c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover MI->getOpcode() == ARM::VMOVSR || 3983c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover MI->getOpcode() == ARM::VMOVS)) 39843c8ad92455ff06c8e69085702ef1f13944eab4ddTim Northover return std::make_pair(ExeVFP, (1<<ExeVFP) | (1<<ExeNEON)); 39853c8ad92455ff06c8e69085702ef1f13944eab4ddTim Northover 398613fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen // No other instructions can be swizzled, so just determine their domain. 398713fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen unsigned Domain = MI->getDesc().TSFlags & ARMII::DomainMask; 398813fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen 398913fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen if (Domain & ARMII::DomainNEON) 39908bb3d3cb30df06bdcb3ef5a208e3e59f4eeb4868Jakob Stoklund Olesen return std::make_pair(ExeNEON, 0); 399113fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen 399213fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen // Certain instructions can go either way on Cortex-A8. 399313fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen // Treat them as NEON instructions. 399413fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen if ((Domain & ARMII::DomainNEONA8) && Subtarget.isCortexA8()) 39958bb3d3cb30df06bdcb3ef5a208e3e59f4eeb4868Jakob Stoklund Olesen return std::make_pair(ExeNEON, 0); 399613fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen 399713fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen if (Domain & ARMII::DomainVFP) 39988bb3d3cb30df06bdcb3ef5a208e3e59f4eeb4868Jakob Stoklund Olesen return std::make_pair(ExeVFP, 0); 399913fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen 40008bb3d3cb30df06bdcb3ef5a208e3e59f4eeb4868Jakob Stoklund Olesen return std::make_pair(ExeGeneric, 0); 400113fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen} 400213fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen 400320599ea4bced03634a54b52e98d261018366f279Tim Northoverstatic unsigned getCorrespondingDRegAndLane(const TargetRegisterInfo *TRI, 400420599ea4bced03634a54b52e98d261018366f279Tim Northover unsigned SReg, unsigned &Lane) { 400520599ea4bced03634a54b52e98d261018366f279Tim Northover unsigned DReg = TRI->getMatchingSuperReg(SReg, ARM::ssub_0, &ARM::DPRRegClass); 400620599ea4bced03634a54b52e98d261018366f279Tim Northover Lane = 0; 400720599ea4bced03634a54b52e98d261018366f279Tim Northover 400820599ea4bced03634a54b52e98d261018366f279Tim Northover if (DReg != ARM::NoRegister) 400920599ea4bced03634a54b52e98d261018366f279Tim Northover return DReg; 401020599ea4bced03634a54b52e98d261018366f279Tim Northover 401120599ea4bced03634a54b52e98d261018366f279Tim Northover Lane = 1; 401220599ea4bced03634a54b52e98d261018366f279Tim Northover DReg = TRI->getMatchingSuperReg(SReg, ARM::ssub_1, &ARM::DPRRegClass); 401320599ea4bced03634a54b52e98d261018366f279Tim Northover 401420599ea4bced03634a54b52e98d261018366f279Tim Northover assert(DReg && "S-register with no D super-register?"); 401520599ea4bced03634a54b52e98d261018366f279Tim Northover return DReg; 401620599ea4bced03634a54b52e98d261018366f279Tim Northover} 401720599ea4bced03634a54b52e98d261018366f279Tim Northover 40182d15d641aa8aa9e48c268170f1a9825bb9926fc7Andrew Trick/// getImplicitSPRUseForDPRUse - Given a use of a DPR register and lane, 401997ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy/// set ImplicitSReg to a register number that must be marked as implicit-use or 402097ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy/// zero if no register needs to be defined as implicit-use. 402197ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy/// 402297ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy/// If the function cannot determine if an SPR should be marked implicit use or 402397ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy/// not, it returns false. 402497ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy/// 402597ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy/// This function handles cases where an instruction is being modified from taking 40262d15d641aa8aa9e48c268170f1a9825bb9926fc7Andrew Trick/// an SPR to a DPR[Lane]. A use of the DPR is being added, which may conflict 402797ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy/// with an earlier def of an SPR corresponding to DPR[Lane^1] (i.e. the other 402897ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy/// lane of the DPR). 402997ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy/// 403097ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy/// If the other SPR is defined, an implicit-use of it should be added. Else, 403197ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy/// (including the case where the DPR itself is defined), it should not. 40322d15d641aa8aa9e48c268170f1a9825bb9926fc7Andrew Trick/// 403397ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloystatic bool getImplicitSPRUseForDPRUse(const TargetRegisterInfo *TRI, 403497ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy MachineInstr *MI, 403597ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy unsigned DReg, unsigned Lane, 403697ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy unsigned &ImplicitSReg) { 403797ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy // If the DPR is defined or used already, the other SPR lane will be chained 403897ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy // correctly, so there is nothing to be done. 403997ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy if (MI->definesRegister(DReg, TRI) || MI->readsRegister(DReg, TRI)) { 404097ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy ImplicitSReg = 0; 404197ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy return true; 404297ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy } 404397ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy 404497ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy // Otherwise we need to go searching to see if the SPR is set explicitly. 404597ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy ImplicitSReg = TRI->getSubReg(DReg, 404697ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy (Lane & 1) ? ARM::ssub_0 : ARM::ssub_1); 404797ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy MachineBasicBlock::LivenessQueryResult LQR = 404897ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy MI->getParent()->computeRegisterLiveness(TRI, ImplicitSReg, MI); 404997ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy 405097ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy if (LQR == MachineBasicBlock::LQR_Live) 405197ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy return true; 405297ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy else if (LQR == MachineBasicBlock::LQR_Unknown) 405397ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy return false; 405497ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy 405597ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy // If the register is known not to be live, there is no need to add an 405697ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy // implicit-use. 405797ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy ImplicitSReg = 0; 405897ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy return true; 405997ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy} 406020599ea4bced03634a54b52e98d261018366f279Tim Northover 406113fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesenvoid 406213fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund OlesenARMBaseInstrInfo::setExecutionDomain(MachineInstr *MI, unsigned Domain) const { 40633c8ad92455ff06c8e69085702ef1f13944eab4ddTim Northover unsigned DstReg, SrcReg, DReg; 40643c8ad92455ff06c8e69085702ef1f13944eab4ddTim Northover unsigned Lane; 406537a942cd52725b1d390989a8267a764b42fcb5d3Jakob Stoklund Olesen MachineInstrBuilder MIB(*MI->getParent()->getParent(), MI); 40663c8ad92455ff06c8e69085702ef1f13944eab4ddTim Northover const TargetRegisterInfo *TRI = &getRegisterInfo(); 40673c8ad92455ff06c8e69085702ef1f13944eab4ddTim Northover switch (MI->getOpcode()) { 40683c8ad92455ff06c8e69085702ef1f13944eab4ddTim Northover default: 40693c8ad92455ff06c8e69085702ef1f13944eab4ddTim Northover llvm_unreachable("cannot handle opcode!"); 40703c8ad92455ff06c8e69085702ef1f13944eab4ddTim Northover break; 40713c8ad92455ff06c8e69085702ef1f13944eab4ddTim Northover case ARM::VMOVD: 40723c8ad92455ff06c8e69085702ef1f13944eab4ddTim Northover if (Domain != ExeNEON) 40733c8ad92455ff06c8e69085702ef1f13944eab4ddTim Northover break; 40743c8ad92455ff06c8e69085702ef1f13944eab4ddTim Northover 40753c8ad92455ff06c8e69085702ef1f13944eab4ddTim Northover // Zap the predicate operands. 40763c8ad92455ff06c8e69085702ef1f13944eab4ddTim Northover assert(!isPredicated(MI) && "Cannot predicate a VORRd"); 40773c8ad92455ff06c8e69085702ef1f13944eab4ddTim Northover 407820599ea4bced03634a54b52e98d261018366f279Tim Northover // Source instruction is %DDst = VMOVD %DSrc, 14, %noreg (; implicits) 407920599ea4bced03634a54b52e98d261018366f279Tim Northover DstReg = MI->getOperand(0).getReg(); 408020599ea4bced03634a54b52e98d261018366f279Tim Northover SrcReg = MI->getOperand(1).getReg(); 40813c8ad92455ff06c8e69085702ef1f13944eab4ddTim Northover 408220599ea4bced03634a54b52e98d261018366f279Tim Northover for (unsigned i = MI->getDesc().getNumOperands(); i; --i) 408320599ea4bced03634a54b52e98d261018366f279Tim Northover MI->RemoveOperand(i-1); 408420599ea4bced03634a54b52e98d261018366f279Tim Northover 408520599ea4bced03634a54b52e98d261018366f279Tim Northover // Change to a %DDst = VORRd %DSrc, %DSrc, 14, %noreg (; implicits) 408620599ea4bced03634a54b52e98d261018366f279Tim Northover MI->setDesc(get(ARM::VORRd)); 408720599ea4bced03634a54b52e98d261018366f279Tim Northover AddDefaultPred(MIB.addReg(DstReg, RegState::Define) 408820599ea4bced03634a54b52e98d261018366f279Tim Northover .addReg(SrcReg) 408920599ea4bced03634a54b52e98d261018366f279Tim Northover .addReg(SrcReg)); 40903c8ad92455ff06c8e69085702ef1f13944eab4ddTim Northover break; 40913c8ad92455ff06c8e69085702ef1f13944eab4ddTim Northover case ARM::VMOVRS: 40923c8ad92455ff06c8e69085702ef1f13944eab4ddTim Northover if (Domain != ExeNEON) 40933c8ad92455ff06c8e69085702ef1f13944eab4ddTim Northover break; 40943c8ad92455ff06c8e69085702ef1f13944eab4ddTim Northover assert(!isPredicated(MI) && "Cannot predicate a VGETLN"); 40953c8ad92455ff06c8e69085702ef1f13944eab4ddTim Northover 409620599ea4bced03634a54b52e98d261018366f279Tim Northover // Source instruction is %RDst = VMOVRS %SSrc, 14, %noreg (; implicits) 40973c8ad92455ff06c8e69085702ef1f13944eab4ddTim Northover DstReg = MI->getOperand(0).getReg(); 40983c8ad92455ff06c8e69085702ef1f13944eab4ddTim Northover SrcReg = MI->getOperand(1).getReg(); 409913fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen 410020599ea4bced03634a54b52e98d261018366f279Tim Northover for (unsigned i = MI->getDesc().getNumOperands(); i; --i) 410120599ea4bced03634a54b52e98d261018366f279Tim Northover MI->RemoveOperand(i-1); 41023c8ad92455ff06c8e69085702ef1f13944eab4ddTim Northover 410320599ea4bced03634a54b52e98d261018366f279Tim Northover DReg = getCorrespondingDRegAndLane(TRI, SrcReg, Lane); 41043c8ad92455ff06c8e69085702ef1f13944eab4ddTim Northover 410520599ea4bced03634a54b52e98d261018366f279Tim Northover // Convert to %RDst = VGETLNi32 %DSrc, Lane, 14, %noreg (; imps) 410620599ea4bced03634a54b52e98d261018366f279Tim Northover // Note that DSrc has been widened and the other lane may be undef, which 410720599ea4bced03634a54b52e98d261018366f279Tim Northover // contaminates the entire register. 41083c8ad92455ff06c8e69085702ef1f13944eab4ddTim Northover MI->setDesc(get(ARM::VGETLNi32)); 410920599ea4bced03634a54b52e98d261018366f279Tim Northover AddDefaultPred(MIB.addReg(DstReg, RegState::Define) 411020599ea4bced03634a54b52e98d261018366f279Tim Northover .addReg(DReg, RegState::Undef) 411120599ea4bced03634a54b52e98d261018366f279Tim Northover .addImm(Lane)); 41123c8ad92455ff06c8e69085702ef1f13944eab4ddTim Northover 411320599ea4bced03634a54b52e98d261018366f279Tim Northover // The old source should be an implicit use, otherwise we might think it 411420599ea4bced03634a54b52e98d261018366f279Tim Northover // was dead before here. 41153c8ad92455ff06c8e69085702ef1f13944eab4ddTim Northover MIB.addReg(SrcReg, RegState::Implicit); 41163c8ad92455ff06c8e69085702ef1f13944eab4ddTim Northover break; 411797ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy case ARM::VMOVSR: { 41183c8ad92455ff06c8e69085702ef1f13944eab4ddTim Northover if (Domain != ExeNEON) 41193c8ad92455ff06c8e69085702ef1f13944eab4ddTim Northover break; 41203c8ad92455ff06c8e69085702ef1f13944eab4ddTim Northover assert(!isPredicated(MI) && "Cannot predicate a VSETLN"); 41213c8ad92455ff06c8e69085702ef1f13944eab4ddTim Northover 412220599ea4bced03634a54b52e98d261018366f279Tim Northover // Source instruction is %SDst = VMOVSR %RSrc, 14, %noreg (; implicits) 41233c8ad92455ff06c8e69085702ef1f13944eab4ddTim Northover DstReg = MI->getOperand(0).getReg(); 41243c8ad92455ff06c8e69085702ef1f13944eab4ddTim Northover SrcReg = MI->getOperand(1).getReg(); 41253c8ad92455ff06c8e69085702ef1f13944eab4ddTim Northover 412620599ea4bced03634a54b52e98d261018366f279Tim Northover DReg = getCorrespondingDRegAndLane(TRI, DstReg, Lane); 41273c8ad92455ff06c8e69085702ef1f13944eab4ddTim Northover 412897ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy unsigned ImplicitSReg; 412997ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy if (!getImplicitSPRUseForDPRUse(TRI, MI, DReg, Lane, ImplicitSReg)) 413097ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy break; 413189f49808ee79eebbc3267b6c595514d4ca1f3247Tim Northover 41327bebddf55ece46995f310d79195afb4e5b239886Tim Northover for (unsigned i = MI->getDesc().getNumOperands(); i; --i) 41337bebddf55ece46995f310d79195afb4e5b239886Tim Northover MI->RemoveOperand(i-1); 41347bebddf55ece46995f310d79195afb4e5b239886Tim Northover 413520599ea4bced03634a54b52e98d261018366f279Tim Northover // Convert to %DDst = VSETLNi32 %DDst, %RSrc, Lane, 14, %noreg (; imps) 413620599ea4bced03634a54b52e98d261018366f279Tim Northover // Again DDst may be undefined at the beginning of this instruction. 413720599ea4bced03634a54b52e98d261018366f279Tim Northover MI->setDesc(get(ARM::VSETLNi32)); 413889f49808ee79eebbc3267b6c595514d4ca1f3247Tim Northover MIB.addReg(DReg, RegState::Define) 413989f49808ee79eebbc3267b6c595514d4ca1f3247Tim Northover .addReg(DReg, getUndefRegState(!MI->readsRegister(DReg, TRI))) 414089f49808ee79eebbc3267b6c595514d4ca1f3247Tim Northover .addReg(SrcReg) 414189f49808ee79eebbc3267b6c595514d4ca1f3247Tim Northover .addImm(Lane); 414289f49808ee79eebbc3267b6c595514d4ca1f3247Tim Northover AddDefaultPred(MIB); 4143c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover 414489f49808ee79eebbc3267b6c595514d4ca1f3247Tim Northover // The narrower destination must be marked as set to keep previous chains 414589f49808ee79eebbc3267b6c595514d4ca1f3247Tim Northover // in place. 414620599ea4bced03634a54b52e98d261018366f279Tim Northover MIB.addReg(DstReg, RegState::Define | RegState::Implicit); 414797ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy if (ImplicitSReg != 0) 414897ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy MIB.addReg(ImplicitSReg, RegState::Implicit); 41493c8ad92455ff06c8e69085702ef1f13944eab4ddTim Northover break; 415097ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy } 4151c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover case ARM::VMOVS: { 4152c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover if (Domain != ExeNEON) 4153c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover break; 4154c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover 4155c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover // Source instruction is %SDst = VMOVS %SSrc, 14, %noreg (; implicits) 4156c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover DstReg = MI->getOperand(0).getReg(); 4157c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover SrcReg = MI->getOperand(1).getReg(); 4158c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover 4159c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover unsigned DstLane = 0, SrcLane = 0, DDst, DSrc; 4160c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover DDst = getCorrespondingDRegAndLane(TRI, DstReg, DstLane); 4161c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover DSrc = getCorrespondingDRegAndLane(TRI, SrcReg, SrcLane); 4162c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover 416397ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy unsigned ImplicitSReg; 416497ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy if (!getImplicitSPRUseForDPRUse(TRI, MI, DSrc, SrcLane, ImplicitSReg)) 416597ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy break; 416689f49808ee79eebbc3267b6c595514d4ca1f3247Tim Northover 41677bebddf55ece46995f310d79195afb4e5b239886Tim Northover for (unsigned i = MI->getDesc().getNumOperands(); i; --i) 41687bebddf55ece46995f310d79195afb4e5b239886Tim Northover MI->RemoveOperand(i-1); 41697bebddf55ece46995f310d79195afb4e5b239886Tim Northover 4170c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover if (DSrc == DDst) { 4171c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover // Destination can be: 4172c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover // %DDst = VDUPLN32d %DDst, Lane, 14, %noreg (; implicits) 4173c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover MI->setDesc(get(ARM::VDUPLN32d)); 417489f49808ee79eebbc3267b6c595514d4ca1f3247Tim Northover MIB.addReg(DDst, RegState::Define) 417589f49808ee79eebbc3267b6c595514d4ca1f3247Tim Northover .addReg(DDst, getUndefRegState(!MI->readsRegister(DDst, TRI))) 417689f49808ee79eebbc3267b6c595514d4ca1f3247Tim Northover .addImm(SrcLane); 417789f49808ee79eebbc3267b6c595514d4ca1f3247Tim Northover AddDefaultPred(MIB); 4178c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover 4179c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover // Neither the source or the destination are naturally represented any 4180c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover // more, so add them in manually. 4181c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover MIB.addReg(DstReg, RegState::Implicit | RegState::Define); 4182c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover MIB.addReg(SrcReg, RegState::Implicit); 418397ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy if (ImplicitSReg != 0) 418497ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy MIB.addReg(ImplicitSReg, RegState::Implicit); 4185c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover break; 4186c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover } 4187c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover 4188c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover // In general there's no single instruction that can perform an S <-> S 4189c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover // move in NEON space, but a pair of VEXT instructions *can* do the 4190c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover // job. It turns out that the VEXTs needed will only use DSrc once, with 4191c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover // the position based purely on the combination of lane-0 and lane-1 4192c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover // involved. For example 4193c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover // vmov s0, s2 -> vext.32 d0, d0, d1, #1 vext.32 d0, d0, d0, #1 4194c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover // vmov s1, s3 -> vext.32 d0, d1, d0, #1 vext.32 d0, d0, d0, #1 4195c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover // vmov s0, s3 -> vext.32 d0, d0, d0, #1 vext.32 d0, d1, d0, #1 4196c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover // vmov s1, s2 -> vext.32 d0, d0, d0, #1 vext.32 d0, d0, d1, #1 4197c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover // 4198c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover // Pattern of the MachineInstrs is: 4199c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover // %DDst = VEXTd32 %DSrc1, %DSrc2, Lane, 14, %noreg (;implicits) 4200c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover MachineInstrBuilder NewMIB; 4201c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover NewMIB = BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), 4202c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover get(ARM::VEXTd32), DDst); 420389f49808ee79eebbc3267b6c595514d4ca1f3247Tim Northover 420489f49808ee79eebbc3267b6c595514d4ca1f3247Tim Northover // On the first instruction, both DSrc and DDst may be <undef> if present. 420589f49808ee79eebbc3267b6c595514d4ca1f3247Tim Northover // Specifically when the original instruction didn't have them as an 420689f49808ee79eebbc3267b6c595514d4ca1f3247Tim Northover // <imp-use>. 420789f49808ee79eebbc3267b6c595514d4ca1f3247Tim Northover unsigned CurReg = SrcLane == 1 && DstLane == 1 ? DSrc : DDst; 420889f49808ee79eebbc3267b6c595514d4ca1f3247Tim Northover bool CurUndef = !MI->readsRegister(CurReg, TRI); 420989f49808ee79eebbc3267b6c595514d4ca1f3247Tim Northover NewMIB.addReg(CurReg, getUndefRegState(CurUndef)); 421089f49808ee79eebbc3267b6c595514d4ca1f3247Tim Northover 421189f49808ee79eebbc3267b6c595514d4ca1f3247Tim Northover CurReg = SrcLane == 0 && DstLane == 0 ? DSrc : DDst; 421289f49808ee79eebbc3267b6c595514d4ca1f3247Tim Northover CurUndef = !MI->readsRegister(CurReg, TRI); 421389f49808ee79eebbc3267b6c595514d4ca1f3247Tim Northover NewMIB.addReg(CurReg, getUndefRegState(CurUndef)); 421489f49808ee79eebbc3267b6c595514d4ca1f3247Tim Northover 4215c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover NewMIB.addImm(1); 4216c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover AddDefaultPred(NewMIB); 4217c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover 4218c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover if (SrcLane == DstLane) 4219c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover NewMIB.addReg(SrcReg, RegState::Implicit); 4220c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover 4221c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover MI->setDesc(get(ARM::VEXTd32)); 4222c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover MIB.addReg(DDst, RegState::Define); 422389f49808ee79eebbc3267b6c595514d4ca1f3247Tim Northover 422489f49808ee79eebbc3267b6c595514d4ca1f3247Tim Northover // On the second instruction, DDst has definitely been defined above, so 422589f49808ee79eebbc3267b6c595514d4ca1f3247Tim Northover // it is not <undef>. DSrc, if present, can be <undef> as above. 422689f49808ee79eebbc3267b6c595514d4ca1f3247Tim Northover CurReg = SrcLane == 1 && DstLane == 0 ? DSrc : DDst; 422789f49808ee79eebbc3267b6c595514d4ca1f3247Tim Northover CurUndef = CurReg == DSrc && !MI->readsRegister(CurReg, TRI); 422889f49808ee79eebbc3267b6c595514d4ca1f3247Tim Northover MIB.addReg(CurReg, getUndefRegState(CurUndef)); 422989f49808ee79eebbc3267b6c595514d4ca1f3247Tim Northover 423089f49808ee79eebbc3267b6c595514d4ca1f3247Tim Northover CurReg = SrcLane == 0 && DstLane == 1 ? DSrc : DDst; 423189f49808ee79eebbc3267b6c595514d4ca1f3247Tim Northover CurUndef = CurReg == DSrc && !MI->readsRegister(CurReg, TRI); 423289f49808ee79eebbc3267b6c595514d4ca1f3247Tim Northover MIB.addReg(CurReg, getUndefRegState(CurUndef)); 423389f49808ee79eebbc3267b6c595514d4ca1f3247Tim Northover 4234c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover MIB.addImm(1); 4235c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover AddDefaultPred(MIB); 4236c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover 4237c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover if (SrcLane != DstLane) 4238c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover MIB.addReg(SrcReg, RegState::Implicit); 4239c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover 4240c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover // As before, the original destination is no longer represented, add it 4241c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover // implicitly. 4242c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover MIB.addReg(DstReg, RegState::Define | RegState::Implicit); 424397ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy if (ImplicitSReg != 0) 424497ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy MIB.addReg(ImplicitSReg, RegState::Implicit); 4245c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover break; 4246c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover } 42473c8ad92455ff06c8e69085702ef1f13944eab4ddTim Northover } 42488bb3d3cb30df06bdcb3ef5a208e3e59f4eeb4868Jakob Stoklund Olesen 424913fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen} 4250c01810eeb7227010f73cb39e3c4fa0197a3c4ef0Jim Grosbach 4251eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson//===----------------------------------------------------------------------===// 4252eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson// Partial register updates 4253eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson//===----------------------------------------------------------------------===// 4254eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson// 4255eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson// Swift renames NEON registers with 64-bit granularity. That means any 4256eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson// instruction writing an S-reg implicitly reads the containing D-reg. The 4257eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson// problem is mostly avoided by translating f32 operations to v2f32 operations 4258eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson// on D-registers, but f32 loads are still a problem. 4259eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson// 4260eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson// These instructions can load an f32 into a NEON register: 4261eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson// 4262eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson// VLDRS - Only writes S, partial D update. 4263eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson// VLD1LNd32 - Writes all D-regs, explicit partial D update, 2 uops. 4264eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson// VLD1DUPd32 - Writes all D-regs, no partial reg update, 2 uops. 4265eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson// 4266eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson// FCONSTD can be used as a dependency-breaking instruction. 4267eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilsonunsigned ARMBaseInstrInfo:: 4268eb1641d54a7eda7717304bc4d55d059208d8ebedBob WilsongetPartialRegUpdateClearance(const MachineInstr *MI, 4269eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson unsigned OpNum, 4270eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson const TargetRegisterInfo *TRI) const { 4271a210db781f17b5ab8e2b71d53276153a9d15eeadSilviu Baranga if (!SwiftPartialUpdateClearance || 4272a210db781f17b5ab8e2b71d53276153a9d15eeadSilviu Baranga !(Subtarget.isSwift() || Subtarget.isCortexA15())) 4273eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson return 0; 4274eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson 4275eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson assert(TRI && "Need TRI instance"); 4276eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson 4277eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson const MachineOperand &MO = MI->getOperand(OpNum); 4278eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson if (MO.readsReg()) 4279eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson return 0; 4280eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson unsigned Reg = MO.getReg(); 4281eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson int UseOp = -1; 4282eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson 4283eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson switch(MI->getOpcode()) { 4284eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson // Normal instructions writing only an S-register. 4285eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::VLDRS: 4286eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::FCONSTS: 4287eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::VMOVSR: 4288eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::VMOVv8i8: 4289eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::VMOVv4i16: 4290eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::VMOVv2i32: 4291eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::VMOVv2f32: 4292eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::VMOVv1i64: 4293eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson UseOp = MI->findRegisterUseOperandIdx(Reg, false, TRI); 4294eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson break; 4295eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson 4296eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson // Explicitly reads the dependency. 4297eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::VLD1LNd32: 4298a210db781f17b5ab8e2b71d53276153a9d15eeadSilviu Baranga UseOp = 3; 4299eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson break; 4300eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson default: 4301eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson return 0; 4302eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson } 4303eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson 4304eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson // If this instruction actually reads a value from Reg, there is no unwanted 4305eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson // dependency. 4306eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson if (UseOp != -1 && MI->getOperand(UseOp).readsReg()) 4307eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson return 0; 4308eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson 4309eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson // We must be able to clobber the whole D-reg. 4310eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson if (TargetRegisterInfo::isVirtualRegister(Reg)) { 4311eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson // Virtual register must be a foo:ssub_0<def,undef> operand. 4312eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson if (!MO.getSubReg() || MI->readsVirtualRegister(Reg)) 4313eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson return 0; 4314eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson } else if (ARM::SPRRegClass.contains(Reg)) { 4315eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson // Physical register: MI must define the full D-reg. 4316eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson unsigned DReg = TRI->getMatchingSuperReg(Reg, ARM::ssub_0, 4317eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson &ARM::DPRRegClass); 4318eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson if (!DReg || !MI->definesRegister(DReg, TRI)) 4319eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson return 0; 4320eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson } 4321eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson 4322eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson // MI has an unwanted D-register dependency. 4323eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson // Avoid defs in the previous N instructrions. 4324eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson return SwiftPartialUpdateClearance; 4325eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson} 4326eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson 4327eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson// Break a partial register dependency after getPartialRegUpdateClearance 4328eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson// returned non-zero. 4329eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilsonvoid ARMBaseInstrInfo:: 4330eb1641d54a7eda7717304bc4d55d059208d8ebedBob WilsonbreakPartialRegDependency(MachineBasicBlock::iterator MI, 4331eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson unsigned OpNum, 4332eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson const TargetRegisterInfo *TRI) const { 4333eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson assert(MI && OpNum < MI->getDesc().getNumDefs() && "OpNum is not a def"); 4334eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson assert(TRI && "Need TRI instance"); 4335eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson 4336eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson const MachineOperand &MO = MI->getOperand(OpNum); 4337eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson unsigned Reg = MO.getReg(); 4338eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson assert(TargetRegisterInfo::isPhysicalRegister(Reg) && 4339eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson "Can't break virtual register dependencies."); 4340eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson unsigned DReg = Reg; 4341eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson 4342eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson // If MI defines an S-reg, find the corresponding D super-register. 4343eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson if (ARM::SPRRegClass.contains(Reg)) { 4344eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson DReg = ARM::D0 + (Reg - ARM::S0) / 2; 4345eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson assert(TRI->isSuperRegister(Reg, DReg) && "Register enums broken"); 4346eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson } 4347eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson 4348eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson assert(ARM::DPRRegClass.contains(DReg) && "Can only break D-reg deps"); 4349eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson assert(MI->definesRegister(DReg, TRI) && "MI doesn't clobber full D-reg"); 4350eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson 4351eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson // FIXME: In some cases, VLDRS can be changed to a VLD1DUPd32 which defines 4352eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson // the full D-register by loading the same value to both lanes. The 4353eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson // instruction is micro-coded with 2 uops, so don't do this until we can 4354d9d6e6d59159160299a51fe5010a940db27ae89bRobert Wilhelm // properly schedule micro-coded instructions. The dispatcher stalls cause 4355eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson // too big regressions. 4356eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson 4357eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson // Insert the dependency-breaking FCONSTD before MI. 4358eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson // 96 is the encoding of 0.5, but the actual value doesn't matter here. 4359eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson AddDefaultPred(BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), 4360eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson get(ARM::FCONSTD), DReg).addImm(96)); 4361eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson MI->addRegisterKilled(DReg, TRI, true); 4362eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson} 4363eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson 4364cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen Hinesvoid ARMBaseInstrInfo::getUnconditionalBranch( 4365cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen Hines MCInst &Branch, const MCSymbolRefExpr *BranchTarget) const { 4366cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen Hines if (Subtarget.isThumb()) 4367cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen Hines Branch.setOpcode(ARM::tB); 4368cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen Hines else if (Subtarget.isThumb2()) 4369cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen Hines Branch.setOpcode(ARM::t2B); 4370cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen Hines else 4371cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen Hines Branch.setOpcode(ARM::Bcc); 4372cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen Hines 4373cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen Hines Branch.addOperand(MCOperand::CreateExpr(BranchTarget)); 4374cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen Hines Branch.addOperand(MCOperand::CreateImm(ARMCC::AL)); 4375cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen Hines Branch.addOperand(MCOperand::CreateReg(0)); 4376cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen Hines} 4377cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen Hines 4378cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen Hinesvoid ARMBaseInstrInfo::getTrap(MCInst &MI) const { 4379cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen Hines if (Subtarget.isThumb()) 4380cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen Hines MI.setOpcode(ARM::tTRAP); 4381cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen Hines else if (Subtarget.useNaClTrap()) 4382cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen Hines MI.setOpcode(ARM::TRAPNaCl); 4383cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen Hines else 4384cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen Hines MI.setOpcode(ARM::TRAP); 4385cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen Hines} 4386cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen Hines 4387c01810eeb7227010f73cb39e3c4fa0197a3c4ef0Jim Grosbachbool ARMBaseInstrInfo::hasNOP() const { 4388c01810eeb7227010f73cb39e3c4fa0197a3c4ef0Jim Grosbach return (Subtarget.getFeatureBits() & ARM::HasV6T2Ops) != 0; 4389c01810eeb7227010f73cb39e3c4fa0197a3c4ef0Jim Grosbach} 439008da4865576056f997a9c8013240d716018f7edfArnold Schwaighofer 439108da4865576056f997a9c8013240d716018f7edfArnold Schwaighoferbool ARMBaseInstrInfo::isSwiftFastImmShift(const MachineInstr *MI) const { 4392d87bd5627e5b78cb556d6c7b5aa76ae3d55d8acfArnold Schwaighofer if (MI->getNumOperands() < 4) 4393d87bd5627e5b78cb556d6c7b5aa76ae3d55d8acfArnold Schwaighofer return true; 439408da4865576056f997a9c8013240d716018f7edfArnold Schwaighofer unsigned ShOpVal = MI->getOperand(3).getImm(); 439508da4865576056f997a9c8013240d716018f7edfArnold Schwaighofer unsigned ShImm = ARM_AM::getSORegOffset(ShOpVal); 439608da4865576056f997a9c8013240d716018f7edfArnold Schwaighofer // Swift supports faster shifts for: lsl 2, lsl 1, and lsr 1. 439708da4865576056f997a9c8013240d716018f7edfArnold Schwaighofer if ((ShImm == 1 && ARM_AM::getSORegShOp(ShOpVal) == ARM_AM::lsr) || 439808da4865576056f997a9c8013240d716018f7edfArnold Schwaighofer ((ShImm == 1 || ShImm == 2) && 439908da4865576056f997a9c8013240d716018f7edfArnold Schwaighofer ARM_AM::getSORegShOp(ShOpVal) == ARM_AM::lsl)) 440008da4865576056f997a9c8013240d716018f7edfArnold Schwaighofer return true; 440108da4865576056f997a9c8013240d716018f7edfArnold Schwaighofer 440208da4865576056f997a9c8013240d716018f7edfArnold Schwaighofer return false; 440308da4865576056f997a9c8013240d716018f7edfArnold Schwaighofer} 4404