ARMBaseInstrInfo.cpp revision 05642a3eba3f35aa8fdf6aa16d87561560e60af3
131c24bf5b39cc8391d4cfdbf8cf5163975fdb81eJim Grosbach//===- ARMBaseInstrInfo.cpp - ARM Instruction Information -------*- C++ -*-===// 2334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// 3334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// The LLVM Compiler Infrastructure 4334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// 5334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// This file is distributed under the University of Illinois Open Source 6334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// License. See LICENSE.TXT for details. 7334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// 8334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin//===----------------------------------------------------------------------===// 9334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// 10334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// This file contains the Base ARM implementation of the TargetInstrInfo class. 11334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// 12334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin//===----------------------------------------------------------------------===// 13334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 14334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "ARMBaseInstrInfo.h" 15334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "ARM.h" 16334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "ARMAddressingModes.h" 17d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng#include "ARMConstantPoolValue.h" 18334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "ARMMachineFunctionInfo.h" 19f95215f551949d5e5adfbf4753aa833b9009b77aAnton Korobeynikov#include "ARMRegisterInfo.h" 204dbbe3433f7339ed277af55037ff6847f484e5abChris Lattner#include "ARMGenInstrInfo.inc" 21fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng#include "llvm/Constants.h" 22fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng#include "llvm/Function.h" 23fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng#include "llvm/GlobalValue.h" 24334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "llvm/ADT/STLExtras.h" 25334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "llvm/CodeGen/LiveVariables.h" 26d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng#include "llvm/CodeGen/MachineConstantPool.h" 27334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "llvm/CodeGen/MachineFrameInfo.h" 28334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "llvm/CodeGen/MachineInstrBuilder.h" 29334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "llvm/CodeGen/MachineJumpTableInfo.h" 30249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov#include "llvm/CodeGen/MachineMemOperand.h" 312457f2c66184e978d4ed8fa9e2128effff26cb0bEvan Cheng#include "llvm/CodeGen/MachineRegisterInfo.h" 32249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov#include "llvm/CodeGen/PseudoSourceValue.h" 33af76e592c7f9deff0e55c13dbb4a34f07f1c7f64Chris Lattner#include "llvm/MC/MCAsmInfo.h" 34334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "llvm/Support/CommandLine.h" 35f95215f551949d5e5adfbf4753aa833b9009b77aAnton Korobeynikov#include "llvm/Support/Debug.h" 36c25e7581b9b8088910da31702d4ca21c4734c6d7Torok Edwin#include "llvm/Support/ErrorHandling.h" 37334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinusing namespace llvm; 38334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 39334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinstatic cl::opt<bool> 40334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinEnableARM3Addr("enable-arm-3-addr-conv", cl::Hidden, 41334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin cl::desc("Enable ARM 2-addr to 3-addr conv")); 42334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 43f95215f551949d5e5adfbf4753aa833b9009b77aAnton KorobeynikovARMBaseInstrInfo::ARMBaseInstrInfo(const ARMSubtarget& STI) 44f95215f551949d5e5adfbf4753aa833b9009b77aAnton Korobeynikov : TargetInstrInfoImpl(ARMInsts, array_lengthof(ARMInsts)), 45f95215f551949d5e5adfbf4753aa833b9009b77aAnton Korobeynikov Subtarget(STI) { 46334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 47334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 48334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinMachineInstr * 49334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinARMBaseInstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI, 50334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineBasicBlock::iterator &MBBI, 51334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin LiveVariables *LV) const { 5278703ddafe3d037f75d8ca188e4829d238289ac3Evan Cheng // FIXME: Thumb2 support. 5378703ddafe3d037f75d8ca188e4829d238289ac3Evan Cheng 54334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (!EnableARM3Addr) 55334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return NULL; 56334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 57334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineInstr *MI = MBBI; 58334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineFunction &MF = *MI->getParent()->getParent(); 5999405df044f2c584242e711cc9023ec90356da82Bruno Cardoso Lopes uint64_t TSFlags = MI->getDesc().TSFlags; 60334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool isPre = false; 61334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin switch ((TSFlags & ARMII::IndexModeMask) >> ARMII::IndexModeShift) { 62334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin default: return NULL; 63334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMII::IndexModePre: 64334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin isPre = true; 65334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin break; 66334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMII::IndexModePost: 67334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin break; 68334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 69334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 70334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Try splitting an indexed load/store to an un-indexed one plus an add/sub 71334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // operation. 72334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned MemOpc = getUnindexedOpcode(MI->getOpcode()); 73334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (MemOpc == 0) 74334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return NULL; 75334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 76334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineInstr *UpdateMI = NULL; 77334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineInstr *MemMI = NULL; 78334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned AddrMode = (TSFlags & ARMII::AddrModeMask); 79334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const TargetInstrDesc &TID = MI->getDesc(); 80334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned NumOps = TID.getNumOperands(); 81334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool isLoad = !TID.mayStore(); 82334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const MachineOperand &WB = isLoad ? MI->getOperand(1) : MI->getOperand(0); 83334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const MachineOperand &Base = MI->getOperand(2); 84334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const MachineOperand &Offset = MI->getOperand(NumOps-3); 85334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned WBReg = WB.getReg(); 86334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned BaseReg = Base.getReg(); 87334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned OffReg = Offset.getReg(); 88334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned OffImm = MI->getOperand(NumOps-2).getImm(); 89334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin ARMCC::CondCodes Pred = (ARMCC::CondCodes)MI->getOperand(NumOps-1).getImm(); 90334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin switch (AddrMode) { 91334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin default: 92334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin assert(false && "Unknown indexed op!"); 93334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return NULL; 94334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMII::AddrMode2: { 95334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool isSub = ARM_AM::getAM2Op(OffImm) == ARM_AM::sub; 96334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned Amt = ARM_AM::getAM2Offset(OffImm); 97334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (OffReg == 0) { 98e7cbe4118b7ddf05032ff8772a98c51e1637bb5cEvan Cheng if (ARM_AM::getSOImmVal(Amt) == -1) 99334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Can't encode it in a so_imm operand. This transformation will 100334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // add more than 1 instruction. Abandon! 101334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return NULL; 102334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin UpdateMI = BuildMI(MF, MI->getDebugLoc(), 10378703ddafe3d037f75d8ca188e4829d238289ac3Evan Cheng get(isSub ? ARM::SUBri : ARM::ADDri), WBReg) 104e7cbe4118b7ddf05032ff8772a98c51e1637bb5cEvan Cheng .addReg(BaseReg).addImm(Amt) 105334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addImm(Pred).addReg(0).addReg(0); 106334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } else if (Amt != 0) { 107334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin ARM_AM::ShiftOpc ShOpc = ARM_AM::getAM2ShiftOpc(OffImm); 108334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned SOOpc = ARM_AM::getSORegOpc(ShOpc, Amt); 109334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin UpdateMI = BuildMI(MF, MI->getDebugLoc(), 11078703ddafe3d037f75d8ca188e4829d238289ac3Evan Cheng get(isSub ? ARM::SUBrs : ARM::ADDrs), WBReg) 111334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(BaseReg).addReg(OffReg).addReg(0).addImm(SOOpc) 112334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addImm(Pred).addReg(0).addReg(0); 113334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } else 114334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin UpdateMI = BuildMI(MF, MI->getDebugLoc(), 11578703ddafe3d037f75d8ca188e4829d238289ac3Evan Cheng get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg) 116334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(BaseReg).addReg(OffReg) 117334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addImm(Pred).addReg(0).addReg(0); 118334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin break; 119334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 120334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMII::AddrMode3 : { 121334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool isSub = ARM_AM::getAM3Op(OffImm) == ARM_AM::sub; 122334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned Amt = ARM_AM::getAM3Offset(OffImm); 123334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (OffReg == 0) 124334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Immediate is 8-bits. It's guaranteed to fit in a so_imm operand. 125334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin UpdateMI = BuildMI(MF, MI->getDebugLoc(), 12678703ddafe3d037f75d8ca188e4829d238289ac3Evan Cheng get(isSub ? ARM::SUBri : ARM::ADDri), WBReg) 127334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(BaseReg).addImm(Amt) 128334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addImm(Pred).addReg(0).addReg(0); 129334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin else 130334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin UpdateMI = BuildMI(MF, MI->getDebugLoc(), 13178703ddafe3d037f75d8ca188e4829d238289ac3Evan Cheng get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg) 132334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(BaseReg).addReg(OffReg) 133334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addImm(Pred).addReg(0).addReg(0); 134334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin break; 135334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 136334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 137334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 138334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin std::vector<MachineInstr*> NewMIs; 139334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (isPre) { 140334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (isLoad) 141334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MemMI = BuildMI(MF, MI->getDebugLoc(), 142334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin get(MemOpc), MI->getOperand(0).getReg()) 143334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(WBReg).addReg(0).addImm(0).addImm(Pred); 144334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin else 145334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MemMI = BuildMI(MF, MI->getDebugLoc(), 146334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin get(MemOpc)).addReg(MI->getOperand(1).getReg()) 147334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(WBReg).addReg(0).addImm(0).addImm(Pred); 148334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin NewMIs.push_back(MemMI); 149334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin NewMIs.push_back(UpdateMI); 150334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } else { 151334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (isLoad) 152334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MemMI = BuildMI(MF, MI->getDebugLoc(), 153334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin get(MemOpc), MI->getOperand(0).getReg()) 154334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred); 155334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin else 156334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MemMI = BuildMI(MF, MI->getDebugLoc(), 157334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin get(MemOpc)).addReg(MI->getOperand(1).getReg()) 158334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred); 159334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (WB.isDead()) 160334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin UpdateMI->getOperand(0).setIsDead(); 161334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin NewMIs.push_back(UpdateMI); 162334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin NewMIs.push_back(MemMI); 163334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 164334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 165334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Transfer LiveVariables states, kill / dead info. 166334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (LV) { 167334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 168334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineOperand &MO = MI->getOperand(i); 169334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (MO.isReg() && MO.getReg() && 170334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin TargetRegisterInfo::isVirtualRegister(MO.getReg())) { 171334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned Reg = MO.getReg(); 172334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 173334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin LiveVariables::VarInfo &VI = LV->getVarInfo(Reg); 174334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (MO.isDef()) { 175334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineInstr *NewMI = (Reg == WBReg) ? UpdateMI : MemMI; 176334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (MO.isDead()) 177334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin LV->addVirtualRegisterDead(Reg, NewMI); 178334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 179334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (MO.isUse() && MO.isKill()) { 180334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin for (unsigned j = 0; j < 2; ++j) { 181334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Look at the two new MI's in reverse order. 182334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineInstr *NewMI = NewMIs[j]; 183334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (!NewMI->readsRegister(Reg)) 184334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin continue; 185334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin LV->addVirtualRegisterKilled(Reg, NewMI); 186334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (VI.removeKill(MI)) 187334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin VI.Kills.push_back(NewMI); 188334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin break; 189334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 190334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 191334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 192334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 193334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 194334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 195334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MFI->insert(MBBI, NewMIs[1]); 196334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MFI->insert(MBBI, NewMIs[0]); 197334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return NewMIs[0]; 198334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 199334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 2002457f2c66184e978d4ed8fa9e2128effff26cb0bEvan Chengbool 2012457f2c66184e978d4ed8fa9e2128effff26cb0bEvan ChengARMBaseInstrInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB, 20218f30e6f5e80787808fe1455742452a5210afe07Jim Grosbach MachineBasicBlock::iterator MI, 20318f30e6f5e80787808fe1455742452a5210afe07Jim Grosbach const std::vector<CalleeSavedInfo> &CSI, 20418f30e6f5e80787808fe1455742452a5210afe07Jim Grosbach const TargetRegisterInfo *TRI) const { 2052457f2c66184e978d4ed8fa9e2128effff26cb0bEvan Cheng if (CSI.empty()) 2062457f2c66184e978d4ed8fa9e2128effff26cb0bEvan Cheng return false; 2072457f2c66184e978d4ed8fa9e2128effff26cb0bEvan Cheng 2082457f2c66184e978d4ed8fa9e2128effff26cb0bEvan Cheng DebugLoc DL; 2092457f2c66184e978d4ed8fa9e2128effff26cb0bEvan Cheng if (MI != MBB.end()) DL = MI->getDebugLoc(); 2102457f2c66184e978d4ed8fa9e2128effff26cb0bEvan Cheng 2112457f2c66184e978d4ed8fa9e2128effff26cb0bEvan Cheng for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 2122457f2c66184e978d4ed8fa9e2128effff26cb0bEvan Cheng unsigned Reg = CSI[i].getReg(); 2132457f2c66184e978d4ed8fa9e2128effff26cb0bEvan Cheng bool isKill = true; 2142457f2c66184e978d4ed8fa9e2128effff26cb0bEvan Cheng 2152457f2c66184e978d4ed8fa9e2128effff26cb0bEvan Cheng // Add the callee-saved register as live-in unless it's LR and 2162457f2c66184e978d4ed8fa9e2128effff26cb0bEvan Cheng // @llvm.returnaddress is called. If LR is returned for @llvm.returnaddress 2172457f2c66184e978d4ed8fa9e2128effff26cb0bEvan Cheng // then it's already added to the function and entry block live-in sets. 2182457f2c66184e978d4ed8fa9e2128effff26cb0bEvan Cheng if (Reg == ARM::LR) { 2192457f2c66184e978d4ed8fa9e2128effff26cb0bEvan Cheng MachineFunction &MF = *MBB.getParent(); 2202457f2c66184e978d4ed8fa9e2128effff26cb0bEvan Cheng if (MF.getFrameInfo()->isReturnAddressTaken() && 2212457f2c66184e978d4ed8fa9e2128effff26cb0bEvan Cheng MF.getRegInfo().isLiveIn(Reg)) 2222457f2c66184e978d4ed8fa9e2128effff26cb0bEvan Cheng isKill = false; 2232457f2c66184e978d4ed8fa9e2128effff26cb0bEvan Cheng } 2242457f2c66184e978d4ed8fa9e2128effff26cb0bEvan Cheng 2252457f2c66184e978d4ed8fa9e2128effff26cb0bEvan Cheng if (isKill) 2262457f2c66184e978d4ed8fa9e2128effff26cb0bEvan Cheng MBB.addLiveIn(Reg); 2272457f2c66184e978d4ed8fa9e2128effff26cb0bEvan Cheng 2282457f2c66184e978d4ed8fa9e2128effff26cb0bEvan Cheng // Insert the spill to the stack frame. The register is killed at the spill 2292457f2c66184e978d4ed8fa9e2128effff26cb0bEvan Cheng // 23042d075c4fb21995265961501cec9ff6e3fb497ceRafael Espindola const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); 2312457f2c66184e978d4ed8fa9e2128effff26cb0bEvan Cheng storeRegToStackSlot(MBB, MI, Reg, isKill, 23242d075c4fb21995265961501cec9ff6e3fb497ceRafael Espindola CSI[i].getFrameIdx(), RC, TRI); 2332457f2c66184e978d4ed8fa9e2128effff26cb0bEvan Cheng } 2342457f2c66184e978d4ed8fa9e2128effff26cb0bEvan Cheng return true; 2352457f2c66184e978d4ed8fa9e2128effff26cb0bEvan Cheng} 2362457f2c66184e978d4ed8fa9e2128effff26cb0bEvan Cheng 237334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// Branch analysis. 238334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinbool 239334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinARMBaseInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB, 240334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineBasicBlock *&FBB, 241334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin SmallVectorImpl<MachineOperand> &Cond, 242334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool AllowModify) const { 243334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // If the block has no terminators, it just falls into the block after it. 244334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineBasicBlock::iterator I = MBB.end(); 24593d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen if (I == MBB.begin()) 24693d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen return false; 24793d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen --I; 24893d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen while (I->isDebugValue()) { 24993d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen if (I == MBB.begin()) 25093d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen return false; 25193d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen --I; 25293d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen } 25393d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen if (!isUnpredicatedTerminator(I)) 254334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 255334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 256334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Get the last instruction in the block. 257334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineInstr *LastInst = I; 258334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 259334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // If there is only one terminator instruction, process it. 260334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned LastOpc = LastInst->getOpcode(); 261334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) { 2625ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng if (isUncondBranchOpcode(LastOpc)) { 263334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin TBB = LastInst->getOperand(0).getMBB(); 264334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 265334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 2665ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng if (isCondBranchOpcode(LastOpc)) { 267334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Block ends with fall-through condbranch. 268334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin TBB = LastInst->getOperand(0).getMBB(); 269334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin Cond.push_back(LastInst->getOperand(1)); 270334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin Cond.push_back(LastInst->getOperand(2)); 271334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 272334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 273334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; // Can't handle indirect branch. 274334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 275334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 276334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Get the instruction before it if it is a terminator. 277334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineInstr *SecondLastInst = I; 278108c8724663354050dc09bb1262c3e4511adf82fEvan Cheng unsigned SecondLastOpc = SecondLastInst->getOpcode(); 279108c8724663354050dc09bb1262c3e4511adf82fEvan Cheng 280108c8724663354050dc09bb1262c3e4511adf82fEvan Cheng // If AllowModify is true and the block ends with two or more unconditional 281108c8724663354050dc09bb1262c3e4511adf82fEvan Cheng // branches, delete all but the first unconditional branch. 282108c8724663354050dc09bb1262c3e4511adf82fEvan Cheng if (AllowModify && isUncondBranchOpcode(LastOpc)) { 283108c8724663354050dc09bb1262c3e4511adf82fEvan Cheng while (isUncondBranchOpcode(SecondLastOpc)) { 284108c8724663354050dc09bb1262c3e4511adf82fEvan Cheng LastInst->eraseFromParent(); 285108c8724663354050dc09bb1262c3e4511adf82fEvan Cheng LastInst = SecondLastInst; 286108c8724663354050dc09bb1262c3e4511adf82fEvan Cheng LastOpc = LastInst->getOpcode(); 287676e258366dd17a0b4ee6ac66914237ce181202eEvan Cheng if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) { 288676e258366dd17a0b4ee6ac66914237ce181202eEvan Cheng // Return now the only terminator is an unconditional branch. 289676e258366dd17a0b4ee6ac66914237ce181202eEvan Cheng TBB = LastInst->getOperand(0).getMBB(); 290676e258366dd17a0b4ee6ac66914237ce181202eEvan Cheng return false; 291676e258366dd17a0b4ee6ac66914237ce181202eEvan Cheng } else { 292108c8724663354050dc09bb1262c3e4511adf82fEvan Cheng SecondLastInst = I; 293108c8724663354050dc09bb1262c3e4511adf82fEvan Cheng SecondLastOpc = SecondLastInst->getOpcode(); 294108c8724663354050dc09bb1262c3e4511adf82fEvan Cheng } 295108c8724663354050dc09bb1262c3e4511adf82fEvan Cheng } 296108c8724663354050dc09bb1262c3e4511adf82fEvan Cheng } 297334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 298334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // If there are three terminators, we don't know what sort of block this is. 299334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(--I)) 300334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; 301334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 3025ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng // If the block ends with a B and a Bcc, handle it. 3035ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng if (isCondBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) { 304334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin TBB = SecondLastInst->getOperand(0).getMBB(); 305334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin Cond.push_back(SecondLastInst->getOperand(1)); 306334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin Cond.push_back(SecondLastInst->getOperand(2)); 307334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin FBB = LastInst->getOperand(0).getMBB(); 308334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 309334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 310334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 311334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // If the block ends with two unconditional branches, handle it. The second 312334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // one is not executed, so remove it. 3135ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng if (isUncondBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) { 314334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin TBB = SecondLastInst->getOperand(0).getMBB(); 315334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin I = LastInst; 316334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (AllowModify) 317334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin I->eraseFromParent(); 318334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 319334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 320334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 321334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // ...likewise if it ends with a branch table followed by an unconditional 322334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // branch. The branch folder can create these, and we must get rid of them for 323334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // correctness of Thumb constant islands. 3248d4de5abfa1bcd974554ea14904ebf7af289e84dBob Wilson if ((isJumpTableBranchOpcode(SecondLastOpc) || 3258d4de5abfa1bcd974554ea14904ebf7af289e84dBob Wilson isIndirectBranchOpcode(SecondLastOpc)) && 3265ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng isUncondBranchOpcode(LastOpc)) { 327334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin I = LastInst; 328334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (AllowModify) 329334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin I->eraseFromParent(); 330334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; 331334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 332334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 333334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Otherwise, can't handle this. 334334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; 335334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 336334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 337334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 338334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinunsigned ARMBaseInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const { 339334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineBasicBlock::iterator I = MBB.end(); 340334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (I == MBB.begin()) return 0; 341334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin --I; 34293d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen while (I->isDebugValue()) { 34393d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen if (I == MBB.begin()) 34493d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen return 0; 34593d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen --I; 34693d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen } 3475ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng if (!isUncondBranchOpcode(I->getOpcode()) && 3485ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng !isCondBranchOpcode(I->getOpcode())) 349334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 0; 350334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 351334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Remove the branch. 352334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin I->eraseFromParent(); 353334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 354334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin I = MBB.end(); 355334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 356334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (I == MBB.begin()) return 1; 357334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin --I; 3585ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng if (!isCondBranchOpcode(I->getOpcode())) 359334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 1; 360334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 361334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Remove the branch. 362334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin I->eraseFromParent(); 363334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 2; 364334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 365334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 366334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinunsigned 367334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinARMBaseInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 3683bf912593301152b65accb9d9c37a95172f1df5aStuart Hastings MachineBasicBlock *FBB, 3693bf912593301152b65accb9d9c37a95172f1df5aStuart Hastings const SmallVectorImpl<MachineOperand> &Cond, 3703bf912593301152b65accb9d9c37a95172f1df5aStuart Hastings DebugLoc DL) const { 3716495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ARMFunctionInfo *AFI = MBB.getParent()->getInfo<ARMFunctionInfo>(); 3726495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng int BOpc = !AFI->isThumbFunction() 3736495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ? ARM::B : (AFI->isThumb2Function() ? ARM::t2B : ARM::tB); 3746495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng int BccOpc = !AFI->isThumbFunction() 3756495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ? ARM::Bcc : (AFI->isThumb2Function() ? ARM::t2Bcc : ARM::tBcc); 376334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 377334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Shouldn't be a fall through. 378334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin assert(TBB && "InsertBranch must not be told to insert a fallthrough"); 379334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin assert((Cond.size() == 2 || Cond.size() == 0) && 380334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin "ARM branch conditions have two components!"); 381334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 382334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (FBB == 0) { 383334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (Cond.empty()) // Unconditional branch? 3843bf912593301152b65accb9d9c37a95172f1df5aStuart Hastings BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB); 385334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin else 3863bf912593301152b65accb9d9c37a95172f1df5aStuart Hastings BuildMI(&MBB, DL, get(BccOpc)).addMBB(TBB) 387334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()); 388334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 1; 389334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 390334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 391334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Two-way conditional branch. 3923bf912593301152b65accb9d9c37a95172f1df5aStuart Hastings BuildMI(&MBB, DL, get(BccOpc)).addMBB(TBB) 393334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()); 3943bf912593301152b65accb9d9c37a95172f1df5aStuart Hastings BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB); 395334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 2; 396334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 397334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 398334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinbool ARMBaseInstrInfo:: 399334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const { 400334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin ARMCC::CondCodes CC = (ARMCC::CondCodes)(int)Cond[0].getImm(); 401334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin Cond[0].setImm(ARMCC::getOppositeCondition(CC)); 402334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 403334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 404334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 405334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinbool ARMBaseInstrInfo:: 406334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinPredicateInstruction(MachineInstr *MI, 407334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const SmallVectorImpl<MachineOperand> &Pred) const { 408334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned Opc = MI->getOpcode(); 4095ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng if (isUncondBranchOpcode(Opc)) { 4105ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng MI->setDesc(get(getMatchingCondBranchOpcode(Opc))); 411334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI->addOperand(MachineOperand::CreateImm(Pred[0].getImm())); 412334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI->addOperand(MachineOperand::CreateReg(Pred[1].getReg(), false)); 413334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; 414334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 415334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 416334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin int PIdx = MI->findFirstPredOperandIdx(); 417334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (PIdx != -1) { 418334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineOperand &PMO = MI->getOperand(PIdx); 419334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin PMO.setImm(Pred[0].getImm()); 420334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI->getOperand(PIdx+1).setReg(Pred[1].getReg()); 421334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; 422334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 423334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 424334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 425334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 426334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinbool ARMBaseInstrInfo:: 427334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinSubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1, 428334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const SmallVectorImpl<MachineOperand> &Pred2) const { 429334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (Pred1.size() > 2 || Pred2.size() > 2) 430334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 431334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 432334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin ARMCC::CondCodes CC1 = (ARMCC::CondCodes)Pred1[0].getImm(); 433334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin ARMCC::CondCodes CC2 = (ARMCC::CondCodes)Pred2[0].getImm(); 434334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (CC1 == CC2) 435334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; 436334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 437334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin switch (CC1) { 438334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin default: 439334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 440334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMCC::AL: 441334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; 442334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMCC::HS: 443334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return CC2 == ARMCC::HI; 444334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMCC::LS: 445334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return CC2 == ARMCC::LO || CC2 == ARMCC::EQ; 446334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMCC::GE: 447334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return CC2 == ARMCC::GT; 448334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMCC::LE: 449334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return CC2 == ARMCC::LT; 450334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 451334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 452334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 453334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinbool ARMBaseInstrInfo::DefinesPredicate(MachineInstr *MI, 454334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin std::vector<MachineOperand> &Pred) const { 4558fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng // FIXME: This confuses implicit_def with optional CPSR def. 456334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const TargetInstrDesc &TID = MI->getDesc(); 457334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (!TID.getImplicitDefs() && !TID.hasOptionalDef()) 458334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 459334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 460334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool Found = false; 461334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 462334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const MachineOperand &MO = MI->getOperand(i); 463334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (MO.isReg() && MO.getReg() == ARM::CPSR) { 464334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin Pred.push_back(MO); 465334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin Found = true; 466334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 467334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 468334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 469334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return Found; 470334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 471334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 472ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng/// isPredicable - Return true if the specified instruction can be predicated. 473ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng/// By default, this returns true for every instruction with a 474ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng/// PredicateOperand. 475ac0869dc8a7986855c5557cc67d4709600158ef5Evan Chengbool ARMBaseInstrInfo::isPredicable(MachineInstr *MI) const { 476ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng const TargetInstrDesc &TID = MI->getDesc(); 477ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng if (!TID.isPredicable()) 478ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng return false; 479ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng 480ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng if ((TID.TSFlags & ARMII::DomainMask) == ARMII::DomainNEON) { 481ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng ARMFunctionInfo *AFI = 482ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng MI->getParent()->getParent()->getInfo<ARMFunctionInfo>(); 483d7f0810c934a7d13acb28c42d737ce58ec990ea8Evan Cheng return AFI->isThumb2Function(); 484ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng } 485ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng return true; 486ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng} 487334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 48856856b1f46ec1f073ceef4e826c544b8b1691608Chris Lattner/// FIXME: Works around a gcc miscompilation with -fstrict-aliasing. 48956856b1f46ec1f073ceef4e826c544b8b1691608Chris LattnerDISABLE_INLINE 490334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinstatic unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT, 49156856b1f46ec1f073ceef4e826c544b8b1691608Chris Lattner unsigned JTI); 492334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinstatic unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT, 493334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned JTI) { 49456856b1f46ec1f073ceef4e826c544b8b1691608Chris Lattner assert(JTI < JT.size()); 495334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return JT[JTI].MBBs.size(); 496334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 497334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 498334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin/// GetInstSize - Return the size of the specified MachineInstr. 499334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin/// 500334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinunsigned ARMBaseInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const { 501334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const MachineBasicBlock &MBB = *MI->getParent(); 502334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const MachineFunction *MF = MBB.getParent(); 50333adcfb4d217f5f23d9bde8ba02b8e48f9605fc5Chris Lattner const MCAsmInfo *MAI = MF->getTarget().getMCAsmInfo(); 504334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 505334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Basic size info comes from the TSFlags field. 506334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const TargetInstrDesc &TID = MI->getDesc(); 50799405df044f2c584242e711cc9023ec90356da82Bruno Cardoso Lopes uint64_t TSFlags = TID.TSFlags; 508334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 509a0ee862f2e3a0d202244e02459ddcf0dca0e8607Evan Cheng unsigned Opc = MI->getOpcode(); 510334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin switch ((TSFlags & ARMII::SizeMask) >> ARMII::SizeShift) { 511334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin default: { 512334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // If this machine instr is an inline asm, measure it. 513334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (MI->getOpcode() == ARM::INLINEASM) 51433adcfb4d217f5f23d9bde8ba02b8e48f9605fc5Chris Lattner return getInlineAsmLength(MI->getOperand(0).getSymbolName(), *MAI); 515334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (MI->isLabel()) 516334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 0; 517a0ee862f2e3a0d202244e02459ddcf0dca0e8607Evan Cheng switch (Opc) { 518334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin default: 519c23197a26f34f559ea9797de51e187087c039c42Torok Edwin llvm_unreachable("Unknown or unset size field for instr!"); 520518bb53485df640d7b7e3f6b0544099020c42aa7Chris Lattner case TargetOpcode::IMPLICIT_DEF: 521518bb53485df640d7b7e3f6b0544099020c42aa7Chris Lattner case TargetOpcode::KILL: 5227431beaba2a01c3fe299c861b2ec85cbf1dc81c4Bill Wendling case TargetOpcode::PROLOG_LABEL: 523518bb53485df640d7b7e3f6b0544099020c42aa7Chris Lattner case TargetOpcode::EH_LABEL: 524375be7730a6f3dee7a6dc319ee6c355a11ac99adDale Johannesen case TargetOpcode::DBG_VALUE: 525334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 0; 526334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 527334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin break; 528334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 529789476240d6b6f8ad9366cadf790a82bd41bb0b3Evan Cheng case ARMII::Size8Bytes: return 8; // ARM instruction x 2. 530789476240d6b6f8ad9366cadf790a82bd41bb0b3Evan Cheng case ARMII::Size4Bytes: return 4; // ARM / Thumb2 instruction. 531789476240d6b6f8ad9366cadf790a82bd41bb0b3Evan Cheng case ARMII::Size2Bytes: return 2; // Thumb1 instruction. 532334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMII::SizeSpecial: { 533a0ee862f2e3a0d202244e02459ddcf0dca0e8607Evan Cheng switch (Opc) { 534334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARM::CONSTPOOL_ENTRY: 535334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // If this machine instr is a constant pool entry, its size is recorded as 536334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // operand #2. 537334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return MI->getOperand(2).getImm(); 5385eb195153950bc7ebfc30649494a78b2096b5ef8Jim Grosbach case ARM::Int_eh_sjlj_longjmp: 5395eb195153950bc7ebfc30649494a78b2096b5ef8Jim Grosbach return 16; 5405eb195153950bc7ebfc30649494a78b2096b5ef8Jim Grosbach case ARM::tInt_eh_sjlj_longjmp: 5415eb195153950bc7ebfc30649494a78b2096b5ef8Jim Grosbach return 10; 542789476240d6b6f8ad9366cadf790a82bd41bb0b3Evan Cheng case ARM::Int_eh_sjlj_setjmp: 543d100755bab38784703f677b8b8eb174b624b346bJim Grosbach case ARM::Int_eh_sjlj_setjmp_nofp: 5440798eddd07b8dc827a4e6e9028c4c3a8d9444286Jim Grosbach return 20; 545d122874996a6faa8832569b632fd73a32ace7ae7Jim Grosbach case ARM::tInt_eh_sjlj_setjmp: 5465aa1684e5da9a85286bf7d29da419d261a70c2f2Jim Grosbach case ARM::t2Int_eh_sjlj_setjmp: 547d100755bab38784703f677b8b8eb174b624b346bJim Grosbach case ARM::t2Int_eh_sjlj_setjmp_nofp: 5480798eddd07b8dc827a4e6e9028c4c3a8d9444286Jim Grosbach return 12; 549334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARM::BR_JTr: 550334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARM::BR_JTm: 551334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARM::BR_JTadd: 552a0ee862f2e3a0d202244e02459ddcf0dca0e8607Evan Cheng case ARM::tBR_JTr: 553d26b14c34cbcee1448b86b524578fc51cc979023Evan Cheng case ARM::t2BR_JT: 554d26b14c34cbcee1448b86b524578fc51cc979023Evan Cheng case ARM::t2TBB: 555d26b14c34cbcee1448b86b524578fc51cc979023Evan Cheng case ARM::t2TBH: { 556334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // These are jumptable branches, i.e. a branch followed by an inlined 557d26b14c34cbcee1448b86b524578fc51cc979023Evan Cheng // jumptable. The size is 4 + 4 * number of entries. For TBB, each 558d26b14c34cbcee1448b86b524578fc51cc979023Evan Cheng // entry is one byte; TBH two byte each. 559a0ee862f2e3a0d202244e02459ddcf0dca0e8607Evan Cheng unsigned EntrySize = (Opc == ARM::t2TBB) 560a0ee862f2e3a0d202244e02459ddcf0dca0e8607Evan Cheng ? 1 : ((Opc == ARM::t2TBH) ? 2 : 4); 561334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned NumOps = TID.getNumOperands(); 562334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineOperand JTOP = 563334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI->getOperand(NumOps - (TID.isPredicable() ? 3 : 2)); 564334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned JTI = JTOP.getIndex(); 565334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo(); 566b1e803985d3378538ae9cff7eed4102c002d1e22Chris Lattner assert(MJTI != 0); 567334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables(); 568334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin assert(JTI < JT.size()); 569334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Thumb instructions are 2 byte aligned, but JT entries are 4 byte 570334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // 4 aligned. The assembler / linker may add 2 byte padding just before 571334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // the JT entries. The size does not include this padding; the 572334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // constant islands pass does separate bookkeeping for it. 573334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // FIXME: If we know the size of the function is less than (1 << 16) *2 574334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // bytes, we can use 16-bit entries instead. Then there won't be an 575334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // alignment issue. 57625f7cfc3cccba6f569f29f79ea533bae960b93c0Evan Cheng unsigned InstSize = (Opc == ARM::tBR_JTr || Opc == ARM::t2BR_JT) ? 2 : 4; 57725f7cfc3cccba6f569f29f79ea533bae960b93c0Evan Cheng unsigned NumEntries = getNumJTEntries(JT, JTI); 57825f7cfc3cccba6f569f29f79ea533bae960b93c0Evan Cheng if (Opc == ARM::t2TBB && (NumEntries & 1)) 57925f7cfc3cccba6f569f29f79ea533bae960b93c0Evan Cheng // Make sure the instruction that follows TBB is 2-byte aligned. 58025f7cfc3cccba6f569f29f79ea533bae960b93c0Evan Cheng // FIXME: Constant island pass should insert an "ALIGN" instruction 58125f7cfc3cccba6f569f29f79ea533bae960b93c0Evan Cheng // instead. 58225f7cfc3cccba6f569f29f79ea533bae960b93c0Evan Cheng ++NumEntries; 58325f7cfc3cccba6f569f29f79ea533bae960b93c0Evan Cheng return NumEntries * EntrySize + InstSize; 584334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 585334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin default: 586334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Otherwise, pseudo-instruction sizes are zero. 587334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 0; 588334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 589334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 590334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 591334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 0; // Not reached 592334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 593334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 594ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesenvoid ARMBaseInstrInfo::copyPhysReg(MachineBasicBlock &MBB, 595ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen MachineBasicBlock::iterator I, DebugLoc DL, 596ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen unsigned DestReg, unsigned SrcReg, 597ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen bool KillSrc) const { 598ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen bool GPRDest = ARM::GPRRegClass.contains(DestReg); 599ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen bool GPRSrc = ARM::GPRRegClass.contains(SrcReg); 600ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen 601ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen if (GPRDest && GPRSrc) { 602ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen AddDefaultCC(AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::MOVr), DestReg) 603ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen .addReg(SrcReg, getKillRegState(KillSrc)))); 604ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen return; 6057bfdca0206f51132b26094c6f83a5ac97ee0f943David Goodwin } 606334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 607ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen bool SPRDest = ARM::SPRRegClass.contains(DestReg); 608ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen bool SPRSrc = ARM::SPRRegClass.contains(SrcReg); 609ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen 610ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen unsigned Opc; 611ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen if (SPRDest && SPRSrc) 612ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen Opc = ARM::VMOVS; 613ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen else if (GPRDest && SPRSrc) 614ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen Opc = ARM::VMOVRS; 615ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen else if (SPRDest && GPRSrc) 616ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen Opc = ARM::VMOVSR; 617ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen else if (ARM::DPRRegClass.contains(DestReg, SrcReg)) 618ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen Opc = ARM::VMOVD; 619ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen else if (ARM::QPRRegClass.contains(DestReg, SrcReg)) 620ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen Opc = ARM::VMOVQ; 621ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen else if (ARM::QQPRRegClass.contains(DestReg, SrcReg)) 622ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen Opc = ARM::VMOVQQ; 623ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen else if (ARM::QQQQPRRegClass.contains(DestReg, SrcReg)) 624ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen Opc = ARM::VMOVQQQQ; 625ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen else 626ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen llvm_unreachable("Impossible reg-to-reg copy"); 627ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen 628ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc), DestReg); 629ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen MIB.addReg(SrcReg, getKillRegState(KillSrc)); 630ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen if (Opc != ARM::VMOVQQ && Opc != ARM::VMOVQQQQ) 631ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen AddDefaultPred(MIB); 632334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 633334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 634c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Chengstatic const 635c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan ChengMachineInstrBuilder &AddDReg(MachineInstrBuilder &MIB, 636c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Cheng unsigned Reg, unsigned SubIdx, unsigned State, 637c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Cheng const TargetRegisterInfo *TRI) { 638c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Cheng if (!SubIdx) 639c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Cheng return MIB.addReg(Reg, State); 640c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Cheng 641c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Cheng if (TargetRegisterInfo::isPhysicalRegister(Reg)) 642c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Cheng return MIB.addReg(TRI->getSubReg(Reg, SubIdx), State); 643c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Cheng return MIB.addReg(Reg, State, SubIdx); 644c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Cheng} 645c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Cheng 646334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinvoid ARMBaseInstrInfo:: 647334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinstoreRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 648334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned SrcReg, bool isKill, int FI, 649746ad69e088176819981b4b2c5ac8dcd49f5e60eEvan Cheng const TargetRegisterClass *RC, 650746ad69e088176819981b4b2c5ac8dcd49f5e60eEvan Cheng const TargetRegisterInfo *TRI) const { 651c7f3ace20c325521c68335a1689645b43b06ddf0Chris Lattner DebugLoc DL; 652334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (I != MBB.end()) DL = I->getDebugLoc(); 653249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MachineFunction &MF = *MBB.getParent(); 654249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MachineFrameInfo &MFI = *MF.getFrameInfo(); 65531bc849123011b8eae6bb3c79876d9a3c26a6a1dJim Grosbach unsigned Align = MFI.getObjectAlignment(FI); 656249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov 657249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MachineMemOperand *MMO = 65859db5496f4fc2ef6111569e542f8b65480ef14c1Chris Lattner MF.getMachineMemOperand(MachinePointerInfo( 65959db5496f4fc2ef6111569e542f8b65480ef14c1Chris Lattner PseudoSourceValue::getFixedStack(FI)), 66059db5496f4fc2ef6111569e542f8b65480ef14c1Chris Lattner MachineMemOperand::MOStore, 661249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MFI.getObjectSize(FI), 66231bc849123011b8eae6bb3c79876d9a3c26a6a1dJim Grosbach Align); 663334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 6640eb0c7401c34c0b4604f732ce54db995eead14e6Bob Wilson // tGPR is used sometimes in ARM instructions that need to avoid using 6656ccfc507dc1f7ad8c8964193a2407264ca644f0dJim Grosbach // certain registers. Just treat it as GPR here. Likewise, rGPR. 6666ccfc507dc1f7ad8c8964193a2407264ca644f0dJim Grosbach if (RC == ARM::tGPRRegisterClass || RC == ARM::tcGPRRegisterClass 6676ccfc507dc1f7ad8c8964193a2407264ca644f0dJim Grosbach || RC == ARM::rGPRRegisterClass) 6680eb0c7401c34c0b4604f732ce54db995eead14e6Bob Wilson RC = ARM::GPRRegisterClass; 6690eb0c7401c34c0b4604f732ce54db995eead14e6Bob Wilson 670ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson switch (RC->getID()) { 671ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson case ARM::GPRRegClassID: 6725732ca084aaa0cd26149e50dd4b487efff37fe41Evan Cheng AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::STR)) 673334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(SrcReg, getKillRegState(isKill)) 674249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov .addFrameIndex(FI).addReg(0).addImm(0).addMemOperand(MMO)); 675ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson break; 676ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson case ARM::SPRRegClassID: 677d31c5496d7e1580058b5c6fbc8fd537a641ea590Evan Cheng AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTRS)) 678d31c5496d7e1580058b5c6fbc8fd537a641ea590Evan Cheng .addReg(SrcReg, getKillRegState(isKill)) 679d31c5496d7e1580058b5c6fbc8fd537a641ea590Evan Cheng .addFrameIndex(FI).addImm(0).addMemOperand(MMO)); 680ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson break; 681ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson case ARM::DPRRegClassID: 682ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson case ARM::DPR_VFP2RegClassID: 683ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson case ARM::DPR_8RegClassID: 684e5165490b7ba24bb2f3043399e0d60e7f3bcf8a5Jim Grosbach AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTRD)) 685334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(SrcReg, getKillRegState(isKill)) 686249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov .addFrameIndex(FI).addImm(0).addMemOperand(MMO)); 687ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson break; 688ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson case ARM::QPRRegClassID: 689ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson case ARM::QPR_VFP2RegClassID: 690ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson case ARM::QPR_8RegClassID: 6910cfcf93c95af91e809ef740eb0ab368477226b40Jim Grosbach if (Align >= 16 && getRegisterInfo().needsStackRealignment(MF)) { 692168f382dc67e5940cabdb28dc933c4f91cdd3137Bob Wilson AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1q64Pseudo)) 693f967ca0eaf30325cabe3c1971bf0dba16cf1b027Bob Wilson .addFrameIndex(FI).addImm(16) 69469b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng .addReg(SrcReg, getKillRegState(isKill)) 69569b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng .addMemOperand(MMO)); 69631bc849123011b8eae6bb3c79876d9a3c26a6a1dJim Grosbach } else { 69769b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMQ)) 69869b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng .addReg(SrcReg, getKillRegState(isKill)) 69969b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng .addFrameIndex(FI) 700d4bfd54ec2947e73ab152c3c548e4dd4beb700baBob Wilson .addImm(ARM_AM::getAM4ModeImm(ARM_AM::ia)) 70169b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng .addMemOperand(MMO)); 70231bc849123011b8eae6bb3c79876d9a3c26a6a1dJim Grosbach } 703ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson break; 704ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson case ARM::QQPRRegClassID: 705ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson case ARM::QQPR_VFP2RegClassID: 706435d4991779d6a47cadff4ea670b490d8507d6c4Evan Cheng if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) { 70722c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng // FIXME: It's possible to only store part of the QQ register if the 70822c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng // spilled def has a sub-register index. 709168f382dc67e5940cabdb28dc933c4f91cdd3137Bob Wilson AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1d64QPseudo)) 710168f382dc67e5940cabdb28dc933c4f91cdd3137Bob Wilson .addFrameIndex(FI).addImm(16) 711168f382dc67e5940cabdb28dc933c4f91cdd3137Bob Wilson .addReg(SrcReg, getKillRegState(isKill)) 712168f382dc67e5940cabdb28dc933c4f91cdd3137Bob Wilson .addMemOperand(MMO)); 713435d4991779d6a47cadff4ea670b490d8507d6c4Evan Cheng } else { 714435d4991779d6a47cadff4ea670b490d8507d6c4Evan Cheng MachineInstrBuilder MIB = 715435d4991779d6a47cadff4ea670b490d8507d6c4Evan Cheng AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMD)) 716435d4991779d6a47cadff4ea670b490d8507d6c4Evan Cheng .addFrameIndex(FI) 717d4bfd54ec2947e73ab152c3c548e4dd4beb700baBob Wilson .addImm(ARM_AM::getAM4ModeImm(ARM_AM::ia))) 718435d4991779d6a47cadff4ea670b490d8507d6c4Evan Cheng .addMemOperand(MMO); 719558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI); 720558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI); 721558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI); 722558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI); 723435d4991779d6a47cadff4ea670b490d8507d6c4Evan Cheng } 724ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson break; 725ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson case ARM::QQQQPRRegClassID: { 72622c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng MachineInstrBuilder MIB = 72722c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMD)) 72822c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng .addFrameIndex(FI) 729d4bfd54ec2947e73ab152c3c548e4dd4beb700baBob Wilson .addImm(ARM_AM::getAM4ModeImm(ARM_AM::ia))) 73022c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng .addMemOperand(MMO); 731558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI); 732558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI); 733558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI); 734558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen MIB = AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI); 735558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen MIB = AddDReg(MIB, SrcReg, ARM::dsub_4, 0, TRI); 736558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen MIB = AddDReg(MIB, SrcReg, ARM::dsub_5, 0, TRI); 737558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen MIB = AddDReg(MIB, SrcReg, ARM::dsub_6, 0, TRI); 738558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen AddDReg(MIB, SrcReg, ARM::dsub_7, 0, TRI); 739ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson break; 740ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson } 741ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson default: 742ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson llvm_unreachable("Unknown regclass!"); 743334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 744334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 745334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 74634327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesenunsigned 74734327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund OlesenARMBaseInstrInfo::isStoreToStackSlot(const MachineInstr *MI, 74834327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen int &FrameIndex) const { 74934327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen switch (MI->getOpcode()) { 75034327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen default: break; 75134327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen case ARM::STR: 75234327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen case ARM::t2STRs: // FIXME: don't use t2STRs to access frame. 75334327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen if (MI->getOperand(1).isFI() && 75434327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen MI->getOperand(2).isReg() && 75534327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen MI->getOperand(3).isImm() && 75634327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen MI->getOperand(2).getReg() == 0 && 75734327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen MI->getOperand(3).getImm() == 0) { 75834327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen FrameIndex = MI->getOperand(1).getIndex(); 75934327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen return MI->getOperand(0).getReg(); 76034327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen } 76134327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen break; 76234327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen case ARM::t2STRi12: 76334327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen case ARM::tSpill: 76434327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen case ARM::VSTRD: 76534327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen case ARM::VSTRS: 76634327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen if (MI->getOperand(1).isFI() && 76734327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen MI->getOperand(2).isImm() && 76834327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen MI->getOperand(2).getImm() == 0) { 76934327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen FrameIndex = MI->getOperand(1).getIndex(); 77034327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen return MI->getOperand(0).getReg(); 77134327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen } 77234327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen break; 773d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen case ARM::VST1q64Pseudo: 774d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen if (MI->getOperand(0).isFI() && 775d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen MI->getOperand(2).getSubReg() == 0) { 776d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen FrameIndex = MI->getOperand(0).getIndex(); 777d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen return MI->getOperand(2).getReg(); 778d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen } 77931bbc51ac9245bc82c933c9db8358ca9bb558ac5Jakob Stoklund Olesen break; 780d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen case ARM::VSTMQ: 781d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen if (MI->getOperand(1).isFI() && 782d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen MI->getOperand(2).isImm() && 783d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen MI->getOperand(2).getImm() == ARM_AM::getAM4ModeImm(ARM_AM::ia) && 784d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen MI->getOperand(0).getSubReg() == 0) { 785d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen FrameIndex = MI->getOperand(1).getIndex(); 786d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen return MI->getOperand(0).getReg(); 787d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen } 788d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen break; 78934327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen } 79034327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen 79134327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen return 0; 79234327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen} 79334327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen 794334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinvoid ARMBaseInstrInfo:: 795334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinloadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 796334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned DestReg, int FI, 797746ad69e088176819981b4b2c5ac8dcd49f5e60eEvan Cheng const TargetRegisterClass *RC, 798746ad69e088176819981b4b2c5ac8dcd49f5e60eEvan Cheng const TargetRegisterInfo *TRI) const { 799c7f3ace20c325521c68335a1689645b43b06ddf0Chris Lattner DebugLoc DL; 800334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (I != MBB.end()) DL = I->getDebugLoc(); 801249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MachineFunction &MF = *MBB.getParent(); 802249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MachineFrameInfo &MFI = *MF.getFrameInfo(); 80331bc849123011b8eae6bb3c79876d9a3c26a6a1dJim Grosbach unsigned Align = MFI.getObjectAlignment(FI); 804249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MachineMemOperand *MMO = 80559db5496f4fc2ef6111569e542f8b65480ef14c1Chris Lattner MF.getMachineMemOperand( 80659db5496f4fc2ef6111569e542f8b65480ef14c1Chris Lattner MachinePointerInfo(PseudoSourceValue::getFixedStack(FI)), 80759db5496f4fc2ef6111569e542f8b65480ef14c1Chris Lattner MachineMemOperand::MOLoad, 808249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MFI.getObjectSize(FI), 80931bc849123011b8eae6bb3c79876d9a3c26a6a1dJim Grosbach Align); 810334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 8110eb0c7401c34c0b4604f732ce54db995eead14e6Bob Wilson // tGPR is used sometimes in ARM instructions that need to avoid using 8120eb0c7401c34c0b4604f732ce54db995eead14e6Bob Wilson // certain registers. Just treat it as GPR here. 8136ccfc507dc1f7ad8c8964193a2407264ca644f0dJim Grosbach if (RC == ARM::tGPRRegisterClass || RC == ARM::tcGPRRegisterClass 8146ccfc507dc1f7ad8c8964193a2407264ca644f0dJim Grosbach || RC == ARM::rGPRRegisterClass) 8150eb0c7401c34c0b4604f732ce54db995eead14e6Bob Wilson RC = ARM::GPRRegisterClass; 8160eb0c7401c34c0b4604f732ce54db995eead14e6Bob Wilson 817ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson switch (RC->getID()) { 818ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson case ARM::GPRRegClassID: 8195732ca084aaa0cd26149e50dd4b487efff37fe41Evan Cheng AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::LDR), DestReg) 820249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov .addFrameIndex(FI).addReg(0).addImm(0).addMemOperand(MMO)); 821ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson break; 822ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson case ARM::SPRRegClassID: 823d31c5496d7e1580058b5c6fbc8fd537a641ea590Evan Cheng AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRS), DestReg) 824d31c5496d7e1580058b5c6fbc8fd537a641ea590Evan Cheng .addFrameIndex(FI).addImm(0).addMemOperand(MMO)); 825ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson break; 826ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson case ARM::DPRRegClassID: 827ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson case ARM::DPR_VFP2RegClassID: 828ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson case ARM::DPR_8RegClassID: 829e5165490b7ba24bb2f3043399e0d60e7f3bcf8a5Jim Grosbach AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRD), DestReg) 830249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov .addFrameIndex(FI).addImm(0).addMemOperand(MMO)); 831ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson break; 832ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson case ARM::QPRRegClassID: 833ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson case ARM::QPR_VFP2RegClassID: 834ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson case ARM::QPR_8RegClassID: 8350cfcf93c95af91e809ef740eb0ab368477226b40Jim Grosbach if (Align >= 16 && getRegisterInfo().needsStackRealignment(MF)) { 836168f382dc67e5940cabdb28dc933c4f91cdd3137Bob Wilson AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1q64Pseudo), DestReg) 837f967ca0eaf30325cabe3c1971bf0dba16cf1b027Bob Wilson .addFrameIndex(FI).addImm(16) 83869b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng .addMemOperand(MMO)); 83931bc849123011b8eae6bb3c79876d9a3c26a6a1dJim Grosbach } else { 84069b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMQ), DestReg) 84169b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng .addFrameIndex(FI) 842d4bfd54ec2947e73ab152c3c548e4dd4beb700baBob Wilson .addImm(ARM_AM::getAM4ModeImm(ARM_AM::ia)) 84369b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng .addMemOperand(MMO)); 84431bc849123011b8eae6bb3c79876d9a3c26a6a1dJim Grosbach } 845ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson break; 846ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson case ARM::QQPRRegClassID: 847ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson case ARM::QQPR_VFP2RegClassID: 848435d4991779d6a47cadff4ea670b490d8507d6c4Evan Cheng if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) { 849168f382dc67e5940cabdb28dc933c4f91cdd3137Bob Wilson AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1d64QPseudo), DestReg) 850168f382dc67e5940cabdb28dc933c4f91cdd3137Bob Wilson .addFrameIndex(FI).addImm(16) 851168f382dc67e5940cabdb28dc933c4f91cdd3137Bob Wilson .addMemOperand(MMO)); 852435d4991779d6a47cadff4ea670b490d8507d6c4Evan Cheng } else { 853435d4991779d6a47cadff4ea670b490d8507d6c4Evan Cheng MachineInstrBuilder MIB = 854435d4991779d6a47cadff4ea670b490d8507d6c4Evan Cheng AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMD)) 855435d4991779d6a47cadff4ea670b490d8507d6c4Evan Cheng .addFrameIndex(FI) 856d4bfd54ec2947e73ab152c3c548e4dd4beb700baBob Wilson .addImm(ARM_AM::getAM4ModeImm(ARM_AM::ia))) 857435d4991779d6a47cadff4ea670b490d8507d6c4Evan Cheng .addMemOperand(MMO); 858558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::Define, TRI); 859558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::Define, TRI); 860558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::Define, TRI); 861558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen AddDReg(MIB, DestReg, ARM::dsub_3, RegState::Define, TRI); 862435d4991779d6a47cadff4ea670b490d8507d6c4Evan Cheng } 863ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson break; 864ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson case ARM::QQQQPRRegClassID: { 865ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson MachineInstrBuilder MIB = 866ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMD)) 867ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson .addFrameIndex(FI) 868d4bfd54ec2947e73ab152c3c548e4dd4beb700baBob Wilson .addImm(ARM_AM::getAM4ModeImm(ARM_AM::ia))) 869ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson .addMemOperand(MMO); 870ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::Define, TRI); 871ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::Define, TRI); 872ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::Define, TRI); 873ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::Define, TRI); 874ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson MIB = AddDReg(MIB, DestReg, ARM::dsub_4, RegState::Define, TRI); 875ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson MIB = AddDReg(MIB, DestReg, ARM::dsub_5, RegState::Define, TRI); 876ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson MIB = AddDReg(MIB, DestReg, ARM::dsub_6, RegState::Define, TRI); 877ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson AddDReg(MIB, DestReg, ARM::dsub_7, RegState::Define, TRI); 878ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson break; 879ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson } 880ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson default: 881ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson llvm_unreachable("Unknown regclass!"); 882334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 883334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 884334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 88534327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesenunsigned 88634327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund OlesenARMBaseInstrInfo::isLoadFromStackSlot(const MachineInstr *MI, 88734327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen int &FrameIndex) const { 88834327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen switch (MI->getOpcode()) { 88934327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen default: break; 89034327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen case ARM::LDR: 89134327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen case ARM::t2LDRs: // FIXME: don't use t2LDRs to access frame. 89234327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen if (MI->getOperand(1).isFI() && 89334327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen MI->getOperand(2).isReg() && 89434327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen MI->getOperand(3).isImm() && 89534327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen MI->getOperand(2).getReg() == 0 && 89634327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen MI->getOperand(3).getImm() == 0) { 89734327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen FrameIndex = MI->getOperand(1).getIndex(); 89834327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen return MI->getOperand(0).getReg(); 89934327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen } 90034327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen break; 90134327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen case ARM::t2LDRi12: 90234327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen case ARM::tRestore: 90334327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen case ARM::VLDRD: 90434327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen case ARM::VLDRS: 90534327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen if (MI->getOperand(1).isFI() && 90634327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen MI->getOperand(2).isImm() && 90734327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen MI->getOperand(2).getImm() == 0) { 90834327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen FrameIndex = MI->getOperand(1).getIndex(); 909d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen return MI->getOperand(0).getReg(); 910d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen } 911d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen break; 912d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen case ARM::VLD1q64Pseudo: 913d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen if (MI->getOperand(1).isFI() && 914d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen MI->getOperand(0).getSubReg() == 0) { 915d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen FrameIndex = MI->getOperand(1).getIndex(); 91606f264e504d75f0426eea55b9f9e36c780d8a4fcJakob Stoklund Olesen return MI->getOperand(0).getReg(); 91706f264e504d75f0426eea55b9f9e36c780d8a4fcJakob Stoklund Olesen } 91806f264e504d75f0426eea55b9f9e36c780d8a4fcJakob Stoklund Olesen break; 91906f264e504d75f0426eea55b9f9e36c780d8a4fcJakob Stoklund Olesen case ARM::VLDMQ: 92006f264e504d75f0426eea55b9f9e36c780d8a4fcJakob Stoklund Olesen if (MI->getOperand(1).isFI() && 92106f264e504d75f0426eea55b9f9e36c780d8a4fcJakob Stoklund Olesen MI->getOperand(2).isImm() && 92206f264e504d75f0426eea55b9f9e36c780d8a4fcJakob Stoklund Olesen MI->getOperand(2).getImm() == ARM_AM::getAM4ModeImm(ARM_AM::ia) && 92306f264e504d75f0426eea55b9f9e36c780d8a4fcJakob Stoklund Olesen MI->getOperand(0).getSubReg() == 0) { 92406f264e504d75f0426eea55b9f9e36c780d8a4fcJakob Stoklund Olesen FrameIndex = MI->getOperand(1).getIndex(); 92534327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen return MI->getOperand(0).getReg(); 92634327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen } 92734327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen break; 92834327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen } 92934327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen 93034327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen return 0; 93134327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen} 93234327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen 93362b50656ceb854eb0be265d63b2a1d46e7400d8aEvan ChengMachineInstr* 93462b50656ceb854eb0be265d63b2a1d46e7400d8aEvan ChengARMBaseInstrInfo::emitFrameIndexDebugValue(MachineFunction &MF, 9358601a3d4decff0a380e059b037dabf71075497d3Evan Cheng int FrameIx, uint64_t Offset, 93662b50656ceb854eb0be265d63b2a1d46e7400d8aEvan Cheng const MDNode *MDPtr, 93762b50656ceb854eb0be265d63b2a1d46e7400d8aEvan Cheng DebugLoc DL) const { 93862b50656ceb854eb0be265d63b2a1d46e7400d8aEvan Cheng MachineInstrBuilder MIB = BuildMI(MF, DL, get(ARM::DBG_VALUE)) 93962b50656ceb854eb0be265d63b2a1d46e7400d8aEvan Cheng .addFrameIndex(FrameIx).addImm(0).addImm(Offset).addMetadata(MDPtr); 94062b50656ceb854eb0be265d63b2a1d46e7400d8aEvan Cheng return &*MIB; 94162b50656ceb854eb0be265d63b2a1d46e7400d8aEvan Cheng} 94262b50656ceb854eb0be265d63b2a1d46e7400d8aEvan Cheng 94330ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen/// Create a copy of a const pool value. Update CPI to the new index and return 94430ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen/// the label UID. 94530ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesenstatic unsigned duplicateCPV(MachineFunction &MF, unsigned &CPI) { 94630ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen MachineConstantPool *MCP = MF.getConstantPool(); 94730ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 94830ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen 94930ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPI]; 95030ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen assert(MCPE.isMachineConstantPoolEntry() && 95130ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen "Expecting a machine constantpool entry!"); 95230ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen ARMConstantPoolValue *ACPV = 95330ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal); 95430ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen 95530ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen unsigned PCLabelId = AFI->createConstPoolEntryUId(); 95630ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen ARMConstantPoolValue *NewCPV = 0; 95751f5b67395780b8421f4aa6ee998ed51b23dae9dJim Grosbach // FIXME: The below assumes PIC relocation model and that the function 95851f5b67395780b8421f4aa6ee998ed51b23dae9dJim Grosbach // is Thumb mode (t1 or t2). PCAdjustment would be 8 for ARM mode PIC, and 95951f5b67395780b8421f4aa6ee998ed51b23dae9dJim Grosbach // zero for non-PIC in ARM or Thumb. The callers are all of thumb LDR 96051f5b67395780b8421f4aa6ee998ed51b23dae9dJim Grosbach // instructions, so that's probably OK, but is PIC always correct when 96151f5b67395780b8421f4aa6ee998ed51b23dae9dJim Grosbach // we get here? 96230ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen if (ACPV->isGlobalValue()) 96330ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen NewCPV = new ARMConstantPoolValue(ACPV->getGV(), PCLabelId, 96430ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen ARMCP::CPValue, 4); 96530ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen else if (ACPV->isExtSymbol()) 96630ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen NewCPV = new ARMConstantPoolValue(MF.getFunction()->getContext(), 96730ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen ACPV->getSymbol(), PCLabelId, 4); 96830ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen else if (ACPV->isBlockAddress()) 96930ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen NewCPV = new ARMConstantPoolValue(ACPV->getBlockAddress(), PCLabelId, 97030ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen ARMCP::CPBlockAddress, 4); 97151f5b67395780b8421f4aa6ee998ed51b23dae9dJim Grosbach else if (ACPV->isLSDA()) 97251f5b67395780b8421f4aa6ee998ed51b23dae9dJim Grosbach NewCPV = new ARMConstantPoolValue(MF.getFunction(), PCLabelId, 97351f5b67395780b8421f4aa6ee998ed51b23dae9dJim Grosbach ARMCP::CPLSDA, 4); 97430ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen else 97530ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen llvm_unreachable("Unexpected ARM constantpool value type!!"); 97630ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen CPI = MCP->getConstantPoolIndex(NewCPV, MCPE.getAlignment()); 97730ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen return PCLabelId; 97830ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen} 97930ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen 980fdc834046efd427d474e3b899ec69354c05071e0Evan Chengvoid ARMBaseInstrInfo:: 981fdc834046efd427d474e3b899ec69354c05071e0Evan ChengreMaterialize(MachineBasicBlock &MBB, 982fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng MachineBasicBlock::iterator I, 983fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng unsigned DestReg, unsigned SubIdx, 984d57cdd5683ea926e489067364fb7ffe5fd5d35eeEvan Cheng const MachineInstr *Orig, 9859edf7deb37f0f97664f279040fa15d89f32e23d9Jakob Stoklund Olesen const TargetRegisterInfo &TRI) const { 986fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng unsigned Opcode = Orig->getOpcode(); 987fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng switch (Opcode) { 988fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng default: { 989fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig); 9909edf7deb37f0f97664f279040fa15d89f32e23d9Jakob Stoklund Olesen MI->substituteRegister(Orig->getOperand(0).getReg(), DestReg, SubIdx, TRI); 991fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng MBB.insert(I, MI); 992fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng break; 993fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng } 994fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng case ARM::tLDRpci_pic: 995fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng case ARM::t2LDRpci_pic: { 996fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng MachineFunction &MF = *MBB.getParent(); 997fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng unsigned CPI = Orig->getOperand(1).getIndex(); 99830ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen unsigned PCLabelId = duplicateCPV(MF, CPI); 999fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng MachineInstrBuilder MIB = BuildMI(MBB, I, Orig->getDebugLoc(), get(Opcode), 1000fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng DestReg) 1001fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng .addConstantPoolIndex(CPI).addImm(PCLabelId); 1002fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng (*MIB).setMemRefs(Orig->memoperands_begin(), Orig->memoperands_end()); 1003fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng break; 1004fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng } 1005fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng } 1006fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng} 1007fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng 100830ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund OlesenMachineInstr * 100930ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund OlesenARMBaseInstrInfo::duplicate(MachineInstr *Orig, MachineFunction &MF) const { 101030ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen MachineInstr *MI = TargetInstrInfoImpl::duplicate(Orig, MF); 101130ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen switch(Orig->getOpcode()) { 101230ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen case ARM::tLDRpci_pic: 101330ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen case ARM::t2LDRpci_pic: { 101430ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen unsigned CPI = Orig->getOperand(1).getIndex(); 101530ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen unsigned PCLabelId = duplicateCPV(MF, CPI); 101630ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen Orig->getOperand(1).setIndex(CPI); 101730ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen Orig->getOperand(2).setImm(PCLabelId); 101830ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen break; 101930ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen } 102030ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen } 102130ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen return MI; 102230ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen} 102330ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen 1024506049f29f4f202a8e45feb916cc0264440a7f6dEvan Chengbool ARMBaseInstrInfo::produceSameValue(const MachineInstr *MI0, 1025506049f29f4f202a8e45feb916cc0264440a7f6dEvan Cheng const MachineInstr *MI1) const { 1026d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng int Opcode = MI0->getOpcode(); 10279b82425cb0105fd5704f6b9bcd5e7693b05b1759Evan Cheng if (Opcode == ARM::t2LDRpci || 10289b82425cb0105fd5704f6b9bcd5e7693b05b1759Evan Cheng Opcode == ARM::t2LDRpci_pic || 10299b82425cb0105fd5704f6b9bcd5e7693b05b1759Evan Cheng Opcode == ARM::tLDRpci || 10309b82425cb0105fd5704f6b9bcd5e7693b05b1759Evan Cheng Opcode == ARM::tLDRpci_pic) { 1031d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng if (MI1->getOpcode() != Opcode) 1032d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng return false; 1033d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng if (MI0->getNumOperands() != MI1->getNumOperands()) 1034d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng return false; 1035d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng 1036d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng const MachineOperand &MO0 = MI0->getOperand(1); 1037d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng const MachineOperand &MO1 = MI1->getOperand(1); 1038d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng if (MO0.getOffset() != MO1.getOffset()) 1039d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng return false; 1040d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng 1041d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng const MachineFunction *MF = MI0->getParent()->getParent(); 1042d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng const MachineConstantPool *MCP = MF->getConstantPool(); 1043d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng int CPI0 = MO0.getIndex(); 1044d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng int CPI1 = MO1.getIndex(); 1045d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng const MachineConstantPoolEntry &MCPE0 = MCP->getConstants()[CPI0]; 1046d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng const MachineConstantPoolEntry &MCPE1 = MCP->getConstants()[CPI1]; 1047d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng ARMConstantPoolValue *ACPV0 = 1048d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng static_cast<ARMConstantPoolValue*>(MCPE0.Val.MachineCPVal); 1049d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng ARMConstantPoolValue *ACPV1 = 1050d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng static_cast<ARMConstantPoolValue*>(MCPE1.Val.MachineCPVal); 1051d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng return ACPV0->hasSameValue(ACPV1); 1052d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng } 1053d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng 1054506049f29f4f202a8e45feb916cc0264440a7f6dEvan Cheng return MI0->isIdenticalTo(MI1, MachineInstr::IgnoreVRegDefs); 1055d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng} 1056d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng 10574b722108e2cf8e77157e0879a23789cd44829933Bill Wendling/// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to 10584b722108e2cf8e77157e0879a23789cd44829933Bill Wendling/// determine if two loads are loading from the same base address. It should 10594b722108e2cf8e77157e0879a23789cd44829933Bill Wendling/// only return true if the base pointers are the same and the only differences 10604b722108e2cf8e77157e0879a23789cd44829933Bill Wendling/// between the two addresses is the offset. It also returns the offsets by 10614b722108e2cf8e77157e0879a23789cd44829933Bill Wendling/// reference. 10624b722108e2cf8e77157e0879a23789cd44829933Bill Wendlingbool ARMBaseInstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, 10634b722108e2cf8e77157e0879a23789cd44829933Bill Wendling int64_t &Offset1, 10644b722108e2cf8e77157e0879a23789cd44829933Bill Wendling int64_t &Offset2) const { 10654b722108e2cf8e77157e0879a23789cd44829933Bill Wendling // Don't worry about Thumb: just ARM and Thumb2. 10664b722108e2cf8e77157e0879a23789cd44829933Bill Wendling if (Subtarget.isThumb1Only()) return false; 10674b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 10684b722108e2cf8e77157e0879a23789cd44829933Bill Wendling if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode()) 10694b722108e2cf8e77157e0879a23789cd44829933Bill Wendling return false; 10704b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 10714b722108e2cf8e77157e0879a23789cd44829933Bill Wendling switch (Load1->getMachineOpcode()) { 10724b722108e2cf8e77157e0879a23789cd44829933Bill Wendling default: 10734b722108e2cf8e77157e0879a23789cd44829933Bill Wendling return false; 10744b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::LDR: 10754b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::LDRB: 10764b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::LDRD: 10774b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::LDRH: 10784b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::LDRSB: 10794b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::LDRSH: 10804b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::VLDRD: 10814b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::VLDRS: 10824b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::t2LDRi8: 10834b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::t2LDRDi8: 10844b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::t2LDRSHi8: 10854b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::t2LDRi12: 10864b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::t2LDRSHi12: 10874b722108e2cf8e77157e0879a23789cd44829933Bill Wendling break; 10884b722108e2cf8e77157e0879a23789cd44829933Bill Wendling } 10894b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 10904b722108e2cf8e77157e0879a23789cd44829933Bill Wendling switch (Load2->getMachineOpcode()) { 10914b722108e2cf8e77157e0879a23789cd44829933Bill Wendling default: 10924b722108e2cf8e77157e0879a23789cd44829933Bill Wendling return false; 10934b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::LDR: 10944b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::LDRB: 10954b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::LDRD: 10964b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::LDRH: 10974b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::LDRSB: 10984b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::LDRSH: 10994b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::VLDRD: 11004b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::VLDRS: 11014b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::t2LDRi8: 11024b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::t2LDRDi8: 11034b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::t2LDRSHi8: 11044b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::t2LDRi12: 11054b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::t2LDRSHi12: 11064b722108e2cf8e77157e0879a23789cd44829933Bill Wendling break; 11074b722108e2cf8e77157e0879a23789cd44829933Bill Wendling } 11084b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 11094b722108e2cf8e77157e0879a23789cd44829933Bill Wendling // Check if base addresses and chain operands match. 11104b722108e2cf8e77157e0879a23789cd44829933Bill Wendling if (Load1->getOperand(0) != Load2->getOperand(0) || 11114b722108e2cf8e77157e0879a23789cd44829933Bill Wendling Load1->getOperand(4) != Load2->getOperand(4)) 11124b722108e2cf8e77157e0879a23789cd44829933Bill Wendling return false; 11134b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 11144b722108e2cf8e77157e0879a23789cd44829933Bill Wendling // Index should be Reg0. 11154b722108e2cf8e77157e0879a23789cd44829933Bill Wendling if (Load1->getOperand(3) != Load2->getOperand(3)) 11164b722108e2cf8e77157e0879a23789cd44829933Bill Wendling return false; 11174b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 11184b722108e2cf8e77157e0879a23789cd44829933Bill Wendling // Determine the offsets. 11194b722108e2cf8e77157e0879a23789cd44829933Bill Wendling if (isa<ConstantSDNode>(Load1->getOperand(1)) && 11204b722108e2cf8e77157e0879a23789cd44829933Bill Wendling isa<ConstantSDNode>(Load2->getOperand(1))) { 11214b722108e2cf8e77157e0879a23789cd44829933Bill Wendling Offset1 = cast<ConstantSDNode>(Load1->getOperand(1))->getSExtValue(); 11224b722108e2cf8e77157e0879a23789cd44829933Bill Wendling Offset2 = cast<ConstantSDNode>(Load2->getOperand(1))->getSExtValue(); 11234b722108e2cf8e77157e0879a23789cd44829933Bill Wendling return true; 11244b722108e2cf8e77157e0879a23789cd44829933Bill Wendling } 11254b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 11264b722108e2cf8e77157e0879a23789cd44829933Bill Wendling return false; 11274b722108e2cf8e77157e0879a23789cd44829933Bill Wendling} 11284b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 11294b722108e2cf8e77157e0879a23789cd44829933Bill Wendling/// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to 11304b722108e2cf8e77157e0879a23789cd44829933Bill Wendling/// determine (in conjuction with areLoadsFromSameBasePtr) if two loads should 11314b722108e2cf8e77157e0879a23789cd44829933Bill Wendling/// be scheduled togther. On some targets if two loads are loading from 11324b722108e2cf8e77157e0879a23789cd44829933Bill Wendling/// addresses in the same cache line, it's better if they are scheduled 11334b722108e2cf8e77157e0879a23789cd44829933Bill Wendling/// together. This function takes two integers that represent the load offsets 11344b722108e2cf8e77157e0879a23789cd44829933Bill Wendling/// from the common base address. It returns true if it decides it's desirable 11354b722108e2cf8e77157e0879a23789cd44829933Bill Wendling/// to schedule the two loads together. "NumLoads" is the number of loads that 11364b722108e2cf8e77157e0879a23789cd44829933Bill Wendling/// have already been scheduled after Load1. 11374b722108e2cf8e77157e0879a23789cd44829933Bill Wendlingbool ARMBaseInstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, 11384b722108e2cf8e77157e0879a23789cd44829933Bill Wendling int64_t Offset1, int64_t Offset2, 11394b722108e2cf8e77157e0879a23789cd44829933Bill Wendling unsigned NumLoads) const { 11404b722108e2cf8e77157e0879a23789cd44829933Bill Wendling // Don't worry about Thumb: just ARM and Thumb2. 11414b722108e2cf8e77157e0879a23789cd44829933Bill Wendling if (Subtarget.isThumb1Only()) return false; 11424b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 11434b722108e2cf8e77157e0879a23789cd44829933Bill Wendling assert(Offset2 > Offset1); 11444b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 11454b722108e2cf8e77157e0879a23789cd44829933Bill Wendling if ((Offset2 - Offset1) / 8 > 64) 11464b722108e2cf8e77157e0879a23789cd44829933Bill Wendling return false; 11474b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 11484b722108e2cf8e77157e0879a23789cd44829933Bill Wendling if (Load1->getMachineOpcode() != Load2->getMachineOpcode()) 11494b722108e2cf8e77157e0879a23789cd44829933Bill Wendling return false; // FIXME: overly conservative? 11504b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 11514b722108e2cf8e77157e0879a23789cd44829933Bill Wendling // Four loads in a row should be sufficient. 11524b722108e2cf8e77157e0879a23789cd44829933Bill Wendling if (NumLoads >= 3) 11534b722108e2cf8e77157e0879a23789cd44829933Bill Wendling return false; 11544b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 11554b722108e2cf8e77157e0879a23789cd44829933Bill Wendling return true; 11564b722108e2cf8e77157e0879a23789cd44829933Bill Wendling} 11574b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 115886050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Chengbool ARMBaseInstrInfo::isSchedulingBoundary(const MachineInstr *MI, 115986050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng const MachineBasicBlock *MBB, 116086050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng const MachineFunction &MF) const { 116157bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach // Debug info is never a scheduling boundary. It's necessary to be explicit 116257bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach // due to the special treatment of IT instructions below, otherwise a 116357bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach // dbg_value followed by an IT will result in the IT instruction being 116457bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach // considered a scheduling hazard, which is wrong. It should be the actual 116557bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach // instruction preceding the dbg_value instruction(s), just like it is 116657bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach // when debug info is not present. 116757bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach if (MI->isDebugValue()) 116857bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach return false; 116957bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach 117086050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // Terminators and labels can't be scheduled around. 117186050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng if (MI->getDesc().isTerminator() || MI->isLabel()) 117286050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng return true; 117386050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng 117486050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // Treat the start of the IT block as a scheduling boundary, but schedule 117586050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // t2IT along with all instructions following it. 117686050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // FIXME: This is a big hammer. But the alternative is to add all potential 117786050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // true and anti dependencies to IT block instructions as implicit operands 117886050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // to the t2IT instruction. The added compile time and complexity does not 117986050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // seem worth it. 118086050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng MachineBasicBlock::const_iterator I = MI; 118157bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach // Make sure to skip any dbg_value instructions 118257bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach while (++I != MBB->end() && I->isDebugValue()) 118357bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach ; 118457bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach if (I != MBB->end() && I->getOpcode() == ARM::t2IT) 118586050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng return true; 118686050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng 118786050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // Don't attempt to schedule around any instruction that defines 118886050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // a stack-oriented pointer, as it's unlikely to be profitable. This 118986050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // saves compile time, because it doesn't require every single 119086050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // stack slot reference to depend on the instruction that does the 119186050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // modification. 119286050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng if (MI->definesRegister(ARM::SP)) 119386050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng return true; 119486050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng 119586050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng return false; 119686050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng} 119786050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng 1198b20b85168c0e9819e6545f08281e9b83c82108f0Owen Andersonbool ARMBaseInstrInfo::isProfitableToIfCvt(MachineBasicBlock &MBB, 1199b20b85168c0e9819e6545f08281e9b83c82108f0Owen Anderson unsigned NumInstrs, 1200b20b85168c0e9819e6545f08281e9b83c82108f0Owen Anderson float Probability) const { 120113151432edace19ee867a93b5c14573df4f75d24Evan Cheng if (!NumInstrs) 120213151432edace19ee867a93b5c14573df4f75d24Evan Cheng return false; 1203b20b85168c0e9819e6545f08281e9b83c82108f0Owen Anderson 1204b20b85168c0e9819e6545f08281e9b83c82108f0Owen Anderson // Attempt to estimate the relative costs of predication versus branching. 1205b20b85168c0e9819e6545f08281e9b83c82108f0Owen Anderson float UnpredCost = Probability * NumInstrs; 1206654d5440a477b1f6c89b051107e041a331f78e27Owen Anderson UnpredCost += 1.0; // The branch itself 1207654d5440a477b1f6c89b051107e041a331f78e27Owen Anderson UnpredCost += 0.1 * Subtarget.getMispredictionPenalty(); 1208b20b85168c0e9819e6545f08281e9b83c82108f0Owen Anderson 1209b20b85168c0e9819e6545f08281e9b83c82108f0Owen Anderson float PredCost = NumInstrs; 1210b20b85168c0e9819e6545f08281e9b83c82108f0Owen Anderson 1211b20b85168c0e9819e6545f08281e9b83c82108f0Owen Anderson return PredCost < UnpredCost; 1212b20b85168c0e9819e6545f08281e9b83c82108f0Owen Anderson 121313151432edace19ee867a93b5c14573df4f75d24Evan Cheng} 121413151432edace19ee867a93b5c14573df4f75d24Evan Cheng 121513151432edace19ee867a93b5c14573df4f75d24Evan Chengbool ARMBaseInstrInfo:: 121613151432edace19ee867a93b5c14573df4f75d24Evan ChengisProfitableToIfCvt(MachineBasicBlock &TMBB, unsigned NumT, 1217b20b85168c0e9819e6545f08281e9b83c82108f0Owen Anderson MachineBasicBlock &FMBB, unsigned NumF, 1218b20b85168c0e9819e6545f08281e9b83c82108f0Owen Anderson float Probability) const { 1219b20b85168c0e9819e6545f08281e9b83c82108f0Owen Anderson if (!NumT || !NumF) 1220b20b85168c0e9819e6545f08281e9b83c82108f0Owen Anderson return false; 1221b20b85168c0e9819e6545f08281e9b83c82108f0Owen Anderson 1222b20b85168c0e9819e6545f08281e9b83c82108f0Owen Anderson // Attempt to estimate the relative costs of predication versus branching. 1223b20b85168c0e9819e6545f08281e9b83c82108f0Owen Anderson float UnpredCost = Probability * NumT + (1.0 - Probability) * NumF; 1224654d5440a477b1f6c89b051107e041a331f78e27Owen Anderson UnpredCost += 1.0; // The branch itself 1225654d5440a477b1f6c89b051107e041a331f78e27Owen Anderson UnpredCost += 0.1 * Subtarget.getMispredictionPenalty(); 1226b20b85168c0e9819e6545f08281e9b83c82108f0Owen Anderson 1227b20b85168c0e9819e6545f08281e9b83c82108f0Owen Anderson float PredCost = NumT + NumF; 1228b20b85168c0e9819e6545f08281e9b83c82108f0Owen Anderson 1229b20b85168c0e9819e6545f08281e9b83c82108f0Owen Anderson return PredCost < UnpredCost; 123013151432edace19ee867a93b5c14573df4f75d24Evan Cheng} 123113151432edace19ee867a93b5c14573df4f75d24Evan Cheng 12328fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng/// getInstrPredicate - If instruction is predicated, returns its predicate 12338fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng/// condition, otherwise returns AL. It also returns the condition code 12348fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng/// register by reference. 12355adb66a646e2ec32265263739f5b01c3f50c176aEvan ChengARMCC::CondCodes 12365adb66a646e2ec32265263739f5b01c3f50c176aEvan Chengllvm::getInstrPredicate(const MachineInstr *MI, unsigned &PredReg) { 12378fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng int PIdx = MI->findFirstPredOperandIdx(); 12388fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng if (PIdx == -1) { 12398fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng PredReg = 0; 12408fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng return ARMCC::AL; 12418fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng } 12428fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng 12438fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng PredReg = MI->getOperand(PIdx+1).getReg(); 12448fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng return (ARMCC::CondCodes)MI->getOperand(PIdx).getImm(); 12458fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng} 12468fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng 12478fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng 12486495f63945e8dbde81f03a1dc2ab421993b9a495Evan Chengint llvm::getMatchingCondBranchOpcode(int Opc) { 12495ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng if (Opc == ARM::B) 12505ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng return ARM::Bcc; 12515ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng else if (Opc == ARM::tB) 12525ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng return ARM::tBcc; 12535ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng else if (Opc == ARM::t2B) 12545ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng return ARM::t2Bcc; 12555ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng 12565ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng llvm_unreachable("Unknown unconditional branch opcode!"); 12575ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng return 0; 12585ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng} 12595ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng 12606495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 12616495f63945e8dbde81f03a1dc2ab421993b9a495Evan Chengvoid llvm::emitARMRegPlusImmediate(MachineBasicBlock &MBB, 12626495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MachineBasicBlock::iterator &MBBI, DebugLoc dl, 12636495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned DestReg, unsigned BaseReg, int NumBytes, 12646495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ARMCC::CondCodes Pred, unsigned PredReg, 12656495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng const ARMBaseInstrInfo &TII) { 12666495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng bool isSub = NumBytes < 0; 12676495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (isSub) NumBytes = -NumBytes; 12686495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 12696495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng while (NumBytes) { 12706495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned RotAmt = ARM_AM::getSOImmValRotate(NumBytes); 12716495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned ThisVal = NumBytes & ARM_AM::rotr32(0xFF, RotAmt); 12726495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng assert(ThisVal && "Didn't extract field correctly"); 12736495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 12746495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // We will handle these bits from offset, clear them. 12756495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng NumBytes &= ~ThisVal; 12766495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 12776495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng assert(ARM_AM::getSOImmVal(ThisVal) != -1 && "Bit extraction didn't work?"); 12786495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 12796495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Build the new ADD / SUB. 12806495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned Opc = isSub ? ARM::SUBri : ARM::ADDri; 12816495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg) 12826495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng .addReg(BaseReg, RegState::Kill).addImm(ThisVal) 12836495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng .addImm((unsigned)Pred).addReg(PredReg).addReg(0); 12846495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng BaseReg = DestReg; 12856495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 12866495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng} 12876495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 1288cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Chengbool llvm::rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx, 1289cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng unsigned FrameReg, int &Offset, 1290cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng const ARMBaseInstrInfo &TII) { 12916495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned Opcode = MI.getOpcode(); 12926495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng const TargetInstrDesc &Desc = MI.getDesc(); 12936495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask); 12946495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng bool isSub = false; 1295764ab52dd80310a205c9888bf166d09dab858f90Jim Grosbach 12966495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Memory operands in inline assembly always use AddrMode2. 12976495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (Opcode == ARM::INLINEASM) 12986495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng AddrMode = ARMII::AddrMode2; 1299764ab52dd80310a205c9888bf166d09dab858f90Jim Grosbach 13006495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (Opcode == ARM::ADDri) { 13016495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng Offset += MI.getOperand(FrameRegIdx+1).getImm(); 13026495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (Offset == 0) { 13036495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Turn it into a move. 13046495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MI.setDesc(TII.get(ARM::MOVr)); 13056495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false); 13066495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MI.RemoveOperand(FrameRegIdx+1); 1307cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng Offset = 0; 1308cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng return true; 13096495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } else if (Offset < 0) { 13106495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng Offset = -Offset; 13116495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng isSub = true; 13126495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MI.setDesc(TII.get(ARM::SUBri)); 13136495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 13146495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 13156495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Common case: small offset, fits into instruction. 13166495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (ARM_AM::getSOImmVal(Offset) != -1) { 13176495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Replace the FrameIndex with sp / fp 13186495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false); 13196495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset); 1320cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng Offset = 0; 1321cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng return true; 13226495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 13236495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 13246495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Otherwise, pull as much of the immedidate into this ADDri/SUBri 13256495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // as possible. 13266495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned RotAmt = ARM_AM::getSOImmValRotate(Offset); 13276495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xFF, RotAmt); 13286495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 13296495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // We will handle these bits from offset, clear them. 13306495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng Offset &= ~ThisImmVal; 13316495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 13326495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Get the properly encoded SOImmVal field. 13336495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng assert(ARM_AM::getSOImmVal(ThisImmVal) != -1 && 13346495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng "Bit extraction didn't work?"); 13356495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MI.getOperand(FrameRegIdx+1).ChangeToImmediate(ThisImmVal); 13366495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } else { 13376495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned ImmIdx = 0; 13386495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng int InstrOffs = 0; 13396495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned NumBits = 0; 13406495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned Scale = 1; 13416495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng switch (AddrMode) { 13426495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng case ARMII::AddrMode2: { 13436495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ImmIdx = FrameRegIdx+2; 13446495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng InstrOffs = ARM_AM::getAM2Offset(MI.getOperand(ImmIdx).getImm()); 13456495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (ARM_AM::getAM2Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub) 13466495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng InstrOffs *= -1; 13476495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng NumBits = 12; 13486495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng break; 13496495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 13506495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng case ARMII::AddrMode3: { 13516495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ImmIdx = FrameRegIdx+2; 13526495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng InstrOffs = ARM_AM::getAM3Offset(MI.getOperand(ImmIdx).getImm()); 13536495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (ARM_AM::getAM3Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub) 13546495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng InstrOffs *= -1; 13556495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng NumBits = 8; 13566495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng break; 13576495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 1358baf31088f1472f48ea5ae81f0b93636cc44ca444Anton Korobeynikov case ARMII::AddrMode4: 1359a44321776ecd96fa0344335d3027758be3386e45Jim Grosbach case ARMII::AddrMode6: 1360cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng // Can't fold any offset even if it's zero. 1361cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng return false; 13626495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng case ARMII::AddrMode5: { 13636495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ImmIdx = FrameRegIdx+1; 13646495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng InstrOffs = ARM_AM::getAM5Offset(MI.getOperand(ImmIdx).getImm()); 13656495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (ARM_AM::getAM5Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub) 13666495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng InstrOffs *= -1; 13676495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng NumBits = 8; 13686495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng Scale = 4; 13696495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng break; 13706495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 13716495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng default: 13726495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng llvm_unreachable("Unsupported addressing mode!"); 13736495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng break; 13746495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 13756495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 13766495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng Offset += InstrOffs * Scale; 13776495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!"); 13786495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (Offset < 0) { 13796495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng Offset = -Offset; 13806495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng isSub = true; 13816495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 13826495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 13836495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Attempt to fold address comp. if opcode has offset bits 13846495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (NumBits > 0) { 13856495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Common case: small offset, fits into instruction. 13866495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MachineOperand &ImmOp = MI.getOperand(ImmIdx); 13876495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng int ImmedOffset = Offset / Scale; 13886495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned Mask = (1 << NumBits) - 1; 13896495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if ((unsigned)Offset <= Mask * Scale) { 13906495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Replace the FrameIndex with sp 13916495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false); 13926495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (isSub) 13936495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ImmedOffset |= 1 << NumBits; 13946495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ImmOp.ChangeToImmediate(ImmedOffset); 1395cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng Offset = 0; 1396cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng return true; 13976495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 1398764ab52dd80310a205c9888bf166d09dab858f90Jim Grosbach 13996495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Otherwise, it didn't fit. Pull in what we can to simplify the immed. 14006495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ImmedOffset = ImmedOffset & Mask; 14016495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (isSub) 14026495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ImmedOffset |= 1 << NumBits; 14036495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ImmOp.ChangeToImmediate(ImmedOffset); 14046495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng Offset &= ~(Mask*Scale); 14056495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 14066495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 14076495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 1408cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng Offset = (isSub) ? -Offset : Offset; 1409cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng return Offset == 0; 14106495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng} 1411e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling 1412e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendlingbool ARMBaseInstrInfo:: 1413a99c3e9acd95f5fbfb611e3f807240cd74001142Eric ChristopherAnalyzeCompare(const MachineInstr *MI, unsigned &SrcReg, int &CmpMask, 1414a99c3e9acd95f5fbfb611e3f807240cd74001142Eric Christopher int &CmpValue) const { 1415e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling switch (MI->getOpcode()) { 1416e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling default: break; 141738ae997e63e3e1bb2c8679e01ea74cf8fd0be893Bill Wendling case ARM::CMPri: 141838ae997e63e3e1bb2c8679e01ea74cf8fd0be893Bill Wendling case ARM::CMPzri: 1419e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling case ARM::t2CMPri: 1420e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling case ARM::t2CMPzri: 1421e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling SrcReg = MI->getOperand(0).getReg(); 142204ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif CmpMask = ~0; 1423e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling CmpValue = MI->getOperand(1).getImm(); 1424e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling return true; 142504ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif case ARM::TSTri: 142604ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif case ARM::t2TSTri: 142704ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif SrcReg = MI->getOperand(0).getReg(); 142804ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif CmpMask = MI->getOperand(1).getImm(); 142904ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif CmpValue = 0; 143004ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif return true; 143104ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif } 143204ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif 143304ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif return false; 143404ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif} 143504ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif 143605642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif/// isSuitableForMask - Identify a suitable 'and' instruction that 143705642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif/// operates on the given source register and applies the same mask 143805642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif/// as a 'tst' instruction. Provide a limited look-through for copies. 143905642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif/// When successful, MI will hold the found instruction. 144005642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greifstatic bool isSuitableForMask(MachineInstr *&MI, unsigned SrcReg, 14418ff9bb189ce188452e6cae6ed65cb2745814126cGabor Greif int CmpMask, bool CommonUse) { 144205642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif switch (MI->getOpcode()) { 144304ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif case ARM::ANDri: 144404ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif case ARM::t2ANDri: 144505642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif if (CmpMask != MI->getOperand(2).getImm()) 14468ff9bb189ce188452e6cae6ed65cb2745814126cGabor Greif return false; 144705642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif if (SrcReg == MI->getOperand(CommonUse ? 1 : 0).getReg()) 144804ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif return true; 144904ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif break; 145005642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif case ARM::COPY: { 145105642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif // Walk down one instruction which is potentially an 'and'. 145205642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif const MachineInstr &Copy = *MI; 145305642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif MachineBasicBlock::iterator AND(next(MachineBasicBlock::iterator(MI))); 145405642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif if (AND == MI->getParent()->end()) return false; 145505642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif MI = AND; 145605642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif return isSuitableForMask(MI, Copy.getOperand(0).getReg(), 145705642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif CmpMask, true); 145805642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif } 1459e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling } 1460e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling 1461e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling return false; 1462e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling} 1463e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling 1464a65568676d0d9d53dd4aae8f1c58271bb4cfff10Bill Wendling/// OptimizeCompareInstr - Convert the instruction supplying the argument to the 146592ad57f066e9f256e4e3d72febf152e68caa80c7Bill Wendling/// comparison into one that sets the zero bit in the flags register. Update the 146692ad57f066e9f256e4e3d72febf152e68caa80c7Bill Wendling/// iterator *only* if a transformation took place. 1467e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendlingbool ARMBaseInstrInfo:: 146804ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor GreifOptimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, int CmpMask, 146904ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif int CmpValue, MachineBasicBlock::iterator &MII) const { 14703665661a5708c8adc2727be38b56d1d87ddeb661Bill Wendling if (CmpValue != 0) 147192ad57f066e9f256e4e3d72febf152e68caa80c7Bill Wendling return false; 147292ad57f066e9f256e4e3d72febf152e68caa80c7Bill Wendling 147392ad57f066e9f256e4e3d72febf152e68caa80c7Bill Wendling MachineRegisterInfo &MRI = CmpInstr->getParent()->getParent()->getRegInfo(); 147492ad57f066e9f256e4e3d72febf152e68caa80c7Bill Wendling MachineRegisterInfo::def_iterator DI = MRI.def_begin(SrcReg); 147592ad57f066e9f256e4e3d72febf152e68caa80c7Bill Wendling if (llvm::next(DI) != MRI.def_end()) 147692ad57f066e9f256e4e3d72febf152e68caa80c7Bill Wendling // Only support one definition. 147792ad57f066e9f256e4e3d72febf152e68caa80c7Bill Wendling return false; 147892ad57f066e9f256e4e3d72febf152e68caa80c7Bill Wendling 147992ad57f066e9f256e4e3d72febf152e68caa80c7Bill Wendling MachineInstr *MI = &*DI; 148092ad57f066e9f256e4e3d72febf152e68caa80c7Bill Wendling 148104ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif // Masked compares sometimes use the same register as the corresponding 'and'. 148204ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif if (CmpMask != ~0) { 148305642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif if (!isSuitableForMask(MI, SrcReg, CmpMask, false)) { 148404ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif MI = 0; 148504ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif for (MachineRegisterInfo::use_iterator UI = MRI.use_begin(SrcReg), 148604ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif UE = MRI.use_end(); UI != UE; ++UI) { 148704ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif if (UI->getParent() != CmpInstr->getParent()) continue; 148805642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif MachineInstr *PotentialAND = &*UI; 14898ff9bb189ce188452e6cae6ed65cb2745814126cGabor Greif if (!isSuitableForMask(PotentialAND, SrcReg, CmpMask, true)) 149004ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif continue; 149105642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif MI = PotentialAND; 149204ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif break; 149304ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif } 149404ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif if (!MI) return false; 149504ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif } 149604ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif } 149704ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif 1498e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling // Conservatively refuse to convert an instruction which isn't in the same BB 1499e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling // as the comparison. 1500e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling if (MI->getParent() != CmpInstr->getParent()) 1501e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling return false; 1502e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling 1503e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling // Check that CPSR isn't set between the comparison instruction and the one we 1504e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling // want to change. 1505691e64a54ce899409abe7c131d15ed75e3c1fef5Evan Cheng MachineBasicBlock::const_iterator I = CmpInstr, E = MI, 1506691e64a54ce899409abe7c131d15ed75e3c1fef5Evan Cheng B = MI->getParent()->begin(); 1507e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling --I; 1508e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling for (; I != E; --I) { 1509e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling const MachineInstr &Instr = *I; 1510e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling 1511e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling for (unsigned IO = 0, EO = Instr.getNumOperands(); IO != EO; ++IO) { 1512e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling const MachineOperand &MO = Instr.getOperand(IO); 151375486dbf4e9611f2070bf13b874f78a5587ed7ffBill Wendling if (!MO.isReg() || !MO.isDef()) continue; 1514e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling 1515e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling // This instruction modifies CPSR before the one we want to change. We 1516e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling // can't do this transformation. 1517e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling if (MO.getReg() == ARM::CPSR) 1518e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling return false; 1519e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling } 1520691e64a54ce899409abe7c131d15ed75e3c1fef5Evan Cheng 1521691e64a54ce899409abe7c131d15ed75e3c1fef5Evan Cheng if (I == B) 1522691e64a54ce899409abe7c131d15ed75e3c1fef5Evan Cheng // The 'and' is below the comparison instruction. 1523691e64a54ce899409abe7c131d15ed75e3c1fef5Evan Cheng return false; 1524e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling } 1525e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling 1526e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling // Set the "zero" bit in CPSR. 1527e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling switch (MI->getOpcode()) { 1528e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling default: break; 152938ae997e63e3e1bb2c8679e01ea74cf8fd0be893Bill Wendling case ARM::ADDri: 15303a951829fef6a2cfca87611e94cf48e0136f81d5Bob Wilson case ARM::ANDri: 15313a951829fef6a2cfca87611e94cf48e0136f81d5Bob Wilson case ARM::t2ANDri: 153238ae997e63e3e1bb2c8679e01ea74cf8fd0be893Bill Wendling case ARM::SUBri: 153338ae997e63e3e1bb2c8679e01ea74cf8fd0be893Bill Wendling case ARM::t2ADDri: 1534ad422718f9b3224234f52e84d28d8a57a4e89987Bill Wendling case ARM::t2SUBri: 1535e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling MI->RemoveOperand(5); 1536ad422718f9b3224234f52e84d28d8a57a4e89987Bill Wendling MachineInstrBuilder(MI) 1537ad422718f9b3224234f52e84d28d8a57a4e89987Bill Wendling .addReg(ARM::CPSR, RegState::Define | RegState::Implicit); 1538220e240bdf3235252c2a1fc8fcc5d4b8e8117918Bill Wendling MII = llvm::next(MachineBasicBlock::iterator(CmpInstr)); 1539e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling CmpInstr->eraseFromParent(); 1540e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling return true; 1541e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling } 1542e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling 1543e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling return false; 1544e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling} 15455f54ce347368105260be2cec497b6a4199dc5789Evan Cheng 15465f54ce347368105260be2cec497b6a4199dc5789Evan Chengunsigned 15475f54ce347368105260be2cec497b6a4199dc5789Evan ChengARMBaseInstrInfo::getNumMicroOps(const MachineInstr *MI, 15483ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng const InstrItineraryData *ItinData) const { 15493ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng if (!ItinData || ItinData->isEmpty()) 15505f54ce347368105260be2cec497b6a4199dc5789Evan Cheng return 1; 15515f54ce347368105260be2cec497b6a4199dc5789Evan Cheng 15525f54ce347368105260be2cec497b6a4199dc5789Evan Cheng const TargetInstrDesc &Desc = MI->getDesc(); 15535f54ce347368105260be2cec497b6a4199dc5789Evan Cheng unsigned Class = Desc.getSchedClass(); 1554064312de8641043b084603aa9a6b409bc794eed2Bob Wilson unsigned UOps = ItinData->Itineraries[Class].NumMicroOps; 15555f54ce347368105260be2cec497b6a4199dc5789Evan Cheng if (UOps) 15565f54ce347368105260be2cec497b6a4199dc5789Evan Cheng return UOps; 15575f54ce347368105260be2cec497b6a4199dc5789Evan Cheng 15585f54ce347368105260be2cec497b6a4199dc5789Evan Cheng unsigned Opc = MI->getOpcode(); 15595f54ce347368105260be2cec497b6a4199dc5789Evan Cheng switch (Opc) { 15605f54ce347368105260be2cec497b6a4199dc5789Evan Cheng default: 15615f54ce347368105260be2cec497b6a4199dc5789Evan Cheng llvm_unreachable("Unexpected multi-uops instruction!"); 15625f54ce347368105260be2cec497b6a4199dc5789Evan Cheng break; 15633ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng case ARM::VLDMQ: 15645f54ce347368105260be2cec497b6a4199dc5789Evan Cheng case ARM::VSTMQ: 15655f54ce347368105260be2cec497b6a4199dc5789Evan Cheng return 2; 15665f54ce347368105260be2cec497b6a4199dc5789Evan Cheng 15675f54ce347368105260be2cec497b6a4199dc5789Evan Cheng // The number of uOps for load / store multiple are determined by the number 15685f54ce347368105260be2cec497b6a4199dc5789Evan Cheng // registers. 15693ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng // On Cortex-A8, each pair of register loads / stores can be scheduled on the 15703ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng // same cycle. The scheduling for the first load / store must be done 15713ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng // separately by assuming the the address is not 64-bit aligned. 15723ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng // On Cortex-A9, the formula is simply (#reg / 2) + (#reg % 2). If the address 15733ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng // is not 64-bit aligned, then AGU would take an extra cycle. 15743ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng // For VFP / NEON load / store multiple, the formula is 15755f54ce347368105260be2cec497b6a4199dc5789Evan Cheng // (#reg / 2) + (#reg % 2) + 1. 15765f54ce347368105260be2cec497b6a4199dc5789Evan Cheng case ARM::VLDMD: 15775f54ce347368105260be2cec497b6a4199dc5789Evan Cheng case ARM::VLDMS: 15785f54ce347368105260be2cec497b6a4199dc5789Evan Cheng case ARM::VLDMD_UPD: 15795f54ce347368105260be2cec497b6a4199dc5789Evan Cheng case ARM::VLDMS_UPD: 15805f54ce347368105260be2cec497b6a4199dc5789Evan Cheng case ARM::VSTMD: 15815f54ce347368105260be2cec497b6a4199dc5789Evan Cheng case ARM::VSTMS: 15825f54ce347368105260be2cec497b6a4199dc5789Evan Cheng case ARM::VSTMD_UPD: 15835f54ce347368105260be2cec497b6a4199dc5789Evan Cheng case ARM::VSTMS_UPD: { 15845f54ce347368105260be2cec497b6a4199dc5789Evan Cheng unsigned NumRegs = MI->getNumOperands() - Desc.getNumOperands(); 15855f54ce347368105260be2cec497b6a4199dc5789Evan Cheng return (NumRegs / 2) + (NumRegs % 2) + 1; 15865f54ce347368105260be2cec497b6a4199dc5789Evan Cheng } 15875f54ce347368105260be2cec497b6a4199dc5789Evan Cheng case ARM::LDM_RET: 15885f54ce347368105260be2cec497b6a4199dc5789Evan Cheng case ARM::LDM: 15895f54ce347368105260be2cec497b6a4199dc5789Evan Cheng case ARM::LDM_UPD: 15905f54ce347368105260be2cec497b6a4199dc5789Evan Cheng case ARM::STM: 15915f54ce347368105260be2cec497b6a4199dc5789Evan Cheng case ARM::STM_UPD: 15925f54ce347368105260be2cec497b6a4199dc5789Evan Cheng case ARM::tLDM: 15935f54ce347368105260be2cec497b6a4199dc5789Evan Cheng case ARM::tLDM_UPD: 15945f54ce347368105260be2cec497b6a4199dc5789Evan Cheng case ARM::tSTM_UPD: 15955f54ce347368105260be2cec497b6a4199dc5789Evan Cheng case ARM::tPOP_RET: 15965f54ce347368105260be2cec497b6a4199dc5789Evan Cheng case ARM::tPOP: 15975f54ce347368105260be2cec497b6a4199dc5789Evan Cheng case ARM::tPUSH: 15985f54ce347368105260be2cec497b6a4199dc5789Evan Cheng case ARM::t2LDM_RET: 15995f54ce347368105260be2cec497b6a4199dc5789Evan Cheng case ARM::t2LDM: 16005f54ce347368105260be2cec497b6a4199dc5789Evan Cheng case ARM::t2LDM_UPD: 16015f54ce347368105260be2cec497b6a4199dc5789Evan Cheng case ARM::t2STM: 16025f54ce347368105260be2cec497b6a4199dc5789Evan Cheng case ARM::t2STM_UPD: { 16033ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng unsigned NumRegs = MI->getNumOperands() - Desc.getNumOperands() + 1; 16043ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng if (Subtarget.isCortexA8()) { 16053ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng // 4 registers would be issued: 1, 2, 1. 16063ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng // 5 registers would be issued: 1, 2, 2. 16073ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng return 1 + (NumRegs / 2); 16083ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng } else if (Subtarget.isCortexA9()) { 16093ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng UOps = (NumRegs / 2); 16103ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng // If there are odd number of registers or if it's not 64-bit aligned, 16113ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng // then it takes an extra AGU (Address Generation Unit) cycle. 16123ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng if ((NumRegs % 2) || 16133ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng !MI->hasOneMemOperand() || 16143ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng (*MI->memoperands_begin())->getAlignment() < 8) 16153ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng ++UOps; 16163ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng return UOps; 16173ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng } else { 16183ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng // Assume the worst. 16193ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng return NumRegs; 16203ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng } 16215f54ce347368105260be2cec497b6a4199dc5789Evan Cheng } 16225f54ce347368105260be2cec497b6a4199dc5789Evan Cheng } 16235f54ce347368105260be2cec497b6a4199dc5789Evan Cheng} 1624