ARMBaseInstrInfo.cpp revision 0cb11ac32fc09c5db42fb801db242ac9fb51f6b1
131c24bf5b39cc8391d4cfdbf8cf5163975fdb81eJim Grosbach//===- ARMBaseInstrInfo.cpp - ARM Instruction Information -------*- C++ -*-===// 2334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// 3334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// The LLVM Compiler Infrastructure 4334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// 5334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// This file is distributed under the University of Illinois Open Source 6334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// License. See LICENSE.TXT for details. 7334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// 8334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin//===----------------------------------------------------------------------===// 9334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// 10334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// This file contains the Base ARM implementation of the TargetInstrInfo class. 11334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// 12334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin//===----------------------------------------------------------------------===// 13334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 14334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "ARMBaseInstrInfo.h" 15334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "ARM.h" 16334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "ARMAddressingModes.h" 17d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng#include "ARMConstantPoolValue.h" 1848575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng#include "ARMHazardRecognizer.h" 19334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "ARMMachineFunctionInfo.h" 20f95215f551949d5e5adfbf4753aa833b9009b77aAnton Korobeynikov#include "ARMRegisterInfo.h" 214dbbe3433f7339ed277af55037ff6847f484e5abChris Lattner#include "ARMGenInstrInfo.inc" 22fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng#include "llvm/Constants.h" 23fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng#include "llvm/Function.h" 24fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng#include "llvm/GlobalValue.h" 25334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "llvm/CodeGen/LiveVariables.h" 26d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng#include "llvm/CodeGen/MachineConstantPool.h" 27334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "llvm/CodeGen/MachineFrameInfo.h" 28334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "llvm/CodeGen/MachineInstrBuilder.h" 29334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "llvm/CodeGen/MachineJumpTableInfo.h" 30249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov#include "llvm/CodeGen/MachineMemOperand.h" 312457f2c66184e978d4ed8fa9e2128effff26cb0bEvan Cheng#include "llvm/CodeGen/MachineRegisterInfo.h" 32249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov#include "llvm/CodeGen/PseudoSourceValue.h" 33af76e592c7f9deff0e55c13dbb4a34f07f1c7f64Chris Lattner#include "llvm/MC/MCAsmInfo.h" 34334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "llvm/Support/CommandLine.h" 35f95215f551949d5e5adfbf4753aa833b9009b77aAnton Korobeynikov#include "llvm/Support/Debug.h" 36c25e7581b9b8088910da31702d4ca21c4734c6d7Torok Edwin#include "llvm/Support/ErrorHandling.h" 3740a5eb18b031fa1a5e9697e21e251e613d441cc5Bill Wendling#include "llvm/ADT/STLExtras.h" 38334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinusing namespace llvm; 39334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 40334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinstatic cl::opt<bool> 41334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinEnableARM3Addr("enable-arm-3-addr-conv", cl::Hidden, 42334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin cl::desc("Enable ARM 2-addr to 3-addr conv")); 43334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 4448575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng/// ARM_MLxEntry - Record information about MLA / MLS instructions. 4548575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Chengstruct ARM_MLxEntry { 4648575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng unsigned MLxOpc; // MLA / MLS opcode 4748575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng unsigned MulOpc; // Expanded multiplication opcode 4848575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng unsigned AddSubOpc; // Expanded add / sub opcode 4948575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng bool NegAcc; // True if the acc is negated before the add / sub. 5048575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng bool HasLane; // True if instruction has an extra "lane" operand. 5148575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng}; 5248575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng 5348575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Chengstatic const ARM_MLxEntry ARM_MLxTable[] = { 5448575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng // MLxOpc, MulOpc, AddSubOpc, NegAcc, HasLane 5548575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng // fp scalar ops 5648575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng { ARM::VMLAS, ARM::VMULS, ARM::VADDS, false, false }, 5748575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng { ARM::VMLSS, ARM::VMULS, ARM::VSUBS, false, false }, 5848575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng { ARM::VMLAD, ARM::VMULD, ARM::VADDD, false, false }, 5948575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng { ARM::VMLSD, ARM::VMULD, ARM::VSUBD, false, false }, 6048575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng { ARM::VNMLAS, ARM::VNMULS, ARM::VSUBS, true, false }, 6148575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng { ARM::VNMLSS, ARM::VMULS, ARM::VSUBS, true, false }, 6248575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng { ARM::VNMLAD, ARM::VNMULD, ARM::VSUBD, true, false }, 6348575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng { ARM::VNMLSD, ARM::VMULD, ARM::VSUBD, true, false }, 6448575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng 6548575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng // fp SIMD ops 6648575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng { ARM::VMLAfd, ARM::VMULfd, ARM::VADDfd, false, false }, 6748575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng { ARM::VMLSfd, ARM::VMULfd, ARM::VSUBfd, false, false }, 6848575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng { ARM::VMLAfq, ARM::VMULfq, ARM::VADDfq, false, false }, 6948575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng { ARM::VMLSfq, ARM::VMULfq, ARM::VSUBfq, false, false }, 7048575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng { ARM::VMLAslfd, ARM::VMULslfd, ARM::VADDfd, false, true }, 7148575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng { ARM::VMLSslfd, ARM::VMULslfd, ARM::VSUBfd, false, true }, 7248575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng { ARM::VMLAslfq, ARM::VMULslfq, ARM::VADDfq, false, true }, 7348575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng { ARM::VMLSslfq, ARM::VMULslfq, ARM::VSUBfq, false, true }, 7448575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng}; 7548575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng 76f95215f551949d5e5adfbf4753aa833b9009b77aAnton KorobeynikovARMBaseInstrInfo::ARMBaseInstrInfo(const ARMSubtarget& STI) 77f95215f551949d5e5adfbf4753aa833b9009b77aAnton Korobeynikov : TargetInstrInfoImpl(ARMInsts, array_lengthof(ARMInsts)), 78f95215f551949d5e5adfbf4753aa833b9009b77aAnton Korobeynikov Subtarget(STI) { 7948575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng for (unsigned i = 0, e = array_lengthof(ARM_MLxTable); i != e; ++i) { 8048575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng if (!MLxEntryMap.insert(std::make_pair(ARM_MLxTable[i].MLxOpc, i)).second) 8148575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng assert(false && "Duplicated entries?"); 8248575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng MLxHazardOpcodes.insert(ARM_MLxTable[i].AddSubOpc); 8348575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng MLxHazardOpcodes.insert(ARM_MLxTable[i].MulOpc); 8448575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng } 8548575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng} 8648575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng 872da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick// Use a ScoreboardHazardRecognizer for prepass ARM scheduling. TargetInstrImpl 882da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick// currently defaults to no prepass hazard recognizer. 8948575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan ChengScheduleHazardRecognizer *ARMBaseInstrInfo:: 902da8bc8a5f7705ac131184cd247f48500da0d74eAndrew TrickCreateTargetHazardRecognizer(const TargetMachine *TM, 912da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick const ScheduleDAG *DAG) const { 92c8bfd1d78ff9a307d1d4cb57cce4549b538e60f4Andrew Trick if (usePreRAHazardRecognizer()) { 932da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick const InstrItineraryData *II = TM->getInstrItineraryData(); 942da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick return new ScoreboardHazardRecognizer(II, DAG, "pre-RA-sched"); 952da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick } 962da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick return TargetInstrInfoImpl::CreateTargetHazardRecognizer(TM, DAG); 972da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick} 982da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick 992da8bc8a5f7705ac131184cd247f48500da0d74eAndrew TrickScheduleHazardRecognizer *ARMBaseInstrInfo:: 1002da8bc8a5f7705ac131184cd247f48500da0d74eAndrew TrickCreateTargetPostRAHazardRecognizer(const InstrItineraryData *II, 1012da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick const ScheduleDAG *DAG) const { 10248575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng if (Subtarget.isThumb2() || Subtarget.hasVFP2()) 10348575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng return (ScheduleHazardRecognizer *) 1042da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick new ARMHazardRecognizer(II, *this, getRegisterInfo(), Subtarget, DAG); 1052da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick return TargetInstrInfoImpl::CreateTargetPostRAHazardRecognizer(II, DAG); 106334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 107334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 108334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinMachineInstr * 109334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinARMBaseInstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI, 110334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineBasicBlock::iterator &MBBI, 111334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin LiveVariables *LV) const { 11278703ddafe3d037f75d8ca188e4829d238289ac3Evan Cheng // FIXME: Thumb2 support. 11378703ddafe3d037f75d8ca188e4829d238289ac3Evan Cheng 114334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (!EnableARM3Addr) 115334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return NULL; 116334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 117334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineInstr *MI = MBBI; 118334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineFunction &MF = *MI->getParent()->getParent(); 11999405df044f2c584242e711cc9023ec90356da82Bruno Cardoso Lopes uint64_t TSFlags = MI->getDesc().TSFlags; 120334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool isPre = false; 121334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin switch ((TSFlags & ARMII::IndexModeMask) >> ARMII::IndexModeShift) { 122334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin default: return NULL; 123334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMII::IndexModePre: 124334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin isPre = true; 125334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin break; 126334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMII::IndexModePost: 127334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin break; 128334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 129334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 130334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Try splitting an indexed load/store to an un-indexed one plus an add/sub 131334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // operation. 132334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned MemOpc = getUnindexedOpcode(MI->getOpcode()); 133334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (MemOpc == 0) 134334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return NULL; 135334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 136334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineInstr *UpdateMI = NULL; 137334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineInstr *MemMI = NULL; 138334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned AddrMode = (TSFlags & ARMII::AddrModeMask); 139334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const TargetInstrDesc &TID = MI->getDesc(); 140334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned NumOps = TID.getNumOperands(); 141334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool isLoad = !TID.mayStore(); 142334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const MachineOperand &WB = isLoad ? MI->getOperand(1) : MI->getOperand(0); 143334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const MachineOperand &Base = MI->getOperand(2); 144334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const MachineOperand &Offset = MI->getOperand(NumOps-3); 145334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned WBReg = WB.getReg(); 146334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned BaseReg = Base.getReg(); 147334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned OffReg = Offset.getReg(); 148334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned OffImm = MI->getOperand(NumOps-2).getImm(); 149334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin ARMCC::CondCodes Pred = (ARMCC::CondCodes)MI->getOperand(NumOps-1).getImm(); 150334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin switch (AddrMode) { 151334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin default: 152334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin assert(false && "Unknown indexed op!"); 153334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return NULL; 154334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMII::AddrMode2: { 155334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool isSub = ARM_AM::getAM2Op(OffImm) == ARM_AM::sub; 156334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned Amt = ARM_AM::getAM2Offset(OffImm); 157334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (OffReg == 0) { 158e7cbe4118b7ddf05032ff8772a98c51e1637bb5cEvan Cheng if (ARM_AM::getSOImmVal(Amt) == -1) 159334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Can't encode it in a so_imm operand. This transformation will 160334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // add more than 1 instruction. Abandon! 161334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return NULL; 162334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin UpdateMI = BuildMI(MF, MI->getDebugLoc(), 16378703ddafe3d037f75d8ca188e4829d238289ac3Evan Cheng get(isSub ? ARM::SUBri : ARM::ADDri), WBReg) 164e7cbe4118b7ddf05032ff8772a98c51e1637bb5cEvan Cheng .addReg(BaseReg).addImm(Amt) 165334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addImm(Pred).addReg(0).addReg(0); 166334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } else if (Amt != 0) { 167334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin ARM_AM::ShiftOpc ShOpc = ARM_AM::getAM2ShiftOpc(OffImm); 168334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned SOOpc = ARM_AM::getSORegOpc(ShOpc, Amt); 169334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin UpdateMI = BuildMI(MF, MI->getDebugLoc(), 17078703ddafe3d037f75d8ca188e4829d238289ac3Evan Cheng get(isSub ? ARM::SUBrs : ARM::ADDrs), WBReg) 171334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(BaseReg).addReg(OffReg).addReg(0).addImm(SOOpc) 172334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addImm(Pred).addReg(0).addReg(0); 173334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } else 174334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin UpdateMI = BuildMI(MF, MI->getDebugLoc(), 17578703ddafe3d037f75d8ca188e4829d238289ac3Evan Cheng get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg) 176334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(BaseReg).addReg(OffReg) 177334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addImm(Pred).addReg(0).addReg(0); 178334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin break; 179334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 180334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMII::AddrMode3 : { 181334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool isSub = ARM_AM::getAM3Op(OffImm) == ARM_AM::sub; 182334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned Amt = ARM_AM::getAM3Offset(OffImm); 183334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (OffReg == 0) 184334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Immediate is 8-bits. It's guaranteed to fit in a so_imm operand. 185334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin UpdateMI = BuildMI(MF, MI->getDebugLoc(), 18678703ddafe3d037f75d8ca188e4829d238289ac3Evan Cheng get(isSub ? ARM::SUBri : ARM::ADDri), WBReg) 187334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(BaseReg).addImm(Amt) 188334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addImm(Pred).addReg(0).addReg(0); 189334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin else 190334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin UpdateMI = BuildMI(MF, MI->getDebugLoc(), 19178703ddafe3d037f75d8ca188e4829d238289ac3Evan Cheng get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg) 192334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(BaseReg).addReg(OffReg) 193334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addImm(Pred).addReg(0).addReg(0); 194334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin break; 195334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 196334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 197334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 198334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin std::vector<MachineInstr*> NewMIs; 199334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (isPre) { 200334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (isLoad) 201334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MemMI = BuildMI(MF, MI->getDebugLoc(), 202334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin get(MemOpc), MI->getOperand(0).getReg()) 2033e5561247202bae994dd259a2d8dc4eff8f799f3Jim Grosbach .addReg(WBReg).addImm(0).addImm(Pred); 204334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin else 205334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MemMI = BuildMI(MF, MI->getDebugLoc(), 206334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin get(MemOpc)).addReg(MI->getOperand(1).getReg()) 207334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(WBReg).addReg(0).addImm(0).addImm(Pred); 208334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin NewMIs.push_back(MemMI); 209334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin NewMIs.push_back(UpdateMI); 210334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } else { 211334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (isLoad) 212334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MemMI = BuildMI(MF, MI->getDebugLoc(), 213334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin get(MemOpc), MI->getOperand(0).getReg()) 2143e5561247202bae994dd259a2d8dc4eff8f799f3Jim Grosbach .addReg(BaseReg).addImm(0).addImm(Pred); 215334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin else 216334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MemMI = BuildMI(MF, MI->getDebugLoc(), 217334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin get(MemOpc)).addReg(MI->getOperand(1).getReg()) 218334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred); 219334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (WB.isDead()) 220334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin UpdateMI->getOperand(0).setIsDead(); 221334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin NewMIs.push_back(UpdateMI); 222334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin NewMIs.push_back(MemMI); 223334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 224334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 225334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Transfer LiveVariables states, kill / dead info. 226334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (LV) { 227334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 228334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineOperand &MO = MI->getOperand(i); 229c9df025e33ac435adb3b3318d237c36ca7cec659Jakob Stoklund Olesen if (MO.isReg() && TargetRegisterInfo::isVirtualRegister(MO.getReg())) { 230334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned Reg = MO.getReg(); 231334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 232334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin LiveVariables::VarInfo &VI = LV->getVarInfo(Reg); 233334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (MO.isDef()) { 234334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineInstr *NewMI = (Reg == WBReg) ? UpdateMI : MemMI; 235334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (MO.isDead()) 236334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin LV->addVirtualRegisterDead(Reg, NewMI); 237334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 238334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (MO.isUse() && MO.isKill()) { 239334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin for (unsigned j = 0; j < 2; ++j) { 240334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Look at the two new MI's in reverse order. 241334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineInstr *NewMI = NewMIs[j]; 242334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (!NewMI->readsRegister(Reg)) 243334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin continue; 244334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin LV->addVirtualRegisterKilled(Reg, NewMI); 245334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (VI.removeKill(MI)) 246334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin VI.Kills.push_back(NewMI); 247334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin break; 248334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 249334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 250334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 251334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 252334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 253334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 254334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MFI->insert(MBBI, NewMIs[1]); 255334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MFI->insert(MBBI, NewMIs[0]); 256334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return NewMIs[0]; 257334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 258334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 259334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// Branch analysis. 260334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinbool 261334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinARMBaseInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB, 262334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineBasicBlock *&FBB, 263334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin SmallVectorImpl<MachineOperand> &Cond, 264334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool AllowModify) const { 265334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // If the block has no terminators, it just falls into the block after it. 266334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineBasicBlock::iterator I = MBB.end(); 26793d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen if (I == MBB.begin()) 26893d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen return false; 26993d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen --I; 27093d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen while (I->isDebugValue()) { 27193d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen if (I == MBB.begin()) 27293d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen return false; 27393d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen --I; 27493d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen } 27593d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen if (!isUnpredicatedTerminator(I)) 276334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 277334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 278334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Get the last instruction in the block. 279334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineInstr *LastInst = I; 280334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 281334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // If there is only one terminator instruction, process it. 282334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned LastOpc = LastInst->getOpcode(); 283334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) { 2845ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng if (isUncondBranchOpcode(LastOpc)) { 285334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin TBB = LastInst->getOperand(0).getMBB(); 286334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 287334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 2885ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng if (isCondBranchOpcode(LastOpc)) { 289334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Block ends with fall-through condbranch. 290334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin TBB = LastInst->getOperand(0).getMBB(); 291334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin Cond.push_back(LastInst->getOperand(1)); 292334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin Cond.push_back(LastInst->getOperand(2)); 293334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 294334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 295334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; // Can't handle indirect branch. 296334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 297334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 298334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Get the instruction before it if it is a terminator. 299334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineInstr *SecondLastInst = I; 300108c8724663354050dc09bb1262c3e4511adf82fEvan Cheng unsigned SecondLastOpc = SecondLastInst->getOpcode(); 301108c8724663354050dc09bb1262c3e4511adf82fEvan Cheng 302108c8724663354050dc09bb1262c3e4511adf82fEvan Cheng // If AllowModify is true and the block ends with two or more unconditional 303108c8724663354050dc09bb1262c3e4511adf82fEvan Cheng // branches, delete all but the first unconditional branch. 304108c8724663354050dc09bb1262c3e4511adf82fEvan Cheng if (AllowModify && isUncondBranchOpcode(LastOpc)) { 305108c8724663354050dc09bb1262c3e4511adf82fEvan Cheng while (isUncondBranchOpcode(SecondLastOpc)) { 306108c8724663354050dc09bb1262c3e4511adf82fEvan Cheng LastInst->eraseFromParent(); 307108c8724663354050dc09bb1262c3e4511adf82fEvan Cheng LastInst = SecondLastInst; 308108c8724663354050dc09bb1262c3e4511adf82fEvan Cheng LastOpc = LastInst->getOpcode(); 309676e258366dd17a0b4ee6ac66914237ce181202eEvan Cheng if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) { 310676e258366dd17a0b4ee6ac66914237ce181202eEvan Cheng // Return now the only terminator is an unconditional branch. 311676e258366dd17a0b4ee6ac66914237ce181202eEvan Cheng TBB = LastInst->getOperand(0).getMBB(); 312676e258366dd17a0b4ee6ac66914237ce181202eEvan Cheng return false; 313676e258366dd17a0b4ee6ac66914237ce181202eEvan Cheng } else { 314108c8724663354050dc09bb1262c3e4511adf82fEvan Cheng SecondLastInst = I; 315108c8724663354050dc09bb1262c3e4511adf82fEvan Cheng SecondLastOpc = SecondLastInst->getOpcode(); 316108c8724663354050dc09bb1262c3e4511adf82fEvan Cheng } 317108c8724663354050dc09bb1262c3e4511adf82fEvan Cheng } 318108c8724663354050dc09bb1262c3e4511adf82fEvan Cheng } 319334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 320334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // If there are three terminators, we don't know what sort of block this is. 321334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(--I)) 322334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; 323334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 3245ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng // If the block ends with a B and a Bcc, handle it. 3255ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng if (isCondBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) { 326334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin TBB = SecondLastInst->getOperand(0).getMBB(); 327334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin Cond.push_back(SecondLastInst->getOperand(1)); 328334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin Cond.push_back(SecondLastInst->getOperand(2)); 329334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin FBB = LastInst->getOperand(0).getMBB(); 330334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 331334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 332334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 333334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // If the block ends with two unconditional branches, handle it. The second 334334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // one is not executed, so remove it. 3355ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng if (isUncondBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) { 336334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin TBB = SecondLastInst->getOperand(0).getMBB(); 337334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin I = LastInst; 338334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (AllowModify) 339334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin I->eraseFromParent(); 340334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 341334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 342334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 343334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // ...likewise if it ends with a branch table followed by an unconditional 344334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // branch. The branch folder can create these, and we must get rid of them for 345334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // correctness of Thumb constant islands. 3468d4de5abfa1bcd974554ea14904ebf7af289e84dBob Wilson if ((isJumpTableBranchOpcode(SecondLastOpc) || 3478d4de5abfa1bcd974554ea14904ebf7af289e84dBob Wilson isIndirectBranchOpcode(SecondLastOpc)) && 3485ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng isUncondBranchOpcode(LastOpc)) { 349334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin I = LastInst; 350334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (AllowModify) 351334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin I->eraseFromParent(); 352334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; 353334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 354334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 355334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Otherwise, can't handle this. 356334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; 357334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 358334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 359334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 360334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinunsigned ARMBaseInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const { 361334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineBasicBlock::iterator I = MBB.end(); 362334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (I == MBB.begin()) return 0; 363334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin --I; 36493d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen while (I->isDebugValue()) { 36593d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen if (I == MBB.begin()) 36693d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen return 0; 36793d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen --I; 36893d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen } 3695ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng if (!isUncondBranchOpcode(I->getOpcode()) && 3705ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng !isCondBranchOpcode(I->getOpcode())) 371334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 0; 372334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 373334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Remove the branch. 374334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin I->eraseFromParent(); 375334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 376334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin I = MBB.end(); 377334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 378334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (I == MBB.begin()) return 1; 379334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin --I; 3805ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng if (!isCondBranchOpcode(I->getOpcode())) 381334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 1; 382334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 383334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Remove the branch. 384334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin I->eraseFromParent(); 385334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 2; 386334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 387334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 388334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinunsigned 389334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinARMBaseInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 3903bf912593301152b65accb9d9c37a95172f1df5aStuart Hastings MachineBasicBlock *FBB, 3913bf912593301152b65accb9d9c37a95172f1df5aStuart Hastings const SmallVectorImpl<MachineOperand> &Cond, 3923bf912593301152b65accb9d9c37a95172f1df5aStuart Hastings DebugLoc DL) const { 3936495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ARMFunctionInfo *AFI = MBB.getParent()->getInfo<ARMFunctionInfo>(); 3946495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng int BOpc = !AFI->isThumbFunction() 3956495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ? ARM::B : (AFI->isThumb2Function() ? ARM::t2B : ARM::tB); 3966495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng int BccOpc = !AFI->isThumbFunction() 3976495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ? ARM::Bcc : (AFI->isThumb2Function() ? ARM::t2Bcc : ARM::tBcc); 398334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 399334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Shouldn't be a fall through. 400334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin assert(TBB && "InsertBranch must not be told to insert a fallthrough"); 401334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin assert((Cond.size() == 2 || Cond.size() == 0) && 402334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin "ARM branch conditions have two components!"); 403334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 404334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (FBB == 0) { 405334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (Cond.empty()) // Unconditional branch? 4063bf912593301152b65accb9d9c37a95172f1df5aStuart Hastings BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB); 407334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin else 4083bf912593301152b65accb9d9c37a95172f1df5aStuart Hastings BuildMI(&MBB, DL, get(BccOpc)).addMBB(TBB) 409334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()); 410334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 1; 411334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 412334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 413334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Two-way conditional branch. 4143bf912593301152b65accb9d9c37a95172f1df5aStuart Hastings BuildMI(&MBB, DL, get(BccOpc)).addMBB(TBB) 415334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()); 4163bf912593301152b65accb9d9c37a95172f1df5aStuart Hastings BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB); 417334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 2; 418334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 419334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 420334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinbool ARMBaseInstrInfo:: 421334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const { 422334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin ARMCC::CondCodes CC = (ARMCC::CondCodes)(int)Cond[0].getImm(); 423334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin Cond[0].setImm(ARMCC::getOppositeCondition(CC)); 424334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 425334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 426334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 427334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinbool ARMBaseInstrInfo:: 428334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinPredicateInstruction(MachineInstr *MI, 429334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const SmallVectorImpl<MachineOperand> &Pred) const { 430334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned Opc = MI->getOpcode(); 4315ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng if (isUncondBranchOpcode(Opc)) { 4325ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng MI->setDesc(get(getMatchingCondBranchOpcode(Opc))); 433334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI->addOperand(MachineOperand::CreateImm(Pred[0].getImm())); 434334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI->addOperand(MachineOperand::CreateReg(Pred[1].getReg(), false)); 435334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; 436334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 437334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 438334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin int PIdx = MI->findFirstPredOperandIdx(); 439334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (PIdx != -1) { 440334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineOperand &PMO = MI->getOperand(PIdx); 441334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin PMO.setImm(Pred[0].getImm()); 442334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI->getOperand(PIdx+1).setReg(Pred[1].getReg()); 443334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; 444334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 445334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 446334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 447334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 448334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinbool ARMBaseInstrInfo:: 449334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinSubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1, 450334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const SmallVectorImpl<MachineOperand> &Pred2) const { 451334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (Pred1.size() > 2 || Pred2.size() > 2) 452334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 453334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 454334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin ARMCC::CondCodes CC1 = (ARMCC::CondCodes)Pred1[0].getImm(); 455334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin ARMCC::CondCodes CC2 = (ARMCC::CondCodes)Pred2[0].getImm(); 456334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (CC1 == CC2) 457334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; 458334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 459334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin switch (CC1) { 460334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin default: 461334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 462334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMCC::AL: 463334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; 464334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMCC::HS: 465334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return CC2 == ARMCC::HI; 466334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMCC::LS: 467334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return CC2 == ARMCC::LO || CC2 == ARMCC::EQ; 468334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMCC::GE: 469334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return CC2 == ARMCC::GT; 470334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMCC::LE: 471334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return CC2 == ARMCC::LT; 472334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 473334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 474334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 475334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinbool ARMBaseInstrInfo::DefinesPredicate(MachineInstr *MI, 476334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin std::vector<MachineOperand> &Pred) const { 4778fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng // FIXME: This confuses implicit_def with optional CPSR def. 478334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const TargetInstrDesc &TID = MI->getDesc(); 479334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (!TID.getImplicitDefs() && !TID.hasOptionalDef()) 480334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 481334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 482334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool Found = false; 483334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 484334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const MachineOperand &MO = MI->getOperand(i); 485334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (MO.isReg() && MO.getReg() == ARM::CPSR) { 486334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin Pred.push_back(MO); 487334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin Found = true; 488334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 489334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 490334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 491334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return Found; 492334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 493334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 494ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng/// isPredicable - Return true if the specified instruction can be predicated. 495ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng/// By default, this returns true for every instruction with a 496ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng/// PredicateOperand. 497ac0869dc8a7986855c5557cc67d4709600158ef5Evan Chengbool ARMBaseInstrInfo::isPredicable(MachineInstr *MI) const { 498ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng const TargetInstrDesc &TID = MI->getDesc(); 499ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng if (!TID.isPredicable()) 500ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng return false; 501ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng 502ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng if ((TID.TSFlags & ARMII::DomainMask) == ARMII::DomainNEON) { 503ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng ARMFunctionInfo *AFI = 504ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng MI->getParent()->getParent()->getInfo<ARMFunctionInfo>(); 505d7f0810c934a7d13acb28c42d737ce58ec990ea8Evan Cheng return AFI->isThumb2Function(); 506ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng } 507ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng return true; 508ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng} 509334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 51056856b1f46ec1f073ceef4e826c544b8b1691608Chris Lattner/// FIXME: Works around a gcc miscompilation with -fstrict-aliasing. 51119e57025d458d3cb50804fd821fd89b868a819bdChandler CarruthLLVM_ATTRIBUTE_NOINLINE 512334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinstatic unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT, 51356856b1f46ec1f073ceef4e826c544b8b1691608Chris Lattner unsigned JTI); 514334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinstatic unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT, 515334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned JTI) { 51656856b1f46ec1f073ceef4e826c544b8b1691608Chris Lattner assert(JTI < JT.size()); 517334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return JT[JTI].MBBs.size(); 518334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 519334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 520334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin/// GetInstSize - Return the size of the specified MachineInstr. 521334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin/// 522334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinunsigned ARMBaseInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const { 523334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const MachineBasicBlock &MBB = *MI->getParent(); 524334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const MachineFunction *MF = MBB.getParent(); 52533adcfb4d217f5f23d9bde8ba02b8e48f9605fc5Chris Lattner const MCAsmInfo *MAI = MF->getTarget().getMCAsmInfo(); 526334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 527334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Basic size info comes from the TSFlags field. 528334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const TargetInstrDesc &TID = MI->getDesc(); 52999405df044f2c584242e711cc9023ec90356da82Bruno Cardoso Lopes uint64_t TSFlags = TID.TSFlags; 530334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 531a0ee862f2e3a0d202244e02459ddcf0dca0e8607Evan Cheng unsigned Opc = MI->getOpcode(); 532334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin switch ((TSFlags & ARMII::SizeMask) >> ARMII::SizeShift) { 533334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin default: { 534334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // If this machine instr is an inline asm, measure it. 535334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (MI->getOpcode() == ARM::INLINEASM) 53633adcfb4d217f5f23d9bde8ba02b8e48f9605fc5Chris Lattner return getInlineAsmLength(MI->getOperand(0).getSymbolName(), *MAI); 537334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (MI->isLabel()) 538334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 0; 539a0ee862f2e3a0d202244e02459ddcf0dca0e8607Evan Cheng switch (Opc) { 540334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin default: 541c23197a26f34f559ea9797de51e187087c039c42Torok Edwin llvm_unreachable("Unknown or unset size field for instr!"); 542518bb53485df640d7b7e3f6b0544099020c42aa7Chris Lattner case TargetOpcode::IMPLICIT_DEF: 543518bb53485df640d7b7e3f6b0544099020c42aa7Chris Lattner case TargetOpcode::KILL: 5447431beaba2a01c3fe299c861b2ec85cbf1dc81c4Bill Wendling case TargetOpcode::PROLOG_LABEL: 545518bb53485df640d7b7e3f6b0544099020c42aa7Chris Lattner case TargetOpcode::EH_LABEL: 546375be7730a6f3dee7a6dc319ee6c355a11ac99adDale Johannesen case TargetOpcode::DBG_VALUE: 547334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 0; 548334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 549334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin break; 550334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 551789476240d6b6f8ad9366cadf790a82bd41bb0b3Evan Cheng case ARMII::Size8Bytes: return 8; // ARM instruction x 2. 552789476240d6b6f8ad9366cadf790a82bd41bb0b3Evan Cheng case ARMII::Size4Bytes: return 4; // ARM / Thumb2 instruction. 553789476240d6b6f8ad9366cadf790a82bd41bb0b3Evan Cheng case ARMII::Size2Bytes: return 2; // Thumb1 instruction. 554334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMII::SizeSpecial: { 555a0ee862f2e3a0d202244e02459ddcf0dca0e8607Evan Cheng switch (Opc) { 55653519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng case ARM::MOVi16_ga_pcrel: 55753519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng case ARM::MOVTi16_ga_pcrel: 55853519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng case ARM::t2MOVi16_ga_pcrel: 55953519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng case ARM::t2MOVTi16_ga_pcrel: 5605de5d4b6d0eb3fd379fa571d82f6fa764460b3b8Evan Cheng return 4; 5613c38f96af2a5443d9f72fd078c2c98dd08746e51Jim Grosbach case ARM::MOVi32imm: 5623c38f96af2a5443d9f72fd078c2c98dd08746e51Jim Grosbach case ARM::t2MOVi32imm: 5633c38f96af2a5443d9f72fd078c2c98dd08746e51Jim Grosbach return 8; 564334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARM::CONSTPOOL_ENTRY: 565334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // If this machine instr is a constant pool entry, its size is recorded as 566334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // operand #2. 567334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return MI->getOperand(2).getImm(); 5685eb195153950bc7ebfc30649494a78b2096b5ef8Jim Grosbach case ARM::Int_eh_sjlj_longjmp: 5695eb195153950bc7ebfc30649494a78b2096b5ef8Jim Grosbach return 16; 5705eb195153950bc7ebfc30649494a78b2096b5ef8Jim Grosbach case ARM::tInt_eh_sjlj_longjmp: 5715eb195153950bc7ebfc30649494a78b2096b5ef8Jim Grosbach return 10; 572789476240d6b6f8ad9366cadf790a82bd41bb0b3Evan Cheng case ARM::Int_eh_sjlj_setjmp: 573d100755bab38784703f677b8b8eb174b624b346bJim Grosbach case ARM::Int_eh_sjlj_setjmp_nofp: 5740798eddd07b8dc827a4e6e9028c4c3a8d9444286Jim Grosbach return 20; 575d122874996a6faa8832569b632fd73a32ace7ae7Jim Grosbach case ARM::tInt_eh_sjlj_setjmp: 5765aa1684e5da9a85286bf7d29da419d261a70c2f2Jim Grosbach case ARM::t2Int_eh_sjlj_setjmp: 577d100755bab38784703f677b8b8eb174b624b346bJim Grosbach case ARM::t2Int_eh_sjlj_setjmp_nofp: 5780798eddd07b8dc827a4e6e9028c4c3a8d9444286Jim Grosbach return 12; 579334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARM::BR_JTr: 580334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARM::BR_JTm: 581334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARM::BR_JTadd: 582a0ee862f2e3a0d202244e02459ddcf0dca0e8607Evan Cheng case ARM::tBR_JTr: 583d26b14c34cbcee1448b86b524578fc51cc979023Evan Cheng case ARM::t2BR_JT: 584d092a87ba3f905a6801a0bdf816267329cf0391cJim Grosbach case ARM::t2TBB_JT: 585d092a87ba3f905a6801a0bdf816267329cf0391cJim Grosbach case ARM::t2TBH_JT: { 586334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // These are jumptable branches, i.e. a branch followed by an inlined 587d26b14c34cbcee1448b86b524578fc51cc979023Evan Cheng // jumptable. The size is 4 + 4 * number of entries. For TBB, each 588d26b14c34cbcee1448b86b524578fc51cc979023Evan Cheng // entry is one byte; TBH two byte each. 589d092a87ba3f905a6801a0bdf816267329cf0391cJim Grosbach unsigned EntrySize = (Opc == ARM::t2TBB_JT) 590d092a87ba3f905a6801a0bdf816267329cf0391cJim Grosbach ? 1 : ((Opc == ARM::t2TBH_JT) ? 2 : 4); 591334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned NumOps = TID.getNumOperands(); 592334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineOperand JTOP = 593334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI->getOperand(NumOps - (TID.isPredicable() ? 3 : 2)); 594334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned JTI = JTOP.getIndex(); 595334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo(); 596b1e803985d3378538ae9cff7eed4102c002d1e22Chris Lattner assert(MJTI != 0); 597334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables(); 598334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin assert(JTI < JT.size()); 599334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Thumb instructions are 2 byte aligned, but JT entries are 4 byte 600334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // 4 aligned. The assembler / linker may add 2 byte padding just before 601334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // the JT entries. The size does not include this padding; the 602334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // constant islands pass does separate bookkeeping for it. 603334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // FIXME: If we know the size of the function is less than (1 << 16) *2 604334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // bytes, we can use 16-bit entries instead. Then there won't be an 605334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // alignment issue. 60625f7cfc3cccba6f569f29f79ea533bae960b93c0Evan Cheng unsigned InstSize = (Opc == ARM::tBR_JTr || Opc == ARM::t2BR_JT) ? 2 : 4; 60725f7cfc3cccba6f569f29f79ea533bae960b93c0Evan Cheng unsigned NumEntries = getNumJTEntries(JT, JTI); 608d092a87ba3f905a6801a0bdf816267329cf0391cJim Grosbach if (Opc == ARM::t2TBB_JT && (NumEntries & 1)) 60925f7cfc3cccba6f569f29f79ea533bae960b93c0Evan Cheng // Make sure the instruction that follows TBB is 2-byte aligned. 61025f7cfc3cccba6f569f29f79ea533bae960b93c0Evan Cheng // FIXME: Constant island pass should insert an "ALIGN" instruction 61125f7cfc3cccba6f569f29f79ea533bae960b93c0Evan Cheng // instead. 61225f7cfc3cccba6f569f29f79ea533bae960b93c0Evan Cheng ++NumEntries; 61325f7cfc3cccba6f569f29f79ea533bae960b93c0Evan Cheng return NumEntries * EntrySize + InstSize; 614334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 615334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin default: 616334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Otherwise, pseudo-instruction sizes are zero. 617334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 0; 618334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 619334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 620334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 621334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 0; // Not reached 622334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 623334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 624ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesenvoid ARMBaseInstrInfo::copyPhysReg(MachineBasicBlock &MBB, 625ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen MachineBasicBlock::iterator I, DebugLoc DL, 626ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen unsigned DestReg, unsigned SrcReg, 627ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen bool KillSrc) const { 628ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen bool GPRDest = ARM::GPRRegClass.contains(DestReg); 629ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen bool GPRSrc = ARM::GPRRegClass.contains(SrcReg); 630ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen 631ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen if (GPRDest && GPRSrc) { 632ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen AddDefaultCC(AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::MOVr), DestReg) 633ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen .addReg(SrcReg, getKillRegState(KillSrc)))); 634ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen return; 6357bfdca0206f51132b26094c6f83a5ac97ee0f943David Goodwin } 636334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 637ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen bool SPRDest = ARM::SPRRegClass.contains(DestReg); 638ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen bool SPRSrc = ARM::SPRRegClass.contains(SrcReg); 639ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen 640ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen unsigned Opc; 641ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen if (SPRDest && SPRSrc) 642ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen Opc = ARM::VMOVS; 643ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen else if (GPRDest && SPRSrc) 644ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen Opc = ARM::VMOVRS; 645ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen else if (SPRDest && GPRSrc) 646ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen Opc = ARM::VMOVSR; 647ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen else if (ARM::DPRRegClass.contains(DestReg, SrcReg)) 648ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen Opc = ARM::VMOVD; 649ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen else if (ARM::QPRRegClass.contains(DestReg, SrcReg)) 650ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen Opc = ARM::VMOVQ; 651ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen else if (ARM::QQPRRegClass.contains(DestReg, SrcReg)) 652ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen Opc = ARM::VMOVQQ; 653ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen else if (ARM::QQQQPRRegClass.contains(DestReg, SrcReg)) 654ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen Opc = ARM::VMOVQQQQ; 655ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen else 656ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen llvm_unreachable("Impossible reg-to-reg copy"); 657ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen 658ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc), DestReg); 659ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen MIB.addReg(SrcReg, getKillRegState(KillSrc)); 660ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen if (Opc != ARM::VMOVQQ && Opc != ARM::VMOVQQQQ) 661ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen AddDefaultPred(MIB); 662334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 663334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 664c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Chengstatic const 665c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan ChengMachineInstrBuilder &AddDReg(MachineInstrBuilder &MIB, 666c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Cheng unsigned Reg, unsigned SubIdx, unsigned State, 667c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Cheng const TargetRegisterInfo *TRI) { 668c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Cheng if (!SubIdx) 669c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Cheng return MIB.addReg(Reg, State); 670c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Cheng 671c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Cheng if (TargetRegisterInfo::isPhysicalRegister(Reg)) 672c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Cheng return MIB.addReg(TRI->getSubReg(Reg, SubIdx), State); 673c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Cheng return MIB.addReg(Reg, State, SubIdx); 674c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Cheng} 675c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Cheng 676334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinvoid ARMBaseInstrInfo:: 677334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinstoreRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 678334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned SrcReg, bool isKill, int FI, 679746ad69e088176819981b4b2c5ac8dcd49f5e60eEvan Cheng const TargetRegisterClass *RC, 680746ad69e088176819981b4b2c5ac8dcd49f5e60eEvan Cheng const TargetRegisterInfo *TRI) const { 681c7f3ace20c325521c68335a1689645b43b06ddf0Chris Lattner DebugLoc DL; 682334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (I != MBB.end()) DL = I->getDebugLoc(); 683249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MachineFunction &MF = *MBB.getParent(); 684249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MachineFrameInfo &MFI = *MF.getFrameInfo(); 68531bc849123011b8eae6bb3c79876d9a3c26a6a1dJim Grosbach unsigned Align = MFI.getObjectAlignment(FI); 686249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov 687249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MachineMemOperand *MMO = 68859db5496f4fc2ef6111569e542f8b65480ef14c1Chris Lattner MF.getMachineMemOperand(MachinePointerInfo( 68959db5496f4fc2ef6111569e542f8b65480ef14c1Chris Lattner PseudoSourceValue::getFixedStack(FI)), 69059db5496f4fc2ef6111569e542f8b65480ef14c1Chris Lattner MachineMemOperand::MOStore, 691249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MFI.getObjectSize(FI), 69231bc849123011b8eae6bb3c79876d9a3c26a6a1dJim Grosbach Align); 693334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 6940eb0c7401c34c0b4604f732ce54db995eead14e6Bob Wilson // tGPR is used sometimes in ARM instructions that need to avoid using 6956ccfc507dc1f7ad8c8964193a2407264ca644f0dJim Grosbach // certain registers. Just treat it as GPR here. Likewise, rGPR. 6966ccfc507dc1f7ad8c8964193a2407264ca644f0dJim Grosbach if (RC == ARM::tGPRRegisterClass || RC == ARM::tcGPRRegisterClass 6976ccfc507dc1f7ad8c8964193a2407264ca644f0dJim Grosbach || RC == ARM::rGPRRegisterClass) 6980eb0c7401c34c0b4604f732ce54db995eead14e6Bob Wilson RC = ARM::GPRRegisterClass; 6990eb0c7401c34c0b4604f732ce54db995eead14e6Bob Wilson 700ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson switch (RC->getID()) { 701ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson case ARM::GPRRegClassID: 7027e3383c007f53b3a00675af225e428cb66ddf404Jim Grosbach AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::STRi12)) 703334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(SrcReg, getKillRegState(isKill)) 7047e3383c007f53b3a00675af225e428cb66ddf404Jim Grosbach .addFrameIndex(FI).addImm(0).addMemOperand(MMO)); 705ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson break; 706ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson case ARM::SPRRegClassID: 707d31c5496d7e1580058b5c6fbc8fd537a641ea590Evan Cheng AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTRS)) 708d31c5496d7e1580058b5c6fbc8fd537a641ea590Evan Cheng .addReg(SrcReg, getKillRegState(isKill)) 709d31c5496d7e1580058b5c6fbc8fd537a641ea590Evan Cheng .addFrameIndex(FI).addImm(0).addMemOperand(MMO)); 710ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson break; 711ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson case ARM::DPRRegClassID: 712ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson case ARM::DPR_VFP2RegClassID: 713ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson case ARM::DPR_8RegClassID: 714e5165490b7ba24bb2f3043399e0d60e7f3bcf8a5Jim Grosbach AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTRD)) 715334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(SrcReg, getKillRegState(isKill)) 716249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov .addFrameIndex(FI).addImm(0).addMemOperand(MMO)); 717ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson break; 718ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson case ARM::QPRRegClassID: 719ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson case ARM::QPR_VFP2RegClassID: 720ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson case ARM::QPR_8RegClassID: 7210cfcf93c95af91e809ef740eb0ab368477226b40Jim Grosbach if (Align >= 16 && getRegisterInfo().needsStackRealignment(MF)) { 722168f382dc67e5940cabdb28dc933c4f91cdd3137Bob Wilson AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1q64Pseudo)) 723f967ca0eaf30325cabe3c1971bf0dba16cf1b027Bob Wilson .addFrameIndex(FI).addImm(16) 72469b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng .addReg(SrcReg, getKillRegState(isKill)) 72569b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng .addMemOperand(MMO)); 72631bc849123011b8eae6bb3c79876d9a3c26a6a1dJim Grosbach } else { 72773fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMQIA)) 72869b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng .addReg(SrcReg, getKillRegState(isKill)) 72969b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng .addFrameIndex(FI) 73069b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng .addMemOperand(MMO)); 73131bc849123011b8eae6bb3c79876d9a3c26a6a1dJim Grosbach } 732ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson break; 733ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson case ARM::QQPRRegClassID: 734ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson case ARM::QQPR_VFP2RegClassID: 735435d4991779d6a47cadff4ea670b490d8507d6c4Evan Cheng if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) { 73622c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng // FIXME: It's possible to only store part of the QQ register if the 73722c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng // spilled def has a sub-register index. 738168f382dc67e5940cabdb28dc933c4f91cdd3137Bob Wilson AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1d64QPseudo)) 739168f382dc67e5940cabdb28dc933c4f91cdd3137Bob Wilson .addFrameIndex(FI).addImm(16) 740168f382dc67e5940cabdb28dc933c4f91cdd3137Bob Wilson .addReg(SrcReg, getKillRegState(isKill)) 741168f382dc67e5940cabdb28dc933c4f91cdd3137Bob Wilson .addMemOperand(MMO)); 742435d4991779d6a47cadff4ea670b490d8507d6c4Evan Cheng } else { 743435d4991779d6a47cadff4ea670b490d8507d6c4Evan Cheng MachineInstrBuilder MIB = 74473fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMDIA)) 74573fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling .addFrameIndex(FI)) 746435d4991779d6a47cadff4ea670b490d8507d6c4Evan Cheng .addMemOperand(MMO); 747558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI); 748558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI); 749558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI); 750558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI); 751435d4991779d6a47cadff4ea670b490d8507d6c4Evan Cheng } 752ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson break; 753ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson case ARM::QQQQPRRegClassID: { 75422c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng MachineInstrBuilder MIB = 75573fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMDIA)) 75673fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling .addFrameIndex(FI)) 75722c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng .addMemOperand(MMO); 758558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI); 759558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI); 760558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI); 761558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen MIB = AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI); 762558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen MIB = AddDReg(MIB, SrcReg, ARM::dsub_4, 0, TRI); 763558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen MIB = AddDReg(MIB, SrcReg, ARM::dsub_5, 0, TRI); 764558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen MIB = AddDReg(MIB, SrcReg, ARM::dsub_6, 0, TRI); 765558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen AddDReg(MIB, SrcReg, ARM::dsub_7, 0, TRI); 766ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson break; 767ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson } 768ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson default: 769ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson llvm_unreachable("Unknown regclass!"); 770334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 771334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 772334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 77334327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesenunsigned 77434327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund OlesenARMBaseInstrInfo::isStoreToStackSlot(const MachineInstr *MI, 77534327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen int &FrameIndex) const { 77634327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen switch (MI->getOpcode()) { 77734327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen default: break; 7787e3383c007f53b3a00675af225e428cb66ddf404Jim Grosbach case ARM::STRrs: 77934327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen case ARM::t2STRs: // FIXME: don't use t2STRs to access frame. 78034327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen if (MI->getOperand(1).isFI() && 78134327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen MI->getOperand(2).isReg() && 78234327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen MI->getOperand(3).isImm() && 78334327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen MI->getOperand(2).getReg() == 0 && 78434327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen MI->getOperand(3).getImm() == 0) { 78534327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen FrameIndex = MI->getOperand(1).getIndex(); 78634327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen return MI->getOperand(0).getReg(); 78734327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen } 78834327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen break; 7897e3383c007f53b3a00675af225e428cb66ddf404Jim Grosbach case ARM::STRi12: 79034327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen case ARM::t2STRi12: 79134327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen case ARM::tSpill: 79234327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen case ARM::VSTRD: 79334327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen case ARM::VSTRS: 79434327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen if (MI->getOperand(1).isFI() && 79534327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen MI->getOperand(2).isImm() && 79634327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen MI->getOperand(2).getImm() == 0) { 79734327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen FrameIndex = MI->getOperand(1).getIndex(); 79834327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen return MI->getOperand(0).getReg(); 79934327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen } 80034327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen break; 801d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen case ARM::VST1q64Pseudo: 802d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen if (MI->getOperand(0).isFI() && 803d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen MI->getOperand(2).getSubReg() == 0) { 804d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen FrameIndex = MI->getOperand(0).getIndex(); 805d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen return MI->getOperand(2).getReg(); 806d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen } 80731bbc51ac9245bc82c933c9db8358ca9bb558ac5Jakob Stoklund Olesen break; 80873fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMQIA: 809d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen if (MI->getOperand(1).isFI() && 810d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen MI->getOperand(0).getSubReg() == 0) { 811d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen FrameIndex = MI->getOperand(1).getIndex(); 812d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen return MI->getOperand(0).getReg(); 813d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen } 814d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen break; 81534327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen } 81634327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen 81734327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen return 0; 81834327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen} 81934327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen 820334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinvoid ARMBaseInstrInfo:: 821334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinloadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 822334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned DestReg, int FI, 823746ad69e088176819981b4b2c5ac8dcd49f5e60eEvan Cheng const TargetRegisterClass *RC, 824746ad69e088176819981b4b2c5ac8dcd49f5e60eEvan Cheng const TargetRegisterInfo *TRI) const { 825c7f3ace20c325521c68335a1689645b43b06ddf0Chris Lattner DebugLoc DL; 826334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (I != MBB.end()) DL = I->getDebugLoc(); 827249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MachineFunction &MF = *MBB.getParent(); 828249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MachineFrameInfo &MFI = *MF.getFrameInfo(); 82931bc849123011b8eae6bb3c79876d9a3c26a6a1dJim Grosbach unsigned Align = MFI.getObjectAlignment(FI); 830249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MachineMemOperand *MMO = 83159db5496f4fc2ef6111569e542f8b65480ef14c1Chris Lattner MF.getMachineMemOperand( 83259db5496f4fc2ef6111569e542f8b65480ef14c1Chris Lattner MachinePointerInfo(PseudoSourceValue::getFixedStack(FI)), 83359db5496f4fc2ef6111569e542f8b65480ef14c1Chris Lattner MachineMemOperand::MOLoad, 834249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MFI.getObjectSize(FI), 83531bc849123011b8eae6bb3c79876d9a3c26a6a1dJim Grosbach Align); 836334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 8370eb0c7401c34c0b4604f732ce54db995eead14e6Bob Wilson // tGPR is used sometimes in ARM instructions that need to avoid using 8380eb0c7401c34c0b4604f732ce54db995eead14e6Bob Wilson // certain registers. Just treat it as GPR here. 8396ccfc507dc1f7ad8c8964193a2407264ca644f0dJim Grosbach if (RC == ARM::tGPRRegisterClass || RC == ARM::tcGPRRegisterClass 8406ccfc507dc1f7ad8c8964193a2407264ca644f0dJim Grosbach || RC == ARM::rGPRRegisterClass) 8410eb0c7401c34c0b4604f732ce54db995eead14e6Bob Wilson RC = ARM::GPRRegisterClass; 8420eb0c7401c34c0b4604f732ce54db995eead14e6Bob Wilson 843ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson switch (RC->getID()) { 844ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson case ARM::GPRRegClassID: 8453e5561247202bae994dd259a2d8dc4eff8f799f3Jim Grosbach AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::LDRi12), DestReg) 8463e5561247202bae994dd259a2d8dc4eff8f799f3Jim Grosbach .addFrameIndex(FI).addImm(0).addMemOperand(MMO)); 847ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson break; 848ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson case ARM::SPRRegClassID: 849d31c5496d7e1580058b5c6fbc8fd537a641ea590Evan Cheng AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRS), DestReg) 850d31c5496d7e1580058b5c6fbc8fd537a641ea590Evan Cheng .addFrameIndex(FI).addImm(0).addMemOperand(MMO)); 851ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson break; 852ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson case ARM::DPRRegClassID: 853ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson case ARM::DPR_VFP2RegClassID: 854ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson case ARM::DPR_8RegClassID: 855e5165490b7ba24bb2f3043399e0d60e7f3bcf8a5Jim Grosbach AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRD), DestReg) 856249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov .addFrameIndex(FI).addImm(0).addMemOperand(MMO)); 857ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson break; 858ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson case ARM::QPRRegClassID: 859ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson case ARM::QPR_VFP2RegClassID: 860ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson case ARM::QPR_8RegClassID: 8610cfcf93c95af91e809ef740eb0ab368477226b40Jim Grosbach if (Align >= 16 && getRegisterInfo().needsStackRealignment(MF)) { 862168f382dc67e5940cabdb28dc933c4f91cdd3137Bob Wilson AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1q64Pseudo), DestReg) 863f967ca0eaf30325cabe3c1971bf0dba16cf1b027Bob Wilson .addFrameIndex(FI).addImm(16) 86469b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng .addMemOperand(MMO)); 86531bc849123011b8eae6bb3c79876d9a3c26a6a1dJim Grosbach } else { 86673fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMQIA), DestReg) 86769b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng .addFrameIndex(FI) 86869b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng .addMemOperand(MMO)); 86931bc849123011b8eae6bb3c79876d9a3c26a6a1dJim Grosbach } 870ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson break; 871ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson case ARM::QQPRRegClassID: 872ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson case ARM::QQPR_VFP2RegClassID: 873435d4991779d6a47cadff4ea670b490d8507d6c4Evan Cheng if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) { 874168f382dc67e5940cabdb28dc933c4f91cdd3137Bob Wilson AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1d64QPseudo), DestReg) 875168f382dc67e5940cabdb28dc933c4f91cdd3137Bob Wilson .addFrameIndex(FI).addImm(16) 876168f382dc67e5940cabdb28dc933c4f91cdd3137Bob Wilson .addMemOperand(MMO)); 877435d4991779d6a47cadff4ea670b490d8507d6c4Evan Cheng } else { 878435d4991779d6a47cadff4ea670b490d8507d6c4Evan Cheng MachineInstrBuilder MIB = 87973fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMDIA)) 88073fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling .addFrameIndex(FI)) 881435d4991779d6a47cadff4ea670b490d8507d6c4Evan Cheng .addMemOperand(MMO); 882558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::Define, TRI); 883558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::Define, TRI); 884558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::Define, TRI); 885558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen AddDReg(MIB, DestReg, ARM::dsub_3, RegState::Define, TRI); 886435d4991779d6a47cadff4ea670b490d8507d6c4Evan Cheng } 887ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson break; 888ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson case ARM::QQQQPRRegClassID: { 889ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson MachineInstrBuilder MIB = 89073fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMDIA)) 89173fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling .addFrameIndex(FI)) 892ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson .addMemOperand(MMO); 893ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::Define, TRI); 894ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::Define, TRI); 895ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::Define, TRI); 896ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::Define, TRI); 897ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson MIB = AddDReg(MIB, DestReg, ARM::dsub_4, RegState::Define, TRI); 898ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson MIB = AddDReg(MIB, DestReg, ARM::dsub_5, RegState::Define, TRI); 899ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson MIB = AddDReg(MIB, DestReg, ARM::dsub_6, RegState::Define, TRI); 900ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson AddDReg(MIB, DestReg, ARM::dsub_7, RegState::Define, TRI); 901ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson break; 902ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson } 903ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson default: 904ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson llvm_unreachable("Unknown regclass!"); 905334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 906334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 907334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 90834327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesenunsigned 90934327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund OlesenARMBaseInstrInfo::isLoadFromStackSlot(const MachineInstr *MI, 91034327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen int &FrameIndex) const { 91134327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen switch (MI->getOpcode()) { 91234327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen default: break; 9133e5561247202bae994dd259a2d8dc4eff8f799f3Jim Grosbach case ARM::LDRrs: 91434327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen case ARM::t2LDRs: // FIXME: don't use t2LDRs to access frame. 91534327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen if (MI->getOperand(1).isFI() && 91634327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen MI->getOperand(2).isReg() && 91734327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen MI->getOperand(3).isImm() && 91834327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen MI->getOperand(2).getReg() == 0 && 91934327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen MI->getOperand(3).getImm() == 0) { 92034327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen FrameIndex = MI->getOperand(1).getIndex(); 92134327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen return MI->getOperand(0).getReg(); 92234327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen } 92334327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen break; 9243e5561247202bae994dd259a2d8dc4eff8f799f3Jim Grosbach case ARM::LDRi12: 92534327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen case ARM::t2LDRi12: 92634327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen case ARM::tRestore: 92734327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen case ARM::VLDRD: 92834327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen case ARM::VLDRS: 92934327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen if (MI->getOperand(1).isFI() && 93034327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen MI->getOperand(2).isImm() && 93134327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen MI->getOperand(2).getImm() == 0) { 93234327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen FrameIndex = MI->getOperand(1).getIndex(); 933d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen return MI->getOperand(0).getReg(); 934d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen } 935d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen break; 936d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen case ARM::VLD1q64Pseudo: 937d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen if (MI->getOperand(1).isFI() && 938d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen MI->getOperand(0).getSubReg() == 0) { 939d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen FrameIndex = MI->getOperand(1).getIndex(); 94006f264e504d75f0426eea55b9f9e36c780d8a4fcJakob Stoklund Olesen return MI->getOperand(0).getReg(); 94106f264e504d75f0426eea55b9f9e36c780d8a4fcJakob Stoklund Olesen } 94206f264e504d75f0426eea55b9f9e36c780d8a4fcJakob Stoklund Olesen break; 94373fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMQIA: 94406f264e504d75f0426eea55b9f9e36c780d8a4fcJakob Stoklund Olesen if (MI->getOperand(1).isFI() && 94506f264e504d75f0426eea55b9f9e36c780d8a4fcJakob Stoklund Olesen MI->getOperand(0).getSubReg() == 0) { 94606f264e504d75f0426eea55b9f9e36c780d8a4fcJakob Stoklund Olesen FrameIndex = MI->getOperand(1).getIndex(); 94734327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen return MI->getOperand(0).getReg(); 94834327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen } 94934327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen break; 95034327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen } 95134327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen 95234327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen return 0; 95334327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen} 95434327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen 95562b50656ceb854eb0be265d63b2a1d46e7400d8aEvan ChengMachineInstr* 95662b50656ceb854eb0be265d63b2a1d46e7400d8aEvan ChengARMBaseInstrInfo::emitFrameIndexDebugValue(MachineFunction &MF, 9578601a3d4decff0a380e059b037dabf71075497d3Evan Cheng int FrameIx, uint64_t Offset, 95862b50656ceb854eb0be265d63b2a1d46e7400d8aEvan Cheng const MDNode *MDPtr, 95962b50656ceb854eb0be265d63b2a1d46e7400d8aEvan Cheng DebugLoc DL) const { 96062b50656ceb854eb0be265d63b2a1d46e7400d8aEvan Cheng MachineInstrBuilder MIB = BuildMI(MF, DL, get(ARM::DBG_VALUE)) 96162b50656ceb854eb0be265d63b2a1d46e7400d8aEvan Cheng .addFrameIndex(FrameIx).addImm(0).addImm(Offset).addMetadata(MDPtr); 96262b50656ceb854eb0be265d63b2a1d46e7400d8aEvan Cheng return &*MIB; 96362b50656ceb854eb0be265d63b2a1d46e7400d8aEvan Cheng} 96462b50656ceb854eb0be265d63b2a1d46e7400d8aEvan Cheng 96530ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen/// Create a copy of a const pool value. Update CPI to the new index and return 96630ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen/// the label UID. 96730ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesenstatic unsigned duplicateCPV(MachineFunction &MF, unsigned &CPI) { 96830ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen MachineConstantPool *MCP = MF.getConstantPool(); 96930ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 97030ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen 97130ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPI]; 97230ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen assert(MCPE.isMachineConstantPoolEntry() && 97330ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen "Expecting a machine constantpool entry!"); 97430ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen ARMConstantPoolValue *ACPV = 97530ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal); 97630ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen 9775de5d4b6d0eb3fd379fa571d82f6fa764460b3b8Evan Cheng unsigned PCLabelId = AFI->createPICLabelUId(); 97830ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen ARMConstantPoolValue *NewCPV = 0; 97951f5b67395780b8421f4aa6ee998ed51b23dae9dJim Grosbach // FIXME: The below assumes PIC relocation model and that the function 98051f5b67395780b8421f4aa6ee998ed51b23dae9dJim Grosbach // is Thumb mode (t1 or t2). PCAdjustment would be 8 for ARM mode PIC, and 98151f5b67395780b8421f4aa6ee998ed51b23dae9dJim Grosbach // zero for non-PIC in ARM or Thumb. The callers are all of thumb LDR 98251f5b67395780b8421f4aa6ee998ed51b23dae9dJim Grosbach // instructions, so that's probably OK, but is PIC always correct when 98351f5b67395780b8421f4aa6ee998ed51b23dae9dJim Grosbach // we get here? 98430ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen if (ACPV->isGlobalValue()) 98530ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen NewCPV = new ARMConstantPoolValue(ACPV->getGV(), PCLabelId, 98630ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen ARMCP::CPValue, 4); 98730ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen else if (ACPV->isExtSymbol()) 98830ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen NewCPV = new ARMConstantPoolValue(MF.getFunction()->getContext(), 98930ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen ACPV->getSymbol(), PCLabelId, 4); 99030ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen else if (ACPV->isBlockAddress()) 99130ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen NewCPV = new ARMConstantPoolValue(ACPV->getBlockAddress(), PCLabelId, 99230ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen ARMCP::CPBlockAddress, 4); 99351f5b67395780b8421f4aa6ee998ed51b23dae9dJim Grosbach else if (ACPV->isLSDA()) 99451f5b67395780b8421f4aa6ee998ed51b23dae9dJim Grosbach NewCPV = new ARMConstantPoolValue(MF.getFunction(), PCLabelId, 99551f5b67395780b8421f4aa6ee998ed51b23dae9dJim Grosbach ARMCP::CPLSDA, 4); 99630ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen else 99730ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen llvm_unreachable("Unexpected ARM constantpool value type!!"); 99830ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen CPI = MCP->getConstantPoolIndex(NewCPV, MCPE.getAlignment()); 99930ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen return PCLabelId; 100030ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen} 100130ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen 1002fdc834046efd427d474e3b899ec69354c05071e0Evan Chengvoid ARMBaseInstrInfo:: 1003fdc834046efd427d474e3b899ec69354c05071e0Evan ChengreMaterialize(MachineBasicBlock &MBB, 1004fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng MachineBasicBlock::iterator I, 1005fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng unsigned DestReg, unsigned SubIdx, 1006d57cdd5683ea926e489067364fb7ffe5fd5d35eeEvan Cheng const MachineInstr *Orig, 10079edf7deb37f0f97664f279040fa15d89f32e23d9Jakob Stoklund Olesen const TargetRegisterInfo &TRI) const { 1008fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng unsigned Opcode = Orig->getOpcode(); 1009fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng switch (Opcode) { 1010fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng default: { 1011fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig); 10129edf7deb37f0f97664f279040fa15d89f32e23d9Jakob Stoklund Olesen MI->substituteRegister(Orig->getOperand(0).getReg(), DestReg, SubIdx, TRI); 1013fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng MBB.insert(I, MI); 1014fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng break; 1015fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng } 1016fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng case ARM::tLDRpci_pic: 1017fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng case ARM::t2LDRpci_pic: { 1018fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng MachineFunction &MF = *MBB.getParent(); 1019fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng unsigned CPI = Orig->getOperand(1).getIndex(); 102030ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen unsigned PCLabelId = duplicateCPV(MF, CPI); 1021fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng MachineInstrBuilder MIB = BuildMI(MBB, I, Orig->getDebugLoc(), get(Opcode), 1022fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng DestReg) 1023fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng .addConstantPoolIndex(CPI).addImm(PCLabelId); 1024fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng (*MIB).setMemRefs(Orig->memoperands_begin(), Orig->memoperands_end()); 1025fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng break; 1026fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng } 1027fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng } 1028fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng} 1029fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng 103030ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund OlesenMachineInstr * 103130ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund OlesenARMBaseInstrInfo::duplicate(MachineInstr *Orig, MachineFunction &MF) const { 103230ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen MachineInstr *MI = TargetInstrInfoImpl::duplicate(Orig, MF); 103330ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen switch(Orig->getOpcode()) { 103430ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen case ARM::tLDRpci_pic: 103530ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen case ARM::t2LDRpci_pic: { 103630ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen unsigned CPI = Orig->getOperand(1).getIndex(); 103730ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen unsigned PCLabelId = duplicateCPV(MF, CPI); 103830ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen Orig->getOperand(1).setIndex(CPI); 103930ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen Orig->getOperand(2).setImm(PCLabelId); 104030ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen break; 104130ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen } 104230ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen } 104330ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen return MI; 104430ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen} 104530ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen 1046506049f29f4f202a8e45feb916cc0264440a7f6dEvan Chengbool ARMBaseInstrInfo::produceSameValue(const MachineInstr *MI0, 10479fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng const MachineInstr *MI1, 10489fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng const MachineRegisterInfo *MRI) const { 1049d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng int Opcode = MI0->getOpcode(); 1050d7e3cc840b81b0438e47f05d9664137a198876dfEvan Cheng if (Opcode == ARM::t2LDRpci || 10519b82425cb0105fd5704f6b9bcd5e7693b05b1759Evan Cheng Opcode == ARM::t2LDRpci_pic || 10529b82425cb0105fd5704f6b9bcd5e7693b05b1759Evan Cheng Opcode == ARM::tLDRpci || 10539fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng Opcode == ARM::tLDRpci_pic || 105453519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng Opcode == ARM::MOV_ga_dyn || 105553519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng Opcode == ARM::MOV_ga_pcrel || 105653519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng Opcode == ARM::MOV_ga_pcrel_ldr || 105753519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng Opcode == ARM::t2MOV_ga_dyn || 105853519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng Opcode == ARM::t2MOV_ga_pcrel) { 1059d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng if (MI1->getOpcode() != Opcode) 1060d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng return false; 1061d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng if (MI0->getNumOperands() != MI1->getNumOperands()) 1062d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng return false; 1063d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng 1064d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng const MachineOperand &MO0 = MI0->getOperand(1); 1065d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng const MachineOperand &MO1 = MI1->getOperand(1); 1066d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng if (MO0.getOffset() != MO1.getOffset()) 1067d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng return false; 1068d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng 106953519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng if (Opcode == ARM::MOV_ga_dyn || 107053519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng Opcode == ARM::MOV_ga_pcrel || 107153519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng Opcode == ARM::MOV_ga_pcrel_ldr || 107253519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng Opcode == ARM::t2MOV_ga_dyn || 107353519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng Opcode == ARM::t2MOV_ga_pcrel) 10749fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng // Ignore the PC labels. 10759fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng return MO0.getGlobal() == MO1.getGlobal(); 10769fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng 1077d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng const MachineFunction *MF = MI0->getParent()->getParent(); 1078d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng const MachineConstantPool *MCP = MF->getConstantPool(); 1079d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng int CPI0 = MO0.getIndex(); 1080d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng int CPI1 = MO1.getIndex(); 1081d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng const MachineConstantPoolEntry &MCPE0 = MCP->getConstants()[CPI0]; 1082d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng const MachineConstantPoolEntry &MCPE1 = MCP->getConstants()[CPI1]; 1083d700617193f3d11deb83cd56c4ababbc8e0ea19fEvan Cheng bool isARMCP0 = MCPE0.isMachineConstantPoolEntry(); 1084d700617193f3d11deb83cd56c4ababbc8e0ea19fEvan Cheng bool isARMCP1 = MCPE1.isMachineConstantPoolEntry(); 1085d700617193f3d11deb83cd56c4ababbc8e0ea19fEvan Cheng if (isARMCP0 && isARMCP1) { 1086d700617193f3d11deb83cd56c4ababbc8e0ea19fEvan Cheng ARMConstantPoolValue *ACPV0 = 1087d700617193f3d11deb83cd56c4ababbc8e0ea19fEvan Cheng static_cast<ARMConstantPoolValue*>(MCPE0.Val.MachineCPVal); 1088d700617193f3d11deb83cd56c4ababbc8e0ea19fEvan Cheng ARMConstantPoolValue *ACPV1 = 1089d700617193f3d11deb83cd56c4ababbc8e0ea19fEvan Cheng static_cast<ARMConstantPoolValue*>(MCPE1.Val.MachineCPVal); 1090d700617193f3d11deb83cd56c4ababbc8e0ea19fEvan Cheng return ACPV0->hasSameValue(ACPV1); 1091d700617193f3d11deb83cd56c4ababbc8e0ea19fEvan Cheng } else if (!isARMCP0 && !isARMCP1) { 1092d700617193f3d11deb83cd56c4ababbc8e0ea19fEvan Cheng return MCPE0.Val.ConstVal == MCPE1.Val.ConstVal; 1093d700617193f3d11deb83cd56c4ababbc8e0ea19fEvan Cheng } 1094d700617193f3d11deb83cd56c4ababbc8e0ea19fEvan Cheng return false; 10959fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng } else if (Opcode == ARM::PICLDR) { 10969fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng if (MI1->getOpcode() != Opcode) 10979fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng return false; 10989fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng if (MI0->getNumOperands() != MI1->getNumOperands()) 10999fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng return false; 11009fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng 11019fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng unsigned Addr0 = MI0->getOperand(1).getReg(); 11029fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng unsigned Addr1 = MI1->getOperand(1).getReg(); 11039fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng if (Addr0 != Addr1) { 11049fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng if (!MRI || 11059fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng !TargetRegisterInfo::isVirtualRegister(Addr0) || 11069fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng !TargetRegisterInfo::isVirtualRegister(Addr1)) 11079fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng return false; 11089fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng 11099fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng // This assumes SSA form. 11109fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng MachineInstr *Def0 = MRI->getVRegDef(Addr0); 11119fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng MachineInstr *Def1 = MRI->getVRegDef(Addr1); 11129fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng // Check if the loaded value, e.g. a constantpool of a global address, are 11139fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng // the same. 11149fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng if (!produceSameValue(Def0, Def1, MRI)) 11159fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng return false; 11169fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng } 11179fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng 11189fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng for (unsigned i = 3, e = MI0->getNumOperands(); i != e; ++i) { 11199fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng // %vreg12<def> = PICLDR %vreg11, 0, pred:14, pred:%noreg 11209fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng const MachineOperand &MO0 = MI0->getOperand(i); 11219fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng const MachineOperand &MO1 = MI1->getOperand(i); 11229fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng if (!MO0.isIdenticalTo(MO1)) 11239fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng return false; 11249fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng } 11259fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng return true; 1126d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng } 1127d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng 1128506049f29f4f202a8e45feb916cc0264440a7f6dEvan Cheng return MI0->isIdenticalTo(MI1, MachineInstr::IgnoreVRegDefs); 1129d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng} 1130d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng 11314b722108e2cf8e77157e0879a23789cd44829933Bill Wendling/// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to 11324b722108e2cf8e77157e0879a23789cd44829933Bill Wendling/// determine if two loads are loading from the same base address. It should 11334b722108e2cf8e77157e0879a23789cd44829933Bill Wendling/// only return true if the base pointers are the same and the only differences 11344b722108e2cf8e77157e0879a23789cd44829933Bill Wendling/// between the two addresses is the offset. It also returns the offsets by 11354b722108e2cf8e77157e0879a23789cd44829933Bill Wendling/// reference. 11364b722108e2cf8e77157e0879a23789cd44829933Bill Wendlingbool ARMBaseInstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, 11374b722108e2cf8e77157e0879a23789cd44829933Bill Wendling int64_t &Offset1, 11384b722108e2cf8e77157e0879a23789cd44829933Bill Wendling int64_t &Offset2) const { 11394b722108e2cf8e77157e0879a23789cd44829933Bill Wendling // Don't worry about Thumb: just ARM and Thumb2. 11404b722108e2cf8e77157e0879a23789cd44829933Bill Wendling if (Subtarget.isThumb1Only()) return false; 11414b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 11424b722108e2cf8e77157e0879a23789cd44829933Bill Wendling if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode()) 11434b722108e2cf8e77157e0879a23789cd44829933Bill Wendling return false; 11444b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 11454b722108e2cf8e77157e0879a23789cd44829933Bill Wendling switch (Load1->getMachineOpcode()) { 11464b722108e2cf8e77157e0879a23789cd44829933Bill Wendling default: 11474b722108e2cf8e77157e0879a23789cd44829933Bill Wendling return false; 11483e5561247202bae994dd259a2d8dc4eff8f799f3Jim Grosbach case ARM::LDRi12: 1149c1d30212e911d1e55ff6b25bffefb503708883c3Jim Grosbach case ARM::LDRBi12: 11504b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::LDRD: 11514b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::LDRH: 11524b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::LDRSB: 11534b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::LDRSH: 11544b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::VLDRD: 11554b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::VLDRS: 11564b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::t2LDRi8: 11574b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::t2LDRDi8: 11584b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::t2LDRSHi8: 11594b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::t2LDRi12: 11604b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::t2LDRSHi12: 11614b722108e2cf8e77157e0879a23789cd44829933Bill Wendling break; 11624b722108e2cf8e77157e0879a23789cd44829933Bill Wendling } 11634b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 11644b722108e2cf8e77157e0879a23789cd44829933Bill Wendling switch (Load2->getMachineOpcode()) { 11654b722108e2cf8e77157e0879a23789cd44829933Bill Wendling default: 11664b722108e2cf8e77157e0879a23789cd44829933Bill Wendling return false; 11673e5561247202bae994dd259a2d8dc4eff8f799f3Jim Grosbach case ARM::LDRi12: 1168c1d30212e911d1e55ff6b25bffefb503708883c3Jim Grosbach case ARM::LDRBi12: 11694b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::LDRD: 11704b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::LDRH: 11714b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::LDRSB: 11724b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::LDRSH: 11734b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::VLDRD: 11744b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::VLDRS: 11754b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::t2LDRi8: 11764b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::t2LDRDi8: 11774b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::t2LDRSHi8: 11784b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::t2LDRi12: 11794b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::t2LDRSHi12: 11804b722108e2cf8e77157e0879a23789cd44829933Bill Wendling break; 11814b722108e2cf8e77157e0879a23789cd44829933Bill Wendling } 11824b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 11834b722108e2cf8e77157e0879a23789cd44829933Bill Wendling // Check if base addresses and chain operands match. 11844b722108e2cf8e77157e0879a23789cd44829933Bill Wendling if (Load1->getOperand(0) != Load2->getOperand(0) || 11854b722108e2cf8e77157e0879a23789cd44829933Bill Wendling Load1->getOperand(4) != Load2->getOperand(4)) 11864b722108e2cf8e77157e0879a23789cd44829933Bill Wendling return false; 11874b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 11884b722108e2cf8e77157e0879a23789cd44829933Bill Wendling // Index should be Reg0. 11894b722108e2cf8e77157e0879a23789cd44829933Bill Wendling if (Load1->getOperand(3) != Load2->getOperand(3)) 11904b722108e2cf8e77157e0879a23789cd44829933Bill Wendling return false; 11914b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 11924b722108e2cf8e77157e0879a23789cd44829933Bill Wendling // Determine the offsets. 11934b722108e2cf8e77157e0879a23789cd44829933Bill Wendling if (isa<ConstantSDNode>(Load1->getOperand(1)) && 11944b722108e2cf8e77157e0879a23789cd44829933Bill Wendling isa<ConstantSDNode>(Load2->getOperand(1))) { 11954b722108e2cf8e77157e0879a23789cd44829933Bill Wendling Offset1 = cast<ConstantSDNode>(Load1->getOperand(1))->getSExtValue(); 11964b722108e2cf8e77157e0879a23789cd44829933Bill Wendling Offset2 = cast<ConstantSDNode>(Load2->getOperand(1))->getSExtValue(); 11974b722108e2cf8e77157e0879a23789cd44829933Bill Wendling return true; 11984b722108e2cf8e77157e0879a23789cd44829933Bill Wendling } 11994b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 12004b722108e2cf8e77157e0879a23789cd44829933Bill Wendling return false; 12014b722108e2cf8e77157e0879a23789cd44829933Bill Wendling} 12024b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 12034b722108e2cf8e77157e0879a23789cd44829933Bill Wendling/// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to 12047a2bdde0a0eebcd2125055e0eacaca040f0b766cChris Lattner/// determine (in conjunction with areLoadsFromSameBasePtr) if two loads should 12054b722108e2cf8e77157e0879a23789cd44829933Bill Wendling/// be scheduled togther. On some targets if two loads are loading from 12064b722108e2cf8e77157e0879a23789cd44829933Bill Wendling/// addresses in the same cache line, it's better if they are scheduled 12074b722108e2cf8e77157e0879a23789cd44829933Bill Wendling/// together. This function takes two integers that represent the load offsets 12084b722108e2cf8e77157e0879a23789cd44829933Bill Wendling/// from the common base address. It returns true if it decides it's desirable 12094b722108e2cf8e77157e0879a23789cd44829933Bill Wendling/// to schedule the two loads together. "NumLoads" is the number of loads that 12104b722108e2cf8e77157e0879a23789cd44829933Bill Wendling/// have already been scheduled after Load1. 12114b722108e2cf8e77157e0879a23789cd44829933Bill Wendlingbool ARMBaseInstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, 12124b722108e2cf8e77157e0879a23789cd44829933Bill Wendling int64_t Offset1, int64_t Offset2, 12134b722108e2cf8e77157e0879a23789cd44829933Bill Wendling unsigned NumLoads) const { 12144b722108e2cf8e77157e0879a23789cd44829933Bill Wendling // Don't worry about Thumb: just ARM and Thumb2. 12154b722108e2cf8e77157e0879a23789cd44829933Bill Wendling if (Subtarget.isThumb1Only()) return false; 12164b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 12174b722108e2cf8e77157e0879a23789cd44829933Bill Wendling assert(Offset2 > Offset1); 12184b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 12194b722108e2cf8e77157e0879a23789cd44829933Bill Wendling if ((Offset2 - Offset1) / 8 > 64) 12204b722108e2cf8e77157e0879a23789cd44829933Bill Wendling return false; 12214b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 12224b722108e2cf8e77157e0879a23789cd44829933Bill Wendling if (Load1->getMachineOpcode() != Load2->getMachineOpcode()) 12234b722108e2cf8e77157e0879a23789cd44829933Bill Wendling return false; // FIXME: overly conservative? 12244b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 12254b722108e2cf8e77157e0879a23789cd44829933Bill Wendling // Four loads in a row should be sufficient. 12264b722108e2cf8e77157e0879a23789cd44829933Bill Wendling if (NumLoads >= 3) 12274b722108e2cf8e77157e0879a23789cd44829933Bill Wendling return false; 12284b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 12294b722108e2cf8e77157e0879a23789cd44829933Bill Wendling return true; 12304b722108e2cf8e77157e0879a23789cd44829933Bill Wendling} 12314b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 123286050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Chengbool ARMBaseInstrInfo::isSchedulingBoundary(const MachineInstr *MI, 123386050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng const MachineBasicBlock *MBB, 123486050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng const MachineFunction &MF) const { 123557bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach // Debug info is never a scheduling boundary. It's necessary to be explicit 123657bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach // due to the special treatment of IT instructions below, otherwise a 123757bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach // dbg_value followed by an IT will result in the IT instruction being 123857bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach // considered a scheduling hazard, which is wrong. It should be the actual 123957bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach // instruction preceding the dbg_value instruction(s), just like it is 124057bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach // when debug info is not present. 124157bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach if (MI->isDebugValue()) 124257bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach return false; 124357bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach 124486050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // Terminators and labels can't be scheduled around. 124586050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng if (MI->getDesc().isTerminator() || MI->isLabel()) 124686050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng return true; 124786050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng 124886050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // Treat the start of the IT block as a scheduling boundary, but schedule 124986050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // t2IT along with all instructions following it. 125086050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // FIXME: This is a big hammer. But the alternative is to add all potential 125186050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // true and anti dependencies to IT block instructions as implicit operands 125286050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // to the t2IT instruction. The added compile time and complexity does not 125386050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // seem worth it. 125486050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng MachineBasicBlock::const_iterator I = MI; 125557bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach // Make sure to skip any dbg_value instructions 125657bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach while (++I != MBB->end() && I->isDebugValue()) 125757bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach ; 125857bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach if (I != MBB->end() && I->getOpcode() == ARM::t2IT) 125986050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng return true; 126086050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng 126186050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // Don't attempt to schedule around any instruction that defines 126286050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // a stack-oriented pointer, as it's unlikely to be profitable. This 126386050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // saves compile time, because it doesn't require every single 126486050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // stack slot reference to depend on the instruction that does the 126586050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // modification. 126686050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng if (MI->definesRegister(ARM::SP)) 126786050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng return true; 126886050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng 126986050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng return false; 127086050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng} 127186050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng 1272b20b85168c0e9819e6545f08281e9b83c82108f0Owen Andersonbool ARMBaseInstrInfo::isProfitableToIfCvt(MachineBasicBlock &MBB, 12735876db7a66fcc4ec4444a9f3e387c1cdc8baf9e5Cameron Zwarich unsigned NumCycles, 12748239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng unsigned ExtraPredCycles, 1275e3cc84a43d6a4bb6c50f58f3dd8e60e28787509eOwen Anderson float Probability, 1276e3cc84a43d6a4bb6c50f58f3dd8e60e28787509eOwen Anderson float Confidence) const { 12775876db7a66fcc4ec4444a9f3e387c1cdc8baf9e5Cameron Zwarich if (!NumCycles) 127813151432edace19ee867a93b5c14573df4f75d24Evan Cheng return false; 12792bbb76909126db5bed6bde84b16d94ab5de4d372Michael J. Spencer 1280b20b85168c0e9819e6545f08281e9b83c82108f0Owen Anderson // Attempt to estimate the relative costs of predication versus branching. 12815876db7a66fcc4ec4444a9f3e387c1cdc8baf9e5Cameron Zwarich float UnpredCost = Probability * NumCycles; 1282654d5440a477b1f6c89b051107e041a331f78e27Owen Anderson UnpredCost += 1.0; // The branch itself 1283e3cc84a43d6a4bb6c50f58f3dd8e60e28787509eOwen Anderson UnpredCost += (1.0 - Confidence) * Subtarget.getMispredictionPenalty(); 12842bbb76909126db5bed6bde84b16d94ab5de4d372Michael J. Spencer 12855876db7a66fcc4ec4444a9f3e387c1cdc8baf9e5Cameron Zwarich return (float)(NumCycles + ExtraPredCycles) < UnpredCost; 128613151432edace19ee867a93b5c14573df4f75d24Evan Cheng} 12872bbb76909126db5bed6bde84b16d94ab5de4d372Michael J. Spencer 128813151432edace19ee867a93b5c14573df4f75d24Evan Chengbool ARMBaseInstrInfo:: 12898239daf7c83a65a189c352cce3191cdc3bbfe151Evan ChengisProfitableToIfCvt(MachineBasicBlock &TMBB, 12908239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng unsigned TCycles, unsigned TExtra, 12918239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng MachineBasicBlock &FMBB, 12928239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng unsigned FCycles, unsigned FExtra, 1293e3cc84a43d6a4bb6c50f58f3dd8e60e28787509eOwen Anderson float Probability, float Confidence) const { 12948239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng if (!TCycles || !FCycles) 1295b20b85168c0e9819e6545f08281e9b83c82108f0Owen Anderson return false; 12962bbb76909126db5bed6bde84b16d94ab5de4d372Michael J. Spencer 1297b20b85168c0e9819e6545f08281e9b83c82108f0Owen Anderson // Attempt to estimate the relative costs of predication versus branching. 12988239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng float UnpredCost = Probability * TCycles + (1.0 - Probability) * FCycles; 1299654d5440a477b1f6c89b051107e041a331f78e27Owen Anderson UnpredCost += 1.0; // The branch itself 1300e3cc84a43d6a4bb6c50f58f3dd8e60e28787509eOwen Anderson UnpredCost += (1.0 - Confidence) * Subtarget.getMispredictionPenalty(); 13012bbb76909126db5bed6bde84b16d94ab5de4d372Michael J. Spencer 13028239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng return (float)(TCycles + FCycles + TExtra + FExtra) < UnpredCost; 130313151432edace19ee867a93b5c14573df4f75d24Evan Cheng} 130413151432edace19ee867a93b5c14573df4f75d24Evan Cheng 13058fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng/// getInstrPredicate - If instruction is predicated, returns its predicate 13068fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng/// condition, otherwise returns AL. It also returns the condition code 13078fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng/// register by reference. 13085adb66a646e2ec32265263739f5b01c3f50c176aEvan ChengARMCC::CondCodes 13095adb66a646e2ec32265263739f5b01c3f50c176aEvan Chengllvm::getInstrPredicate(const MachineInstr *MI, unsigned &PredReg) { 13108fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng int PIdx = MI->findFirstPredOperandIdx(); 13118fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng if (PIdx == -1) { 13128fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng PredReg = 0; 13138fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng return ARMCC::AL; 13148fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng } 13158fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng 13168fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng PredReg = MI->getOperand(PIdx+1).getReg(); 13178fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng return (ARMCC::CondCodes)MI->getOperand(PIdx).getImm(); 13188fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng} 13198fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng 13208fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng 13216495f63945e8dbde81f03a1dc2ab421993b9a495Evan Chengint llvm::getMatchingCondBranchOpcode(int Opc) { 13225ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng if (Opc == ARM::B) 13235ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng return ARM::Bcc; 13245ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng else if (Opc == ARM::tB) 13255ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng return ARM::tBcc; 13265ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng else if (Opc == ARM::t2B) 13275ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng return ARM::t2Bcc; 13285ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng 13295ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng llvm_unreachable("Unknown unconditional branch opcode!"); 13305ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng return 0; 13315ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng} 13325ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng 13336495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 13346495f63945e8dbde81f03a1dc2ab421993b9a495Evan Chengvoid llvm::emitARMRegPlusImmediate(MachineBasicBlock &MBB, 13356495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MachineBasicBlock::iterator &MBBI, DebugLoc dl, 13366495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned DestReg, unsigned BaseReg, int NumBytes, 13376495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ARMCC::CondCodes Pred, unsigned PredReg, 133857caad7a33ff145b71545f10dcfbbf2fd0f595d3Anton Korobeynikov const ARMBaseInstrInfo &TII, unsigned MIFlags) { 13396495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng bool isSub = NumBytes < 0; 13406495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (isSub) NumBytes = -NumBytes; 13416495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 13426495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng while (NumBytes) { 13436495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned RotAmt = ARM_AM::getSOImmValRotate(NumBytes); 13446495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned ThisVal = NumBytes & ARM_AM::rotr32(0xFF, RotAmt); 13456495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng assert(ThisVal && "Didn't extract field correctly"); 13466495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 13476495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // We will handle these bits from offset, clear them. 13486495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng NumBytes &= ~ThisVal; 13496495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 13506495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng assert(ARM_AM::getSOImmVal(ThisVal) != -1 && "Bit extraction didn't work?"); 13516495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 13526495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Build the new ADD / SUB. 13536495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned Opc = isSub ? ARM::SUBri : ARM::ADDri; 13546495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg) 13556495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng .addReg(BaseReg, RegState::Kill).addImm(ThisVal) 135657caad7a33ff145b71545f10dcfbbf2fd0f595d3Anton Korobeynikov .addImm((unsigned)Pred).addReg(PredReg).addReg(0) 135757caad7a33ff145b71545f10dcfbbf2fd0f595d3Anton Korobeynikov .setMIFlags(MIFlags); 13586495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng BaseReg = DestReg; 13596495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 13606495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng} 13616495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 1362cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Chengbool llvm::rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx, 1363cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng unsigned FrameReg, int &Offset, 1364cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng const ARMBaseInstrInfo &TII) { 13656495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned Opcode = MI.getOpcode(); 13666495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng const TargetInstrDesc &Desc = MI.getDesc(); 13676495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask); 13686495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng bool isSub = false; 1369764ab52dd80310a205c9888bf166d09dab858f90Jim Grosbach 13706495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Memory operands in inline assembly always use AddrMode2. 13716495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (Opcode == ARM::INLINEASM) 13726495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng AddrMode = ARMII::AddrMode2; 1373764ab52dd80310a205c9888bf166d09dab858f90Jim Grosbach 13746495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (Opcode == ARM::ADDri) { 13756495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng Offset += MI.getOperand(FrameRegIdx+1).getImm(); 13766495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (Offset == 0) { 13776495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Turn it into a move. 13786495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MI.setDesc(TII.get(ARM::MOVr)); 13796495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false); 13806495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MI.RemoveOperand(FrameRegIdx+1); 1381cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng Offset = 0; 1382cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng return true; 13836495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } else if (Offset < 0) { 13846495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng Offset = -Offset; 13856495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng isSub = true; 13866495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MI.setDesc(TII.get(ARM::SUBri)); 13876495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 13886495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 13896495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Common case: small offset, fits into instruction. 13906495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (ARM_AM::getSOImmVal(Offset) != -1) { 13916495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Replace the FrameIndex with sp / fp 13926495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false); 13936495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset); 1394cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng Offset = 0; 1395cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng return true; 13966495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 13976495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 13986495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Otherwise, pull as much of the immedidate into this ADDri/SUBri 13996495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // as possible. 14006495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned RotAmt = ARM_AM::getSOImmValRotate(Offset); 14016495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xFF, RotAmt); 14026495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 14036495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // We will handle these bits from offset, clear them. 14046495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng Offset &= ~ThisImmVal; 14056495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 14066495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Get the properly encoded SOImmVal field. 14076495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng assert(ARM_AM::getSOImmVal(ThisImmVal) != -1 && 14086495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng "Bit extraction didn't work?"); 14096495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MI.getOperand(FrameRegIdx+1).ChangeToImmediate(ThisImmVal); 14106495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } else { 14116495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned ImmIdx = 0; 14126495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng int InstrOffs = 0; 14136495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned NumBits = 0; 14146495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned Scale = 1; 14156495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng switch (AddrMode) { 14163e5561247202bae994dd259a2d8dc4eff8f799f3Jim Grosbach case ARMII::AddrMode_i12: { 14173e5561247202bae994dd259a2d8dc4eff8f799f3Jim Grosbach ImmIdx = FrameRegIdx + 1; 14183e5561247202bae994dd259a2d8dc4eff8f799f3Jim Grosbach InstrOffs = MI.getOperand(ImmIdx).getImm(); 14193e5561247202bae994dd259a2d8dc4eff8f799f3Jim Grosbach NumBits = 12; 14203e5561247202bae994dd259a2d8dc4eff8f799f3Jim Grosbach break; 14213e5561247202bae994dd259a2d8dc4eff8f799f3Jim Grosbach } 14226495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng case ARMII::AddrMode2: { 14236495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ImmIdx = FrameRegIdx+2; 14246495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng InstrOffs = ARM_AM::getAM2Offset(MI.getOperand(ImmIdx).getImm()); 14256495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (ARM_AM::getAM2Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub) 14266495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng InstrOffs *= -1; 14276495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng NumBits = 12; 14286495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng break; 14296495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 14306495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng case ARMII::AddrMode3: { 14316495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ImmIdx = FrameRegIdx+2; 14326495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng InstrOffs = ARM_AM::getAM3Offset(MI.getOperand(ImmIdx).getImm()); 14336495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (ARM_AM::getAM3Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub) 14346495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng InstrOffs *= -1; 14356495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng NumBits = 8; 14366495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng break; 14376495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 1438baf31088f1472f48ea5ae81f0b93636cc44ca444Anton Korobeynikov case ARMII::AddrMode4: 1439a44321776ecd96fa0344335d3027758be3386e45Jim Grosbach case ARMII::AddrMode6: 1440cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng // Can't fold any offset even if it's zero. 1441cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng return false; 14426495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng case ARMII::AddrMode5: { 14436495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ImmIdx = FrameRegIdx+1; 14446495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng InstrOffs = ARM_AM::getAM5Offset(MI.getOperand(ImmIdx).getImm()); 14456495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (ARM_AM::getAM5Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub) 14466495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng InstrOffs *= -1; 14476495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng NumBits = 8; 14486495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng Scale = 4; 14496495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng break; 14506495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 14516495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng default: 14526495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng llvm_unreachable("Unsupported addressing mode!"); 14536495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng break; 14546495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 14556495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 14566495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng Offset += InstrOffs * Scale; 14576495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!"); 14586495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (Offset < 0) { 14596495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng Offset = -Offset; 14606495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng isSub = true; 14616495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 14626495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 14636495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Attempt to fold address comp. if opcode has offset bits 14646495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (NumBits > 0) { 14656495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Common case: small offset, fits into instruction. 14666495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MachineOperand &ImmOp = MI.getOperand(ImmIdx); 14676495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng int ImmedOffset = Offset / Scale; 14686495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned Mask = (1 << NumBits) - 1; 14696495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if ((unsigned)Offset <= Mask * Scale) { 14706495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Replace the FrameIndex with sp 14716495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false); 147277aee8e22c36257716c2df2f275724765704f20cJim Grosbach // FIXME: When addrmode2 goes away, this will simplify (like the 147377aee8e22c36257716c2df2f275724765704f20cJim Grosbach // T2 version), as the LDR.i12 versions don't need the encoding 147477aee8e22c36257716c2df2f275724765704f20cJim Grosbach // tricks for the offset value. 147577aee8e22c36257716c2df2f275724765704f20cJim Grosbach if (isSub) { 147677aee8e22c36257716c2df2f275724765704f20cJim Grosbach if (AddrMode == ARMII::AddrMode_i12) 147777aee8e22c36257716c2df2f275724765704f20cJim Grosbach ImmedOffset = -ImmedOffset; 147877aee8e22c36257716c2df2f275724765704f20cJim Grosbach else 147977aee8e22c36257716c2df2f275724765704f20cJim Grosbach ImmedOffset |= 1 << NumBits; 148077aee8e22c36257716c2df2f275724765704f20cJim Grosbach } 14816495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ImmOp.ChangeToImmediate(ImmedOffset); 1482cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng Offset = 0; 1483cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng return true; 14846495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 1485764ab52dd80310a205c9888bf166d09dab858f90Jim Grosbach 14866495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Otherwise, it didn't fit. Pull in what we can to simplify the immed. 14876495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ImmedOffset = ImmedOffset & Mask; 1488063efbf569e46776093ddf50099c98fdbb362167Jim Grosbach if (isSub) { 1489063efbf569e46776093ddf50099c98fdbb362167Jim Grosbach if (AddrMode == ARMII::AddrMode_i12) 1490063efbf569e46776093ddf50099c98fdbb362167Jim Grosbach ImmedOffset = -ImmedOffset; 1491063efbf569e46776093ddf50099c98fdbb362167Jim Grosbach else 1492063efbf569e46776093ddf50099c98fdbb362167Jim Grosbach ImmedOffset |= 1 << NumBits; 1493063efbf569e46776093ddf50099c98fdbb362167Jim Grosbach } 14946495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ImmOp.ChangeToImmediate(ImmedOffset); 14956495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng Offset &= ~(Mask*Scale); 14966495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 14976495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 14986495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 1499cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng Offset = (isSub) ? -Offset : Offset; 1500cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng return Offset == 0; 15016495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng} 1502e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling 1503e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendlingbool ARMBaseInstrInfo:: 1504a99c3e9acd95f5fbfb611e3f807240cd74001142Eric ChristopherAnalyzeCompare(const MachineInstr *MI, unsigned &SrcReg, int &CmpMask, 1505a99c3e9acd95f5fbfb611e3f807240cd74001142Eric Christopher int &CmpValue) const { 1506e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling switch (MI->getOpcode()) { 1507e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling default: break; 150838ae997e63e3e1bb2c8679e01ea74cf8fd0be893Bill Wendling case ARM::CMPri: 1509e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling case ARM::t2CMPri: 1510e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling SrcReg = MI->getOperand(0).getReg(); 151104ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif CmpMask = ~0; 1512e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling CmpValue = MI->getOperand(1).getImm(); 1513e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling return true; 151404ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif case ARM::TSTri: 151504ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif case ARM::t2TSTri: 151604ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif SrcReg = MI->getOperand(0).getReg(); 151704ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif CmpMask = MI->getOperand(1).getImm(); 151804ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif CmpValue = 0; 151904ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif return true; 152004ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif } 152104ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif 152204ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif return false; 152304ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif} 152404ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif 152505642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif/// isSuitableForMask - Identify a suitable 'and' instruction that 152605642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif/// operates on the given source register and applies the same mask 152705642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif/// as a 'tst' instruction. Provide a limited look-through for copies. 152805642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif/// When successful, MI will hold the found instruction. 152905642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greifstatic bool isSuitableForMask(MachineInstr *&MI, unsigned SrcReg, 15308ff9bb189ce188452e6cae6ed65cb2745814126cGabor Greif int CmpMask, bool CommonUse) { 153105642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif switch (MI->getOpcode()) { 153204ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif case ARM::ANDri: 153304ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif case ARM::t2ANDri: 153405642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif if (CmpMask != MI->getOperand(2).getImm()) 15358ff9bb189ce188452e6cae6ed65cb2745814126cGabor Greif return false; 153605642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif if (SrcReg == MI->getOperand(CommonUse ? 1 : 0).getReg()) 153704ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif return true; 153804ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif break; 153905642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif case ARM::COPY: { 154005642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif // Walk down one instruction which is potentially an 'and'. 154105642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif const MachineInstr &Copy = *MI; 1542f000a7a212590bfd45e23c05bff5e1b683d25dd6Michael J. Spencer MachineBasicBlock::iterator AND( 1543f000a7a212590bfd45e23c05bff5e1b683d25dd6Michael J. Spencer llvm::next(MachineBasicBlock::iterator(MI))); 154405642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif if (AND == MI->getParent()->end()) return false; 154505642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif MI = AND; 154605642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif return isSuitableForMask(MI, Copy.getOperand(0).getReg(), 154705642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif CmpMask, true); 154805642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif } 1549e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling } 1550e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling 1551e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling return false; 1552e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling} 1553e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling 1554a65568676d0d9d53dd4aae8f1c58271bb4cfff10Bill Wendling/// OptimizeCompareInstr - Convert the instruction supplying the argument to the 1555eb96a2f6c03c0ec97c56a3493ac38024afacc774Evan Cheng/// comparison into one that sets the zero bit in the flags register. 1556e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendlingbool ARMBaseInstrInfo:: 155704ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor GreifOptimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, int CmpMask, 1558eb96a2f6c03c0ec97c56a3493ac38024afacc774Evan Cheng int CmpValue, const MachineRegisterInfo *MRI) const { 15593665661a5708c8adc2727be38b56d1d87ddeb661Bill Wendling if (CmpValue != 0) 156092ad57f066e9f256e4e3d72febf152e68caa80c7Bill Wendling return false; 156192ad57f066e9f256e4e3d72febf152e68caa80c7Bill Wendling 1562b41ee96d76ccf1eec2fd898def4cfd7c16868708Bill Wendling MachineRegisterInfo::def_iterator DI = MRI->def_begin(SrcReg); 1563b41ee96d76ccf1eec2fd898def4cfd7c16868708Bill Wendling if (llvm::next(DI) != MRI->def_end()) 156492ad57f066e9f256e4e3d72febf152e68caa80c7Bill Wendling // Only support one definition. 156592ad57f066e9f256e4e3d72febf152e68caa80c7Bill Wendling return false; 156692ad57f066e9f256e4e3d72febf152e68caa80c7Bill Wendling 156792ad57f066e9f256e4e3d72febf152e68caa80c7Bill Wendling MachineInstr *MI = &*DI; 156892ad57f066e9f256e4e3d72febf152e68caa80c7Bill Wendling 156904ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif // Masked compares sometimes use the same register as the corresponding 'and'. 157004ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif if (CmpMask != ~0) { 157105642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif if (!isSuitableForMask(MI, SrcReg, CmpMask, false)) { 157204ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif MI = 0; 1573b41ee96d76ccf1eec2fd898def4cfd7c16868708Bill Wendling for (MachineRegisterInfo::use_iterator UI = MRI->use_begin(SrcReg), 1574b41ee96d76ccf1eec2fd898def4cfd7c16868708Bill Wendling UE = MRI->use_end(); UI != UE; ++UI) { 157504ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif if (UI->getParent() != CmpInstr->getParent()) continue; 157605642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif MachineInstr *PotentialAND = &*UI; 15778ff9bb189ce188452e6cae6ed65cb2745814126cGabor Greif if (!isSuitableForMask(PotentialAND, SrcReg, CmpMask, true)) 157804ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif continue; 157905642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif MI = PotentialAND; 158004ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif break; 158104ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif } 158204ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif if (!MI) return false; 158304ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif } 158404ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif } 158504ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif 1586e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling // Conservatively refuse to convert an instruction which isn't in the same BB 1587e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling // as the comparison. 1588e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling if (MI->getParent() != CmpInstr->getParent()) 1589e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling return false; 1590e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling 1591e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling // Check that CPSR isn't set between the comparison instruction and the one we 1592e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling // want to change. 1593691e64a54ce899409abe7c131d15ed75e3c1fef5Evan Cheng MachineBasicBlock::const_iterator I = CmpInstr, E = MI, 1594691e64a54ce899409abe7c131d15ed75e3c1fef5Evan Cheng B = MI->getParent()->begin(); 15950aa38b9381a5be42abd4f5ca5baa8c2930d148d3Bill Wendling 15960aa38b9381a5be42abd4f5ca5baa8c2930d148d3Bill Wendling // Early exit if CmpInstr is at the beginning of the BB. 15970aa38b9381a5be42abd4f5ca5baa8c2930d148d3Bill Wendling if (I == B) return false; 15980aa38b9381a5be42abd4f5ca5baa8c2930d148d3Bill Wendling 1599e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling --I; 1600e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling for (; I != E; --I) { 1601e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling const MachineInstr &Instr = *I; 1602e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling 1603e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling for (unsigned IO = 0, EO = Instr.getNumOperands(); IO != EO; ++IO) { 1604e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling const MachineOperand &MO = Instr.getOperand(IO); 160540a5eb18b031fa1a5e9697e21e251e613d441cc5Bill Wendling if (!MO.isReg()) continue; 1606e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling 160740a5eb18b031fa1a5e9697e21e251e613d441cc5Bill Wendling // This instruction modifies or uses CPSR after the one we want to 160840a5eb18b031fa1a5e9697e21e251e613d441cc5Bill Wendling // change. We can't do this transformation. 1609e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling if (MO.getReg() == ARM::CPSR) 1610e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling return false; 1611e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling } 1612691e64a54ce899409abe7c131d15ed75e3c1fef5Evan Cheng 1613691e64a54ce899409abe7c131d15ed75e3c1fef5Evan Cheng if (I == B) 1614691e64a54ce899409abe7c131d15ed75e3c1fef5Evan Cheng // The 'and' is below the comparison instruction. 1615691e64a54ce899409abe7c131d15ed75e3c1fef5Evan Cheng return false; 1616e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling } 1617e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling 1618e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling // Set the "zero" bit in CPSR. 1619e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling switch (MI->getOpcode()) { 1620e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling default: break; 1621ca3f6a3925e9a6e91022aa211bdc1b6e3f2ff41fCameron Zwarich case ARM::RSBrr: 1622df298c9ea64eb335f63fc075d8ef6306682ffe75Owen Anderson case ARM::RSBri: 1623ca3f6a3925e9a6e91022aa211bdc1b6e3f2ff41fCameron Zwarich case ARM::RSCrr: 1624df298c9ea64eb335f63fc075d8ef6306682ffe75Owen Anderson case ARM::RSCri: 1625ca3f6a3925e9a6e91022aa211bdc1b6e3f2ff41fCameron Zwarich case ARM::ADDrr: 162638ae997e63e3e1bb2c8679e01ea74cf8fd0be893Bill Wendling case ARM::ADDri: 1627ca3f6a3925e9a6e91022aa211bdc1b6e3f2ff41fCameron Zwarich case ARM::ADCrr: 1628df298c9ea64eb335f63fc075d8ef6306682ffe75Owen Anderson case ARM::ADCri: 1629ca3f6a3925e9a6e91022aa211bdc1b6e3f2ff41fCameron Zwarich case ARM::SUBrr: 163038ae997e63e3e1bb2c8679e01ea74cf8fd0be893Bill Wendling case ARM::SUBri: 1631ca3f6a3925e9a6e91022aa211bdc1b6e3f2ff41fCameron Zwarich case ARM::SBCrr: 1632df298c9ea64eb335f63fc075d8ef6306682ffe75Owen Anderson case ARM::SBCri: 1633df298c9ea64eb335f63fc075d8ef6306682ffe75Owen Anderson case ARM::t2RSBri: 1634ca3f6a3925e9a6e91022aa211bdc1b6e3f2ff41fCameron Zwarich case ARM::t2ADDrr: 163538ae997e63e3e1bb2c8679e01ea74cf8fd0be893Bill Wendling case ARM::t2ADDri: 1636ca3f6a3925e9a6e91022aa211bdc1b6e3f2ff41fCameron Zwarich case ARM::t2ADCrr: 1637df298c9ea64eb335f63fc075d8ef6306682ffe75Owen Anderson case ARM::t2ADCri: 1638ca3f6a3925e9a6e91022aa211bdc1b6e3f2ff41fCameron Zwarich case ARM::t2SUBrr: 1639df298c9ea64eb335f63fc075d8ef6306682ffe75Owen Anderson case ARM::t2SUBri: 1640ca3f6a3925e9a6e91022aa211bdc1b6e3f2ff41fCameron Zwarich case ARM::t2SBCrr: 1641b485de5d8c3fe0c62c0b07f63f64bd10f6803c17Cameron Zwarich case ARM::t2SBCri: 1642b485de5d8c3fe0c62c0b07f63f64bd10f6803c17Cameron Zwarich case ARM::ANDrr: 1643b485de5d8c3fe0c62c0b07f63f64bd10f6803c17Cameron Zwarich case ARM::ANDri: 1644b485de5d8c3fe0c62c0b07f63f64bd10f6803c17Cameron Zwarich case ARM::t2ANDrr: 16450cb11ac32fc09c5db42fb801db242ac9fb51f6b1Cameron Zwarich case ARM::t2ANDri: 16460cb11ac32fc09c5db42fb801db242ac9fb51f6b1Cameron Zwarich case ARM::ORRrr: 16470cb11ac32fc09c5db42fb801db242ac9fb51f6b1Cameron Zwarich case ARM::ORRri: 16480cb11ac32fc09c5db42fb801db242ac9fb51f6b1Cameron Zwarich case ARM::t2ORRrr: 16490cb11ac32fc09c5db42fb801db242ac9fb51f6b1Cameron Zwarich case ARM::t2ORRri: 16500cb11ac32fc09c5db42fb801db242ac9fb51f6b1Cameron Zwarich case ARM::EORrr: 16510cb11ac32fc09c5db42fb801db242ac9fb51f6b1Cameron Zwarich case ARM::EORri: 16520cb11ac32fc09c5db42fb801db242ac9fb51f6b1Cameron Zwarich case ARM::t2EORrr: 16530cb11ac32fc09c5db42fb801db242ac9fb51f6b1Cameron Zwarich case ARM::t2EORri: { 16542c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng // Scan forward for the use of CPSR, if it's a conditional code requires 16552c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng // checking of V bit, then this is not safe to do. If we can't find the 16562c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng // CPSR use (i.e. used in another block), then it's not safe to perform 16572c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng // the optimization. 16582c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng bool isSafe = false; 16592c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng I = CmpInstr; 16602c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng E = MI->getParent()->end(); 16612c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng while (!isSafe && ++I != E) { 16622c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng const MachineInstr &Instr = *I; 16632c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng for (unsigned IO = 0, EO = Instr.getNumOperands(); 16642c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng !isSafe && IO != EO; ++IO) { 16652c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng const MachineOperand &MO = Instr.getOperand(IO); 16662c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng if (!MO.isReg() || MO.getReg() != ARM::CPSR) 16672c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng continue; 16682c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng if (MO.isDef()) { 16692c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng isSafe = true; 16702c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng break; 16712c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng } 16722c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng // Condition code is after the operand before CPSR. 16732c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng ARMCC::CondCodes CC = (ARMCC::CondCodes)Instr.getOperand(IO-1).getImm(); 16742c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng switch (CC) { 16752c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng default: 16762c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng isSafe = true; 16772c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng break; 16782c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng case ARMCC::VS: 16792c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng case ARMCC::VC: 16802c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng case ARMCC::GE: 16812c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng case ARMCC::LT: 16822c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng case ARMCC::GT: 16832c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng case ARMCC::LE: 16842c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng return false; 16852c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng } 16862c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng } 16872c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng } 16882c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng 16892c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng if (!isSafe) 16902c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng return false; 16912c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng 16923642e64c114e636548888c72c21ae023ee0121a7Evan Cheng // Toggle the optional operand to CPSR. 16933642e64c114e636548888c72c21ae023ee0121a7Evan Cheng MI->getOperand(5).setReg(ARM::CPSR); 16943642e64c114e636548888c72c21ae023ee0121a7Evan Cheng MI->getOperand(5).setIsDef(true); 1695e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling CmpInstr->eraseFromParent(); 1696e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling return true; 1697e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling } 1698b485de5d8c3fe0c62c0b07f63f64bd10f6803c17Cameron Zwarich } 1699e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling 1700e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling return false; 1701e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling} 17025f54ce347368105260be2cec497b6a4199dc5789Evan Cheng 1703c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Chengbool ARMBaseInstrInfo::FoldImmediate(MachineInstr *UseMI, 1704c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng MachineInstr *DefMI, unsigned Reg, 1705c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng MachineRegisterInfo *MRI) const { 1706c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng // Fold large immediates into add, sub, or, xor. 1707c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng unsigned DefOpc = DefMI->getOpcode(); 1708c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng if (DefOpc != ARM::t2MOVi32imm && DefOpc != ARM::MOVi32imm) 1709c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng return false; 1710c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng if (!DefMI->getOperand(1).isImm()) 1711c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng // Could be t2MOVi32imm <ga:xx> 1712c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng return false; 1713c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng 1714c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng if (!MRI->hasOneNonDBGUse(Reg)) 1715c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng return false; 1716c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng 1717c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng unsigned UseOpc = UseMI->getOpcode(); 17185c71c7a13715ed6f5bfdd5497172ddec316b68b0Evan Cheng unsigned NewUseOpc = 0; 1719c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng uint32_t ImmVal = (uint32_t)DefMI->getOperand(1).getImm(); 17205c71c7a13715ed6f5bfdd5497172ddec316b68b0Evan Cheng uint32_t SOImmValV1 = 0, SOImmValV2 = 0; 1721c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng bool Commute = false; 1722c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng switch (UseOpc) { 1723c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng default: return false; 1724c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::SUBrr: 1725c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::ADDrr: 1726c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::ORRrr: 1727c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::EORrr: 1728c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::t2SUBrr: 1729c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::t2ADDrr: 1730c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::t2ORRrr: 1731c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::t2EORrr: { 1732c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng Commute = UseMI->getOperand(2).getReg() != Reg; 1733c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng switch (UseOpc) { 1734c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng default: break; 1735c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::SUBrr: { 1736c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng if (Commute) 1737c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng return false; 1738c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng ImmVal = -ImmVal; 1739c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng NewUseOpc = ARM::SUBri; 1740c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng // Fallthrough 1741c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng } 1742c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::ADDrr: 1743c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::ORRrr: 1744c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::EORrr: { 1745c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng if (!ARM_AM::isSOImmTwoPartVal(ImmVal)) 1746c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng return false; 1747c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng SOImmValV1 = (uint32_t)ARM_AM::getSOImmTwoPartFirst(ImmVal); 1748c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng SOImmValV2 = (uint32_t)ARM_AM::getSOImmTwoPartSecond(ImmVal); 1749c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng switch (UseOpc) { 1750c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng default: break; 1751c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::ADDrr: NewUseOpc = ARM::ADDri; break; 1752c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::ORRrr: NewUseOpc = ARM::ORRri; break; 1753c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::EORrr: NewUseOpc = ARM::EORri; break; 1754c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng } 1755c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng break; 1756c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng } 1757c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::t2SUBrr: { 1758c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng if (Commute) 1759c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng return false; 1760c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng ImmVal = -ImmVal; 1761c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng NewUseOpc = ARM::t2SUBri; 1762c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng // Fallthrough 1763c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng } 1764c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::t2ADDrr: 1765c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::t2ORRrr: 1766c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::t2EORrr: { 1767c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng if (!ARM_AM::isT2SOImmTwoPartVal(ImmVal)) 1768c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng return false; 1769c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng SOImmValV1 = (uint32_t)ARM_AM::getT2SOImmTwoPartFirst(ImmVal); 1770c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng SOImmValV2 = (uint32_t)ARM_AM::getT2SOImmTwoPartSecond(ImmVal); 1771c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng switch (UseOpc) { 1772c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng default: break; 1773c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::t2ADDrr: NewUseOpc = ARM::t2ADDri; break; 1774c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::t2ORRrr: NewUseOpc = ARM::t2ORRri; break; 1775c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::t2EORrr: NewUseOpc = ARM::t2EORri; break; 1776c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng } 1777c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng break; 1778c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng } 1779c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng } 1780c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng } 1781c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng } 1782c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng 1783c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng unsigned OpIdx = Commute ? 2 : 1; 1784c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng unsigned Reg1 = UseMI->getOperand(OpIdx).getReg(); 1785c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng bool isKill = UseMI->getOperand(OpIdx).isKill(); 1786c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng unsigned NewReg = MRI->createVirtualRegister(MRI->getRegClass(Reg)); 1787c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng AddDefaultCC(AddDefaultPred(BuildMI(*UseMI->getParent(), 1788c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng *UseMI, UseMI->getDebugLoc(), 1789c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng get(NewUseOpc), NewReg) 1790c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng .addReg(Reg1, getKillRegState(isKill)) 1791c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng .addImm(SOImmValV1))); 1792c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng UseMI->setDesc(get(NewUseOpc)); 1793c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng UseMI->getOperand(1).setReg(NewReg); 1794c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng UseMI->getOperand(1).setIsKill(); 1795c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng UseMI->getOperand(2).ChangeToImmediate(SOImmValV2); 1796c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng DefMI->eraseFromParent(); 1797c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng return true; 1798c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng} 1799c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng 18005f54ce347368105260be2cec497b6a4199dc5789Evan Chengunsigned 18018239daf7c83a65a189c352cce3191cdc3bbfe151Evan ChengARMBaseInstrInfo::getNumMicroOps(const InstrItineraryData *ItinData, 18028239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng const MachineInstr *MI) const { 18033ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng if (!ItinData || ItinData->isEmpty()) 18045f54ce347368105260be2cec497b6a4199dc5789Evan Cheng return 1; 18055f54ce347368105260be2cec497b6a4199dc5789Evan Cheng 18065f54ce347368105260be2cec497b6a4199dc5789Evan Cheng const TargetInstrDesc &Desc = MI->getDesc(); 18075f54ce347368105260be2cec497b6a4199dc5789Evan Cheng unsigned Class = Desc.getSchedClass(); 1808064312de8641043b084603aa9a6b409bc794eed2Bob Wilson unsigned UOps = ItinData->Itineraries[Class].NumMicroOps; 18095f54ce347368105260be2cec497b6a4199dc5789Evan Cheng if (UOps) 18105f54ce347368105260be2cec497b6a4199dc5789Evan Cheng return UOps; 18115f54ce347368105260be2cec497b6a4199dc5789Evan Cheng 18125f54ce347368105260be2cec497b6a4199dc5789Evan Cheng unsigned Opc = MI->getOpcode(); 18135f54ce347368105260be2cec497b6a4199dc5789Evan Cheng switch (Opc) { 18145f54ce347368105260be2cec497b6a4199dc5789Evan Cheng default: 18155f54ce347368105260be2cec497b6a4199dc5789Evan Cheng llvm_unreachable("Unexpected multi-uops instruction!"); 18165f54ce347368105260be2cec497b6a4199dc5789Evan Cheng break; 181773fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMQIA: 181873fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMQIA: 18195f54ce347368105260be2cec497b6a4199dc5789Evan Cheng return 2; 18205f54ce347368105260be2cec497b6a4199dc5789Evan Cheng 18215f54ce347368105260be2cec497b6a4199dc5789Evan Cheng // The number of uOps for load / store multiple are determined by the number 18225f54ce347368105260be2cec497b6a4199dc5789Evan Cheng // registers. 18236e8f4c404825b79f9b9176483653f1aa927dfbdeAndrew Trick // 18243ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng // On Cortex-A8, each pair of register loads / stores can be scheduled on the 18253ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng // same cycle. The scheduling for the first load / store must be done 18263ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng // separately by assuming the the address is not 64-bit aligned. 182773fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling // 18283ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng // On Cortex-A9, the formula is simply (#reg / 2) + (#reg % 2). If the address 182973fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling // is not 64-bit aligned, then AGU would take an extra cycle. For VFP / NEON 183073fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling // load / store multiple, the formula is (#reg / 2) + (#reg % 2) + 1. 183173fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMDIA: 183273fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMDIA_UPD: 183373fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMDDB_UPD: 183473fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMSIA: 183573fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMSIA_UPD: 183673fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMSDB_UPD: 183773fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMDIA: 183873fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMDIA_UPD: 183973fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMDDB_UPD: 184073fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMSIA: 184173fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMSIA_UPD: 184273fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMSDB_UPD: { 18435f54ce347368105260be2cec497b6a4199dc5789Evan Cheng unsigned NumRegs = MI->getNumOperands() - Desc.getNumOperands(); 18445f54ce347368105260be2cec497b6a4199dc5789Evan Cheng return (NumRegs / 2) + (NumRegs % 2) + 1; 18455f54ce347368105260be2cec497b6a4199dc5789Evan Cheng } 184673fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling 184773fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMIA_RET: 184873fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMIA: 184973fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMDA: 185073fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMDB: 185173fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMIB: 185273fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMIA_UPD: 185373fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMDA_UPD: 185473fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMDB_UPD: 185573fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMIB_UPD: 185673fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::STMIA: 185773fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::STMDA: 185873fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::STMDB: 185973fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::STMIB: 186073fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::STMIA_UPD: 186173fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::STMDA_UPD: 186273fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::STMDB_UPD: 186373fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::STMIB_UPD: 186473fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::tLDMIA: 186573fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::tLDMIA_UPD: 186673fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::tSTMIA: 186773fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::tSTMIA_UPD: 18685f54ce347368105260be2cec497b6a4199dc5789Evan Cheng case ARM::tPOP_RET: 18695f54ce347368105260be2cec497b6a4199dc5789Evan Cheng case ARM::tPOP: 18705f54ce347368105260be2cec497b6a4199dc5789Evan Cheng case ARM::tPUSH: 187173fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2LDMIA_RET: 187273fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2LDMIA: 187373fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2LDMDB: 187473fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2LDMIA_UPD: 187573fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2LDMDB_UPD: 187673fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2STMIA: 187773fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2STMDB: 187873fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2STMIA_UPD: 187973fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2STMDB_UPD: { 18803ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng unsigned NumRegs = MI->getNumOperands() - Desc.getNumOperands() + 1; 18813ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng if (Subtarget.isCortexA8()) { 18828239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng if (NumRegs < 4) 18838239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng return 2; 18848239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng // 4 registers would be issued: 2, 2. 18858239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng // 5 registers would be issued: 2, 2, 1. 18868239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng UOps = (NumRegs / 2); 18878239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng if (NumRegs % 2) 18888239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng ++UOps; 18898239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng return UOps; 18903ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng } else if (Subtarget.isCortexA9()) { 18913ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng UOps = (NumRegs / 2); 18923ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng // If there are odd number of registers or if it's not 64-bit aligned, 18933ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng // then it takes an extra AGU (Address Generation Unit) cycle. 18943ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng if ((NumRegs % 2) || 18953ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng !MI->hasOneMemOperand() || 18963ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng (*MI->memoperands_begin())->getAlignment() < 8) 18973ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng ++UOps; 18983ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng return UOps; 18993ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng } else { 19003ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng // Assume the worst. 19013ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng return NumRegs; 19022bbb76909126db5bed6bde84b16d94ab5de4d372Michael J. Spencer } 19035f54ce347368105260be2cec497b6a4199dc5789Evan Cheng } 19045f54ce347368105260be2cec497b6a4199dc5789Evan Cheng } 19055f54ce347368105260be2cec497b6a4199dc5789Evan Cheng} 1906a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng 1907a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Chengint 1908344d9db97062736cd66da6c07baa9108b6cfa419Evan ChengARMBaseInstrInfo::getVLDMDefCycle(const InstrItineraryData *ItinData, 1909344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng const TargetInstrDesc &DefTID, 1910344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng unsigned DefClass, 1911344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng unsigned DefIdx, unsigned DefAlign) const { 1912344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng int RegNo = (int)(DefIdx+1) - DefTID.getNumOperands() + 1; 1913344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng if (RegNo <= 0) 1914344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // Def is the address writeback. 1915344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng return ItinData->getOperandCycle(DefClass, DefIdx); 1916344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng 1917344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng int DefCycle; 1918344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng if (Subtarget.isCortexA8()) { 1919344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // (regno / 2) + (regno % 2) + 1 1920344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng DefCycle = RegNo / 2 + 1; 1921344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng if (RegNo % 2) 1922344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng ++DefCycle; 1923344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng } else if (Subtarget.isCortexA9()) { 1924344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng DefCycle = RegNo; 1925344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng bool isSLoad = false; 192673fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling 1927344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng switch (DefTID.getOpcode()) { 1928344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng default: break; 192973fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMSIA: 193073fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMSIA_UPD: 193173fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMSDB_UPD: 1932344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng isSLoad = true; 1933344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng break; 1934344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng } 193573fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling 1936344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // If there are odd number of 'S' registers or if it's not 64-bit aligned, 1937344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // then it takes an extra cycle. 1938344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng if ((isSLoad && (RegNo % 2)) || DefAlign < 8) 1939344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng ++DefCycle; 1940344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng } else { 1941344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // Assume the worst. 1942344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng DefCycle = RegNo + 2; 1943344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng } 1944344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng 1945344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng return DefCycle; 1946344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng} 1947344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng 1948344d9db97062736cd66da6c07baa9108b6cfa419Evan Chengint 1949344d9db97062736cd66da6c07baa9108b6cfa419Evan ChengARMBaseInstrInfo::getLDMDefCycle(const InstrItineraryData *ItinData, 1950344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng const TargetInstrDesc &DefTID, 1951344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng unsigned DefClass, 1952344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng unsigned DefIdx, unsigned DefAlign) const { 1953344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng int RegNo = (int)(DefIdx+1) - DefTID.getNumOperands() + 1; 1954344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng if (RegNo <= 0) 1955344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // Def is the address writeback. 1956344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng return ItinData->getOperandCycle(DefClass, DefIdx); 1957344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng 1958344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng int DefCycle; 1959344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng if (Subtarget.isCortexA8()) { 1960344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // 4 registers would be issued: 1, 2, 1. 1961344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // 5 registers would be issued: 1, 2, 2. 1962344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng DefCycle = RegNo / 2; 1963344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng if (DefCycle < 1) 1964344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng DefCycle = 1; 1965344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // Result latency is issue cycle + 2: E2. 1966344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng DefCycle += 2; 1967344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng } else if (Subtarget.isCortexA9()) { 1968344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng DefCycle = (RegNo / 2); 1969344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // If there are odd number of registers or if it's not 64-bit aligned, 1970344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // then it takes an extra AGU (Address Generation Unit) cycle. 1971344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng if ((RegNo % 2) || DefAlign < 8) 1972344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng ++DefCycle; 1973344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // Result latency is AGU cycles + 2. 1974344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng DefCycle += 2; 1975344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng } else { 1976344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // Assume the worst. 1977344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng DefCycle = RegNo + 2; 1978344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng } 1979344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng 1980344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng return DefCycle; 1981344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng} 1982344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng 1983344d9db97062736cd66da6c07baa9108b6cfa419Evan Chengint 1984344d9db97062736cd66da6c07baa9108b6cfa419Evan ChengARMBaseInstrInfo::getVSTMUseCycle(const InstrItineraryData *ItinData, 1985344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng const TargetInstrDesc &UseTID, 1986344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng unsigned UseClass, 1987344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng unsigned UseIdx, unsigned UseAlign) const { 1988344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng int RegNo = (int)(UseIdx+1) - UseTID.getNumOperands() + 1; 1989344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng if (RegNo <= 0) 1990344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng return ItinData->getOperandCycle(UseClass, UseIdx); 1991344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng 1992344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng int UseCycle; 1993344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng if (Subtarget.isCortexA8()) { 1994344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // (regno / 2) + (regno % 2) + 1 1995344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng UseCycle = RegNo / 2 + 1; 1996344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng if (RegNo % 2) 1997344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng ++UseCycle; 1998344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng } else if (Subtarget.isCortexA9()) { 1999344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng UseCycle = RegNo; 2000344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng bool isSStore = false; 200173fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling 2002344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng switch (UseTID.getOpcode()) { 2003344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng default: break; 200473fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMSIA: 200573fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMSIA_UPD: 200673fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMSDB_UPD: 2007344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng isSStore = true; 2008344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng break; 2009344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng } 201073fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling 2011344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // If there are odd number of 'S' registers or if it's not 64-bit aligned, 2012344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // then it takes an extra cycle. 2013344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng if ((isSStore && (RegNo % 2)) || UseAlign < 8) 2014344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng ++UseCycle; 2015344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng } else { 2016344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // Assume the worst. 2017344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng UseCycle = RegNo + 2; 2018344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng } 2019344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng 2020344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng return UseCycle; 2021344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng} 2022344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng 2023344d9db97062736cd66da6c07baa9108b6cfa419Evan Chengint 2024344d9db97062736cd66da6c07baa9108b6cfa419Evan ChengARMBaseInstrInfo::getSTMUseCycle(const InstrItineraryData *ItinData, 2025344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng const TargetInstrDesc &UseTID, 2026344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng unsigned UseClass, 2027344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng unsigned UseIdx, unsigned UseAlign) const { 2028344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng int RegNo = (int)(UseIdx+1) - UseTID.getNumOperands() + 1; 2029344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng if (RegNo <= 0) 2030344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng return ItinData->getOperandCycle(UseClass, UseIdx); 2031344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng 2032344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng int UseCycle; 2033344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng if (Subtarget.isCortexA8()) { 2034344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng UseCycle = RegNo / 2; 2035344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng if (UseCycle < 2) 2036344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng UseCycle = 2; 2037344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // Read in E3. 2038344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng UseCycle += 2; 2039344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng } else if (Subtarget.isCortexA9()) { 2040344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng UseCycle = (RegNo / 2); 2041344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // If there are odd number of registers or if it's not 64-bit aligned, 2042344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // then it takes an extra AGU (Address Generation Unit) cycle. 2043344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng if ((RegNo % 2) || UseAlign < 8) 2044344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng ++UseCycle; 2045344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng } else { 2046344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // Assume the worst. 2047344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng UseCycle = 1; 2048344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng } 2049344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng return UseCycle; 2050344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng} 2051344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng 2052344d9db97062736cd66da6c07baa9108b6cfa419Evan Chengint 2053a0792de66c8364d47b0a688c7f408efb7b10f31bEvan ChengARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData, 2054a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng const TargetInstrDesc &DefTID, 2055a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng unsigned DefIdx, unsigned DefAlign, 2056a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng const TargetInstrDesc &UseTID, 2057a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng unsigned UseIdx, unsigned UseAlign) const { 2058a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng unsigned DefClass = DefTID.getSchedClass(); 2059a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng unsigned UseClass = UseTID.getSchedClass(); 2060a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng 2061a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng if (DefIdx < DefTID.getNumDefs() && UseIdx < UseTID.getNumOperands()) 2062a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx); 2063a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng 2064a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng // This may be a def / use of a variable_ops instruction, the operand 2065a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng // latency might be determinable dynamically. Let the target try to 2066a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng // figure it out. 20679e08ee5d16b596078e20787f0b5f36121f099333Evan Cheng int DefCycle = -1; 20687e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng bool LdmBypass = false; 2069a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng switch (DefTID.getOpcode()) { 2070a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng default: 2071a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng DefCycle = ItinData->getOperandCycle(DefClass, DefIdx); 2072a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng break; 207373fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling 207473fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMDIA: 207573fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMDIA_UPD: 207673fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMDDB_UPD: 207773fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMSIA: 207873fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMSIA_UPD: 207973fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMSDB_UPD: 2080344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng DefCycle = getVLDMDefCycle(ItinData, DefTID, DefClass, DefIdx, DefAlign); 20815a50ceeaea980962c1982ad535226c7ab06c971cEvan Cheng break; 208273fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling 208373fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMIA_RET: 208473fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMIA: 208573fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMDA: 208673fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMDB: 208773fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMIB: 208873fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMIA_UPD: 208973fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMDA_UPD: 209073fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMDB_UPD: 209173fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMIB_UPD: 209273fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::tLDMIA: 209373fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::tLDMIA_UPD: 2094a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng case ARM::tPUSH: 209573fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2LDMIA_RET: 209673fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2LDMIA: 209773fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2LDMDB: 209873fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2LDMIA_UPD: 209973fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2LDMDB_UPD: 2100a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng LdmBypass = 1; 2101344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng DefCycle = getLDMDefCycle(ItinData, DefTID, DefClass, DefIdx, DefAlign); 2102344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng break; 2103a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng } 2104a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng 2105a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng if (DefCycle == -1) 2106a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng // We can't seem to determine the result latency of the def, assume it's 2. 2107a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng DefCycle = 2; 2108a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng 2109a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng int UseCycle = -1; 2110a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng switch (UseTID.getOpcode()) { 2111a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng default: 2112a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng UseCycle = ItinData->getOperandCycle(UseClass, UseIdx); 2113a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng break; 211473fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling 211573fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMDIA: 211673fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMDIA_UPD: 211773fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMDDB_UPD: 211873fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMSIA: 211973fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMSIA_UPD: 212073fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMSDB_UPD: 2121344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng UseCycle = getVSTMUseCycle(ItinData, UseTID, UseClass, UseIdx, UseAlign); 21225a50ceeaea980962c1982ad535226c7ab06c971cEvan Cheng break; 212373fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling 212473fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::STMIA: 212573fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::STMDA: 212673fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::STMDB: 212773fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::STMIB: 212873fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::STMIA_UPD: 212973fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::STMDA_UPD: 213073fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::STMDB_UPD: 213173fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::STMIB_UPD: 213273fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::tSTMIA: 213373fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::tSTMIA_UPD: 2134a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng case ARM::tPOP_RET: 2135a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng case ARM::tPOP: 213673fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2STMIA: 213773fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2STMDB: 213873fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2STMIA_UPD: 213973fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2STMDB_UPD: 2140344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng UseCycle = getSTMUseCycle(ItinData, UseTID, UseClass, UseIdx, UseAlign); 21415a50ceeaea980962c1982ad535226c7ab06c971cEvan Cheng break; 2142a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng } 2143a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng 2144a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng if (UseCycle == -1) 2145a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng // Assume it's read in the first stage. 2146a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng UseCycle = 1; 2147a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng 2148a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng UseCycle = DefCycle - UseCycle + 1; 2149a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng if (UseCycle > 0) { 2150a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng if (LdmBypass) { 2151a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng // It's a variable_ops instruction so we can't use DefIdx here. Just use 2152a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng // first def operand. 2153a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng if (ItinData->hasPipelineForwarding(DefClass, DefTID.getNumOperands()-1, 2154a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng UseClass, UseIdx)) 2155a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng --UseCycle; 2156a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng } else if (ItinData->hasPipelineForwarding(DefClass, DefIdx, 215773fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling UseClass, UseIdx)) { 2158a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng --UseCycle; 215973fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling } 2160a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng } 2161a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng 2162a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng return UseCycle; 2163a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng} 2164a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng 2165a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Chengint 2166a0792de66c8364d47b0a688c7f408efb7b10f31bEvan ChengARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData, 2167a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng const MachineInstr *DefMI, unsigned DefIdx, 2168a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng const MachineInstr *UseMI, unsigned UseIdx) const { 2169a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng if (DefMI->isCopyLike() || DefMI->isInsertSubreg() || 2170a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng DefMI->isRegSequence() || DefMI->isImplicitDef()) 2171a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng return 1; 2172a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng 2173a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng const TargetInstrDesc &DefTID = DefMI->getDesc(); 2174a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng if (!ItinData || ItinData->isEmpty()) 2175a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng return DefTID.mayLoad() ? 3 : 1; 2176a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng 2177a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng const TargetInstrDesc &UseTID = UseMI->getDesc(); 2178dd9dd6f857604abdeb5213648ffe50c10ccc59b9Evan Cheng const MachineOperand &DefMO = DefMI->getOperand(DefIdx); 2179e09206d4d7683e2a421104c5cb83f7808ba4b06eEvan Cheng if (DefMO.getReg() == ARM::CPSR) { 2180e09206d4d7683e2a421104c5cb83f7808ba4b06eEvan Cheng if (DefMI->getOpcode() == ARM::FMSTAT) { 2181e09206d4d7683e2a421104c5cb83f7808ba4b06eEvan Cheng // fpscr -> cpsr stalls over 20 cycles on A8 (and earlier?) 2182e09206d4d7683e2a421104c5cb83f7808ba4b06eEvan Cheng return Subtarget.isCortexA9() ? 1 : 20; 2183e09206d4d7683e2a421104c5cb83f7808ba4b06eEvan Cheng } 2184e09206d4d7683e2a421104c5cb83f7808ba4b06eEvan Cheng 2185dd9dd6f857604abdeb5213648ffe50c10ccc59b9Evan Cheng // CPSR set and branch can be paired in the same cycle. 2186e09206d4d7683e2a421104c5cb83f7808ba4b06eEvan Cheng if (UseTID.isBranch()) 2187e09206d4d7683e2a421104c5cb83f7808ba4b06eEvan Cheng return 0; 2188e09206d4d7683e2a421104c5cb83f7808ba4b06eEvan Cheng } 2189dd9dd6f857604abdeb5213648ffe50c10ccc59b9Evan Cheng 2190a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng unsigned DefAlign = DefMI->hasOneMemOperand() 2191a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng ? (*DefMI->memoperands_begin())->getAlignment() : 0; 2192a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng unsigned UseAlign = UseMI->hasOneMemOperand() 2193a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng ? (*UseMI->memoperands_begin())->getAlignment() : 0; 21947e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng int Latency = getOperandLatency(ItinData, DefTID, DefIdx, DefAlign, 21957e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng UseTID, UseIdx, UseAlign); 21967e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng 21977e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng if (Latency > 1 && 21987e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng (Subtarget.isCortexA8() || Subtarget.isCortexA9())) { 21997e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng // FIXME: Shifter op hack: no shift (i.e. [r +/- r]) or [r + r << 2] 22007e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng // variants are one cycle cheaper. 22017e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng switch (DefTID.getOpcode()) { 22027e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng default: break; 22037e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng case ARM::LDRrs: 22047e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng case ARM::LDRBrs: { 22057e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng unsigned ShOpVal = DefMI->getOperand(3).getImm(); 22067e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal); 22077e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng if (ShImm == 0 || 22087e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng (ShImm == 2 && ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl)) 22097e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng --Latency; 22107e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng break; 22117e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng } 22127e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng case ARM::t2LDRs: 22137e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng case ARM::t2LDRBs: 22147e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng case ARM::t2LDRHs: 22157e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng case ARM::t2LDRSHs: { 22167e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng // Thumb2 mode: lsl only. 22177e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng unsigned ShAmt = DefMI->getOperand(3).getImm(); 22187e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng if (ShAmt == 0 || ShAmt == 2) 22197e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng --Latency; 22207e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng break; 22217e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng } 22227e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng } 22237e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng } 22247e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng 22257e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng return Latency; 2226a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng} 2227a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng 2228a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Chengint 2229a0792de66c8364d47b0a688c7f408efb7b10f31bEvan ChengARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData, 2230a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng SDNode *DefNode, unsigned DefIdx, 2231a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng SDNode *UseNode, unsigned UseIdx) const { 2232a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng if (!DefNode->isMachineOpcode()) 2233a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng return 1; 2234a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng 2235a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng const TargetInstrDesc &DefTID = get(DefNode->getMachineOpcode()); 2236c8bfd1d78ff9a307d1d4cb57cce4549b538e60f4Andrew Trick 2237c8bfd1d78ff9a307d1d4cb57cce4549b538e60f4Andrew Trick if (isZeroCost(DefTID.Opcode)) 2238c8bfd1d78ff9a307d1d4cb57cce4549b538e60f4Andrew Trick return 0; 2239c8bfd1d78ff9a307d1d4cb57cce4549b538e60f4Andrew Trick 2240a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng if (!ItinData || ItinData->isEmpty()) 2241a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng return DefTID.mayLoad() ? 3 : 1; 2242a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng 2243089751535d6e9adf65842e2ca5867bf9a70e1e95Evan Cheng if (!UseNode->isMachineOpcode()) { 2244089751535d6e9adf65842e2ca5867bf9a70e1e95Evan Cheng int Latency = ItinData->getOperandCycle(DefTID.getSchedClass(), DefIdx); 2245089751535d6e9adf65842e2ca5867bf9a70e1e95Evan Cheng if (Subtarget.isCortexA9()) 2246089751535d6e9adf65842e2ca5867bf9a70e1e95Evan Cheng return Latency <= 2 ? 1 : Latency - 1; 2247089751535d6e9adf65842e2ca5867bf9a70e1e95Evan Cheng else 2248089751535d6e9adf65842e2ca5867bf9a70e1e95Evan Cheng return Latency <= 3 ? 1 : Latency - 2; 2249089751535d6e9adf65842e2ca5867bf9a70e1e95Evan Cheng } 2250a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng 2251a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng const TargetInstrDesc &UseTID = get(UseNode->getMachineOpcode()); 2252a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng const MachineSDNode *DefMN = dyn_cast<MachineSDNode>(DefNode); 2253a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng unsigned DefAlign = !DefMN->memoperands_empty() 2254a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng ? (*DefMN->memoperands_begin())->getAlignment() : 0; 2255a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng const MachineSDNode *UseMN = dyn_cast<MachineSDNode>(UseNode); 2256a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng unsigned UseAlign = !UseMN->memoperands_empty() 2257a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng ? (*UseMN->memoperands_begin())->getAlignment() : 0; 22587e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng int Latency = getOperandLatency(ItinData, DefTID, DefIdx, DefAlign, 22597e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng UseTID, UseIdx, UseAlign); 22607e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng 22617e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng if (Latency > 1 && 22627e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng (Subtarget.isCortexA8() || Subtarget.isCortexA9())) { 22637e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng // FIXME: Shifter op hack: no shift (i.e. [r +/- r]) or [r + r << 2] 22647e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng // variants are one cycle cheaper. 22657e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng switch (DefTID.getOpcode()) { 22667e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng default: break; 22677e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng case ARM::LDRrs: 22687e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng case ARM::LDRBrs: { 22697e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng unsigned ShOpVal = 22707e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng cast<ConstantSDNode>(DefNode->getOperand(2))->getZExtValue(); 22717e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal); 22727e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng if (ShImm == 0 || 22737e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng (ShImm == 2 && ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl)) 22747e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng --Latency; 22757e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng break; 22767e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng } 22777e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng case ARM::t2LDRs: 22787e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng case ARM::t2LDRBs: 22797e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng case ARM::t2LDRHs: 22807e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng case ARM::t2LDRSHs: { 22817e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng // Thumb2 mode: lsl only. 22827e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng unsigned ShAmt = 22837e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng cast<ConstantSDNode>(DefNode->getOperand(2))->getZExtValue(); 22847e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng if (ShAmt == 0 || ShAmt == 2) 22857e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng --Latency; 22867e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng break; 22877e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng } 22887e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng } 22897e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng } 22907e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng 22917e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng return Latency; 2292a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng} 22932312842de0c641107dd04d7e056d02491cc781caEvan Cheng 22948239daf7c83a65a189c352cce3191cdc3bbfe151Evan Chengint ARMBaseInstrInfo::getInstrLatency(const InstrItineraryData *ItinData, 22958239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng const MachineInstr *MI, 22968239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng unsigned *PredCost) const { 22978239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng if (MI->isCopyLike() || MI->isInsertSubreg() || 22988239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng MI->isRegSequence() || MI->isImplicitDef()) 22998239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng return 1; 23008239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng 23018239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng if (!ItinData || ItinData->isEmpty()) 23028239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng return 1; 23038239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng 23048239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng const TargetInstrDesc &TID = MI->getDesc(); 23058239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng unsigned Class = TID.getSchedClass(); 23068239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng unsigned UOps = ItinData->Itineraries[Class].NumMicroOps; 23078239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng if (PredCost && TID.hasImplicitDefOfPhysReg(ARM::CPSR)) 23088239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng // When predicated, CPSR is an additional source operand for CPSR updating 23098239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng // instructions, this apparently increases their latencies. 23108239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng *PredCost = 1; 23118239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng if (UOps) 23128239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng return ItinData->getStageLatency(Class); 23138239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng return getNumMicroOps(ItinData, MI); 23148239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng} 23158239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng 23168239daf7c83a65a189c352cce3191cdc3bbfe151Evan Chengint ARMBaseInstrInfo::getInstrLatency(const InstrItineraryData *ItinData, 23178239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng SDNode *Node) const { 23188239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng if (!Node->isMachineOpcode()) 23198239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng return 1; 23208239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng 23218239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng if (!ItinData || ItinData->isEmpty()) 23228239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng return 1; 23238239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng 23248239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng unsigned Opcode = Node->getMachineOpcode(); 23258239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng switch (Opcode) { 23268239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng default: 23278239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng return ItinData->getStageLatency(get(Opcode).getSchedClass()); 232873fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMQIA: 232973fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMQIA: 23308239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng return 2; 23318b3ca6216d62bf3f729c2e122dcfeb7c4d7500dcEric Christopher } 23328239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng} 23338239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng 23342312842de0c641107dd04d7e056d02491cc781caEvan Chengbool ARMBaseInstrInfo:: 23352312842de0c641107dd04d7e056d02491cc781caEvan ChenghasHighOperandLatency(const InstrItineraryData *ItinData, 23362312842de0c641107dd04d7e056d02491cc781caEvan Cheng const MachineRegisterInfo *MRI, 23372312842de0c641107dd04d7e056d02491cc781caEvan Cheng const MachineInstr *DefMI, unsigned DefIdx, 23382312842de0c641107dd04d7e056d02491cc781caEvan Cheng const MachineInstr *UseMI, unsigned UseIdx) const { 23392312842de0c641107dd04d7e056d02491cc781caEvan Cheng unsigned DDomain = DefMI->getDesc().TSFlags & ARMII::DomainMask; 23402312842de0c641107dd04d7e056d02491cc781caEvan Cheng unsigned UDomain = UseMI->getDesc().TSFlags & ARMII::DomainMask; 23412312842de0c641107dd04d7e056d02491cc781caEvan Cheng if (Subtarget.isCortexA8() && 23422312842de0c641107dd04d7e056d02491cc781caEvan Cheng (DDomain == ARMII::DomainVFP || UDomain == ARMII::DomainVFP)) 23432312842de0c641107dd04d7e056d02491cc781caEvan Cheng // CortexA8 VFP instructions are not pipelined. 23442312842de0c641107dd04d7e056d02491cc781caEvan Cheng return true; 23452312842de0c641107dd04d7e056d02491cc781caEvan Cheng 23462312842de0c641107dd04d7e056d02491cc781caEvan Cheng // Hoist VFP / NEON instructions with 4 or higher latency. 23472312842de0c641107dd04d7e056d02491cc781caEvan Cheng int Latency = getOperandLatency(ItinData, DefMI, DefIdx, UseMI, UseIdx); 23482312842de0c641107dd04d7e056d02491cc781caEvan Cheng if (Latency <= 3) 23492312842de0c641107dd04d7e056d02491cc781caEvan Cheng return false; 23502312842de0c641107dd04d7e056d02491cc781caEvan Cheng return DDomain == ARMII::DomainVFP || DDomain == ARMII::DomainNEON || 23512312842de0c641107dd04d7e056d02491cc781caEvan Cheng UDomain == ARMII::DomainVFP || UDomain == ARMII::DomainNEON; 23522312842de0c641107dd04d7e056d02491cc781caEvan Cheng} 2353c8141dfc7f983cb04e65d8acd6bcbdc8e4b8a0aeEvan Cheng 2354c8141dfc7f983cb04e65d8acd6bcbdc8e4b8a0aeEvan Chengbool ARMBaseInstrInfo:: 2355c8141dfc7f983cb04e65d8acd6bcbdc8e4b8a0aeEvan ChenghasLowDefLatency(const InstrItineraryData *ItinData, 2356c8141dfc7f983cb04e65d8acd6bcbdc8e4b8a0aeEvan Cheng const MachineInstr *DefMI, unsigned DefIdx) const { 2357c8141dfc7f983cb04e65d8acd6bcbdc8e4b8a0aeEvan Cheng if (!ItinData || ItinData->isEmpty()) 2358c8141dfc7f983cb04e65d8acd6bcbdc8e4b8a0aeEvan Cheng return false; 2359c8141dfc7f983cb04e65d8acd6bcbdc8e4b8a0aeEvan Cheng 2360c8141dfc7f983cb04e65d8acd6bcbdc8e4b8a0aeEvan Cheng unsigned DDomain = DefMI->getDesc().TSFlags & ARMII::DomainMask; 2361c8141dfc7f983cb04e65d8acd6bcbdc8e4b8a0aeEvan Cheng if (DDomain == ARMII::DomainGeneral) { 2362c8141dfc7f983cb04e65d8acd6bcbdc8e4b8a0aeEvan Cheng unsigned DefClass = DefMI->getDesc().getSchedClass(); 2363c8141dfc7f983cb04e65d8acd6bcbdc8e4b8a0aeEvan Cheng int DefCycle = ItinData->getOperandCycle(DefClass, DefIdx); 2364c8141dfc7f983cb04e65d8acd6bcbdc8e4b8a0aeEvan Cheng return (DefCycle != -1 && DefCycle <= 2); 2365c8141dfc7f983cb04e65d8acd6bcbdc8e4b8a0aeEvan Cheng } 2366c8141dfc7f983cb04e65d8acd6bcbdc8e4b8a0aeEvan Cheng return false; 2367c8141dfc7f983cb04e65d8acd6bcbdc8e4b8a0aeEvan Cheng} 236848575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng 236948575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Chengbool 237048575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan ChengARMBaseInstrInfo::isFpMLxInstruction(unsigned Opcode, unsigned &MulOpc, 237148575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng unsigned &AddSubOpc, 237248575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng bool &NegAcc, bool &HasLane) const { 237348575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng DenseMap<unsigned, unsigned>::const_iterator I = MLxEntryMap.find(Opcode); 237448575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng if (I == MLxEntryMap.end()) 237548575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng return false; 237648575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng 237748575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng const ARM_MLxEntry &Entry = ARM_MLxTable[I->second]; 237848575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng MulOpc = Entry.MulOpc; 237948575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng AddSubOpc = Entry.AddSubOpc; 238048575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng NegAcc = Entry.NegAcc; 238148575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng HasLane = Entry.HasLane; 238248575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng return true; 238348575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng} 2384