ARMBaseInstrInfo.cpp revision 168f382dc67e5940cabdb28dc933c4f91cdd3137
131c24bf5b39cc8391d4cfdbf8cf5163975fdb81eJim Grosbach//===- ARMBaseInstrInfo.cpp - ARM Instruction Information -------*- C++ -*-===// 2334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// 3334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// The LLVM Compiler Infrastructure 4334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// 5334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// This file is distributed under the University of Illinois Open Source 6334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// License. See LICENSE.TXT for details. 7334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// 8334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin//===----------------------------------------------------------------------===// 9334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// 10334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// This file contains the Base ARM implementation of the TargetInstrInfo class. 11334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// 12334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin//===----------------------------------------------------------------------===// 13334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 14334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "ARMBaseInstrInfo.h" 15334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "ARM.h" 16334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "ARMAddressingModes.h" 17d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng#include "ARMConstantPoolValue.h" 18334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "ARMMachineFunctionInfo.h" 19f95215f551949d5e5adfbf4753aa833b9009b77aAnton Korobeynikov#include "ARMRegisterInfo.h" 204dbbe3433f7339ed277af55037ff6847f484e5abChris Lattner#include "ARMGenInstrInfo.inc" 21fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng#include "llvm/Constants.h" 22fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng#include "llvm/Function.h" 23fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng#include "llvm/GlobalValue.h" 24334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "llvm/ADT/STLExtras.h" 25334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "llvm/CodeGen/LiveVariables.h" 26d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng#include "llvm/CodeGen/MachineConstantPool.h" 27334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "llvm/CodeGen/MachineFrameInfo.h" 28334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "llvm/CodeGen/MachineInstrBuilder.h" 29334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "llvm/CodeGen/MachineJumpTableInfo.h" 30249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov#include "llvm/CodeGen/MachineMemOperand.h" 312457f2c66184e978d4ed8fa9e2128effff26cb0bEvan Cheng#include "llvm/CodeGen/MachineRegisterInfo.h" 32249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov#include "llvm/CodeGen/PseudoSourceValue.h" 33af76e592c7f9deff0e55c13dbb4a34f07f1c7f64Chris Lattner#include "llvm/MC/MCAsmInfo.h" 34334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "llvm/Support/CommandLine.h" 35f95215f551949d5e5adfbf4753aa833b9009b77aAnton Korobeynikov#include "llvm/Support/Debug.h" 36c25e7581b9b8088910da31702d4ca21c4734c6d7Torok Edwin#include "llvm/Support/ErrorHandling.h" 37334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinusing namespace llvm; 38334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 39334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinstatic cl::opt<bool> 40334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinEnableARM3Addr("enable-arm-3-addr-conv", cl::Hidden, 41334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin cl::desc("Enable ARM 2-addr to 3-addr conv")); 42334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 43f95215f551949d5e5adfbf4753aa833b9009b77aAnton KorobeynikovARMBaseInstrInfo::ARMBaseInstrInfo(const ARMSubtarget& STI) 44f95215f551949d5e5adfbf4753aa833b9009b77aAnton Korobeynikov : TargetInstrInfoImpl(ARMInsts, array_lengthof(ARMInsts)), 45f95215f551949d5e5adfbf4753aa833b9009b77aAnton Korobeynikov Subtarget(STI) { 46334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 47334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 48334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinMachineInstr * 49334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinARMBaseInstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI, 50334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineBasicBlock::iterator &MBBI, 51334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin LiveVariables *LV) const { 5278703ddafe3d037f75d8ca188e4829d238289ac3Evan Cheng // FIXME: Thumb2 support. 5378703ddafe3d037f75d8ca188e4829d238289ac3Evan Cheng 54334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (!EnableARM3Addr) 55334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return NULL; 56334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 57334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineInstr *MI = MBBI; 58334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineFunction &MF = *MI->getParent()->getParent(); 5999405df044f2c584242e711cc9023ec90356da82Bruno Cardoso Lopes uint64_t TSFlags = MI->getDesc().TSFlags; 60334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool isPre = false; 61334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin switch ((TSFlags & ARMII::IndexModeMask) >> ARMII::IndexModeShift) { 62334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin default: return NULL; 63334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMII::IndexModePre: 64334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin isPre = true; 65334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin break; 66334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMII::IndexModePost: 67334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin break; 68334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 69334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 70334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Try splitting an indexed load/store to an un-indexed one plus an add/sub 71334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // operation. 72334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned MemOpc = getUnindexedOpcode(MI->getOpcode()); 73334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (MemOpc == 0) 74334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return NULL; 75334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 76334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineInstr *UpdateMI = NULL; 77334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineInstr *MemMI = NULL; 78334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned AddrMode = (TSFlags & ARMII::AddrModeMask); 79334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const TargetInstrDesc &TID = MI->getDesc(); 80334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned NumOps = TID.getNumOperands(); 81334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool isLoad = !TID.mayStore(); 82334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const MachineOperand &WB = isLoad ? MI->getOperand(1) : MI->getOperand(0); 83334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const MachineOperand &Base = MI->getOperand(2); 84334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const MachineOperand &Offset = MI->getOperand(NumOps-3); 85334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned WBReg = WB.getReg(); 86334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned BaseReg = Base.getReg(); 87334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned OffReg = Offset.getReg(); 88334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned OffImm = MI->getOperand(NumOps-2).getImm(); 89334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin ARMCC::CondCodes Pred = (ARMCC::CondCodes)MI->getOperand(NumOps-1).getImm(); 90334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin switch (AddrMode) { 91334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin default: 92334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin assert(false && "Unknown indexed op!"); 93334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return NULL; 94334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMII::AddrMode2: { 95334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool isSub = ARM_AM::getAM2Op(OffImm) == ARM_AM::sub; 96334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned Amt = ARM_AM::getAM2Offset(OffImm); 97334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (OffReg == 0) { 98e7cbe4118b7ddf05032ff8772a98c51e1637bb5cEvan Cheng if (ARM_AM::getSOImmVal(Amt) == -1) 99334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Can't encode it in a so_imm operand. This transformation will 100334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // add more than 1 instruction. Abandon! 101334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return NULL; 102334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin UpdateMI = BuildMI(MF, MI->getDebugLoc(), 10378703ddafe3d037f75d8ca188e4829d238289ac3Evan Cheng get(isSub ? ARM::SUBri : ARM::ADDri), WBReg) 104e7cbe4118b7ddf05032ff8772a98c51e1637bb5cEvan Cheng .addReg(BaseReg).addImm(Amt) 105334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addImm(Pred).addReg(0).addReg(0); 106334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } else if (Amt != 0) { 107334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin ARM_AM::ShiftOpc ShOpc = ARM_AM::getAM2ShiftOpc(OffImm); 108334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned SOOpc = ARM_AM::getSORegOpc(ShOpc, Amt); 109334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin UpdateMI = BuildMI(MF, MI->getDebugLoc(), 11078703ddafe3d037f75d8ca188e4829d238289ac3Evan Cheng get(isSub ? ARM::SUBrs : ARM::ADDrs), WBReg) 111334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(BaseReg).addReg(OffReg).addReg(0).addImm(SOOpc) 112334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addImm(Pred).addReg(0).addReg(0); 113334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } else 114334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin UpdateMI = BuildMI(MF, MI->getDebugLoc(), 11578703ddafe3d037f75d8ca188e4829d238289ac3Evan Cheng get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg) 116334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(BaseReg).addReg(OffReg) 117334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addImm(Pred).addReg(0).addReg(0); 118334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin break; 119334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 120334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMII::AddrMode3 : { 121334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool isSub = ARM_AM::getAM3Op(OffImm) == ARM_AM::sub; 122334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned Amt = ARM_AM::getAM3Offset(OffImm); 123334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (OffReg == 0) 124334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Immediate is 8-bits. It's guaranteed to fit in a so_imm operand. 125334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin UpdateMI = BuildMI(MF, MI->getDebugLoc(), 12678703ddafe3d037f75d8ca188e4829d238289ac3Evan Cheng get(isSub ? ARM::SUBri : ARM::ADDri), WBReg) 127334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(BaseReg).addImm(Amt) 128334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addImm(Pred).addReg(0).addReg(0); 129334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin else 130334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin UpdateMI = BuildMI(MF, MI->getDebugLoc(), 13178703ddafe3d037f75d8ca188e4829d238289ac3Evan Cheng get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg) 132334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(BaseReg).addReg(OffReg) 133334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addImm(Pred).addReg(0).addReg(0); 134334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin break; 135334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 136334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 137334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 138334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin std::vector<MachineInstr*> NewMIs; 139334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (isPre) { 140334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (isLoad) 141334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MemMI = BuildMI(MF, MI->getDebugLoc(), 142334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin get(MemOpc), MI->getOperand(0).getReg()) 143334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(WBReg).addReg(0).addImm(0).addImm(Pred); 144334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin else 145334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MemMI = BuildMI(MF, MI->getDebugLoc(), 146334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin get(MemOpc)).addReg(MI->getOperand(1).getReg()) 147334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(WBReg).addReg(0).addImm(0).addImm(Pred); 148334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin NewMIs.push_back(MemMI); 149334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin NewMIs.push_back(UpdateMI); 150334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } else { 151334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (isLoad) 152334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MemMI = BuildMI(MF, MI->getDebugLoc(), 153334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin get(MemOpc), MI->getOperand(0).getReg()) 154334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred); 155334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin else 156334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MemMI = BuildMI(MF, MI->getDebugLoc(), 157334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin get(MemOpc)).addReg(MI->getOperand(1).getReg()) 158334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred); 159334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (WB.isDead()) 160334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin UpdateMI->getOperand(0).setIsDead(); 161334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin NewMIs.push_back(UpdateMI); 162334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin NewMIs.push_back(MemMI); 163334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 164334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 165334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Transfer LiveVariables states, kill / dead info. 166334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (LV) { 167334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 168334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineOperand &MO = MI->getOperand(i); 169334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (MO.isReg() && MO.getReg() && 170334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin TargetRegisterInfo::isVirtualRegister(MO.getReg())) { 171334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned Reg = MO.getReg(); 172334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 173334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin LiveVariables::VarInfo &VI = LV->getVarInfo(Reg); 174334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (MO.isDef()) { 175334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineInstr *NewMI = (Reg == WBReg) ? UpdateMI : MemMI; 176334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (MO.isDead()) 177334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin LV->addVirtualRegisterDead(Reg, NewMI); 178334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 179334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (MO.isUse() && MO.isKill()) { 180334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin for (unsigned j = 0; j < 2; ++j) { 181334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Look at the two new MI's in reverse order. 182334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineInstr *NewMI = NewMIs[j]; 183334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (!NewMI->readsRegister(Reg)) 184334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin continue; 185334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin LV->addVirtualRegisterKilled(Reg, NewMI); 186334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (VI.removeKill(MI)) 187334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin VI.Kills.push_back(NewMI); 188334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin break; 189334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 190334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 191334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 192334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 193334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 194334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 195334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MFI->insert(MBBI, NewMIs[1]); 196334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MFI->insert(MBBI, NewMIs[0]); 197334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return NewMIs[0]; 198334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 199334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 2002457f2c66184e978d4ed8fa9e2128effff26cb0bEvan Chengbool 2012457f2c66184e978d4ed8fa9e2128effff26cb0bEvan ChengARMBaseInstrInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB, 20218f30e6f5e80787808fe1455742452a5210afe07Jim Grosbach MachineBasicBlock::iterator MI, 20318f30e6f5e80787808fe1455742452a5210afe07Jim Grosbach const std::vector<CalleeSavedInfo> &CSI, 20418f30e6f5e80787808fe1455742452a5210afe07Jim Grosbach const TargetRegisterInfo *TRI) const { 2052457f2c66184e978d4ed8fa9e2128effff26cb0bEvan Cheng if (CSI.empty()) 2062457f2c66184e978d4ed8fa9e2128effff26cb0bEvan Cheng return false; 2072457f2c66184e978d4ed8fa9e2128effff26cb0bEvan Cheng 2082457f2c66184e978d4ed8fa9e2128effff26cb0bEvan Cheng DebugLoc DL; 2092457f2c66184e978d4ed8fa9e2128effff26cb0bEvan Cheng if (MI != MBB.end()) DL = MI->getDebugLoc(); 2102457f2c66184e978d4ed8fa9e2128effff26cb0bEvan Cheng 2112457f2c66184e978d4ed8fa9e2128effff26cb0bEvan Cheng for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 2122457f2c66184e978d4ed8fa9e2128effff26cb0bEvan Cheng unsigned Reg = CSI[i].getReg(); 2132457f2c66184e978d4ed8fa9e2128effff26cb0bEvan Cheng bool isKill = true; 2142457f2c66184e978d4ed8fa9e2128effff26cb0bEvan Cheng 2152457f2c66184e978d4ed8fa9e2128effff26cb0bEvan Cheng // Add the callee-saved register as live-in unless it's LR and 2162457f2c66184e978d4ed8fa9e2128effff26cb0bEvan Cheng // @llvm.returnaddress is called. If LR is returned for @llvm.returnaddress 2172457f2c66184e978d4ed8fa9e2128effff26cb0bEvan Cheng // then it's already added to the function and entry block live-in sets. 2182457f2c66184e978d4ed8fa9e2128effff26cb0bEvan Cheng if (Reg == ARM::LR) { 2192457f2c66184e978d4ed8fa9e2128effff26cb0bEvan Cheng MachineFunction &MF = *MBB.getParent(); 2202457f2c66184e978d4ed8fa9e2128effff26cb0bEvan Cheng if (MF.getFrameInfo()->isReturnAddressTaken() && 2212457f2c66184e978d4ed8fa9e2128effff26cb0bEvan Cheng MF.getRegInfo().isLiveIn(Reg)) 2222457f2c66184e978d4ed8fa9e2128effff26cb0bEvan Cheng isKill = false; 2232457f2c66184e978d4ed8fa9e2128effff26cb0bEvan Cheng } 2242457f2c66184e978d4ed8fa9e2128effff26cb0bEvan Cheng 2252457f2c66184e978d4ed8fa9e2128effff26cb0bEvan Cheng if (isKill) 2262457f2c66184e978d4ed8fa9e2128effff26cb0bEvan Cheng MBB.addLiveIn(Reg); 2272457f2c66184e978d4ed8fa9e2128effff26cb0bEvan Cheng 2282457f2c66184e978d4ed8fa9e2128effff26cb0bEvan Cheng // Insert the spill to the stack frame. The register is killed at the spill 2292457f2c66184e978d4ed8fa9e2128effff26cb0bEvan Cheng // 23042d075c4fb21995265961501cec9ff6e3fb497ceRafael Espindola const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); 2312457f2c66184e978d4ed8fa9e2128effff26cb0bEvan Cheng storeRegToStackSlot(MBB, MI, Reg, isKill, 23242d075c4fb21995265961501cec9ff6e3fb497ceRafael Espindola CSI[i].getFrameIdx(), RC, TRI); 2332457f2c66184e978d4ed8fa9e2128effff26cb0bEvan Cheng } 2342457f2c66184e978d4ed8fa9e2128effff26cb0bEvan Cheng return true; 2352457f2c66184e978d4ed8fa9e2128effff26cb0bEvan Cheng} 2362457f2c66184e978d4ed8fa9e2128effff26cb0bEvan Cheng 237334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// Branch analysis. 238334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinbool 239334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinARMBaseInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB, 240334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineBasicBlock *&FBB, 241334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin SmallVectorImpl<MachineOperand> &Cond, 242334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool AllowModify) const { 243334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // If the block has no terminators, it just falls into the block after it. 244334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineBasicBlock::iterator I = MBB.end(); 24593d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen if (I == MBB.begin()) 24693d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen return false; 24793d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen --I; 24893d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen while (I->isDebugValue()) { 24993d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen if (I == MBB.begin()) 25093d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen return false; 25193d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen --I; 25293d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen } 25393d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen if (!isUnpredicatedTerminator(I)) 254334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 255334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 256334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Get the last instruction in the block. 257334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineInstr *LastInst = I; 258334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 259334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // If there is only one terminator instruction, process it. 260334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned LastOpc = LastInst->getOpcode(); 261334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) { 2625ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng if (isUncondBranchOpcode(LastOpc)) { 263334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin TBB = LastInst->getOperand(0).getMBB(); 264334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 265334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 2665ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng if (isCondBranchOpcode(LastOpc)) { 267334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Block ends with fall-through condbranch. 268334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin TBB = LastInst->getOperand(0).getMBB(); 269334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin Cond.push_back(LastInst->getOperand(1)); 270334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin Cond.push_back(LastInst->getOperand(2)); 271334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 272334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 273334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; // Can't handle indirect branch. 274334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 275334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 276334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Get the instruction before it if it is a terminator. 277334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineInstr *SecondLastInst = I; 278334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 279334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // If there are three terminators, we don't know what sort of block this is. 280334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(--I)) 281334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; 282334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 2835ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng // If the block ends with a B and a Bcc, handle it. 284334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned SecondLastOpc = SecondLastInst->getOpcode(); 2855ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng if (isCondBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) { 286334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin TBB = SecondLastInst->getOperand(0).getMBB(); 287334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin Cond.push_back(SecondLastInst->getOperand(1)); 288334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin Cond.push_back(SecondLastInst->getOperand(2)); 289334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin FBB = LastInst->getOperand(0).getMBB(); 290334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 291334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 292334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 293334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // If the block ends with two unconditional branches, handle it. The second 294334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // one is not executed, so remove it. 2955ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng if (isUncondBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) { 296334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin TBB = SecondLastInst->getOperand(0).getMBB(); 297334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin I = LastInst; 298334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (AllowModify) 299334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin I->eraseFromParent(); 300334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 301334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 302334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 303334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // ...likewise if it ends with a branch table followed by an unconditional 304334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // branch. The branch folder can create these, and we must get rid of them for 305334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // correctness of Thumb constant islands. 3068d4de5abfa1bcd974554ea14904ebf7af289e84dBob Wilson if ((isJumpTableBranchOpcode(SecondLastOpc) || 3078d4de5abfa1bcd974554ea14904ebf7af289e84dBob Wilson isIndirectBranchOpcode(SecondLastOpc)) && 3085ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng isUncondBranchOpcode(LastOpc)) { 309334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin I = LastInst; 310334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (AllowModify) 311334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin I->eraseFromParent(); 312334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; 313334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 314334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 315334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Otherwise, can't handle this. 316334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; 317334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 318334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 319334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 320334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinunsigned ARMBaseInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const { 321334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineBasicBlock::iterator I = MBB.end(); 322334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (I == MBB.begin()) return 0; 323334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin --I; 32493d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen while (I->isDebugValue()) { 32593d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen if (I == MBB.begin()) 32693d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen return 0; 32793d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen --I; 32893d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen } 3295ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng if (!isUncondBranchOpcode(I->getOpcode()) && 3305ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng !isCondBranchOpcode(I->getOpcode())) 331334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 0; 332334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 333334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Remove the branch. 334334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin I->eraseFromParent(); 335334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 336334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin I = MBB.end(); 337334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 338334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (I == MBB.begin()) return 1; 339334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin --I; 3405ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng if (!isCondBranchOpcode(I->getOpcode())) 341334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 1; 342334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 343334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Remove the branch. 344334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin I->eraseFromParent(); 345334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 2; 346334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 347334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 348334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinunsigned 349334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinARMBaseInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 3503bf912593301152b65accb9d9c37a95172f1df5aStuart Hastings MachineBasicBlock *FBB, 3513bf912593301152b65accb9d9c37a95172f1df5aStuart Hastings const SmallVectorImpl<MachineOperand> &Cond, 3523bf912593301152b65accb9d9c37a95172f1df5aStuart Hastings DebugLoc DL) const { 3536495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ARMFunctionInfo *AFI = MBB.getParent()->getInfo<ARMFunctionInfo>(); 3546495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng int BOpc = !AFI->isThumbFunction() 3556495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ? ARM::B : (AFI->isThumb2Function() ? ARM::t2B : ARM::tB); 3566495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng int BccOpc = !AFI->isThumbFunction() 3576495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ? ARM::Bcc : (AFI->isThumb2Function() ? ARM::t2Bcc : ARM::tBcc); 358334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 359334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Shouldn't be a fall through. 360334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin assert(TBB && "InsertBranch must not be told to insert a fallthrough"); 361334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin assert((Cond.size() == 2 || Cond.size() == 0) && 362334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin "ARM branch conditions have two components!"); 363334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 364334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (FBB == 0) { 365334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (Cond.empty()) // Unconditional branch? 3663bf912593301152b65accb9d9c37a95172f1df5aStuart Hastings BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB); 367334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin else 3683bf912593301152b65accb9d9c37a95172f1df5aStuart Hastings BuildMI(&MBB, DL, get(BccOpc)).addMBB(TBB) 369334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()); 370334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 1; 371334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 372334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 373334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Two-way conditional branch. 3743bf912593301152b65accb9d9c37a95172f1df5aStuart Hastings BuildMI(&MBB, DL, get(BccOpc)).addMBB(TBB) 375334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()); 3763bf912593301152b65accb9d9c37a95172f1df5aStuart Hastings BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB); 377334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 2; 378334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 379334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 380334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinbool ARMBaseInstrInfo:: 381334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const { 382334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin ARMCC::CondCodes CC = (ARMCC::CondCodes)(int)Cond[0].getImm(); 383334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin Cond[0].setImm(ARMCC::getOppositeCondition(CC)); 384334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 385334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 386334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 387334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinbool ARMBaseInstrInfo:: 388334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinPredicateInstruction(MachineInstr *MI, 389334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const SmallVectorImpl<MachineOperand> &Pred) const { 390334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned Opc = MI->getOpcode(); 3915ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng if (isUncondBranchOpcode(Opc)) { 3925ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng MI->setDesc(get(getMatchingCondBranchOpcode(Opc))); 393334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI->addOperand(MachineOperand::CreateImm(Pred[0].getImm())); 394334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI->addOperand(MachineOperand::CreateReg(Pred[1].getReg(), false)); 395334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; 396334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 397334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 398334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin int PIdx = MI->findFirstPredOperandIdx(); 399334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (PIdx != -1) { 400334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineOperand &PMO = MI->getOperand(PIdx); 401334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin PMO.setImm(Pred[0].getImm()); 402334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI->getOperand(PIdx+1).setReg(Pred[1].getReg()); 403334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; 404334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 405334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 406334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 407334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 408334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinbool ARMBaseInstrInfo:: 409334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinSubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1, 410334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const SmallVectorImpl<MachineOperand> &Pred2) const { 411334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (Pred1.size() > 2 || Pred2.size() > 2) 412334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 413334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 414334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin ARMCC::CondCodes CC1 = (ARMCC::CondCodes)Pred1[0].getImm(); 415334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin ARMCC::CondCodes CC2 = (ARMCC::CondCodes)Pred2[0].getImm(); 416334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (CC1 == CC2) 417334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; 418334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 419334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin switch (CC1) { 420334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin default: 421334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 422334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMCC::AL: 423334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; 424334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMCC::HS: 425334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return CC2 == ARMCC::HI; 426334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMCC::LS: 427334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return CC2 == ARMCC::LO || CC2 == ARMCC::EQ; 428334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMCC::GE: 429334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return CC2 == ARMCC::GT; 430334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMCC::LE: 431334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return CC2 == ARMCC::LT; 432334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 433334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 434334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 435334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinbool ARMBaseInstrInfo::DefinesPredicate(MachineInstr *MI, 436334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin std::vector<MachineOperand> &Pred) const { 4378fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng // FIXME: This confuses implicit_def with optional CPSR def. 438334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const TargetInstrDesc &TID = MI->getDesc(); 439334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (!TID.getImplicitDefs() && !TID.hasOptionalDef()) 440334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 441334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 442334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool Found = false; 443334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 444334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const MachineOperand &MO = MI->getOperand(i); 445334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (MO.isReg() && MO.getReg() == ARM::CPSR) { 446334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin Pred.push_back(MO); 447334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin Found = true; 448334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 449334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 450334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 451334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return Found; 452334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 453334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 454ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng/// isPredicable - Return true if the specified instruction can be predicated. 455ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng/// By default, this returns true for every instruction with a 456ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng/// PredicateOperand. 457ac0869dc8a7986855c5557cc67d4709600158ef5Evan Chengbool ARMBaseInstrInfo::isPredicable(MachineInstr *MI) const { 458ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng const TargetInstrDesc &TID = MI->getDesc(); 459ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng if (!TID.isPredicable()) 460ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng return false; 461ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng 462ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng if ((TID.TSFlags & ARMII::DomainMask) == ARMII::DomainNEON) { 463ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng ARMFunctionInfo *AFI = 464ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng MI->getParent()->getParent()->getInfo<ARMFunctionInfo>(); 465d7f0810c934a7d13acb28c42d737ce58ec990ea8Evan Cheng return AFI->isThumb2Function(); 466ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng } 467ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng return true; 468ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng} 469334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 47056856b1f46ec1f073ceef4e826c544b8b1691608Chris Lattner/// FIXME: Works around a gcc miscompilation with -fstrict-aliasing. 47156856b1f46ec1f073ceef4e826c544b8b1691608Chris LattnerDISABLE_INLINE 472334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinstatic unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT, 47356856b1f46ec1f073ceef4e826c544b8b1691608Chris Lattner unsigned JTI); 474334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinstatic unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT, 475334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned JTI) { 47656856b1f46ec1f073ceef4e826c544b8b1691608Chris Lattner assert(JTI < JT.size()); 477334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return JT[JTI].MBBs.size(); 478334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 479334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 480334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin/// GetInstSize - Return the size of the specified MachineInstr. 481334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin/// 482334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinunsigned ARMBaseInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const { 483334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const MachineBasicBlock &MBB = *MI->getParent(); 484334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const MachineFunction *MF = MBB.getParent(); 48533adcfb4d217f5f23d9bde8ba02b8e48f9605fc5Chris Lattner const MCAsmInfo *MAI = MF->getTarget().getMCAsmInfo(); 486334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 487334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Basic size info comes from the TSFlags field. 488334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const TargetInstrDesc &TID = MI->getDesc(); 48999405df044f2c584242e711cc9023ec90356da82Bruno Cardoso Lopes uint64_t TSFlags = TID.TSFlags; 490334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 491a0ee862f2e3a0d202244e02459ddcf0dca0e8607Evan Cheng unsigned Opc = MI->getOpcode(); 492334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin switch ((TSFlags & ARMII::SizeMask) >> ARMII::SizeShift) { 493334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin default: { 494334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // If this machine instr is an inline asm, measure it. 495334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (MI->getOpcode() == ARM::INLINEASM) 49633adcfb4d217f5f23d9bde8ba02b8e48f9605fc5Chris Lattner return getInlineAsmLength(MI->getOperand(0).getSymbolName(), *MAI); 497334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (MI->isLabel()) 498334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 0; 499a0ee862f2e3a0d202244e02459ddcf0dca0e8607Evan Cheng switch (Opc) { 500334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin default: 501c23197a26f34f559ea9797de51e187087c039c42Torok Edwin llvm_unreachable("Unknown or unset size field for instr!"); 502518bb53485df640d7b7e3f6b0544099020c42aa7Chris Lattner case TargetOpcode::IMPLICIT_DEF: 503518bb53485df640d7b7e3f6b0544099020c42aa7Chris Lattner case TargetOpcode::KILL: 5047431beaba2a01c3fe299c861b2ec85cbf1dc81c4Bill Wendling case TargetOpcode::PROLOG_LABEL: 505518bb53485df640d7b7e3f6b0544099020c42aa7Chris Lattner case TargetOpcode::EH_LABEL: 506375be7730a6f3dee7a6dc319ee6c355a11ac99adDale Johannesen case TargetOpcode::DBG_VALUE: 507334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 0; 508334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 509334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin break; 510334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 511789476240d6b6f8ad9366cadf790a82bd41bb0b3Evan Cheng case ARMII::Size8Bytes: return 8; // ARM instruction x 2. 512789476240d6b6f8ad9366cadf790a82bd41bb0b3Evan Cheng case ARMII::Size4Bytes: return 4; // ARM / Thumb2 instruction. 513789476240d6b6f8ad9366cadf790a82bd41bb0b3Evan Cheng case ARMII::Size2Bytes: return 2; // Thumb1 instruction. 514334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMII::SizeSpecial: { 515a0ee862f2e3a0d202244e02459ddcf0dca0e8607Evan Cheng switch (Opc) { 516334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARM::CONSTPOOL_ENTRY: 517334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // If this machine instr is a constant pool entry, its size is recorded as 518334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // operand #2. 519334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return MI->getOperand(2).getImm(); 5205eb195153950bc7ebfc30649494a78b2096b5ef8Jim Grosbach case ARM::Int_eh_sjlj_longjmp: 5215eb195153950bc7ebfc30649494a78b2096b5ef8Jim Grosbach return 16; 5225eb195153950bc7ebfc30649494a78b2096b5ef8Jim Grosbach case ARM::tInt_eh_sjlj_longjmp: 5235eb195153950bc7ebfc30649494a78b2096b5ef8Jim Grosbach return 10; 524789476240d6b6f8ad9366cadf790a82bd41bb0b3Evan Cheng case ARM::Int_eh_sjlj_setjmp: 525d100755bab38784703f677b8b8eb174b624b346bJim Grosbach case ARM::Int_eh_sjlj_setjmp_nofp: 5260798eddd07b8dc827a4e6e9028c4c3a8d9444286Jim Grosbach return 20; 527d122874996a6faa8832569b632fd73a32ace7ae7Jim Grosbach case ARM::tInt_eh_sjlj_setjmp: 5285aa1684e5da9a85286bf7d29da419d261a70c2f2Jim Grosbach case ARM::t2Int_eh_sjlj_setjmp: 529d100755bab38784703f677b8b8eb174b624b346bJim Grosbach case ARM::t2Int_eh_sjlj_setjmp_nofp: 5300798eddd07b8dc827a4e6e9028c4c3a8d9444286Jim Grosbach return 12; 531334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARM::BR_JTr: 532334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARM::BR_JTm: 533334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARM::BR_JTadd: 534a0ee862f2e3a0d202244e02459ddcf0dca0e8607Evan Cheng case ARM::tBR_JTr: 535d26b14c34cbcee1448b86b524578fc51cc979023Evan Cheng case ARM::t2BR_JT: 536d26b14c34cbcee1448b86b524578fc51cc979023Evan Cheng case ARM::t2TBB: 537d26b14c34cbcee1448b86b524578fc51cc979023Evan Cheng case ARM::t2TBH: { 538334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // These are jumptable branches, i.e. a branch followed by an inlined 539d26b14c34cbcee1448b86b524578fc51cc979023Evan Cheng // jumptable. The size is 4 + 4 * number of entries. For TBB, each 540d26b14c34cbcee1448b86b524578fc51cc979023Evan Cheng // entry is one byte; TBH two byte each. 541a0ee862f2e3a0d202244e02459ddcf0dca0e8607Evan Cheng unsigned EntrySize = (Opc == ARM::t2TBB) 542a0ee862f2e3a0d202244e02459ddcf0dca0e8607Evan Cheng ? 1 : ((Opc == ARM::t2TBH) ? 2 : 4); 543334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned NumOps = TID.getNumOperands(); 544334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineOperand JTOP = 545334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI->getOperand(NumOps - (TID.isPredicable() ? 3 : 2)); 546334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned JTI = JTOP.getIndex(); 547334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo(); 548b1e803985d3378538ae9cff7eed4102c002d1e22Chris Lattner assert(MJTI != 0); 549334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables(); 550334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin assert(JTI < JT.size()); 551334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Thumb instructions are 2 byte aligned, but JT entries are 4 byte 552334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // 4 aligned. The assembler / linker may add 2 byte padding just before 553334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // the JT entries. The size does not include this padding; the 554334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // constant islands pass does separate bookkeeping for it. 555334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // FIXME: If we know the size of the function is less than (1 << 16) *2 556334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // bytes, we can use 16-bit entries instead. Then there won't be an 557334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // alignment issue. 55825f7cfc3cccba6f569f29f79ea533bae960b93c0Evan Cheng unsigned InstSize = (Opc == ARM::tBR_JTr || Opc == ARM::t2BR_JT) ? 2 : 4; 55925f7cfc3cccba6f569f29f79ea533bae960b93c0Evan Cheng unsigned NumEntries = getNumJTEntries(JT, JTI); 56025f7cfc3cccba6f569f29f79ea533bae960b93c0Evan Cheng if (Opc == ARM::t2TBB && (NumEntries & 1)) 56125f7cfc3cccba6f569f29f79ea533bae960b93c0Evan Cheng // Make sure the instruction that follows TBB is 2-byte aligned. 56225f7cfc3cccba6f569f29f79ea533bae960b93c0Evan Cheng // FIXME: Constant island pass should insert an "ALIGN" instruction 56325f7cfc3cccba6f569f29f79ea533bae960b93c0Evan Cheng // instead. 56425f7cfc3cccba6f569f29f79ea533bae960b93c0Evan Cheng ++NumEntries; 56525f7cfc3cccba6f569f29f79ea533bae960b93c0Evan Cheng return NumEntries * EntrySize + InstSize; 566334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 567334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin default: 568334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Otherwise, pseudo-instruction sizes are zero. 569334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 0; 570334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 571334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 572334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 573334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 0; // Not reached 574334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 575334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 576764ab52dd80310a205c9888bf166d09dab858f90Jim Grosbachunsigned 577334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinARMBaseInstrInfo::isLoadFromStackSlot(const MachineInstr *MI, 578334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin int &FrameIndex) const { 579dced03fc846fa7cd9558ecb8e33ca98ec29bdcf0Evan Cheng switch (MI->getOpcode()) { 580dced03fc846fa7cd9558ecb8e33ca98ec29bdcf0Evan Cheng default: break; 581dced03fc846fa7cd9558ecb8e33ca98ec29bdcf0Evan Cheng case ARM::LDR: 582dced03fc846fa7cd9558ecb8e33ca98ec29bdcf0Evan Cheng case ARM::t2LDRs: // FIXME: don't use t2LDRs to access frame. 583334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (MI->getOperand(1).isFI() && 584334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI->getOperand(2).isReg() && 585334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI->getOperand(3).isImm() && 586334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI->getOperand(2).getReg() == 0 && 587334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI->getOperand(3).getImm() == 0) { 588334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin FrameIndex = MI->getOperand(1).getIndex(); 589334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return MI->getOperand(0).getReg(); 590334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 591dced03fc846fa7cd9558ecb8e33ca98ec29bdcf0Evan Cheng break; 592dced03fc846fa7cd9558ecb8e33ca98ec29bdcf0Evan Cheng case ARM::t2LDRi12: 593dced03fc846fa7cd9558ecb8e33ca98ec29bdcf0Evan Cheng case ARM::tRestore: 5945ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin if (MI->getOperand(1).isFI() && 5955ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin MI->getOperand(2).isImm() && 5965ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin MI->getOperand(2).getImm() == 0) { 5975ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin FrameIndex = MI->getOperand(1).getIndex(); 5985ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin return MI->getOperand(0).getReg(); 5995ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin } 600dced03fc846fa7cd9558ecb8e33ca98ec29bdcf0Evan Cheng break; 601e5165490b7ba24bb2f3043399e0d60e7f3bcf8a5Jim Grosbach case ARM::VLDRD: 602e5165490b7ba24bb2f3043399e0d60e7f3bcf8a5Jim Grosbach case ARM::VLDRS: 603334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (MI->getOperand(1).isFI() && 604334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI->getOperand(2).isImm() && 605334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI->getOperand(2).getImm() == 0) { 606334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin FrameIndex = MI->getOperand(1).getIndex(); 607334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return MI->getOperand(0).getReg(); 608334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 609dced03fc846fa7cd9558ecb8e33ca98ec29bdcf0Evan Cheng break; 610334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 611334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 612334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 0; 613334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 614334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 615334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinunsigned 616334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinARMBaseInstrInfo::isStoreToStackSlot(const MachineInstr *MI, 617334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin int &FrameIndex) const { 618dced03fc846fa7cd9558ecb8e33ca98ec29bdcf0Evan Cheng switch (MI->getOpcode()) { 619dced03fc846fa7cd9558ecb8e33ca98ec29bdcf0Evan Cheng default: break; 620dced03fc846fa7cd9558ecb8e33ca98ec29bdcf0Evan Cheng case ARM::STR: 621dced03fc846fa7cd9558ecb8e33ca98ec29bdcf0Evan Cheng case ARM::t2STRs: // FIXME: don't use t2STRs to access frame. 622334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (MI->getOperand(1).isFI() && 623334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI->getOperand(2).isReg() && 624334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI->getOperand(3).isImm() && 625334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI->getOperand(2).getReg() == 0 && 626334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI->getOperand(3).getImm() == 0) { 627334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin FrameIndex = MI->getOperand(1).getIndex(); 628334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return MI->getOperand(0).getReg(); 629334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 630dced03fc846fa7cd9558ecb8e33ca98ec29bdcf0Evan Cheng break; 631dced03fc846fa7cd9558ecb8e33ca98ec29bdcf0Evan Cheng case ARM::t2STRi12: 632dced03fc846fa7cd9558ecb8e33ca98ec29bdcf0Evan Cheng case ARM::tSpill: 6335ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin if (MI->getOperand(1).isFI() && 6345ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin MI->getOperand(2).isImm() && 6355ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin MI->getOperand(2).getImm() == 0) { 6365ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin FrameIndex = MI->getOperand(1).getIndex(); 6375ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin return MI->getOperand(0).getReg(); 6385ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin } 639dced03fc846fa7cd9558ecb8e33ca98ec29bdcf0Evan Cheng break; 640e5165490b7ba24bb2f3043399e0d60e7f3bcf8a5Jim Grosbach case ARM::VSTRD: 641e5165490b7ba24bb2f3043399e0d60e7f3bcf8a5Jim Grosbach case ARM::VSTRS: 642334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (MI->getOperand(1).isFI() && 643334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI->getOperand(2).isImm() && 644334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI->getOperand(2).getImm() == 0) { 645334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin FrameIndex = MI->getOperand(1).getIndex(); 646334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return MI->getOperand(0).getReg(); 647334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 648dced03fc846fa7cd9558ecb8e33ca98ec29bdcf0Evan Cheng break; 649334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 650334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 651334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 0; 652334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 653334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 654ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesenvoid ARMBaseInstrInfo::copyPhysReg(MachineBasicBlock &MBB, 655ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen MachineBasicBlock::iterator I, DebugLoc DL, 656ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen unsigned DestReg, unsigned SrcReg, 657ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen bool KillSrc) const { 658ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen bool GPRDest = ARM::GPRRegClass.contains(DestReg); 659ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen bool GPRSrc = ARM::GPRRegClass.contains(SrcReg); 660ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen 661ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen if (GPRDest && GPRSrc) { 662ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen AddDefaultCC(AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::MOVr), DestReg) 663ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen .addReg(SrcReg, getKillRegState(KillSrc)))); 664ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen return; 6657bfdca0206f51132b26094c6f83a5ac97ee0f943David Goodwin } 666334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 667ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen bool SPRDest = ARM::SPRRegClass.contains(DestReg); 668ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen bool SPRSrc = ARM::SPRRegClass.contains(SrcReg); 669ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen 670ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen unsigned Opc; 671ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen if (SPRDest && SPRSrc) 672ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen Opc = ARM::VMOVS; 673ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen else if (GPRDest && SPRSrc) 674ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen Opc = ARM::VMOVRS; 675ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen else if (SPRDest && GPRSrc) 676ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen Opc = ARM::VMOVSR; 677ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen else if (ARM::DPRRegClass.contains(DestReg, SrcReg)) 678ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen Opc = ARM::VMOVD; 679ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen else if (ARM::QPRRegClass.contains(DestReg, SrcReg)) 680ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen Opc = ARM::VMOVQ; 681ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen else if (ARM::QQPRRegClass.contains(DestReg, SrcReg)) 682ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen Opc = ARM::VMOVQQ; 683ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen else if (ARM::QQQQPRRegClass.contains(DestReg, SrcReg)) 684ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen Opc = ARM::VMOVQQQQ; 685ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen else 686ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen llvm_unreachable("Impossible reg-to-reg copy"); 687ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen 688ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc), DestReg); 689ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen MIB.addReg(SrcReg, getKillRegState(KillSrc)); 690ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen if (Opc != ARM::VMOVQQ && Opc != ARM::VMOVQQQQ) 691ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen AddDefaultPred(MIB); 692334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 693334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 694c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Chengstatic const 695c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan ChengMachineInstrBuilder &AddDReg(MachineInstrBuilder &MIB, 696c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Cheng unsigned Reg, unsigned SubIdx, unsigned State, 697c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Cheng const TargetRegisterInfo *TRI) { 698c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Cheng if (!SubIdx) 699c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Cheng return MIB.addReg(Reg, State); 700c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Cheng 701c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Cheng if (TargetRegisterInfo::isPhysicalRegister(Reg)) 702c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Cheng return MIB.addReg(TRI->getSubReg(Reg, SubIdx), State); 703c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Cheng return MIB.addReg(Reg, State, SubIdx); 704c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Cheng} 705c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Cheng 706334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinvoid ARMBaseInstrInfo:: 707334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinstoreRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 708334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned SrcReg, bool isKill, int FI, 709746ad69e088176819981b4b2c5ac8dcd49f5e60eEvan Cheng const TargetRegisterClass *RC, 710746ad69e088176819981b4b2c5ac8dcd49f5e60eEvan Cheng const TargetRegisterInfo *TRI) const { 711c7f3ace20c325521c68335a1689645b43b06ddf0Chris Lattner DebugLoc DL; 712334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (I != MBB.end()) DL = I->getDebugLoc(); 713249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MachineFunction &MF = *MBB.getParent(); 714249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MachineFrameInfo &MFI = *MF.getFrameInfo(); 71531bc849123011b8eae6bb3c79876d9a3c26a6a1dJim Grosbach unsigned Align = MFI.getObjectAlignment(FI); 716249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov 717249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MachineMemOperand *MMO = 718ff89dcb06fbd103373436e2d0ae85f252fae2254Evan Cheng MF.getMachineMemOperand(PseudoSourceValue::getFixedStack(FI), 719249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MachineMemOperand::MOStore, 0, 720249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MFI.getObjectSize(FI), 72131bc849123011b8eae6bb3c79876d9a3c26a6a1dJim Grosbach Align); 722334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 7230eb0c7401c34c0b4604f732ce54db995eead14e6Bob Wilson // tGPR is used sometimes in ARM instructions that need to avoid using 7246ccfc507dc1f7ad8c8964193a2407264ca644f0dJim Grosbach // certain registers. Just treat it as GPR here. Likewise, rGPR. 7256ccfc507dc1f7ad8c8964193a2407264ca644f0dJim Grosbach if (RC == ARM::tGPRRegisterClass || RC == ARM::tcGPRRegisterClass 7266ccfc507dc1f7ad8c8964193a2407264ca644f0dJim Grosbach || RC == ARM::rGPRRegisterClass) 7270eb0c7401c34c0b4604f732ce54db995eead14e6Bob Wilson RC = ARM::GPRRegisterClass; 7280eb0c7401c34c0b4604f732ce54db995eead14e6Bob Wilson 729ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson switch (RC->getID()) { 730ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson case ARM::GPRRegClassID: 7315732ca084aaa0cd26149e50dd4b487efff37fe41Evan Cheng AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::STR)) 732334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(SrcReg, getKillRegState(isKill)) 733249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov .addFrameIndex(FI).addReg(0).addImm(0).addMemOperand(MMO)); 734ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson break; 735ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson case ARM::SPRRegClassID: 736d31c5496d7e1580058b5c6fbc8fd537a641ea590Evan Cheng AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTRS)) 737d31c5496d7e1580058b5c6fbc8fd537a641ea590Evan Cheng .addReg(SrcReg, getKillRegState(isKill)) 738d31c5496d7e1580058b5c6fbc8fd537a641ea590Evan Cheng .addFrameIndex(FI).addImm(0).addMemOperand(MMO)); 739ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson break; 740ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson case ARM::DPRRegClassID: 741ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson case ARM::DPR_VFP2RegClassID: 742ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson case ARM::DPR_8RegClassID: 743e5165490b7ba24bb2f3043399e0d60e7f3bcf8a5Jim Grosbach AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTRD)) 744334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(SrcReg, getKillRegState(isKill)) 745249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov .addFrameIndex(FI).addImm(0).addMemOperand(MMO)); 746ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson break; 747ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson case ARM::QPRRegClassID: 748ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson case ARM::QPR_VFP2RegClassID: 749ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson case ARM::QPR_8RegClassID: 7500cfcf93c95af91e809ef740eb0ab368477226b40Jim Grosbach if (Align >= 16 && getRegisterInfo().needsStackRealignment(MF)) { 751168f382dc67e5940cabdb28dc933c4f91cdd3137Bob Wilson AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1q64Pseudo)) 752f967ca0eaf30325cabe3c1971bf0dba16cf1b027Bob Wilson .addFrameIndex(FI).addImm(16) 75369b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng .addReg(SrcReg, getKillRegState(isKill)) 75469b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng .addMemOperand(MMO)); 75531bc849123011b8eae6bb3c79876d9a3c26a6a1dJim Grosbach } else { 75669b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMQ)) 75769b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng .addReg(SrcReg, getKillRegState(isKill)) 75869b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng .addFrameIndex(FI) 759d4bfd54ec2947e73ab152c3c548e4dd4beb700baBob Wilson .addImm(ARM_AM::getAM4ModeImm(ARM_AM::ia)) 76069b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng .addMemOperand(MMO)); 76131bc849123011b8eae6bb3c79876d9a3c26a6a1dJim Grosbach } 762ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson break; 763ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson case ARM::QQPRRegClassID: 764ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson case ARM::QQPR_VFP2RegClassID: 765435d4991779d6a47cadff4ea670b490d8507d6c4Evan Cheng if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) { 76622c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng // FIXME: It's possible to only store part of the QQ register if the 76722c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng // spilled def has a sub-register index. 768168f382dc67e5940cabdb28dc933c4f91cdd3137Bob Wilson AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1d64QPseudo)) 769168f382dc67e5940cabdb28dc933c4f91cdd3137Bob Wilson .addFrameIndex(FI).addImm(16) 770168f382dc67e5940cabdb28dc933c4f91cdd3137Bob Wilson .addReg(SrcReg, getKillRegState(isKill)) 771168f382dc67e5940cabdb28dc933c4f91cdd3137Bob Wilson .addMemOperand(MMO)); 772435d4991779d6a47cadff4ea670b490d8507d6c4Evan Cheng } else { 773435d4991779d6a47cadff4ea670b490d8507d6c4Evan Cheng MachineInstrBuilder MIB = 774435d4991779d6a47cadff4ea670b490d8507d6c4Evan Cheng AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMD)) 775435d4991779d6a47cadff4ea670b490d8507d6c4Evan Cheng .addFrameIndex(FI) 776d4bfd54ec2947e73ab152c3c548e4dd4beb700baBob Wilson .addImm(ARM_AM::getAM4ModeImm(ARM_AM::ia))) 777435d4991779d6a47cadff4ea670b490d8507d6c4Evan Cheng .addMemOperand(MMO); 778558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI); 779558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI); 780558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI); 781558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI); 782435d4991779d6a47cadff4ea670b490d8507d6c4Evan Cheng } 783ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson break; 784ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson case ARM::QQQQPRRegClassID: { 78522c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng MachineInstrBuilder MIB = 78622c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMD)) 78722c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng .addFrameIndex(FI) 788d4bfd54ec2947e73ab152c3c548e4dd4beb700baBob Wilson .addImm(ARM_AM::getAM4ModeImm(ARM_AM::ia))) 78922c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng .addMemOperand(MMO); 790558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI); 791558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI); 792558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI); 793558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen MIB = AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI); 794558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen MIB = AddDReg(MIB, SrcReg, ARM::dsub_4, 0, TRI); 795558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen MIB = AddDReg(MIB, SrcReg, ARM::dsub_5, 0, TRI); 796558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen MIB = AddDReg(MIB, SrcReg, ARM::dsub_6, 0, TRI); 797558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen AddDReg(MIB, SrcReg, ARM::dsub_7, 0, TRI); 798ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson break; 799ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson } 800ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson default: 801ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson llvm_unreachable("Unknown regclass!"); 802334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 803334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 804334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 805334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinvoid ARMBaseInstrInfo:: 806334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinloadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 807334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned DestReg, int FI, 808746ad69e088176819981b4b2c5ac8dcd49f5e60eEvan Cheng const TargetRegisterClass *RC, 809746ad69e088176819981b4b2c5ac8dcd49f5e60eEvan Cheng const TargetRegisterInfo *TRI) const { 810c7f3ace20c325521c68335a1689645b43b06ddf0Chris Lattner DebugLoc DL; 811334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (I != MBB.end()) DL = I->getDebugLoc(); 812249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MachineFunction &MF = *MBB.getParent(); 813249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MachineFrameInfo &MFI = *MF.getFrameInfo(); 81431bc849123011b8eae6bb3c79876d9a3c26a6a1dJim Grosbach unsigned Align = MFI.getObjectAlignment(FI); 815249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MachineMemOperand *MMO = 816ff89dcb06fbd103373436e2d0ae85f252fae2254Evan Cheng MF.getMachineMemOperand(PseudoSourceValue::getFixedStack(FI), 817249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MachineMemOperand::MOLoad, 0, 818249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MFI.getObjectSize(FI), 81931bc849123011b8eae6bb3c79876d9a3c26a6a1dJim Grosbach Align); 820334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 8210eb0c7401c34c0b4604f732ce54db995eead14e6Bob Wilson // tGPR is used sometimes in ARM instructions that need to avoid using 8220eb0c7401c34c0b4604f732ce54db995eead14e6Bob Wilson // certain registers. Just treat it as GPR here. 8236ccfc507dc1f7ad8c8964193a2407264ca644f0dJim Grosbach if (RC == ARM::tGPRRegisterClass || RC == ARM::tcGPRRegisterClass 8246ccfc507dc1f7ad8c8964193a2407264ca644f0dJim Grosbach || RC == ARM::rGPRRegisterClass) 8250eb0c7401c34c0b4604f732ce54db995eead14e6Bob Wilson RC = ARM::GPRRegisterClass; 8260eb0c7401c34c0b4604f732ce54db995eead14e6Bob Wilson 827ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson switch (RC->getID()) { 828ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson case ARM::GPRRegClassID: 8295732ca084aaa0cd26149e50dd4b487efff37fe41Evan Cheng AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::LDR), DestReg) 830249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov .addFrameIndex(FI).addReg(0).addImm(0).addMemOperand(MMO)); 831ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson break; 832ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson case ARM::SPRRegClassID: 833d31c5496d7e1580058b5c6fbc8fd537a641ea590Evan Cheng AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRS), DestReg) 834d31c5496d7e1580058b5c6fbc8fd537a641ea590Evan Cheng .addFrameIndex(FI).addImm(0).addMemOperand(MMO)); 835ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson break; 836ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson case ARM::DPRRegClassID: 837ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson case ARM::DPR_VFP2RegClassID: 838ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson case ARM::DPR_8RegClassID: 839e5165490b7ba24bb2f3043399e0d60e7f3bcf8a5Jim Grosbach AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRD), DestReg) 840249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov .addFrameIndex(FI).addImm(0).addMemOperand(MMO)); 841ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson break; 842ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson case ARM::QPRRegClassID: 843ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson case ARM::QPR_VFP2RegClassID: 844ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson case ARM::QPR_8RegClassID: 8450cfcf93c95af91e809ef740eb0ab368477226b40Jim Grosbach if (Align >= 16 && getRegisterInfo().needsStackRealignment(MF)) { 846168f382dc67e5940cabdb28dc933c4f91cdd3137Bob Wilson AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1q64Pseudo), DestReg) 847f967ca0eaf30325cabe3c1971bf0dba16cf1b027Bob Wilson .addFrameIndex(FI).addImm(16) 84869b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng .addMemOperand(MMO)); 84931bc849123011b8eae6bb3c79876d9a3c26a6a1dJim Grosbach } else { 85069b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMQ), DestReg) 85169b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng .addFrameIndex(FI) 852d4bfd54ec2947e73ab152c3c548e4dd4beb700baBob Wilson .addImm(ARM_AM::getAM4ModeImm(ARM_AM::ia)) 85369b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng .addMemOperand(MMO)); 85431bc849123011b8eae6bb3c79876d9a3c26a6a1dJim Grosbach } 855ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson break; 856ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson case ARM::QQPRRegClassID: 857ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson case ARM::QQPR_VFP2RegClassID: 858435d4991779d6a47cadff4ea670b490d8507d6c4Evan Cheng if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) { 859168f382dc67e5940cabdb28dc933c4f91cdd3137Bob Wilson AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1d64QPseudo), DestReg) 860168f382dc67e5940cabdb28dc933c4f91cdd3137Bob Wilson .addFrameIndex(FI).addImm(16) 861168f382dc67e5940cabdb28dc933c4f91cdd3137Bob Wilson .addMemOperand(MMO)); 862435d4991779d6a47cadff4ea670b490d8507d6c4Evan Cheng } else { 863435d4991779d6a47cadff4ea670b490d8507d6c4Evan Cheng MachineInstrBuilder MIB = 864435d4991779d6a47cadff4ea670b490d8507d6c4Evan Cheng AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMD)) 865435d4991779d6a47cadff4ea670b490d8507d6c4Evan Cheng .addFrameIndex(FI) 866d4bfd54ec2947e73ab152c3c548e4dd4beb700baBob Wilson .addImm(ARM_AM::getAM4ModeImm(ARM_AM::ia))) 867435d4991779d6a47cadff4ea670b490d8507d6c4Evan Cheng .addMemOperand(MMO); 868558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::Define, TRI); 869558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::Define, TRI); 870558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::Define, TRI); 871558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen AddDReg(MIB, DestReg, ARM::dsub_3, RegState::Define, TRI); 872435d4991779d6a47cadff4ea670b490d8507d6c4Evan Cheng } 873ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson break; 874ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson case ARM::QQQQPRRegClassID: { 875ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson MachineInstrBuilder MIB = 876ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMD)) 877ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson .addFrameIndex(FI) 878d4bfd54ec2947e73ab152c3c548e4dd4beb700baBob Wilson .addImm(ARM_AM::getAM4ModeImm(ARM_AM::ia))) 879ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson .addMemOperand(MMO); 880ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::Define, TRI); 881ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::Define, TRI); 882ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::Define, TRI); 883ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::Define, TRI); 884ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson MIB = AddDReg(MIB, DestReg, ARM::dsub_4, RegState::Define, TRI); 885ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson MIB = AddDReg(MIB, DestReg, ARM::dsub_5, RegState::Define, TRI); 886ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson MIB = AddDReg(MIB, DestReg, ARM::dsub_6, RegState::Define, TRI); 887ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson AddDReg(MIB, DestReg, ARM::dsub_7, RegState::Define, TRI); 888ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson break; 889ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson } 890ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson default: 891ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson llvm_unreachable("Unknown regclass!"); 892334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 893334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 894334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 89562b50656ceb854eb0be265d63b2a1d46e7400d8aEvan ChengMachineInstr* 89662b50656ceb854eb0be265d63b2a1d46e7400d8aEvan ChengARMBaseInstrInfo::emitFrameIndexDebugValue(MachineFunction &MF, 8978601a3d4decff0a380e059b037dabf71075497d3Evan Cheng int FrameIx, uint64_t Offset, 89862b50656ceb854eb0be265d63b2a1d46e7400d8aEvan Cheng const MDNode *MDPtr, 89962b50656ceb854eb0be265d63b2a1d46e7400d8aEvan Cheng DebugLoc DL) const { 90062b50656ceb854eb0be265d63b2a1d46e7400d8aEvan Cheng MachineInstrBuilder MIB = BuildMI(MF, DL, get(ARM::DBG_VALUE)) 90162b50656ceb854eb0be265d63b2a1d46e7400d8aEvan Cheng .addFrameIndex(FrameIx).addImm(0).addImm(Offset).addMetadata(MDPtr); 90262b50656ceb854eb0be265d63b2a1d46e7400d8aEvan Cheng return &*MIB; 90362b50656ceb854eb0be265d63b2a1d46e7400d8aEvan Cheng} 90462b50656ceb854eb0be265d63b2a1d46e7400d8aEvan Cheng 90530ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen/// Create a copy of a const pool value. Update CPI to the new index and return 90630ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen/// the label UID. 90730ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesenstatic unsigned duplicateCPV(MachineFunction &MF, unsigned &CPI) { 90830ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen MachineConstantPool *MCP = MF.getConstantPool(); 90930ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 91030ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen 91130ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPI]; 91230ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen assert(MCPE.isMachineConstantPoolEntry() && 91330ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen "Expecting a machine constantpool entry!"); 91430ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen ARMConstantPoolValue *ACPV = 91530ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal); 91630ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen 91730ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen unsigned PCLabelId = AFI->createConstPoolEntryUId(); 91830ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen ARMConstantPoolValue *NewCPV = 0; 91951f5b67395780b8421f4aa6ee998ed51b23dae9dJim Grosbach // FIXME: The below assumes PIC relocation model and that the function 92051f5b67395780b8421f4aa6ee998ed51b23dae9dJim Grosbach // is Thumb mode (t1 or t2). PCAdjustment would be 8 for ARM mode PIC, and 92151f5b67395780b8421f4aa6ee998ed51b23dae9dJim Grosbach // zero for non-PIC in ARM or Thumb. The callers are all of thumb LDR 92251f5b67395780b8421f4aa6ee998ed51b23dae9dJim Grosbach // instructions, so that's probably OK, but is PIC always correct when 92351f5b67395780b8421f4aa6ee998ed51b23dae9dJim Grosbach // we get here? 92430ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen if (ACPV->isGlobalValue()) 92530ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen NewCPV = new ARMConstantPoolValue(ACPV->getGV(), PCLabelId, 92630ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen ARMCP::CPValue, 4); 92730ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen else if (ACPV->isExtSymbol()) 92830ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen NewCPV = new ARMConstantPoolValue(MF.getFunction()->getContext(), 92930ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen ACPV->getSymbol(), PCLabelId, 4); 93030ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen else if (ACPV->isBlockAddress()) 93130ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen NewCPV = new ARMConstantPoolValue(ACPV->getBlockAddress(), PCLabelId, 93230ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen ARMCP::CPBlockAddress, 4); 93351f5b67395780b8421f4aa6ee998ed51b23dae9dJim Grosbach else if (ACPV->isLSDA()) 93451f5b67395780b8421f4aa6ee998ed51b23dae9dJim Grosbach NewCPV = new ARMConstantPoolValue(MF.getFunction(), PCLabelId, 93551f5b67395780b8421f4aa6ee998ed51b23dae9dJim Grosbach ARMCP::CPLSDA, 4); 93630ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen else 93730ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen llvm_unreachable("Unexpected ARM constantpool value type!!"); 93830ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen CPI = MCP->getConstantPoolIndex(NewCPV, MCPE.getAlignment()); 93930ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen return PCLabelId; 94030ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen} 94130ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen 942fdc834046efd427d474e3b899ec69354c05071e0Evan Chengvoid ARMBaseInstrInfo:: 943fdc834046efd427d474e3b899ec69354c05071e0Evan ChengreMaterialize(MachineBasicBlock &MBB, 944fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng MachineBasicBlock::iterator I, 945fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng unsigned DestReg, unsigned SubIdx, 946d57cdd5683ea926e489067364fb7ffe5fd5d35eeEvan Cheng const MachineInstr *Orig, 9479edf7deb37f0f97664f279040fa15d89f32e23d9Jakob Stoklund Olesen const TargetRegisterInfo &TRI) const { 948fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng unsigned Opcode = Orig->getOpcode(); 949fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng switch (Opcode) { 950fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng default: { 951fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig); 9529edf7deb37f0f97664f279040fa15d89f32e23d9Jakob Stoklund Olesen MI->substituteRegister(Orig->getOperand(0).getReg(), DestReg, SubIdx, TRI); 953fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng MBB.insert(I, MI); 954fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng break; 955fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng } 956fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng case ARM::tLDRpci_pic: 957fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng case ARM::t2LDRpci_pic: { 958fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng MachineFunction &MF = *MBB.getParent(); 959fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng unsigned CPI = Orig->getOperand(1).getIndex(); 96030ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen unsigned PCLabelId = duplicateCPV(MF, CPI); 961fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng MachineInstrBuilder MIB = BuildMI(MBB, I, Orig->getDebugLoc(), get(Opcode), 962fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng DestReg) 963fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng .addConstantPoolIndex(CPI).addImm(PCLabelId); 964fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng (*MIB).setMemRefs(Orig->memoperands_begin(), Orig->memoperands_end()); 965fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng break; 966fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng } 967fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng } 968fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng} 969fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng 97030ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund OlesenMachineInstr * 97130ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund OlesenARMBaseInstrInfo::duplicate(MachineInstr *Orig, MachineFunction &MF) const { 97230ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen MachineInstr *MI = TargetInstrInfoImpl::duplicate(Orig, MF); 97330ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen switch(Orig->getOpcode()) { 97430ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen case ARM::tLDRpci_pic: 97530ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen case ARM::t2LDRpci_pic: { 97630ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen unsigned CPI = Orig->getOperand(1).getIndex(); 97730ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen unsigned PCLabelId = duplicateCPV(MF, CPI); 97830ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen Orig->getOperand(1).setIndex(CPI); 97930ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen Orig->getOperand(2).setImm(PCLabelId); 98030ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen break; 98130ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen } 98230ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen } 98330ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen return MI; 98430ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen} 98530ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen 986506049f29f4f202a8e45feb916cc0264440a7f6dEvan Chengbool ARMBaseInstrInfo::produceSameValue(const MachineInstr *MI0, 987506049f29f4f202a8e45feb916cc0264440a7f6dEvan Cheng const MachineInstr *MI1) const { 988d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng int Opcode = MI0->getOpcode(); 9899b82425cb0105fd5704f6b9bcd5e7693b05b1759Evan Cheng if (Opcode == ARM::t2LDRpci || 9909b82425cb0105fd5704f6b9bcd5e7693b05b1759Evan Cheng Opcode == ARM::t2LDRpci_pic || 9919b82425cb0105fd5704f6b9bcd5e7693b05b1759Evan Cheng Opcode == ARM::tLDRpci || 9929b82425cb0105fd5704f6b9bcd5e7693b05b1759Evan Cheng Opcode == ARM::tLDRpci_pic) { 993d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng if (MI1->getOpcode() != Opcode) 994d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng return false; 995d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng if (MI0->getNumOperands() != MI1->getNumOperands()) 996d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng return false; 997d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng 998d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng const MachineOperand &MO0 = MI0->getOperand(1); 999d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng const MachineOperand &MO1 = MI1->getOperand(1); 1000d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng if (MO0.getOffset() != MO1.getOffset()) 1001d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng return false; 1002d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng 1003d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng const MachineFunction *MF = MI0->getParent()->getParent(); 1004d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng const MachineConstantPool *MCP = MF->getConstantPool(); 1005d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng int CPI0 = MO0.getIndex(); 1006d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng int CPI1 = MO1.getIndex(); 1007d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng const MachineConstantPoolEntry &MCPE0 = MCP->getConstants()[CPI0]; 1008d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng const MachineConstantPoolEntry &MCPE1 = MCP->getConstants()[CPI1]; 1009d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng ARMConstantPoolValue *ACPV0 = 1010d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng static_cast<ARMConstantPoolValue*>(MCPE0.Val.MachineCPVal); 1011d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng ARMConstantPoolValue *ACPV1 = 1012d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng static_cast<ARMConstantPoolValue*>(MCPE1.Val.MachineCPVal); 1013d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng return ACPV0->hasSameValue(ACPV1); 1014d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng } 1015d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng 1016506049f29f4f202a8e45feb916cc0264440a7f6dEvan Cheng return MI0->isIdenticalTo(MI1, MachineInstr::IgnoreVRegDefs); 1017d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng} 1018d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng 10194b722108e2cf8e77157e0879a23789cd44829933Bill Wendling/// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to 10204b722108e2cf8e77157e0879a23789cd44829933Bill Wendling/// determine if two loads are loading from the same base address. It should 10214b722108e2cf8e77157e0879a23789cd44829933Bill Wendling/// only return true if the base pointers are the same and the only differences 10224b722108e2cf8e77157e0879a23789cd44829933Bill Wendling/// between the two addresses is the offset. It also returns the offsets by 10234b722108e2cf8e77157e0879a23789cd44829933Bill Wendling/// reference. 10244b722108e2cf8e77157e0879a23789cd44829933Bill Wendlingbool ARMBaseInstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, 10254b722108e2cf8e77157e0879a23789cd44829933Bill Wendling int64_t &Offset1, 10264b722108e2cf8e77157e0879a23789cd44829933Bill Wendling int64_t &Offset2) const { 10274b722108e2cf8e77157e0879a23789cd44829933Bill Wendling // Don't worry about Thumb: just ARM and Thumb2. 10284b722108e2cf8e77157e0879a23789cd44829933Bill Wendling if (Subtarget.isThumb1Only()) return false; 10294b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 10304b722108e2cf8e77157e0879a23789cd44829933Bill Wendling if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode()) 10314b722108e2cf8e77157e0879a23789cd44829933Bill Wendling return false; 10324b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 10334b722108e2cf8e77157e0879a23789cd44829933Bill Wendling switch (Load1->getMachineOpcode()) { 10344b722108e2cf8e77157e0879a23789cd44829933Bill Wendling default: 10354b722108e2cf8e77157e0879a23789cd44829933Bill Wendling return false; 10364b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::LDR: 10374b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::LDRB: 10384b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::LDRD: 10394b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::LDRH: 10404b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::LDRSB: 10414b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::LDRSH: 10424b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::VLDRD: 10434b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::VLDRS: 10444b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::t2LDRi8: 10454b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::t2LDRDi8: 10464b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::t2LDRSHi8: 10474b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::t2LDRi12: 10484b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::t2LDRSHi12: 10494b722108e2cf8e77157e0879a23789cd44829933Bill Wendling break; 10504b722108e2cf8e77157e0879a23789cd44829933Bill Wendling } 10514b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 10524b722108e2cf8e77157e0879a23789cd44829933Bill Wendling switch (Load2->getMachineOpcode()) { 10534b722108e2cf8e77157e0879a23789cd44829933Bill Wendling default: 10544b722108e2cf8e77157e0879a23789cd44829933Bill Wendling return false; 10554b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::LDR: 10564b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::LDRB: 10574b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::LDRD: 10584b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::LDRH: 10594b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::LDRSB: 10604b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::LDRSH: 10614b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::VLDRD: 10624b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::VLDRS: 10634b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::t2LDRi8: 10644b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::t2LDRDi8: 10654b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::t2LDRSHi8: 10664b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::t2LDRi12: 10674b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::t2LDRSHi12: 10684b722108e2cf8e77157e0879a23789cd44829933Bill Wendling break; 10694b722108e2cf8e77157e0879a23789cd44829933Bill Wendling } 10704b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 10714b722108e2cf8e77157e0879a23789cd44829933Bill Wendling // Check if base addresses and chain operands match. 10724b722108e2cf8e77157e0879a23789cd44829933Bill Wendling if (Load1->getOperand(0) != Load2->getOperand(0) || 10734b722108e2cf8e77157e0879a23789cd44829933Bill Wendling Load1->getOperand(4) != Load2->getOperand(4)) 10744b722108e2cf8e77157e0879a23789cd44829933Bill Wendling return false; 10754b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 10764b722108e2cf8e77157e0879a23789cd44829933Bill Wendling // Index should be Reg0. 10774b722108e2cf8e77157e0879a23789cd44829933Bill Wendling if (Load1->getOperand(3) != Load2->getOperand(3)) 10784b722108e2cf8e77157e0879a23789cd44829933Bill Wendling return false; 10794b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 10804b722108e2cf8e77157e0879a23789cd44829933Bill Wendling // Determine the offsets. 10814b722108e2cf8e77157e0879a23789cd44829933Bill Wendling if (isa<ConstantSDNode>(Load1->getOperand(1)) && 10824b722108e2cf8e77157e0879a23789cd44829933Bill Wendling isa<ConstantSDNode>(Load2->getOperand(1))) { 10834b722108e2cf8e77157e0879a23789cd44829933Bill Wendling Offset1 = cast<ConstantSDNode>(Load1->getOperand(1))->getSExtValue(); 10844b722108e2cf8e77157e0879a23789cd44829933Bill Wendling Offset2 = cast<ConstantSDNode>(Load2->getOperand(1))->getSExtValue(); 10854b722108e2cf8e77157e0879a23789cd44829933Bill Wendling return true; 10864b722108e2cf8e77157e0879a23789cd44829933Bill Wendling } 10874b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 10884b722108e2cf8e77157e0879a23789cd44829933Bill Wendling return false; 10894b722108e2cf8e77157e0879a23789cd44829933Bill Wendling} 10904b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 10914b722108e2cf8e77157e0879a23789cd44829933Bill Wendling/// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to 10924b722108e2cf8e77157e0879a23789cd44829933Bill Wendling/// determine (in conjuction with areLoadsFromSameBasePtr) if two loads should 10934b722108e2cf8e77157e0879a23789cd44829933Bill Wendling/// be scheduled togther. On some targets if two loads are loading from 10944b722108e2cf8e77157e0879a23789cd44829933Bill Wendling/// addresses in the same cache line, it's better if they are scheduled 10954b722108e2cf8e77157e0879a23789cd44829933Bill Wendling/// together. This function takes two integers that represent the load offsets 10964b722108e2cf8e77157e0879a23789cd44829933Bill Wendling/// from the common base address. It returns true if it decides it's desirable 10974b722108e2cf8e77157e0879a23789cd44829933Bill Wendling/// to schedule the two loads together. "NumLoads" is the number of loads that 10984b722108e2cf8e77157e0879a23789cd44829933Bill Wendling/// have already been scheduled after Load1. 10994b722108e2cf8e77157e0879a23789cd44829933Bill Wendlingbool ARMBaseInstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, 11004b722108e2cf8e77157e0879a23789cd44829933Bill Wendling int64_t Offset1, int64_t Offset2, 11014b722108e2cf8e77157e0879a23789cd44829933Bill Wendling unsigned NumLoads) const { 11024b722108e2cf8e77157e0879a23789cd44829933Bill Wendling // Don't worry about Thumb: just ARM and Thumb2. 11034b722108e2cf8e77157e0879a23789cd44829933Bill Wendling if (Subtarget.isThumb1Only()) return false; 11044b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 11054b722108e2cf8e77157e0879a23789cd44829933Bill Wendling assert(Offset2 > Offset1); 11064b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 11074b722108e2cf8e77157e0879a23789cd44829933Bill Wendling if ((Offset2 - Offset1) / 8 > 64) 11084b722108e2cf8e77157e0879a23789cd44829933Bill Wendling return false; 11094b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 11104b722108e2cf8e77157e0879a23789cd44829933Bill Wendling if (Load1->getMachineOpcode() != Load2->getMachineOpcode()) 11114b722108e2cf8e77157e0879a23789cd44829933Bill Wendling return false; // FIXME: overly conservative? 11124b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 11134b722108e2cf8e77157e0879a23789cd44829933Bill Wendling // Four loads in a row should be sufficient. 11144b722108e2cf8e77157e0879a23789cd44829933Bill Wendling if (NumLoads >= 3) 11154b722108e2cf8e77157e0879a23789cd44829933Bill Wendling return false; 11164b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 11174b722108e2cf8e77157e0879a23789cd44829933Bill Wendling return true; 11184b722108e2cf8e77157e0879a23789cd44829933Bill Wendling} 11194b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 112086050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Chengbool ARMBaseInstrInfo::isSchedulingBoundary(const MachineInstr *MI, 112186050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng const MachineBasicBlock *MBB, 112286050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng const MachineFunction &MF) const { 112357bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach // Debug info is never a scheduling boundary. It's necessary to be explicit 112457bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach // due to the special treatment of IT instructions below, otherwise a 112557bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach // dbg_value followed by an IT will result in the IT instruction being 112657bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach // considered a scheduling hazard, which is wrong. It should be the actual 112757bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach // instruction preceding the dbg_value instruction(s), just like it is 112857bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach // when debug info is not present. 112957bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach if (MI->isDebugValue()) 113057bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach return false; 113157bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach 113286050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // Terminators and labels can't be scheduled around. 113386050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng if (MI->getDesc().isTerminator() || MI->isLabel()) 113486050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng return true; 113586050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng 113686050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // Treat the start of the IT block as a scheduling boundary, but schedule 113786050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // t2IT along with all instructions following it. 113886050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // FIXME: This is a big hammer. But the alternative is to add all potential 113986050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // true and anti dependencies to IT block instructions as implicit operands 114086050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // to the t2IT instruction. The added compile time and complexity does not 114186050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // seem worth it. 114286050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng MachineBasicBlock::const_iterator I = MI; 114357bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach // Make sure to skip any dbg_value instructions 114457bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach while (++I != MBB->end() && I->isDebugValue()) 114557bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach ; 114657bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach if (I != MBB->end() && I->getOpcode() == ARM::t2IT) 114786050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng return true; 114886050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng 114986050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // Don't attempt to schedule around any instruction that defines 115086050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // a stack-oriented pointer, as it's unlikely to be profitable. This 115186050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // saves compile time, because it doesn't require every single 115286050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // stack slot reference to depend on the instruction that does the 115386050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // modification. 115486050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng if (MI->definesRegister(ARM::SP)) 115586050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng return true; 115686050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng 115786050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng return false; 115886050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng} 115986050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng 116013151432edace19ee867a93b5c14573df4f75d24Evan Chengbool ARMBaseInstrInfo:: 116113151432edace19ee867a93b5c14573df4f75d24Evan ChengisProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumInstrs) const { 116213151432edace19ee867a93b5c14573df4f75d24Evan Cheng if (!NumInstrs) 116313151432edace19ee867a93b5c14573df4f75d24Evan Cheng return false; 116413151432edace19ee867a93b5c14573df4f75d24Evan Cheng if (Subtarget.getCPUString() == "generic") 116513151432edace19ee867a93b5c14573df4f75d24Evan Cheng // Generic (and overly aggressive) if-conversion limits for testing. 116613151432edace19ee867a93b5c14573df4f75d24Evan Cheng return NumInstrs <= 10; 116713151432edace19ee867a93b5c14573df4f75d24Evan Cheng else if (Subtarget.hasV7Ops()) 116813151432edace19ee867a93b5c14573df4f75d24Evan Cheng return NumInstrs <= 3; 116913151432edace19ee867a93b5c14573df4f75d24Evan Cheng return NumInstrs <= 2; 117013151432edace19ee867a93b5c14573df4f75d24Evan Cheng} 117113151432edace19ee867a93b5c14573df4f75d24Evan Cheng 117213151432edace19ee867a93b5c14573df4f75d24Evan Chengbool ARMBaseInstrInfo:: 117313151432edace19ee867a93b5c14573df4f75d24Evan ChengisProfitableToIfCvt(MachineBasicBlock &TMBB, unsigned NumT, 117413151432edace19ee867a93b5c14573df4f75d24Evan Cheng MachineBasicBlock &FMBB, unsigned NumF) const { 117513151432edace19ee867a93b5c14573df4f75d24Evan Cheng return NumT && NumF && NumT <= 2 && NumF <= 2; 117613151432edace19ee867a93b5c14573df4f75d24Evan Cheng} 117713151432edace19ee867a93b5c14573df4f75d24Evan Cheng 11788fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng/// getInstrPredicate - If instruction is predicated, returns its predicate 11798fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng/// condition, otherwise returns AL. It also returns the condition code 11808fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng/// register by reference. 11815adb66a646e2ec32265263739f5b01c3f50c176aEvan ChengARMCC::CondCodes 11825adb66a646e2ec32265263739f5b01c3f50c176aEvan Chengllvm::getInstrPredicate(const MachineInstr *MI, unsigned &PredReg) { 11838fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng int PIdx = MI->findFirstPredOperandIdx(); 11848fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng if (PIdx == -1) { 11858fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng PredReg = 0; 11868fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng return ARMCC::AL; 11878fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng } 11888fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng 11898fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng PredReg = MI->getOperand(PIdx+1).getReg(); 11908fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng return (ARMCC::CondCodes)MI->getOperand(PIdx).getImm(); 11918fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng} 11928fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng 11938fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng 11946495f63945e8dbde81f03a1dc2ab421993b9a495Evan Chengint llvm::getMatchingCondBranchOpcode(int Opc) { 11955ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng if (Opc == ARM::B) 11965ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng return ARM::Bcc; 11975ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng else if (Opc == ARM::tB) 11985ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng return ARM::tBcc; 11995ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng else if (Opc == ARM::t2B) 12005ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng return ARM::t2Bcc; 12015ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng 12025ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng llvm_unreachable("Unknown unconditional branch opcode!"); 12035ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng return 0; 12045ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng} 12055ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng 12066495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 12076495f63945e8dbde81f03a1dc2ab421993b9a495Evan Chengvoid llvm::emitARMRegPlusImmediate(MachineBasicBlock &MBB, 12086495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MachineBasicBlock::iterator &MBBI, DebugLoc dl, 12096495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned DestReg, unsigned BaseReg, int NumBytes, 12106495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ARMCC::CondCodes Pred, unsigned PredReg, 12116495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng const ARMBaseInstrInfo &TII) { 12126495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng bool isSub = NumBytes < 0; 12136495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (isSub) NumBytes = -NumBytes; 12146495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 12156495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng while (NumBytes) { 12166495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned RotAmt = ARM_AM::getSOImmValRotate(NumBytes); 12176495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned ThisVal = NumBytes & ARM_AM::rotr32(0xFF, RotAmt); 12186495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng assert(ThisVal && "Didn't extract field correctly"); 12196495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 12206495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // We will handle these bits from offset, clear them. 12216495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng NumBytes &= ~ThisVal; 12226495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 12236495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng assert(ARM_AM::getSOImmVal(ThisVal) != -1 && "Bit extraction didn't work?"); 12246495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 12256495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Build the new ADD / SUB. 12266495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned Opc = isSub ? ARM::SUBri : ARM::ADDri; 12276495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg) 12286495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng .addReg(BaseReg, RegState::Kill).addImm(ThisVal) 12296495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng .addImm((unsigned)Pred).addReg(PredReg).addReg(0); 12306495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng BaseReg = DestReg; 12316495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 12326495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng} 12336495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 1234cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Chengbool llvm::rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx, 1235cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng unsigned FrameReg, int &Offset, 1236cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng const ARMBaseInstrInfo &TII) { 12376495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned Opcode = MI.getOpcode(); 12386495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng const TargetInstrDesc &Desc = MI.getDesc(); 12396495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask); 12406495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng bool isSub = false; 1241764ab52dd80310a205c9888bf166d09dab858f90Jim Grosbach 12426495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Memory operands in inline assembly always use AddrMode2. 12436495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (Opcode == ARM::INLINEASM) 12446495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng AddrMode = ARMII::AddrMode2; 1245764ab52dd80310a205c9888bf166d09dab858f90Jim Grosbach 12466495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (Opcode == ARM::ADDri) { 12476495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng Offset += MI.getOperand(FrameRegIdx+1).getImm(); 12486495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (Offset == 0) { 12496495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Turn it into a move. 12506495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MI.setDesc(TII.get(ARM::MOVr)); 12516495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false); 12526495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MI.RemoveOperand(FrameRegIdx+1); 1253cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng Offset = 0; 1254cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng return true; 12556495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } else if (Offset < 0) { 12566495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng Offset = -Offset; 12576495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng isSub = true; 12586495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MI.setDesc(TII.get(ARM::SUBri)); 12596495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 12606495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 12616495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Common case: small offset, fits into instruction. 12626495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (ARM_AM::getSOImmVal(Offset) != -1) { 12636495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Replace the FrameIndex with sp / fp 12646495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false); 12656495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset); 1266cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng Offset = 0; 1267cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng return true; 12686495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 12696495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 12706495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Otherwise, pull as much of the immedidate into this ADDri/SUBri 12716495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // as possible. 12726495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned RotAmt = ARM_AM::getSOImmValRotate(Offset); 12736495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xFF, RotAmt); 12746495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 12756495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // We will handle these bits from offset, clear them. 12766495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng Offset &= ~ThisImmVal; 12776495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 12786495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Get the properly encoded SOImmVal field. 12796495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng assert(ARM_AM::getSOImmVal(ThisImmVal) != -1 && 12806495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng "Bit extraction didn't work?"); 12816495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MI.getOperand(FrameRegIdx+1).ChangeToImmediate(ThisImmVal); 12826495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } else { 12836495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned ImmIdx = 0; 12846495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng int InstrOffs = 0; 12856495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned NumBits = 0; 12866495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned Scale = 1; 12876495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng switch (AddrMode) { 12886495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng case ARMII::AddrMode2: { 12896495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ImmIdx = FrameRegIdx+2; 12906495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng InstrOffs = ARM_AM::getAM2Offset(MI.getOperand(ImmIdx).getImm()); 12916495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (ARM_AM::getAM2Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub) 12926495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng InstrOffs *= -1; 12936495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng NumBits = 12; 12946495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng break; 12956495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 12966495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng case ARMII::AddrMode3: { 12976495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ImmIdx = FrameRegIdx+2; 12986495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng InstrOffs = ARM_AM::getAM3Offset(MI.getOperand(ImmIdx).getImm()); 12996495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (ARM_AM::getAM3Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub) 13006495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng InstrOffs *= -1; 13016495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng NumBits = 8; 13026495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng break; 13036495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 1304baf31088f1472f48ea5ae81f0b93636cc44ca444Anton Korobeynikov case ARMII::AddrMode4: 1305a44321776ecd96fa0344335d3027758be3386e45Jim Grosbach case ARMII::AddrMode6: 1306cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng // Can't fold any offset even if it's zero. 1307cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng return false; 13086495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng case ARMII::AddrMode5: { 13096495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ImmIdx = FrameRegIdx+1; 13106495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng InstrOffs = ARM_AM::getAM5Offset(MI.getOperand(ImmIdx).getImm()); 13116495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (ARM_AM::getAM5Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub) 13126495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng InstrOffs *= -1; 13136495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng NumBits = 8; 13146495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng Scale = 4; 13156495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng break; 13166495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 13176495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng default: 13186495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng llvm_unreachable("Unsupported addressing mode!"); 13196495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng break; 13206495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 13216495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 13226495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng Offset += InstrOffs * Scale; 13236495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!"); 13246495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (Offset < 0) { 13256495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng Offset = -Offset; 13266495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng isSub = true; 13276495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 13286495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 13296495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Attempt to fold address comp. if opcode has offset bits 13306495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (NumBits > 0) { 13316495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Common case: small offset, fits into instruction. 13326495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MachineOperand &ImmOp = MI.getOperand(ImmIdx); 13336495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng int ImmedOffset = Offset / Scale; 13346495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned Mask = (1 << NumBits) - 1; 13356495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if ((unsigned)Offset <= Mask * Scale) { 13366495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Replace the FrameIndex with sp 13376495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false); 13386495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (isSub) 13396495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ImmedOffset |= 1 << NumBits; 13406495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ImmOp.ChangeToImmediate(ImmedOffset); 1341cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng Offset = 0; 1342cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng return true; 13436495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 1344764ab52dd80310a205c9888bf166d09dab858f90Jim Grosbach 13456495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Otherwise, it didn't fit. Pull in what we can to simplify the immed. 13466495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ImmedOffset = ImmedOffset & Mask; 13476495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (isSub) 13486495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ImmedOffset |= 1 << NumBits; 13496495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ImmOp.ChangeToImmediate(ImmedOffset); 13506495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng Offset &= ~(Mask*Scale); 13516495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 13526495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 13536495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 1354cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng Offset = (isSub) ? -Offset : Offset; 1355cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng return Offset == 0; 13566495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng} 1357e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling 1358e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendlingbool ARMBaseInstrInfo:: 1359c98af3370f899a0d1570b1dff01a2e36632f884fBill WendlingAnalyzeCompare(const MachineInstr *MI, unsigned &SrcReg, int &CmpValue) const { 1360e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling switch (MI->getOpcode()) { 1361e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling default: break; 136238ae997e63e3e1bb2c8679e01ea74cf8fd0be893Bill Wendling case ARM::CMPri: 136338ae997e63e3e1bb2c8679e01ea74cf8fd0be893Bill Wendling case ARM::CMPzri: 1364e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling case ARM::t2CMPri: 1365e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling case ARM::t2CMPzri: 1366e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling SrcReg = MI->getOperand(0).getReg(); 1367e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling CmpValue = MI->getOperand(1).getImm(); 1368e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling return true; 1369de90bfd14af1a850ec43438d9cfffeb83f50a5a1Gabor Greif case ARM::TSTri: { 1370308f64a7c847821a4260da673089e7b4af74e56cGabor Greif if (&*MI->getParent()->begin() == MI) 1371de90bfd14af1a850ec43438d9cfffeb83f50a5a1Gabor Greif return false; 1372de90bfd14af1a850ec43438d9cfffeb83f50a5a1Gabor Greif const MachineInstr *AND = llvm::prior(MI); 1373de90bfd14af1a850ec43438d9cfffeb83f50a5a1Gabor Greif if (AND->getOpcode() != ARM::ANDri) 1374de90bfd14af1a850ec43438d9cfffeb83f50a5a1Gabor Greif return false; 1375de90bfd14af1a850ec43438d9cfffeb83f50a5a1Gabor Greif if (MI->getOperand(0).getReg() == AND->getOperand(1).getReg() && 1376de90bfd14af1a850ec43438d9cfffeb83f50a5a1Gabor Greif MI->getOperand(1).getImm() == AND->getOperand(2).getImm()) { 1377de90bfd14af1a850ec43438d9cfffeb83f50a5a1Gabor Greif SrcReg = AND->getOperand(0).getReg(); 1378de90bfd14af1a850ec43438d9cfffeb83f50a5a1Gabor Greif CmpValue = 0; 1379de90bfd14af1a850ec43438d9cfffeb83f50a5a1Gabor Greif return true; 1380de90bfd14af1a850ec43438d9cfffeb83f50a5a1Gabor Greif } 1381de90bfd14af1a850ec43438d9cfffeb83f50a5a1Gabor Greif } 1382308f64a7c847821a4260da673089e7b4af74e56cGabor Greif break; 1383e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling } 1384e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling 1385e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling return false; 1386e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling} 1387e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling 1388a65568676d0d9d53dd4aae8f1c58271bb4cfff10Bill Wendling/// OptimizeCompareInstr - Convert the instruction supplying the argument to the 138992ad57f066e9f256e4e3d72febf152e68caa80c7Bill Wendling/// comparison into one that sets the zero bit in the flags register. Update the 139092ad57f066e9f256e4e3d72febf152e68caa80c7Bill Wendling/// iterator *only* if a transformation took place. 1391e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendlingbool ARMBaseInstrInfo:: 1392a65568676d0d9d53dd4aae8f1c58271bb4cfff10Bill WendlingOptimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, int CmpValue, 1393220e240bdf3235252c2a1fc8fcc5d4b8e8117918Bill Wendling MachineBasicBlock::iterator &MII) const { 13943665661a5708c8adc2727be38b56d1d87ddeb661Bill Wendling if (CmpValue != 0) 139592ad57f066e9f256e4e3d72febf152e68caa80c7Bill Wendling return false; 139692ad57f066e9f256e4e3d72febf152e68caa80c7Bill Wendling 139792ad57f066e9f256e4e3d72febf152e68caa80c7Bill Wendling MachineRegisterInfo &MRI = CmpInstr->getParent()->getParent()->getRegInfo(); 139892ad57f066e9f256e4e3d72febf152e68caa80c7Bill Wendling MachineRegisterInfo::def_iterator DI = MRI.def_begin(SrcReg); 139992ad57f066e9f256e4e3d72febf152e68caa80c7Bill Wendling if (llvm::next(DI) != MRI.def_end()) 140092ad57f066e9f256e4e3d72febf152e68caa80c7Bill Wendling // Only support one definition. 140192ad57f066e9f256e4e3d72febf152e68caa80c7Bill Wendling return false; 140292ad57f066e9f256e4e3d72febf152e68caa80c7Bill Wendling 140392ad57f066e9f256e4e3d72febf152e68caa80c7Bill Wendling MachineInstr *MI = &*DI; 140492ad57f066e9f256e4e3d72febf152e68caa80c7Bill Wendling 1405e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling // Conservatively refuse to convert an instruction which isn't in the same BB 1406e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling // as the comparison. 1407e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling if (MI->getParent() != CmpInstr->getParent()) 1408e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling return false; 1409e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling 1410e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling // Check that CPSR isn't set between the comparison instruction and the one we 1411e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling // want to change. 1412e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling MachineBasicBlock::const_iterator I = CmpInstr, E = MI; 1413e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling --I; 1414e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling for (; I != E; --I) { 1415e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling const MachineInstr &Instr = *I; 1416e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling 1417e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling for (unsigned IO = 0, EO = Instr.getNumOperands(); IO != EO; ++IO) { 1418e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling const MachineOperand &MO = Instr.getOperand(IO); 141975486dbf4e9611f2070bf13b874f78a5587ed7ffBill Wendling if (!MO.isReg() || !MO.isDef()) continue; 1420e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling 1421e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling // This instruction modifies CPSR before the one we want to change. We 1422e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling // can't do this transformation. 1423e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling if (MO.getReg() == ARM::CPSR) 1424e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling return false; 1425e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling } 1426e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling } 1427e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling 1428e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling // Set the "zero" bit in CPSR. 1429e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling switch (MI->getOpcode()) { 1430e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling default: break; 143138ae997e63e3e1bb2c8679e01ea74cf8fd0be893Bill Wendling case ARM::ADDri: 1432de90bfd14af1a850ec43438d9cfffeb83f50a5a1Gabor Greif case ARM::ANDri: 1433de90bfd14af1a850ec43438d9cfffeb83f50a5a1Gabor Greif case ARM::t2ANDri: 143438ae997e63e3e1bb2c8679e01ea74cf8fd0be893Bill Wendling case ARM::SUBri: 143538ae997e63e3e1bb2c8679e01ea74cf8fd0be893Bill Wendling case ARM::t2ADDri: 1436ad422718f9b3224234f52e84d28d8a57a4e89987Bill Wendling case ARM::t2SUBri: 1437e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling MI->RemoveOperand(5); 1438ad422718f9b3224234f52e84d28d8a57a4e89987Bill Wendling MachineInstrBuilder(MI) 1439ad422718f9b3224234f52e84d28d8a57a4e89987Bill Wendling .addReg(ARM::CPSR, RegState::Define | RegState::Implicit); 1440220e240bdf3235252c2a1fc8fcc5d4b8e8117918Bill Wendling MII = llvm::next(MachineBasicBlock::iterator(CmpInstr)); 1441e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling CmpInstr->eraseFromParent(); 1442e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling return true; 1443e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling } 1444e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling 1445e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling return false; 1446e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling} 14475f54ce347368105260be2cec497b6a4199dc5789Evan Cheng 14485f54ce347368105260be2cec497b6a4199dc5789Evan Chengunsigned 14495f54ce347368105260be2cec497b6a4199dc5789Evan ChengARMBaseInstrInfo::getNumMicroOps(const MachineInstr *MI, 14503ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng const InstrItineraryData *ItinData) const { 14513ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng if (!ItinData || ItinData->isEmpty()) 14525f54ce347368105260be2cec497b6a4199dc5789Evan Cheng return 1; 14535f54ce347368105260be2cec497b6a4199dc5789Evan Cheng 14545f54ce347368105260be2cec497b6a4199dc5789Evan Cheng const TargetInstrDesc &Desc = MI->getDesc(); 14555f54ce347368105260be2cec497b6a4199dc5789Evan Cheng unsigned Class = Desc.getSchedClass(); 14563ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng unsigned UOps = ItinData->Itineratries[Class].NumMicroOps; 14575f54ce347368105260be2cec497b6a4199dc5789Evan Cheng if (UOps) 14585f54ce347368105260be2cec497b6a4199dc5789Evan Cheng return UOps; 14595f54ce347368105260be2cec497b6a4199dc5789Evan Cheng 14605f54ce347368105260be2cec497b6a4199dc5789Evan Cheng unsigned Opc = MI->getOpcode(); 14615f54ce347368105260be2cec497b6a4199dc5789Evan Cheng switch (Opc) { 14625f54ce347368105260be2cec497b6a4199dc5789Evan Cheng default: 14635f54ce347368105260be2cec497b6a4199dc5789Evan Cheng llvm_unreachable("Unexpected multi-uops instruction!"); 14645f54ce347368105260be2cec497b6a4199dc5789Evan Cheng break; 14653ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng case ARM::VLDMQ: 14665f54ce347368105260be2cec497b6a4199dc5789Evan Cheng case ARM::VSTMQ: 14675f54ce347368105260be2cec497b6a4199dc5789Evan Cheng return 2; 14685f54ce347368105260be2cec497b6a4199dc5789Evan Cheng 14695f54ce347368105260be2cec497b6a4199dc5789Evan Cheng // The number of uOps for load / store multiple are determined by the number 14705f54ce347368105260be2cec497b6a4199dc5789Evan Cheng // registers. 14713ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng // On Cortex-A8, each pair of register loads / stores can be scheduled on the 14723ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng // same cycle. The scheduling for the first load / store must be done 14733ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng // separately by assuming the the address is not 64-bit aligned. 14743ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng // On Cortex-A9, the formula is simply (#reg / 2) + (#reg % 2). If the address 14753ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng // is not 64-bit aligned, then AGU would take an extra cycle. 14763ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng // For VFP / NEON load / store multiple, the formula is 14775f54ce347368105260be2cec497b6a4199dc5789Evan Cheng // (#reg / 2) + (#reg % 2) + 1. 14785f54ce347368105260be2cec497b6a4199dc5789Evan Cheng case ARM::VLDMD: 14795f54ce347368105260be2cec497b6a4199dc5789Evan Cheng case ARM::VLDMS: 14805f54ce347368105260be2cec497b6a4199dc5789Evan Cheng case ARM::VLDMD_UPD: 14815f54ce347368105260be2cec497b6a4199dc5789Evan Cheng case ARM::VLDMS_UPD: 14825f54ce347368105260be2cec497b6a4199dc5789Evan Cheng case ARM::VSTMD: 14835f54ce347368105260be2cec497b6a4199dc5789Evan Cheng case ARM::VSTMS: 14845f54ce347368105260be2cec497b6a4199dc5789Evan Cheng case ARM::VSTMD_UPD: 14855f54ce347368105260be2cec497b6a4199dc5789Evan Cheng case ARM::VSTMS_UPD: { 14865f54ce347368105260be2cec497b6a4199dc5789Evan Cheng unsigned NumRegs = MI->getNumOperands() - Desc.getNumOperands(); 14875f54ce347368105260be2cec497b6a4199dc5789Evan Cheng return (NumRegs / 2) + (NumRegs % 2) + 1; 14885f54ce347368105260be2cec497b6a4199dc5789Evan Cheng } 14895f54ce347368105260be2cec497b6a4199dc5789Evan Cheng case ARM::LDM_RET: 14905f54ce347368105260be2cec497b6a4199dc5789Evan Cheng case ARM::LDM: 14915f54ce347368105260be2cec497b6a4199dc5789Evan Cheng case ARM::LDM_UPD: 14925f54ce347368105260be2cec497b6a4199dc5789Evan Cheng case ARM::STM: 14935f54ce347368105260be2cec497b6a4199dc5789Evan Cheng case ARM::STM_UPD: 14945f54ce347368105260be2cec497b6a4199dc5789Evan Cheng case ARM::tLDM: 14955f54ce347368105260be2cec497b6a4199dc5789Evan Cheng case ARM::tLDM_UPD: 14965f54ce347368105260be2cec497b6a4199dc5789Evan Cheng case ARM::tSTM_UPD: 14975f54ce347368105260be2cec497b6a4199dc5789Evan Cheng case ARM::tPOP_RET: 14985f54ce347368105260be2cec497b6a4199dc5789Evan Cheng case ARM::tPOP: 14995f54ce347368105260be2cec497b6a4199dc5789Evan Cheng case ARM::tPUSH: 15005f54ce347368105260be2cec497b6a4199dc5789Evan Cheng case ARM::t2LDM_RET: 15015f54ce347368105260be2cec497b6a4199dc5789Evan Cheng case ARM::t2LDM: 15025f54ce347368105260be2cec497b6a4199dc5789Evan Cheng case ARM::t2LDM_UPD: 15035f54ce347368105260be2cec497b6a4199dc5789Evan Cheng case ARM::t2STM: 15045f54ce347368105260be2cec497b6a4199dc5789Evan Cheng case ARM::t2STM_UPD: { 15053ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng unsigned NumRegs = MI->getNumOperands() - Desc.getNumOperands() + 1; 15063ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng if (Subtarget.isCortexA8()) { 15073ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng // 4 registers would be issued: 1, 2, 1. 15083ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng // 5 registers would be issued: 1, 2, 2. 15093ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng return 1 + (NumRegs / 2); 15103ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng } else if (Subtarget.isCortexA9()) { 15113ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng UOps = (NumRegs / 2); 15123ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng // If there are odd number of registers or if it's not 64-bit aligned, 15133ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng // then it takes an extra AGU (Address Generation Unit) cycle. 15143ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng if ((NumRegs % 2) || 15153ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng !MI->hasOneMemOperand() || 15163ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng (*MI->memoperands_begin())->getAlignment() < 8) 15173ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng ++UOps; 15183ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng return UOps; 15193ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng } else { 15203ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng // Assume the worst. 15213ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng return NumRegs; 15223ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng } 15235f54ce347368105260be2cec497b6a4199dc5789Evan Cheng } 15245f54ce347368105260be2cec497b6a4199dc5789Evan Cheng } 15255f54ce347368105260be2cec497b6a4199dc5789Evan Cheng} 1526