ARMBaseInstrInfo.cpp revision 1c062c24aba08962b4687f56b274f182e5b7a8e5
131c24bf5b39cc8391d4cfdbf8cf5163975fdb81eJim Grosbach//===- ARMBaseInstrInfo.cpp - ARM Instruction Information -------*- C++ -*-===// 2334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// 3334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// The LLVM Compiler Infrastructure 4334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// 5334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// This file is distributed under the University of Illinois Open Source 6334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// License. See LICENSE.TXT for details. 7334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// 8334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin//===----------------------------------------------------------------------===// 9334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// 10334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// This file contains the Base ARM implementation of the TargetInstrInfo class. 11334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// 12334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin//===----------------------------------------------------------------------===// 13334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 14334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "ARMBaseInstrInfo.h" 15334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "ARM.h" 16d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng#include "ARMConstantPoolValue.h" 1748575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng#include "ARMHazardRecognizer.h" 18334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "ARMMachineFunctionInfo.h" 19f95215f551949d5e5adfbf4753aa833b9009b77aAnton Korobeynikov#include "ARMRegisterInfo.h" 20ee04a6d3a40c3017124e3fd89a0db473a2824498Evan Cheng#include "MCTargetDesc/ARMAddressingModes.h" 21fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng#include "llvm/Constants.h" 22fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng#include "llvm/Function.h" 23fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng#include "llvm/GlobalValue.h" 24334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "llvm/CodeGen/LiveVariables.h" 25d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng#include "llvm/CodeGen/MachineConstantPool.h" 26334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "llvm/CodeGen/MachineFrameInfo.h" 27334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "llvm/CodeGen/MachineInstrBuilder.h" 28334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "llvm/CodeGen/MachineJumpTableInfo.h" 29249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov#include "llvm/CodeGen/MachineMemOperand.h" 302457f2c66184e978d4ed8fa9e2128effff26cb0bEvan Cheng#include "llvm/CodeGen/MachineRegisterInfo.h" 31249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov#include "llvm/CodeGen/PseudoSourceValue.h" 32ee04a6d3a40c3017124e3fd89a0db473a2824498Evan Cheng#include "llvm/CodeGen/SelectionDAGNodes.h" 33af76e592c7f9deff0e55c13dbb4a34f07f1c7f64Chris Lattner#include "llvm/MC/MCAsmInfo.h" 34f81b7f6069b27c0a515070dcb392f6828437412fJakub Staszak#include "llvm/Support/BranchProbability.h" 35334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "llvm/Support/CommandLine.h" 36f95215f551949d5e5adfbf4753aa833b9009b77aAnton Korobeynikov#include "llvm/Support/Debug.h" 37c25e7581b9b8088910da31702d4ca21c4734c6d7Torok Edwin#include "llvm/Support/ErrorHandling.h" 3840a5eb18b031fa1a5e9697e21e251e613d441cc5Bill Wendling#include "llvm/ADT/STLExtras.h" 3922fee2dff4c43b551aefa44a96ca74fcade6bfacEvan Cheng 404db3cffe94a5285239cc0056f939c6b74a5ca0b6Evan Cheng#define GET_INSTRINFO_CTOR 4122fee2dff4c43b551aefa44a96ca74fcade6bfacEvan Cheng#include "ARMGenInstrInfo.inc" 4222fee2dff4c43b551aefa44a96ca74fcade6bfacEvan Cheng 43334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinusing namespace llvm; 44334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 45334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinstatic cl::opt<bool> 46334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinEnableARM3Addr("enable-arm-3-addr-conv", cl::Hidden, 47334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin cl::desc("Enable ARM 2-addr to 3-addr conv")); 48334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 4961545829832ba0375249c42c84843d0b62c8f55fJakob Stoklund Olesenstatic cl::opt<bool> 5061545829832ba0375249c42c84843d0b62c8f55fJakob Stoklund OlesenWidenVMOVS("widen-vmovs", cl::Hidden, 5161545829832ba0375249c42c84843d0b62c8f55fJakob Stoklund Olesen cl::desc("Widen ARM vmovs to vmovd when possible")); 5261545829832ba0375249c42c84843d0b62c8f55fJakob Stoklund Olesen 5348575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng/// ARM_MLxEntry - Record information about MLA / MLS instructions. 5448575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Chengstruct ARM_MLxEntry { 5548575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng unsigned MLxOpc; // MLA / MLS opcode 5648575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng unsigned MulOpc; // Expanded multiplication opcode 5748575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng unsigned AddSubOpc; // Expanded add / sub opcode 5848575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng bool NegAcc; // True if the acc is negated before the add / sub. 5948575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng bool HasLane; // True if instruction has an extra "lane" operand. 6048575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng}; 6148575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng 6248575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Chengstatic const ARM_MLxEntry ARM_MLxTable[] = { 6348575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng // MLxOpc, MulOpc, AddSubOpc, NegAcc, HasLane 6448575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng // fp scalar ops 6548575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng { ARM::VMLAS, ARM::VMULS, ARM::VADDS, false, false }, 6648575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng { ARM::VMLSS, ARM::VMULS, ARM::VSUBS, false, false }, 6748575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng { ARM::VMLAD, ARM::VMULD, ARM::VADDD, false, false }, 6848575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng { ARM::VMLSD, ARM::VMULD, ARM::VSUBD, false, false }, 6948575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng { ARM::VNMLAS, ARM::VNMULS, ARM::VSUBS, true, false }, 7048575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng { ARM::VNMLSS, ARM::VMULS, ARM::VSUBS, true, false }, 7148575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng { ARM::VNMLAD, ARM::VNMULD, ARM::VSUBD, true, false }, 7248575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng { ARM::VNMLSD, ARM::VMULD, ARM::VSUBD, true, false }, 7348575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng 7448575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng // fp SIMD ops 7548575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng { ARM::VMLAfd, ARM::VMULfd, ARM::VADDfd, false, false }, 7648575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng { ARM::VMLSfd, ARM::VMULfd, ARM::VSUBfd, false, false }, 7748575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng { ARM::VMLAfq, ARM::VMULfq, ARM::VADDfq, false, false }, 7848575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng { ARM::VMLSfq, ARM::VMULfq, ARM::VSUBfq, false, false }, 7948575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng { ARM::VMLAslfd, ARM::VMULslfd, ARM::VADDfd, false, true }, 8048575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng { ARM::VMLSslfd, ARM::VMULslfd, ARM::VSUBfd, false, true }, 8148575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng { ARM::VMLAslfq, ARM::VMULslfq, ARM::VADDfq, false, true }, 8248575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng { ARM::VMLSslfq, ARM::VMULslfq, ARM::VSUBfq, false, true }, 8348575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng}; 8448575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng 85f95215f551949d5e5adfbf4753aa833b9009b77aAnton KorobeynikovARMBaseInstrInfo::ARMBaseInstrInfo(const ARMSubtarget& STI) 864db3cffe94a5285239cc0056f939c6b74a5ca0b6Evan Cheng : ARMGenInstrInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP), 87f95215f551949d5e5adfbf4753aa833b9009b77aAnton Korobeynikov Subtarget(STI) { 8848575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng for (unsigned i = 0, e = array_lengthof(ARM_MLxTable); i != e; ++i) { 8948575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng if (!MLxEntryMap.insert(std::make_pair(ARM_MLxTable[i].MLxOpc, i)).second) 9048575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng assert(false && "Duplicated entries?"); 9148575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng MLxHazardOpcodes.insert(ARM_MLxTable[i].AddSubOpc); 9248575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng MLxHazardOpcodes.insert(ARM_MLxTable[i].MulOpc); 9348575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng } 9448575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng} 9548575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng 962da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick// Use a ScoreboardHazardRecognizer for prepass ARM scheduling. TargetInstrImpl 972da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick// currently defaults to no prepass hazard recognizer. 9848575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan ChengScheduleHazardRecognizer *ARMBaseInstrInfo:: 992da8bc8a5f7705ac131184cd247f48500da0d74eAndrew TrickCreateTargetHazardRecognizer(const TargetMachine *TM, 1002da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick const ScheduleDAG *DAG) const { 101c8bfd1d78ff9a307d1d4cb57cce4549b538e60f4Andrew Trick if (usePreRAHazardRecognizer()) { 1022da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick const InstrItineraryData *II = TM->getInstrItineraryData(); 1032da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick return new ScoreboardHazardRecognizer(II, DAG, "pre-RA-sched"); 1042da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick } 1052da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick return TargetInstrInfoImpl::CreateTargetHazardRecognizer(TM, DAG); 1062da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick} 1072da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick 1082da8bc8a5f7705ac131184cd247f48500da0d74eAndrew TrickScheduleHazardRecognizer *ARMBaseInstrInfo:: 1092da8bc8a5f7705ac131184cd247f48500da0d74eAndrew TrickCreateTargetPostRAHazardRecognizer(const InstrItineraryData *II, 1102da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick const ScheduleDAG *DAG) const { 11148575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng if (Subtarget.isThumb2() || Subtarget.hasVFP2()) 11248575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng return (ScheduleHazardRecognizer *) 1132da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick new ARMHazardRecognizer(II, *this, getRegisterInfo(), Subtarget, DAG); 1142da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick return TargetInstrInfoImpl::CreateTargetPostRAHazardRecognizer(II, DAG); 115334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 116334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 117334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinMachineInstr * 118334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinARMBaseInstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI, 119334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineBasicBlock::iterator &MBBI, 120334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin LiveVariables *LV) const { 12178703ddafe3d037f75d8ca188e4829d238289ac3Evan Cheng // FIXME: Thumb2 support. 12278703ddafe3d037f75d8ca188e4829d238289ac3Evan Cheng 123334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (!EnableARM3Addr) 124334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return NULL; 125334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 126334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineInstr *MI = MBBI; 127334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineFunction &MF = *MI->getParent()->getParent(); 12899405df044f2c584242e711cc9023ec90356da82Bruno Cardoso Lopes uint64_t TSFlags = MI->getDesc().TSFlags; 129334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool isPre = false; 130334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin switch ((TSFlags & ARMII::IndexModeMask) >> ARMII::IndexModeShift) { 131334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin default: return NULL; 132334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMII::IndexModePre: 133334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin isPre = true; 134334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin break; 135334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMII::IndexModePost: 136334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin break; 137334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 138334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 139334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Try splitting an indexed load/store to an un-indexed one plus an add/sub 140334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // operation. 141334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned MemOpc = getUnindexedOpcode(MI->getOpcode()); 142334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (MemOpc == 0) 143334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return NULL; 144334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 145334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineInstr *UpdateMI = NULL; 146334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineInstr *MemMI = NULL; 147334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned AddrMode = (TSFlags & ARMII::AddrModeMask); 148e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng const MCInstrDesc &MCID = MI->getDesc(); 149e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng unsigned NumOps = MCID.getNumOperands(); 150e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng bool isLoad = !MCID.mayStore(); 151334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const MachineOperand &WB = isLoad ? MI->getOperand(1) : MI->getOperand(0); 152334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const MachineOperand &Base = MI->getOperand(2); 153334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const MachineOperand &Offset = MI->getOperand(NumOps-3); 154334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned WBReg = WB.getReg(); 155334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned BaseReg = Base.getReg(); 156334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned OffReg = Offset.getReg(); 157334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned OffImm = MI->getOperand(NumOps-2).getImm(); 158334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin ARMCC::CondCodes Pred = (ARMCC::CondCodes)MI->getOperand(NumOps-1).getImm(); 159334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin switch (AddrMode) { 160334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin default: 161334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin assert(false && "Unknown indexed op!"); 162334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return NULL; 163334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMII::AddrMode2: { 164334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool isSub = ARM_AM::getAM2Op(OffImm) == ARM_AM::sub; 165334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned Amt = ARM_AM::getAM2Offset(OffImm); 166334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (OffReg == 0) { 167e7cbe4118b7ddf05032ff8772a98c51e1637bb5cEvan Cheng if (ARM_AM::getSOImmVal(Amt) == -1) 168334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Can't encode it in a so_imm operand. This transformation will 169334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // add more than 1 instruction. Abandon! 170334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return NULL; 171334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin UpdateMI = BuildMI(MF, MI->getDebugLoc(), 17278703ddafe3d037f75d8ca188e4829d238289ac3Evan Cheng get(isSub ? ARM::SUBri : ARM::ADDri), WBReg) 173e7cbe4118b7ddf05032ff8772a98c51e1637bb5cEvan Cheng .addReg(BaseReg).addImm(Amt) 174334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addImm(Pred).addReg(0).addReg(0); 175334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } else if (Amt != 0) { 176334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin ARM_AM::ShiftOpc ShOpc = ARM_AM::getAM2ShiftOpc(OffImm); 177334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned SOOpc = ARM_AM::getSORegOpc(ShOpc, Amt); 178334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin UpdateMI = BuildMI(MF, MI->getDebugLoc(), 17992a202213bb4c20301abf6ab64e46df3695e60bfOwen Anderson get(isSub ? ARM::SUBrsi : ARM::ADDrsi), WBReg) 180334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(BaseReg).addReg(OffReg).addReg(0).addImm(SOOpc) 181334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addImm(Pred).addReg(0).addReg(0); 182334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } else 183334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin UpdateMI = BuildMI(MF, MI->getDebugLoc(), 18478703ddafe3d037f75d8ca188e4829d238289ac3Evan Cheng get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg) 185334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(BaseReg).addReg(OffReg) 186334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addImm(Pred).addReg(0).addReg(0); 187334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin break; 188334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 189334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMII::AddrMode3 : { 190334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool isSub = ARM_AM::getAM3Op(OffImm) == ARM_AM::sub; 191334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned Amt = ARM_AM::getAM3Offset(OffImm); 192334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (OffReg == 0) 193334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Immediate is 8-bits. It's guaranteed to fit in a so_imm operand. 194334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin UpdateMI = BuildMI(MF, MI->getDebugLoc(), 19578703ddafe3d037f75d8ca188e4829d238289ac3Evan Cheng get(isSub ? ARM::SUBri : ARM::ADDri), WBReg) 196334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(BaseReg).addImm(Amt) 197334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addImm(Pred).addReg(0).addReg(0); 198334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin else 199334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin UpdateMI = BuildMI(MF, MI->getDebugLoc(), 20078703ddafe3d037f75d8ca188e4829d238289ac3Evan Cheng get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg) 201334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(BaseReg).addReg(OffReg) 202334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addImm(Pred).addReg(0).addReg(0); 203334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin break; 204334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 205334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 206334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 207334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin std::vector<MachineInstr*> NewMIs; 208334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (isPre) { 209334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (isLoad) 210334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MemMI = BuildMI(MF, MI->getDebugLoc(), 211334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin get(MemOpc), MI->getOperand(0).getReg()) 2123e5561247202bae994dd259a2d8dc4eff8f799f3Jim Grosbach .addReg(WBReg).addImm(0).addImm(Pred); 213334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin else 214334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MemMI = BuildMI(MF, MI->getDebugLoc(), 215334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin get(MemOpc)).addReg(MI->getOperand(1).getReg()) 216334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(WBReg).addReg(0).addImm(0).addImm(Pred); 217334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin NewMIs.push_back(MemMI); 218334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin NewMIs.push_back(UpdateMI); 219334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } else { 220334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (isLoad) 221334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MemMI = BuildMI(MF, MI->getDebugLoc(), 222334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin get(MemOpc), MI->getOperand(0).getReg()) 2233e5561247202bae994dd259a2d8dc4eff8f799f3Jim Grosbach .addReg(BaseReg).addImm(0).addImm(Pred); 224334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin else 225334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MemMI = BuildMI(MF, MI->getDebugLoc(), 226334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin get(MemOpc)).addReg(MI->getOperand(1).getReg()) 227334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred); 228334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (WB.isDead()) 229334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin UpdateMI->getOperand(0).setIsDead(); 230334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin NewMIs.push_back(UpdateMI); 231334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin NewMIs.push_back(MemMI); 232334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 233334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 234334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Transfer LiveVariables states, kill / dead info. 235334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (LV) { 236334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 237334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineOperand &MO = MI->getOperand(i); 238c9df025e33ac435adb3b3318d237c36ca7cec659Jakob Stoklund Olesen if (MO.isReg() && TargetRegisterInfo::isVirtualRegister(MO.getReg())) { 239334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned Reg = MO.getReg(); 240334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 241334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin LiveVariables::VarInfo &VI = LV->getVarInfo(Reg); 242334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (MO.isDef()) { 243334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineInstr *NewMI = (Reg == WBReg) ? UpdateMI : MemMI; 244334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (MO.isDead()) 245334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin LV->addVirtualRegisterDead(Reg, NewMI); 246334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 247334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (MO.isUse() && MO.isKill()) { 248334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin for (unsigned j = 0; j < 2; ++j) { 249334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Look at the two new MI's in reverse order. 250334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineInstr *NewMI = NewMIs[j]; 251334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (!NewMI->readsRegister(Reg)) 252334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin continue; 253334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin LV->addVirtualRegisterKilled(Reg, NewMI); 254334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (VI.removeKill(MI)) 255334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin VI.Kills.push_back(NewMI); 256334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin break; 257334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 258334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 259334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 260334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 261334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 262334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 263334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MFI->insert(MBBI, NewMIs[1]); 264334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MFI->insert(MBBI, NewMIs[0]); 265334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return NewMIs[0]; 266334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 267334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 268334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// Branch analysis. 269334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinbool 270334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinARMBaseInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB, 271334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineBasicBlock *&FBB, 272334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin SmallVectorImpl<MachineOperand> &Cond, 273334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool AllowModify) const { 274334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // If the block has no terminators, it just falls into the block after it. 275334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineBasicBlock::iterator I = MBB.end(); 27693d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen if (I == MBB.begin()) 27793d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen return false; 27893d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen --I; 27993d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen while (I->isDebugValue()) { 28093d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen if (I == MBB.begin()) 28193d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen return false; 28293d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen --I; 28393d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen } 28493d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen if (!isUnpredicatedTerminator(I)) 285334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 286334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 287334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Get the last instruction in the block. 288334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineInstr *LastInst = I; 289334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 290334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // If there is only one terminator instruction, process it. 291334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned LastOpc = LastInst->getOpcode(); 292334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) { 2935ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng if (isUncondBranchOpcode(LastOpc)) { 294334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin TBB = LastInst->getOperand(0).getMBB(); 295334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 296334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 2975ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng if (isCondBranchOpcode(LastOpc)) { 298334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Block ends with fall-through condbranch. 299334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin TBB = LastInst->getOperand(0).getMBB(); 300334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin Cond.push_back(LastInst->getOperand(1)); 301334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin Cond.push_back(LastInst->getOperand(2)); 302334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 303334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 304334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; // Can't handle indirect branch. 305334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 306334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 307334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Get the instruction before it if it is a terminator. 308334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineInstr *SecondLastInst = I; 309108c8724663354050dc09bb1262c3e4511adf82fEvan Cheng unsigned SecondLastOpc = SecondLastInst->getOpcode(); 310108c8724663354050dc09bb1262c3e4511adf82fEvan Cheng 311108c8724663354050dc09bb1262c3e4511adf82fEvan Cheng // If AllowModify is true and the block ends with two or more unconditional 312108c8724663354050dc09bb1262c3e4511adf82fEvan Cheng // branches, delete all but the first unconditional branch. 313108c8724663354050dc09bb1262c3e4511adf82fEvan Cheng if (AllowModify && isUncondBranchOpcode(LastOpc)) { 314108c8724663354050dc09bb1262c3e4511adf82fEvan Cheng while (isUncondBranchOpcode(SecondLastOpc)) { 315108c8724663354050dc09bb1262c3e4511adf82fEvan Cheng LastInst->eraseFromParent(); 316108c8724663354050dc09bb1262c3e4511adf82fEvan Cheng LastInst = SecondLastInst; 317108c8724663354050dc09bb1262c3e4511adf82fEvan Cheng LastOpc = LastInst->getOpcode(); 318676e258366dd17a0b4ee6ac66914237ce181202eEvan Cheng if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) { 319676e258366dd17a0b4ee6ac66914237ce181202eEvan Cheng // Return now the only terminator is an unconditional branch. 320676e258366dd17a0b4ee6ac66914237ce181202eEvan Cheng TBB = LastInst->getOperand(0).getMBB(); 321676e258366dd17a0b4ee6ac66914237ce181202eEvan Cheng return false; 322676e258366dd17a0b4ee6ac66914237ce181202eEvan Cheng } else { 323108c8724663354050dc09bb1262c3e4511adf82fEvan Cheng SecondLastInst = I; 324108c8724663354050dc09bb1262c3e4511adf82fEvan Cheng SecondLastOpc = SecondLastInst->getOpcode(); 325108c8724663354050dc09bb1262c3e4511adf82fEvan Cheng } 326108c8724663354050dc09bb1262c3e4511adf82fEvan Cheng } 327108c8724663354050dc09bb1262c3e4511adf82fEvan Cheng } 328334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 329334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // If there are three terminators, we don't know what sort of block this is. 330334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(--I)) 331334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; 332334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 3335ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng // If the block ends with a B and a Bcc, handle it. 3345ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng if (isCondBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) { 335334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin TBB = SecondLastInst->getOperand(0).getMBB(); 336334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin Cond.push_back(SecondLastInst->getOperand(1)); 337334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin Cond.push_back(SecondLastInst->getOperand(2)); 338334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin FBB = LastInst->getOperand(0).getMBB(); 339334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 340334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 341334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 342334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // If the block ends with two unconditional branches, handle it. The second 343334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // one is not executed, so remove it. 3445ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng if (isUncondBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) { 345334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin TBB = SecondLastInst->getOperand(0).getMBB(); 346334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin I = LastInst; 347334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (AllowModify) 348334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin I->eraseFromParent(); 349334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 350334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 351334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 352334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // ...likewise if it ends with a branch table followed by an unconditional 353334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // branch. The branch folder can create these, and we must get rid of them for 354334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // correctness of Thumb constant islands. 3558d4de5abfa1bcd974554ea14904ebf7af289e84dBob Wilson if ((isJumpTableBranchOpcode(SecondLastOpc) || 3568d4de5abfa1bcd974554ea14904ebf7af289e84dBob Wilson isIndirectBranchOpcode(SecondLastOpc)) && 3575ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng isUncondBranchOpcode(LastOpc)) { 358334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin I = LastInst; 359334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (AllowModify) 360334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin I->eraseFromParent(); 361334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; 362334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 363334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 364334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Otherwise, can't handle this. 365334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; 366334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 367334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 368334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 369334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinunsigned ARMBaseInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const { 370334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineBasicBlock::iterator I = MBB.end(); 371334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (I == MBB.begin()) return 0; 372334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin --I; 37393d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen while (I->isDebugValue()) { 37493d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen if (I == MBB.begin()) 37593d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen return 0; 37693d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen --I; 37793d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen } 3785ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng if (!isUncondBranchOpcode(I->getOpcode()) && 3795ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng !isCondBranchOpcode(I->getOpcode())) 380334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 0; 381334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 382334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Remove the branch. 383334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin I->eraseFromParent(); 384334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 385334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin I = MBB.end(); 386334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 387334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (I == MBB.begin()) return 1; 388334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin --I; 3895ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng if (!isCondBranchOpcode(I->getOpcode())) 390334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 1; 391334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 392334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Remove the branch. 393334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin I->eraseFromParent(); 394334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 2; 395334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 396334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 397334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinunsigned 398334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinARMBaseInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 3993bf912593301152b65accb9d9c37a95172f1df5aStuart Hastings MachineBasicBlock *FBB, 4003bf912593301152b65accb9d9c37a95172f1df5aStuart Hastings const SmallVectorImpl<MachineOperand> &Cond, 4013bf912593301152b65accb9d9c37a95172f1df5aStuart Hastings DebugLoc DL) const { 4026495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ARMFunctionInfo *AFI = MBB.getParent()->getInfo<ARMFunctionInfo>(); 4036495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng int BOpc = !AFI->isThumbFunction() 4046495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ? ARM::B : (AFI->isThumb2Function() ? ARM::t2B : ARM::tB); 4056495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng int BccOpc = !AFI->isThumbFunction() 4066495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ? ARM::Bcc : (AFI->isThumb2Function() ? ARM::t2Bcc : ARM::tBcc); 40751f6a7abf27fc92c3d8904c2334feab8b498e8e9Owen Anderson bool isThumb = AFI->isThumbFunction() || AFI->isThumb2Function(); 408e23dc9c0ef50b0a1934c04c1786f3a0478d62f41Andrew Trick 409334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Shouldn't be a fall through. 410334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin assert(TBB && "InsertBranch must not be told to insert a fallthrough"); 411334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin assert((Cond.size() == 2 || Cond.size() == 0) && 412334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin "ARM branch conditions have two components!"); 413334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 414334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (FBB == 0) { 415112fb73502d54dd7dd61ae2de24c92d4df181294Owen Anderson if (Cond.empty()) { // Unconditional branch? 41651f6a7abf27fc92c3d8904c2334feab8b498e8e9Owen Anderson if (isThumb) 41751f6a7abf27fc92c3d8904c2334feab8b498e8e9Owen Anderson BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB).addImm(ARMCC::AL).addReg(0); 41851f6a7abf27fc92c3d8904c2334feab8b498e8e9Owen Anderson else 41951f6a7abf27fc92c3d8904c2334feab8b498e8e9Owen Anderson BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB); 420112fb73502d54dd7dd61ae2de24c92d4df181294Owen Anderson } else 4213bf912593301152b65accb9d9c37a95172f1df5aStuart Hastings BuildMI(&MBB, DL, get(BccOpc)).addMBB(TBB) 422334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()); 423334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 1; 424334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 425334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 426334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Two-way conditional branch. 4273bf912593301152b65accb9d9c37a95172f1df5aStuart Hastings BuildMI(&MBB, DL, get(BccOpc)).addMBB(TBB) 428334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()); 42951f6a7abf27fc92c3d8904c2334feab8b498e8e9Owen Anderson if (isThumb) 43051f6a7abf27fc92c3d8904c2334feab8b498e8e9Owen Anderson BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB).addImm(ARMCC::AL).addReg(0); 43151f6a7abf27fc92c3d8904c2334feab8b498e8e9Owen Anderson else 43251f6a7abf27fc92c3d8904c2334feab8b498e8e9Owen Anderson BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB); 433334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 2; 434334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 435334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 436334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinbool ARMBaseInstrInfo:: 437334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const { 438334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin ARMCC::CondCodes CC = (ARMCC::CondCodes)(int)Cond[0].getImm(); 439334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin Cond[0].setImm(ARMCC::getOppositeCondition(CC)); 440334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 441334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 442334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 443334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinbool ARMBaseInstrInfo:: 444334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinPredicateInstruction(MachineInstr *MI, 445334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const SmallVectorImpl<MachineOperand> &Pred) const { 446334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned Opc = MI->getOpcode(); 4475ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng if (isUncondBranchOpcode(Opc)) { 4485ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng MI->setDesc(get(getMatchingCondBranchOpcode(Opc))); 449334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI->addOperand(MachineOperand::CreateImm(Pred[0].getImm())); 450334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI->addOperand(MachineOperand::CreateReg(Pred[1].getReg(), false)); 451334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; 452334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 453334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 454334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin int PIdx = MI->findFirstPredOperandIdx(); 455334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (PIdx != -1) { 456334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineOperand &PMO = MI->getOperand(PIdx); 457334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin PMO.setImm(Pred[0].getImm()); 458334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI->getOperand(PIdx+1).setReg(Pred[1].getReg()); 459334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; 460334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 461334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 462334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 463334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 464334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinbool ARMBaseInstrInfo:: 465334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinSubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1, 466334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const SmallVectorImpl<MachineOperand> &Pred2) const { 467334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (Pred1.size() > 2 || Pred2.size() > 2) 468334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 469334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 470334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin ARMCC::CondCodes CC1 = (ARMCC::CondCodes)Pred1[0].getImm(); 471334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin ARMCC::CondCodes CC2 = (ARMCC::CondCodes)Pred2[0].getImm(); 472334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (CC1 == CC2) 473334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; 474334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 475334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin switch (CC1) { 476334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin default: 477334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 478334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMCC::AL: 479334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; 480334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMCC::HS: 481334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return CC2 == ARMCC::HI; 482334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMCC::LS: 483334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return CC2 == ARMCC::LO || CC2 == ARMCC::EQ; 484334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMCC::GE: 485334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return CC2 == ARMCC::GT; 486334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMCC::LE: 487334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return CC2 == ARMCC::LT; 488334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 489334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 490334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 491334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinbool ARMBaseInstrInfo::DefinesPredicate(MachineInstr *MI, 492334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin std::vector<MachineOperand> &Pred) const { 4938fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng // FIXME: This confuses implicit_def with optional CPSR def. 494e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng const MCInstrDesc &MCID = MI->getDesc(); 495e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng if (!MCID.getImplicitDefs() && !MCID.hasOptionalDef()) 496334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 497334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 498334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool Found = false; 499334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 500334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const MachineOperand &MO = MI->getOperand(i); 501334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (MO.isReg() && MO.getReg() == ARM::CPSR) { 502334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin Pred.push_back(MO); 503334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin Found = true; 504334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 505334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 506334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 507334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return Found; 508334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 509334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 510ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng/// isPredicable - Return true if the specified instruction can be predicated. 511ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng/// By default, this returns true for every instruction with a 512ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng/// PredicateOperand. 513ac0869dc8a7986855c5557cc67d4709600158ef5Evan Chengbool ARMBaseInstrInfo::isPredicable(MachineInstr *MI) const { 514e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng const MCInstrDesc &MCID = MI->getDesc(); 515e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng if (!MCID.isPredicable()) 516ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng return false; 517ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng 518e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng if ((MCID.TSFlags & ARMII::DomainMask) == ARMII::DomainNEON) { 519ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng ARMFunctionInfo *AFI = 520ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng MI->getParent()->getParent()->getInfo<ARMFunctionInfo>(); 521d7f0810c934a7d13acb28c42d737ce58ec990ea8Evan Cheng return AFI->isThumb2Function(); 522ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng } 523ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng return true; 524ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng} 525334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 52656856b1f46ec1f073ceef4e826c544b8b1691608Chris Lattner/// FIXME: Works around a gcc miscompilation with -fstrict-aliasing. 52719e57025d458d3cb50804fd821fd89b868a819bdChandler CarruthLLVM_ATTRIBUTE_NOINLINE 528334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinstatic unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT, 52956856b1f46ec1f073ceef4e826c544b8b1691608Chris Lattner unsigned JTI); 530334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinstatic unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT, 531334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned JTI) { 53256856b1f46ec1f073ceef4e826c544b8b1691608Chris Lattner assert(JTI < JT.size()); 533334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return JT[JTI].MBBs.size(); 534334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 535334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 536334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin/// GetInstSize - Return the size of the specified MachineInstr. 537334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin/// 538334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinunsigned ARMBaseInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const { 539334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const MachineBasicBlock &MBB = *MI->getParent(); 540334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const MachineFunction *MF = MBB.getParent(); 54133adcfb4d217f5f23d9bde8ba02b8e48f9605fc5Chris Lattner const MCAsmInfo *MAI = MF->getTarget().getMCAsmInfo(); 542334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 543e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng const MCInstrDesc &MCID = MI->getDesc(); 54416884415db751c75f2133bd04921393c792b1158Owen Anderson if (MCID.getSize()) 54516884415db751c75f2133bd04921393c792b1158Owen Anderson return MCID.getSize(); 546334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 547334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // If this machine instr is an inline asm, measure it. 548334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (MI->getOpcode() == ARM::INLINEASM) 54933adcfb4d217f5f23d9bde8ba02b8e48f9605fc5Chris Lattner return getInlineAsmLength(MI->getOperand(0).getSymbolName(), *MAI); 550334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (MI->isLabel()) 551334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 0; 55216884415db751c75f2133bd04921393c792b1158Owen Anderson unsigned Opc = MI->getOpcode(); 553a0ee862f2e3a0d202244e02459ddcf0dca0e8607Evan Cheng switch (Opc) { 554518bb53485df640d7b7e3f6b0544099020c42aa7Chris Lattner case TargetOpcode::IMPLICIT_DEF: 555518bb53485df640d7b7e3f6b0544099020c42aa7Chris Lattner case TargetOpcode::KILL: 5567431beaba2a01c3fe299c861b2ec85cbf1dc81c4Bill Wendling case TargetOpcode::PROLOG_LABEL: 557518bb53485df640d7b7e3f6b0544099020c42aa7Chris Lattner case TargetOpcode::EH_LABEL: 558375be7730a6f3dee7a6dc319ee6c355a11ac99adDale Johannesen case TargetOpcode::DBG_VALUE: 559334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 0; 56053519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng case ARM::MOVi16_ga_pcrel: 56153519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng case ARM::MOVTi16_ga_pcrel: 56253519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng case ARM::t2MOVi16_ga_pcrel: 56353519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng case ARM::t2MOVTi16_ga_pcrel: 5645de5d4b6d0eb3fd379fa571d82f6fa764460b3b8Evan Cheng return 4; 5653c38f96af2a5443d9f72fd078c2c98dd08746e51Jim Grosbach case ARM::MOVi32imm: 5663c38f96af2a5443d9f72fd078c2c98dd08746e51Jim Grosbach case ARM::t2MOVi32imm: 5673c38f96af2a5443d9f72fd078c2c98dd08746e51Jim Grosbach return 8; 568334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARM::CONSTPOOL_ENTRY: 569334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // If this machine instr is a constant pool entry, its size is recorded as 570334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // operand #2. 571334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return MI->getOperand(2).getImm(); 5725eb195153950bc7ebfc30649494a78b2096b5ef8Jim Grosbach case ARM::Int_eh_sjlj_longjmp: 5735eb195153950bc7ebfc30649494a78b2096b5ef8Jim Grosbach return 16; 5745eb195153950bc7ebfc30649494a78b2096b5ef8Jim Grosbach case ARM::tInt_eh_sjlj_longjmp: 5755eb195153950bc7ebfc30649494a78b2096b5ef8Jim Grosbach return 10; 576789476240d6b6f8ad9366cadf790a82bd41bb0b3Evan Cheng case ARM::Int_eh_sjlj_setjmp: 577d100755bab38784703f677b8b8eb174b624b346bJim Grosbach case ARM::Int_eh_sjlj_setjmp_nofp: 5780798eddd07b8dc827a4e6e9028c4c3a8d9444286Jim Grosbach return 20; 579d122874996a6faa8832569b632fd73a32ace7ae7Jim Grosbach case ARM::tInt_eh_sjlj_setjmp: 5805aa1684e5da9a85286bf7d29da419d261a70c2f2Jim Grosbach case ARM::t2Int_eh_sjlj_setjmp: 581d100755bab38784703f677b8b8eb174b624b346bJim Grosbach case ARM::t2Int_eh_sjlj_setjmp_nofp: 5820798eddd07b8dc827a4e6e9028c4c3a8d9444286Jim Grosbach return 12; 583334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARM::BR_JTr: 584334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARM::BR_JTm: 585334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARM::BR_JTadd: 586a0ee862f2e3a0d202244e02459ddcf0dca0e8607Evan Cheng case ARM::tBR_JTr: 587d26b14c34cbcee1448b86b524578fc51cc979023Evan Cheng case ARM::t2BR_JT: 588d092a87ba3f905a6801a0bdf816267329cf0391cJim Grosbach case ARM::t2TBB_JT: 589d092a87ba3f905a6801a0bdf816267329cf0391cJim Grosbach case ARM::t2TBH_JT: { 590334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // These are jumptable branches, i.e. a branch followed by an inlined 591d26b14c34cbcee1448b86b524578fc51cc979023Evan Cheng // jumptable. The size is 4 + 4 * number of entries. For TBB, each 592d26b14c34cbcee1448b86b524578fc51cc979023Evan Cheng // entry is one byte; TBH two byte each. 593d092a87ba3f905a6801a0bdf816267329cf0391cJim Grosbach unsigned EntrySize = (Opc == ARM::t2TBB_JT) 594d092a87ba3f905a6801a0bdf816267329cf0391cJim Grosbach ? 1 : ((Opc == ARM::t2TBH_JT) ? 2 : 4); 595e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng unsigned NumOps = MCID.getNumOperands(); 596334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineOperand JTOP = 597e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng MI->getOperand(NumOps - (MCID.isPredicable() ? 3 : 2)); 598334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned JTI = JTOP.getIndex(); 599334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo(); 600b1e803985d3378538ae9cff7eed4102c002d1e22Chris Lattner assert(MJTI != 0); 601334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables(); 602334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin assert(JTI < JT.size()); 603334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Thumb instructions are 2 byte aligned, but JT entries are 4 byte 604334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // 4 aligned. The assembler / linker may add 2 byte padding just before 605334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // the JT entries. The size does not include this padding; the 606334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // constant islands pass does separate bookkeeping for it. 607334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // FIXME: If we know the size of the function is less than (1 << 16) *2 608334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // bytes, we can use 16-bit entries instead. Then there won't be an 609334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // alignment issue. 61025f7cfc3cccba6f569f29f79ea533bae960b93c0Evan Cheng unsigned InstSize = (Opc == ARM::tBR_JTr || Opc == ARM::t2BR_JT) ? 2 : 4; 61125f7cfc3cccba6f569f29f79ea533bae960b93c0Evan Cheng unsigned NumEntries = getNumJTEntries(JT, JTI); 612d092a87ba3f905a6801a0bdf816267329cf0391cJim Grosbach if (Opc == ARM::t2TBB_JT && (NumEntries & 1)) 61325f7cfc3cccba6f569f29f79ea533bae960b93c0Evan Cheng // Make sure the instruction that follows TBB is 2-byte aligned. 61425f7cfc3cccba6f569f29f79ea533bae960b93c0Evan Cheng // FIXME: Constant island pass should insert an "ALIGN" instruction 61525f7cfc3cccba6f569f29f79ea533bae960b93c0Evan Cheng // instead. 61625f7cfc3cccba6f569f29f79ea533bae960b93c0Evan Cheng ++NumEntries; 61725f7cfc3cccba6f569f29f79ea533bae960b93c0Evan Cheng return NumEntries * EntrySize + InstSize; 618334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 619334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin default: 620334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Otherwise, pseudo-instruction sizes are zero. 621334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 0; 622334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 623334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 0; // Not reached 624334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 625334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 626ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesenvoid ARMBaseInstrInfo::copyPhysReg(MachineBasicBlock &MBB, 627ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen MachineBasicBlock::iterator I, DebugLoc DL, 628ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen unsigned DestReg, unsigned SrcReg, 629ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen bool KillSrc) const { 630ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen bool GPRDest = ARM::GPRRegClass.contains(DestReg); 631ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen bool GPRSrc = ARM::GPRRegClass.contains(SrcReg); 632ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen 633ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen if (GPRDest && GPRSrc) { 634ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen AddDefaultCC(AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::MOVr), DestReg) 635ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen .addReg(SrcReg, getKillRegState(KillSrc)))); 636ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen return; 6377bfdca0206f51132b26094c6f83a5ac97ee0f943David Goodwin } 638334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 639ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen bool SPRDest = ARM::SPRRegClass.contains(DestReg); 640ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen bool SPRSrc = ARM::SPRRegClass.contains(SrcReg); 641ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen 642e5038e191db82d4d92fdeec1b5bce5cae21f6d8fChad Rosier unsigned Opc = 0; 643142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen if (SPRDest && SPRSrc) 644ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen Opc = ARM::VMOVS; 645142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen else if (GPRDest && SPRSrc) 646ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen Opc = ARM::VMOVRS; 647ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen else if (SPRDest && GPRSrc) 648ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen Opc = ARM::VMOVSR; 649ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen else if (ARM::DPRRegClass.contains(DestReg, SrcReg)) 650ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen Opc = ARM::VMOVD; 651ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen else if (ARM::QPRRegClass.contains(DestReg, SrcReg)) 65243967a97cf9a296623e1cf5ed643e2f40b7e5766Owen Anderson Opc = ARM::VORRq; 653e5038e191db82d4d92fdeec1b5bce5cae21f6d8fChad Rosier 654e5038e191db82d4d92fdeec1b5bce5cae21f6d8fChad Rosier if (Opc) { 655e5038e191db82d4d92fdeec1b5bce5cae21f6d8fChad Rosier MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc), DestReg); 65643967a97cf9a296623e1cf5ed643e2f40b7e5766Owen Anderson MIB.addReg(SrcReg, getKillRegState(KillSrc)); 657e5038e191db82d4d92fdeec1b5bce5cae21f6d8fChad Rosier if (Opc == ARM::VORRq) 658e5038e191db82d4d92fdeec1b5bce5cae21f6d8fChad Rosier MIB.addReg(SrcReg, getKillRegState(KillSrc)); 659fea95c6bade86fcfa5bd07efdda9bd902f53be8cChad Rosier AddDefaultPred(MIB); 660e5038e191db82d4d92fdeec1b5bce5cae21f6d8fChad Rosier return; 661e5038e191db82d4d92fdeec1b5bce5cae21f6d8fChad Rosier } 662e5038e191db82d4d92fdeec1b5bce5cae21f6d8fChad Rosier 663fea95c6bade86fcfa5bd07efdda9bd902f53be8cChad Rosier // Generate instructions for VMOVQQ and VMOVQQQQ pseudos in place. 664fea95c6bade86fcfa5bd07efdda9bd902f53be8cChad Rosier if (ARM::QQPRRegClass.contains(DestReg, SrcReg) || 665fea95c6bade86fcfa5bd07efdda9bd902f53be8cChad Rosier ARM::QQQQPRRegClass.contains(DestReg, SrcReg)) { 666e5038e191db82d4d92fdeec1b5bce5cae21f6d8fChad Rosier const TargetRegisterInfo *TRI = &getRegisterInfo(); 667e5038e191db82d4d92fdeec1b5bce5cae21f6d8fChad Rosier assert(ARM::qsub_0 + 3 == ARM::qsub_3 && "Expected contiguous enum."); 668e23dc9c0ef50b0a1934c04c1786f3a0478d62f41Andrew Trick unsigned EndSubReg = ARM::QQPRRegClass.contains(DestReg, SrcReg) ? 669fea95c6bade86fcfa5bd07efdda9bd902f53be8cChad Rosier ARM::qsub_1 : ARM::qsub_3; 670e23dc9c0ef50b0a1934c04c1786f3a0478d62f41Andrew Trick for (unsigned i = ARM::qsub_0, e = EndSubReg + 1; i != e; ++i) { 671e5038e191db82d4d92fdeec1b5bce5cae21f6d8fChad Rosier unsigned Dst = TRI->getSubReg(DestReg, i); 672e5038e191db82d4d92fdeec1b5bce5cae21f6d8fChad Rosier unsigned Src = TRI->getSubReg(SrcReg, i); 673e5038e191db82d4d92fdeec1b5bce5cae21f6d8fChad Rosier MachineInstrBuilder Mov = 674e5038e191db82d4d92fdeec1b5bce5cae21f6d8fChad Rosier AddDefaultPred(BuildMI(MBB, I, I->getDebugLoc(), get(ARM::VORRq)) 675e5038e191db82d4d92fdeec1b5bce5cae21f6d8fChad Rosier .addReg(Dst, RegState::Define) 676e5038e191db82d4d92fdeec1b5bce5cae21f6d8fChad Rosier .addReg(Src, getKillRegState(KillSrc)) 677e5038e191db82d4d92fdeec1b5bce5cae21f6d8fChad Rosier .addReg(Src, getKillRegState(KillSrc))); 678fea95c6bade86fcfa5bd07efdda9bd902f53be8cChad Rosier if (i == EndSubReg) { 679e5038e191db82d4d92fdeec1b5bce5cae21f6d8fChad Rosier Mov->addRegisterDefined(DestReg, TRI); 680e5038e191db82d4d92fdeec1b5bce5cae21f6d8fChad Rosier if (KillSrc) 681e5038e191db82d4d92fdeec1b5bce5cae21f6d8fChad Rosier Mov->addRegisterKilled(SrcReg, TRI); 682e5038e191db82d4d92fdeec1b5bce5cae21f6d8fChad Rosier } 683e5038e191db82d4d92fdeec1b5bce5cae21f6d8fChad Rosier } 684e5038e191db82d4d92fdeec1b5bce5cae21f6d8fChad Rosier return; 685e5038e191db82d4d92fdeec1b5bce5cae21f6d8fChad Rosier } 686e5038e191db82d4d92fdeec1b5bce5cae21f6d8fChad Rosier llvm_unreachable("Impossible reg-to-reg copy"); 687334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 688334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 689c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Chengstatic const 690c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan ChengMachineInstrBuilder &AddDReg(MachineInstrBuilder &MIB, 691c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Cheng unsigned Reg, unsigned SubIdx, unsigned State, 692c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Cheng const TargetRegisterInfo *TRI) { 693c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Cheng if (!SubIdx) 694c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Cheng return MIB.addReg(Reg, State); 695c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Cheng 696c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Cheng if (TargetRegisterInfo::isPhysicalRegister(Reg)) 697c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Cheng return MIB.addReg(TRI->getSubReg(Reg, SubIdx), State); 698c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Cheng return MIB.addReg(Reg, State, SubIdx); 699c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Cheng} 700c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Cheng 701334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinvoid ARMBaseInstrInfo:: 702334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinstoreRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 703334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned SrcReg, bool isKill, int FI, 704746ad69e088176819981b4b2c5ac8dcd49f5e60eEvan Cheng const TargetRegisterClass *RC, 705746ad69e088176819981b4b2c5ac8dcd49f5e60eEvan Cheng const TargetRegisterInfo *TRI) const { 706c7f3ace20c325521c68335a1689645b43b06ddf0Chris Lattner DebugLoc DL; 707334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (I != MBB.end()) DL = I->getDebugLoc(); 708249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MachineFunction &MF = *MBB.getParent(); 709249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MachineFrameInfo &MFI = *MF.getFrameInfo(); 71031bc849123011b8eae6bb3c79876d9a3c26a6a1dJim Grosbach unsigned Align = MFI.getObjectAlignment(FI); 711249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov 712249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MachineMemOperand *MMO = 71359db5496f4fc2ef6111569e542f8b65480ef14c1Chris Lattner MF.getMachineMemOperand(MachinePointerInfo( 71459db5496f4fc2ef6111569e542f8b65480ef14c1Chris Lattner PseudoSourceValue::getFixedStack(FI)), 71559db5496f4fc2ef6111569e542f8b65480ef14c1Chris Lattner MachineMemOperand::MOStore, 716249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MFI.getObjectSize(FI), 71731bc849123011b8eae6bb3c79876d9a3c26a6a1dJim Grosbach Align); 718334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 719e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson switch (RC->getSize()) { 720e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson case 4: 721e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson if (ARM::GPRRegClass.hasSubClassEq(RC)) { 722e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::STRi12)) 723334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(SrcReg, getKillRegState(isKill)) 7247e3383c007f53b3a00675af225e428cb66ddf404Jim Grosbach .addFrameIndex(FI).addImm(0).addMemOperand(MMO)); 725e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson } else if (ARM::SPRRegClass.hasSubClassEq(RC)) { 726e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTRS)) 727d31c5496d7e1580058b5c6fbc8fd537a641ea590Evan Cheng .addReg(SrcReg, getKillRegState(isKill)) 728d31c5496d7e1580058b5c6fbc8fd537a641ea590Evan Cheng .addFrameIndex(FI).addImm(0).addMemOperand(MMO)); 729e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson } else 730e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson llvm_unreachable("Unknown reg class!"); 731e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson break; 732e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson case 8: 733e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson if (ARM::DPRRegClass.hasSubClassEq(RC)) { 734e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTRD)) 735334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(SrcReg, getKillRegState(isKill)) 736249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov .addFrameIndex(FI).addImm(0).addMemOperand(MMO)); 737e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson } else 738e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson llvm_unreachable("Unknown reg class!"); 739e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson break; 740e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson case 16: 741e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson if (ARM::QPRRegClass.hasSubClassEq(RC)) { 742e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson if (Align >= 16 && getRegisterInfo().needsStackRealignment(MF)) { 743e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1q64Pseudo)) 744f967ca0eaf30325cabe3c1971bf0dba16cf1b027Bob Wilson .addFrameIndex(FI).addImm(16) 74569b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng .addReg(SrcReg, getKillRegState(isKill)) 74669b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng .addMemOperand(MMO)); 747e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson } else { 748e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMQIA)) 74969b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng .addReg(SrcReg, getKillRegState(isKill)) 75069b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng .addFrameIndex(FI) 75169b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng .addMemOperand(MMO)); 752e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson } 753e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson } else 754e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson llvm_unreachable("Unknown reg class!"); 755e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson break; 756e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson case 32: 757e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson if (ARM::QQPRRegClass.hasSubClassEq(RC)) { 758e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) { 759e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson // FIXME: It's possible to only store part of the QQ register if the 760e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson // spilled def has a sub-register index. 761e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1d64QPseudo)) 762168f382dc67e5940cabdb28dc933c4f91cdd3137Bob Wilson .addFrameIndex(FI).addImm(16) 763168f382dc67e5940cabdb28dc933c4f91cdd3137Bob Wilson .addReg(SrcReg, getKillRegState(isKill)) 764168f382dc67e5940cabdb28dc933c4f91cdd3137Bob Wilson .addMemOperand(MMO)); 765e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson } else { 766e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson MachineInstrBuilder MIB = 767e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMDIA)) 76873fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling .addFrameIndex(FI)) 769e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson .addMemOperand(MMO); 770e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI); 771e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI); 772e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI); 773e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI); 774e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson } 775e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson } else 776e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson llvm_unreachable("Unknown reg class!"); 777e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson break; 778e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson case 64: 779e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson if (ARM::QQQQPRRegClass.hasSubClassEq(RC)) { 780e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson MachineInstrBuilder MIB = 781e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMDIA)) 782e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson .addFrameIndex(FI)) 783e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson .addMemOperand(MMO); 784e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI); 785e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI); 786e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI); 787e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson MIB = AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI); 788e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson MIB = AddDReg(MIB, SrcReg, ARM::dsub_4, 0, TRI); 789e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson MIB = AddDReg(MIB, SrcReg, ARM::dsub_5, 0, TRI); 790e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson MIB = AddDReg(MIB, SrcReg, ARM::dsub_6, 0, TRI); 791e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson AddDReg(MIB, SrcReg, ARM::dsub_7, 0, TRI); 792e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson } else 793e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson llvm_unreachable("Unknown reg class!"); 794e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson break; 795e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson default: 796e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson llvm_unreachable("Unknown reg class!"); 797334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 798334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 799334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 80034327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesenunsigned 80134327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund OlesenARMBaseInstrInfo::isStoreToStackSlot(const MachineInstr *MI, 80234327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen int &FrameIndex) const { 80334327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen switch (MI->getOpcode()) { 80434327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen default: break; 8057e3383c007f53b3a00675af225e428cb66ddf404Jim Grosbach case ARM::STRrs: 80634327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen case ARM::t2STRs: // FIXME: don't use t2STRs to access frame. 80734327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen if (MI->getOperand(1).isFI() && 80834327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen MI->getOperand(2).isReg() && 80934327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen MI->getOperand(3).isImm() && 81034327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen MI->getOperand(2).getReg() == 0 && 81134327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen MI->getOperand(3).getImm() == 0) { 81234327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen FrameIndex = MI->getOperand(1).getIndex(); 81334327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen return MI->getOperand(0).getReg(); 81434327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen } 81534327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen break; 8167e3383c007f53b3a00675af225e428cb66ddf404Jim Grosbach case ARM::STRi12: 81734327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen case ARM::t2STRi12: 81874472b4bf963c424da04f42dffdb94c85ef964bcJim Grosbach case ARM::tSTRspi: 81934327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen case ARM::VSTRD: 82034327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen case ARM::VSTRS: 82134327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen if (MI->getOperand(1).isFI() && 82234327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen MI->getOperand(2).isImm() && 82334327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen MI->getOperand(2).getImm() == 0) { 82434327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen FrameIndex = MI->getOperand(1).getIndex(); 82534327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen return MI->getOperand(0).getReg(); 82634327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen } 82734327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen break; 828d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen case ARM::VST1q64Pseudo: 829d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen if (MI->getOperand(0).isFI() && 830d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen MI->getOperand(2).getSubReg() == 0) { 831d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen FrameIndex = MI->getOperand(0).getIndex(); 832d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen return MI->getOperand(2).getReg(); 833d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen } 83431bbc51ac9245bc82c933c9db8358ca9bb558ac5Jakob Stoklund Olesen break; 83573fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMQIA: 836d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen if (MI->getOperand(1).isFI() && 837d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen MI->getOperand(0).getSubReg() == 0) { 838d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen FrameIndex = MI->getOperand(1).getIndex(); 839d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen return MI->getOperand(0).getReg(); 840d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen } 841d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen break; 84234327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen } 84334327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen 84434327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen return 0; 84534327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen} 84634327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen 84736ee0e640554b8cc6ad1658fc3049e05d9967160Jakob Stoklund Olesenunsigned ARMBaseInstrInfo::isStoreToStackSlotPostFE(const MachineInstr *MI, 84836ee0e640554b8cc6ad1658fc3049e05d9967160Jakob Stoklund Olesen int &FrameIndex) const { 84936ee0e640554b8cc6ad1658fc3049e05d9967160Jakob Stoklund Olesen const MachineMemOperand *Dummy; 85036ee0e640554b8cc6ad1658fc3049e05d9967160Jakob Stoklund Olesen return MI->getDesc().mayStore() && hasStoreToStackSlot(MI, Dummy, FrameIndex); 85136ee0e640554b8cc6ad1658fc3049e05d9967160Jakob Stoklund Olesen} 85236ee0e640554b8cc6ad1658fc3049e05d9967160Jakob Stoklund Olesen 853334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinvoid ARMBaseInstrInfo:: 854334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinloadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 855334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned DestReg, int FI, 856746ad69e088176819981b4b2c5ac8dcd49f5e60eEvan Cheng const TargetRegisterClass *RC, 857746ad69e088176819981b4b2c5ac8dcd49f5e60eEvan Cheng const TargetRegisterInfo *TRI) const { 858c7f3ace20c325521c68335a1689645b43b06ddf0Chris Lattner DebugLoc DL; 859334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (I != MBB.end()) DL = I->getDebugLoc(); 860249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MachineFunction &MF = *MBB.getParent(); 861249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MachineFrameInfo &MFI = *MF.getFrameInfo(); 86231bc849123011b8eae6bb3c79876d9a3c26a6a1dJim Grosbach unsigned Align = MFI.getObjectAlignment(FI); 863249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MachineMemOperand *MMO = 86459db5496f4fc2ef6111569e542f8b65480ef14c1Chris Lattner MF.getMachineMemOperand( 86559db5496f4fc2ef6111569e542f8b65480ef14c1Chris Lattner MachinePointerInfo(PseudoSourceValue::getFixedStack(FI)), 86659db5496f4fc2ef6111569e542f8b65480ef14c1Chris Lattner MachineMemOperand::MOLoad, 867249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MFI.getObjectSize(FI), 86831bc849123011b8eae6bb3c79876d9a3c26a6a1dJim Grosbach Align); 869334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 870e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson switch (RC->getSize()) { 871e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson case 4: 872e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson if (ARM::GPRRegClass.hasSubClassEq(RC)) { 873e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::LDRi12), DestReg) 8743e5561247202bae994dd259a2d8dc4eff8f799f3Jim Grosbach .addFrameIndex(FI).addImm(0).addMemOperand(MMO)); 875e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson 876e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson } else if (ARM::SPRRegClass.hasSubClassEq(RC)) { 877e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRS), DestReg) 878d31c5496d7e1580058b5c6fbc8fd537a641ea590Evan Cheng .addFrameIndex(FI).addImm(0).addMemOperand(MMO)); 879e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson } else 880e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson llvm_unreachable("Unknown reg class!"); 881ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson break; 882e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson case 8: 883e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson if (ARM::DPRRegClass.hasSubClassEq(RC)) { 884e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRD), DestReg) 885249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov .addFrameIndex(FI).addImm(0).addMemOperand(MMO)); 886e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson } else 887e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson llvm_unreachable("Unknown reg class!"); 888ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson break; 889e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson case 16: 890e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson if (ARM::QPRRegClass.hasSubClassEq(RC)) { 891e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson if (Align >= 16 && getRegisterInfo().needsStackRealignment(MF)) { 892e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1q64Pseudo), DestReg) 893f967ca0eaf30325cabe3c1971bf0dba16cf1b027Bob Wilson .addFrameIndex(FI).addImm(16) 89469b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng .addMemOperand(MMO)); 895e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson } else { 896e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMQIA), DestReg) 897e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson .addFrameIndex(FI) 898e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson .addMemOperand(MMO)); 899e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson } 900e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson } else 901e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson llvm_unreachable("Unknown reg class!"); 902ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson break; 903e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson case 32: 904e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson if (ARM::QQPRRegClass.hasSubClassEq(RC)) { 905e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) { 906e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1d64QPseudo), DestReg) 907168f382dc67e5940cabdb28dc933c4f91cdd3137Bob Wilson .addFrameIndex(FI).addImm(16) 908168f382dc67e5940cabdb28dc933c4f91cdd3137Bob Wilson .addMemOperand(MMO)); 909e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson } else { 910e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson MachineInstrBuilder MIB = 91173fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMDIA)) 91273fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling .addFrameIndex(FI)) 913e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson .addMemOperand(MMO); 914e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::Define, TRI); 915e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::Define, TRI); 916e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::Define, TRI); 917ac3656ed7a67eaacb8d2c62e1841ed4df799f72aJakob Stoklund Olesen MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::Define, TRI); 918ac3656ed7a67eaacb8d2c62e1841ed4df799f72aJakob Stoklund Olesen MIB.addReg(DestReg, RegState::Define | RegState::Implicit); 919e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson } 920e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson } else 921e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson llvm_unreachable("Unknown reg class!"); 922ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson break; 923e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson case 64: 924e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson if (ARM::QQQQPRRegClass.hasSubClassEq(RC)) { 925e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson MachineInstrBuilder MIB = 92673fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMDIA)) 92773fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling .addFrameIndex(FI)) 928e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson .addMemOperand(MMO); 929e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::Define, TRI); 930e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::Define, TRI); 931e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::Define, TRI); 932e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::Define, TRI); 933e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson MIB = AddDReg(MIB, DestReg, ARM::dsub_4, RegState::Define, TRI); 934e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson MIB = AddDReg(MIB, DestReg, ARM::dsub_5, RegState::Define, TRI); 935e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson MIB = AddDReg(MIB, DestReg, ARM::dsub_6, RegState::Define, TRI); 936ac3656ed7a67eaacb8d2c62e1841ed4df799f72aJakob Stoklund Olesen MIB = AddDReg(MIB, DestReg, ARM::dsub_7, RegState::Define, TRI); 937ac3656ed7a67eaacb8d2c62e1841ed4df799f72aJakob Stoklund Olesen MIB.addReg(DestReg, RegState::Define | RegState::Implicit); 938e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson } else 939e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson llvm_unreachable("Unknown reg class!"); 940ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson break; 941ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson default: 942ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson llvm_unreachable("Unknown regclass!"); 943334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 944334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 945334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 94634327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesenunsigned 94734327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund OlesenARMBaseInstrInfo::isLoadFromStackSlot(const MachineInstr *MI, 94834327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen int &FrameIndex) const { 94934327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen switch (MI->getOpcode()) { 95034327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen default: break; 9513e5561247202bae994dd259a2d8dc4eff8f799f3Jim Grosbach case ARM::LDRrs: 95234327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen case ARM::t2LDRs: // FIXME: don't use t2LDRs to access frame. 95334327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen if (MI->getOperand(1).isFI() && 95434327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen MI->getOperand(2).isReg() && 95534327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen MI->getOperand(3).isImm() && 95634327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen MI->getOperand(2).getReg() == 0 && 95734327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen MI->getOperand(3).getImm() == 0) { 95834327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen FrameIndex = MI->getOperand(1).getIndex(); 95934327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen return MI->getOperand(0).getReg(); 96034327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen } 96134327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen break; 9623e5561247202bae994dd259a2d8dc4eff8f799f3Jim Grosbach case ARM::LDRi12: 96334327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen case ARM::t2LDRi12: 96474472b4bf963c424da04f42dffdb94c85ef964bcJim Grosbach case ARM::tLDRspi: 96534327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen case ARM::VLDRD: 96634327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen case ARM::VLDRS: 96734327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen if (MI->getOperand(1).isFI() && 96834327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen MI->getOperand(2).isImm() && 96934327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen MI->getOperand(2).getImm() == 0) { 97034327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen FrameIndex = MI->getOperand(1).getIndex(); 971d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen return MI->getOperand(0).getReg(); 972d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen } 973d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen break; 974d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen case ARM::VLD1q64Pseudo: 975d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen if (MI->getOperand(1).isFI() && 976d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen MI->getOperand(0).getSubReg() == 0) { 977d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen FrameIndex = MI->getOperand(1).getIndex(); 97806f264e504d75f0426eea55b9f9e36c780d8a4fcJakob Stoklund Olesen return MI->getOperand(0).getReg(); 97906f264e504d75f0426eea55b9f9e36c780d8a4fcJakob Stoklund Olesen } 98006f264e504d75f0426eea55b9f9e36c780d8a4fcJakob Stoklund Olesen break; 98173fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMQIA: 98206f264e504d75f0426eea55b9f9e36c780d8a4fcJakob Stoklund Olesen if (MI->getOperand(1).isFI() && 98306f264e504d75f0426eea55b9f9e36c780d8a4fcJakob Stoklund Olesen MI->getOperand(0).getSubReg() == 0) { 98406f264e504d75f0426eea55b9f9e36c780d8a4fcJakob Stoklund Olesen FrameIndex = MI->getOperand(1).getIndex(); 98534327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen return MI->getOperand(0).getReg(); 98634327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen } 98734327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen break; 98834327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen } 98934327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen 99034327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen return 0; 99134327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen} 99234327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen 99336ee0e640554b8cc6ad1658fc3049e05d9967160Jakob Stoklund Olesenunsigned ARMBaseInstrInfo::isLoadFromStackSlotPostFE(const MachineInstr *MI, 99436ee0e640554b8cc6ad1658fc3049e05d9967160Jakob Stoklund Olesen int &FrameIndex) const { 99536ee0e640554b8cc6ad1658fc3049e05d9967160Jakob Stoklund Olesen const MachineMemOperand *Dummy; 99636ee0e640554b8cc6ad1658fc3049e05d9967160Jakob Stoklund Olesen return MI->getDesc().mayLoad() && hasLoadFromStackSlot(MI, Dummy, FrameIndex); 99736ee0e640554b8cc6ad1658fc3049e05d9967160Jakob Stoklund Olesen} 99836ee0e640554b8cc6ad1658fc3049e05d9967160Jakob Stoklund Olesen 999142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesenbool ARMBaseInstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const{ 1000142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen // This hook gets to expand COPY instructions before they become 1001142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen // copyPhysReg() calls. Look for VMOVS instructions that can legally be 1002142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen // widened to VMOVD. We prefer the VMOVD when possible because it may be 1003142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen // changed into a VORR that can go down the NEON pipeline. 1004142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen if (!WidenVMOVS || !MI->isCopy()) 1005142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen return false; 1006142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen 1007142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen // Look for a copy between even S-registers. That is where we keep floats 1008142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen // when using NEON v2f32 instructions for f32 arithmetic. 1009142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen unsigned DstRegS = MI->getOperand(0).getReg(); 1010142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen unsigned SrcRegS = MI->getOperand(1).getReg(); 1011142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen if (!ARM::SPRRegClass.contains(DstRegS, SrcRegS)) 1012142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen return false; 1013142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen 1014142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen const TargetRegisterInfo *TRI = &getRegisterInfo(); 1015142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen unsigned DstRegD = TRI->getMatchingSuperReg(DstRegS, ARM::ssub_0, 1016142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen &ARM::DPRRegClass); 1017142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen unsigned SrcRegD = TRI->getMatchingSuperReg(SrcRegS, ARM::ssub_0, 1018142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen &ARM::DPRRegClass); 1019142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen if (!DstRegD || !SrcRegD) 1020142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen return false; 1021142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen 1022142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen // We want to widen this into a DstRegD = VMOVD SrcRegD copy. This is only 1023142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen // legal if the COPY already defines the full DstRegD, and it isn't a 1024142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen // sub-register insertion. 1025142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen if (!MI->definesRegister(DstRegD, TRI) || MI->readsRegister(DstRegD, TRI)) 1026142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen return false; 1027142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen 10281c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen // A dead copy shouldn't show up here, but reject it just in case. 10291c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen if (MI->getOperand(0).isDead()) 10301c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen return false; 10311c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen 10321c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen // All clear, widen the COPY. 1033142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen DEBUG(dbgs() << "widening: " << *MI); 10341c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen 10351c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen // Get rid of the old <imp-def> of DstRegD. Leave it if it defines a Q-reg 10361c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen // or some other super-register. 10371c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen int ImpDefIdx = MI->findRegisterDefOperandIdx(DstRegD); 10381c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen if (ImpDefIdx != -1) 10391c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen MI->RemoveOperand(ImpDefIdx); 10401c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen 10411c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen // Change the opcode and operands. 1042142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen MI->setDesc(get(ARM::VMOVD)); 1043142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen MI->getOperand(0).setReg(DstRegD); 1044142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen MI->getOperand(1).setReg(SrcRegD); 1045142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen AddDefaultPred(MachineInstrBuilder(MI)); 10461c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen 10471c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen // We are now reading SrcRegD instead of SrcRegS. This may upset the 10481c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen // register scavenger and machine verifier, so we need to indicate that we 10491c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen // are reading an undefined value from SrcRegD, but a proper value from 10501c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen // SrcRegS. 10511c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen MI->getOperand(1).setIsUndef(); 10521c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen MachineInstrBuilder(MI).addReg(SrcRegS, RegState::Implicit); 10531c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen 10541c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen // SrcRegD may actually contain an unrelated value in the ssub_1 10551c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen // sub-register. Don't kill it. Only kill the ssub_0 sub-register. 10561c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen if (MI->getOperand(1).isKill()) { 10571c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen MI->getOperand(1).setIsKill(false); 10581c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen MI->addRegisterKilled(SrcRegS, TRI, true); 10591c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen } 10601c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen 1061142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen DEBUG(dbgs() << "replaced by: " << *MI); 1062142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen return true; 1063142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen} 1064142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen 106562b50656ceb854eb0be265d63b2a1d46e7400d8aEvan ChengMachineInstr* 106662b50656ceb854eb0be265d63b2a1d46e7400d8aEvan ChengARMBaseInstrInfo::emitFrameIndexDebugValue(MachineFunction &MF, 10678601a3d4decff0a380e059b037dabf71075497d3Evan Cheng int FrameIx, uint64_t Offset, 106862b50656ceb854eb0be265d63b2a1d46e7400d8aEvan Cheng const MDNode *MDPtr, 106962b50656ceb854eb0be265d63b2a1d46e7400d8aEvan Cheng DebugLoc DL) const { 107062b50656ceb854eb0be265d63b2a1d46e7400d8aEvan Cheng MachineInstrBuilder MIB = BuildMI(MF, DL, get(ARM::DBG_VALUE)) 107162b50656ceb854eb0be265d63b2a1d46e7400d8aEvan Cheng .addFrameIndex(FrameIx).addImm(0).addImm(Offset).addMetadata(MDPtr); 107262b50656ceb854eb0be265d63b2a1d46e7400d8aEvan Cheng return &*MIB; 107362b50656ceb854eb0be265d63b2a1d46e7400d8aEvan Cheng} 107462b50656ceb854eb0be265d63b2a1d46e7400d8aEvan Cheng 107530ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen/// Create a copy of a const pool value. Update CPI to the new index and return 107630ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen/// the label UID. 107730ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesenstatic unsigned duplicateCPV(MachineFunction &MF, unsigned &CPI) { 107830ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen MachineConstantPool *MCP = MF.getConstantPool(); 107930ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 108030ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen 108130ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPI]; 108230ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen assert(MCPE.isMachineConstantPoolEntry() && 108330ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen "Expecting a machine constantpool entry!"); 108430ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen ARMConstantPoolValue *ACPV = 108530ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal); 108630ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen 10875de5d4b6d0eb3fd379fa571d82f6fa764460b3b8Evan Cheng unsigned PCLabelId = AFI->createPICLabelUId(); 108830ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen ARMConstantPoolValue *NewCPV = 0; 108951f5b67395780b8421f4aa6ee998ed51b23dae9dJim Grosbach // FIXME: The below assumes PIC relocation model and that the function 109051f5b67395780b8421f4aa6ee998ed51b23dae9dJim Grosbach // is Thumb mode (t1 or t2). PCAdjustment would be 8 for ARM mode PIC, and 109151f5b67395780b8421f4aa6ee998ed51b23dae9dJim Grosbach // zero for non-PIC in ARM or Thumb. The callers are all of thumb LDR 109251f5b67395780b8421f4aa6ee998ed51b23dae9dJim Grosbach // instructions, so that's probably OK, but is PIC always correct when 109351f5b67395780b8421f4aa6ee998ed51b23dae9dJim Grosbach // we get here? 109430ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen if (ACPV->isGlobalValue()) 10955bb779976a7d8e48408051ec2289fe69206dc072Bill Wendling NewCPV = ARMConstantPoolConstant:: 10965bb779976a7d8e48408051ec2289fe69206dc072Bill Wendling Create(cast<ARMConstantPoolConstant>(ACPV)->getGV(), PCLabelId, 10975bb779976a7d8e48408051ec2289fe69206dc072Bill Wendling ARMCP::CPValue, 4); 109830ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen else if (ACPV->isExtSymbol()) 1099fe31e673506ef9a1080eaa684b43b34178c6f447Bill Wendling NewCPV = ARMConstantPoolSymbol:: 1100fe31e673506ef9a1080eaa684b43b34178c6f447Bill Wendling Create(MF.getFunction()->getContext(), 1101fe31e673506ef9a1080eaa684b43b34178c6f447Bill Wendling cast<ARMConstantPoolSymbol>(ACPV)->getSymbol(), PCLabelId, 4); 110230ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen else if (ACPV->isBlockAddress()) 11035bb779976a7d8e48408051ec2289fe69206dc072Bill Wendling NewCPV = ARMConstantPoolConstant:: 11045bb779976a7d8e48408051ec2289fe69206dc072Bill Wendling Create(cast<ARMConstantPoolConstant>(ACPV)->getBlockAddress(), PCLabelId, 11055bb779976a7d8e48408051ec2289fe69206dc072Bill Wendling ARMCP::CPBlockAddress, 4); 110651f5b67395780b8421f4aa6ee998ed51b23dae9dJim Grosbach else if (ACPV->isLSDA()) 11075bb779976a7d8e48408051ec2289fe69206dc072Bill Wendling NewCPV = ARMConstantPoolConstant::Create(MF.getFunction(), PCLabelId, 11085bb779976a7d8e48408051ec2289fe69206dc072Bill Wendling ARMCP::CPLSDA, 4); 1109e00897c5a91febe90ba21082fc636be892bf9bf1Bill Wendling else if (ACPV->isMachineBasicBlock()) 11103320f2a3bfd4daec23ba7ceb50525140cc6316daBill Wendling NewCPV = ARMConstantPoolMBB:: 11113320f2a3bfd4daec23ba7ceb50525140cc6316daBill Wendling Create(MF.getFunction()->getContext(), 11123320f2a3bfd4daec23ba7ceb50525140cc6316daBill Wendling cast<ARMConstantPoolMBB>(ACPV)->getMBB(), PCLabelId, 4); 111330ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen else 111430ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen llvm_unreachable("Unexpected ARM constantpool value type!!"); 111530ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen CPI = MCP->getConstantPoolIndex(NewCPV, MCPE.getAlignment()); 111630ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen return PCLabelId; 111730ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen} 111830ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen 1119fdc834046efd427d474e3b899ec69354c05071e0Evan Chengvoid ARMBaseInstrInfo:: 1120fdc834046efd427d474e3b899ec69354c05071e0Evan ChengreMaterialize(MachineBasicBlock &MBB, 1121fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng MachineBasicBlock::iterator I, 1122fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng unsigned DestReg, unsigned SubIdx, 1123d57cdd5683ea926e489067364fb7ffe5fd5d35eeEvan Cheng const MachineInstr *Orig, 11249edf7deb37f0f97664f279040fa15d89f32e23d9Jakob Stoklund Olesen const TargetRegisterInfo &TRI) const { 1125fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng unsigned Opcode = Orig->getOpcode(); 1126fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng switch (Opcode) { 1127fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng default: { 1128fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig); 11299edf7deb37f0f97664f279040fa15d89f32e23d9Jakob Stoklund Olesen MI->substituteRegister(Orig->getOperand(0).getReg(), DestReg, SubIdx, TRI); 1130fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng MBB.insert(I, MI); 1131fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng break; 1132fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng } 1133fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng case ARM::tLDRpci_pic: 1134fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng case ARM::t2LDRpci_pic: { 1135fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng MachineFunction &MF = *MBB.getParent(); 1136fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng unsigned CPI = Orig->getOperand(1).getIndex(); 113730ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen unsigned PCLabelId = duplicateCPV(MF, CPI); 1138fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng MachineInstrBuilder MIB = BuildMI(MBB, I, Orig->getDebugLoc(), get(Opcode), 1139fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng DestReg) 1140fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng .addConstantPoolIndex(CPI).addImm(PCLabelId); 1141d7d030a44796adc73a6eaa939cd17e52047734c1Chris Lattner MIB->setMemRefs(Orig->memoperands_begin(), Orig->memoperands_end()); 1142fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng break; 1143fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng } 1144fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng } 1145fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng} 1146fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng 114730ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund OlesenMachineInstr * 114830ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund OlesenARMBaseInstrInfo::duplicate(MachineInstr *Orig, MachineFunction &MF) const { 114930ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen MachineInstr *MI = TargetInstrInfoImpl::duplicate(Orig, MF); 115030ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen switch(Orig->getOpcode()) { 115130ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen case ARM::tLDRpci_pic: 115230ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen case ARM::t2LDRpci_pic: { 115330ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen unsigned CPI = Orig->getOperand(1).getIndex(); 115430ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen unsigned PCLabelId = duplicateCPV(MF, CPI); 115530ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen Orig->getOperand(1).setIndex(CPI); 115630ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen Orig->getOperand(2).setImm(PCLabelId); 115730ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen break; 115830ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen } 115930ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen } 116030ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen return MI; 116130ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen} 116230ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen 1163506049f29f4f202a8e45feb916cc0264440a7f6dEvan Chengbool ARMBaseInstrInfo::produceSameValue(const MachineInstr *MI0, 11649fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng const MachineInstr *MI1, 11659fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng const MachineRegisterInfo *MRI) const { 1166d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng int Opcode = MI0->getOpcode(); 1167d7e3cc840b81b0438e47f05d9664137a198876dfEvan Cheng if (Opcode == ARM::t2LDRpci || 11689b82425cb0105fd5704f6b9bcd5e7693b05b1759Evan Cheng Opcode == ARM::t2LDRpci_pic || 11699b82425cb0105fd5704f6b9bcd5e7693b05b1759Evan Cheng Opcode == ARM::tLDRpci || 11709fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng Opcode == ARM::tLDRpci_pic || 117153519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng Opcode == ARM::MOV_ga_dyn || 117253519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng Opcode == ARM::MOV_ga_pcrel || 117353519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng Opcode == ARM::MOV_ga_pcrel_ldr || 117453519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng Opcode == ARM::t2MOV_ga_dyn || 117553519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng Opcode == ARM::t2MOV_ga_pcrel) { 1176d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng if (MI1->getOpcode() != Opcode) 1177d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng return false; 1178d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng if (MI0->getNumOperands() != MI1->getNumOperands()) 1179d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng return false; 1180d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng 1181d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng const MachineOperand &MO0 = MI0->getOperand(1); 1182d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng const MachineOperand &MO1 = MI1->getOperand(1); 1183d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng if (MO0.getOffset() != MO1.getOffset()) 1184d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng return false; 1185d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng 118653519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng if (Opcode == ARM::MOV_ga_dyn || 118753519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng Opcode == ARM::MOV_ga_pcrel || 118853519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng Opcode == ARM::MOV_ga_pcrel_ldr || 118953519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng Opcode == ARM::t2MOV_ga_dyn || 119053519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng Opcode == ARM::t2MOV_ga_pcrel) 11919fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng // Ignore the PC labels. 11929fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng return MO0.getGlobal() == MO1.getGlobal(); 11939fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng 1194d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng const MachineFunction *MF = MI0->getParent()->getParent(); 1195d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng const MachineConstantPool *MCP = MF->getConstantPool(); 1196d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng int CPI0 = MO0.getIndex(); 1197d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng int CPI1 = MO1.getIndex(); 1198d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng const MachineConstantPoolEntry &MCPE0 = MCP->getConstants()[CPI0]; 1199d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng const MachineConstantPoolEntry &MCPE1 = MCP->getConstants()[CPI1]; 1200d700617193f3d11deb83cd56c4ababbc8e0ea19fEvan Cheng bool isARMCP0 = MCPE0.isMachineConstantPoolEntry(); 1201d700617193f3d11deb83cd56c4ababbc8e0ea19fEvan Cheng bool isARMCP1 = MCPE1.isMachineConstantPoolEntry(); 1202d700617193f3d11deb83cd56c4ababbc8e0ea19fEvan Cheng if (isARMCP0 && isARMCP1) { 1203d700617193f3d11deb83cd56c4ababbc8e0ea19fEvan Cheng ARMConstantPoolValue *ACPV0 = 1204d700617193f3d11deb83cd56c4ababbc8e0ea19fEvan Cheng static_cast<ARMConstantPoolValue*>(MCPE0.Val.MachineCPVal); 1205d700617193f3d11deb83cd56c4ababbc8e0ea19fEvan Cheng ARMConstantPoolValue *ACPV1 = 1206d700617193f3d11deb83cd56c4ababbc8e0ea19fEvan Cheng static_cast<ARMConstantPoolValue*>(MCPE1.Val.MachineCPVal); 1207d700617193f3d11deb83cd56c4ababbc8e0ea19fEvan Cheng return ACPV0->hasSameValue(ACPV1); 1208d700617193f3d11deb83cd56c4ababbc8e0ea19fEvan Cheng } else if (!isARMCP0 && !isARMCP1) { 1209d700617193f3d11deb83cd56c4ababbc8e0ea19fEvan Cheng return MCPE0.Val.ConstVal == MCPE1.Val.ConstVal; 1210d700617193f3d11deb83cd56c4ababbc8e0ea19fEvan Cheng } 1211d700617193f3d11deb83cd56c4ababbc8e0ea19fEvan Cheng return false; 12129fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng } else if (Opcode == ARM::PICLDR) { 12139fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng if (MI1->getOpcode() != Opcode) 12149fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng return false; 12159fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng if (MI0->getNumOperands() != MI1->getNumOperands()) 12169fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng return false; 12179fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng 12189fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng unsigned Addr0 = MI0->getOperand(1).getReg(); 12199fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng unsigned Addr1 = MI1->getOperand(1).getReg(); 12209fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng if (Addr0 != Addr1) { 12219fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng if (!MRI || 12229fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng !TargetRegisterInfo::isVirtualRegister(Addr0) || 12239fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng !TargetRegisterInfo::isVirtualRegister(Addr1)) 12249fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng return false; 12259fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng 12269fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng // This assumes SSA form. 12279fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng MachineInstr *Def0 = MRI->getVRegDef(Addr0); 12289fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng MachineInstr *Def1 = MRI->getVRegDef(Addr1); 12299fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng // Check if the loaded value, e.g. a constantpool of a global address, are 12309fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng // the same. 12319fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng if (!produceSameValue(Def0, Def1, MRI)) 12329fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng return false; 12339fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng } 12349fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng 12359fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng for (unsigned i = 3, e = MI0->getNumOperands(); i != e; ++i) { 12369fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng // %vreg12<def> = PICLDR %vreg11, 0, pred:14, pred:%noreg 12379fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng const MachineOperand &MO0 = MI0->getOperand(i); 12389fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng const MachineOperand &MO1 = MI1->getOperand(i); 12399fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng if (!MO0.isIdenticalTo(MO1)) 12409fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng return false; 12419fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng } 12429fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng return true; 1243d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng } 1244d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng 1245506049f29f4f202a8e45feb916cc0264440a7f6dEvan Cheng return MI0->isIdenticalTo(MI1, MachineInstr::IgnoreVRegDefs); 1246d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng} 1247d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng 12484b722108e2cf8e77157e0879a23789cd44829933Bill Wendling/// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to 12494b722108e2cf8e77157e0879a23789cd44829933Bill Wendling/// determine if two loads are loading from the same base address. It should 12504b722108e2cf8e77157e0879a23789cd44829933Bill Wendling/// only return true if the base pointers are the same and the only differences 12514b722108e2cf8e77157e0879a23789cd44829933Bill Wendling/// between the two addresses is the offset. It also returns the offsets by 12524b722108e2cf8e77157e0879a23789cd44829933Bill Wendling/// reference. 12534b722108e2cf8e77157e0879a23789cd44829933Bill Wendlingbool ARMBaseInstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, 12544b722108e2cf8e77157e0879a23789cd44829933Bill Wendling int64_t &Offset1, 12554b722108e2cf8e77157e0879a23789cd44829933Bill Wendling int64_t &Offset2) const { 12564b722108e2cf8e77157e0879a23789cd44829933Bill Wendling // Don't worry about Thumb: just ARM and Thumb2. 12574b722108e2cf8e77157e0879a23789cd44829933Bill Wendling if (Subtarget.isThumb1Only()) return false; 12584b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 12594b722108e2cf8e77157e0879a23789cd44829933Bill Wendling if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode()) 12604b722108e2cf8e77157e0879a23789cd44829933Bill Wendling return false; 12614b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 12624b722108e2cf8e77157e0879a23789cd44829933Bill Wendling switch (Load1->getMachineOpcode()) { 12634b722108e2cf8e77157e0879a23789cd44829933Bill Wendling default: 12644b722108e2cf8e77157e0879a23789cd44829933Bill Wendling return false; 12653e5561247202bae994dd259a2d8dc4eff8f799f3Jim Grosbach case ARM::LDRi12: 1266c1d30212e911d1e55ff6b25bffefb503708883c3Jim Grosbach case ARM::LDRBi12: 12674b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::LDRD: 12684b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::LDRH: 12694b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::LDRSB: 12704b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::LDRSH: 12714b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::VLDRD: 12724b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::VLDRS: 12734b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::t2LDRi8: 12744b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::t2LDRDi8: 12754b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::t2LDRSHi8: 12764b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::t2LDRi12: 12774b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::t2LDRSHi12: 12784b722108e2cf8e77157e0879a23789cd44829933Bill Wendling break; 12794b722108e2cf8e77157e0879a23789cd44829933Bill Wendling } 12804b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 12814b722108e2cf8e77157e0879a23789cd44829933Bill Wendling switch (Load2->getMachineOpcode()) { 12824b722108e2cf8e77157e0879a23789cd44829933Bill Wendling default: 12834b722108e2cf8e77157e0879a23789cd44829933Bill Wendling return false; 12843e5561247202bae994dd259a2d8dc4eff8f799f3Jim Grosbach case ARM::LDRi12: 1285c1d30212e911d1e55ff6b25bffefb503708883c3Jim Grosbach case ARM::LDRBi12: 12864b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::LDRD: 12874b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::LDRH: 12884b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::LDRSB: 12894b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::LDRSH: 12904b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::VLDRD: 12914b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::VLDRS: 12924b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::t2LDRi8: 12934b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::t2LDRDi8: 12944b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::t2LDRSHi8: 12954b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::t2LDRi12: 12964b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::t2LDRSHi12: 12974b722108e2cf8e77157e0879a23789cd44829933Bill Wendling break; 12984b722108e2cf8e77157e0879a23789cd44829933Bill Wendling } 12994b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 13004b722108e2cf8e77157e0879a23789cd44829933Bill Wendling // Check if base addresses and chain operands match. 13014b722108e2cf8e77157e0879a23789cd44829933Bill Wendling if (Load1->getOperand(0) != Load2->getOperand(0) || 13024b722108e2cf8e77157e0879a23789cd44829933Bill Wendling Load1->getOperand(4) != Load2->getOperand(4)) 13034b722108e2cf8e77157e0879a23789cd44829933Bill Wendling return false; 13044b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 13054b722108e2cf8e77157e0879a23789cd44829933Bill Wendling // Index should be Reg0. 13064b722108e2cf8e77157e0879a23789cd44829933Bill Wendling if (Load1->getOperand(3) != Load2->getOperand(3)) 13074b722108e2cf8e77157e0879a23789cd44829933Bill Wendling return false; 13084b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 13094b722108e2cf8e77157e0879a23789cd44829933Bill Wendling // Determine the offsets. 13104b722108e2cf8e77157e0879a23789cd44829933Bill Wendling if (isa<ConstantSDNode>(Load1->getOperand(1)) && 13114b722108e2cf8e77157e0879a23789cd44829933Bill Wendling isa<ConstantSDNode>(Load2->getOperand(1))) { 13124b722108e2cf8e77157e0879a23789cd44829933Bill Wendling Offset1 = cast<ConstantSDNode>(Load1->getOperand(1))->getSExtValue(); 13134b722108e2cf8e77157e0879a23789cd44829933Bill Wendling Offset2 = cast<ConstantSDNode>(Load2->getOperand(1))->getSExtValue(); 13144b722108e2cf8e77157e0879a23789cd44829933Bill Wendling return true; 13154b722108e2cf8e77157e0879a23789cd44829933Bill Wendling } 13164b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 13174b722108e2cf8e77157e0879a23789cd44829933Bill Wendling return false; 13184b722108e2cf8e77157e0879a23789cd44829933Bill Wendling} 13194b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 13204b722108e2cf8e77157e0879a23789cd44829933Bill Wendling/// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to 13217a2bdde0a0eebcd2125055e0eacaca040f0b766cChris Lattner/// determine (in conjunction with areLoadsFromSameBasePtr) if two loads should 13224b722108e2cf8e77157e0879a23789cd44829933Bill Wendling/// be scheduled togther. On some targets if two loads are loading from 13234b722108e2cf8e77157e0879a23789cd44829933Bill Wendling/// addresses in the same cache line, it's better if they are scheduled 13244b722108e2cf8e77157e0879a23789cd44829933Bill Wendling/// together. This function takes two integers that represent the load offsets 13254b722108e2cf8e77157e0879a23789cd44829933Bill Wendling/// from the common base address. It returns true if it decides it's desirable 13264b722108e2cf8e77157e0879a23789cd44829933Bill Wendling/// to schedule the two loads together. "NumLoads" is the number of loads that 13274b722108e2cf8e77157e0879a23789cd44829933Bill Wendling/// have already been scheduled after Load1. 13284b722108e2cf8e77157e0879a23789cd44829933Bill Wendlingbool ARMBaseInstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, 13294b722108e2cf8e77157e0879a23789cd44829933Bill Wendling int64_t Offset1, int64_t Offset2, 13304b722108e2cf8e77157e0879a23789cd44829933Bill Wendling unsigned NumLoads) const { 13314b722108e2cf8e77157e0879a23789cd44829933Bill Wendling // Don't worry about Thumb: just ARM and Thumb2. 13324b722108e2cf8e77157e0879a23789cd44829933Bill Wendling if (Subtarget.isThumb1Only()) return false; 13334b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 13344b722108e2cf8e77157e0879a23789cd44829933Bill Wendling assert(Offset2 > Offset1); 13354b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 13364b722108e2cf8e77157e0879a23789cd44829933Bill Wendling if ((Offset2 - Offset1) / 8 > 64) 13374b722108e2cf8e77157e0879a23789cd44829933Bill Wendling return false; 13384b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 13394b722108e2cf8e77157e0879a23789cd44829933Bill Wendling if (Load1->getMachineOpcode() != Load2->getMachineOpcode()) 13404b722108e2cf8e77157e0879a23789cd44829933Bill Wendling return false; // FIXME: overly conservative? 13414b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 13424b722108e2cf8e77157e0879a23789cd44829933Bill Wendling // Four loads in a row should be sufficient. 13434b722108e2cf8e77157e0879a23789cd44829933Bill Wendling if (NumLoads >= 3) 13444b722108e2cf8e77157e0879a23789cd44829933Bill Wendling return false; 13454b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 13464b722108e2cf8e77157e0879a23789cd44829933Bill Wendling return true; 13474b722108e2cf8e77157e0879a23789cd44829933Bill Wendling} 13484b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 134986050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Chengbool ARMBaseInstrInfo::isSchedulingBoundary(const MachineInstr *MI, 135086050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng const MachineBasicBlock *MBB, 135186050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng const MachineFunction &MF) const { 135257bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach // Debug info is never a scheduling boundary. It's necessary to be explicit 135357bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach // due to the special treatment of IT instructions below, otherwise a 135457bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach // dbg_value followed by an IT will result in the IT instruction being 135557bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach // considered a scheduling hazard, which is wrong. It should be the actual 135657bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach // instruction preceding the dbg_value instruction(s), just like it is 135757bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach // when debug info is not present. 135857bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach if (MI->isDebugValue()) 135957bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach return false; 136057bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach 136186050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // Terminators and labels can't be scheduled around. 136286050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng if (MI->getDesc().isTerminator() || MI->isLabel()) 136386050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng return true; 136486050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng 136586050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // Treat the start of the IT block as a scheduling boundary, but schedule 136686050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // t2IT along with all instructions following it. 136786050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // FIXME: This is a big hammer. But the alternative is to add all potential 136886050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // true and anti dependencies to IT block instructions as implicit operands 136986050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // to the t2IT instruction. The added compile time and complexity does not 137086050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // seem worth it. 137186050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng MachineBasicBlock::const_iterator I = MI; 137257bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach // Make sure to skip any dbg_value instructions 137357bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach while (++I != MBB->end() && I->isDebugValue()) 137457bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach ; 137557bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach if (I != MBB->end() && I->getOpcode() == ARM::t2IT) 137686050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng return true; 137786050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng 137886050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // Don't attempt to schedule around any instruction that defines 137986050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // a stack-oriented pointer, as it's unlikely to be profitable. This 138086050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // saves compile time, because it doesn't require every single 138186050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // stack slot reference to depend on the instruction that does the 138286050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // modification. 138386050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng if (MI->definesRegister(ARM::SP)) 138486050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng return true; 138586050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng 138686050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng return false; 138786050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng} 138886050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng 1389f81b7f6069b27c0a515070dcb392f6828437412fJakub Staszakbool ARMBaseInstrInfo:: 1390f81b7f6069b27c0a515070dcb392f6828437412fJakub StaszakisProfitableToIfCvt(MachineBasicBlock &MBB, 1391f81b7f6069b27c0a515070dcb392f6828437412fJakub Staszak unsigned NumCycles, unsigned ExtraPredCycles, 1392f81b7f6069b27c0a515070dcb392f6828437412fJakub Staszak const BranchProbability &Probability) const { 13935876db7a66fcc4ec4444a9f3e387c1cdc8baf9e5Cameron Zwarich if (!NumCycles) 139413151432edace19ee867a93b5c14573df4f75d24Evan Cheng return false; 13952bbb76909126db5bed6bde84b16d94ab5de4d372Michael J. Spencer 1396b20b85168c0e9819e6545f08281e9b83c82108f0Owen Anderson // Attempt to estimate the relative costs of predication versus branching. 1397f81b7f6069b27c0a515070dcb392f6828437412fJakub Staszak unsigned UnpredCost = Probability.getNumerator() * NumCycles; 1398f81b7f6069b27c0a515070dcb392f6828437412fJakub Staszak UnpredCost /= Probability.getDenominator(); 1399f81b7f6069b27c0a515070dcb392f6828437412fJakub Staszak UnpredCost += 1; // The branch itself 1400f81b7f6069b27c0a515070dcb392f6828437412fJakub Staszak UnpredCost += Subtarget.getMispredictionPenalty() / 10; 14012bbb76909126db5bed6bde84b16d94ab5de4d372Michael J. Spencer 1402f81b7f6069b27c0a515070dcb392f6828437412fJakub Staszak return (NumCycles + ExtraPredCycles) <= UnpredCost; 140313151432edace19ee867a93b5c14573df4f75d24Evan Cheng} 14042bbb76909126db5bed6bde84b16d94ab5de4d372Michael J. Spencer 140513151432edace19ee867a93b5c14573df4f75d24Evan Chengbool ARMBaseInstrInfo:: 14068239daf7c83a65a189c352cce3191cdc3bbfe151Evan ChengisProfitableToIfCvt(MachineBasicBlock &TMBB, 14078239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng unsigned TCycles, unsigned TExtra, 14088239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng MachineBasicBlock &FMBB, 14098239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng unsigned FCycles, unsigned FExtra, 1410f81b7f6069b27c0a515070dcb392f6828437412fJakub Staszak const BranchProbability &Probability) const { 14118239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng if (!TCycles || !FCycles) 1412b20b85168c0e9819e6545f08281e9b83c82108f0Owen Anderson return false; 14132bbb76909126db5bed6bde84b16d94ab5de4d372Michael J. Spencer 1414b20b85168c0e9819e6545f08281e9b83c82108f0Owen Anderson // Attempt to estimate the relative costs of predication versus branching. 1415f81b7f6069b27c0a515070dcb392f6828437412fJakub Staszak unsigned TUnpredCost = Probability.getNumerator() * TCycles; 1416f81b7f6069b27c0a515070dcb392f6828437412fJakub Staszak TUnpredCost /= Probability.getDenominator(); 1417e23dc9c0ef50b0a1934c04c1786f3a0478d62f41Andrew Trick 1418f81b7f6069b27c0a515070dcb392f6828437412fJakub Staszak uint32_t Comp = Probability.getDenominator() - Probability.getNumerator(); 1419f81b7f6069b27c0a515070dcb392f6828437412fJakub Staszak unsigned FUnpredCost = Comp * FCycles; 1420f81b7f6069b27c0a515070dcb392f6828437412fJakub Staszak FUnpredCost /= Probability.getDenominator(); 1421f81b7f6069b27c0a515070dcb392f6828437412fJakub Staszak 1422f81b7f6069b27c0a515070dcb392f6828437412fJakub Staszak unsigned UnpredCost = TUnpredCost + FUnpredCost; 1423f81b7f6069b27c0a515070dcb392f6828437412fJakub Staszak UnpredCost += 1; // The branch itself 1424f81b7f6069b27c0a515070dcb392f6828437412fJakub Staszak UnpredCost += Subtarget.getMispredictionPenalty() / 10; 1425f81b7f6069b27c0a515070dcb392f6828437412fJakub Staszak 1426f81b7f6069b27c0a515070dcb392f6828437412fJakub Staszak return (TCycles + FCycles + TExtra + FExtra) <= UnpredCost; 142713151432edace19ee867a93b5c14573df4f75d24Evan Cheng} 142813151432edace19ee867a93b5c14573df4f75d24Evan Cheng 14298fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng/// getInstrPredicate - If instruction is predicated, returns its predicate 14308fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng/// condition, otherwise returns AL. It also returns the condition code 14318fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng/// register by reference. 14325adb66a646e2ec32265263739f5b01c3f50c176aEvan ChengARMCC::CondCodes 14335adb66a646e2ec32265263739f5b01c3f50c176aEvan Chengllvm::getInstrPredicate(const MachineInstr *MI, unsigned &PredReg) { 14348fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng int PIdx = MI->findFirstPredOperandIdx(); 14358fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng if (PIdx == -1) { 14368fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng PredReg = 0; 14378fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng return ARMCC::AL; 14388fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng } 14398fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng 14408fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng PredReg = MI->getOperand(PIdx+1).getReg(); 14418fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng return (ARMCC::CondCodes)MI->getOperand(PIdx).getImm(); 14428fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng} 14438fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng 14448fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng 14456495f63945e8dbde81f03a1dc2ab421993b9a495Evan Chengint llvm::getMatchingCondBranchOpcode(int Opc) { 14465ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng if (Opc == ARM::B) 14475ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng return ARM::Bcc; 14485ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng else if (Opc == ARM::tB) 14495ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng return ARM::tBcc; 14505ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng else if (Opc == ARM::t2B) 14515ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng return ARM::t2Bcc; 14525ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng 14535ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng llvm_unreachable("Unknown unconditional branch opcode!"); 14545ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng return 0; 14555ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng} 14565ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng 14576495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 14583be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick/// Map pseudo instructions that imply an 'S' bit onto real opcodes. Whether the 14593be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick/// instruction is encoded with an 'S' bit is determined by the optional CPSR 14603be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick/// def operand. 14613be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick/// 14623be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick/// This will go away once we can teach tblgen how to set the optional CPSR def 14633be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick/// operand itself. 14643be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trickstruct AddSubFlagsOpcodePair { 14653be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick unsigned PseudoOpc; 14663be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick unsigned MachineOpc; 14673be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick}; 14683be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick 14693be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trickstatic AddSubFlagsOpcodePair AddSubFlagsOpcodeMap[] = { 14703be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick {ARM::ADDSri, ARM::ADDri}, 14713be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick {ARM::ADDSrr, ARM::ADDrr}, 14723be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick {ARM::ADDSrsi, ARM::ADDrsi}, 14733be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick {ARM::ADDSrsr, ARM::ADDrsr}, 14743be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick 14753be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick {ARM::SUBSri, ARM::SUBri}, 14763be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick {ARM::SUBSrr, ARM::SUBrr}, 14773be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick {ARM::SUBSrsi, ARM::SUBrsi}, 14783be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick {ARM::SUBSrsr, ARM::SUBrsr}, 14793be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick 14803be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick {ARM::RSBSri, ARM::RSBri}, 14813be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick {ARM::RSBSrr, ARM::RSBrr}, 14823be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick {ARM::RSBSrsi, ARM::RSBrsi}, 14833be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick {ARM::RSBSrsr, ARM::RSBrsr}, 14843be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick 14853be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick {ARM::t2ADDSri, ARM::t2ADDri}, 14863be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick {ARM::t2ADDSrr, ARM::t2ADDrr}, 14873be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick {ARM::t2ADDSrs, ARM::t2ADDrs}, 14883be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick 14893be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick {ARM::t2SUBSri, ARM::t2SUBri}, 14903be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick {ARM::t2SUBSrr, ARM::t2SUBrr}, 14913be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick {ARM::t2SUBSrs, ARM::t2SUBrs}, 14923be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick 14933be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick {ARM::t2RSBSri, ARM::t2RSBri}, 14943be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick {ARM::t2RSBSrs, ARM::t2RSBrs}, 14953be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick}; 14963be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick 14973be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trickunsigned llvm::convertAddSubFlagsOpcode(unsigned OldOpc) { 14983be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick static const int NPairs = 14993be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick sizeof(AddSubFlagsOpcodeMap) / sizeof(AddSubFlagsOpcodePair); 15003be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick for (AddSubFlagsOpcodePair *OpcPair = &AddSubFlagsOpcodeMap[0], 15013be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick *End = &AddSubFlagsOpcodeMap[NPairs]; OpcPair != End; ++OpcPair) { 15023be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick if (OldOpc == OpcPair->PseudoOpc) { 15033be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick return OpcPair->MachineOpc; 15043be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick } 15053be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick } 15063be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick return 0; 15073be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick} 15083be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick 15096495f63945e8dbde81f03a1dc2ab421993b9a495Evan Chengvoid llvm::emitARMRegPlusImmediate(MachineBasicBlock &MBB, 15106495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MachineBasicBlock::iterator &MBBI, DebugLoc dl, 15116495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned DestReg, unsigned BaseReg, int NumBytes, 15126495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ARMCC::CondCodes Pred, unsigned PredReg, 151357caad7a33ff145b71545f10dcfbbf2fd0f595d3Anton Korobeynikov const ARMBaseInstrInfo &TII, unsigned MIFlags) { 15146495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng bool isSub = NumBytes < 0; 15156495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (isSub) NumBytes = -NumBytes; 15166495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 15176495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng while (NumBytes) { 15186495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned RotAmt = ARM_AM::getSOImmValRotate(NumBytes); 15196495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned ThisVal = NumBytes & ARM_AM::rotr32(0xFF, RotAmt); 15206495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng assert(ThisVal && "Didn't extract field correctly"); 15216495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 15226495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // We will handle these bits from offset, clear them. 15236495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng NumBytes &= ~ThisVal; 15246495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 15256495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng assert(ARM_AM::getSOImmVal(ThisVal) != -1 && "Bit extraction didn't work?"); 15266495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 15276495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Build the new ADD / SUB. 15286495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned Opc = isSub ? ARM::SUBri : ARM::ADDri; 15296495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg) 15306495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng .addReg(BaseReg, RegState::Kill).addImm(ThisVal) 153157caad7a33ff145b71545f10dcfbbf2fd0f595d3Anton Korobeynikov .addImm((unsigned)Pred).addReg(PredReg).addReg(0) 153257caad7a33ff145b71545f10dcfbbf2fd0f595d3Anton Korobeynikov .setMIFlags(MIFlags); 15336495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng BaseReg = DestReg; 15346495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 15356495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng} 15366495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 1537cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Chengbool llvm::rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx, 1538cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng unsigned FrameReg, int &Offset, 1539cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng const ARMBaseInstrInfo &TII) { 15406495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned Opcode = MI.getOpcode(); 1541e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng const MCInstrDesc &Desc = MI.getDesc(); 15426495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask); 15436495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng bool isSub = false; 1544764ab52dd80310a205c9888bf166d09dab858f90Jim Grosbach 15456495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Memory operands in inline assembly always use AddrMode2. 15466495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (Opcode == ARM::INLINEASM) 15476495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng AddrMode = ARMII::AddrMode2; 1548764ab52dd80310a205c9888bf166d09dab858f90Jim Grosbach 15496495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (Opcode == ARM::ADDri) { 15506495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng Offset += MI.getOperand(FrameRegIdx+1).getImm(); 15516495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (Offset == 0) { 15526495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Turn it into a move. 15536495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MI.setDesc(TII.get(ARM::MOVr)); 15546495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false); 15556495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MI.RemoveOperand(FrameRegIdx+1); 1556cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng Offset = 0; 1557cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng return true; 15586495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } else if (Offset < 0) { 15596495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng Offset = -Offset; 15606495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng isSub = true; 15616495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MI.setDesc(TII.get(ARM::SUBri)); 15626495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 15636495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 15646495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Common case: small offset, fits into instruction. 15656495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (ARM_AM::getSOImmVal(Offset) != -1) { 15666495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Replace the FrameIndex with sp / fp 15676495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false); 15686495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset); 1569cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng Offset = 0; 1570cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng return true; 15716495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 15726495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 15736495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Otherwise, pull as much of the immedidate into this ADDri/SUBri 15746495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // as possible. 15756495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned RotAmt = ARM_AM::getSOImmValRotate(Offset); 15766495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xFF, RotAmt); 15776495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 15786495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // We will handle these bits from offset, clear them. 15796495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng Offset &= ~ThisImmVal; 15806495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 15816495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Get the properly encoded SOImmVal field. 15826495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng assert(ARM_AM::getSOImmVal(ThisImmVal) != -1 && 15836495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng "Bit extraction didn't work?"); 15846495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MI.getOperand(FrameRegIdx+1).ChangeToImmediate(ThisImmVal); 15856495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } else { 15866495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned ImmIdx = 0; 15876495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng int InstrOffs = 0; 15886495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned NumBits = 0; 15896495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned Scale = 1; 15906495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng switch (AddrMode) { 15913e5561247202bae994dd259a2d8dc4eff8f799f3Jim Grosbach case ARMII::AddrMode_i12: { 15923e5561247202bae994dd259a2d8dc4eff8f799f3Jim Grosbach ImmIdx = FrameRegIdx + 1; 15933e5561247202bae994dd259a2d8dc4eff8f799f3Jim Grosbach InstrOffs = MI.getOperand(ImmIdx).getImm(); 15943e5561247202bae994dd259a2d8dc4eff8f799f3Jim Grosbach NumBits = 12; 15953e5561247202bae994dd259a2d8dc4eff8f799f3Jim Grosbach break; 15963e5561247202bae994dd259a2d8dc4eff8f799f3Jim Grosbach } 15976495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng case ARMII::AddrMode2: { 15986495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ImmIdx = FrameRegIdx+2; 15996495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng InstrOffs = ARM_AM::getAM2Offset(MI.getOperand(ImmIdx).getImm()); 16006495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (ARM_AM::getAM2Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub) 16016495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng InstrOffs *= -1; 16026495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng NumBits = 12; 16036495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng break; 16046495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 16056495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng case ARMII::AddrMode3: { 16066495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ImmIdx = FrameRegIdx+2; 16076495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng InstrOffs = ARM_AM::getAM3Offset(MI.getOperand(ImmIdx).getImm()); 16086495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (ARM_AM::getAM3Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub) 16096495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng InstrOffs *= -1; 16106495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng NumBits = 8; 16116495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng break; 16126495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 1613baf31088f1472f48ea5ae81f0b93636cc44ca444Anton Korobeynikov case ARMII::AddrMode4: 1614a44321776ecd96fa0344335d3027758be3386e45Jim Grosbach case ARMII::AddrMode6: 1615cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng // Can't fold any offset even if it's zero. 1616cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng return false; 16176495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng case ARMII::AddrMode5: { 16186495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ImmIdx = FrameRegIdx+1; 16196495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng InstrOffs = ARM_AM::getAM5Offset(MI.getOperand(ImmIdx).getImm()); 16206495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (ARM_AM::getAM5Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub) 16216495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng InstrOffs *= -1; 16226495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng NumBits = 8; 16236495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng Scale = 4; 16246495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng break; 16256495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 16266495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng default: 16276495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng llvm_unreachable("Unsupported addressing mode!"); 16286495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng break; 16296495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 16306495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 16316495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng Offset += InstrOffs * Scale; 16326495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!"); 16336495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (Offset < 0) { 16346495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng Offset = -Offset; 16356495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng isSub = true; 16366495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 16376495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 16386495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Attempt to fold address comp. if opcode has offset bits 16396495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (NumBits > 0) { 16406495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Common case: small offset, fits into instruction. 16416495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MachineOperand &ImmOp = MI.getOperand(ImmIdx); 16426495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng int ImmedOffset = Offset / Scale; 16436495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned Mask = (1 << NumBits) - 1; 16446495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if ((unsigned)Offset <= Mask * Scale) { 16456495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Replace the FrameIndex with sp 16466495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false); 164777aee8e22c36257716c2df2f275724765704f20cJim Grosbach // FIXME: When addrmode2 goes away, this will simplify (like the 164877aee8e22c36257716c2df2f275724765704f20cJim Grosbach // T2 version), as the LDR.i12 versions don't need the encoding 164977aee8e22c36257716c2df2f275724765704f20cJim Grosbach // tricks for the offset value. 165077aee8e22c36257716c2df2f275724765704f20cJim Grosbach if (isSub) { 165177aee8e22c36257716c2df2f275724765704f20cJim Grosbach if (AddrMode == ARMII::AddrMode_i12) 165277aee8e22c36257716c2df2f275724765704f20cJim Grosbach ImmedOffset = -ImmedOffset; 165377aee8e22c36257716c2df2f275724765704f20cJim Grosbach else 165477aee8e22c36257716c2df2f275724765704f20cJim Grosbach ImmedOffset |= 1 << NumBits; 165577aee8e22c36257716c2df2f275724765704f20cJim Grosbach } 16566495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ImmOp.ChangeToImmediate(ImmedOffset); 1657cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng Offset = 0; 1658cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng return true; 16596495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 1660764ab52dd80310a205c9888bf166d09dab858f90Jim Grosbach 16616495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Otherwise, it didn't fit. Pull in what we can to simplify the immed. 16626495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ImmedOffset = ImmedOffset & Mask; 1663063efbf569e46776093ddf50099c98fdbb362167Jim Grosbach if (isSub) { 1664063efbf569e46776093ddf50099c98fdbb362167Jim Grosbach if (AddrMode == ARMII::AddrMode_i12) 1665063efbf569e46776093ddf50099c98fdbb362167Jim Grosbach ImmedOffset = -ImmedOffset; 1666063efbf569e46776093ddf50099c98fdbb362167Jim Grosbach else 1667063efbf569e46776093ddf50099c98fdbb362167Jim Grosbach ImmedOffset |= 1 << NumBits; 1668063efbf569e46776093ddf50099c98fdbb362167Jim Grosbach } 16696495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ImmOp.ChangeToImmediate(ImmedOffset); 16706495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng Offset &= ~(Mask*Scale); 16716495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 16726495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 16736495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 1674cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng Offset = (isSub) ? -Offset : Offset; 1675cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng return Offset == 0; 16766495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng} 1677e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling 1678e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendlingbool ARMBaseInstrInfo:: 1679a99c3e9acd95f5fbfb611e3f807240cd74001142Eric ChristopherAnalyzeCompare(const MachineInstr *MI, unsigned &SrcReg, int &CmpMask, 1680a99c3e9acd95f5fbfb611e3f807240cd74001142Eric Christopher int &CmpValue) const { 1681e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling switch (MI->getOpcode()) { 1682e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling default: break; 168338ae997e63e3e1bb2c8679e01ea74cf8fd0be893Bill Wendling case ARM::CMPri: 1684e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling case ARM::t2CMPri: 1685e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling SrcReg = MI->getOperand(0).getReg(); 168604ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif CmpMask = ~0; 1687e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling CmpValue = MI->getOperand(1).getImm(); 1688e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling return true; 168904ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif case ARM::TSTri: 169004ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif case ARM::t2TSTri: 169104ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif SrcReg = MI->getOperand(0).getReg(); 169204ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif CmpMask = MI->getOperand(1).getImm(); 169304ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif CmpValue = 0; 169404ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif return true; 169504ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif } 169604ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif 169704ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif return false; 169804ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif} 169904ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif 170005642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif/// isSuitableForMask - Identify a suitable 'and' instruction that 170105642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif/// operates on the given source register and applies the same mask 170205642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif/// as a 'tst' instruction. Provide a limited look-through for copies. 170305642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif/// When successful, MI will hold the found instruction. 170405642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greifstatic bool isSuitableForMask(MachineInstr *&MI, unsigned SrcReg, 17058ff9bb189ce188452e6cae6ed65cb2745814126cGabor Greif int CmpMask, bool CommonUse) { 170605642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif switch (MI->getOpcode()) { 170704ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif case ARM::ANDri: 170804ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif case ARM::t2ANDri: 170905642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif if (CmpMask != MI->getOperand(2).getImm()) 17108ff9bb189ce188452e6cae6ed65cb2745814126cGabor Greif return false; 171105642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif if (SrcReg == MI->getOperand(CommonUse ? 1 : 0).getReg()) 171204ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif return true; 171304ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif break; 171405642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif case ARM::COPY: { 171505642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif // Walk down one instruction which is potentially an 'and'. 171605642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif const MachineInstr &Copy = *MI; 1717f000a7a212590bfd45e23c05bff5e1b683d25dd6Michael J. Spencer MachineBasicBlock::iterator AND( 1718f000a7a212590bfd45e23c05bff5e1b683d25dd6Michael J. Spencer llvm::next(MachineBasicBlock::iterator(MI))); 171905642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif if (AND == MI->getParent()->end()) return false; 172005642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif MI = AND; 172105642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif return isSuitableForMask(MI, Copy.getOperand(0).getReg(), 172205642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif CmpMask, true); 172305642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif } 1724e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling } 1725e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling 1726e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling return false; 1727e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling} 1728e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling 1729a65568676d0d9d53dd4aae8f1c58271bb4cfff10Bill Wendling/// OptimizeCompareInstr - Convert the instruction supplying the argument to the 1730eb96a2f6c03c0ec97c56a3493ac38024afacc774Evan Cheng/// comparison into one that sets the zero bit in the flags register. 1731e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendlingbool ARMBaseInstrInfo:: 173204ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor GreifOptimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, int CmpMask, 1733eb96a2f6c03c0ec97c56a3493ac38024afacc774Evan Cheng int CmpValue, const MachineRegisterInfo *MRI) const { 17343665661a5708c8adc2727be38b56d1d87ddeb661Bill Wendling if (CmpValue != 0) 173592ad57f066e9f256e4e3d72febf152e68caa80c7Bill Wendling return false; 173692ad57f066e9f256e4e3d72febf152e68caa80c7Bill Wendling 1737b41ee96d76ccf1eec2fd898def4cfd7c16868708Bill Wendling MachineRegisterInfo::def_iterator DI = MRI->def_begin(SrcReg); 1738b41ee96d76ccf1eec2fd898def4cfd7c16868708Bill Wendling if (llvm::next(DI) != MRI->def_end()) 173992ad57f066e9f256e4e3d72febf152e68caa80c7Bill Wendling // Only support one definition. 174092ad57f066e9f256e4e3d72febf152e68caa80c7Bill Wendling return false; 174192ad57f066e9f256e4e3d72febf152e68caa80c7Bill Wendling 174292ad57f066e9f256e4e3d72febf152e68caa80c7Bill Wendling MachineInstr *MI = &*DI; 174392ad57f066e9f256e4e3d72febf152e68caa80c7Bill Wendling 174404ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif // Masked compares sometimes use the same register as the corresponding 'and'. 174504ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif if (CmpMask != ~0) { 174605642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif if (!isSuitableForMask(MI, SrcReg, CmpMask, false)) { 174704ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif MI = 0; 1748b41ee96d76ccf1eec2fd898def4cfd7c16868708Bill Wendling for (MachineRegisterInfo::use_iterator UI = MRI->use_begin(SrcReg), 1749b41ee96d76ccf1eec2fd898def4cfd7c16868708Bill Wendling UE = MRI->use_end(); UI != UE; ++UI) { 175004ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif if (UI->getParent() != CmpInstr->getParent()) continue; 175105642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif MachineInstr *PotentialAND = &*UI; 17528ff9bb189ce188452e6cae6ed65cb2745814126cGabor Greif if (!isSuitableForMask(PotentialAND, SrcReg, CmpMask, true)) 175304ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif continue; 175405642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif MI = PotentialAND; 175504ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif break; 175604ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif } 175704ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif if (!MI) return false; 175804ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif } 175904ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif } 176004ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif 1761e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling // Conservatively refuse to convert an instruction which isn't in the same BB 1762e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling // as the comparison. 1763e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling if (MI->getParent() != CmpInstr->getParent()) 1764e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling return false; 1765e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling 1766e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling // Check that CPSR isn't set between the comparison instruction and the one we 1767e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling // want to change. 1768691e64a54ce899409abe7c131d15ed75e3c1fef5Evan Cheng MachineBasicBlock::const_iterator I = CmpInstr, E = MI, 1769691e64a54ce899409abe7c131d15ed75e3c1fef5Evan Cheng B = MI->getParent()->begin(); 17700aa38b9381a5be42abd4f5ca5baa8c2930d148d3Bill Wendling 17710aa38b9381a5be42abd4f5ca5baa8c2930d148d3Bill Wendling // Early exit if CmpInstr is at the beginning of the BB. 17720aa38b9381a5be42abd4f5ca5baa8c2930d148d3Bill Wendling if (I == B) return false; 17730aa38b9381a5be42abd4f5ca5baa8c2930d148d3Bill Wendling 1774e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling --I; 1775e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling for (; I != E; --I) { 1776e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling const MachineInstr &Instr = *I; 1777e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling 1778e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling for (unsigned IO = 0, EO = Instr.getNumOperands(); IO != EO; ++IO) { 1779e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling const MachineOperand &MO = Instr.getOperand(IO); 178040a5eb18b031fa1a5e9697e21e251e613d441cc5Bill Wendling if (!MO.isReg()) continue; 1781e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling 178240a5eb18b031fa1a5e9697e21e251e613d441cc5Bill Wendling // This instruction modifies or uses CPSR after the one we want to 178340a5eb18b031fa1a5e9697e21e251e613d441cc5Bill Wendling // change. We can't do this transformation. 1784e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling if (MO.getReg() == ARM::CPSR) 1785e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling return false; 1786e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling } 1787691e64a54ce899409abe7c131d15ed75e3c1fef5Evan Cheng 1788691e64a54ce899409abe7c131d15ed75e3c1fef5Evan Cheng if (I == B) 1789691e64a54ce899409abe7c131d15ed75e3c1fef5Evan Cheng // The 'and' is below the comparison instruction. 1790691e64a54ce899409abe7c131d15ed75e3c1fef5Evan Cheng return false; 1791e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling } 1792e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling 1793e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling // Set the "zero" bit in CPSR. 1794e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling switch (MI->getOpcode()) { 1795e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling default: break; 1796ca3f6a3925e9a6e91022aa211bdc1b6e3f2ff41fCameron Zwarich case ARM::RSBrr: 1797df298c9ea64eb335f63fc075d8ef6306682ffe75Owen Anderson case ARM::RSBri: 1798ca3f6a3925e9a6e91022aa211bdc1b6e3f2ff41fCameron Zwarich case ARM::RSCrr: 1799df298c9ea64eb335f63fc075d8ef6306682ffe75Owen Anderson case ARM::RSCri: 1800ca3f6a3925e9a6e91022aa211bdc1b6e3f2ff41fCameron Zwarich case ARM::ADDrr: 180138ae997e63e3e1bb2c8679e01ea74cf8fd0be893Bill Wendling case ARM::ADDri: 1802ca3f6a3925e9a6e91022aa211bdc1b6e3f2ff41fCameron Zwarich case ARM::ADCrr: 1803df298c9ea64eb335f63fc075d8ef6306682ffe75Owen Anderson case ARM::ADCri: 1804ca3f6a3925e9a6e91022aa211bdc1b6e3f2ff41fCameron Zwarich case ARM::SUBrr: 180538ae997e63e3e1bb2c8679e01ea74cf8fd0be893Bill Wendling case ARM::SUBri: 1806ca3f6a3925e9a6e91022aa211bdc1b6e3f2ff41fCameron Zwarich case ARM::SBCrr: 1807df298c9ea64eb335f63fc075d8ef6306682ffe75Owen Anderson case ARM::SBCri: 1808df298c9ea64eb335f63fc075d8ef6306682ffe75Owen Anderson case ARM::t2RSBri: 1809ca3f6a3925e9a6e91022aa211bdc1b6e3f2ff41fCameron Zwarich case ARM::t2ADDrr: 181038ae997e63e3e1bb2c8679e01ea74cf8fd0be893Bill Wendling case ARM::t2ADDri: 1811ca3f6a3925e9a6e91022aa211bdc1b6e3f2ff41fCameron Zwarich case ARM::t2ADCrr: 1812df298c9ea64eb335f63fc075d8ef6306682ffe75Owen Anderson case ARM::t2ADCri: 1813ca3f6a3925e9a6e91022aa211bdc1b6e3f2ff41fCameron Zwarich case ARM::t2SUBrr: 1814df298c9ea64eb335f63fc075d8ef6306682ffe75Owen Anderson case ARM::t2SUBri: 1815ca3f6a3925e9a6e91022aa211bdc1b6e3f2ff41fCameron Zwarich case ARM::t2SBCrr: 1816b485de5d8c3fe0c62c0b07f63f64bd10f6803c17Cameron Zwarich case ARM::t2SBCri: 1817b485de5d8c3fe0c62c0b07f63f64bd10f6803c17Cameron Zwarich case ARM::ANDrr: 1818b485de5d8c3fe0c62c0b07f63f64bd10f6803c17Cameron Zwarich case ARM::ANDri: 1819b485de5d8c3fe0c62c0b07f63f64bd10f6803c17Cameron Zwarich case ARM::t2ANDrr: 18200cb11ac32fc09c5db42fb801db242ac9fb51f6b1Cameron Zwarich case ARM::t2ANDri: 18210cb11ac32fc09c5db42fb801db242ac9fb51f6b1Cameron Zwarich case ARM::ORRrr: 18220cb11ac32fc09c5db42fb801db242ac9fb51f6b1Cameron Zwarich case ARM::ORRri: 18230cb11ac32fc09c5db42fb801db242ac9fb51f6b1Cameron Zwarich case ARM::t2ORRrr: 18240cb11ac32fc09c5db42fb801db242ac9fb51f6b1Cameron Zwarich case ARM::t2ORRri: 18250cb11ac32fc09c5db42fb801db242ac9fb51f6b1Cameron Zwarich case ARM::EORrr: 18260cb11ac32fc09c5db42fb801db242ac9fb51f6b1Cameron Zwarich case ARM::EORri: 18270cb11ac32fc09c5db42fb801db242ac9fb51f6b1Cameron Zwarich case ARM::t2EORrr: 18280cb11ac32fc09c5db42fb801db242ac9fb51f6b1Cameron Zwarich case ARM::t2EORri: { 18292c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng // Scan forward for the use of CPSR, if it's a conditional code requires 18302c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng // checking of V bit, then this is not safe to do. If we can't find the 18312c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng // CPSR use (i.e. used in another block), then it's not safe to perform 18322c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng // the optimization. 18332c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng bool isSafe = false; 18342c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng I = CmpInstr; 18352c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng E = MI->getParent()->end(); 18362c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng while (!isSafe && ++I != E) { 18372c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng const MachineInstr &Instr = *I; 18382c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng for (unsigned IO = 0, EO = Instr.getNumOperands(); 18392c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng !isSafe && IO != EO; ++IO) { 18402c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng const MachineOperand &MO = Instr.getOperand(IO); 18412c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng if (!MO.isReg() || MO.getReg() != ARM::CPSR) 18422c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng continue; 18432c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng if (MO.isDef()) { 18442c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng isSafe = true; 18452c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng break; 18462c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng } 18472c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng // Condition code is after the operand before CPSR. 18482c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng ARMCC::CondCodes CC = (ARMCC::CondCodes)Instr.getOperand(IO-1).getImm(); 18492c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng switch (CC) { 18502c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng default: 18512c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng isSafe = true; 18522c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng break; 18532c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng case ARMCC::VS: 18542c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng case ARMCC::VC: 18552c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng case ARMCC::GE: 18562c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng case ARMCC::LT: 18572c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng case ARMCC::GT: 18582c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng case ARMCC::LE: 18592c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng return false; 18602c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng } 18612c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng } 18622c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng } 18632c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng 18642c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng if (!isSafe) 18652c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng return false; 18662c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng 18673642e64c114e636548888c72c21ae023ee0121a7Evan Cheng // Toggle the optional operand to CPSR. 18683642e64c114e636548888c72c21ae023ee0121a7Evan Cheng MI->getOperand(5).setReg(ARM::CPSR); 18693642e64c114e636548888c72c21ae023ee0121a7Evan Cheng MI->getOperand(5).setIsDef(true); 1870e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling CmpInstr->eraseFromParent(); 1871e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling return true; 1872e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling } 1873b485de5d8c3fe0c62c0b07f63f64bd10f6803c17Cameron Zwarich } 1874e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling 1875e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling return false; 1876e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling} 18775f54ce347368105260be2cec497b6a4199dc5789Evan Cheng 1878c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Chengbool ARMBaseInstrInfo::FoldImmediate(MachineInstr *UseMI, 1879c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng MachineInstr *DefMI, unsigned Reg, 1880c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng MachineRegisterInfo *MRI) const { 1881c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng // Fold large immediates into add, sub, or, xor. 1882c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng unsigned DefOpc = DefMI->getOpcode(); 1883c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng if (DefOpc != ARM::t2MOVi32imm && DefOpc != ARM::MOVi32imm) 1884c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng return false; 1885c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng if (!DefMI->getOperand(1).isImm()) 1886c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng // Could be t2MOVi32imm <ga:xx> 1887c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng return false; 1888c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng 1889c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng if (!MRI->hasOneNonDBGUse(Reg)) 1890c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng return false; 1891c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng 1892c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng unsigned UseOpc = UseMI->getOpcode(); 18935c71c7a13715ed6f5bfdd5497172ddec316b68b0Evan Cheng unsigned NewUseOpc = 0; 1894c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng uint32_t ImmVal = (uint32_t)DefMI->getOperand(1).getImm(); 18955c71c7a13715ed6f5bfdd5497172ddec316b68b0Evan Cheng uint32_t SOImmValV1 = 0, SOImmValV2 = 0; 1896c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng bool Commute = false; 1897c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng switch (UseOpc) { 1898c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng default: return false; 1899c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::SUBrr: 1900c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::ADDrr: 1901c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::ORRrr: 1902c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::EORrr: 1903c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::t2SUBrr: 1904c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::t2ADDrr: 1905c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::t2ORRrr: 1906c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::t2EORrr: { 1907c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng Commute = UseMI->getOperand(2).getReg() != Reg; 1908c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng switch (UseOpc) { 1909c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng default: break; 1910c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::SUBrr: { 1911c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng if (Commute) 1912c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng return false; 1913c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng ImmVal = -ImmVal; 1914c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng NewUseOpc = ARM::SUBri; 1915c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng // Fallthrough 1916c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng } 1917c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::ADDrr: 1918c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::ORRrr: 1919c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::EORrr: { 1920c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng if (!ARM_AM::isSOImmTwoPartVal(ImmVal)) 1921c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng return false; 1922c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng SOImmValV1 = (uint32_t)ARM_AM::getSOImmTwoPartFirst(ImmVal); 1923c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng SOImmValV2 = (uint32_t)ARM_AM::getSOImmTwoPartSecond(ImmVal); 1924c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng switch (UseOpc) { 1925c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng default: break; 1926c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::ADDrr: NewUseOpc = ARM::ADDri; break; 1927c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::ORRrr: NewUseOpc = ARM::ORRri; break; 1928c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::EORrr: NewUseOpc = ARM::EORri; break; 1929c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng } 1930c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng break; 1931c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng } 1932c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::t2SUBrr: { 1933c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng if (Commute) 1934c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng return false; 1935c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng ImmVal = -ImmVal; 1936c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng NewUseOpc = ARM::t2SUBri; 1937c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng // Fallthrough 1938c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng } 1939c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::t2ADDrr: 1940c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::t2ORRrr: 1941c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::t2EORrr: { 1942c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng if (!ARM_AM::isT2SOImmTwoPartVal(ImmVal)) 1943c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng return false; 1944c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng SOImmValV1 = (uint32_t)ARM_AM::getT2SOImmTwoPartFirst(ImmVal); 1945c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng SOImmValV2 = (uint32_t)ARM_AM::getT2SOImmTwoPartSecond(ImmVal); 1946c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng switch (UseOpc) { 1947c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng default: break; 1948c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::t2ADDrr: NewUseOpc = ARM::t2ADDri; break; 1949c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::t2ORRrr: NewUseOpc = ARM::t2ORRri; break; 1950c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::t2EORrr: NewUseOpc = ARM::t2EORri; break; 1951c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng } 1952c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng break; 1953c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng } 1954c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng } 1955c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng } 1956c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng } 1957c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng 1958c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng unsigned OpIdx = Commute ? 2 : 1; 1959c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng unsigned Reg1 = UseMI->getOperand(OpIdx).getReg(); 1960c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng bool isKill = UseMI->getOperand(OpIdx).isKill(); 1961c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng unsigned NewReg = MRI->createVirtualRegister(MRI->getRegClass(Reg)); 1962c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng AddDefaultCC(AddDefaultPred(BuildMI(*UseMI->getParent(), 1963c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng *UseMI, UseMI->getDebugLoc(), 1964c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng get(NewUseOpc), NewReg) 1965c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng .addReg(Reg1, getKillRegState(isKill)) 1966c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng .addImm(SOImmValV1))); 1967c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng UseMI->setDesc(get(NewUseOpc)); 1968c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng UseMI->getOperand(1).setReg(NewReg); 1969c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng UseMI->getOperand(1).setIsKill(); 1970c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng UseMI->getOperand(2).ChangeToImmediate(SOImmValV2); 1971c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng DefMI->eraseFromParent(); 1972c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng return true; 1973c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng} 1974c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng 19755f54ce347368105260be2cec497b6a4199dc5789Evan Chengunsigned 19768239daf7c83a65a189c352cce3191cdc3bbfe151Evan ChengARMBaseInstrInfo::getNumMicroOps(const InstrItineraryData *ItinData, 19778239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng const MachineInstr *MI) const { 19783ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng if (!ItinData || ItinData->isEmpty()) 19795f54ce347368105260be2cec497b6a4199dc5789Evan Cheng return 1; 19805f54ce347368105260be2cec497b6a4199dc5789Evan Cheng 1981e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng const MCInstrDesc &Desc = MI->getDesc(); 19825f54ce347368105260be2cec497b6a4199dc5789Evan Cheng unsigned Class = Desc.getSchedClass(); 1983064312de8641043b084603aa9a6b409bc794eed2Bob Wilson unsigned UOps = ItinData->Itineraries[Class].NumMicroOps; 19845f54ce347368105260be2cec497b6a4199dc5789Evan Cheng if (UOps) 19855f54ce347368105260be2cec497b6a4199dc5789Evan Cheng return UOps; 19865f54ce347368105260be2cec497b6a4199dc5789Evan Cheng 19875f54ce347368105260be2cec497b6a4199dc5789Evan Cheng unsigned Opc = MI->getOpcode(); 19885f54ce347368105260be2cec497b6a4199dc5789Evan Cheng switch (Opc) { 19895f54ce347368105260be2cec497b6a4199dc5789Evan Cheng default: 19905f54ce347368105260be2cec497b6a4199dc5789Evan Cheng llvm_unreachable("Unexpected multi-uops instruction!"); 19915f54ce347368105260be2cec497b6a4199dc5789Evan Cheng break; 199273fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMQIA: 199373fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMQIA: 19945f54ce347368105260be2cec497b6a4199dc5789Evan Cheng return 2; 19955f54ce347368105260be2cec497b6a4199dc5789Evan Cheng 19965f54ce347368105260be2cec497b6a4199dc5789Evan Cheng // The number of uOps for load / store multiple are determined by the number 19975f54ce347368105260be2cec497b6a4199dc5789Evan Cheng // registers. 19986e8f4c404825b79f9b9176483653f1aa927dfbdeAndrew Trick // 19993ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng // On Cortex-A8, each pair of register loads / stores can be scheduled on the 20003ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng // same cycle. The scheduling for the first load / store must be done 20013ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng // separately by assuming the the address is not 64-bit aligned. 200273fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling // 20033ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng // On Cortex-A9, the formula is simply (#reg / 2) + (#reg % 2). If the address 200473fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling // is not 64-bit aligned, then AGU would take an extra cycle. For VFP / NEON 200573fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling // load / store multiple, the formula is (#reg / 2) + (#reg % 2) + 1. 200673fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMDIA: 200773fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMDIA_UPD: 200873fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMDDB_UPD: 200973fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMSIA: 201073fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMSIA_UPD: 201173fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMSDB_UPD: 201273fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMDIA: 201373fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMDIA_UPD: 201473fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMDDB_UPD: 201573fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMSIA: 201673fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMSIA_UPD: 201773fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMSDB_UPD: { 20185f54ce347368105260be2cec497b6a4199dc5789Evan Cheng unsigned NumRegs = MI->getNumOperands() - Desc.getNumOperands(); 20195f54ce347368105260be2cec497b6a4199dc5789Evan Cheng return (NumRegs / 2) + (NumRegs % 2) + 1; 20205f54ce347368105260be2cec497b6a4199dc5789Evan Cheng } 202173fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling 202273fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMIA_RET: 202373fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMIA: 202473fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMDA: 202573fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMDB: 202673fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMIB: 202773fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMIA_UPD: 202873fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMDA_UPD: 202973fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMDB_UPD: 203073fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMIB_UPD: 203173fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::STMIA: 203273fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::STMDA: 203373fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::STMDB: 203473fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::STMIB: 203573fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::STMIA_UPD: 203673fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::STMDA_UPD: 203773fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::STMDB_UPD: 203873fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::STMIB_UPD: 203973fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::tLDMIA: 204073fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::tLDMIA_UPD: 204173fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::tSTMIA_UPD: 20425f54ce347368105260be2cec497b6a4199dc5789Evan Cheng case ARM::tPOP_RET: 20435f54ce347368105260be2cec497b6a4199dc5789Evan Cheng case ARM::tPOP: 20445f54ce347368105260be2cec497b6a4199dc5789Evan Cheng case ARM::tPUSH: 204573fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2LDMIA_RET: 204673fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2LDMIA: 204773fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2LDMDB: 204873fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2LDMIA_UPD: 204973fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2LDMDB_UPD: 205073fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2STMIA: 205173fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2STMDB: 205273fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2STMIA_UPD: 205373fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2STMDB_UPD: { 20543ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng unsigned NumRegs = MI->getNumOperands() - Desc.getNumOperands() + 1; 20553ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng if (Subtarget.isCortexA8()) { 20568239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng if (NumRegs < 4) 20578239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng return 2; 20588239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng // 4 registers would be issued: 2, 2. 20598239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng // 5 registers would be issued: 2, 2, 1. 20608239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng UOps = (NumRegs / 2); 20618239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng if (NumRegs % 2) 20628239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng ++UOps; 20638239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng return UOps; 20643ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng } else if (Subtarget.isCortexA9()) { 20653ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng UOps = (NumRegs / 2); 20663ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng // If there are odd number of registers or if it's not 64-bit aligned, 20673ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng // then it takes an extra AGU (Address Generation Unit) cycle. 20683ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng if ((NumRegs % 2) || 20693ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng !MI->hasOneMemOperand() || 20703ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng (*MI->memoperands_begin())->getAlignment() < 8) 20713ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng ++UOps; 20723ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng return UOps; 20733ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng } else { 20743ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng // Assume the worst. 20753ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng return NumRegs; 20762bbb76909126db5bed6bde84b16d94ab5de4d372Michael J. Spencer } 20775f54ce347368105260be2cec497b6a4199dc5789Evan Cheng } 20785f54ce347368105260be2cec497b6a4199dc5789Evan Cheng } 20795f54ce347368105260be2cec497b6a4199dc5789Evan Cheng} 2080a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng 2081a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Chengint 2082344d9db97062736cd66da6c07baa9108b6cfa419Evan ChengARMBaseInstrInfo::getVLDMDefCycle(const InstrItineraryData *ItinData, 2083e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng const MCInstrDesc &DefMCID, 2084344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng unsigned DefClass, 2085344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng unsigned DefIdx, unsigned DefAlign) const { 2086e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng int RegNo = (int)(DefIdx+1) - DefMCID.getNumOperands() + 1; 2087344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng if (RegNo <= 0) 2088344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // Def is the address writeback. 2089344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng return ItinData->getOperandCycle(DefClass, DefIdx); 2090344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng 2091344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng int DefCycle; 2092344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng if (Subtarget.isCortexA8()) { 2093344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // (regno / 2) + (regno % 2) + 1 2094344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng DefCycle = RegNo / 2 + 1; 2095344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng if (RegNo % 2) 2096344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng ++DefCycle; 2097344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng } else if (Subtarget.isCortexA9()) { 2098344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng DefCycle = RegNo; 2099344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng bool isSLoad = false; 210073fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling 2101e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng switch (DefMCID.getOpcode()) { 2102344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng default: break; 210373fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMSIA: 210473fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMSIA_UPD: 210573fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMSDB_UPD: 2106344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng isSLoad = true; 2107344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng break; 2108344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng } 210973fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling 2110344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // If there are odd number of 'S' registers or if it's not 64-bit aligned, 2111344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // then it takes an extra cycle. 2112344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng if ((isSLoad && (RegNo % 2)) || DefAlign < 8) 2113344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng ++DefCycle; 2114344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng } else { 2115344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // Assume the worst. 2116344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng DefCycle = RegNo + 2; 2117344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng } 2118344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng 2119344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng return DefCycle; 2120344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng} 2121344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng 2122344d9db97062736cd66da6c07baa9108b6cfa419Evan Chengint 2123344d9db97062736cd66da6c07baa9108b6cfa419Evan ChengARMBaseInstrInfo::getLDMDefCycle(const InstrItineraryData *ItinData, 2124e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng const MCInstrDesc &DefMCID, 2125344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng unsigned DefClass, 2126344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng unsigned DefIdx, unsigned DefAlign) const { 2127e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng int RegNo = (int)(DefIdx+1) - DefMCID.getNumOperands() + 1; 2128344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng if (RegNo <= 0) 2129344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // Def is the address writeback. 2130344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng return ItinData->getOperandCycle(DefClass, DefIdx); 2131344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng 2132344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng int DefCycle; 2133344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng if (Subtarget.isCortexA8()) { 2134344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // 4 registers would be issued: 1, 2, 1. 2135344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // 5 registers would be issued: 1, 2, 2. 2136344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng DefCycle = RegNo / 2; 2137344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng if (DefCycle < 1) 2138344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng DefCycle = 1; 2139344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // Result latency is issue cycle + 2: E2. 2140344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng DefCycle += 2; 2141344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng } else if (Subtarget.isCortexA9()) { 2142344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng DefCycle = (RegNo / 2); 2143344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // If there are odd number of registers or if it's not 64-bit aligned, 2144344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // then it takes an extra AGU (Address Generation Unit) cycle. 2145344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng if ((RegNo % 2) || DefAlign < 8) 2146344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng ++DefCycle; 2147344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // Result latency is AGU cycles + 2. 2148344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng DefCycle += 2; 2149344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng } else { 2150344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // Assume the worst. 2151344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng DefCycle = RegNo + 2; 2152344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng } 2153344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng 2154344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng return DefCycle; 2155344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng} 2156344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng 2157344d9db97062736cd66da6c07baa9108b6cfa419Evan Chengint 2158344d9db97062736cd66da6c07baa9108b6cfa419Evan ChengARMBaseInstrInfo::getVSTMUseCycle(const InstrItineraryData *ItinData, 2159e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng const MCInstrDesc &UseMCID, 2160344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng unsigned UseClass, 2161344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng unsigned UseIdx, unsigned UseAlign) const { 2162e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng int RegNo = (int)(UseIdx+1) - UseMCID.getNumOperands() + 1; 2163344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng if (RegNo <= 0) 2164344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng return ItinData->getOperandCycle(UseClass, UseIdx); 2165344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng 2166344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng int UseCycle; 2167344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng if (Subtarget.isCortexA8()) { 2168344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // (regno / 2) + (regno % 2) + 1 2169344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng UseCycle = RegNo / 2 + 1; 2170344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng if (RegNo % 2) 2171344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng ++UseCycle; 2172344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng } else if (Subtarget.isCortexA9()) { 2173344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng UseCycle = RegNo; 2174344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng bool isSStore = false; 217573fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling 2176e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng switch (UseMCID.getOpcode()) { 2177344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng default: break; 217873fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMSIA: 217973fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMSIA_UPD: 218073fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMSDB_UPD: 2181344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng isSStore = true; 2182344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng break; 2183344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng } 218473fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling 2185344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // If there are odd number of 'S' registers or if it's not 64-bit aligned, 2186344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // then it takes an extra cycle. 2187344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng if ((isSStore && (RegNo % 2)) || UseAlign < 8) 2188344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng ++UseCycle; 2189344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng } else { 2190344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // Assume the worst. 2191344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng UseCycle = RegNo + 2; 2192344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng } 2193344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng 2194344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng return UseCycle; 2195344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng} 2196344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng 2197344d9db97062736cd66da6c07baa9108b6cfa419Evan Chengint 2198344d9db97062736cd66da6c07baa9108b6cfa419Evan ChengARMBaseInstrInfo::getSTMUseCycle(const InstrItineraryData *ItinData, 2199e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng const MCInstrDesc &UseMCID, 2200344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng unsigned UseClass, 2201344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng unsigned UseIdx, unsigned UseAlign) const { 2202e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng int RegNo = (int)(UseIdx+1) - UseMCID.getNumOperands() + 1; 2203344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng if (RegNo <= 0) 2204344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng return ItinData->getOperandCycle(UseClass, UseIdx); 2205344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng 2206344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng int UseCycle; 2207344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng if (Subtarget.isCortexA8()) { 2208344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng UseCycle = RegNo / 2; 2209344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng if (UseCycle < 2) 2210344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng UseCycle = 2; 2211344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // Read in E3. 2212344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng UseCycle += 2; 2213344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng } else if (Subtarget.isCortexA9()) { 2214344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng UseCycle = (RegNo / 2); 2215344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // If there are odd number of registers or if it's not 64-bit aligned, 2216344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // then it takes an extra AGU (Address Generation Unit) cycle. 2217344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng if ((RegNo % 2) || UseAlign < 8) 2218344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng ++UseCycle; 2219344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng } else { 2220344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // Assume the worst. 2221344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng UseCycle = 1; 2222344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng } 2223344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng return UseCycle; 2224344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng} 2225344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng 2226344d9db97062736cd66da6c07baa9108b6cfa419Evan Chengint 2227a0792de66c8364d47b0a688c7f408efb7b10f31bEvan ChengARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData, 2228e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng const MCInstrDesc &DefMCID, 2229a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng unsigned DefIdx, unsigned DefAlign, 2230e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng const MCInstrDesc &UseMCID, 2231a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng unsigned UseIdx, unsigned UseAlign) const { 2232e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng unsigned DefClass = DefMCID.getSchedClass(); 2233e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng unsigned UseClass = UseMCID.getSchedClass(); 2234a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng 2235e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng if (DefIdx < DefMCID.getNumDefs() && UseIdx < UseMCID.getNumOperands()) 2236a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx); 2237a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng 2238a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng // This may be a def / use of a variable_ops instruction, the operand 2239a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng // latency might be determinable dynamically. Let the target try to 2240a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng // figure it out. 22419e08ee5d16b596078e20787f0b5f36121f099333Evan Cheng int DefCycle = -1; 22427e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng bool LdmBypass = false; 2243e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng switch (DefMCID.getOpcode()) { 2244a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng default: 2245a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng DefCycle = ItinData->getOperandCycle(DefClass, DefIdx); 2246a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng break; 224773fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling 224873fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMDIA: 224973fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMDIA_UPD: 225073fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMDDB_UPD: 225173fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMSIA: 225273fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMSIA_UPD: 225373fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMSDB_UPD: 2254e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng DefCycle = getVLDMDefCycle(ItinData, DefMCID, DefClass, DefIdx, DefAlign); 22555a50ceeaea980962c1982ad535226c7ab06c971cEvan Cheng break; 225673fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling 225773fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMIA_RET: 225873fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMIA: 225973fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMDA: 226073fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMDB: 226173fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMIB: 226273fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMIA_UPD: 226373fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMDA_UPD: 226473fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMDB_UPD: 226573fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMIB_UPD: 226673fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::tLDMIA: 226773fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::tLDMIA_UPD: 2268a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng case ARM::tPUSH: 226973fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2LDMIA_RET: 227073fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2LDMIA: 227173fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2LDMDB: 227273fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2LDMIA_UPD: 227373fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2LDMDB_UPD: 2274a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng LdmBypass = 1; 2275e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng DefCycle = getLDMDefCycle(ItinData, DefMCID, DefClass, DefIdx, DefAlign); 2276344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng break; 2277a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng } 2278a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng 2279a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng if (DefCycle == -1) 2280a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng // We can't seem to determine the result latency of the def, assume it's 2. 2281a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng DefCycle = 2; 2282a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng 2283a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng int UseCycle = -1; 2284e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng switch (UseMCID.getOpcode()) { 2285a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng default: 2286a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng UseCycle = ItinData->getOperandCycle(UseClass, UseIdx); 2287a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng break; 228873fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling 228973fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMDIA: 229073fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMDIA_UPD: 229173fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMDDB_UPD: 229273fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMSIA: 229373fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMSIA_UPD: 229473fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMSDB_UPD: 2295e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng UseCycle = getVSTMUseCycle(ItinData, UseMCID, UseClass, UseIdx, UseAlign); 22965a50ceeaea980962c1982ad535226c7ab06c971cEvan Cheng break; 229773fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling 229873fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::STMIA: 229973fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::STMDA: 230073fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::STMDB: 230173fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::STMIB: 230273fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::STMIA_UPD: 230373fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::STMDA_UPD: 230473fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::STMDB_UPD: 230573fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::STMIB_UPD: 230673fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::tSTMIA_UPD: 2307a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng case ARM::tPOP_RET: 2308a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng case ARM::tPOP: 230973fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2STMIA: 231073fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2STMDB: 231173fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2STMIA_UPD: 231273fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2STMDB_UPD: 2313e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng UseCycle = getSTMUseCycle(ItinData, UseMCID, UseClass, UseIdx, UseAlign); 23145a50ceeaea980962c1982ad535226c7ab06c971cEvan Cheng break; 2315a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng } 2316a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng 2317a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng if (UseCycle == -1) 2318a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng // Assume it's read in the first stage. 2319a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng UseCycle = 1; 2320a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng 2321a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng UseCycle = DefCycle - UseCycle + 1; 2322a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng if (UseCycle > 0) { 2323a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng if (LdmBypass) { 2324a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng // It's a variable_ops instruction so we can't use DefIdx here. Just use 2325a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng // first def operand. 2326e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng if (ItinData->hasPipelineForwarding(DefClass, DefMCID.getNumOperands()-1, 2327a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng UseClass, UseIdx)) 2328a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng --UseCycle; 2329a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng } else if (ItinData->hasPipelineForwarding(DefClass, DefIdx, 233073fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling UseClass, UseIdx)) { 2331a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng --UseCycle; 233273fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling } 2333a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng } 2334a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng 2335a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng return UseCycle; 2336a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng} 2337a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng 2338a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Chengint 2339a0792de66c8364d47b0a688c7f408efb7b10f31bEvan ChengARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData, 2340a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng const MachineInstr *DefMI, unsigned DefIdx, 2341a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng const MachineInstr *UseMI, unsigned UseIdx) const { 2342a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng if (DefMI->isCopyLike() || DefMI->isInsertSubreg() || 2343a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng DefMI->isRegSequence() || DefMI->isImplicitDef()) 2344a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng return 1; 2345a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng 2346e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng const MCInstrDesc &DefMCID = DefMI->getDesc(); 2347a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng if (!ItinData || ItinData->isEmpty()) 2348e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng return DefMCID.mayLoad() ? 3 : 1; 2349a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng 2350e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng const MCInstrDesc &UseMCID = UseMI->getDesc(); 2351dd9dd6f857604abdeb5213648ffe50c10ccc59b9Evan Cheng const MachineOperand &DefMO = DefMI->getOperand(DefIdx); 2352e09206d4d7683e2a421104c5cb83f7808ba4b06eEvan Cheng if (DefMO.getReg() == ARM::CPSR) { 2353e09206d4d7683e2a421104c5cb83f7808ba4b06eEvan Cheng if (DefMI->getOpcode() == ARM::FMSTAT) { 2354e09206d4d7683e2a421104c5cb83f7808ba4b06eEvan Cheng // fpscr -> cpsr stalls over 20 cycles on A8 (and earlier?) 2355e09206d4d7683e2a421104c5cb83f7808ba4b06eEvan Cheng return Subtarget.isCortexA9() ? 1 : 20; 2356e09206d4d7683e2a421104c5cb83f7808ba4b06eEvan Cheng } 2357e09206d4d7683e2a421104c5cb83f7808ba4b06eEvan Cheng 2358dd9dd6f857604abdeb5213648ffe50c10ccc59b9Evan Cheng // CPSR set and branch can be paired in the same cycle. 2359e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng if (UseMCID.isBranch()) 2360e09206d4d7683e2a421104c5cb83f7808ba4b06eEvan Cheng return 0; 2361e09206d4d7683e2a421104c5cb83f7808ba4b06eEvan Cheng } 2362dd9dd6f857604abdeb5213648ffe50c10ccc59b9Evan Cheng 2363a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng unsigned DefAlign = DefMI->hasOneMemOperand() 2364a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng ? (*DefMI->memoperands_begin())->getAlignment() : 0; 2365a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng unsigned UseAlign = UseMI->hasOneMemOperand() 2366a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng ? (*UseMI->memoperands_begin())->getAlignment() : 0; 2367e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng int Latency = getOperandLatency(ItinData, DefMCID, DefIdx, DefAlign, 2368e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng UseMCID, UseIdx, UseAlign); 23697e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng 23707e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng if (Latency > 1 && 23717e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng (Subtarget.isCortexA8() || Subtarget.isCortexA9())) { 23727e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng // FIXME: Shifter op hack: no shift (i.e. [r +/- r]) or [r + r << 2] 23737e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng // variants are one cycle cheaper. 2374e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng switch (DefMCID.getOpcode()) { 23757e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng default: break; 23767e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng case ARM::LDRrs: 23777e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng case ARM::LDRBrs: { 23787e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng unsigned ShOpVal = DefMI->getOperand(3).getImm(); 23797e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal); 23807e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng if (ShImm == 0 || 23817e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng (ShImm == 2 && ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl)) 23827e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng --Latency; 23837e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng break; 23847e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng } 23857e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng case ARM::t2LDRs: 23867e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng case ARM::t2LDRBs: 23877e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng case ARM::t2LDRHs: 23887e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng case ARM::t2LDRSHs: { 23897e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng // Thumb2 mode: lsl only. 23907e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng unsigned ShAmt = DefMI->getOperand(3).getImm(); 23917e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng if (ShAmt == 0 || ShAmt == 2) 23927e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng --Latency; 23937e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng break; 23947e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng } 23957e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng } 23967e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng } 23977e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng 239875b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng if (DefAlign < 8 && Subtarget.isCortexA9()) 2399e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng switch (DefMCID.getOpcode()) { 240075b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng default: break; 240175b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1q8: 240275b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1q16: 240375b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1q32: 240475b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1q64: 240575b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1q8_UPD: 240675b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1q16_UPD: 240775b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1q32_UPD: 240875b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1q64_UPD: 240975b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2d8: 241075b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2d16: 241175b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2d32: 241275b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2q8: 241375b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2q16: 241475b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2q32: 241575b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2d8_UPD: 241675b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2d16_UPD: 241775b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2d32_UPD: 241875b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2q8_UPD: 241975b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2q16_UPD: 242075b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2q32_UPD: 242175b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3d8: 242275b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3d16: 242375b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3d32: 242475b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1d64T: 242575b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3d8_UPD: 242675b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3d16_UPD: 242775b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3d32_UPD: 242875b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1d64T_UPD: 242975b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3q8_UPD: 243075b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3q16_UPD: 243175b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3q32_UPD: 243275b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4d8: 243375b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4d16: 243475b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4d32: 243575b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1d64Q: 243675b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4d8_UPD: 243775b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4d16_UPD: 243875b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4d32_UPD: 243975b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1d64Q_UPD: 244075b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4q8_UPD: 244175b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4q16_UPD: 244275b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4q32_UPD: 244375b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1DUPq8: 244475b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1DUPq16: 244575b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1DUPq32: 244675b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1DUPq8_UPD: 244775b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1DUPq16_UPD: 244875b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1DUPq32_UPD: 244975b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2DUPd8: 245075b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2DUPd16: 245175b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2DUPd32: 245275b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2DUPd8_UPD: 245375b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2DUPd16_UPD: 245475b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2DUPd32_UPD: 245575b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4DUPd8: 245675b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4DUPd16: 245775b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4DUPd32: 245875b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4DUPd8_UPD: 245975b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4DUPd16_UPD: 246075b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4DUPd32_UPD: 246175b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1LNd8: 246275b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1LNd16: 246375b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1LNd32: 246475b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1LNd8_UPD: 246575b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1LNd16_UPD: 246675b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1LNd32_UPD: 246775b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2LNd8: 246875b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2LNd16: 246975b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2LNd32: 247075b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2LNq16: 247175b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2LNq32: 247275b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2LNd8_UPD: 247375b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2LNd16_UPD: 247475b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2LNd32_UPD: 247575b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2LNq16_UPD: 247675b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2LNq32_UPD: 247775b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4LNd8: 247875b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4LNd16: 247975b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4LNd32: 248075b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4LNq16: 248175b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4LNq32: 248275b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4LNd8_UPD: 248375b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4LNd16_UPD: 248475b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4LNd32_UPD: 248575b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4LNq16_UPD: 248675b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4LNq32_UPD: 248775b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng // If the address is not 64-bit aligned, the latencies of these 248875b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng // instructions increases by one. 248975b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng ++Latency; 249075b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng break; 249175b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng } 249275b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng 24937e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng return Latency; 2494a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng} 2495a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng 2496a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Chengint 2497a0792de66c8364d47b0a688c7f408efb7b10f31bEvan ChengARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData, 2498a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng SDNode *DefNode, unsigned DefIdx, 2499a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng SDNode *UseNode, unsigned UseIdx) const { 2500a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng if (!DefNode->isMachineOpcode()) 2501a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng return 1; 2502a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng 2503e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng const MCInstrDesc &DefMCID = get(DefNode->getMachineOpcode()); 2504c8bfd1d78ff9a307d1d4cb57cce4549b538e60f4Andrew Trick 2505e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng if (isZeroCost(DefMCID.Opcode)) 2506c8bfd1d78ff9a307d1d4cb57cce4549b538e60f4Andrew Trick return 0; 2507c8bfd1d78ff9a307d1d4cb57cce4549b538e60f4Andrew Trick 2508a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng if (!ItinData || ItinData->isEmpty()) 2509e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng return DefMCID.mayLoad() ? 3 : 1; 2510a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng 2511089751535d6e9adf65842e2ca5867bf9a70e1e95Evan Cheng if (!UseNode->isMachineOpcode()) { 2512e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng int Latency = ItinData->getOperandCycle(DefMCID.getSchedClass(), DefIdx); 2513089751535d6e9adf65842e2ca5867bf9a70e1e95Evan Cheng if (Subtarget.isCortexA9()) 2514089751535d6e9adf65842e2ca5867bf9a70e1e95Evan Cheng return Latency <= 2 ? 1 : Latency - 1; 2515089751535d6e9adf65842e2ca5867bf9a70e1e95Evan Cheng else 2516089751535d6e9adf65842e2ca5867bf9a70e1e95Evan Cheng return Latency <= 3 ? 1 : Latency - 2; 2517089751535d6e9adf65842e2ca5867bf9a70e1e95Evan Cheng } 2518a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng 2519e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng const MCInstrDesc &UseMCID = get(UseNode->getMachineOpcode()); 2520a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng const MachineSDNode *DefMN = dyn_cast<MachineSDNode>(DefNode); 2521a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng unsigned DefAlign = !DefMN->memoperands_empty() 2522a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng ? (*DefMN->memoperands_begin())->getAlignment() : 0; 2523a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng const MachineSDNode *UseMN = dyn_cast<MachineSDNode>(UseNode); 2524a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng unsigned UseAlign = !UseMN->memoperands_empty() 2525a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng ? (*UseMN->memoperands_begin())->getAlignment() : 0; 2526e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng int Latency = getOperandLatency(ItinData, DefMCID, DefIdx, DefAlign, 2527e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng UseMCID, UseIdx, UseAlign); 25287e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng 25297e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng if (Latency > 1 && 25307e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng (Subtarget.isCortexA8() || Subtarget.isCortexA9())) { 25317e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng // FIXME: Shifter op hack: no shift (i.e. [r +/- r]) or [r + r << 2] 25327e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng // variants are one cycle cheaper. 2533e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng switch (DefMCID.getOpcode()) { 25347e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng default: break; 25357e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng case ARM::LDRrs: 25367e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng case ARM::LDRBrs: { 25377e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng unsigned ShOpVal = 25387e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng cast<ConstantSDNode>(DefNode->getOperand(2))->getZExtValue(); 25397e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal); 25407e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng if (ShImm == 0 || 25417e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng (ShImm == 2 && ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl)) 25427e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng --Latency; 25437e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng break; 25447e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng } 25457e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng case ARM::t2LDRs: 25467e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng case ARM::t2LDRBs: 25477e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng case ARM::t2LDRHs: 25487e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng case ARM::t2LDRSHs: { 25497e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng // Thumb2 mode: lsl only. 25507e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng unsigned ShAmt = 25517e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng cast<ConstantSDNode>(DefNode->getOperand(2))->getZExtValue(); 25527e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng if (ShAmt == 0 || ShAmt == 2) 25537e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng --Latency; 25547e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng break; 25557e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng } 25567e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng } 25577e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng } 25587e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng 255975b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng if (DefAlign < 8 && Subtarget.isCortexA9()) 2560e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng switch (DefMCID.getOpcode()) { 256175b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng default: break; 256275b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1q8Pseudo: 256375b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1q16Pseudo: 256475b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1q32Pseudo: 256575b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1q64Pseudo: 256675b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1q8Pseudo_UPD: 256775b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1q16Pseudo_UPD: 256875b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1q32Pseudo_UPD: 256975b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1q64Pseudo_UPD: 257075b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2d8Pseudo: 257175b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2d16Pseudo: 257275b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2d32Pseudo: 257375b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2q8Pseudo: 257475b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2q16Pseudo: 257575b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2q32Pseudo: 257675b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2d8Pseudo_UPD: 257775b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2d16Pseudo_UPD: 257875b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2d32Pseudo_UPD: 257975b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2q8Pseudo_UPD: 258075b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2q16Pseudo_UPD: 258175b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2q32Pseudo_UPD: 258275b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3d8Pseudo: 258375b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3d16Pseudo: 258475b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3d32Pseudo: 258575b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1d64TPseudo: 258675b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3d8Pseudo_UPD: 258775b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3d16Pseudo_UPD: 258875b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3d32Pseudo_UPD: 258975b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1d64TPseudo_UPD: 259075b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3q8Pseudo_UPD: 259175b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3q16Pseudo_UPD: 259275b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3q32Pseudo_UPD: 259375b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3q8oddPseudo: 259475b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3q16oddPseudo: 259575b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3q32oddPseudo: 259675b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3q8oddPseudo_UPD: 259775b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3q16oddPseudo_UPD: 259875b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3q32oddPseudo_UPD: 259975b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4d8Pseudo: 260075b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4d16Pseudo: 260175b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4d32Pseudo: 260275b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1d64QPseudo: 260375b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4d8Pseudo_UPD: 260475b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4d16Pseudo_UPD: 260575b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4d32Pseudo_UPD: 260675b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1d64QPseudo_UPD: 260775b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4q8Pseudo_UPD: 260875b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4q16Pseudo_UPD: 260975b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4q32Pseudo_UPD: 261075b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4q8oddPseudo: 261175b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4q16oddPseudo: 261275b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4q32oddPseudo: 261375b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4q8oddPseudo_UPD: 261475b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4q16oddPseudo_UPD: 261575b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4q32oddPseudo_UPD: 261675b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1DUPq8Pseudo: 261775b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1DUPq16Pseudo: 261875b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1DUPq32Pseudo: 261975b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1DUPq8Pseudo_UPD: 262075b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1DUPq16Pseudo_UPD: 262175b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1DUPq32Pseudo_UPD: 262275b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2DUPd8Pseudo: 262375b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2DUPd16Pseudo: 262475b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2DUPd32Pseudo: 262575b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2DUPd8Pseudo_UPD: 262675b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2DUPd16Pseudo_UPD: 262775b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2DUPd32Pseudo_UPD: 262875b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4DUPd8Pseudo: 262975b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4DUPd16Pseudo: 263075b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4DUPd32Pseudo: 263175b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4DUPd8Pseudo_UPD: 263275b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4DUPd16Pseudo_UPD: 263375b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4DUPd32Pseudo_UPD: 263475b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1LNq8Pseudo: 263575b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1LNq16Pseudo: 263675b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1LNq32Pseudo: 263775b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1LNq8Pseudo_UPD: 263875b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1LNq16Pseudo_UPD: 263975b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1LNq32Pseudo_UPD: 264075b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2LNd8Pseudo: 264175b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2LNd16Pseudo: 264275b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2LNd32Pseudo: 264375b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2LNq16Pseudo: 264475b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2LNq32Pseudo: 264575b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2LNd8Pseudo_UPD: 264675b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2LNd16Pseudo_UPD: 264775b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2LNd32Pseudo_UPD: 264875b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2LNq16Pseudo_UPD: 264975b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2LNq32Pseudo_UPD: 265075b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4LNd8Pseudo: 265175b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4LNd16Pseudo: 265275b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4LNd32Pseudo: 265375b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4LNq16Pseudo: 265475b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4LNq32Pseudo: 265575b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4LNd8Pseudo_UPD: 265675b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4LNd16Pseudo_UPD: 265775b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4LNd32Pseudo_UPD: 265875b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4LNq16Pseudo_UPD: 265975b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4LNq32Pseudo_UPD: 266075b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng // If the address is not 64-bit aligned, the latencies of these 266175b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng // instructions increases by one. 266275b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng ++Latency; 266375b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng break; 266475b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng } 266575b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng 26667e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng return Latency; 2667a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng} 26682312842de0c641107dd04d7e056d02491cc781caEvan Cheng 26698239daf7c83a65a189c352cce3191cdc3bbfe151Evan Chengint ARMBaseInstrInfo::getInstrLatency(const InstrItineraryData *ItinData, 26708239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng const MachineInstr *MI, 26718239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng unsigned *PredCost) const { 26728239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng if (MI->isCopyLike() || MI->isInsertSubreg() || 26738239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng MI->isRegSequence() || MI->isImplicitDef()) 26748239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng return 1; 26758239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng 26768239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng if (!ItinData || ItinData->isEmpty()) 26778239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng return 1; 26788239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng 2679e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng const MCInstrDesc &MCID = MI->getDesc(); 2680e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng unsigned Class = MCID.getSchedClass(); 26818239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng unsigned UOps = ItinData->Itineraries[Class].NumMicroOps; 2682e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng if (PredCost && MCID.hasImplicitDefOfPhysReg(ARM::CPSR)) 26838239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng // When predicated, CPSR is an additional source operand for CPSR updating 26848239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng // instructions, this apparently increases their latencies. 26858239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng *PredCost = 1; 26868239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng if (UOps) 26878239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng return ItinData->getStageLatency(Class); 26888239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng return getNumMicroOps(ItinData, MI); 26898239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng} 26908239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng 26918239daf7c83a65a189c352cce3191cdc3bbfe151Evan Chengint ARMBaseInstrInfo::getInstrLatency(const InstrItineraryData *ItinData, 26928239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng SDNode *Node) const { 26938239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng if (!Node->isMachineOpcode()) 26948239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng return 1; 26958239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng 26968239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng if (!ItinData || ItinData->isEmpty()) 26978239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng return 1; 26988239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng 26998239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng unsigned Opcode = Node->getMachineOpcode(); 27008239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng switch (Opcode) { 27018239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng default: 27028239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng return ItinData->getStageLatency(get(Opcode).getSchedClass()); 270373fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMQIA: 270473fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMQIA: 27058239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng return 2; 27068b3ca6216d62bf3f729c2e122dcfeb7c4d7500dcEric Christopher } 27078239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng} 27088239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng 27092312842de0c641107dd04d7e056d02491cc781caEvan Chengbool ARMBaseInstrInfo:: 27102312842de0c641107dd04d7e056d02491cc781caEvan ChenghasHighOperandLatency(const InstrItineraryData *ItinData, 27112312842de0c641107dd04d7e056d02491cc781caEvan Cheng const MachineRegisterInfo *MRI, 27122312842de0c641107dd04d7e056d02491cc781caEvan Cheng const MachineInstr *DefMI, unsigned DefIdx, 27132312842de0c641107dd04d7e056d02491cc781caEvan Cheng const MachineInstr *UseMI, unsigned UseIdx) const { 27142312842de0c641107dd04d7e056d02491cc781caEvan Cheng unsigned DDomain = DefMI->getDesc().TSFlags & ARMII::DomainMask; 27152312842de0c641107dd04d7e056d02491cc781caEvan Cheng unsigned UDomain = UseMI->getDesc().TSFlags & ARMII::DomainMask; 27162312842de0c641107dd04d7e056d02491cc781caEvan Cheng if (Subtarget.isCortexA8() && 27172312842de0c641107dd04d7e056d02491cc781caEvan Cheng (DDomain == ARMII::DomainVFP || UDomain == ARMII::DomainVFP)) 27182312842de0c641107dd04d7e056d02491cc781caEvan Cheng // CortexA8 VFP instructions are not pipelined. 27192312842de0c641107dd04d7e056d02491cc781caEvan Cheng return true; 27202312842de0c641107dd04d7e056d02491cc781caEvan Cheng 27212312842de0c641107dd04d7e056d02491cc781caEvan Cheng // Hoist VFP / NEON instructions with 4 or higher latency. 27222312842de0c641107dd04d7e056d02491cc781caEvan Cheng int Latency = getOperandLatency(ItinData, DefMI, DefIdx, UseMI, UseIdx); 27232312842de0c641107dd04d7e056d02491cc781caEvan Cheng if (Latency <= 3) 27242312842de0c641107dd04d7e056d02491cc781caEvan Cheng return false; 27252312842de0c641107dd04d7e056d02491cc781caEvan Cheng return DDomain == ARMII::DomainVFP || DDomain == ARMII::DomainNEON || 27262312842de0c641107dd04d7e056d02491cc781caEvan Cheng UDomain == ARMII::DomainVFP || UDomain == ARMII::DomainNEON; 27272312842de0c641107dd04d7e056d02491cc781caEvan Cheng} 2728c8141dfc7f983cb04e65d8acd6bcbdc8e4b8a0aeEvan Cheng 2729c8141dfc7f983cb04e65d8acd6bcbdc8e4b8a0aeEvan Chengbool ARMBaseInstrInfo:: 2730c8141dfc7f983cb04e65d8acd6bcbdc8e4b8a0aeEvan ChenghasLowDefLatency(const InstrItineraryData *ItinData, 2731c8141dfc7f983cb04e65d8acd6bcbdc8e4b8a0aeEvan Cheng const MachineInstr *DefMI, unsigned DefIdx) const { 2732c8141dfc7f983cb04e65d8acd6bcbdc8e4b8a0aeEvan Cheng if (!ItinData || ItinData->isEmpty()) 2733c8141dfc7f983cb04e65d8acd6bcbdc8e4b8a0aeEvan Cheng return false; 2734c8141dfc7f983cb04e65d8acd6bcbdc8e4b8a0aeEvan Cheng 2735c8141dfc7f983cb04e65d8acd6bcbdc8e4b8a0aeEvan Cheng unsigned DDomain = DefMI->getDesc().TSFlags & ARMII::DomainMask; 2736c8141dfc7f983cb04e65d8acd6bcbdc8e4b8a0aeEvan Cheng if (DDomain == ARMII::DomainGeneral) { 2737c8141dfc7f983cb04e65d8acd6bcbdc8e4b8a0aeEvan Cheng unsigned DefClass = DefMI->getDesc().getSchedClass(); 2738c8141dfc7f983cb04e65d8acd6bcbdc8e4b8a0aeEvan Cheng int DefCycle = ItinData->getOperandCycle(DefClass, DefIdx); 2739c8141dfc7f983cb04e65d8acd6bcbdc8e4b8a0aeEvan Cheng return (DefCycle != -1 && DefCycle <= 2); 2740c8141dfc7f983cb04e65d8acd6bcbdc8e4b8a0aeEvan Cheng } 2741c8141dfc7f983cb04e65d8acd6bcbdc8e4b8a0aeEvan Cheng return false; 2742c8141dfc7f983cb04e65d8acd6bcbdc8e4b8a0aeEvan Cheng} 274348575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng 27443be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trickbool ARMBaseInstrInfo::verifyInstruction(const MachineInstr *MI, 27453be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick StringRef &ErrInfo) const { 27463be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick if (convertAddSubFlagsOpcode(MI->getOpcode())) { 27473be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick ErrInfo = "Pseudo flag setting opcodes only exist in Selection DAG"; 27483be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick return false; 27493be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick } 27503be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick return true; 27513be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick} 27523be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick 275348575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Chengbool 275448575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan ChengARMBaseInstrInfo::isFpMLxInstruction(unsigned Opcode, unsigned &MulOpc, 275548575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng unsigned &AddSubOpc, 275648575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng bool &NegAcc, bool &HasLane) const { 275748575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng DenseMap<unsigned, unsigned>::const_iterator I = MLxEntryMap.find(Opcode); 275848575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng if (I == MLxEntryMap.end()) 275948575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng return false; 276048575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng 276148575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng const ARM_MLxEntry &Entry = ARM_MLxTable[I->second]; 276248575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng MulOpc = Entry.MulOpc; 276348575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng AddSubOpc = Entry.AddSubOpc; 276448575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng NegAcc = Entry.NegAcc; 276548575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng HasLane = Entry.HasLane; 276648575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng return true; 276748575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng} 276813fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen 276913fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen//===----------------------------------------------------------------------===// 277013fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen// Execution domains. 277113fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen//===----------------------------------------------------------------------===// 277213fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen// 277313fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen// Some instructions go down the NEON pipeline, some go down the VFP pipeline, 277413fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen// and some can go down both. The vmov instructions go down the VFP pipeline, 277513fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen// but they can be changed to vorr equivalents that are executed by the NEON 277613fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen// pipeline. 277713fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen// 277813fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen// We use the following execution domain numbering: 277913fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen// 27808bb3d3cb30df06bdcb3ef5a208e3e59f4eeb4868Jakob Stoklund Olesenenum ARMExeDomain { 27818bb3d3cb30df06bdcb3ef5a208e3e59f4eeb4868Jakob Stoklund Olesen ExeGeneric = 0, 27828bb3d3cb30df06bdcb3ef5a208e3e59f4eeb4868Jakob Stoklund Olesen ExeVFP = 1, 27838bb3d3cb30df06bdcb3ef5a208e3e59f4eeb4868Jakob Stoklund Olesen ExeNEON = 2 27848bb3d3cb30df06bdcb3ef5a208e3e59f4eeb4868Jakob Stoklund Olesen}; 278513fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen// 278613fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen// Also see ARMInstrFormats.td and Domain* enums in ARMBaseInfo.h 278713fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen// 278813fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesenstd::pair<uint16_t, uint16_t> 278913fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund OlesenARMBaseInstrInfo::getExecutionDomain(const MachineInstr *MI) const { 279013fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen // VMOVD is a VFP instruction, but can be changed to NEON if it isn't 279113fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen // predicated. 279213fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen if (MI->getOpcode() == ARM::VMOVD && !isPredicated(MI)) 27938bb3d3cb30df06bdcb3ef5a208e3e59f4eeb4868Jakob Stoklund Olesen return std::make_pair(ExeVFP, (1<<ExeVFP) | (1<<ExeNEON)); 279413fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen 279513fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen // No other instructions can be swizzled, so just determine their domain. 279613fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen unsigned Domain = MI->getDesc().TSFlags & ARMII::DomainMask; 279713fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen 279813fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen if (Domain & ARMII::DomainNEON) 27998bb3d3cb30df06bdcb3ef5a208e3e59f4eeb4868Jakob Stoklund Olesen return std::make_pair(ExeNEON, 0); 280013fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen 280113fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen // Certain instructions can go either way on Cortex-A8. 280213fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen // Treat them as NEON instructions. 280313fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen if ((Domain & ARMII::DomainNEONA8) && Subtarget.isCortexA8()) 28048bb3d3cb30df06bdcb3ef5a208e3e59f4eeb4868Jakob Stoklund Olesen return std::make_pair(ExeNEON, 0); 280513fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen 280613fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen if (Domain & ARMII::DomainVFP) 28078bb3d3cb30df06bdcb3ef5a208e3e59f4eeb4868Jakob Stoklund Olesen return std::make_pair(ExeVFP, 0); 280813fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen 28098bb3d3cb30df06bdcb3ef5a208e3e59f4eeb4868Jakob Stoklund Olesen return std::make_pair(ExeGeneric, 0); 281013fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen} 281113fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen 281213fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesenvoid 281313fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund OlesenARMBaseInstrInfo::setExecutionDomain(MachineInstr *MI, unsigned Domain) const { 281413fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen // We only know how to change VMOVD into VORR. 281513fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen assert(MI->getOpcode() == ARM::VMOVD && "Can only swizzle VMOVD"); 28168bb3d3cb30df06bdcb3ef5a208e3e59f4eeb4868Jakob Stoklund Olesen if (Domain != ExeNEON) 281713fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen return; 281813fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen 28198bb3d3cb30df06bdcb3ef5a208e3e59f4eeb4868Jakob Stoklund Olesen // Zap the predicate operands. 28208bb3d3cb30df06bdcb3ef5a208e3e59f4eeb4868Jakob Stoklund Olesen assert(!isPredicated(MI) && "Cannot predicate a VORRd"); 28218bb3d3cb30df06bdcb3ef5a208e3e59f4eeb4868Jakob Stoklund Olesen MI->RemoveOperand(3); 28228bb3d3cb30df06bdcb3ef5a208e3e59f4eeb4868Jakob Stoklund Olesen MI->RemoveOperand(2); 28238bb3d3cb30df06bdcb3ef5a208e3e59f4eeb4868Jakob Stoklund Olesen 282413fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen // Change to a VORRd which requires two identical use operands. 282513fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen MI->setDesc(get(ARM::VORRd)); 28268bb3d3cb30df06bdcb3ef5a208e3e59f4eeb4868Jakob Stoklund Olesen 28278bb3d3cb30df06bdcb3ef5a208e3e59f4eeb4868Jakob Stoklund Olesen // Add the extra source operand and new predicates. 28288bb3d3cb30df06bdcb3ef5a208e3e59f4eeb4868Jakob Stoklund Olesen // This will go before any implicit ops. 28291c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen AddDefaultPred(MachineInstrBuilder(MI).addOperand(MI->getOperand(1))); 283013fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen} 2831