ARMBaseInstrInfo.cpp revision 22fee2dff4c43b551aefa44a96ca74fcade6bfac
131c24bf5b39cc8391d4cfdbf8cf5163975fdb81eJim Grosbach//===- ARMBaseInstrInfo.cpp - ARM Instruction Information -------*- C++ -*-===// 2334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// 3334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// The LLVM Compiler Infrastructure 4334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// 5334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// This file is distributed under the University of Illinois Open Source 6334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// License. See LICENSE.TXT for details. 7334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// 8334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin//===----------------------------------------------------------------------===// 9334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// 10334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// This file contains the Base ARM implementation of the TargetInstrInfo class. 11334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// 12334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin//===----------------------------------------------------------------------===// 13334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 14334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "ARMBaseInstrInfo.h" 15334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "ARM.h" 16334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "ARMAddressingModes.h" 17d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng#include "ARMConstantPoolValue.h" 1848575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng#include "ARMHazardRecognizer.h" 19334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "ARMMachineFunctionInfo.h" 20f95215f551949d5e5adfbf4753aa833b9009b77aAnton Korobeynikov#include "ARMRegisterInfo.h" 21fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng#include "llvm/Constants.h" 22fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng#include "llvm/Function.h" 23fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng#include "llvm/GlobalValue.h" 24334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "llvm/CodeGen/LiveVariables.h" 25d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng#include "llvm/CodeGen/MachineConstantPool.h" 26334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "llvm/CodeGen/MachineFrameInfo.h" 27334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "llvm/CodeGen/MachineInstrBuilder.h" 28334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "llvm/CodeGen/MachineJumpTableInfo.h" 29249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov#include "llvm/CodeGen/MachineMemOperand.h" 302457f2c66184e978d4ed8fa9e2128effff26cb0bEvan Cheng#include "llvm/CodeGen/MachineRegisterInfo.h" 31249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov#include "llvm/CodeGen/PseudoSourceValue.h" 32af76e592c7f9deff0e55c13dbb4a34f07f1c7f64Chris Lattner#include "llvm/MC/MCAsmInfo.h" 33334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "llvm/Support/CommandLine.h" 34f95215f551949d5e5adfbf4753aa833b9009b77aAnton Korobeynikov#include "llvm/Support/Debug.h" 35c25e7581b9b8088910da31702d4ca21c4734c6d7Torok Edwin#include "llvm/Support/ErrorHandling.h" 3640a5eb18b031fa1a5e9697e21e251e613d441cc5Bill Wendling#include "llvm/ADT/STLExtras.h" 3722fee2dff4c43b551aefa44a96ca74fcade6bfacEvan Cheng 3822fee2dff4c43b551aefa44a96ca74fcade6bfacEvan Cheng#define GET_INSTRINFO_MC_DESC 3922fee2dff4c43b551aefa44a96ca74fcade6bfacEvan Cheng#include "ARMGenInstrInfo.inc" 4022fee2dff4c43b551aefa44a96ca74fcade6bfacEvan Cheng 41334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinusing namespace llvm; 42334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 43334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinstatic cl::opt<bool> 44334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinEnableARM3Addr("enable-arm-3-addr-conv", cl::Hidden, 45334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin cl::desc("Enable ARM 2-addr to 3-addr conv")); 46334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 4748575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng/// ARM_MLxEntry - Record information about MLA / MLS instructions. 4848575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Chengstruct ARM_MLxEntry { 4948575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng unsigned MLxOpc; // MLA / MLS opcode 5048575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng unsigned MulOpc; // Expanded multiplication opcode 5148575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng unsigned AddSubOpc; // Expanded add / sub opcode 5248575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng bool NegAcc; // True if the acc is negated before the add / sub. 5348575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng bool HasLane; // True if instruction has an extra "lane" operand. 5448575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng}; 5548575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng 5648575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Chengstatic const ARM_MLxEntry ARM_MLxTable[] = { 5748575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng // MLxOpc, MulOpc, AddSubOpc, NegAcc, HasLane 5848575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng // fp scalar ops 5948575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng { ARM::VMLAS, ARM::VMULS, ARM::VADDS, false, false }, 6048575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng { ARM::VMLSS, ARM::VMULS, ARM::VSUBS, false, false }, 6148575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng { ARM::VMLAD, ARM::VMULD, ARM::VADDD, false, false }, 6248575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng { ARM::VMLSD, ARM::VMULD, ARM::VSUBD, false, false }, 6348575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng { ARM::VNMLAS, ARM::VNMULS, ARM::VSUBS, true, false }, 6448575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng { ARM::VNMLSS, ARM::VMULS, ARM::VSUBS, true, false }, 6548575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng { ARM::VNMLAD, ARM::VNMULD, ARM::VSUBD, true, false }, 6648575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng { ARM::VNMLSD, ARM::VMULD, ARM::VSUBD, true, false }, 6748575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng 6848575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng // fp SIMD ops 6948575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng { ARM::VMLAfd, ARM::VMULfd, ARM::VADDfd, false, false }, 7048575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng { ARM::VMLSfd, ARM::VMULfd, ARM::VSUBfd, false, false }, 7148575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng { ARM::VMLAfq, ARM::VMULfq, ARM::VADDfq, false, false }, 7248575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng { ARM::VMLSfq, ARM::VMULfq, ARM::VSUBfq, false, false }, 7348575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng { ARM::VMLAslfd, ARM::VMULslfd, ARM::VADDfd, false, true }, 7448575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng { ARM::VMLSslfd, ARM::VMULslfd, ARM::VSUBfd, false, true }, 7548575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng { ARM::VMLAslfq, ARM::VMULslfq, ARM::VADDfq, false, true }, 7648575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng { ARM::VMLSslfq, ARM::VMULslfq, ARM::VSUBfq, false, true }, 7748575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng}; 7848575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng 79f95215f551949d5e5adfbf4753aa833b9009b77aAnton KorobeynikovARMBaseInstrInfo::ARMBaseInstrInfo(const ARMSubtarget& STI) 80f95215f551949d5e5adfbf4753aa833b9009b77aAnton Korobeynikov : TargetInstrInfoImpl(ARMInsts, array_lengthof(ARMInsts)), 81f95215f551949d5e5adfbf4753aa833b9009b77aAnton Korobeynikov Subtarget(STI) { 8248575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng for (unsigned i = 0, e = array_lengthof(ARM_MLxTable); i != e; ++i) { 8348575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng if (!MLxEntryMap.insert(std::make_pair(ARM_MLxTable[i].MLxOpc, i)).second) 8448575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng assert(false && "Duplicated entries?"); 8548575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng MLxHazardOpcodes.insert(ARM_MLxTable[i].AddSubOpc); 8648575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng MLxHazardOpcodes.insert(ARM_MLxTable[i].MulOpc); 8748575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng } 8848575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng} 8948575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng 902da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick// Use a ScoreboardHazardRecognizer for prepass ARM scheduling. TargetInstrImpl 912da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick// currently defaults to no prepass hazard recognizer. 9248575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan ChengScheduleHazardRecognizer *ARMBaseInstrInfo:: 932da8bc8a5f7705ac131184cd247f48500da0d74eAndrew TrickCreateTargetHazardRecognizer(const TargetMachine *TM, 942da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick const ScheduleDAG *DAG) const { 95c8bfd1d78ff9a307d1d4cb57cce4549b538e60f4Andrew Trick if (usePreRAHazardRecognizer()) { 962da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick const InstrItineraryData *II = TM->getInstrItineraryData(); 972da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick return new ScoreboardHazardRecognizer(II, DAG, "pre-RA-sched"); 982da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick } 992da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick return TargetInstrInfoImpl::CreateTargetHazardRecognizer(TM, DAG); 1002da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick} 1012da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick 1022da8bc8a5f7705ac131184cd247f48500da0d74eAndrew TrickScheduleHazardRecognizer *ARMBaseInstrInfo:: 1032da8bc8a5f7705ac131184cd247f48500da0d74eAndrew TrickCreateTargetPostRAHazardRecognizer(const InstrItineraryData *II, 1042da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick const ScheduleDAG *DAG) const { 10548575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng if (Subtarget.isThumb2() || Subtarget.hasVFP2()) 10648575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng return (ScheduleHazardRecognizer *) 1072da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick new ARMHazardRecognizer(II, *this, getRegisterInfo(), Subtarget, DAG); 1082da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick return TargetInstrInfoImpl::CreateTargetPostRAHazardRecognizer(II, DAG); 109334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 110334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 111334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinMachineInstr * 112334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinARMBaseInstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI, 113334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineBasicBlock::iterator &MBBI, 114334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin LiveVariables *LV) const { 11578703ddafe3d037f75d8ca188e4829d238289ac3Evan Cheng // FIXME: Thumb2 support. 11678703ddafe3d037f75d8ca188e4829d238289ac3Evan Cheng 117334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (!EnableARM3Addr) 118334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return NULL; 119334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 120334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineInstr *MI = MBBI; 121334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineFunction &MF = *MI->getParent()->getParent(); 12299405df044f2c584242e711cc9023ec90356da82Bruno Cardoso Lopes uint64_t TSFlags = MI->getDesc().TSFlags; 123334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool isPre = false; 124334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin switch ((TSFlags & ARMII::IndexModeMask) >> ARMII::IndexModeShift) { 125334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin default: return NULL; 126334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMII::IndexModePre: 127334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin isPre = true; 128334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin break; 129334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMII::IndexModePost: 130334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin break; 131334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 132334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 133334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Try splitting an indexed load/store to an un-indexed one plus an add/sub 134334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // operation. 135334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned MemOpc = getUnindexedOpcode(MI->getOpcode()); 136334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (MemOpc == 0) 137334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return NULL; 138334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 139334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineInstr *UpdateMI = NULL; 140334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineInstr *MemMI = NULL; 141334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned AddrMode = (TSFlags & ARMII::AddrModeMask); 142e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng const MCInstrDesc &MCID = MI->getDesc(); 143e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng unsigned NumOps = MCID.getNumOperands(); 144e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng bool isLoad = !MCID.mayStore(); 145334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const MachineOperand &WB = isLoad ? MI->getOperand(1) : MI->getOperand(0); 146334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const MachineOperand &Base = MI->getOperand(2); 147334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const MachineOperand &Offset = MI->getOperand(NumOps-3); 148334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned WBReg = WB.getReg(); 149334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned BaseReg = Base.getReg(); 150334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned OffReg = Offset.getReg(); 151334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned OffImm = MI->getOperand(NumOps-2).getImm(); 152334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin ARMCC::CondCodes Pred = (ARMCC::CondCodes)MI->getOperand(NumOps-1).getImm(); 153334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin switch (AddrMode) { 154334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin default: 155334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin assert(false && "Unknown indexed op!"); 156334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return NULL; 157334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMII::AddrMode2: { 158334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool isSub = ARM_AM::getAM2Op(OffImm) == ARM_AM::sub; 159334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned Amt = ARM_AM::getAM2Offset(OffImm); 160334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (OffReg == 0) { 161e7cbe4118b7ddf05032ff8772a98c51e1637bb5cEvan Cheng if (ARM_AM::getSOImmVal(Amt) == -1) 162334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Can't encode it in a so_imm operand. This transformation will 163334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // add more than 1 instruction. Abandon! 164334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return NULL; 165334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin UpdateMI = BuildMI(MF, MI->getDebugLoc(), 16678703ddafe3d037f75d8ca188e4829d238289ac3Evan Cheng get(isSub ? ARM::SUBri : ARM::ADDri), WBReg) 167e7cbe4118b7ddf05032ff8772a98c51e1637bb5cEvan Cheng .addReg(BaseReg).addImm(Amt) 168334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addImm(Pred).addReg(0).addReg(0); 169334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } else if (Amt != 0) { 170334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin ARM_AM::ShiftOpc ShOpc = ARM_AM::getAM2ShiftOpc(OffImm); 171334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned SOOpc = ARM_AM::getSORegOpc(ShOpc, Amt); 172334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin UpdateMI = BuildMI(MF, MI->getDebugLoc(), 17378703ddafe3d037f75d8ca188e4829d238289ac3Evan Cheng get(isSub ? ARM::SUBrs : ARM::ADDrs), WBReg) 174334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(BaseReg).addReg(OffReg).addReg(0).addImm(SOOpc) 175334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addImm(Pred).addReg(0).addReg(0); 176334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } else 177334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin UpdateMI = BuildMI(MF, MI->getDebugLoc(), 17878703ddafe3d037f75d8ca188e4829d238289ac3Evan Cheng get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg) 179334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(BaseReg).addReg(OffReg) 180334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addImm(Pred).addReg(0).addReg(0); 181334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin break; 182334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 183334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMII::AddrMode3 : { 184334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool isSub = ARM_AM::getAM3Op(OffImm) == ARM_AM::sub; 185334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned Amt = ARM_AM::getAM3Offset(OffImm); 186334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (OffReg == 0) 187334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Immediate is 8-bits. It's guaranteed to fit in a so_imm operand. 188334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin UpdateMI = BuildMI(MF, MI->getDebugLoc(), 18978703ddafe3d037f75d8ca188e4829d238289ac3Evan Cheng get(isSub ? ARM::SUBri : ARM::ADDri), WBReg) 190334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(BaseReg).addImm(Amt) 191334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addImm(Pred).addReg(0).addReg(0); 192334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin else 193334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin UpdateMI = BuildMI(MF, MI->getDebugLoc(), 19478703ddafe3d037f75d8ca188e4829d238289ac3Evan Cheng get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg) 195334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(BaseReg).addReg(OffReg) 196334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addImm(Pred).addReg(0).addReg(0); 197334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin break; 198334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 199334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 200334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 201334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin std::vector<MachineInstr*> NewMIs; 202334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (isPre) { 203334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (isLoad) 204334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MemMI = BuildMI(MF, MI->getDebugLoc(), 205334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin get(MemOpc), MI->getOperand(0).getReg()) 2063e5561247202bae994dd259a2d8dc4eff8f799f3Jim Grosbach .addReg(WBReg).addImm(0).addImm(Pred); 207334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin else 208334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MemMI = BuildMI(MF, MI->getDebugLoc(), 209334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin get(MemOpc)).addReg(MI->getOperand(1).getReg()) 210334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(WBReg).addReg(0).addImm(0).addImm(Pred); 211334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin NewMIs.push_back(MemMI); 212334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin NewMIs.push_back(UpdateMI); 213334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } else { 214334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (isLoad) 215334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MemMI = BuildMI(MF, MI->getDebugLoc(), 216334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin get(MemOpc), MI->getOperand(0).getReg()) 2173e5561247202bae994dd259a2d8dc4eff8f799f3Jim Grosbach .addReg(BaseReg).addImm(0).addImm(Pred); 218334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin else 219334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MemMI = BuildMI(MF, MI->getDebugLoc(), 220334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin get(MemOpc)).addReg(MI->getOperand(1).getReg()) 221334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred); 222334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (WB.isDead()) 223334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin UpdateMI->getOperand(0).setIsDead(); 224334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin NewMIs.push_back(UpdateMI); 225334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin NewMIs.push_back(MemMI); 226334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 227334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 228334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Transfer LiveVariables states, kill / dead info. 229334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (LV) { 230334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 231334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineOperand &MO = MI->getOperand(i); 232c9df025e33ac435adb3b3318d237c36ca7cec659Jakob Stoklund Olesen if (MO.isReg() && TargetRegisterInfo::isVirtualRegister(MO.getReg())) { 233334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned Reg = MO.getReg(); 234334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 235334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin LiveVariables::VarInfo &VI = LV->getVarInfo(Reg); 236334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (MO.isDef()) { 237334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineInstr *NewMI = (Reg == WBReg) ? UpdateMI : MemMI; 238334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (MO.isDead()) 239334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin LV->addVirtualRegisterDead(Reg, NewMI); 240334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 241334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (MO.isUse() && MO.isKill()) { 242334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin for (unsigned j = 0; j < 2; ++j) { 243334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Look at the two new MI's in reverse order. 244334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineInstr *NewMI = NewMIs[j]; 245334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (!NewMI->readsRegister(Reg)) 246334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin continue; 247334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin LV->addVirtualRegisterKilled(Reg, NewMI); 248334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (VI.removeKill(MI)) 249334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin VI.Kills.push_back(NewMI); 250334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin break; 251334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 252334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 253334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 254334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 255334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 256334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 257334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MFI->insert(MBBI, NewMIs[1]); 258334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MFI->insert(MBBI, NewMIs[0]); 259334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return NewMIs[0]; 260334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 261334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 262334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// Branch analysis. 263334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinbool 264334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinARMBaseInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB, 265334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineBasicBlock *&FBB, 266334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin SmallVectorImpl<MachineOperand> &Cond, 267334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool AllowModify) const { 268334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // If the block has no terminators, it just falls into the block after it. 269334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineBasicBlock::iterator I = MBB.end(); 27093d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen if (I == MBB.begin()) 27193d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen return false; 27293d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen --I; 27393d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen while (I->isDebugValue()) { 27493d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen if (I == MBB.begin()) 27593d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen return false; 27693d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen --I; 27793d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen } 27893d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen if (!isUnpredicatedTerminator(I)) 279334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 280334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 281334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Get the last instruction in the block. 282334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineInstr *LastInst = I; 283334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 284334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // If there is only one terminator instruction, process it. 285334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned LastOpc = LastInst->getOpcode(); 286334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) { 2875ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng if (isUncondBranchOpcode(LastOpc)) { 288334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin TBB = LastInst->getOperand(0).getMBB(); 289334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 290334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 2915ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng if (isCondBranchOpcode(LastOpc)) { 292334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Block ends with fall-through condbranch. 293334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin TBB = LastInst->getOperand(0).getMBB(); 294334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin Cond.push_back(LastInst->getOperand(1)); 295334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin Cond.push_back(LastInst->getOperand(2)); 296334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 297334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 298334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; // Can't handle indirect branch. 299334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 300334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 301334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Get the instruction before it if it is a terminator. 302334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineInstr *SecondLastInst = I; 303108c8724663354050dc09bb1262c3e4511adf82fEvan Cheng unsigned SecondLastOpc = SecondLastInst->getOpcode(); 304108c8724663354050dc09bb1262c3e4511adf82fEvan Cheng 305108c8724663354050dc09bb1262c3e4511adf82fEvan Cheng // If AllowModify is true and the block ends with two or more unconditional 306108c8724663354050dc09bb1262c3e4511adf82fEvan Cheng // branches, delete all but the first unconditional branch. 307108c8724663354050dc09bb1262c3e4511adf82fEvan Cheng if (AllowModify && isUncondBranchOpcode(LastOpc)) { 308108c8724663354050dc09bb1262c3e4511adf82fEvan Cheng while (isUncondBranchOpcode(SecondLastOpc)) { 309108c8724663354050dc09bb1262c3e4511adf82fEvan Cheng LastInst->eraseFromParent(); 310108c8724663354050dc09bb1262c3e4511adf82fEvan Cheng LastInst = SecondLastInst; 311108c8724663354050dc09bb1262c3e4511adf82fEvan Cheng LastOpc = LastInst->getOpcode(); 312676e258366dd17a0b4ee6ac66914237ce181202eEvan Cheng if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) { 313676e258366dd17a0b4ee6ac66914237ce181202eEvan Cheng // Return now the only terminator is an unconditional branch. 314676e258366dd17a0b4ee6ac66914237ce181202eEvan Cheng TBB = LastInst->getOperand(0).getMBB(); 315676e258366dd17a0b4ee6ac66914237ce181202eEvan Cheng return false; 316676e258366dd17a0b4ee6ac66914237ce181202eEvan Cheng } else { 317108c8724663354050dc09bb1262c3e4511adf82fEvan Cheng SecondLastInst = I; 318108c8724663354050dc09bb1262c3e4511adf82fEvan Cheng SecondLastOpc = SecondLastInst->getOpcode(); 319108c8724663354050dc09bb1262c3e4511adf82fEvan Cheng } 320108c8724663354050dc09bb1262c3e4511adf82fEvan Cheng } 321108c8724663354050dc09bb1262c3e4511adf82fEvan Cheng } 322334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 323334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // If there are three terminators, we don't know what sort of block this is. 324334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(--I)) 325334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; 326334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 3275ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng // If the block ends with a B and a Bcc, handle it. 3285ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng if (isCondBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) { 329334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin TBB = SecondLastInst->getOperand(0).getMBB(); 330334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin Cond.push_back(SecondLastInst->getOperand(1)); 331334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin Cond.push_back(SecondLastInst->getOperand(2)); 332334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin FBB = LastInst->getOperand(0).getMBB(); 333334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 334334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 335334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 336334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // If the block ends with two unconditional branches, handle it. The second 337334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // one is not executed, so remove it. 3385ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng if (isUncondBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) { 339334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin TBB = SecondLastInst->getOperand(0).getMBB(); 340334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin I = LastInst; 341334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (AllowModify) 342334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin I->eraseFromParent(); 343334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 344334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 345334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 346334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // ...likewise if it ends with a branch table followed by an unconditional 347334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // branch. The branch folder can create these, and we must get rid of them for 348334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // correctness of Thumb constant islands. 3498d4de5abfa1bcd974554ea14904ebf7af289e84dBob Wilson if ((isJumpTableBranchOpcode(SecondLastOpc) || 3508d4de5abfa1bcd974554ea14904ebf7af289e84dBob Wilson isIndirectBranchOpcode(SecondLastOpc)) && 3515ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng isUncondBranchOpcode(LastOpc)) { 352334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin I = LastInst; 353334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (AllowModify) 354334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin I->eraseFromParent(); 355334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; 356334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 357334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 358334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Otherwise, can't handle this. 359334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; 360334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 361334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 362334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 363334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinunsigned ARMBaseInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const { 364334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineBasicBlock::iterator I = MBB.end(); 365334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (I == MBB.begin()) return 0; 366334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin --I; 36793d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen while (I->isDebugValue()) { 36893d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen if (I == MBB.begin()) 36993d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen return 0; 37093d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen --I; 37193d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen } 3725ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng if (!isUncondBranchOpcode(I->getOpcode()) && 3735ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng !isCondBranchOpcode(I->getOpcode())) 374334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 0; 375334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 376334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Remove the branch. 377334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin I->eraseFromParent(); 378334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 379334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin I = MBB.end(); 380334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 381334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (I == MBB.begin()) return 1; 382334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin --I; 3835ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng if (!isCondBranchOpcode(I->getOpcode())) 384334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 1; 385334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 386334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Remove the branch. 387334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin I->eraseFromParent(); 388334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 2; 389334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 390334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 391334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinunsigned 392334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinARMBaseInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 3933bf912593301152b65accb9d9c37a95172f1df5aStuart Hastings MachineBasicBlock *FBB, 3943bf912593301152b65accb9d9c37a95172f1df5aStuart Hastings const SmallVectorImpl<MachineOperand> &Cond, 3953bf912593301152b65accb9d9c37a95172f1df5aStuart Hastings DebugLoc DL) const { 3966495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ARMFunctionInfo *AFI = MBB.getParent()->getInfo<ARMFunctionInfo>(); 3976495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng int BOpc = !AFI->isThumbFunction() 3986495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ? ARM::B : (AFI->isThumb2Function() ? ARM::t2B : ARM::tB); 3996495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng int BccOpc = !AFI->isThumbFunction() 4006495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ? ARM::Bcc : (AFI->isThumb2Function() ? ARM::t2Bcc : ARM::tBcc); 401334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 402334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Shouldn't be a fall through. 403334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin assert(TBB && "InsertBranch must not be told to insert a fallthrough"); 404334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin assert((Cond.size() == 2 || Cond.size() == 0) && 405334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin "ARM branch conditions have two components!"); 406334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 407334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (FBB == 0) { 408334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (Cond.empty()) // Unconditional branch? 4093bf912593301152b65accb9d9c37a95172f1df5aStuart Hastings BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB); 410334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin else 4113bf912593301152b65accb9d9c37a95172f1df5aStuart Hastings BuildMI(&MBB, DL, get(BccOpc)).addMBB(TBB) 412334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()); 413334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 1; 414334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 415334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 416334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Two-way conditional branch. 4173bf912593301152b65accb9d9c37a95172f1df5aStuart Hastings BuildMI(&MBB, DL, get(BccOpc)).addMBB(TBB) 418334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()); 4193bf912593301152b65accb9d9c37a95172f1df5aStuart Hastings BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB); 420334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 2; 421334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 422334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 423334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinbool ARMBaseInstrInfo:: 424334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const { 425334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin ARMCC::CondCodes CC = (ARMCC::CondCodes)(int)Cond[0].getImm(); 426334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin Cond[0].setImm(ARMCC::getOppositeCondition(CC)); 427334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 428334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 429334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 430334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinbool ARMBaseInstrInfo:: 431334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinPredicateInstruction(MachineInstr *MI, 432334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const SmallVectorImpl<MachineOperand> &Pred) const { 433334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned Opc = MI->getOpcode(); 4345ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng if (isUncondBranchOpcode(Opc)) { 4355ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng MI->setDesc(get(getMatchingCondBranchOpcode(Opc))); 436334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI->addOperand(MachineOperand::CreateImm(Pred[0].getImm())); 437334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI->addOperand(MachineOperand::CreateReg(Pred[1].getReg(), false)); 438334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; 439334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 440334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 441334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin int PIdx = MI->findFirstPredOperandIdx(); 442334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (PIdx != -1) { 443334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineOperand &PMO = MI->getOperand(PIdx); 444334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin PMO.setImm(Pred[0].getImm()); 445334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI->getOperand(PIdx+1).setReg(Pred[1].getReg()); 446334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; 447334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 448334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 449334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 450334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 451334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinbool ARMBaseInstrInfo:: 452334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinSubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1, 453334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const SmallVectorImpl<MachineOperand> &Pred2) const { 454334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (Pred1.size() > 2 || Pred2.size() > 2) 455334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 456334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 457334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin ARMCC::CondCodes CC1 = (ARMCC::CondCodes)Pred1[0].getImm(); 458334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin ARMCC::CondCodes CC2 = (ARMCC::CondCodes)Pred2[0].getImm(); 459334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (CC1 == CC2) 460334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; 461334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 462334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin switch (CC1) { 463334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin default: 464334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 465334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMCC::AL: 466334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; 467334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMCC::HS: 468334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return CC2 == ARMCC::HI; 469334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMCC::LS: 470334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return CC2 == ARMCC::LO || CC2 == ARMCC::EQ; 471334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMCC::GE: 472334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return CC2 == ARMCC::GT; 473334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMCC::LE: 474334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return CC2 == ARMCC::LT; 475334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 476334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 477334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 478334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinbool ARMBaseInstrInfo::DefinesPredicate(MachineInstr *MI, 479334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin std::vector<MachineOperand> &Pred) const { 4808fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng // FIXME: This confuses implicit_def with optional CPSR def. 481e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng const MCInstrDesc &MCID = MI->getDesc(); 482e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng if (!MCID.getImplicitDefs() && !MCID.hasOptionalDef()) 483334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 484334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 485334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool Found = false; 486334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 487334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const MachineOperand &MO = MI->getOperand(i); 488334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (MO.isReg() && MO.getReg() == ARM::CPSR) { 489334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin Pred.push_back(MO); 490334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin Found = true; 491334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 492334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 493334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 494334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return Found; 495334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 496334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 497ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng/// isPredicable - Return true if the specified instruction can be predicated. 498ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng/// By default, this returns true for every instruction with a 499ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng/// PredicateOperand. 500ac0869dc8a7986855c5557cc67d4709600158ef5Evan Chengbool ARMBaseInstrInfo::isPredicable(MachineInstr *MI) const { 501e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng const MCInstrDesc &MCID = MI->getDesc(); 502e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng if (!MCID.isPredicable()) 503ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng return false; 504ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng 505e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng if ((MCID.TSFlags & ARMII::DomainMask) == ARMII::DomainNEON) { 506ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng ARMFunctionInfo *AFI = 507ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng MI->getParent()->getParent()->getInfo<ARMFunctionInfo>(); 508d7f0810c934a7d13acb28c42d737ce58ec990ea8Evan Cheng return AFI->isThumb2Function(); 509ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng } 510ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng return true; 511ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng} 512334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 51356856b1f46ec1f073ceef4e826c544b8b1691608Chris Lattner/// FIXME: Works around a gcc miscompilation with -fstrict-aliasing. 51419e57025d458d3cb50804fd821fd89b868a819bdChandler CarruthLLVM_ATTRIBUTE_NOINLINE 515334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinstatic unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT, 51656856b1f46ec1f073ceef4e826c544b8b1691608Chris Lattner unsigned JTI); 517334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinstatic unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT, 518334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned JTI) { 51956856b1f46ec1f073ceef4e826c544b8b1691608Chris Lattner assert(JTI < JT.size()); 520334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return JT[JTI].MBBs.size(); 521334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 522334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 523334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin/// GetInstSize - Return the size of the specified MachineInstr. 524334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin/// 525334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinunsigned ARMBaseInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const { 526334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const MachineBasicBlock &MBB = *MI->getParent(); 527334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const MachineFunction *MF = MBB.getParent(); 52833adcfb4d217f5f23d9bde8ba02b8e48f9605fc5Chris Lattner const MCAsmInfo *MAI = MF->getTarget().getMCAsmInfo(); 529334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 530334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Basic size info comes from the TSFlags field. 531e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng const MCInstrDesc &MCID = MI->getDesc(); 532e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng uint64_t TSFlags = MCID.TSFlags; 533334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 534a0ee862f2e3a0d202244e02459ddcf0dca0e8607Evan Cheng unsigned Opc = MI->getOpcode(); 535334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin switch ((TSFlags & ARMII::SizeMask) >> ARMII::SizeShift) { 536334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin default: { 537334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // If this machine instr is an inline asm, measure it. 538334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (MI->getOpcode() == ARM::INLINEASM) 53933adcfb4d217f5f23d9bde8ba02b8e48f9605fc5Chris Lattner return getInlineAsmLength(MI->getOperand(0).getSymbolName(), *MAI); 540334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (MI->isLabel()) 541334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 0; 542a0ee862f2e3a0d202244e02459ddcf0dca0e8607Evan Cheng switch (Opc) { 543334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin default: 544c23197a26f34f559ea9797de51e187087c039c42Torok Edwin llvm_unreachable("Unknown or unset size field for instr!"); 545518bb53485df640d7b7e3f6b0544099020c42aa7Chris Lattner case TargetOpcode::IMPLICIT_DEF: 546518bb53485df640d7b7e3f6b0544099020c42aa7Chris Lattner case TargetOpcode::KILL: 5477431beaba2a01c3fe299c861b2ec85cbf1dc81c4Bill Wendling case TargetOpcode::PROLOG_LABEL: 548518bb53485df640d7b7e3f6b0544099020c42aa7Chris Lattner case TargetOpcode::EH_LABEL: 549375be7730a6f3dee7a6dc319ee6c355a11ac99adDale Johannesen case TargetOpcode::DBG_VALUE: 550334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 0; 551334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 552334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin break; 553334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 554789476240d6b6f8ad9366cadf790a82bd41bb0b3Evan Cheng case ARMII::Size8Bytes: return 8; // ARM instruction x 2. 555789476240d6b6f8ad9366cadf790a82bd41bb0b3Evan Cheng case ARMII::Size4Bytes: return 4; // ARM / Thumb2 instruction. 556789476240d6b6f8ad9366cadf790a82bd41bb0b3Evan Cheng case ARMII::Size2Bytes: return 2; // Thumb1 instruction. 557334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMII::SizeSpecial: { 558a0ee862f2e3a0d202244e02459ddcf0dca0e8607Evan Cheng switch (Opc) { 55953519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng case ARM::MOVi16_ga_pcrel: 56053519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng case ARM::MOVTi16_ga_pcrel: 56153519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng case ARM::t2MOVi16_ga_pcrel: 56253519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng case ARM::t2MOVTi16_ga_pcrel: 5635de5d4b6d0eb3fd379fa571d82f6fa764460b3b8Evan Cheng return 4; 5643c38f96af2a5443d9f72fd078c2c98dd08746e51Jim Grosbach case ARM::MOVi32imm: 5653c38f96af2a5443d9f72fd078c2c98dd08746e51Jim Grosbach case ARM::t2MOVi32imm: 5663c38f96af2a5443d9f72fd078c2c98dd08746e51Jim Grosbach return 8; 567334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARM::CONSTPOOL_ENTRY: 568334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // If this machine instr is a constant pool entry, its size is recorded as 569334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // operand #2. 570334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return MI->getOperand(2).getImm(); 5715eb195153950bc7ebfc30649494a78b2096b5ef8Jim Grosbach case ARM::Int_eh_sjlj_longjmp: 5725eb195153950bc7ebfc30649494a78b2096b5ef8Jim Grosbach return 16; 5735eb195153950bc7ebfc30649494a78b2096b5ef8Jim Grosbach case ARM::tInt_eh_sjlj_longjmp: 5745eb195153950bc7ebfc30649494a78b2096b5ef8Jim Grosbach return 10; 575789476240d6b6f8ad9366cadf790a82bd41bb0b3Evan Cheng case ARM::Int_eh_sjlj_setjmp: 576d100755bab38784703f677b8b8eb174b624b346bJim Grosbach case ARM::Int_eh_sjlj_setjmp_nofp: 5770798eddd07b8dc827a4e6e9028c4c3a8d9444286Jim Grosbach return 20; 578d122874996a6faa8832569b632fd73a32ace7ae7Jim Grosbach case ARM::tInt_eh_sjlj_setjmp: 5795aa1684e5da9a85286bf7d29da419d261a70c2f2Jim Grosbach case ARM::t2Int_eh_sjlj_setjmp: 580d100755bab38784703f677b8b8eb174b624b346bJim Grosbach case ARM::t2Int_eh_sjlj_setjmp_nofp: 5810798eddd07b8dc827a4e6e9028c4c3a8d9444286Jim Grosbach return 12; 582334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARM::BR_JTr: 583334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARM::BR_JTm: 584334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARM::BR_JTadd: 585a0ee862f2e3a0d202244e02459ddcf0dca0e8607Evan Cheng case ARM::tBR_JTr: 586d26b14c34cbcee1448b86b524578fc51cc979023Evan Cheng case ARM::t2BR_JT: 587d092a87ba3f905a6801a0bdf816267329cf0391cJim Grosbach case ARM::t2TBB_JT: 588d092a87ba3f905a6801a0bdf816267329cf0391cJim Grosbach case ARM::t2TBH_JT: { 589334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // These are jumptable branches, i.e. a branch followed by an inlined 590d26b14c34cbcee1448b86b524578fc51cc979023Evan Cheng // jumptable. The size is 4 + 4 * number of entries. For TBB, each 591d26b14c34cbcee1448b86b524578fc51cc979023Evan Cheng // entry is one byte; TBH two byte each. 592d092a87ba3f905a6801a0bdf816267329cf0391cJim Grosbach unsigned EntrySize = (Opc == ARM::t2TBB_JT) 593d092a87ba3f905a6801a0bdf816267329cf0391cJim Grosbach ? 1 : ((Opc == ARM::t2TBH_JT) ? 2 : 4); 594e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng unsigned NumOps = MCID.getNumOperands(); 595334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineOperand JTOP = 596e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng MI->getOperand(NumOps - (MCID.isPredicable() ? 3 : 2)); 597334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned JTI = JTOP.getIndex(); 598334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo(); 599b1e803985d3378538ae9cff7eed4102c002d1e22Chris Lattner assert(MJTI != 0); 600334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables(); 601334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin assert(JTI < JT.size()); 602334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Thumb instructions are 2 byte aligned, but JT entries are 4 byte 603334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // 4 aligned. The assembler / linker may add 2 byte padding just before 604334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // the JT entries. The size does not include this padding; the 605334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // constant islands pass does separate bookkeeping for it. 606334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // FIXME: If we know the size of the function is less than (1 << 16) *2 607334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // bytes, we can use 16-bit entries instead. Then there won't be an 608334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // alignment issue. 60925f7cfc3cccba6f569f29f79ea533bae960b93c0Evan Cheng unsigned InstSize = (Opc == ARM::tBR_JTr || Opc == ARM::t2BR_JT) ? 2 : 4; 61025f7cfc3cccba6f569f29f79ea533bae960b93c0Evan Cheng unsigned NumEntries = getNumJTEntries(JT, JTI); 611d092a87ba3f905a6801a0bdf816267329cf0391cJim Grosbach if (Opc == ARM::t2TBB_JT && (NumEntries & 1)) 61225f7cfc3cccba6f569f29f79ea533bae960b93c0Evan Cheng // Make sure the instruction that follows TBB is 2-byte aligned. 61325f7cfc3cccba6f569f29f79ea533bae960b93c0Evan Cheng // FIXME: Constant island pass should insert an "ALIGN" instruction 61425f7cfc3cccba6f569f29f79ea533bae960b93c0Evan Cheng // instead. 61525f7cfc3cccba6f569f29f79ea533bae960b93c0Evan Cheng ++NumEntries; 61625f7cfc3cccba6f569f29f79ea533bae960b93c0Evan Cheng return NumEntries * EntrySize + InstSize; 617334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 618334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin default: 619334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Otherwise, pseudo-instruction sizes are zero. 620334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 0; 621334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 622334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 623334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 624334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 0; // Not reached 625334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 626334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 627ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesenvoid ARMBaseInstrInfo::copyPhysReg(MachineBasicBlock &MBB, 628ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen MachineBasicBlock::iterator I, DebugLoc DL, 629ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen unsigned DestReg, unsigned SrcReg, 630ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen bool KillSrc) const { 631ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen bool GPRDest = ARM::GPRRegClass.contains(DestReg); 632ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen bool GPRSrc = ARM::GPRRegClass.contains(SrcReg); 633ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen 634ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen if (GPRDest && GPRSrc) { 635ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen AddDefaultCC(AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::MOVr), DestReg) 636ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen .addReg(SrcReg, getKillRegState(KillSrc)))); 637ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen return; 6387bfdca0206f51132b26094c6f83a5ac97ee0f943David Goodwin } 639334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 640ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen bool SPRDest = ARM::SPRRegClass.contains(DestReg); 641ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen bool SPRSrc = ARM::SPRRegClass.contains(SrcReg); 642ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen 643ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen unsigned Opc; 644ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen if (SPRDest && SPRSrc) 645ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen Opc = ARM::VMOVS; 646ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen else if (GPRDest && SPRSrc) 647ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen Opc = ARM::VMOVRS; 648ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen else if (SPRDest && GPRSrc) 649ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen Opc = ARM::VMOVSR; 650ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen else if (ARM::DPRRegClass.contains(DestReg, SrcReg)) 651ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen Opc = ARM::VMOVD; 652ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen else if (ARM::QPRRegClass.contains(DestReg, SrcReg)) 653ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen Opc = ARM::VMOVQ; 654ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen else if (ARM::QQPRRegClass.contains(DestReg, SrcReg)) 655ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen Opc = ARM::VMOVQQ; 656ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen else if (ARM::QQQQPRRegClass.contains(DestReg, SrcReg)) 657ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen Opc = ARM::VMOVQQQQ; 658ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen else 659ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen llvm_unreachable("Impossible reg-to-reg copy"); 660ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen 661ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc), DestReg); 662ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen MIB.addReg(SrcReg, getKillRegState(KillSrc)); 663ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen if (Opc != ARM::VMOVQQ && Opc != ARM::VMOVQQQQ) 664ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen AddDefaultPred(MIB); 665334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 666334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 667c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Chengstatic const 668c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan ChengMachineInstrBuilder &AddDReg(MachineInstrBuilder &MIB, 669c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Cheng unsigned Reg, unsigned SubIdx, unsigned State, 670c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Cheng const TargetRegisterInfo *TRI) { 671c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Cheng if (!SubIdx) 672c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Cheng return MIB.addReg(Reg, State); 673c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Cheng 674c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Cheng if (TargetRegisterInfo::isPhysicalRegister(Reg)) 675c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Cheng return MIB.addReg(TRI->getSubReg(Reg, SubIdx), State); 676c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Cheng return MIB.addReg(Reg, State, SubIdx); 677c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Cheng} 678c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Cheng 679334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinvoid ARMBaseInstrInfo:: 680334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinstoreRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 681334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned SrcReg, bool isKill, int FI, 682746ad69e088176819981b4b2c5ac8dcd49f5e60eEvan Cheng const TargetRegisterClass *RC, 683746ad69e088176819981b4b2c5ac8dcd49f5e60eEvan Cheng const TargetRegisterInfo *TRI) const { 684c7f3ace20c325521c68335a1689645b43b06ddf0Chris Lattner DebugLoc DL; 685334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (I != MBB.end()) DL = I->getDebugLoc(); 686249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MachineFunction &MF = *MBB.getParent(); 687249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MachineFrameInfo &MFI = *MF.getFrameInfo(); 68831bc849123011b8eae6bb3c79876d9a3c26a6a1dJim Grosbach unsigned Align = MFI.getObjectAlignment(FI); 689249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov 690249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MachineMemOperand *MMO = 69159db5496f4fc2ef6111569e542f8b65480ef14c1Chris Lattner MF.getMachineMemOperand(MachinePointerInfo( 69259db5496f4fc2ef6111569e542f8b65480ef14c1Chris Lattner PseudoSourceValue::getFixedStack(FI)), 69359db5496f4fc2ef6111569e542f8b65480ef14c1Chris Lattner MachineMemOperand::MOStore, 694249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MFI.getObjectSize(FI), 69531bc849123011b8eae6bb3c79876d9a3c26a6a1dJim Grosbach Align); 696334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 6970eb0c7401c34c0b4604f732ce54db995eead14e6Bob Wilson // tGPR is used sometimes in ARM instructions that need to avoid using 6986ccfc507dc1f7ad8c8964193a2407264ca644f0dJim Grosbach // certain registers. Just treat it as GPR here. Likewise, rGPR. 6996ccfc507dc1f7ad8c8964193a2407264ca644f0dJim Grosbach if (RC == ARM::tGPRRegisterClass || RC == ARM::tcGPRRegisterClass 7006ccfc507dc1f7ad8c8964193a2407264ca644f0dJim Grosbach || RC == ARM::rGPRRegisterClass) 7010eb0c7401c34c0b4604f732ce54db995eead14e6Bob Wilson RC = ARM::GPRRegisterClass; 7020eb0c7401c34c0b4604f732ce54db995eead14e6Bob Wilson 703ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson switch (RC->getID()) { 704ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson case ARM::GPRRegClassID: 7057e3383c007f53b3a00675af225e428cb66ddf404Jim Grosbach AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::STRi12)) 706334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(SrcReg, getKillRegState(isKill)) 7077e3383c007f53b3a00675af225e428cb66ddf404Jim Grosbach .addFrameIndex(FI).addImm(0).addMemOperand(MMO)); 708ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson break; 709ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson case ARM::SPRRegClassID: 710d31c5496d7e1580058b5c6fbc8fd537a641ea590Evan Cheng AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTRS)) 711d31c5496d7e1580058b5c6fbc8fd537a641ea590Evan Cheng .addReg(SrcReg, getKillRegState(isKill)) 712d31c5496d7e1580058b5c6fbc8fd537a641ea590Evan Cheng .addFrameIndex(FI).addImm(0).addMemOperand(MMO)); 713ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson break; 714ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson case ARM::DPRRegClassID: 715ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson case ARM::DPR_VFP2RegClassID: 716ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson case ARM::DPR_8RegClassID: 717e5165490b7ba24bb2f3043399e0d60e7f3bcf8a5Jim Grosbach AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTRD)) 718334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(SrcReg, getKillRegState(isKill)) 719249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov .addFrameIndex(FI).addImm(0).addMemOperand(MMO)); 720ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson break; 721ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson case ARM::QPRRegClassID: 722ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson case ARM::QPR_VFP2RegClassID: 723ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson case ARM::QPR_8RegClassID: 7240cfcf93c95af91e809ef740eb0ab368477226b40Jim Grosbach if (Align >= 16 && getRegisterInfo().needsStackRealignment(MF)) { 725168f382dc67e5940cabdb28dc933c4f91cdd3137Bob Wilson AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1q64Pseudo)) 726f967ca0eaf30325cabe3c1971bf0dba16cf1b027Bob Wilson .addFrameIndex(FI).addImm(16) 72769b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng .addReg(SrcReg, getKillRegState(isKill)) 72869b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng .addMemOperand(MMO)); 72931bc849123011b8eae6bb3c79876d9a3c26a6a1dJim Grosbach } else { 73073fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMQIA)) 73169b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng .addReg(SrcReg, getKillRegState(isKill)) 73269b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng .addFrameIndex(FI) 73369b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng .addMemOperand(MMO)); 73431bc849123011b8eae6bb3c79876d9a3c26a6a1dJim Grosbach } 735ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson break; 736ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson case ARM::QQPRRegClassID: 737ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson case ARM::QQPR_VFP2RegClassID: 738435d4991779d6a47cadff4ea670b490d8507d6c4Evan Cheng if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) { 73922c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng // FIXME: It's possible to only store part of the QQ register if the 74022c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng // spilled def has a sub-register index. 741168f382dc67e5940cabdb28dc933c4f91cdd3137Bob Wilson AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1d64QPseudo)) 742168f382dc67e5940cabdb28dc933c4f91cdd3137Bob Wilson .addFrameIndex(FI).addImm(16) 743168f382dc67e5940cabdb28dc933c4f91cdd3137Bob Wilson .addReg(SrcReg, getKillRegState(isKill)) 744168f382dc67e5940cabdb28dc933c4f91cdd3137Bob Wilson .addMemOperand(MMO)); 745435d4991779d6a47cadff4ea670b490d8507d6c4Evan Cheng } else { 746435d4991779d6a47cadff4ea670b490d8507d6c4Evan Cheng MachineInstrBuilder MIB = 74773fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMDIA)) 74873fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling .addFrameIndex(FI)) 749435d4991779d6a47cadff4ea670b490d8507d6c4Evan Cheng .addMemOperand(MMO); 750558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI); 751558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI); 752558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI); 753558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI); 754435d4991779d6a47cadff4ea670b490d8507d6c4Evan Cheng } 755ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson break; 756ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson case ARM::QQQQPRRegClassID: { 75722c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng MachineInstrBuilder MIB = 75873fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMDIA)) 75973fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling .addFrameIndex(FI)) 76022c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng .addMemOperand(MMO); 761558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI); 762558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI); 763558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI); 764558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen MIB = AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI); 765558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen MIB = AddDReg(MIB, SrcReg, ARM::dsub_4, 0, TRI); 766558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen MIB = AddDReg(MIB, SrcReg, ARM::dsub_5, 0, TRI); 767558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen MIB = AddDReg(MIB, SrcReg, ARM::dsub_6, 0, TRI); 768558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen AddDReg(MIB, SrcReg, ARM::dsub_7, 0, TRI); 769ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson break; 770ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson } 771ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson default: 772ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson llvm_unreachable("Unknown regclass!"); 773334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 774334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 775334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 77634327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesenunsigned 77734327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund OlesenARMBaseInstrInfo::isStoreToStackSlot(const MachineInstr *MI, 77834327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen int &FrameIndex) const { 77934327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen switch (MI->getOpcode()) { 78034327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen default: break; 7817e3383c007f53b3a00675af225e428cb66ddf404Jim Grosbach case ARM::STRrs: 78234327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen case ARM::t2STRs: // FIXME: don't use t2STRs to access frame. 78334327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen if (MI->getOperand(1).isFI() && 78434327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen MI->getOperand(2).isReg() && 78534327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen MI->getOperand(3).isImm() && 78634327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen MI->getOperand(2).getReg() == 0 && 78734327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen MI->getOperand(3).getImm() == 0) { 78834327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen FrameIndex = MI->getOperand(1).getIndex(); 78934327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen return MI->getOperand(0).getReg(); 79034327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen } 79134327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen break; 7927e3383c007f53b3a00675af225e428cb66ddf404Jim Grosbach case ARM::STRi12: 79334327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen case ARM::t2STRi12: 79434327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen case ARM::tSpill: 79534327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen case ARM::VSTRD: 79634327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen case ARM::VSTRS: 79734327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen if (MI->getOperand(1).isFI() && 79834327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen MI->getOperand(2).isImm() && 79934327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen MI->getOperand(2).getImm() == 0) { 80034327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen FrameIndex = MI->getOperand(1).getIndex(); 80134327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen return MI->getOperand(0).getReg(); 80234327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen } 80334327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen break; 804d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen case ARM::VST1q64Pseudo: 805d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen if (MI->getOperand(0).isFI() && 806d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen MI->getOperand(2).getSubReg() == 0) { 807d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen FrameIndex = MI->getOperand(0).getIndex(); 808d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen return MI->getOperand(2).getReg(); 809d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen } 81031bbc51ac9245bc82c933c9db8358ca9bb558ac5Jakob Stoklund Olesen break; 81173fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMQIA: 812d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen if (MI->getOperand(1).isFI() && 813d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen MI->getOperand(0).getSubReg() == 0) { 814d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen FrameIndex = MI->getOperand(1).getIndex(); 815d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen return MI->getOperand(0).getReg(); 816d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen } 817d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen break; 81834327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen } 81934327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen 82034327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen return 0; 82134327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen} 82234327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen 823334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinvoid ARMBaseInstrInfo:: 824334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinloadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 825334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned DestReg, int FI, 826746ad69e088176819981b4b2c5ac8dcd49f5e60eEvan Cheng const TargetRegisterClass *RC, 827746ad69e088176819981b4b2c5ac8dcd49f5e60eEvan Cheng const TargetRegisterInfo *TRI) const { 828c7f3ace20c325521c68335a1689645b43b06ddf0Chris Lattner DebugLoc DL; 829334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (I != MBB.end()) DL = I->getDebugLoc(); 830249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MachineFunction &MF = *MBB.getParent(); 831249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MachineFrameInfo &MFI = *MF.getFrameInfo(); 83231bc849123011b8eae6bb3c79876d9a3c26a6a1dJim Grosbach unsigned Align = MFI.getObjectAlignment(FI); 833249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MachineMemOperand *MMO = 83459db5496f4fc2ef6111569e542f8b65480ef14c1Chris Lattner MF.getMachineMemOperand( 83559db5496f4fc2ef6111569e542f8b65480ef14c1Chris Lattner MachinePointerInfo(PseudoSourceValue::getFixedStack(FI)), 83659db5496f4fc2ef6111569e542f8b65480ef14c1Chris Lattner MachineMemOperand::MOLoad, 837249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MFI.getObjectSize(FI), 83831bc849123011b8eae6bb3c79876d9a3c26a6a1dJim Grosbach Align); 839334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 8400eb0c7401c34c0b4604f732ce54db995eead14e6Bob Wilson // tGPR is used sometimes in ARM instructions that need to avoid using 8410eb0c7401c34c0b4604f732ce54db995eead14e6Bob Wilson // certain registers. Just treat it as GPR here. 8426ccfc507dc1f7ad8c8964193a2407264ca644f0dJim Grosbach if (RC == ARM::tGPRRegisterClass || RC == ARM::tcGPRRegisterClass 8436ccfc507dc1f7ad8c8964193a2407264ca644f0dJim Grosbach || RC == ARM::rGPRRegisterClass) 8440eb0c7401c34c0b4604f732ce54db995eead14e6Bob Wilson RC = ARM::GPRRegisterClass; 8450eb0c7401c34c0b4604f732ce54db995eead14e6Bob Wilson 846ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson switch (RC->getID()) { 847ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson case ARM::GPRRegClassID: 8483e5561247202bae994dd259a2d8dc4eff8f799f3Jim Grosbach AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::LDRi12), DestReg) 8493e5561247202bae994dd259a2d8dc4eff8f799f3Jim Grosbach .addFrameIndex(FI).addImm(0).addMemOperand(MMO)); 850ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson break; 851ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson case ARM::SPRRegClassID: 852d31c5496d7e1580058b5c6fbc8fd537a641ea590Evan Cheng AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRS), DestReg) 853d31c5496d7e1580058b5c6fbc8fd537a641ea590Evan Cheng .addFrameIndex(FI).addImm(0).addMemOperand(MMO)); 854ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson break; 855ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson case ARM::DPRRegClassID: 856ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson case ARM::DPR_VFP2RegClassID: 857ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson case ARM::DPR_8RegClassID: 858e5165490b7ba24bb2f3043399e0d60e7f3bcf8a5Jim Grosbach AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRD), DestReg) 859249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov .addFrameIndex(FI).addImm(0).addMemOperand(MMO)); 860ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson break; 861ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson case ARM::QPRRegClassID: 862ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson case ARM::QPR_VFP2RegClassID: 863ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson case ARM::QPR_8RegClassID: 8640cfcf93c95af91e809ef740eb0ab368477226b40Jim Grosbach if (Align >= 16 && getRegisterInfo().needsStackRealignment(MF)) { 865168f382dc67e5940cabdb28dc933c4f91cdd3137Bob Wilson AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1q64Pseudo), DestReg) 866f967ca0eaf30325cabe3c1971bf0dba16cf1b027Bob Wilson .addFrameIndex(FI).addImm(16) 86769b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng .addMemOperand(MMO)); 86831bc849123011b8eae6bb3c79876d9a3c26a6a1dJim Grosbach } else { 86973fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMQIA), DestReg) 87069b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng .addFrameIndex(FI) 87169b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng .addMemOperand(MMO)); 87231bc849123011b8eae6bb3c79876d9a3c26a6a1dJim Grosbach } 873ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson break; 874ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson case ARM::QQPRRegClassID: 875ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson case ARM::QQPR_VFP2RegClassID: 876435d4991779d6a47cadff4ea670b490d8507d6c4Evan Cheng if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) { 877168f382dc67e5940cabdb28dc933c4f91cdd3137Bob Wilson AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1d64QPseudo), DestReg) 878168f382dc67e5940cabdb28dc933c4f91cdd3137Bob Wilson .addFrameIndex(FI).addImm(16) 879168f382dc67e5940cabdb28dc933c4f91cdd3137Bob Wilson .addMemOperand(MMO)); 880435d4991779d6a47cadff4ea670b490d8507d6c4Evan Cheng } else { 881435d4991779d6a47cadff4ea670b490d8507d6c4Evan Cheng MachineInstrBuilder MIB = 88273fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMDIA)) 88373fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling .addFrameIndex(FI)) 884435d4991779d6a47cadff4ea670b490d8507d6c4Evan Cheng .addMemOperand(MMO); 885558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::Define, TRI); 886558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::Define, TRI); 887558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::Define, TRI); 888558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen AddDReg(MIB, DestReg, ARM::dsub_3, RegState::Define, TRI); 889435d4991779d6a47cadff4ea670b490d8507d6c4Evan Cheng } 890ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson break; 891ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson case ARM::QQQQPRRegClassID: { 892ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson MachineInstrBuilder MIB = 89373fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMDIA)) 89473fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling .addFrameIndex(FI)) 895ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson .addMemOperand(MMO); 896ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::Define, TRI); 897ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::Define, TRI); 898ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::Define, TRI); 899ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::Define, TRI); 900ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson MIB = AddDReg(MIB, DestReg, ARM::dsub_4, RegState::Define, TRI); 901ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson MIB = AddDReg(MIB, DestReg, ARM::dsub_5, RegState::Define, TRI); 902ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson MIB = AddDReg(MIB, DestReg, ARM::dsub_6, RegState::Define, TRI); 903ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson AddDReg(MIB, DestReg, ARM::dsub_7, RegState::Define, TRI); 904ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson break; 905ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson } 906ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson default: 907ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson llvm_unreachable("Unknown regclass!"); 908334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 909334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 910334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 91134327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesenunsigned 91234327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund OlesenARMBaseInstrInfo::isLoadFromStackSlot(const MachineInstr *MI, 91334327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen int &FrameIndex) const { 91434327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen switch (MI->getOpcode()) { 91534327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen default: break; 9163e5561247202bae994dd259a2d8dc4eff8f799f3Jim Grosbach case ARM::LDRrs: 91734327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen case ARM::t2LDRs: // FIXME: don't use t2LDRs to access frame. 91834327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen if (MI->getOperand(1).isFI() && 91934327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen MI->getOperand(2).isReg() && 92034327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen MI->getOperand(3).isImm() && 92134327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen MI->getOperand(2).getReg() == 0 && 92234327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen MI->getOperand(3).getImm() == 0) { 92334327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen FrameIndex = MI->getOperand(1).getIndex(); 92434327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen return MI->getOperand(0).getReg(); 92534327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen } 92634327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen break; 9273e5561247202bae994dd259a2d8dc4eff8f799f3Jim Grosbach case ARM::LDRi12: 92834327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen case ARM::t2LDRi12: 92934327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen case ARM::tRestore: 93034327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen case ARM::VLDRD: 93134327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen case ARM::VLDRS: 93234327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen if (MI->getOperand(1).isFI() && 93334327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen MI->getOperand(2).isImm() && 93434327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen MI->getOperand(2).getImm() == 0) { 93534327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen FrameIndex = MI->getOperand(1).getIndex(); 936d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen return MI->getOperand(0).getReg(); 937d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen } 938d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen break; 939d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen case ARM::VLD1q64Pseudo: 940d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen if (MI->getOperand(1).isFI() && 941d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen MI->getOperand(0).getSubReg() == 0) { 942d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen FrameIndex = MI->getOperand(1).getIndex(); 94306f264e504d75f0426eea55b9f9e36c780d8a4fcJakob Stoklund Olesen return MI->getOperand(0).getReg(); 94406f264e504d75f0426eea55b9f9e36c780d8a4fcJakob Stoklund Olesen } 94506f264e504d75f0426eea55b9f9e36c780d8a4fcJakob Stoklund Olesen break; 94673fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMQIA: 94706f264e504d75f0426eea55b9f9e36c780d8a4fcJakob Stoklund Olesen if (MI->getOperand(1).isFI() && 94806f264e504d75f0426eea55b9f9e36c780d8a4fcJakob Stoklund Olesen MI->getOperand(0).getSubReg() == 0) { 94906f264e504d75f0426eea55b9f9e36c780d8a4fcJakob Stoklund Olesen FrameIndex = MI->getOperand(1).getIndex(); 95034327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen return MI->getOperand(0).getReg(); 95134327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen } 95234327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen break; 95334327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen } 95434327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen 95534327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen return 0; 95634327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen} 95734327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen 95862b50656ceb854eb0be265d63b2a1d46e7400d8aEvan ChengMachineInstr* 95962b50656ceb854eb0be265d63b2a1d46e7400d8aEvan ChengARMBaseInstrInfo::emitFrameIndexDebugValue(MachineFunction &MF, 9608601a3d4decff0a380e059b037dabf71075497d3Evan Cheng int FrameIx, uint64_t Offset, 96162b50656ceb854eb0be265d63b2a1d46e7400d8aEvan Cheng const MDNode *MDPtr, 96262b50656ceb854eb0be265d63b2a1d46e7400d8aEvan Cheng DebugLoc DL) const { 96362b50656ceb854eb0be265d63b2a1d46e7400d8aEvan Cheng MachineInstrBuilder MIB = BuildMI(MF, DL, get(ARM::DBG_VALUE)) 96462b50656ceb854eb0be265d63b2a1d46e7400d8aEvan Cheng .addFrameIndex(FrameIx).addImm(0).addImm(Offset).addMetadata(MDPtr); 96562b50656ceb854eb0be265d63b2a1d46e7400d8aEvan Cheng return &*MIB; 96662b50656ceb854eb0be265d63b2a1d46e7400d8aEvan Cheng} 96762b50656ceb854eb0be265d63b2a1d46e7400d8aEvan Cheng 96830ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen/// Create a copy of a const pool value. Update CPI to the new index and return 96930ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen/// the label UID. 97030ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesenstatic unsigned duplicateCPV(MachineFunction &MF, unsigned &CPI) { 97130ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen MachineConstantPool *MCP = MF.getConstantPool(); 97230ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 97330ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen 97430ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPI]; 97530ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen assert(MCPE.isMachineConstantPoolEntry() && 97630ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen "Expecting a machine constantpool entry!"); 97730ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen ARMConstantPoolValue *ACPV = 97830ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal); 97930ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen 9805de5d4b6d0eb3fd379fa571d82f6fa764460b3b8Evan Cheng unsigned PCLabelId = AFI->createPICLabelUId(); 98130ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen ARMConstantPoolValue *NewCPV = 0; 98251f5b67395780b8421f4aa6ee998ed51b23dae9dJim Grosbach // FIXME: The below assumes PIC relocation model and that the function 98351f5b67395780b8421f4aa6ee998ed51b23dae9dJim Grosbach // is Thumb mode (t1 or t2). PCAdjustment would be 8 for ARM mode PIC, and 98451f5b67395780b8421f4aa6ee998ed51b23dae9dJim Grosbach // zero for non-PIC in ARM or Thumb. The callers are all of thumb LDR 98551f5b67395780b8421f4aa6ee998ed51b23dae9dJim Grosbach // instructions, so that's probably OK, but is PIC always correct when 98651f5b67395780b8421f4aa6ee998ed51b23dae9dJim Grosbach // we get here? 98730ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen if (ACPV->isGlobalValue()) 98830ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen NewCPV = new ARMConstantPoolValue(ACPV->getGV(), PCLabelId, 98930ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen ARMCP::CPValue, 4); 99030ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen else if (ACPV->isExtSymbol()) 99130ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen NewCPV = new ARMConstantPoolValue(MF.getFunction()->getContext(), 99230ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen ACPV->getSymbol(), PCLabelId, 4); 99330ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen else if (ACPV->isBlockAddress()) 99430ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen NewCPV = new ARMConstantPoolValue(ACPV->getBlockAddress(), PCLabelId, 99530ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen ARMCP::CPBlockAddress, 4); 99651f5b67395780b8421f4aa6ee998ed51b23dae9dJim Grosbach else if (ACPV->isLSDA()) 99751f5b67395780b8421f4aa6ee998ed51b23dae9dJim Grosbach NewCPV = new ARMConstantPoolValue(MF.getFunction(), PCLabelId, 99851f5b67395780b8421f4aa6ee998ed51b23dae9dJim Grosbach ARMCP::CPLSDA, 4); 99930ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen else 100030ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen llvm_unreachable("Unexpected ARM constantpool value type!!"); 100130ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen CPI = MCP->getConstantPoolIndex(NewCPV, MCPE.getAlignment()); 100230ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen return PCLabelId; 100330ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen} 100430ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen 1005fdc834046efd427d474e3b899ec69354c05071e0Evan Chengvoid ARMBaseInstrInfo:: 1006fdc834046efd427d474e3b899ec69354c05071e0Evan ChengreMaterialize(MachineBasicBlock &MBB, 1007fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng MachineBasicBlock::iterator I, 1008fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng unsigned DestReg, unsigned SubIdx, 1009d57cdd5683ea926e489067364fb7ffe5fd5d35eeEvan Cheng const MachineInstr *Orig, 10109edf7deb37f0f97664f279040fa15d89f32e23d9Jakob Stoklund Olesen const TargetRegisterInfo &TRI) const { 1011fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng unsigned Opcode = Orig->getOpcode(); 1012fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng switch (Opcode) { 1013fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng default: { 1014fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig); 10159edf7deb37f0f97664f279040fa15d89f32e23d9Jakob Stoklund Olesen MI->substituteRegister(Orig->getOperand(0).getReg(), DestReg, SubIdx, TRI); 1016fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng MBB.insert(I, MI); 1017fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng break; 1018fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng } 1019fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng case ARM::tLDRpci_pic: 1020fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng case ARM::t2LDRpci_pic: { 1021fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng MachineFunction &MF = *MBB.getParent(); 1022fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng unsigned CPI = Orig->getOperand(1).getIndex(); 102330ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen unsigned PCLabelId = duplicateCPV(MF, CPI); 1024fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng MachineInstrBuilder MIB = BuildMI(MBB, I, Orig->getDebugLoc(), get(Opcode), 1025fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng DestReg) 1026fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng .addConstantPoolIndex(CPI).addImm(PCLabelId); 1027d7d030a44796adc73a6eaa939cd17e52047734c1Chris Lattner MIB->setMemRefs(Orig->memoperands_begin(), Orig->memoperands_end()); 1028fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng break; 1029fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng } 1030fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng } 1031fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng} 1032fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng 103330ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund OlesenMachineInstr * 103430ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund OlesenARMBaseInstrInfo::duplicate(MachineInstr *Orig, MachineFunction &MF) const { 103530ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen MachineInstr *MI = TargetInstrInfoImpl::duplicate(Orig, MF); 103630ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen switch(Orig->getOpcode()) { 103730ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen case ARM::tLDRpci_pic: 103830ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen case ARM::t2LDRpci_pic: { 103930ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen unsigned CPI = Orig->getOperand(1).getIndex(); 104030ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen unsigned PCLabelId = duplicateCPV(MF, CPI); 104130ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen Orig->getOperand(1).setIndex(CPI); 104230ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen Orig->getOperand(2).setImm(PCLabelId); 104330ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen break; 104430ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen } 104530ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen } 104630ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen return MI; 104730ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen} 104830ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen 1049506049f29f4f202a8e45feb916cc0264440a7f6dEvan Chengbool ARMBaseInstrInfo::produceSameValue(const MachineInstr *MI0, 10509fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng const MachineInstr *MI1, 10519fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng const MachineRegisterInfo *MRI) const { 1052d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng int Opcode = MI0->getOpcode(); 1053d7e3cc840b81b0438e47f05d9664137a198876dfEvan Cheng if (Opcode == ARM::t2LDRpci || 10549b82425cb0105fd5704f6b9bcd5e7693b05b1759Evan Cheng Opcode == ARM::t2LDRpci_pic || 10559b82425cb0105fd5704f6b9bcd5e7693b05b1759Evan Cheng Opcode == ARM::tLDRpci || 10569fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng Opcode == ARM::tLDRpci_pic || 105753519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng Opcode == ARM::MOV_ga_dyn || 105853519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng Opcode == ARM::MOV_ga_pcrel || 105953519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng Opcode == ARM::MOV_ga_pcrel_ldr || 106053519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng Opcode == ARM::t2MOV_ga_dyn || 106153519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng Opcode == ARM::t2MOV_ga_pcrel) { 1062d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng if (MI1->getOpcode() != Opcode) 1063d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng return false; 1064d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng if (MI0->getNumOperands() != MI1->getNumOperands()) 1065d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng return false; 1066d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng 1067d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng const MachineOperand &MO0 = MI0->getOperand(1); 1068d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng const MachineOperand &MO1 = MI1->getOperand(1); 1069d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng if (MO0.getOffset() != MO1.getOffset()) 1070d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng return false; 1071d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng 107253519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng if (Opcode == ARM::MOV_ga_dyn || 107353519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng Opcode == ARM::MOV_ga_pcrel || 107453519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng Opcode == ARM::MOV_ga_pcrel_ldr || 107553519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng Opcode == ARM::t2MOV_ga_dyn || 107653519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng Opcode == ARM::t2MOV_ga_pcrel) 10779fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng // Ignore the PC labels. 10789fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng return MO0.getGlobal() == MO1.getGlobal(); 10799fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng 1080d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng const MachineFunction *MF = MI0->getParent()->getParent(); 1081d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng const MachineConstantPool *MCP = MF->getConstantPool(); 1082d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng int CPI0 = MO0.getIndex(); 1083d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng int CPI1 = MO1.getIndex(); 1084d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng const MachineConstantPoolEntry &MCPE0 = MCP->getConstants()[CPI0]; 1085d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng const MachineConstantPoolEntry &MCPE1 = MCP->getConstants()[CPI1]; 1086d700617193f3d11deb83cd56c4ababbc8e0ea19fEvan Cheng bool isARMCP0 = MCPE0.isMachineConstantPoolEntry(); 1087d700617193f3d11deb83cd56c4ababbc8e0ea19fEvan Cheng bool isARMCP1 = MCPE1.isMachineConstantPoolEntry(); 1088d700617193f3d11deb83cd56c4ababbc8e0ea19fEvan Cheng if (isARMCP0 && isARMCP1) { 1089d700617193f3d11deb83cd56c4ababbc8e0ea19fEvan Cheng ARMConstantPoolValue *ACPV0 = 1090d700617193f3d11deb83cd56c4ababbc8e0ea19fEvan Cheng static_cast<ARMConstantPoolValue*>(MCPE0.Val.MachineCPVal); 1091d700617193f3d11deb83cd56c4ababbc8e0ea19fEvan Cheng ARMConstantPoolValue *ACPV1 = 1092d700617193f3d11deb83cd56c4ababbc8e0ea19fEvan Cheng static_cast<ARMConstantPoolValue*>(MCPE1.Val.MachineCPVal); 1093d700617193f3d11deb83cd56c4ababbc8e0ea19fEvan Cheng return ACPV0->hasSameValue(ACPV1); 1094d700617193f3d11deb83cd56c4ababbc8e0ea19fEvan Cheng } else if (!isARMCP0 && !isARMCP1) { 1095d700617193f3d11deb83cd56c4ababbc8e0ea19fEvan Cheng return MCPE0.Val.ConstVal == MCPE1.Val.ConstVal; 1096d700617193f3d11deb83cd56c4ababbc8e0ea19fEvan Cheng } 1097d700617193f3d11deb83cd56c4ababbc8e0ea19fEvan Cheng return false; 10989fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng } else if (Opcode == ARM::PICLDR) { 10999fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng if (MI1->getOpcode() != Opcode) 11009fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng return false; 11019fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng if (MI0->getNumOperands() != MI1->getNumOperands()) 11029fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng return false; 11039fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng 11049fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng unsigned Addr0 = MI0->getOperand(1).getReg(); 11059fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng unsigned Addr1 = MI1->getOperand(1).getReg(); 11069fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng if (Addr0 != Addr1) { 11079fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng if (!MRI || 11089fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng !TargetRegisterInfo::isVirtualRegister(Addr0) || 11099fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng !TargetRegisterInfo::isVirtualRegister(Addr1)) 11109fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng return false; 11119fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng 11129fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng // This assumes SSA form. 11139fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng MachineInstr *Def0 = MRI->getVRegDef(Addr0); 11149fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng MachineInstr *Def1 = MRI->getVRegDef(Addr1); 11159fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng // Check if the loaded value, e.g. a constantpool of a global address, are 11169fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng // the same. 11179fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng if (!produceSameValue(Def0, Def1, MRI)) 11189fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng return false; 11199fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng } 11209fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng 11219fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng for (unsigned i = 3, e = MI0->getNumOperands(); i != e; ++i) { 11229fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng // %vreg12<def> = PICLDR %vreg11, 0, pred:14, pred:%noreg 11239fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng const MachineOperand &MO0 = MI0->getOperand(i); 11249fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng const MachineOperand &MO1 = MI1->getOperand(i); 11259fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng if (!MO0.isIdenticalTo(MO1)) 11269fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng return false; 11279fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng } 11289fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng return true; 1129d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng } 1130d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng 1131506049f29f4f202a8e45feb916cc0264440a7f6dEvan Cheng return MI0->isIdenticalTo(MI1, MachineInstr::IgnoreVRegDefs); 1132d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng} 1133d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng 11344b722108e2cf8e77157e0879a23789cd44829933Bill Wendling/// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to 11354b722108e2cf8e77157e0879a23789cd44829933Bill Wendling/// determine if two loads are loading from the same base address. It should 11364b722108e2cf8e77157e0879a23789cd44829933Bill Wendling/// only return true if the base pointers are the same and the only differences 11374b722108e2cf8e77157e0879a23789cd44829933Bill Wendling/// between the two addresses is the offset. It also returns the offsets by 11384b722108e2cf8e77157e0879a23789cd44829933Bill Wendling/// reference. 11394b722108e2cf8e77157e0879a23789cd44829933Bill Wendlingbool ARMBaseInstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, 11404b722108e2cf8e77157e0879a23789cd44829933Bill Wendling int64_t &Offset1, 11414b722108e2cf8e77157e0879a23789cd44829933Bill Wendling int64_t &Offset2) const { 11424b722108e2cf8e77157e0879a23789cd44829933Bill Wendling // Don't worry about Thumb: just ARM and Thumb2. 11434b722108e2cf8e77157e0879a23789cd44829933Bill Wendling if (Subtarget.isThumb1Only()) return false; 11444b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 11454b722108e2cf8e77157e0879a23789cd44829933Bill Wendling if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode()) 11464b722108e2cf8e77157e0879a23789cd44829933Bill Wendling return false; 11474b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 11484b722108e2cf8e77157e0879a23789cd44829933Bill Wendling switch (Load1->getMachineOpcode()) { 11494b722108e2cf8e77157e0879a23789cd44829933Bill Wendling default: 11504b722108e2cf8e77157e0879a23789cd44829933Bill Wendling return false; 11513e5561247202bae994dd259a2d8dc4eff8f799f3Jim Grosbach case ARM::LDRi12: 1152c1d30212e911d1e55ff6b25bffefb503708883c3Jim Grosbach case ARM::LDRBi12: 11534b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::LDRD: 11544b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::LDRH: 11554b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::LDRSB: 11564b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::LDRSH: 11574b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::VLDRD: 11584b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::VLDRS: 11594b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::t2LDRi8: 11604b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::t2LDRDi8: 11614b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::t2LDRSHi8: 11624b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::t2LDRi12: 11634b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::t2LDRSHi12: 11644b722108e2cf8e77157e0879a23789cd44829933Bill Wendling break; 11654b722108e2cf8e77157e0879a23789cd44829933Bill Wendling } 11664b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 11674b722108e2cf8e77157e0879a23789cd44829933Bill Wendling switch (Load2->getMachineOpcode()) { 11684b722108e2cf8e77157e0879a23789cd44829933Bill Wendling default: 11694b722108e2cf8e77157e0879a23789cd44829933Bill Wendling return false; 11703e5561247202bae994dd259a2d8dc4eff8f799f3Jim Grosbach case ARM::LDRi12: 1171c1d30212e911d1e55ff6b25bffefb503708883c3Jim Grosbach case ARM::LDRBi12: 11724b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::LDRD: 11734b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::LDRH: 11744b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::LDRSB: 11754b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::LDRSH: 11764b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::VLDRD: 11774b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::VLDRS: 11784b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::t2LDRi8: 11794b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::t2LDRDi8: 11804b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::t2LDRSHi8: 11814b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::t2LDRi12: 11824b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::t2LDRSHi12: 11834b722108e2cf8e77157e0879a23789cd44829933Bill Wendling break; 11844b722108e2cf8e77157e0879a23789cd44829933Bill Wendling } 11854b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 11864b722108e2cf8e77157e0879a23789cd44829933Bill Wendling // Check if base addresses and chain operands match. 11874b722108e2cf8e77157e0879a23789cd44829933Bill Wendling if (Load1->getOperand(0) != Load2->getOperand(0) || 11884b722108e2cf8e77157e0879a23789cd44829933Bill Wendling Load1->getOperand(4) != Load2->getOperand(4)) 11894b722108e2cf8e77157e0879a23789cd44829933Bill Wendling return false; 11904b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 11914b722108e2cf8e77157e0879a23789cd44829933Bill Wendling // Index should be Reg0. 11924b722108e2cf8e77157e0879a23789cd44829933Bill Wendling if (Load1->getOperand(3) != Load2->getOperand(3)) 11934b722108e2cf8e77157e0879a23789cd44829933Bill Wendling return false; 11944b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 11954b722108e2cf8e77157e0879a23789cd44829933Bill Wendling // Determine the offsets. 11964b722108e2cf8e77157e0879a23789cd44829933Bill Wendling if (isa<ConstantSDNode>(Load1->getOperand(1)) && 11974b722108e2cf8e77157e0879a23789cd44829933Bill Wendling isa<ConstantSDNode>(Load2->getOperand(1))) { 11984b722108e2cf8e77157e0879a23789cd44829933Bill Wendling Offset1 = cast<ConstantSDNode>(Load1->getOperand(1))->getSExtValue(); 11994b722108e2cf8e77157e0879a23789cd44829933Bill Wendling Offset2 = cast<ConstantSDNode>(Load2->getOperand(1))->getSExtValue(); 12004b722108e2cf8e77157e0879a23789cd44829933Bill Wendling return true; 12014b722108e2cf8e77157e0879a23789cd44829933Bill Wendling } 12024b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 12034b722108e2cf8e77157e0879a23789cd44829933Bill Wendling return false; 12044b722108e2cf8e77157e0879a23789cd44829933Bill Wendling} 12054b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 12064b722108e2cf8e77157e0879a23789cd44829933Bill Wendling/// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to 12077a2bdde0a0eebcd2125055e0eacaca040f0b766cChris Lattner/// determine (in conjunction with areLoadsFromSameBasePtr) if two loads should 12084b722108e2cf8e77157e0879a23789cd44829933Bill Wendling/// be scheduled togther. On some targets if two loads are loading from 12094b722108e2cf8e77157e0879a23789cd44829933Bill Wendling/// addresses in the same cache line, it's better if they are scheduled 12104b722108e2cf8e77157e0879a23789cd44829933Bill Wendling/// together. This function takes two integers that represent the load offsets 12114b722108e2cf8e77157e0879a23789cd44829933Bill Wendling/// from the common base address. It returns true if it decides it's desirable 12124b722108e2cf8e77157e0879a23789cd44829933Bill Wendling/// to schedule the two loads together. "NumLoads" is the number of loads that 12134b722108e2cf8e77157e0879a23789cd44829933Bill Wendling/// have already been scheduled after Load1. 12144b722108e2cf8e77157e0879a23789cd44829933Bill Wendlingbool ARMBaseInstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, 12154b722108e2cf8e77157e0879a23789cd44829933Bill Wendling int64_t Offset1, int64_t Offset2, 12164b722108e2cf8e77157e0879a23789cd44829933Bill Wendling unsigned NumLoads) const { 12174b722108e2cf8e77157e0879a23789cd44829933Bill Wendling // Don't worry about Thumb: just ARM and Thumb2. 12184b722108e2cf8e77157e0879a23789cd44829933Bill Wendling if (Subtarget.isThumb1Only()) return false; 12194b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 12204b722108e2cf8e77157e0879a23789cd44829933Bill Wendling assert(Offset2 > Offset1); 12214b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 12224b722108e2cf8e77157e0879a23789cd44829933Bill Wendling if ((Offset2 - Offset1) / 8 > 64) 12234b722108e2cf8e77157e0879a23789cd44829933Bill Wendling return false; 12244b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 12254b722108e2cf8e77157e0879a23789cd44829933Bill Wendling if (Load1->getMachineOpcode() != Load2->getMachineOpcode()) 12264b722108e2cf8e77157e0879a23789cd44829933Bill Wendling return false; // FIXME: overly conservative? 12274b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 12284b722108e2cf8e77157e0879a23789cd44829933Bill Wendling // Four loads in a row should be sufficient. 12294b722108e2cf8e77157e0879a23789cd44829933Bill Wendling if (NumLoads >= 3) 12304b722108e2cf8e77157e0879a23789cd44829933Bill Wendling return false; 12314b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 12324b722108e2cf8e77157e0879a23789cd44829933Bill Wendling return true; 12334b722108e2cf8e77157e0879a23789cd44829933Bill Wendling} 12344b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 123586050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Chengbool ARMBaseInstrInfo::isSchedulingBoundary(const MachineInstr *MI, 123686050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng const MachineBasicBlock *MBB, 123786050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng const MachineFunction &MF) const { 123857bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach // Debug info is never a scheduling boundary. It's necessary to be explicit 123957bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach // due to the special treatment of IT instructions below, otherwise a 124057bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach // dbg_value followed by an IT will result in the IT instruction being 124157bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach // considered a scheduling hazard, which is wrong. It should be the actual 124257bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach // instruction preceding the dbg_value instruction(s), just like it is 124357bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach // when debug info is not present. 124457bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach if (MI->isDebugValue()) 124557bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach return false; 124657bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach 124786050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // Terminators and labels can't be scheduled around. 124886050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng if (MI->getDesc().isTerminator() || MI->isLabel()) 124986050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng return true; 125086050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng 125186050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // Treat the start of the IT block as a scheduling boundary, but schedule 125286050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // t2IT along with all instructions following it. 125386050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // FIXME: This is a big hammer. But the alternative is to add all potential 125486050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // true and anti dependencies to IT block instructions as implicit operands 125586050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // to the t2IT instruction. The added compile time and complexity does not 125686050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // seem worth it. 125786050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng MachineBasicBlock::const_iterator I = MI; 125857bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach // Make sure to skip any dbg_value instructions 125957bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach while (++I != MBB->end() && I->isDebugValue()) 126057bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach ; 126157bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach if (I != MBB->end() && I->getOpcode() == ARM::t2IT) 126286050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng return true; 126386050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng 126486050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // Don't attempt to schedule around any instruction that defines 126586050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // a stack-oriented pointer, as it's unlikely to be profitable. This 126686050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // saves compile time, because it doesn't require every single 126786050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // stack slot reference to depend on the instruction that does the 126886050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // modification. 126986050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng if (MI->definesRegister(ARM::SP)) 127086050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng return true; 127186050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng 127286050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng return false; 127386050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng} 127486050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng 1275b20b85168c0e9819e6545f08281e9b83c82108f0Owen Andersonbool ARMBaseInstrInfo::isProfitableToIfCvt(MachineBasicBlock &MBB, 12765876db7a66fcc4ec4444a9f3e387c1cdc8baf9e5Cameron Zwarich unsigned NumCycles, 12778239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng unsigned ExtraPredCycles, 1278e3cc84a43d6a4bb6c50f58f3dd8e60e28787509eOwen Anderson float Probability, 1279e3cc84a43d6a4bb6c50f58f3dd8e60e28787509eOwen Anderson float Confidence) const { 12805876db7a66fcc4ec4444a9f3e387c1cdc8baf9e5Cameron Zwarich if (!NumCycles) 128113151432edace19ee867a93b5c14573df4f75d24Evan Cheng return false; 12822bbb76909126db5bed6bde84b16d94ab5de4d372Michael J. Spencer 1283b20b85168c0e9819e6545f08281e9b83c82108f0Owen Anderson // Attempt to estimate the relative costs of predication versus branching. 12845876db7a66fcc4ec4444a9f3e387c1cdc8baf9e5Cameron Zwarich float UnpredCost = Probability * NumCycles; 1285654d5440a477b1f6c89b051107e041a331f78e27Owen Anderson UnpredCost += 1.0; // The branch itself 1286e3cc84a43d6a4bb6c50f58f3dd8e60e28787509eOwen Anderson UnpredCost += (1.0 - Confidence) * Subtarget.getMispredictionPenalty(); 12872bbb76909126db5bed6bde84b16d94ab5de4d372Michael J. Spencer 12885876db7a66fcc4ec4444a9f3e387c1cdc8baf9e5Cameron Zwarich return (float)(NumCycles + ExtraPredCycles) < UnpredCost; 128913151432edace19ee867a93b5c14573df4f75d24Evan Cheng} 12902bbb76909126db5bed6bde84b16d94ab5de4d372Michael J. Spencer 129113151432edace19ee867a93b5c14573df4f75d24Evan Chengbool ARMBaseInstrInfo:: 12928239daf7c83a65a189c352cce3191cdc3bbfe151Evan ChengisProfitableToIfCvt(MachineBasicBlock &TMBB, 12938239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng unsigned TCycles, unsigned TExtra, 12948239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng MachineBasicBlock &FMBB, 12958239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng unsigned FCycles, unsigned FExtra, 1296e3cc84a43d6a4bb6c50f58f3dd8e60e28787509eOwen Anderson float Probability, float Confidence) const { 12978239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng if (!TCycles || !FCycles) 1298b20b85168c0e9819e6545f08281e9b83c82108f0Owen Anderson return false; 12992bbb76909126db5bed6bde84b16d94ab5de4d372Michael J. Spencer 1300b20b85168c0e9819e6545f08281e9b83c82108f0Owen Anderson // Attempt to estimate the relative costs of predication versus branching. 13018239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng float UnpredCost = Probability * TCycles + (1.0 - Probability) * FCycles; 1302654d5440a477b1f6c89b051107e041a331f78e27Owen Anderson UnpredCost += 1.0; // The branch itself 1303e3cc84a43d6a4bb6c50f58f3dd8e60e28787509eOwen Anderson UnpredCost += (1.0 - Confidence) * Subtarget.getMispredictionPenalty(); 13042bbb76909126db5bed6bde84b16d94ab5de4d372Michael J. Spencer 13058239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng return (float)(TCycles + FCycles + TExtra + FExtra) < UnpredCost; 130613151432edace19ee867a93b5c14573df4f75d24Evan Cheng} 130713151432edace19ee867a93b5c14573df4f75d24Evan Cheng 13088fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng/// getInstrPredicate - If instruction is predicated, returns its predicate 13098fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng/// condition, otherwise returns AL. It also returns the condition code 13108fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng/// register by reference. 13115adb66a646e2ec32265263739f5b01c3f50c176aEvan ChengARMCC::CondCodes 13125adb66a646e2ec32265263739f5b01c3f50c176aEvan Chengllvm::getInstrPredicate(const MachineInstr *MI, unsigned &PredReg) { 13138fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng int PIdx = MI->findFirstPredOperandIdx(); 13148fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng if (PIdx == -1) { 13158fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng PredReg = 0; 13168fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng return ARMCC::AL; 13178fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng } 13188fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng 13198fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng PredReg = MI->getOperand(PIdx+1).getReg(); 13208fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng return (ARMCC::CondCodes)MI->getOperand(PIdx).getImm(); 13218fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng} 13228fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng 13238fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng 13246495f63945e8dbde81f03a1dc2ab421993b9a495Evan Chengint llvm::getMatchingCondBranchOpcode(int Opc) { 13255ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng if (Opc == ARM::B) 13265ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng return ARM::Bcc; 13275ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng else if (Opc == ARM::tB) 13285ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng return ARM::tBcc; 13295ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng else if (Opc == ARM::t2B) 13305ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng return ARM::t2Bcc; 13315ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng 13325ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng llvm_unreachable("Unknown unconditional branch opcode!"); 13335ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng return 0; 13345ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng} 13355ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng 13366495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 13376495f63945e8dbde81f03a1dc2ab421993b9a495Evan Chengvoid llvm::emitARMRegPlusImmediate(MachineBasicBlock &MBB, 13386495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MachineBasicBlock::iterator &MBBI, DebugLoc dl, 13396495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned DestReg, unsigned BaseReg, int NumBytes, 13406495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ARMCC::CondCodes Pred, unsigned PredReg, 134157caad7a33ff145b71545f10dcfbbf2fd0f595d3Anton Korobeynikov const ARMBaseInstrInfo &TII, unsigned MIFlags) { 13426495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng bool isSub = NumBytes < 0; 13436495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (isSub) NumBytes = -NumBytes; 13446495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 13456495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng while (NumBytes) { 13466495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned RotAmt = ARM_AM::getSOImmValRotate(NumBytes); 13476495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned ThisVal = NumBytes & ARM_AM::rotr32(0xFF, RotAmt); 13486495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng assert(ThisVal && "Didn't extract field correctly"); 13496495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 13506495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // We will handle these bits from offset, clear them. 13516495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng NumBytes &= ~ThisVal; 13526495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 13536495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng assert(ARM_AM::getSOImmVal(ThisVal) != -1 && "Bit extraction didn't work?"); 13546495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 13556495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Build the new ADD / SUB. 13566495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned Opc = isSub ? ARM::SUBri : ARM::ADDri; 13576495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg) 13586495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng .addReg(BaseReg, RegState::Kill).addImm(ThisVal) 135957caad7a33ff145b71545f10dcfbbf2fd0f595d3Anton Korobeynikov .addImm((unsigned)Pred).addReg(PredReg).addReg(0) 136057caad7a33ff145b71545f10dcfbbf2fd0f595d3Anton Korobeynikov .setMIFlags(MIFlags); 13616495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng BaseReg = DestReg; 13626495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 13636495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng} 13646495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 1365cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Chengbool llvm::rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx, 1366cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng unsigned FrameReg, int &Offset, 1367cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng const ARMBaseInstrInfo &TII) { 13686495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned Opcode = MI.getOpcode(); 1369e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng const MCInstrDesc &Desc = MI.getDesc(); 13706495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask); 13716495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng bool isSub = false; 1372764ab52dd80310a205c9888bf166d09dab858f90Jim Grosbach 13736495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Memory operands in inline assembly always use AddrMode2. 13746495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (Opcode == ARM::INLINEASM) 13756495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng AddrMode = ARMII::AddrMode2; 1376764ab52dd80310a205c9888bf166d09dab858f90Jim Grosbach 13776495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (Opcode == ARM::ADDri) { 13786495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng Offset += MI.getOperand(FrameRegIdx+1).getImm(); 13796495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (Offset == 0) { 13806495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Turn it into a move. 13816495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MI.setDesc(TII.get(ARM::MOVr)); 13826495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false); 13836495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MI.RemoveOperand(FrameRegIdx+1); 1384cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng Offset = 0; 1385cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng return true; 13866495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } else if (Offset < 0) { 13876495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng Offset = -Offset; 13886495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng isSub = true; 13896495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MI.setDesc(TII.get(ARM::SUBri)); 13906495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 13916495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 13926495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Common case: small offset, fits into instruction. 13936495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (ARM_AM::getSOImmVal(Offset) != -1) { 13946495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Replace the FrameIndex with sp / fp 13956495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false); 13966495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset); 1397cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng Offset = 0; 1398cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng return true; 13996495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 14006495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 14016495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Otherwise, pull as much of the immedidate into this ADDri/SUBri 14026495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // as possible. 14036495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned RotAmt = ARM_AM::getSOImmValRotate(Offset); 14046495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xFF, RotAmt); 14056495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 14066495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // We will handle these bits from offset, clear them. 14076495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng Offset &= ~ThisImmVal; 14086495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 14096495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Get the properly encoded SOImmVal field. 14106495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng assert(ARM_AM::getSOImmVal(ThisImmVal) != -1 && 14116495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng "Bit extraction didn't work?"); 14126495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MI.getOperand(FrameRegIdx+1).ChangeToImmediate(ThisImmVal); 14136495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } else { 14146495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned ImmIdx = 0; 14156495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng int InstrOffs = 0; 14166495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned NumBits = 0; 14176495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned Scale = 1; 14186495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng switch (AddrMode) { 14193e5561247202bae994dd259a2d8dc4eff8f799f3Jim Grosbach case ARMII::AddrMode_i12: { 14203e5561247202bae994dd259a2d8dc4eff8f799f3Jim Grosbach ImmIdx = FrameRegIdx + 1; 14213e5561247202bae994dd259a2d8dc4eff8f799f3Jim Grosbach InstrOffs = MI.getOperand(ImmIdx).getImm(); 14223e5561247202bae994dd259a2d8dc4eff8f799f3Jim Grosbach NumBits = 12; 14233e5561247202bae994dd259a2d8dc4eff8f799f3Jim Grosbach break; 14243e5561247202bae994dd259a2d8dc4eff8f799f3Jim Grosbach } 14256495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng case ARMII::AddrMode2: { 14266495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ImmIdx = FrameRegIdx+2; 14276495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng InstrOffs = ARM_AM::getAM2Offset(MI.getOperand(ImmIdx).getImm()); 14286495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (ARM_AM::getAM2Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub) 14296495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng InstrOffs *= -1; 14306495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng NumBits = 12; 14316495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng break; 14326495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 14336495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng case ARMII::AddrMode3: { 14346495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ImmIdx = FrameRegIdx+2; 14356495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng InstrOffs = ARM_AM::getAM3Offset(MI.getOperand(ImmIdx).getImm()); 14366495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (ARM_AM::getAM3Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub) 14376495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng InstrOffs *= -1; 14386495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng NumBits = 8; 14396495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng break; 14406495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 1441baf31088f1472f48ea5ae81f0b93636cc44ca444Anton Korobeynikov case ARMII::AddrMode4: 1442a44321776ecd96fa0344335d3027758be3386e45Jim Grosbach case ARMII::AddrMode6: 1443cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng // Can't fold any offset even if it's zero. 1444cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng return false; 14456495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng case ARMII::AddrMode5: { 14466495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ImmIdx = FrameRegIdx+1; 14476495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng InstrOffs = ARM_AM::getAM5Offset(MI.getOperand(ImmIdx).getImm()); 14486495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (ARM_AM::getAM5Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub) 14496495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng InstrOffs *= -1; 14506495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng NumBits = 8; 14516495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng Scale = 4; 14526495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng break; 14536495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 14546495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng default: 14556495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng llvm_unreachable("Unsupported addressing mode!"); 14566495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng break; 14576495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 14586495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 14596495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng Offset += InstrOffs * Scale; 14606495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!"); 14616495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (Offset < 0) { 14626495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng Offset = -Offset; 14636495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng isSub = true; 14646495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 14656495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 14666495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Attempt to fold address comp. if opcode has offset bits 14676495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (NumBits > 0) { 14686495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Common case: small offset, fits into instruction. 14696495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MachineOperand &ImmOp = MI.getOperand(ImmIdx); 14706495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng int ImmedOffset = Offset / Scale; 14716495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned Mask = (1 << NumBits) - 1; 14726495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if ((unsigned)Offset <= Mask * Scale) { 14736495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Replace the FrameIndex with sp 14746495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false); 147577aee8e22c36257716c2df2f275724765704f20cJim Grosbach // FIXME: When addrmode2 goes away, this will simplify (like the 147677aee8e22c36257716c2df2f275724765704f20cJim Grosbach // T2 version), as the LDR.i12 versions don't need the encoding 147777aee8e22c36257716c2df2f275724765704f20cJim Grosbach // tricks for the offset value. 147877aee8e22c36257716c2df2f275724765704f20cJim Grosbach if (isSub) { 147977aee8e22c36257716c2df2f275724765704f20cJim Grosbach if (AddrMode == ARMII::AddrMode_i12) 148077aee8e22c36257716c2df2f275724765704f20cJim Grosbach ImmedOffset = -ImmedOffset; 148177aee8e22c36257716c2df2f275724765704f20cJim Grosbach else 148277aee8e22c36257716c2df2f275724765704f20cJim Grosbach ImmedOffset |= 1 << NumBits; 148377aee8e22c36257716c2df2f275724765704f20cJim Grosbach } 14846495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ImmOp.ChangeToImmediate(ImmedOffset); 1485cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng Offset = 0; 1486cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng return true; 14876495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 1488764ab52dd80310a205c9888bf166d09dab858f90Jim Grosbach 14896495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Otherwise, it didn't fit. Pull in what we can to simplify the immed. 14906495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ImmedOffset = ImmedOffset & Mask; 1491063efbf569e46776093ddf50099c98fdbb362167Jim Grosbach if (isSub) { 1492063efbf569e46776093ddf50099c98fdbb362167Jim Grosbach if (AddrMode == ARMII::AddrMode_i12) 1493063efbf569e46776093ddf50099c98fdbb362167Jim Grosbach ImmedOffset = -ImmedOffset; 1494063efbf569e46776093ddf50099c98fdbb362167Jim Grosbach else 1495063efbf569e46776093ddf50099c98fdbb362167Jim Grosbach ImmedOffset |= 1 << NumBits; 1496063efbf569e46776093ddf50099c98fdbb362167Jim Grosbach } 14976495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ImmOp.ChangeToImmediate(ImmedOffset); 14986495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng Offset &= ~(Mask*Scale); 14996495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 15006495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 15016495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 1502cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng Offset = (isSub) ? -Offset : Offset; 1503cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng return Offset == 0; 15046495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng} 1505e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling 1506e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendlingbool ARMBaseInstrInfo:: 1507a99c3e9acd95f5fbfb611e3f807240cd74001142Eric ChristopherAnalyzeCompare(const MachineInstr *MI, unsigned &SrcReg, int &CmpMask, 1508a99c3e9acd95f5fbfb611e3f807240cd74001142Eric Christopher int &CmpValue) const { 1509e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling switch (MI->getOpcode()) { 1510e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling default: break; 151138ae997e63e3e1bb2c8679e01ea74cf8fd0be893Bill Wendling case ARM::CMPri: 1512e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling case ARM::t2CMPri: 1513e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling SrcReg = MI->getOperand(0).getReg(); 151404ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif CmpMask = ~0; 1515e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling CmpValue = MI->getOperand(1).getImm(); 1516e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling return true; 151704ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif case ARM::TSTri: 151804ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif case ARM::t2TSTri: 151904ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif SrcReg = MI->getOperand(0).getReg(); 152004ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif CmpMask = MI->getOperand(1).getImm(); 152104ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif CmpValue = 0; 152204ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif return true; 152304ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif } 152404ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif 152504ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif return false; 152604ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif} 152704ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif 152805642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif/// isSuitableForMask - Identify a suitable 'and' instruction that 152905642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif/// operates on the given source register and applies the same mask 153005642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif/// as a 'tst' instruction. Provide a limited look-through for copies. 153105642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif/// When successful, MI will hold the found instruction. 153205642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greifstatic bool isSuitableForMask(MachineInstr *&MI, unsigned SrcReg, 15338ff9bb189ce188452e6cae6ed65cb2745814126cGabor Greif int CmpMask, bool CommonUse) { 153405642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif switch (MI->getOpcode()) { 153504ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif case ARM::ANDri: 153604ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif case ARM::t2ANDri: 153705642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif if (CmpMask != MI->getOperand(2).getImm()) 15388ff9bb189ce188452e6cae6ed65cb2745814126cGabor Greif return false; 153905642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif if (SrcReg == MI->getOperand(CommonUse ? 1 : 0).getReg()) 154004ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif return true; 154104ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif break; 154205642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif case ARM::COPY: { 154305642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif // Walk down one instruction which is potentially an 'and'. 154405642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif const MachineInstr &Copy = *MI; 1545f000a7a212590bfd45e23c05bff5e1b683d25dd6Michael J. Spencer MachineBasicBlock::iterator AND( 1546f000a7a212590bfd45e23c05bff5e1b683d25dd6Michael J. Spencer llvm::next(MachineBasicBlock::iterator(MI))); 154705642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif if (AND == MI->getParent()->end()) return false; 154805642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif MI = AND; 154905642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif return isSuitableForMask(MI, Copy.getOperand(0).getReg(), 155005642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif CmpMask, true); 155105642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif } 1552e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling } 1553e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling 1554e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling return false; 1555e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling} 1556e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling 1557a65568676d0d9d53dd4aae8f1c58271bb4cfff10Bill Wendling/// OptimizeCompareInstr - Convert the instruction supplying the argument to the 1558eb96a2f6c03c0ec97c56a3493ac38024afacc774Evan Cheng/// comparison into one that sets the zero bit in the flags register. 1559e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendlingbool ARMBaseInstrInfo:: 156004ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor GreifOptimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, int CmpMask, 1561eb96a2f6c03c0ec97c56a3493ac38024afacc774Evan Cheng int CmpValue, const MachineRegisterInfo *MRI) const { 15623665661a5708c8adc2727be38b56d1d87ddeb661Bill Wendling if (CmpValue != 0) 156392ad57f066e9f256e4e3d72febf152e68caa80c7Bill Wendling return false; 156492ad57f066e9f256e4e3d72febf152e68caa80c7Bill Wendling 1565b41ee96d76ccf1eec2fd898def4cfd7c16868708Bill Wendling MachineRegisterInfo::def_iterator DI = MRI->def_begin(SrcReg); 1566b41ee96d76ccf1eec2fd898def4cfd7c16868708Bill Wendling if (llvm::next(DI) != MRI->def_end()) 156792ad57f066e9f256e4e3d72febf152e68caa80c7Bill Wendling // Only support one definition. 156892ad57f066e9f256e4e3d72febf152e68caa80c7Bill Wendling return false; 156992ad57f066e9f256e4e3d72febf152e68caa80c7Bill Wendling 157092ad57f066e9f256e4e3d72febf152e68caa80c7Bill Wendling MachineInstr *MI = &*DI; 157192ad57f066e9f256e4e3d72febf152e68caa80c7Bill Wendling 157204ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif // Masked compares sometimes use the same register as the corresponding 'and'. 157304ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif if (CmpMask != ~0) { 157405642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif if (!isSuitableForMask(MI, SrcReg, CmpMask, false)) { 157504ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif MI = 0; 1576b41ee96d76ccf1eec2fd898def4cfd7c16868708Bill Wendling for (MachineRegisterInfo::use_iterator UI = MRI->use_begin(SrcReg), 1577b41ee96d76ccf1eec2fd898def4cfd7c16868708Bill Wendling UE = MRI->use_end(); UI != UE; ++UI) { 157804ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif if (UI->getParent() != CmpInstr->getParent()) continue; 157905642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif MachineInstr *PotentialAND = &*UI; 15808ff9bb189ce188452e6cae6ed65cb2745814126cGabor Greif if (!isSuitableForMask(PotentialAND, SrcReg, CmpMask, true)) 158104ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif continue; 158205642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif MI = PotentialAND; 158304ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif break; 158404ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif } 158504ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif if (!MI) return false; 158604ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif } 158704ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif } 158804ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif 1589e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling // Conservatively refuse to convert an instruction which isn't in the same BB 1590e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling // as the comparison. 1591e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling if (MI->getParent() != CmpInstr->getParent()) 1592e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling return false; 1593e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling 1594e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling // Check that CPSR isn't set between the comparison instruction and the one we 1595e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling // want to change. 1596691e64a54ce899409abe7c131d15ed75e3c1fef5Evan Cheng MachineBasicBlock::const_iterator I = CmpInstr, E = MI, 1597691e64a54ce899409abe7c131d15ed75e3c1fef5Evan Cheng B = MI->getParent()->begin(); 15980aa38b9381a5be42abd4f5ca5baa8c2930d148d3Bill Wendling 15990aa38b9381a5be42abd4f5ca5baa8c2930d148d3Bill Wendling // Early exit if CmpInstr is at the beginning of the BB. 16000aa38b9381a5be42abd4f5ca5baa8c2930d148d3Bill Wendling if (I == B) return false; 16010aa38b9381a5be42abd4f5ca5baa8c2930d148d3Bill Wendling 1602e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling --I; 1603e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling for (; I != E; --I) { 1604e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling const MachineInstr &Instr = *I; 1605e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling 1606e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling for (unsigned IO = 0, EO = Instr.getNumOperands(); IO != EO; ++IO) { 1607e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling const MachineOperand &MO = Instr.getOperand(IO); 160840a5eb18b031fa1a5e9697e21e251e613d441cc5Bill Wendling if (!MO.isReg()) continue; 1609e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling 161040a5eb18b031fa1a5e9697e21e251e613d441cc5Bill Wendling // This instruction modifies or uses CPSR after the one we want to 161140a5eb18b031fa1a5e9697e21e251e613d441cc5Bill Wendling // change. We can't do this transformation. 1612e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling if (MO.getReg() == ARM::CPSR) 1613e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling return false; 1614e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling } 1615691e64a54ce899409abe7c131d15ed75e3c1fef5Evan Cheng 1616691e64a54ce899409abe7c131d15ed75e3c1fef5Evan Cheng if (I == B) 1617691e64a54ce899409abe7c131d15ed75e3c1fef5Evan Cheng // The 'and' is below the comparison instruction. 1618691e64a54ce899409abe7c131d15ed75e3c1fef5Evan Cheng return false; 1619e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling } 1620e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling 1621e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling // Set the "zero" bit in CPSR. 1622e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling switch (MI->getOpcode()) { 1623e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling default: break; 1624ca3f6a3925e9a6e91022aa211bdc1b6e3f2ff41fCameron Zwarich case ARM::RSBrr: 1625df298c9ea64eb335f63fc075d8ef6306682ffe75Owen Anderson case ARM::RSBri: 1626ca3f6a3925e9a6e91022aa211bdc1b6e3f2ff41fCameron Zwarich case ARM::RSCrr: 1627df298c9ea64eb335f63fc075d8ef6306682ffe75Owen Anderson case ARM::RSCri: 1628ca3f6a3925e9a6e91022aa211bdc1b6e3f2ff41fCameron Zwarich case ARM::ADDrr: 162938ae997e63e3e1bb2c8679e01ea74cf8fd0be893Bill Wendling case ARM::ADDri: 1630ca3f6a3925e9a6e91022aa211bdc1b6e3f2ff41fCameron Zwarich case ARM::ADCrr: 1631df298c9ea64eb335f63fc075d8ef6306682ffe75Owen Anderson case ARM::ADCri: 1632ca3f6a3925e9a6e91022aa211bdc1b6e3f2ff41fCameron Zwarich case ARM::SUBrr: 163338ae997e63e3e1bb2c8679e01ea74cf8fd0be893Bill Wendling case ARM::SUBri: 1634ca3f6a3925e9a6e91022aa211bdc1b6e3f2ff41fCameron Zwarich case ARM::SBCrr: 1635df298c9ea64eb335f63fc075d8ef6306682ffe75Owen Anderson case ARM::SBCri: 1636df298c9ea64eb335f63fc075d8ef6306682ffe75Owen Anderson case ARM::t2RSBri: 1637ca3f6a3925e9a6e91022aa211bdc1b6e3f2ff41fCameron Zwarich case ARM::t2ADDrr: 163838ae997e63e3e1bb2c8679e01ea74cf8fd0be893Bill Wendling case ARM::t2ADDri: 1639ca3f6a3925e9a6e91022aa211bdc1b6e3f2ff41fCameron Zwarich case ARM::t2ADCrr: 1640df298c9ea64eb335f63fc075d8ef6306682ffe75Owen Anderson case ARM::t2ADCri: 1641ca3f6a3925e9a6e91022aa211bdc1b6e3f2ff41fCameron Zwarich case ARM::t2SUBrr: 1642df298c9ea64eb335f63fc075d8ef6306682ffe75Owen Anderson case ARM::t2SUBri: 1643ca3f6a3925e9a6e91022aa211bdc1b6e3f2ff41fCameron Zwarich case ARM::t2SBCrr: 1644b485de5d8c3fe0c62c0b07f63f64bd10f6803c17Cameron Zwarich case ARM::t2SBCri: 1645b485de5d8c3fe0c62c0b07f63f64bd10f6803c17Cameron Zwarich case ARM::ANDrr: 1646b485de5d8c3fe0c62c0b07f63f64bd10f6803c17Cameron Zwarich case ARM::ANDri: 1647b485de5d8c3fe0c62c0b07f63f64bd10f6803c17Cameron Zwarich case ARM::t2ANDrr: 16480cb11ac32fc09c5db42fb801db242ac9fb51f6b1Cameron Zwarich case ARM::t2ANDri: 16490cb11ac32fc09c5db42fb801db242ac9fb51f6b1Cameron Zwarich case ARM::ORRrr: 16500cb11ac32fc09c5db42fb801db242ac9fb51f6b1Cameron Zwarich case ARM::ORRri: 16510cb11ac32fc09c5db42fb801db242ac9fb51f6b1Cameron Zwarich case ARM::t2ORRrr: 16520cb11ac32fc09c5db42fb801db242ac9fb51f6b1Cameron Zwarich case ARM::t2ORRri: 16530cb11ac32fc09c5db42fb801db242ac9fb51f6b1Cameron Zwarich case ARM::EORrr: 16540cb11ac32fc09c5db42fb801db242ac9fb51f6b1Cameron Zwarich case ARM::EORri: 16550cb11ac32fc09c5db42fb801db242ac9fb51f6b1Cameron Zwarich case ARM::t2EORrr: 16560cb11ac32fc09c5db42fb801db242ac9fb51f6b1Cameron Zwarich case ARM::t2EORri: { 16572c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng // Scan forward for the use of CPSR, if it's a conditional code requires 16582c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng // checking of V bit, then this is not safe to do. If we can't find the 16592c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng // CPSR use (i.e. used in another block), then it's not safe to perform 16602c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng // the optimization. 16612c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng bool isSafe = false; 16622c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng I = CmpInstr; 16632c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng E = MI->getParent()->end(); 16642c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng while (!isSafe && ++I != E) { 16652c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng const MachineInstr &Instr = *I; 16662c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng for (unsigned IO = 0, EO = Instr.getNumOperands(); 16672c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng !isSafe && IO != EO; ++IO) { 16682c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng const MachineOperand &MO = Instr.getOperand(IO); 16692c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng if (!MO.isReg() || MO.getReg() != ARM::CPSR) 16702c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng continue; 16712c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng if (MO.isDef()) { 16722c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng isSafe = true; 16732c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng break; 16742c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng } 16752c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng // Condition code is after the operand before CPSR. 16762c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng ARMCC::CondCodes CC = (ARMCC::CondCodes)Instr.getOperand(IO-1).getImm(); 16772c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng switch (CC) { 16782c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng default: 16792c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng isSafe = true; 16802c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng break; 16812c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng case ARMCC::VS: 16822c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng case ARMCC::VC: 16832c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng case ARMCC::GE: 16842c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng case ARMCC::LT: 16852c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng case ARMCC::GT: 16862c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng case ARMCC::LE: 16872c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng return false; 16882c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng } 16892c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng } 16902c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng } 16912c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng 16922c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng if (!isSafe) 16932c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng return false; 16942c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng 16953642e64c114e636548888c72c21ae023ee0121a7Evan Cheng // Toggle the optional operand to CPSR. 16963642e64c114e636548888c72c21ae023ee0121a7Evan Cheng MI->getOperand(5).setReg(ARM::CPSR); 16973642e64c114e636548888c72c21ae023ee0121a7Evan Cheng MI->getOperand(5).setIsDef(true); 1698e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling CmpInstr->eraseFromParent(); 1699e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling return true; 1700e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling } 1701b485de5d8c3fe0c62c0b07f63f64bd10f6803c17Cameron Zwarich } 1702e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling 1703e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling return false; 1704e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling} 17055f54ce347368105260be2cec497b6a4199dc5789Evan Cheng 1706c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Chengbool ARMBaseInstrInfo::FoldImmediate(MachineInstr *UseMI, 1707c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng MachineInstr *DefMI, unsigned Reg, 1708c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng MachineRegisterInfo *MRI) const { 1709c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng // Fold large immediates into add, sub, or, xor. 1710c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng unsigned DefOpc = DefMI->getOpcode(); 1711c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng if (DefOpc != ARM::t2MOVi32imm && DefOpc != ARM::MOVi32imm) 1712c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng return false; 1713c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng if (!DefMI->getOperand(1).isImm()) 1714c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng // Could be t2MOVi32imm <ga:xx> 1715c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng return false; 1716c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng 1717c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng if (!MRI->hasOneNonDBGUse(Reg)) 1718c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng return false; 1719c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng 1720c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng unsigned UseOpc = UseMI->getOpcode(); 17215c71c7a13715ed6f5bfdd5497172ddec316b68b0Evan Cheng unsigned NewUseOpc = 0; 1722c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng uint32_t ImmVal = (uint32_t)DefMI->getOperand(1).getImm(); 17235c71c7a13715ed6f5bfdd5497172ddec316b68b0Evan Cheng uint32_t SOImmValV1 = 0, SOImmValV2 = 0; 1724c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng bool Commute = false; 1725c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng switch (UseOpc) { 1726c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng default: return false; 1727c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::SUBrr: 1728c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::ADDrr: 1729c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::ORRrr: 1730c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::EORrr: 1731c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::t2SUBrr: 1732c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::t2ADDrr: 1733c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::t2ORRrr: 1734c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::t2EORrr: { 1735c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng Commute = UseMI->getOperand(2).getReg() != Reg; 1736c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng switch (UseOpc) { 1737c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng default: break; 1738c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::SUBrr: { 1739c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng if (Commute) 1740c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng return false; 1741c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng ImmVal = -ImmVal; 1742c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng NewUseOpc = ARM::SUBri; 1743c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng // Fallthrough 1744c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng } 1745c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::ADDrr: 1746c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::ORRrr: 1747c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::EORrr: { 1748c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng if (!ARM_AM::isSOImmTwoPartVal(ImmVal)) 1749c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng return false; 1750c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng SOImmValV1 = (uint32_t)ARM_AM::getSOImmTwoPartFirst(ImmVal); 1751c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng SOImmValV2 = (uint32_t)ARM_AM::getSOImmTwoPartSecond(ImmVal); 1752c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng switch (UseOpc) { 1753c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng default: break; 1754c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::ADDrr: NewUseOpc = ARM::ADDri; break; 1755c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::ORRrr: NewUseOpc = ARM::ORRri; break; 1756c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::EORrr: NewUseOpc = ARM::EORri; break; 1757c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng } 1758c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng break; 1759c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng } 1760c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::t2SUBrr: { 1761c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng if (Commute) 1762c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng return false; 1763c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng ImmVal = -ImmVal; 1764c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng NewUseOpc = ARM::t2SUBri; 1765c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng // Fallthrough 1766c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng } 1767c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::t2ADDrr: 1768c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::t2ORRrr: 1769c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::t2EORrr: { 1770c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng if (!ARM_AM::isT2SOImmTwoPartVal(ImmVal)) 1771c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng return false; 1772c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng SOImmValV1 = (uint32_t)ARM_AM::getT2SOImmTwoPartFirst(ImmVal); 1773c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng SOImmValV2 = (uint32_t)ARM_AM::getT2SOImmTwoPartSecond(ImmVal); 1774c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng switch (UseOpc) { 1775c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng default: break; 1776c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::t2ADDrr: NewUseOpc = ARM::t2ADDri; break; 1777c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::t2ORRrr: NewUseOpc = ARM::t2ORRri; break; 1778c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::t2EORrr: NewUseOpc = ARM::t2EORri; break; 1779c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng } 1780c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng break; 1781c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng } 1782c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng } 1783c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng } 1784c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng } 1785c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng 1786c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng unsigned OpIdx = Commute ? 2 : 1; 1787c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng unsigned Reg1 = UseMI->getOperand(OpIdx).getReg(); 1788c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng bool isKill = UseMI->getOperand(OpIdx).isKill(); 1789c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng unsigned NewReg = MRI->createVirtualRegister(MRI->getRegClass(Reg)); 1790c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng AddDefaultCC(AddDefaultPred(BuildMI(*UseMI->getParent(), 1791c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng *UseMI, UseMI->getDebugLoc(), 1792c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng get(NewUseOpc), NewReg) 1793c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng .addReg(Reg1, getKillRegState(isKill)) 1794c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng .addImm(SOImmValV1))); 1795c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng UseMI->setDesc(get(NewUseOpc)); 1796c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng UseMI->getOperand(1).setReg(NewReg); 1797c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng UseMI->getOperand(1).setIsKill(); 1798c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng UseMI->getOperand(2).ChangeToImmediate(SOImmValV2); 1799c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng DefMI->eraseFromParent(); 1800c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng return true; 1801c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng} 1802c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng 18035f54ce347368105260be2cec497b6a4199dc5789Evan Chengunsigned 18048239daf7c83a65a189c352cce3191cdc3bbfe151Evan ChengARMBaseInstrInfo::getNumMicroOps(const InstrItineraryData *ItinData, 18058239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng const MachineInstr *MI) const { 18063ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng if (!ItinData || ItinData->isEmpty()) 18075f54ce347368105260be2cec497b6a4199dc5789Evan Cheng return 1; 18085f54ce347368105260be2cec497b6a4199dc5789Evan Cheng 1809e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng const MCInstrDesc &Desc = MI->getDesc(); 18105f54ce347368105260be2cec497b6a4199dc5789Evan Cheng unsigned Class = Desc.getSchedClass(); 1811064312de8641043b084603aa9a6b409bc794eed2Bob Wilson unsigned UOps = ItinData->Itineraries[Class].NumMicroOps; 18125f54ce347368105260be2cec497b6a4199dc5789Evan Cheng if (UOps) 18135f54ce347368105260be2cec497b6a4199dc5789Evan Cheng return UOps; 18145f54ce347368105260be2cec497b6a4199dc5789Evan Cheng 18155f54ce347368105260be2cec497b6a4199dc5789Evan Cheng unsigned Opc = MI->getOpcode(); 18165f54ce347368105260be2cec497b6a4199dc5789Evan Cheng switch (Opc) { 18175f54ce347368105260be2cec497b6a4199dc5789Evan Cheng default: 18185f54ce347368105260be2cec497b6a4199dc5789Evan Cheng llvm_unreachable("Unexpected multi-uops instruction!"); 18195f54ce347368105260be2cec497b6a4199dc5789Evan Cheng break; 182073fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMQIA: 182173fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMQIA: 18225f54ce347368105260be2cec497b6a4199dc5789Evan Cheng return 2; 18235f54ce347368105260be2cec497b6a4199dc5789Evan Cheng 18245f54ce347368105260be2cec497b6a4199dc5789Evan Cheng // The number of uOps for load / store multiple are determined by the number 18255f54ce347368105260be2cec497b6a4199dc5789Evan Cheng // registers. 18266e8f4c404825b79f9b9176483653f1aa927dfbdeAndrew Trick // 18273ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng // On Cortex-A8, each pair of register loads / stores can be scheduled on the 18283ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng // same cycle. The scheduling for the first load / store must be done 18293ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng // separately by assuming the the address is not 64-bit aligned. 183073fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling // 18313ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng // On Cortex-A9, the formula is simply (#reg / 2) + (#reg % 2). If the address 183273fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling // is not 64-bit aligned, then AGU would take an extra cycle. For VFP / NEON 183373fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling // load / store multiple, the formula is (#reg / 2) + (#reg % 2) + 1. 183473fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMDIA: 183573fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMDIA_UPD: 183673fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMDDB_UPD: 183773fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMSIA: 183873fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMSIA_UPD: 183973fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMSDB_UPD: 184073fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMDIA: 184173fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMDIA_UPD: 184273fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMDDB_UPD: 184373fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMSIA: 184473fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMSIA_UPD: 184573fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMSDB_UPD: { 18465f54ce347368105260be2cec497b6a4199dc5789Evan Cheng unsigned NumRegs = MI->getNumOperands() - Desc.getNumOperands(); 18475f54ce347368105260be2cec497b6a4199dc5789Evan Cheng return (NumRegs / 2) + (NumRegs % 2) + 1; 18485f54ce347368105260be2cec497b6a4199dc5789Evan Cheng } 184973fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling 185073fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMIA_RET: 185173fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMIA: 185273fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMDA: 185373fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMDB: 185473fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMIB: 185573fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMIA_UPD: 185673fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMDA_UPD: 185773fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMDB_UPD: 185873fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMIB_UPD: 185973fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::STMIA: 186073fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::STMDA: 186173fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::STMDB: 186273fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::STMIB: 186373fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::STMIA_UPD: 186473fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::STMDA_UPD: 186573fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::STMDB_UPD: 186673fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::STMIB_UPD: 186773fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::tLDMIA: 186873fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::tLDMIA_UPD: 186973fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::tSTMIA: 187073fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::tSTMIA_UPD: 18715f54ce347368105260be2cec497b6a4199dc5789Evan Cheng case ARM::tPOP_RET: 18725f54ce347368105260be2cec497b6a4199dc5789Evan Cheng case ARM::tPOP: 18735f54ce347368105260be2cec497b6a4199dc5789Evan Cheng case ARM::tPUSH: 187473fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2LDMIA_RET: 187573fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2LDMIA: 187673fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2LDMDB: 187773fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2LDMIA_UPD: 187873fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2LDMDB_UPD: 187973fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2STMIA: 188073fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2STMDB: 188173fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2STMIA_UPD: 188273fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2STMDB_UPD: { 18833ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng unsigned NumRegs = MI->getNumOperands() - Desc.getNumOperands() + 1; 18843ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng if (Subtarget.isCortexA8()) { 18858239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng if (NumRegs < 4) 18868239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng return 2; 18878239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng // 4 registers would be issued: 2, 2. 18888239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng // 5 registers would be issued: 2, 2, 1. 18898239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng UOps = (NumRegs / 2); 18908239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng if (NumRegs % 2) 18918239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng ++UOps; 18928239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng return UOps; 18933ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng } else if (Subtarget.isCortexA9()) { 18943ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng UOps = (NumRegs / 2); 18953ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng // If there are odd number of registers or if it's not 64-bit aligned, 18963ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng // then it takes an extra AGU (Address Generation Unit) cycle. 18973ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng if ((NumRegs % 2) || 18983ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng !MI->hasOneMemOperand() || 18993ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng (*MI->memoperands_begin())->getAlignment() < 8) 19003ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng ++UOps; 19013ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng return UOps; 19023ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng } else { 19033ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng // Assume the worst. 19043ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng return NumRegs; 19052bbb76909126db5bed6bde84b16d94ab5de4d372Michael J. Spencer } 19065f54ce347368105260be2cec497b6a4199dc5789Evan Cheng } 19075f54ce347368105260be2cec497b6a4199dc5789Evan Cheng } 19085f54ce347368105260be2cec497b6a4199dc5789Evan Cheng} 1909a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng 1910a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Chengint 1911344d9db97062736cd66da6c07baa9108b6cfa419Evan ChengARMBaseInstrInfo::getVLDMDefCycle(const InstrItineraryData *ItinData, 1912e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng const MCInstrDesc &DefMCID, 1913344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng unsigned DefClass, 1914344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng unsigned DefIdx, unsigned DefAlign) const { 1915e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng int RegNo = (int)(DefIdx+1) - DefMCID.getNumOperands() + 1; 1916344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng if (RegNo <= 0) 1917344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // Def is the address writeback. 1918344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng return ItinData->getOperandCycle(DefClass, DefIdx); 1919344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng 1920344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng int DefCycle; 1921344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng if (Subtarget.isCortexA8()) { 1922344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // (regno / 2) + (regno % 2) + 1 1923344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng DefCycle = RegNo / 2 + 1; 1924344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng if (RegNo % 2) 1925344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng ++DefCycle; 1926344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng } else if (Subtarget.isCortexA9()) { 1927344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng DefCycle = RegNo; 1928344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng bool isSLoad = false; 192973fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling 1930e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng switch (DefMCID.getOpcode()) { 1931344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng default: break; 193273fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMSIA: 193373fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMSIA_UPD: 193473fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMSDB_UPD: 1935344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng isSLoad = true; 1936344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng break; 1937344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng } 193873fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling 1939344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // If there are odd number of 'S' registers or if it's not 64-bit aligned, 1940344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // then it takes an extra cycle. 1941344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng if ((isSLoad && (RegNo % 2)) || DefAlign < 8) 1942344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng ++DefCycle; 1943344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng } else { 1944344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // Assume the worst. 1945344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng DefCycle = RegNo + 2; 1946344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng } 1947344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng 1948344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng return DefCycle; 1949344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng} 1950344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng 1951344d9db97062736cd66da6c07baa9108b6cfa419Evan Chengint 1952344d9db97062736cd66da6c07baa9108b6cfa419Evan ChengARMBaseInstrInfo::getLDMDefCycle(const InstrItineraryData *ItinData, 1953e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng const MCInstrDesc &DefMCID, 1954344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng unsigned DefClass, 1955344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng unsigned DefIdx, unsigned DefAlign) const { 1956e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng int RegNo = (int)(DefIdx+1) - DefMCID.getNumOperands() + 1; 1957344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng if (RegNo <= 0) 1958344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // Def is the address writeback. 1959344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng return ItinData->getOperandCycle(DefClass, DefIdx); 1960344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng 1961344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng int DefCycle; 1962344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng if (Subtarget.isCortexA8()) { 1963344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // 4 registers would be issued: 1, 2, 1. 1964344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // 5 registers would be issued: 1, 2, 2. 1965344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng DefCycle = RegNo / 2; 1966344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng if (DefCycle < 1) 1967344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng DefCycle = 1; 1968344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // Result latency is issue cycle + 2: E2. 1969344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng DefCycle += 2; 1970344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng } else if (Subtarget.isCortexA9()) { 1971344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng DefCycle = (RegNo / 2); 1972344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // If there are odd number of registers or if it's not 64-bit aligned, 1973344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // then it takes an extra AGU (Address Generation Unit) cycle. 1974344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng if ((RegNo % 2) || DefAlign < 8) 1975344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng ++DefCycle; 1976344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // Result latency is AGU cycles + 2. 1977344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng DefCycle += 2; 1978344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng } else { 1979344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // Assume the worst. 1980344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng DefCycle = RegNo + 2; 1981344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng } 1982344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng 1983344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng return DefCycle; 1984344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng} 1985344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng 1986344d9db97062736cd66da6c07baa9108b6cfa419Evan Chengint 1987344d9db97062736cd66da6c07baa9108b6cfa419Evan ChengARMBaseInstrInfo::getVSTMUseCycle(const InstrItineraryData *ItinData, 1988e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng const MCInstrDesc &UseMCID, 1989344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng unsigned UseClass, 1990344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng unsigned UseIdx, unsigned UseAlign) const { 1991e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng int RegNo = (int)(UseIdx+1) - UseMCID.getNumOperands() + 1; 1992344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng if (RegNo <= 0) 1993344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng return ItinData->getOperandCycle(UseClass, UseIdx); 1994344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng 1995344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng int UseCycle; 1996344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng if (Subtarget.isCortexA8()) { 1997344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // (regno / 2) + (regno % 2) + 1 1998344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng UseCycle = RegNo / 2 + 1; 1999344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng if (RegNo % 2) 2000344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng ++UseCycle; 2001344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng } else if (Subtarget.isCortexA9()) { 2002344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng UseCycle = RegNo; 2003344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng bool isSStore = false; 200473fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling 2005e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng switch (UseMCID.getOpcode()) { 2006344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng default: break; 200773fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMSIA: 200873fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMSIA_UPD: 200973fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMSDB_UPD: 2010344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng isSStore = true; 2011344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng break; 2012344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng } 201373fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling 2014344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // If there are odd number of 'S' registers or if it's not 64-bit aligned, 2015344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // then it takes an extra cycle. 2016344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng if ((isSStore && (RegNo % 2)) || UseAlign < 8) 2017344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng ++UseCycle; 2018344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng } else { 2019344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // Assume the worst. 2020344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng UseCycle = RegNo + 2; 2021344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng } 2022344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng 2023344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng return UseCycle; 2024344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng} 2025344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng 2026344d9db97062736cd66da6c07baa9108b6cfa419Evan Chengint 2027344d9db97062736cd66da6c07baa9108b6cfa419Evan ChengARMBaseInstrInfo::getSTMUseCycle(const InstrItineraryData *ItinData, 2028e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng const MCInstrDesc &UseMCID, 2029344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng unsigned UseClass, 2030344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng unsigned UseIdx, unsigned UseAlign) const { 2031e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng int RegNo = (int)(UseIdx+1) - UseMCID.getNumOperands() + 1; 2032344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng if (RegNo <= 0) 2033344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng return ItinData->getOperandCycle(UseClass, UseIdx); 2034344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng 2035344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng int UseCycle; 2036344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng if (Subtarget.isCortexA8()) { 2037344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng UseCycle = RegNo / 2; 2038344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng if (UseCycle < 2) 2039344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng UseCycle = 2; 2040344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // Read in E3. 2041344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng UseCycle += 2; 2042344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng } else if (Subtarget.isCortexA9()) { 2043344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng UseCycle = (RegNo / 2); 2044344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // If there are odd number of registers or if it's not 64-bit aligned, 2045344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // then it takes an extra AGU (Address Generation Unit) cycle. 2046344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng if ((RegNo % 2) || UseAlign < 8) 2047344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng ++UseCycle; 2048344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng } else { 2049344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // Assume the worst. 2050344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng UseCycle = 1; 2051344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng } 2052344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng return UseCycle; 2053344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng} 2054344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng 2055344d9db97062736cd66da6c07baa9108b6cfa419Evan Chengint 2056a0792de66c8364d47b0a688c7f408efb7b10f31bEvan ChengARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData, 2057e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng const MCInstrDesc &DefMCID, 2058a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng unsigned DefIdx, unsigned DefAlign, 2059e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng const MCInstrDesc &UseMCID, 2060a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng unsigned UseIdx, unsigned UseAlign) const { 2061e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng unsigned DefClass = DefMCID.getSchedClass(); 2062e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng unsigned UseClass = UseMCID.getSchedClass(); 2063a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng 2064e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng if (DefIdx < DefMCID.getNumDefs() && UseIdx < UseMCID.getNumOperands()) 2065a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx); 2066a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng 2067a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng // This may be a def / use of a variable_ops instruction, the operand 2068a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng // latency might be determinable dynamically. Let the target try to 2069a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng // figure it out. 20709e08ee5d16b596078e20787f0b5f36121f099333Evan Cheng int DefCycle = -1; 20717e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng bool LdmBypass = false; 2072e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng switch (DefMCID.getOpcode()) { 2073a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng default: 2074a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng DefCycle = ItinData->getOperandCycle(DefClass, DefIdx); 2075a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng break; 207673fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling 207773fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMDIA: 207873fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMDIA_UPD: 207973fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMDDB_UPD: 208073fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMSIA: 208173fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMSIA_UPD: 208273fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMSDB_UPD: 2083e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng DefCycle = getVLDMDefCycle(ItinData, DefMCID, DefClass, DefIdx, DefAlign); 20845a50ceeaea980962c1982ad535226c7ab06c971cEvan Cheng break; 208573fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling 208673fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMIA_RET: 208773fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMIA: 208873fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMDA: 208973fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMDB: 209073fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMIB: 209173fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMIA_UPD: 209273fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMDA_UPD: 209373fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMDB_UPD: 209473fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMIB_UPD: 209573fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::tLDMIA: 209673fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::tLDMIA_UPD: 2097a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng case ARM::tPUSH: 209873fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2LDMIA_RET: 209973fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2LDMIA: 210073fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2LDMDB: 210173fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2LDMIA_UPD: 210273fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2LDMDB_UPD: 2103a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng LdmBypass = 1; 2104e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng DefCycle = getLDMDefCycle(ItinData, DefMCID, DefClass, DefIdx, DefAlign); 2105344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng break; 2106a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng } 2107a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng 2108a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng if (DefCycle == -1) 2109a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng // We can't seem to determine the result latency of the def, assume it's 2. 2110a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng DefCycle = 2; 2111a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng 2112a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng int UseCycle = -1; 2113e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng switch (UseMCID.getOpcode()) { 2114a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng default: 2115a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng UseCycle = ItinData->getOperandCycle(UseClass, UseIdx); 2116a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng break; 211773fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling 211873fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMDIA: 211973fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMDIA_UPD: 212073fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMDDB_UPD: 212173fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMSIA: 212273fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMSIA_UPD: 212373fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMSDB_UPD: 2124e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng UseCycle = getVSTMUseCycle(ItinData, UseMCID, UseClass, UseIdx, UseAlign); 21255a50ceeaea980962c1982ad535226c7ab06c971cEvan Cheng break; 212673fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling 212773fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::STMIA: 212873fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::STMDA: 212973fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::STMDB: 213073fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::STMIB: 213173fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::STMIA_UPD: 213273fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::STMDA_UPD: 213373fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::STMDB_UPD: 213473fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::STMIB_UPD: 213573fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::tSTMIA: 213673fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::tSTMIA_UPD: 2137a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng case ARM::tPOP_RET: 2138a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng case ARM::tPOP: 213973fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2STMIA: 214073fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2STMDB: 214173fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2STMIA_UPD: 214273fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2STMDB_UPD: 2143e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng UseCycle = getSTMUseCycle(ItinData, UseMCID, UseClass, UseIdx, UseAlign); 21445a50ceeaea980962c1982ad535226c7ab06c971cEvan Cheng break; 2145a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng } 2146a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng 2147a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng if (UseCycle == -1) 2148a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng // Assume it's read in the first stage. 2149a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng UseCycle = 1; 2150a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng 2151a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng UseCycle = DefCycle - UseCycle + 1; 2152a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng if (UseCycle > 0) { 2153a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng if (LdmBypass) { 2154a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng // It's a variable_ops instruction so we can't use DefIdx here. Just use 2155a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng // first def operand. 2156e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng if (ItinData->hasPipelineForwarding(DefClass, DefMCID.getNumOperands()-1, 2157a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng UseClass, UseIdx)) 2158a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng --UseCycle; 2159a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng } else if (ItinData->hasPipelineForwarding(DefClass, DefIdx, 216073fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling UseClass, UseIdx)) { 2161a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng --UseCycle; 216273fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling } 2163a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng } 2164a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng 2165a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng return UseCycle; 2166a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng} 2167a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng 2168a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Chengint 2169a0792de66c8364d47b0a688c7f408efb7b10f31bEvan ChengARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData, 2170a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng const MachineInstr *DefMI, unsigned DefIdx, 2171a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng const MachineInstr *UseMI, unsigned UseIdx) const { 2172a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng if (DefMI->isCopyLike() || DefMI->isInsertSubreg() || 2173a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng DefMI->isRegSequence() || DefMI->isImplicitDef()) 2174a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng return 1; 2175a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng 2176e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng const MCInstrDesc &DefMCID = DefMI->getDesc(); 2177a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng if (!ItinData || ItinData->isEmpty()) 2178e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng return DefMCID.mayLoad() ? 3 : 1; 2179a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng 2180e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng const MCInstrDesc &UseMCID = UseMI->getDesc(); 2181dd9dd6f857604abdeb5213648ffe50c10ccc59b9Evan Cheng const MachineOperand &DefMO = DefMI->getOperand(DefIdx); 2182e09206d4d7683e2a421104c5cb83f7808ba4b06eEvan Cheng if (DefMO.getReg() == ARM::CPSR) { 2183e09206d4d7683e2a421104c5cb83f7808ba4b06eEvan Cheng if (DefMI->getOpcode() == ARM::FMSTAT) { 2184e09206d4d7683e2a421104c5cb83f7808ba4b06eEvan Cheng // fpscr -> cpsr stalls over 20 cycles on A8 (and earlier?) 2185e09206d4d7683e2a421104c5cb83f7808ba4b06eEvan Cheng return Subtarget.isCortexA9() ? 1 : 20; 2186e09206d4d7683e2a421104c5cb83f7808ba4b06eEvan Cheng } 2187e09206d4d7683e2a421104c5cb83f7808ba4b06eEvan Cheng 2188dd9dd6f857604abdeb5213648ffe50c10ccc59b9Evan Cheng // CPSR set and branch can be paired in the same cycle. 2189e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng if (UseMCID.isBranch()) 2190e09206d4d7683e2a421104c5cb83f7808ba4b06eEvan Cheng return 0; 2191e09206d4d7683e2a421104c5cb83f7808ba4b06eEvan Cheng } 2192dd9dd6f857604abdeb5213648ffe50c10ccc59b9Evan Cheng 2193a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng unsigned DefAlign = DefMI->hasOneMemOperand() 2194a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng ? (*DefMI->memoperands_begin())->getAlignment() : 0; 2195a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng unsigned UseAlign = UseMI->hasOneMemOperand() 2196a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng ? (*UseMI->memoperands_begin())->getAlignment() : 0; 2197e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng int Latency = getOperandLatency(ItinData, DefMCID, DefIdx, DefAlign, 2198e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng UseMCID, UseIdx, UseAlign); 21997e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng 22007e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng if (Latency > 1 && 22017e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng (Subtarget.isCortexA8() || Subtarget.isCortexA9())) { 22027e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng // FIXME: Shifter op hack: no shift (i.e. [r +/- r]) or [r + r << 2] 22037e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng // variants are one cycle cheaper. 2204e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng switch (DefMCID.getOpcode()) { 22057e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng default: break; 22067e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng case ARM::LDRrs: 22077e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng case ARM::LDRBrs: { 22087e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng unsigned ShOpVal = DefMI->getOperand(3).getImm(); 22097e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal); 22107e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng if (ShImm == 0 || 22117e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng (ShImm == 2 && ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl)) 22127e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng --Latency; 22137e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng break; 22147e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng } 22157e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng case ARM::t2LDRs: 22167e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng case ARM::t2LDRBs: 22177e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng case ARM::t2LDRHs: 22187e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng case ARM::t2LDRSHs: { 22197e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng // Thumb2 mode: lsl only. 22207e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng unsigned ShAmt = DefMI->getOperand(3).getImm(); 22217e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng if (ShAmt == 0 || ShAmt == 2) 22227e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng --Latency; 22237e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng break; 22247e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng } 22257e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng } 22267e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng } 22277e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng 222875b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng if (DefAlign < 8 && Subtarget.isCortexA9()) 2229e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng switch (DefMCID.getOpcode()) { 223075b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng default: break; 223175b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1q8: 223275b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1q16: 223375b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1q32: 223475b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1q64: 223575b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1q8_UPD: 223675b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1q16_UPD: 223775b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1q32_UPD: 223875b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1q64_UPD: 223975b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2d8: 224075b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2d16: 224175b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2d32: 224275b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2q8: 224375b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2q16: 224475b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2q32: 224575b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2d8_UPD: 224675b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2d16_UPD: 224775b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2d32_UPD: 224875b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2q8_UPD: 224975b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2q16_UPD: 225075b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2q32_UPD: 225175b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3d8: 225275b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3d16: 225375b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3d32: 225475b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1d64T: 225575b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3d8_UPD: 225675b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3d16_UPD: 225775b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3d32_UPD: 225875b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1d64T_UPD: 225975b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3q8_UPD: 226075b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3q16_UPD: 226175b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3q32_UPD: 226275b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4d8: 226375b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4d16: 226475b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4d32: 226575b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1d64Q: 226675b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4d8_UPD: 226775b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4d16_UPD: 226875b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4d32_UPD: 226975b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1d64Q_UPD: 227075b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4q8_UPD: 227175b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4q16_UPD: 227275b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4q32_UPD: 227375b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1DUPq8: 227475b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1DUPq16: 227575b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1DUPq32: 227675b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1DUPq8_UPD: 227775b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1DUPq16_UPD: 227875b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1DUPq32_UPD: 227975b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2DUPd8: 228075b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2DUPd16: 228175b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2DUPd32: 228275b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2DUPd8_UPD: 228375b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2DUPd16_UPD: 228475b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2DUPd32_UPD: 228575b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4DUPd8: 228675b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4DUPd16: 228775b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4DUPd32: 228875b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4DUPd8_UPD: 228975b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4DUPd16_UPD: 229075b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4DUPd32_UPD: 229175b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1LNd8: 229275b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1LNd16: 229375b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1LNd32: 229475b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1LNd8_UPD: 229575b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1LNd16_UPD: 229675b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1LNd32_UPD: 229775b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2LNd8: 229875b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2LNd16: 229975b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2LNd32: 230075b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2LNq16: 230175b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2LNq32: 230275b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2LNd8_UPD: 230375b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2LNd16_UPD: 230475b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2LNd32_UPD: 230575b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2LNq16_UPD: 230675b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2LNq32_UPD: 230775b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4LNd8: 230875b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4LNd16: 230975b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4LNd32: 231075b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4LNq16: 231175b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4LNq32: 231275b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4LNd8_UPD: 231375b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4LNd16_UPD: 231475b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4LNd32_UPD: 231575b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4LNq16_UPD: 231675b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4LNq32_UPD: 231775b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng // If the address is not 64-bit aligned, the latencies of these 231875b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng // instructions increases by one. 231975b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng ++Latency; 232075b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng break; 232175b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng } 232275b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng 23237e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng return Latency; 2324a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng} 2325a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng 2326a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Chengint 2327a0792de66c8364d47b0a688c7f408efb7b10f31bEvan ChengARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData, 2328a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng SDNode *DefNode, unsigned DefIdx, 2329a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng SDNode *UseNode, unsigned UseIdx) const { 2330a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng if (!DefNode->isMachineOpcode()) 2331a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng return 1; 2332a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng 2333e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng const MCInstrDesc &DefMCID = get(DefNode->getMachineOpcode()); 2334c8bfd1d78ff9a307d1d4cb57cce4549b538e60f4Andrew Trick 2335e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng if (isZeroCost(DefMCID.Opcode)) 2336c8bfd1d78ff9a307d1d4cb57cce4549b538e60f4Andrew Trick return 0; 2337c8bfd1d78ff9a307d1d4cb57cce4549b538e60f4Andrew Trick 2338a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng if (!ItinData || ItinData->isEmpty()) 2339e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng return DefMCID.mayLoad() ? 3 : 1; 2340a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng 2341089751535d6e9adf65842e2ca5867bf9a70e1e95Evan Cheng if (!UseNode->isMachineOpcode()) { 2342e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng int Latency = ItinData->getOperandCycle(DefMCID.getSchedClass(), DefIdx); 2343089751535d6e9adf65842e2ca5867bf9a70e1e95Evan Cheng if (Subtarget.isCortexA9()) 2344089751535d6e9adf65842e2ca5867bf9a70e1e95Evan Cheng return Latency <= 2 ? 1 : Latency - 1; 2345089751535d6e9adf65842e2ca5867bf9a70e1e95Evan Cheng else 2346089751535d6e9adf65842e2ca5867bf9a70e1e95Evan Cheng return Latency <= 3 ? 1 : Latency - 2; 2347089751535d6e9adf65842e2ca5867bf9a70e1e95Evan Cheng } 2348a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng 2349e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng const MCInstrDesc &UseMCID = get(UseNode->getMachineOpcode()); 2350a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng const MachineSDNode *DefMN = dyn_cast<MachineSDNode>(DefNode); 2351a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng unsigned DefAlign = !DefMN->memoperands_empty() 2352a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng ? (*DefMN->memoperands_begin())->getAlignment() : 0; 2353a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng const MachineSDNode *UseMN = dyn_cast<MachineSDNode>(UseNode); 2354a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng unsigned UseAlign = !UseMN->memoperands_empty() 2355a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng ? (*UseMN->memoperands_begin())->getAlignment() : 0; 2356e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng int Latency = getOperandLatency(ItinData, DefMCID, DefIdx, DefAlign, 2357e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng UseMCID, UseIdx, UseAlign); 23587e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng 23597e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng if (Latency > 1 && 23607e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng (Subtarget.isCortexA8() || Subtarget.isCortexA9())) { 23617e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng // FIXME: Shifter op hack: no shift (i.e. [r +/- r]) or [r + r << 2] 23627e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng // variants are one cycle cheaper. 2363e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng switch (DefMCID.getOpcode()) { 23647e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng default: break; 23657e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng case ARM::LDRrs: 23667e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng case ARM::LDRBrs: { 23677e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng unsigned ShOpVal = 23687e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng cast<ConstantSDNode>(DefNode->getOperand(2))->getZExtValue(); 23697e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal); 23707e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng if (ShImm == 0 || 23717e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng (ShImm == 2 && ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl)) 23727e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng --Latency; 23737e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng break; 23747e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng } 23757e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng case ARM::t2LDRs: 23767e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng case ARM::t2LDRBs: 23777e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng case ARM::t2LDRHs: 23787e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng case ARM::t2LDRSHs: { 23797e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng // Thumb2 mode: lsl only. 23807e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng unsigned ShAmt = 23817e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng cast<ConstantSDNode>(DefNode->getOperand(2))->getZExtValue(); 23827e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng if (ShAmt == 0 || ShAmt == 2) 23837e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng --Latency; 23847e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng break; 23857e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng } 23867e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng } 23877e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng } 23887e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng 238975b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng if (DefAlign < 8 && Subtarget.isCortexA9()) 2390e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng switch (DefMCID.getOpcode()) { 239175b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng default: break; 239275b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1q8Pseudo: 239375b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1q16Pseudo: 239475b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1q32Pseudo: 239575b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1q64Pseudo: 239675b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1q8Pseudo_UPD: 239775b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1q16Pseudo_UPD: 239875b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1q32Pseudo_UPD: 239975b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1q64Pseudo_UPD: 240075b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2d8Pseudo: 240175b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2d16Pseudo: 240275b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2d32Pseudo: 240375b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2q8Pseudo: 240475b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2q16Pseudo: 240575b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2q32Pseudo: 240675b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2d8Pseudo_UPD: 240775b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2d16Pseudo_UPD: 240875b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2d32Pseudo_UPD: 240975b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2q8Pseudo_UPD: 241075b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2q16Pseudo_UPD: 241175b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2q32Pseudo_UPD: 241275b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3d8Pseudo: 241375b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3d16Pseudo: 241475b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3d32Pseudo: 241575b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1d64TPseudo: 241675b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3d8Pseudo_UPD: 241775b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3d16Pseudo_UPD: 241875b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3d32Pseudo_UPD: 241975b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1d64TPseudo_UPD: 242075b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3q8Pseudo_UPD: 242175b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3q16Pseudo_UPD: 242275b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3q32Pseudo_UPD: 242375b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3q8oddPseudo: 242475b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3q16oddPseudo: 242575b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3q32oddPseudo: 242675b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3q8oddPseudo_UPD: 242775b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3q16oddPseudo_UPD: 242875b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3q32oddPseudo_UPD: 242975b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4d8Pseudo: 243075b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4d16Pseudo: 243175b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4d32Pseudo: 243275b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1d64QPseudo: 243375b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4d8Pseudo_UPD: 243475b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4d16Pseudo_UPD: 243575b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4d32Pseudo_UPD: 243675b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1d64QPseudo_UPD: 243775b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4q8Pseudo_UPD: 243875b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4q16Pseudo_UPD: 243975b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4q32Pseudo_UPD: 244075b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4q8oddPseudo: 244175b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4q16oddPseudo: 244275b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4q32oddPseudo: 244375b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4q8oddPseudo_UPD: 244475b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4q16oddPseudo_UPD: 244575b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4q32oddPseudo_UPD: 244675b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1DUPq8Pseudo: 244775b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1DUPq16Pseudo: 244875b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1DUPq32Pseudo: 244975b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1DUPq8Pseudo_UPD: 245075b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1DUPq16Pseudo_UPD: 245175b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1DUPq32Pseudo_UPD: 245275b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2DUPd8Pseudo: 245375b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2DUPd16Pseudo: 245475b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2DUPd32Pseudo: 245575b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2DUPd8Pseudo_UPD: 245675b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2DUPd16Pseudo_UPD: 245775b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2DUPd32Pseudo_UPD: 245875b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4DUPd8Pseudo: 245975b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4DUPd16Pseudo: 246075b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4DUPd32Pseudo: 246175b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4DUPd8Pseudo_UPD: 246275b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4DUPd16Pseudo_UPD: 246375b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4DUPd32Pseudo_UPD: 246475b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1LNq8Pseudo: 246575b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1LNq16Pseudo: 246675b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1LNq32Pseudo: 246775b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1LNq8Pseudo_UPD: 246875b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1LNq16Pseudo_UPD: 246975b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1LNq32Pseudo_UPD: 247075b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2LNd8Pseudo: 247175b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2LNd16Pseudo: 247275b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2LNd32Pseudo: 247375b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2LNq16Pseudo: 247475b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2LNq32Pseudo: 247575b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2LNd8Pseudo_UPD: 247675b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2LNd16Pseudo_UPD: 247775b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2LNd32Pseudo_UPD: 247875b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2LNq16Pseudo_UPD: 247975b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2LNq32Pseudo_UPD: 248075b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4LNd8Pseudo: 248175b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4LNd16Pseudo: 248275b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4LNd32Pseudo: 248375b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4LNq16Pseudo: 248475b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4LNq32Pseudo: 248575b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4LNd8Pseudo_UPD: 248675b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4LNd16Pseudo_UPD: 248775b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4LNd32Pseudo_UPD: 248875b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4LNq16Pseudo_UPD: 248975b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4LNq32Pseudo_UPD: 249075b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng // If the address is not 64-bit aligned, the latencies of these 249175b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng // instructions increases by one. 249275b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng ++Latency; 249375b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng break; 249475b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng } 249575b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng 24967e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng return Latency; 2497a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng} 24982312842de0c641107dd04d7e056d02491cc781caEvan Cheng 24998239daf7c83a65a189c352cce3191cdc3bbfe151Evan Chengint ARMBaseInstrInfo::getInstrLatency(const InstrItineraryData *ItinData, 25008239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng const MachineInstr *MI, 25018239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng unsigned *PredCost) const { 25028239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng if (MI->isCopyLike() || MI->isInsertSubreg() || 25038239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng MI->isRegSequence() || MI->isImplicitDef()) 25048239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng return 1; 25058239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng 25068239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng if (!ItinData || ItinData->isEmpty()) 25078239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng return 1; 25088239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng 2509e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng const MCInstrDesc &MCID = MI->getDesc(); 2510e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng unsigned Class = MCID.getSchedClass(); 25118239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng unsigned UOps = ItinData->Itineraries[Class].NumMicroOps; 2512e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng if (PredCost && MCID.hasImplicitDefOfPhysReg(ARM::CPSR)) 25138239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng // When predicated, CPSR is an additional source operand for CPSR updating 25148239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng // instructions, this apparently increases their latencies. 25158239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng *PredCost = 1; 25168239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng if (UOps) 25178239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng return ItinData->getStageLatency(Class); 25188239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng return getNumMicroOps(ItinData, MI); 25198239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng} 25208239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng 25218239daf7c83a65a189c352cce3191cdc3bbfe151Evan Chengint ARMBaseInstrInfo::getInstrLatency(const InstrItineraryData *ItinData, 25228239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng SDNode *Node) const { 25238239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng if (!Node->isMachineOpcode()) 25248239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng return 1; 25258239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng 25268239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng if (!ItinData || ItinData->isEmpty()) 25278239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng return 1; 25288239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng 25298239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng unsigned Opcode = Node->getMachineOpcode(); 25308239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng switch (Opcode) { 25318239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng default: 25328239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng return ItinData->getStageLatency(get(Opcode).getSchedClass()); 253373fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMQIA: 253473fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMQIA: 25358239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng return 2; 25368b3ca6216d62bf3f729c2e122dcfeb7c4d7500dcEric Christopher } 25378239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng} 25388239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng 25392312842de0c641107dd04d7e056d02491cc781caEvan Chengbool ARMBaseInstrInfo:: 25402312842de0c641107dd04d7e056d02491cc781caEvan ChenghasHighOperandLatency(const InstrItineraryData *ItinData, 25412312842de0c641107dd04d7e056d02491cc781caEvan Cheng const MachineRegisterInfo *MRI, 25422312842de0c641107dd04d7e056d02491cc781caEvan Cheng const MachineInstr *DefMI, unsigned DefIdx, 25432312842de0c641107dd04d7e056d02491cc781caEvan Cheng const MachineInstr *UseMI, unsigned UseIdx) const { 25442312842de0c641107dd04d7e056d02491cc781caEvan Cheng unsigned DDomain = DefMI->getDesc().TSFlags & ARMII::DomainMask; 25452312842de0c641107dd04d7e056d02491cc781caEvan Cheng unsigned UDomain = UseMI->getDesc().TSFlags & ARMII::DomainMask; 25462312842de0c641107dd04d7e056d02491cc781caEvan Cheng if (Subtarget.isCortexA8() && 25472312842de0c641107dd04d7e056d02491cc781caEvan Cheng (DDomain == ARMII::DomainVFP || UDomain == ARMII::DomainVFP)) 25482312842de0c641107dd04d7e056d02491cc781caEvan Cheng // CortexA8 VFP instructions are not pipelined. 25492312842de0c641107dd04d7e056d02491cc781caEvan Cheng return true; 25502312842de0c641107dd04d7e056d02491cc781caEvan Cheng 25512312842de0c641107dd04d7e056d02491cc781caEvan Cheng // Hoist VFP / NEON instructions with 4 or higher latency. 25522312842de0c641107dd04d7e056d02491cc781caEvan Cheng int Latency = getOperandLatency(ItinData, DefMI, DefIdx, UseMI, UseIdx); 25532312842de0c641107dd04d7e056d02491cc781caEvan Cheng if (Latency <= 3) 25542312842de0c641107dd04d7e056d02491cc781caEvan Cheng return false; 25552312842de0c641107dd04d7e056d02491cc781caEvan Cheng return DDomain == ARMII::DomainVFP || DDomain == ARMII::DomainNEON || 25562312842de0c641107dd04d7e056d02491cc781caEvan Cheng UDomain == ARMII::DomainVFP || UDomain == ARMII::DomainNEON; 25572312842de0c641107dd04d7e056d02491cc781caEvan Cheng} 2558c8141dfc7f983cb04e65d8acd6bcbdc8e4b8a0aeEvan Cheng 2559c8141dfc7f983cb04e65d8acd6bcbdc8e4b8a0aeEvan Chengbool ARMBaseInstrInfo:: 2560c8141dfc7f983cb04e65d8acd6bcbdc8e4b8a0aeEvan ChenghasLowDefLatency(const InstrItineraryData *ItinData, 2561c8141dfc7f983cb04e65d8acd6bcbdc8e4b8a0aeEvan Cheng const MachineInstr *DefMI, unsigned DefIdx) const { 2562c8141dfc7f983cb04e65d8acd6bcbdc8e4b8a0aeEvan Cheng if (!ItinData || ItinData->isEmpty()) 2563c8141dfc7f983cb04e65d8acd6bcbdc8e4b8a0aeEvan Cheng return false; 2564c8141dfc7f983cb04e65d8acd6bcbdc8e4b8a0aeEvan Cheng 2565c8141dfc7f983cb04e65d8acd6bcbdc8e4b8a0aeEvan Cheng unsigned DDomain = DefMI->getDesc().TSFlags & ARMII::DomainMask; 2566c8141dfc7f983cb04e65d8acd6bcbdc8e4b8a0aeEvan Cheng if (DDomain == ARMII::DomainGeneral) { 2567c8141dfc7f983cb04e65d8acd6bcbdc8e4b8a0aeEvan Cheng unsigned DefClass = DefMI->getDesc().getSchedClass(); 2568c8141dfc7f983cb04e65d8acd6bcbdc8e4b8a0aeEvan Cheng int DefCycle = ItinData->getOperandCycle(DefClass, DefIdx); 2569c8141dfc7f983cb04e65d8acd6bcbdc8e4b8a0aeEvan Cheng return (DefCycle != -1 && DefCycle <= 2); 2570c8141dfc7f983cb04e65d8acd6bcbdc8e4b8a0aeEvan Cheng } 2571c8141dfc7f983cb04e65d8acd6bcbdc8e4b8a0aeEvan Cheng return false; 2572c8141dfc7f983cb04e65d8acd6bcbdc8e4b8a0aeEvan Cheng} 257348575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng 257448575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Chengbool 257548575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan ChengARMBaseInstrInfo::isFpMLxInstruction(unsigned Opcode, unsigned &MulOpc, 257648575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng unsigned &AddSubOpc, 257748575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng bool &NegAcc, bool &HasLane) const { 257848575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng DenseMap<unsigned, unsigned>::const_iterator I = MLxEntryMap.find(Opcode); 257948575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng if (I == MLxEntryMap.end()) 258048575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng return false; 258148575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng 258248575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng const ARM_MLxEntry &Entry = ARM_MLxTable[I->second]; 258348575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng MulOpc = Entry.MulOpc; 258448575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng AddSubOpc = Entry.AddSubOpc; 258548575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng NegAcc = Entry.NegAcc; 258648575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng HasLane = Entry.HasLane; 258748575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng return true; 258848575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng} 2589