ARMBaseInstrInfo.cpp revision 247c5ab07c1c136f37f5ad8ade9a1ee086ca452e
131d157ae1ac2cd9c787dc3c1d28e64c682803844Jia Liu//===-- ARMBaseInstrInfo.cpp - ARM Instruction Information ----------------===// 2334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// 3334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// The LLVM Compiler Infrastructure 4334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// 5334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// This file is distributed under the University of Illinois Open Source 6334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// License. See LICENSE.TXT for details. 7334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// 8334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin//===----------------------------------------------------------------------===// 9334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// 10334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// This file contains the Base ARM implementation of the TargetInstrInfo class. 11334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// 12334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin//===----------------------------------------------------------------------===// 13334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 14334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "ARMBaseInstrInfo.h" 15334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "ARM.h" 160e5233a9e5ee9385c6a940e3985194d77bee0bbbCraig Topper#include "ARMBaseRegisterInfo.h" 17d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng#include "ARMConstantPoolValue.h" 1848575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng#include "ARMHazardRecognizer.h" 19334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "ARMMachineFunctionInfo.h" 20ee04a6d3a40c3017124e3fd89a0db473a2824498Evan Cheng#include "MCTargetDesc/ARMAddressingModes.h" 21fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng#include "llvm/Constants.h" 22fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng#include "llvm/Function.h" 23fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng#include "llvm/GlobalValue.h" 24334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "llvm/CodeGen/LiveVariables.h" 25d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng#include "llvm/CodeGen/MachineConstantPool.h" 26334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "llvm/CodeGen/MachineFrameInfo.h" 27334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "llvm/CodeGen/MachineInstrBuilder.h" 28334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "llvm/CodeGen/MachineJumpTableInfo.h" 29249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov#include "llvm/CodeGen/MachineMemOperand.h" 302457f2c66184e978d4ed8fa9e2128effff26cb0bEvan Cheng#include "llvm/CodeGen/MachineRegisterInfo.h" 31ee04a6d3a40c3017124e3fd89a0db473a2824498Evan Cheng#include "llvm/CodeGen/SelectionDAGNodes.h" 32af76e592c7f9deff0e55c13dbb4a34f07f1c7f64Chris Lattner#include "llvm/MC/MCAsmInfo.h" 33f81b7f6069b27c0a515070dcb392f6828437412fJakub Staszak#include "llvm/Support/BranchProbability.h" 34334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "llvm/Support/CommandLine.h" 35f95215f551949d5e5adfbf4753aa833b9009b77aAnton Korobeynikov#include "llvm/Support/Debug.h" 36c25e7581b9b8088910da31702d4ca21c4734c6d7Torok Edwin#include "llvm/Support/ErrorHandling.h" 3740a5eb18b031fa1a5e9697e21e251e613d441cc5Bill Wendling#include "llvm/ADT/STLExtras.h" 3822fee2dff4c43b551aefa44a96ca74fcade6bfacEvan Cheng 394db3cffe94a5285239cc0056f939c6b74a5ca0b6Evan Cheng#define GET_INSTRINFO_CTOR 4022fee2dff4c43b551aefa44a96ca74fcade6bfacEvan Cheng#include "ARMGenInstrInfo.inc" 4122fee2dff4c43b551aefa44a96ca74fcade6bfacEvan Cheng 42334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinusing namespace llvm; 43334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 44334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinstatic cl::opt<bool> 45334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinEnableARM3Addr("enable-arm-3-addr-conv", cl::Hidden, 46334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin cl::desc("Enable ARM 2-addr to 3-addr conv")); 47334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 4861545829832ba0375249c42c84843d0b62c8f55fJakob Stoklund Olesenstatic cl::opt<bool> 493805d85e38c29d9106c758b63851eb847201f315Jakob Stoklund OlesenWidenVMOVS("widen-vmovs", cl::Hidden, cl::init(true), 5061545829832ba0375249c42c84843d0b62c8f55fJakob Stoklund Olesen cl::desc("Widen ARM vmovs to vmovd when possible")); 5161545829832ba0375249c42c84843d0b62c8f55fJakob Stoklund Olesen 5248575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng/// ARM_MLxEntry - Record information about MLA / MLS instructions. 5348575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Chengstruct ARM_MLxEntry { 5448575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng unsigned MLxOpc; // MLA / MLS opcode 5548575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng unsigned MulOpc; // Expanded multiplication opcode 5648575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng unsigned AddSubOpc; // Expanded add / sub opcode 5748575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng bool NegAcc; // True if the acc is negated before the add / sub. 5848575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng bool HasLane; // True if instruction has an extra "lane" operand. 5948575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng}; 6048575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng 6148575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Chengstatic const ARM_MLxEntry ARM_MLxTable[] = { 6248575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng // MLxOpc, MulOpc, AddSubOpc, NegAcc, HasLane 6348575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng // fp scalar ops 6448575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng { ARM::VMLAS, ARM::VMULS, ARM::VADDS, false, false }, 6548575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng { ARM::VMLSS, ARM::VMULS, ARM::VSUBS, false, false }, 6648575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng { ARM::VMLAD, ARM::VMULD, ARM::VADDD, false, false }, 6748575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng { ARM::VMLSD, ARM::VMULD, ARM::VSUBD, false, false }, 6848575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng { ARM::VNMLAS, ARM::VNMULS, ARM::VSUBS, true, false }, 6948575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng { ARM::VNMLSS, ARM::VMULS, ARM::VSUBS, true, false }, 7048575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng { ARM::VNMLAD, ARM::VNMULD, ARM::VSUBD, true, false }, 7148575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng { ARM::VNMLSD, ARM::VMULD, ARM::VSUBD, true, false }, 7248575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng 7348575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng // fp SIMD ops 7448575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng { ARM::VMLAfd, ARM::VMULfd, ARM::VADDfd, false, false }, 7548575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng { ARM::VMLSfd, ARM::VMULfd, ARM::VSUBfd, false, false }, 7648575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng { ARM::VMLAfq, ARM::VMULfq, ARM::VADDfq, false, false }, 7748575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng { ARM::VMLSfq, ARM::VMULfq, ARM::VSUBfq, false, false }, 7848575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng { ARM::VMLAslfd, ARM::VMULslfd, ARM::VADDfd, false, true }, 7948575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng { ARM::VMLSslfd, ARM::VMULslfd, ARM::VSUBfd, false, true }, 8048575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng { ARM::VMLAslfq, ARM::VMULslfq, ARM::VADDfq, false, true }, 8148575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng { ARM::VMLSslfq, ARM::VMULslfq, ARM::VSUBfq, false, true }, 8248575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng}; 8348575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng 84f95215f551949d5e5adfbf4753aa833b9009b77aAnton KorobeynikovARMBaseInstrInfo::ARMBaseInstrInfo(const ARMSubtarget& STI) 854db3cffe94a5285239cc0056f939c6b74a5ca0b6Evan Cheng : ARMGenInstrInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP), 86f95215f551949d5e5adfbf4753aa833b9009b77aAnton Korobeynikov Subtarget(STI) { 8748575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng for (unsigned i = 0, e = array_lengthof(ARM_MLxTable); i != e; ++i) { 8848575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng if (!MLxEntryMap.insert(std::make_pair(ARM_MLxTable[i].MLxOpc, i)).second) 8948575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng assert(false && "Duplicated entries?"); 9048575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng MLxHazardOpcodes.insert(ARM_MLxTable[i].AddSubOpc); 9148575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng MLxHazardOpcodes.insert(ARM_MLxTable[i].MulOpc); 9248575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng } 9348575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng} 9448575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng 952da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick// Use a ScoreboardHazardRecognizer for prepass ARM scheduling. TargetInstrImpl 962da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick// currently defaults to no prepass hazard recognizer. 9748575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan ChengScheduleHazardRecognizer *ARMBaseInstrInfo:: 982da8bc8a5f7705ac131184cd247f48500da0d74eAndrew TrickCreateTargetHazardRecognizer(const TargetMachine *TM, 992da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick const ScheduleDAG *DAG) const { 100c8bfd1d78ff9a307d1d4cb57cce4549b538e60f4Andrew Trick if (usePreRAHazardRecognizer()) { 1012da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick const InstrItineraryData *II = TM->getInstrItineraryData(); 1022da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick return new ScoreboardHazardRecognizer(II, DAG, "pre-RA-sched"); 1032da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick } 1042da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick return TargetInstrInfoImpl::CreateTargetHazardRecognizer(TM, DAG); 1052da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick} 1062da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick 1072da8bc8a5f7705ac131184cd247f48500da0d74eAndrew TrickScheduleHazardRecognizer *ARMBaseInstrInfo:: 1082da8bc8a5f7705ac131184cd247f48500da0d74eAndrew TrickCreateTargetPostRAHazardRecognizer(const InstrItineraryData *II, 1092da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick const ScheduleDAG *DAG) const { 11048575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng if (Subtarget.isThumb2() || Subtarget.hasVFP2()) 11148575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng return (ScheduleHazardRecognizer *) 1122da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick new ARMHazardRecognizer(II, *this, getRegisterInfo(), Subtarget, DAG); 1132da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick return TargetInstrInfoImpl::CreateTargetPostRAHazardRecognizer(II, DAG); 114334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 115334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 116334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinMachineInstr * 117334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinARMBaseInstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI, 118334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineBasicBlock::iterator &MBBI, 119334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin LiveVariables *LV) const { 12078703ddafe3d037f75d8ca188e4829d238289ac3Evan Cheng // FIXME: Thumb2 support. 12178703ddafe3d037f75d8ca188e4829d238289ac3Evan Cheng 122334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (!EnableARM3Addr) 123334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return NULL; 124334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 125334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineInstr *MI = MBBI; 126334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineFunction &MF = *MI->getParent()->getParent(); 12799405df044f2c584242e711cc9023ec90356da82Bruno Cardoso Lopes uint64_t TSFlags = MI->getDesc().TSFlags; 128334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool isPre = false; 129334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin switch ((TSFlags & ARMII::IndexModeMask) >> ARMII::IndexModeShift) { 130334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin default: return NULL; 131334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMII::IndexModePre: 132334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin isPre = true; 133334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin break; 134334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMII::IndexModePost: 135334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin break; 136334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 137334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 138334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Try splitting an indexed load/store to an un-indexed one plus an add/sub 139334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // operation. 140334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned MemOpc = getUnindexedOpcode(MI->getOpcode()); 141334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (MemOpc == 0) 142334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return NULL; 143334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 144334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineInstr *UpdateMI = NULL; 145334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineInstr *MemMI = NULL; 146334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned AddrMode = (TSFlags & ARMII::AddrModeMask); 147e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng const MCInstrDesc &MCID = MI->getDesc(); 148e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng unsigned NumOps = MCID.getNumOperands(); 1495a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng bool isLoad = !MI->mayStore(); 150334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const MachineOperand &WB = isLoad ? MI->getOperand(1) : MI->getOperand(0); 151334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const MachineOperand &Base = MI->getOperand(2); 152334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const MachineOperand &Offset = MI->getOperand(NumOps-3); 153334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned WBReg = WB.getReg(); 154334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned BaseReg = Base.getReg(); 155334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned OffReg = Offset.getReg(); 156334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned OffImm = MI->getOperand(NumOps-2).getImm(); 157334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin ARMCC::CondCodes Pred = (ARMCC::CondCodes)MI->getOperand(NumOps-1).getImm(); 158334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin switch (AddrMode) { 159bc2198133a1836598b54b943420748e75d5dea94Craig Topper default: llvm_unreachable("Unknown indexed op!"); 160334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMII::AddrMode2: { 161334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool isSub = ARM_AM::getAM2Op(OffImm) == ARM_AM::sub; 162334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned Amt = ARM_AM::getAM2Offset(OffImm); 163334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (OffReg == 0) { 164e7cbe4118b7ddf05032ff8772a98c51e1637bb5cEvan Cheng if (ARM_AM::getSOImmVal(Amt) == -1) 165334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Can't encode it in a so_imm operand. This transformation will 166334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // add more than 1 instruction. Abandon! 167334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return NULL; 168334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin UpdateMI = BuildMI(MF, MI->getDebugLoc(), 16978703ddafe3d037f75d8ca188e4829d238289ac3Evan Cheng get(isSub ? ARM::SUBri : ARM::ADDri), WBReg) 170e7cbe4118b7ddf05032ff8772a98c51e1637bb5cEvan Cheng .addReg(BaseReg).addImm(Amt) 171334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addImm(Pred).addReg(0).addReg(0); 172334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } else if (Amt != 0) { 173334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin ARM_AM::ShiftOpc ShOpc = ARM_AM::getAM2ShiftOpc(OffImm); 174334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned SOOpc = ARM_AM::getSORegOpc(ShOpc, Amt); 175334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin UpdateMI = BuildMI(MF, MI->getDebugLoc(), 17692a202213bb4c20301abf6ab64e46df3695e60bfOwen Anderson get(isSub ? ARM::SUBrsi : ARM::ADDrsi), WBReg) 177334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(BaseReg).addReg(OffReg).addReg(0).addImm(SOOpc) 178334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addImm(Pred).addReg(0).addReg(0); 179334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } else 180334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin UpdateMI = BuildMI(MF, MI->getDebugLoc(), 18178703ddafe3d037f75d8ca188e4829d238289ac3Evan Cheng get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg) 182334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(BaseReg).addReg(OffReg) 183334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addImm(Pred).addReg(0).addReg(0); 184334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin break; 185334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 186334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMII::AddrMode3 : { 187334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool isSub = ARM_AM::getAM3Op(OffImm) == ARM_AM::sub; 188334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned Amt = ARM_AM::getAM3Offset(OffImm); 189334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (OffReg == 0) 190334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Immediate is 8-bits. It's guaranteed to fit in a so_imm operand. 191334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin UpdateMI = BuildMI(MF, MI->getDebugLoc(), 19278703ddafe3d037f75d8ca188e4829d238289ac3Evan Cheng get(isSub ? ARM::SUBri : ARM::ADDri), WBReg) 193334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(BaseReg).addImm(Amt) 194334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addImm(Pred).addReg(0).addReg(0); 195334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin else 196334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin UpdateMI = BuildMI(MF, MI->getDebugLoc(), 19778703ddafe3d037f75d8ca188e4829d238289ac3Evan Cheng get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg) 198334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(BaseReg).addReg(OffReg) 199334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addImm(Pred).addReg(0).addReg(0); 200334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin break; 201334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 202334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 203334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 204334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin std::vector<MachineInstr*> NewMIs; 205334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (isPre) { 206334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (isLoad) 207334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MemMI = BuildMI(MF, MI->getDebugLoc(), 208334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin get(MemOpc), MI->getOperand(0).getReg()) 2093e5561247202bae994dd259a2d8dc4eff8f799f3Jim Grosbach .addReg(WBReg).addImm(0).addImm(Pred); 210334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin else 211334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MemMI = BuildMI(MF, MI->getDebugLoc(), 212334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin get(MemOpc)).addReg(MI->getOperand(1).getReg()) 213334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(WBReg).addReg(0).addImm(0).addImm(Pred); 214334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin NewMIs.push_back(MemMI); 215334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin NewMIs.push_back(UpdateMI); 216334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } else { 217334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (isLoad) 218334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MemMI = BuildMI(MF, MI->getDebugLoc(), 219334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin get(MemOpc), MI->getOperand(0).getReg()) 2203e5561247202bae994dd259a2d8dc4eff8f799f3Jim Grosbach .addReg(BaseReg).addImm(0).addImm(Pred); 221334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin else 222334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MemMI = BuildMI(MF, MI->getDebugLoc(), 223334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin get(MemOpc)).addReg(MI->getOperand(1).getReg()) 224334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred); 225334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (WB.isDead()) 226334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin UpdateMI->getOperand(0).setIsDead(); 227334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin NewMIs.push_back(UpdateMI); 228334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin NewMIs.push_back(MemMI); 229334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 230334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 231334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Transfer LiveVariables states, kill / dead info. 232334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (LV) { 233334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 234334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineOperand &MO = MI->getOperand(i); 235c9df025e33ac435adb3b3318d237c36ca7cec659Jakob Stoklund Olesen if (MO.isReg() && TargetRegisterInfo::isVirtualRegister(MO.getReg())) { 236334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned Reg = MO.getReg(); 237334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 238334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin LiveVariables::VarInfo &VI = LV->getVarInfo(Reg); 239334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (MO.isDef()) { 240334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineInstr *NewMI = (Reg == WBReg) ? UpdateMI : MemMI; 241334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (MO.isDead()) 242334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin LV->addVirtualRegisterDead(Reg, NewMI); 243334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 244334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (MO.isUse() && MO.isKill()) { 245334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin for (unsigned j = 0; j < 2; ++j) { 246334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Look at the two new MI's in reverse order. 247334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineInstr *NewMI = NewMIs[j]; 248334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (!NewMI->readsRegister(Reg)) 249334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin continue; 250334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin LV->addVirtualRegisterKilled(Reg, NewMI); 251334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (VI.removeKill(MI)) 252334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin VI.Kills.push_back(NewMI); 253334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin break; 254334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 255334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 256334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 257334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 258334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 259334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 260334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MFI->insert(MBBI, NewMIs[1]); 261334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MFI->insert(MBBI, NewMIs[0]); 262334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return NewMIs[0]; 263334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 264334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 265334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// Branch analysis. 266334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinbool 267334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinARMBaseInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB, 268334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineBasicBlock *&FBB, 269334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin SmallVectorImpl<MachineOperand> &Cond, 270334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool AllowModify) const { 271334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // If the block has no terminators, it just falls into the block after it. 272334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineBasicBlock::iterator I = MBB.end(); 27393d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen if (I == MBB.begin()) 27493d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen return false; 27593d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen --I; 27693d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen while (I->isDebugValue()) { 27793d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen if (I == MBB.begin()) 27893d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen return false; 27993d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen --I; 28093d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen } 28193d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen if (!isUnpredicatedTerminator(I)) 282334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 283334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 284334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Get the last instruction in the block. 285334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineInstr *LastInst = I; 286334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 287334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // If there is only one terminator instruction, process it. 288334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned LastOpc = LastInst->getOpcode(); 289334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) { 2905ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng if (isUncondBranchOpcode(LastOpc)) { 291334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin TBB = LastInst->getOperand(0).getMBB(); 292334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 293334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 2945ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng if (isCondBranchOpcode(LastOpc)) { 295334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Block ends with fall-through condbranch. 296334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin TBB = LastInst->getOperand(0).getMBB(); 297334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin Cond.push_back(LastInst->getOperand(1)); 298334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin Cond.push_back(LastInst->getOperand(2)); 299334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 300334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 301334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; // Can't handle indirect branch. 302334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 303334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 304334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Get the instruction before it if it is a terminator. 305334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineInstr *SecondLastInst = I; 306108c8724663354050dc09bb1262c3e4511adf82fEvan Cheng unsigned SecondLastOpc = SecondLastInst->getOpcode(); 307108c8724663354050dc09bb1262c3e4511adf82fEvan Cheng 308108c8724663354050dc09bb1262c3e4511adf82fEvan Cheng // If AllowModify is true and the block ends with two or more unconditional 309108c8724663354050dc09bb1262c3e4511adf82fEvan Cheng // branches, delete all but the first unconditional branch. 310108c8724663354050dc09bb1262c3e4511adf82fEvan Cheng if (AllowModify && isUncondBranchOpcode(LastOpc)) { 311108c8724663354050dc09bb1262c3e4511adf82fEvan Cheng while (isUncondBranchOpcode(SecondLastOpc)) { 312108c8724663354050dc09bb1262c3e4511adf82fEvan Cheng LastInst->eraseFromParent(); 313108c8724663354050dc09bb1262c3e4511adf82fEvan Cheng LastInst = SecondLastInst; 314108c8724663354050dc09bb1262c3e4511adf82fEvan Cheng LastOpc = LastInst->getOpcode(); 315676e258366dd17a0b4ee6ac66914237ce181202eEvan Cheng if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) { 316676e258366dd17a0b4ee6ac66914237ce181202eEvan Cheng // Return now the only terminator is an unconditional branch. 317676e258366dd17a0b4ee6ac66914237ce181202eEvan Cheng TBB = LastInst->getOperand(0).getMBB(); 318676e258366dd17a0b4ee6ac66914237ce181202eEvan Cheng return false; 319676e258366dd17a0b4ee6ac66914237ce181202eEvan Cheng } else { 320108c8724663354050dc09bb1262c3e4511adf82fEvan Cheng SecondLastInst = I; 321108c8724663354050dc09bb1262c3e4511adf82fEvan Cheng SecondLastOpc = SecondLastInst->getOpcode(); 322108c8724663354050dc09bb1262c3e4511adf82fEvan Cheng } 323108c8724663354050dc09bb1262c3e4511adf82fEvan Cheng } 324108c8724663354050dc09bb1262c3e4511adf82fEvan Cheng } 325334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 326334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // If there are three terminators, we don't know what sort of block this is. 327334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(--I)) 328334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; 329334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 3305ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng // If the block ends with a B and a Bcc, handle it. 3315ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng if (isCondBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) { 332334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin TBB = SecondLastInst->getOperand(0).getMBB(); 333334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin Cond.push_back(SecondLastInst->getOperand(1)); 334334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin Cond.push_back(SecondLastInst->getOperand(2)); 335334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin FBB = LastInst->getOperand(0).getMBB(); 336334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 337334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 338334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 339334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // If the block ends with two unconditional branches, handle it. The second 340334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // one is not executed, so remove it. 3415ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng if (isUncondBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) { 342334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin TBB = SecondLastInst->getOperand(0).getMBB(); 343334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin I = LastInst; 344334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (AllowModify) 345334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin I->eraseFromParent(); 346334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 347334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 348334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 349334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // ...likewise if it ends with a branch table followed by an unconditional 350334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // branch. The branch folder can create these, and we must get rid of them for 351334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // correctness of Thumb constant islands. 3528d4de5abfa1bcd974554ea14904ebf7af289e84dBob Wilson if ((isJumpTableBranchOpcode(SecondLastOpc) || 3538d4de5abfa1bcd974554ea14904ebf7af289e84dBob Wilson isIndirectBranchOpcode(SecondLastOpc)) && 3545ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng isUncondBranchOpcode(LastOpc)) { 355334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin I = LastInst; 356334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (AllowModify) 357334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin I->eraseFromParent(); 358334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; 359334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 360334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 361334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Otherwise, can't handle this. 362334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; 363334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 364334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 365334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 366334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinunsigned ARMBaseInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const { 367334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineBasicBlock::iterator I = MBB.end(); 368334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (I == MBB.begin()) return 0; 369334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin --I; 37093d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen while (I->isDebugValue()) { 37193d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen if (I == MBB.begin()) 37293d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen return 0; 37393d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen --I; 37493d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen } 3755ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng if (!isUncondBranchOpcode(I->getOpcode()) && 3765ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng !isCondBranchOpcode(I->getOpcode())) 377334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 0; 378334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 379334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Remove the branch. 380334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin I->eraseFromParent(); 381334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 382334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin I = MBB.end(); 383334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 384334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (I == MBB.begin()) return 1; 385334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin --I; 3865ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng if (!isCondBranchOpcode(I->getOpcode())) 387334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 1; 388334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 389334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Remove the branch. 390334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin I->eraseFromParent(); 391334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 2; 392334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 393334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 394334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinunsigned 395334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinARMBaseInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 3963bf912593301152b65accb9d9c37a95172f1df5aStuart Hastings MachineBasicBlock *FBB, 3973bf912593301152b65accb9d9c37a95172f1df5aStuart Hastings const SmallVectorImpl<MachineOperand> &Cond, 3983bf912593301152b65accb9d9c37a95172f1df5aStuart Hastings DebugLoc DL) const { 3996495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ARMFunctionInfo *AFI = MBB.getParent()->getInfo<ARMFunctionInfo>(); 4006495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng int BOpc = !AFI->isThumbFunction() 4016495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ? ARM::B : (AFI->isThumb2Function() ? ARM::t2B : ARM::tB); 4026495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng int BccOpc = !AFI->isThumbFunction() 4036495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ? ARM::Bcc : (AFI->isThumb2Function() ? ARM::t2Bcc : ARM::tBcc); 40451f6a7abf27fc92c3d8904c2334feab8b498e8e9Owen Anderson bool isThumb = AFI->isThumbFunction() || AFI->isThumb2Function(); 405e23dc9c0ef50b0a1934c04c1786f3a0478d62f41Andrew Trick 406334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Shouldn't be a fall through. 407334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin assert(TBB && "InsertBranch must not be told to insert a fallthrough"); 408334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin assert((Cond.size() == 2 || Cond.size() == 0) && 409334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin "ARM branch conditions have two components!"); 410334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 411334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (FBB == 0) { 412112fb73502d54dd7dd61ae2de24c92d4df181294Owen Anderson if (Cond.empty()) { // Unconditional branch? 41351f6a7abf27fc92c3d8904c2334feab8b498e8e9Owen Anderson if (isThumb) 41451f6a7abf27fc92c3d8904c2334feab8b498e8e9Owen Anderson BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB).addImm(ARMCC::AL).addReg(0); 41551f6a7abf27fc92c3d8904c2334feab8b498e8e9Owen Anderson else 41651f6a7abf27fc92c3d8904c2334feab8b498e8e9Owen Anderson BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB); 417112fb73502d54dd7dd61ae2de24c92d4df181294Owen Anderson } else 4183bf912593301152b65accb9d9c37a95172f1df5aStuart Hastings BuildMI(&MBB, DL, get(BccOpc)).addMBB(TBB) 419334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()); 420334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 1; 421334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 422334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 423334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Two-way conditional branch. 4243bf912593301152b65accb9d9c37a95172f1df5aStuart Hastings BuildMI(&MBB, DL, get(BccOpc)).addMBB(TBB) 425334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()); 42651f6a7abf27fc92c3d8904c2334feab8b498e8e9Owen Anderson if (isThumb) 42751f6a7abf27fc92c3d8904c2334feab8b498e8e9Owen Anderson BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB).addImm(ARMCC::AL).addReg(0); 42851f6a7abf27fc92c3d8904c2334feab8b498e8e9Owen Anderson else 42951f6a7abf27fc92c3d8904c2334feab8b498e8e9Owen Anderson BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB); 430334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 2; 431334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 432334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 433334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinbool ARMBaseInstrInfo:: 434334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const { 435334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin ARMCC::CondCodes CC = (ARMCC::CondCodes)(int)Cond[0].getImm(); 436334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin Cond[0].setImm(ARMCC::getOppositeCondition(CC)); 437334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 438334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 439334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 440ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Chengbool ARMBaseInstrInfo::isPredicated(const MachineInstr *MI) const { 441ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng if (MI->isBundle()) { 442ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng MachineBasicBlock::const_instr_iterator I = MI; 443ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end(); 444ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng while (++I != E && I->isInsideBundle()) { 445ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng int PIdx = I->findFirstPredOperandIdx(); 446ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng if (PIdx != -1 && I->getOperand(PIdx).getImm() != ARMCC::AL) 447ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng return true; 448ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng } 449ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng return false; 450ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng } 451ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng 452ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng int PIdx = MI->findFirstPredOperandIdx(); 453ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng return PIdx != -1 && MI->getOperand(PIdx).getImm() != ARMCC::AL; 454ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng} 455ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng 456334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinbool ARMBaseInstrInfo:: 457334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinPredicateInstruction(MachineInstr *MI, 458334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const SmallVectorImpl<MachineOperand> &Pred) const { 459334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned Opc = MI->getOpcode(); 4605ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng if (isUncondBranchOpcode(Opc)) { 4615ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng MI->setDesc(get(getMatchingCondBranchOpcode(Opc))); 462334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI->addOperand(MachineOperand::CreateImm(Pred[0].getImm())); 463334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI->addOperand(MachineOperand::CreateReg(Pred[1].getReg(), false)); 464334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; 465334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 466334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 467334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin int PIdx = MI->findFirstPredOperandIdx(); 468334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (PIdx != -1) { 469334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineOperand &PMO = MI->getOperand(PIdx); 470334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin PMO.setImm(Pred[0].getImm()); 471334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI->getOperand(PIdx+1).setReg(Pred[1].getReg()); 472334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; 473334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 474334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 475334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 476334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 477334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinbool ARMBaseInstrInfo:: 478334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinSubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1, 479334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const SmallVectorImpl<MachineOperand> &Pred2) const { 480334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (Pred1.size() > 2 || Pred2.size() > 2) 481334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 482334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 483334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin ARMCC::CondCodes CC1 = (ARMCC::CondCodes)Pred1[0].getImm(); 484334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin ARMCC::CondCodes CC2 = (ARMCC::CondCodes)Pred2[0].getImm(); 485334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (CC1 == CC2) 486334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; 487334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 488334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin switch (CC1) { 489334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin default: 490334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 491334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMCC::AL: 492334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; 493334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMCC::HS: 494334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return CC2 == ARMCC::HI; 495334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMCC::LS: 496334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return CC2 == ARMCC::LO || CC2 == ARMCC::EQ; 497334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMCC::GE: 498334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return CC2 == ARMCC::GT; 499334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMCC::LE: 500334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return CC2 == ARMCC::LT; 501334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 502334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 503334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 504334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinbool ARMBaseInstrInfo::DefinesPredicate(MachineInstr *MI, 505334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin std::vector<MachineOperand> &Pred) const { 506334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool Found = false; 507334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 508334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const MachineOperand &MO = MI->getOperand(i); 5092420b558de5d291d8503c1339004e5b5bf99a48aJakob Stoklund Olesen if ((MO.isRegMask() && MO.clobbersPhysReg(ARM::CPSR)) || 5102420b558de5d291d8503c1339004e5b5bf99a48aJakob Stoklund Olesen (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR)) { 511334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin Pred.push_back(MO); 512334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin Found = true; 513334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 514334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 515334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 516334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return Found; 517334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 518334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 519ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng/// isPredicable - Return true if the specified instruction can be predicated. 520ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng/// By default, this returns true for every instruction with a 521ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng/// PredicateOperand. 522ac0869dc8a7986855c5557cc67d4709600158ef5Evan Chengbool ARMBaseInstrInfo::isPredicable(MachineInstr *MI) const { 5235a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng if (!MI->isPredicable()) 524ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng return false; 525ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng 5265a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng if ((MI->getDesc().TSFlags & ARMII::DomainMask) == ARMII::DomainNEON) { 527ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng ARMFunctionInfo *AFI = 528ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng MI->getParent()->getParent()->getInfo<ARMFunctionInfo>(); 529d7f0810c934a7d13acb28c42d737ce58ec990ea8Evan Cheng return AFI->isThumb2Function(); 530ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng } 531ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng return true; 532ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng} 533334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 53456856b1f46ec1f073ceef4e826c544b8b1691608Chris Lattner/// FIXME: Works around a gcc miscompilation with -fstrict-aliasing. 53519e57025d458d3cb50804fd821fd89b868a819bdChandler CarruthLLVM_ATTRIBUTE_NOINLINE 536334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinstatic unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT, 53756856b1f46ec1f073ceef4e826c544b8b1691608Chris Lattner unsigned JTI); 538334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinstatic unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT, 539334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned JTI) { 54056856b1f46ec1f073ceef4e826c544b8b1691608Chris Lattner assert(JTI < JT.size()); 541334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return JT[JTI].MBBs.size(); 542334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 543334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 544334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin/// GetInstSize - Return the size of the specified MachineInstr. 545334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin/// 546334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinunsigned ARMBaseInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const { 547334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const MachineBasicBlock &MBB = *MI->getParent(); 548334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const MachineFunction *MF = MBB.getParent(); 54933adcfb4d217f5f23d9bde8ba02b8e48f9605fc5Chris Lattner const MCAsmInfo *MAI = MF->getTarget().getMCAsmInfo(); 550334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 551e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng const MCInstrDesc &MCID = MI->getDesc(); 55216884415db751c75f2133bd04921393c792b1158Owen Anderson if (MCID.getSize()) 55316884415db751c75f2133bd04921393c792b1158Owen Anderson return MCID.getSize(); 554334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 5554d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie // If this machine instr is an inline asm, measure it. 5564d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie if (MI->getOpcode() == ARM::INLINEASM) 5574d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie return getInlineAsmLength(MI->getOperand(0).getSymbolName(), *MAI); 5584d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie if (MI->isLabel()) 5594d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie return 0; 5604d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie unsigned Opc = MI->getOpcode(); 5614d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie switch (Opc) { 5624d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie case TargetOpcode::IMPLICIT_DEF: 5634d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie case TargetOpcode::KILL: 5644d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie case TargetOpcode::PROLOG_LABEL: 5654d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie case TargetOpcode::EH_LABEL: 5664d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie case TargetOpcode::DBG_VALUE: 5674d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie return 0; 5684d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie case TargetOpcode::BUNDLE: 5694d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie return getInstBundleLength(MI); 5704d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie case ARM::MOVi16_ga_pcrel: 5714d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie case ARM::MOVTi16_ga_pcrel: 5724d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie case ARM::t2MOVi16_ga_pcrel: 5734d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie case ARM::t2MOVTi16_ga_pcrel: 5744d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie return 4; 5754d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie case ARM::MOVi32imm: 5764d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie case ARM::t2MOVi32imm: 5774d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie return 8; 5784d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie case ARM::CONSTPOOL_ENTRY: 5794d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie // If this machine instr is a constant pool entry, its size is recorded as 5804d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie // operand #2. 5814d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie return MI->getOperand(2).getImm(); 5824d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie case ARM::Int_eh_sjlj_longjmp: 5834d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie return 16; 5844d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie case ARM::tInt_eh_sjlj_longjmp: 5854d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie return 10; 5864d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie case ARM::Int_eh_sjlj_setjmp: 5874d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie case ARM::Int_eh_sjlj_setjmp_nofp: 5884d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie return 20; 5894d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie case ARM::tInt_eh_sjlj_setjmp: 5904d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie case ARM::t2Int_eh_sjlj_setjmp: 5914d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie case ARM::t2Int_eh_sjlj_setjmp_nofp: 5924d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie return 12; 5934d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie case ARM::BR_JTr: 5944d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie case ARM::BR_JTm: 5954d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie case ARM::BR_JTadd: 5964d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie case ARM::tBR_JTr: 5974d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie case ARM::t2BR_JT: 5984d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie case ARM::t2TBB_JT: 5994d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie case ARM::t2TBH_JT: { 6004d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie // These are jumptable branches, i.e. a branch followed by an inlined 6014d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie // jumptable. The size is 4 + 4 * number of entries. For TBB, each 6024d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie // entry is one byte; TBH two byte each. 6034d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie unsigned EntrySize = (Opc == ARM::t2TBB_JT) 6044d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie ? 1 : ((Opc == ARM::t2TBH_JT) ? 2 : 4); 6054d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie unsigned NumOps = MCID.getNumOperands(); 6064d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie MachineOperand JTOP = 6074d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie MI->getOperand(NumOps - (MI->isPredicable() ? 3 : 2)); 6084d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie unsigned JTI = JTOP.getIndex(); 6094d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo(); 6104d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie assert(MJTI != 0); 6114d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables(); 6124d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie assert(JTI < JT.size()); 6134d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie // Thumb instructions are 2 byte aligned, but JT entries are 4 byte 6144d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie // 4 aligned. The assembler / linker may add 2 byte padding just before 6154d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie // the JT entries. The size does not include this padding; the 6164d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie // constant islands pass does separate bookkeeping for it. 6174d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie // FIXME: If we know the size of the function is less than (1 << 16) *2 6184d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie // bytes, we can use 16-bit entries instead. Then there won't be an 6194d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie // alignment issue. 6204d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie unsigned InstSize = (Opc == ARM::tBR_JTr || Opc == ARM::t2BR_JT) ? 2 : 4; 6214d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie unsigned NumEntries = getNumJTEntries(JT, JTI); 6224d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie if (Opc == ARM::t2TBB_JT && (NumEntries & 1)) 6234d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie // Make sure the instruction that follows TBB is 2-byte aligned. 6244d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie // FIXME: Constant island pass should insert an "ALIGN" instruction 6254d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie // instead. 6264d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie ++NumEntries; 6274d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie return NumEntries * EntrySize + InstSize; 6284d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie } 6294d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie default: 6304d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie // Otherwise, pseudo-instruction sizes are zero. 6314d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie return 0; 6324d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie } 633334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 634334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 635ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Chengunsigned ARMBaseInstrInfo::getInstBundleLength(const MachineInstr *MI) const { 636ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng unsigned Size = 0; 637ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng MachineBasicBlock::const_instr_iterator I = MI; 638ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end(); 639ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng while (++I != E && I->isInsideBundle()) { 640ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng assert(!I->isBundle() && "No nested bundle!"); 641ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng Size += GetInstSizeInBytes(&*I); 642ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng } 643ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng return Size; 644ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng} 645ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng 646ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesenvoid ARMBaseInstrInfo::copyPhysReg(MachineBasicBlock &MBB, 647ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen MachineBasicBlock::iterator I, DebugLoc DL, 648ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen unsigned DestReg, unsigned SrcReg, 649ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen bool KillSrc) const { 650ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen bool GPRDest = ARM::GPRRegClass.contains(DestReg); 651ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen bool GPRSrc = ARM::GPRRegClass.contains(SrcReg); 652ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen 653ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen if (GPRDest && GPRSrc) { 654ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen AddDefaultCC(AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::MOVr), DestReg) 655ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen .addReg(SrcReg, getKillRegState(KillSrc)))); 656ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen return; 6577bfdca0206f51132b26094c6f83a5ac97ee0f943David Goodwin } 658334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 659ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen bool SPRDest = ARM::SPRRegClass.contains(DestReg); 660ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen bool SPRSrc = ARM::SPRRegClass.contains(SrcReg); 661ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen 662e5038e191db82d4d92fdeec1b5bce5cae21f6d8fChad Rosier unsigned Opc = 0; 663142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen if (SPRDest && SPRSrc) 664ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen Opc = ARM::VMOVS; 665142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen else if (GPRDest && SPRSrc) 666ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen Opc = ARM::VMOVRS; 667ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen else if (SPRDest && GPRSrc) 668ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen Opc = ARM::VMOVSR; 669ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen else if (ARM::DPRRegClass.contains(DestReg, SrcReg)) 670ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen Opc = ARM::VMOVD; 671ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen else if (ARM::QPRRegClass.contains(DestReg, SrcReg)) 67243967a97cf9a296623e1cf5ed643e2f40b7e5766Owen Anderson Opc = ARM::VORRq; 673e5038e191db82d4d92fdeec1b5bce5cae21f6d8fChad Rosier 674e5038e191db82d4d92fdeec1b5bce5cae21f6d8fChad Rosier if (Opc) { 675e5038e191db82d4d92fdeec1b5bce5cae21f6d8fChad Rosier MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc), DestReg); 67643967a97cf9a296623e1cf5ed643e2f40b7e5766Owen Anderson MIB.addReg(SrcReg, getKillRegState(KillSrc)); 677e5038e191db82d4d92fdeec1b5bce5cae21f6d8fChad Rosier if (Opc == ARM::VORRq) 678e5038e191db82d4d92fdeec1b5bce5cae21f6d8fChad Rosier MIB.addReg(SrcReg, getKillRegState(KillSrc)); 679fea95c6bade86fcfa5bd07efdda9bd902f53be8cChad Rosier AddDefaultPred(MIB); 680e5038e191db82d4d92fdeec1b5bce5cae21f6d8fChad Rosier return; 681e5038e191db82d4d92fdeec1b5bce5cae21f6d8fChad Rosier } 682e5038e191db82d4d92fdeec1b5bce5cae21f6d8fChad Rosier 68385bdf2e76a0351468f231f48069c64bc6938f140Jakob Stoklund Olesen // Handle register classes that require multiple instructions. 68485bdf2e76a0351468f231f48069c64bc6938f140Jakob Stoklund Olesen unsigned BeginIdx = 0; 68585bdf2e76a0351468f231f48069c64bc6938f140Jakob Stoklund Olesen unsigned SubRegs = 0; 68685bdf2e76a0351468f231f48069c64bc6938f140Jakob Stoklund Olesen unsigned Spacing = 1; 68785bdf2e76a0351468f231f48069c64bc6938f140Jakob Stoklund Olesen 68885bdf2e76a0351468f231f48069c64bc6938f140Jakob Stoklund Olesen // Use VORRq when possible. 68985bdf2e76a0351468f231f48069c64bc6938f140Jakob Stoklund Olesen if (ARM::QQPRRegClass.contains(DestReg, SrcReg)) 69085bdf2e76a0351468f231f48069c64bc6938f140Jakob Stoklund Olesen Opc = ARM::VORRq, BeginIdx = ARM::qsub_0, SubRegs = 2; 69185bdf2e76a0351468f231f48069c64bc6938f140Jakob Stoklund Olesen else if (ARM::QQQQPRRegClass.contains(DestReg, SrcReg)) 69285bdf2e76a0351468f231f48069c64bc6938f140Jakob Stoklund Olesen Opc = ARM::VORRq, BeginIdx = ARM::qsub_0, SubRegs = 4; 69385bdf2e76a0351468f231f48069c64bc6938f140Jakob Stoklund Olesen // Fall back to VMOVD. 69485bdf2e76a0351468f231f48069c64bc6938f140Jakob Stoklund Olesen else if (ARM::DPairRegClass.contains(DestReg, SrcReg)) 69585bdf2e76a0351468f231f48069c64bc6938f140Jakob Stoklund Olesen Opc = ARM::VMOVD, BeginIdx = ARM::dsub_0, SubRegs = 2; 69685bdf2e76a0351468f231f48069c64bc6938f140Jakob Stoklund Olesen else if (ARM::DTripleRegClass.contains(DestReg, SrcReg)) 69785bdf2e76a0351468f231f48069c64bc6938f140Jakob Stoklund Olesen Opc = ARM::VMOVD, BeginIdx = ARM::dsub_0, SubRegs = 3; 69885bdf2e76a0351468f231f48069c64bc6938f140Jakob Stoklund Olesen else if (ARM::DQuadRegClass.contains(DestReg, SrcReg)) 69985bdf2e76a0351468f231f48069c64bc6938f140Jakob Stoklund Olesen Opc = ARM::VMOVD, BeginIdx = ARM::dsub_0, SubRegs = 4; 70085bdf2e76a0351468f231f48069c64bc6938f140Jakob Stoklund Olesen 70185bdf2e76a0351468f231f48069c64bc6938f140Jakob Stoklund Olesen else if (ARM::DPairSpcRegClass.contains(DestReg, SrcReg)) 70285bdf2e76a0351468f231f48069c64bc6938f140Jakob Stoklund Olesen Opc = ARM::VMOVD, BeginIdx = ARM::dsub_0, SubRegs = 2, Spacing = 2; 70385bdf2e76a0351468f231f48069c64bc6938f140Jakob Stoklund Olesen else if (ARM::DTripleSpcRegClass.contains(DestReg, SrcReg)) 70485bdf2e76a0351468f231f48069c64bc6938f140Jakob Stoklund Olesen Opc = ARM::VMOVD, BeginIdx = ARM::dsub_0, SubRegs = 3, Spacing = 2; 70585bdf2e76a0351468f231f48069c64bc6938f140Jakob Stoklund Olesen else if (ARM::DQuadSpcRegClass.contains(DestReg, SrcReg)) 70685bdf2e76a0351468f231f48069c64bc6938f140Jakob Stoklund Olesen Opc = ARM::VMOVD, BeginIdx = ARM::dsub_0, SubRegs = 4, Spacing = 2; 70785bdf2e76a0351468f231f48069c64bc6938f140Jakob Stoklund Olesen 70885bdf2e76a0351468f231f48069c64bc6938f140Jakob Stoklund Olesen if (Opc) { 709e5038e191db82d4d92fdeec1b5bce5cae21f6d8fChad Rosier const TargetRegisterInfo *TRI = &getRegisterInfo(); 71085bdf2e76a0351468f231f48069c64bc6938f140Jakob Stoklund Olesen MachineInstrBuilder Mov; 71185bdf2e76a0351468f231f48069c64bc6938f140Jakob Stoklund Olesen for (unsigned i = 0; i != SubRegs; ++i) { 71285bdf2e76a0351468f231f48069c64bc6938f140Jakob Stoklund Olesen unsigned Dst = TRI->getSubReg(DestReg, BeginIdx + i*Spacing); 71385bdf2e76a0351468f231f48069c64bc6938f140Jakob Stoklund Olesen unsigned Src = TRI->getSubReg(SrcReg, BeginIdx + i*Spacing); 71485bdf2e76a0351468f231f48069c64bc6938f140Jakob Stoklund Olesen assert(Dst && Src && "Bad sub-register"); 71585bdf2e76a0351468f231f48069c64bc6938f140Jakob Stoklund Olesen Mov = AddDefaultPred(BuildMI(MBB, I, I->getDebugLoc(), get(Opc), Dst) 71685bdf2e76a0351468f231f48069c64bc6938f140Jakob Stoklund Olesen .addReg(Src)); 71785bdf2e76a0351468f231f48069c64bc6938f140Jakob Stoklund Olesen // VORR takes two source operands. 71885bdf2e76a0351468f231f48069c64bc6938f140Jakob Stoklund Olesen if (Opc == ARM::VORRq) 71985bdf2e76a0351468f231f48069c64bc6938f140Jakob Stoklund Olesen Mov.addReg(Src); 720e5038e191db82d4d92fdeec1b5bce5cae21f6d8fChad Rosier } 72185bdf2e76a0351468f231f48069c64bc6938f140Jakob Stoklund Olesen // Add implicit super-register defs and kills to the last instruction. 72285bdf2e76a0351468f231f48069c64bc6938f140Jakob Stoklund Olesen Mov->addRegisterDefined(DestReg, TRI); 72385bdf2e76a0351468f231f48069c64bc6938f140Jakob Stoklund Olesen if (KillSrc) 72485bdf2e76a0351468f231f48069c64bc6938f140Jakob Stoklund Olesen Mov->addRegisterKilled(SrcReg, TRI); 725e5038e191db82d4d92fdeec1b5bce5cae21f6d8fChad Rosier return; 726e5038e191db82d4d92fdeec1b5bce5cae21f6d8fChad Rosier } 72785bdf2e76a0351468f231f48069c64bc6938f140Jakob Stoklund Olesen 728e5038e191db82d4d92fdeec1b5bce5cae21f6d8fChad Rosier llvm_unreachable("Impossible reg-to-reg copy"); 729334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 730334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 731c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Chengstatic const 732c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan ChengMachineInstrBuilder &AddDReg(MachineInstrBuilder &MIB, 733c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Cheng unsigned Reg, unsigned SubIdx, unsigned State, 734c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Cheng const TargetRegisterInfo *TRI) { 735c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Cheng if (!SubIdx) 736c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Cheng return MIB.addReg(Reg, State); 737c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Cheng 738c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Cheng if (TargetRegisterInfo::isPhysicalRegister(Reg)) 739c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Cheng return MIB.addReg(TRI->getSubReg(Reg, SubIdx), State); 740c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Cheng return MIB.addReg(Reg, State, SubIdx); 741c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Cheng} 742c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Cheng 743334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinvoid ARMBaseInstrInfo:: 744334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinstoreRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 745334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned SrcReg, bool isKill, int FI, 746746ad69e088176819981b4b2c5ac8dcd49f5e60eEvan Cheng const TargetRegisterClass *RC, 747746ad69e088176819981b4b2c5ac8dcd49f5e60eEvan Cheng const TargetRegisterInfo *TRI) const { 748c7f3ace20c325521c68335a1689645b43b06ddf0Chris Lattner DebugLoc DL; 749334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (I != MBB.end()) DL = I->getDebugLoc(); 750249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MachineFunction &MF = *MBB.getParent(); 751249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MachineFrameInfo &MFI = *MF.getFrameInfo(); 75231bc849123011b8eae6bb3c79876d9a3c26a6a1dJim Grosbach unsigned Align = MFI.getObjectAlignment(FI); 753249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov 754249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MachineMemOperand *MMO = 755978e0dfe46e481bfb1281e683aa308329e879e95Jay Foad MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FI), 75659db5496f4fc2ef6111569e542f8b65480ef14c1Chris Lattner MachineMemOperand::MOStore, 757249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MFI.getObjectSize(FI), 75831bc849123011b8eae6bb3c79876d9a3c26a6a1dJim Grosbach Align); 759334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 760e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson switch (RC->getSize()) { 761e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson case 4: 762e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson if (ARM::GPRRegClass.hasSubClassEq(RC)) { 763e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::STRi12)) 764334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(SrcReg, getKillRegState(isKill)) 7657e3383c007f53b3a00675af225e428cb66ddf404Jim Grosbach .addFrameIndex(FI).addImm(0).addMemOperand(MMO)); 766e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson } else if (ARM::SPRRegClass.hasSubClassEq(RC)) { 767e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTRS)) 768d31c5496d7e1580058b5c6fbc8fd537a641ea590Evan Cheng .addReg(SrcReg, getKillRegState(isKill)) 769d31c5496d7e1580058b5c6fbc8fd537a641ea590Evan Cheng .addFrameIndex(FI).addImm(0).addMemOperand(MMO)); 770e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson } else 771e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson llvm_unreachable("Unknown reg class!"); 772e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson break; 773e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson case 8: 774e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson if (ARM::DPRRegClass.hasSubClassEq(RC)) { 775e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTRD)) 776334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(SrcReg, getKillRegState(isKill)) 777249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov .addFrameIndex(FI).addImm(0).addMemOperand(MMO)); 778e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson } else 779e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson llvm_unreachable("Unknown reg class!"); 780e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson break; 781e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson case 16: 7825b2f9136644c58ae32e00d8317540692a697d1c9Jakob Stoklund Olesen if (ARM::DPairRegClass.hasSubClassEq(RC)) { 7837255a4e1332ccb69918ebe041dff05f9e4e5815dJakob Stoklund Olesen // Use aligned spills if the stack can be realigned. 7847255a4e1332ccb69918ebe041dff05f9e4e5815dJakob Stoklund Olesen if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) { 78528f08c93e75d291695ea89b9004145103292e85bJim Grosbach AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1q64)) 786f967ca0eaf30325cabe3c1971bf0dba16cf1b027Bob Wilson .addFrameIndex(FI).addImm(16) 78769b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng .addReg(SrcReg, getKillRegState(isKill)) 78869b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng .addMemOperand(MMO)); 789e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson } else { 790e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMQIA)) 79169b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng .addReg(SrcReg, getKillRegState(isKill)) 79269b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng .addFrameIndex(FI) 79369b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng .addMemOperand(MMO)); 794e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson } 795e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson } else 796e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson llvm_unreachable("Unknown reg class!"); 797e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson break; 798e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson case 32: 799e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson if (ARM::QQPRRegClass.hasSubClassEq(RC)) { 800e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) { 801e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson // FIXME: It's possible to only store part of the QQ register if the 802e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson // spilled def has a sub-register index. 803e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1d64QPseudo)) 804168f382dc67e5940cabdb28dc933c4f91cdd3137Bob Wilson .addFrameIndex(FI).addImm(16) 805168f382dc67e5940cabdb28dc933c4f91cdd3137Bob Wilson .addReg(SrcReg, getKillRegState(isKill)) 806168f382dc67e5940cabdb28dc933c4f91cdd3137Bob Wilson .addMemOperand(MMO)); 807e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson } else { 808e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson MachineInstrBuilder MIB = 809e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMDIA)) 81073fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling .addFrameIndex(FI)) 811e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson .addMemOperand(MMO); 812e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI); 813e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI); 814e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI); 815e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI); 816e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson } 817e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson } else 818e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson llvm_unreachable("Unknown reg class!"); 819e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson break; 820e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson case 64: 821e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson if (ARM::QQQQPRRegClass.hasSubClassEq(RC)) { 822e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson MachineInstrBuilder MIB = 823e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMDIA)) 824e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson .addFrameIndex(FI)) 825e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson .addMemOperand(MMO); 826e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI); 827e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI); 828e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI); 829e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson MIB = AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI); 830e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson MIB = AddDReg(MIB, SrcReg, ARM::dsub_4, 0, TRI); 831e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson MIB = AddDReg(MIB, SrcReg, ARM::dsub_5, 0, TRI); 832e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson MIB = AddDReg(MIB, SrcReg, ARM::dsub_6, 0, TRI); 833e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson AddDReg(MIB, SrcReg, ARM::dsub_7, 0, TRI); 834e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson } else 835e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson llvm_unreachable("Unknown reg class!"); 836e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson break; 837e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson default: 838e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson llvm_unreachable("Unknown reg class!"); 839334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 840334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 841334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 84234327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesenunsigned 84334327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund OlesenARMBaseInstrInfo::isStoreToStackSlot(const MachineInstr *MI, 84434327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen int &FrameIndex) const { 84534327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen switch (MI->getOpcode()) { 84634327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen default: break; 8477e3383c007f53b3a00675af225e428cb66ddf404Jim Grosbach case ARM::STRrs: 84834327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen case ARM::t2STRs: // FIXME: don't use t2STRs to access frame. 84934327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen if (MI->getOperand(1).isFI() && 85034327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen MI->getOperand(2).isReg() && 85134327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen MI->getOperand(3).isImm() && 85234327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen MI->getOperand(2).getReg() == 0 && 85334327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen MI->getOperand(3).getImm() == 0) { 85434327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen FrameIndex = MI->getOperand(1).getIndex(); 85534327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen return MI->getOperand(0).getReg(); 85634327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen } 85734327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen break; 8587e3383c007f53b3a00675af225e428cb66ddf404Jim Grosbach case ARM::STRi12: 85934327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen case ARM::t2STRi12: 86074472b4bf963c424da04f42dffdb94c85ef964bcJim Grosbach case ARM::tSTRspi: 86134327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen case ARM::VSTRD: 86234327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen case ARM::VSTRS: 86334327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen if (MI->getOperand(1).isFI() && 86434327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen MI->getOperand(2).isImm() && 86534327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen MI->getOperand(2).getImm() == 0) { 86634327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen FrameIndex = MI->getOperand(1).getIndex(); 86734327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen return MI->getOperand(0).getReg(); 86834327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen } 86934327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen break; 87028f08c93e75d291695ea89b9004145103292e85bJim Grosbach case ARM::VST1q64: 871d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen if (MI->getOperand(0).isFI() && 872d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen MI->getOperand(2).getSubReg() == 0) { 873d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen FrameIndex = MI->getOperand(0).getIndex(); 874d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen return MI->getOperand(2).getReg(); 875d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen } 87631bbc51ac9245bc82c933c9db8358ca9bb558ac5Jakob Stoklund Olesen break; 87773fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMQIA: 878d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen if (MI->getOperand(1).isFI() && 879d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen MI->getOperand(0).getSubReg() == 0) { 880d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen FrameIndex = MI->getOperand(1).getIndex(); 881d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen return MI->getOperand(0).getReg(); 882d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen } 883d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen break; 88434327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen } 88534327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen 88634327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen return 0; 88734327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen} 88834327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen 88936ee0e640554b8cc6ad1658fc3049e05d9967160Jakob Stoklund Olesenunsigned ARMBaseInstrInfo::isStoreToStackSlotPostFE(const MachineInstr *MI, 89036ee0e640554b8cc6ad1658fc3049e05d9967160Jakob Stoklund Olesen int &FrameIndex) const { 89136ee0e640554b8cc6ad1658fc3049e05d9967160Jakob Stoklund Olesen const MachineMemOperand *Dummy; 8925a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng return MI->mayStore() && hasStoreToStackSlot(MI, Dummy, FrameIndex); 89336ee0e640554b8cc6ad1658fc3049e05d9967160Jakob Stoklund Olesen} 89436ee0e640554b8cc6ad1658fc3049e05d9967160Jakob Stoklund Olesen 895334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinvoid ARMBaseInstrInfo:: 896334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinloadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 897334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned DestReg, int FI, 898746ad69e088176819981b4b2c5ac8dcd49f5e60eEvan Cheng const TargetRegisterClass *RC, 899746ad69e088176819981b4b2c5ac8dcd49f5e60eEvan Cheng const TargetRegisterInfo *TRI) const { 900c7f3ace20c325521c68335a1689645b43b06ddf0Chris Lattner DebugLoc DL; 901334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (I != MBB.end()) DL = I->getDebugLoc(); 902249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MachineFunction &MF = *MBB.getParent(); 903249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MachineFrameInfo &MFI = *MF.getFrameInfo(); 90431bc849123011b8eae6bb3c79876d9a3c26a6a1dJim Grosbach unsigned Align = MFI.getObjectAlignment(FI); 905249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MachineMemOperand *MMO = 90659db5496f4fc2ef6111569e542f8b65480ef14c1Chris Lattner MF.getMachineMemOperand( 907978e0dfe46e481bfb1281e683aa308329e879e95Jay Foad MachinePointerInfo::getFixedStack(FI), 90859db5496f4fc2ef6111569e542f8b65480ef14c1Chris Lattner MachineMemOperand::MOLoad, 909249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MFI.getObjectSize(FI), 91031bc849123011b8eae6bb3c79876d9a3c26a6a1dJim Grosbach Align); 911334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 912e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson switch (RC->getSize()) { 913e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson case 4: 914e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson if (ARM::GPRRegClass.hasSubClassEq(RC)) { 915e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::LDRi12), DestReg) 9163e5561247202bae994dd259a2d8dc4eff8f799f3Jim Grosbach .addFrameIndex(FI).addImm(0).addMemOperand(MMO)); 917e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson 918e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson } else if (ARM::SPRRegClass.hasSubClassEq(RC)) { 919e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRS), DestReg) 920d31c5496d7e1580058b5c6fbc8fd537a641ea590Evan Cheng .addFrameIndex(FI).addImm(0).addMemOperand(MMO)); 921e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson } else 922e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson llvm_unreachable("Unknown reg class!"); 923ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson break; 924e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson case 8: 925e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson if (ARM::DPRRegClass.hasSubClassEq(RC)) { 926e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRD), DestReg) 927249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov .addFrameIndex(FI).addImm(0).addMemOperand(MMO)); 928e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson } else 929e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson llvm_unreachable("Unknown reg class!"); 930ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson break; 931e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson case 16: 9325b2f9136644c58ae32e00d8317540692a697d1c9Jakob Stoklund Olesen if (ARM::DPairRegClass.hasSubClassEq(RC)) { 9337255a4e1332ccb69918ebe041dff05f9e4e5815dJakob Stoklund Olesen if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) { 93428f08c93e75d291695ea89b9004145103292e85bJim Grosbach AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1q64), DestReg) 935f967ca0eaf30325cabe3c1971bf0dba16cf1b027Bob Wilson .addFrameIndex(FI).addImm(16) 93669b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng .addMemOperand(MMO)); 937e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson } else { 938e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMQIA), DestReg) 939e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson .addFrameIndex(FI) 940e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson .addMemOperand(MMO)); 941e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson } 942e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson } else 943e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson llvm_unreachable("Unknown reg class!"); 944ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson break; 945e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson case 32: 946e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson if (ARM::QQPRRegClass.hasSubClassEq(RC)) { 947e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) { 948e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1d64QPseudo), DestReg) 949168f382dc67e5940cabdb28dc933c4f91cdd3137Bob Wilson .addFrameIndex(FI).addImm(16) 950168f382dc67e5940cabdb28dc933c4f91cdd3137Bob Wilson .addMemOperand(MMO)); 951e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson } else { 952e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson MachineInstrBuilder MIB = 95373fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMDIA)) 95473fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling .addFrameIndex(FI)) 955e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson .addMemOperand(MMO); 956fce711cb65716f86b4e150f42cbb597bbecf7dbeJakob Stoklund Olesen MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI); 957fce711cb65716f86b4e150f42cbb597bbecf7dbeJakob Stoklund Olesen MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI); 958fce711cb65716f86b4e150f42cbb597bbecf7dbeJakob Stoklund Olesen MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI); 959fce711cb65716f86b4e150f42cbb597bbecf7dbeJakob Stoklund Olesen MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::DefineNoRead, TRI); 9603247af294996ff8588077c06505b64966ad41542Jakob Stoklund Olesen if (TargetRegisterInfo::isPhysicalRegister(DestReg)) 9613247af294996ff8588077c06505b64966ad41542Jakob Stoklund Olesen MIB.addReg(DestReg, RegState::ImplicitDefine); 962e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson } 963e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson } else 964e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson llvm_unreachable("Unknown reg class!"); 965ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson break; 966e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson case 64: 967e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson if (ARM::QQQQPRRegClass.hasSubClassEq(RC)) { 968e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson MachineInstrBuilder MIB = 96973fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMDIA)) 97073fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling .addFrameIndex(FI)) 971e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson .addMemOperand(MMO); 972fce711cb65716f86b4e150f42cbb597bbecf7dbeJakob Stoklund Olesen MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI); 973fce711cb65716f86b4e150f42cbb597bbecf7dbeJakob Stoklund Olesen MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI); 974fce711cb65716f86b4e150f42cbb597bbecf7dbeJakob Stoklund Olesen MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI); 975fce711cb65716f86b4e150f42cbb597bbecf7dbeJakob Stoklund Olesen MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::DefineNoRead, TRI); 976fce711cb65716f86b4e150f42cbb597bbecf7dbeJakob Stoklund Olesen MIB = AddDReg(MIB, DestReg, ARM::dsub_4, RegState::DefineNoRead, TRI); 977fce711cb65716f86b4e150f42cbb597bbecf7dbeJakob Stoklund Olesen MIB = AddDReg(MIB, DestReg, ARM::dsub_5, RegState::DefineNoRead, TRI); 978fce711cb65716f86b4e150f42cbb597bbecf7dbeJakob Stoklund Olesen MIB = AddDReg(MIB, DestReg, ARM::dsub_6, RegState::DefineNoRead, TRI); 979fce711cb65716f86b4e150f42cbb597bbecf7dbeJakob Stoklund Olesen MIB = AddDReg(MIB, DestReg, ARM::dsub_7, RegState::DefineNoRead, TRI); 9803247af294996ff8588077c06505b64966ad41542Jakob Stoklund Olesen if (TargetRegisterInfo::isPhysicalRegister(DestReg)) 9813247af294996ff8588077c06505b64966ad41542Jakob Stoklund Olesen MIB.addReg(DestReg, RegState::ImplicitDefine); 982e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson } else 983e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson llvm_unreachable("Unknown reg class!"); 984ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson break; 985ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson default: 986ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson llvm_unreachable("Unknown regclass!"); 987334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 988334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 989334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 99034327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesenunsigned 99134327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund OlesenARMBaseInstrInfo::isLoadFromStackSlot(const MachineInstr *MI, 99234327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen int &FrameIndex) const { 99334327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen switch (MI->getOpcode()) { 99434327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen default: break; 9953e5561247202bae994dd259a2d8dc4eff8f799f3Jim Grosbach case ARM::LDRrs: 99634327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen case ARM::t2LDRs: // FIXME: don't use t2LDRs to access frame. 99734327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen if (MI->getOperand(1).isFI() && 99834327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen MI->getOperand(2).isReg() && 99934327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen MI->getOperand(3).isImm() && 100034327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen MI->getOperand(2).getReg() == 0 && 100134327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen MI->getOperand(3).getImm() == 0) { 100234327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen FrameIndex = MI->getOperand(1).getIndex(); 100334327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen return MI->getOperand(0).getReg(); 100434327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen } 100534327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen break; 10063e5561247202bae994dd259a2d8dc4eff8f799f3Jim Grosbach case ARM::LDRi12: 100734327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen case ARM::t2LDRi12: 100874472b4bf963c424da04f42dffdb94c85ef964bcJim Grosbach case ARM::tLDRspi: 100934327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen case ARM::VLDRD: 101034327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen case ARM::VLDRS: 101134327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen if (MI->getOperand(1).isFI() && 101234327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen MI->getOperand(2).isImm() && 101334327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen MI->getOperand(2).getImm() == 0) { 101434327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen FrameIndex = MI->getOperand(1).getIndex(); 1015d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen return MI->getOperand(0).getReg(); 1016d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen } 1017d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen break; 101828f08c93e75d291695ea89b9004145103292e85bJim Grosbach case ARM::VLD1q64: 1019d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen if (MI->getOperand(1).isFI() && 1020d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen MI->getOperand(0).getSubReg() == 0) { 1021d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen FrameIndex = MI->getOperand(1).getIndex(); 102206f264e504d75f0426eea55b9f9e36c780d8a4fcJakob Stoklund Olesen return MI->getOperand(0).getReg(); 102306f264e504d75f0426eea55b9f9e36c780d8a4fcJakob Stoklund Olesen } 102406f264e504d75f0426eea55b9f9e36c780d8a4fcJakob Stoklund Olesen break; 102573fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMQIA: 102606f264e504d75f0426eea55b9f9e36c780d8a4fcJakob Stoklund Olesen if (MI->getOperand(1).isFI() && 102706f264e504d75f0426eea55b9f9e36c780d8a4fcJakob Stoklund Olesen MI->getOperand(0).getSubReg() == 0) { 102806f264e504d75f0426eea55b9f9e36c780d8a4fcJakob Stoklund Olesen FrameIndex = MI->getOperand(1).getIndex(); 102934327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen return MI->getOperand(0).getReg(); 103034327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen } 103134327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen break; 103234327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen } 103334327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen 103434327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen return 0; 103534327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen} 103634327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen 103736ee0e640554b8cc6ad1658fc3049e05d9967160Jakob Stoklund Olesenunsigned ARMBaseInstrInfo::isLoadFromStackSlotPostFE(const MachineInstr *MI, 103836ee0e640554b8cc6ad1658fc3049e05d9967160Jakob Stoklund Olesen int &FrameIndex) const { 103936ee0e640554b8cc6ad1658fc3049e05d9967160Jakob Stoklund Olesen const MachineMemOperand *Dummy; 10405a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng return MI->mayLoad() && hasLoadFromStackSlot(MI, Dummy, FrameIndex); 104136ee0e640554b8cc6ad1658fc3049e05d9967160Jakob Stoklund Olesen} 104236ee0e640554b8cc6ad1658fc3049e05d9967160Jakob Stoklund Olesen 1043142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesenbool ARMBaseInstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const{ 1044142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen // This hook gets to expand COPY instructions before they become 1045142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen // copyPhysReg() calls. Look for VMOVS instructions that can legally be 1046142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen // widened to VMOVD. We prefer the VMOVD when possible because it may be 1047142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen // changed into a VORR that can go down the NEON pipeline. 1048142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen if (!WidenVMOVS || !MI->isCopy()) 1049142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen return false; 1050142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen 1051142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen // Look for a copy between even S-registers. That is where we keep floats 1052142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen // when using NEON v2f32 instructions for f32 arithmetic. 1053142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen unsigned DstRegS = MI->getOperand(0).getReg(); 1054142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen unsigned SrcRegS = MI->getOperand(1).getReg(); 1055142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen if (!ARM::SPRRegClass.contains(DstRegS, SrcRegS)) 1056142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen return false; 1057142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen 1058142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen const TargetRegisterInfo *TRI = &getRegisterInfo(); 1059142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen unsigned DstRegD = TRI->getMatchingSuperReg(DstRegS, ARM::ssub_0, 1060142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen &ARM::DPRRegClass); 1061142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen unsigned SrcRegD = TRI->getMatchingSuperReg(SrcRegS, ARM::ssub_0, 1062142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen &ARM::DPRRegClass); 1063142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen if (!DstRegD || !SrcRegD) 1064142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen return false; 1065142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen 1066142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen // We want to widen this into a DstRegD = VMOVD SrcRegD copy. This is only 1067142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen // legal if the COPY already defines the full DstRegD, and it isn't a 1068142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen // sub-register insertion. 1069142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen if (!MI->definesRegister(DstRegD, TRI) || MI->readsRegister(DstRegD, TRI)) 1070142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen return false; 1071142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen 10721c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen // A dead copy shouldn't show up here, but reject it just in case. 10731c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen if (MI->getOperand(0).isDead()) 10741c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen return false; 10751c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen 10761c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen // All clear, widen the COPY. 1077142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen DEBUG(dbgs() << "widening: " << *MI); 10781c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen 10791c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen // Get rid of the old <imp-def> of DstRegD. Leave it if it defines a Q-reg 10801c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen // or some other super-register. 10811c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen int ImpDefIdx = MI->findRegisterDefOperandIdx(DstRegD); 10821c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen if (ImpDefIdx != -1) 10831c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen MI->RemoveOperand(ImpDefIdx); 10841c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen 10851c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen // Change the opcode and operands. 1086142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen MI->setDesc(get(ARM::VMOVD)); 1087142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen MI->getOperand(0).setReg(DstRegD); 1088142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen MI->getOperand(1).setReg(SrcRegD); 1089142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen AddDefaultPred(MachineInstrBuilder(MI)); 10901c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen 10911c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen // We are now reading SrcRegD instead of SrcRegS. This may upset the 10921c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen // register scavenger and machine verifier, so we need to indicate that we 10931c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen // are reading an undefined value from SrcRegD, but a proper value from 10941c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen // SrcRegS. 10951c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen MI->getOperand(1).setIsUndef(); 10961c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen MachineInstrBuilder(MI).addReg(SrcRegS, RegState::Implicit); 10971c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen 10981c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen // SrcRegD may actually contain an unrelated value in the ssub_1 10991c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen // sub-register. Don't kill it. Only kill the ssub_0 sub-register. 11001c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen if (MI->getOperand(1).isKill()) { 11011c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen MI->getOperand(1).setIsKill(false); 11021c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen MI->addRegisterKilled(SrcRegS, TRI, true); 11031c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen } 11041c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen 1105142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen DEBUG(dbgs() << "replaced by: " << *MI); 1106142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen return true; 1107142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen} 1108142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen 110962b50656ceb854eb0be265d63b2a1d46e7400d8aEvan ChengMachineInstr* 111062b50656ceb854eb0be265d63b2a1d46e7400d8aEvan ChengARMBaseInstrInfo::emitFrameIndexDebugValue(MachineFunction &MF, 11118601a3d4decff0a380e059b037dabf71075497d3Evan Cheng int FrameIx, uint64_t Offset, 111262b50656ceb854eb0be265d63b2a1d46e7400d8aEvan Cheng const MDNode *MDPtr, 111362b50656ceb854eb0be265d63b2a1d46e7400d8aEvan Cheng DebugLoc DL) const { 111462b50656ceb854eb0be265d63b2a1d46e7400d8aEvan Cheng MachineInstrBuilder MIB = BuildMI(MF, DL, get(ARM::DBG_VALUE)) 111562b50656ceb854eb0be265d63b2a1d46e7400d8aEvan Cheng .addFrameIndex(FrameIx).addImm(0).addImm(Offset).addMetadata(MDPtr); 111662b50656ceb854eb0be265d63b2a1d46e7400d8aEvan Cheng return &*MIB; 111762b50656ceb854eb0be265d63b2a1d46e7400d8aEvan Cheng} 111862b50656ceb854eb0be265d63b2a1d46e7400d8aEvan Cheng 111930ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen/// Create a copy of a const pool value. Update CPI to the new index and return 112030ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen/// the label UID. 112130ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesenstatic unsigned duplicateCPV(MachineFunction &MF, unsigned &CPI) { 112230ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen MachineConstantPool *MCP = MF.getConstantPool(); 112330ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 112430ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen 112530ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPI]; 112630ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen assert(MCPE.isMachineConstantPoolEntry() && 112730ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen "Expecting a machine constantpool entry!"); 112830ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen ARMConstantPoolValue *ACPV = 112930ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal); 113030ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen 11315de5d4b6d0eb3fd379fa571d82f6fa764460b3b8Evan Cheng unsigned PCLabelId = AFI->createPICLabelUId(); 113230ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen ARMConstantPoolValue *NewCPV = 0; 113351f5b67395780b8421f4aa6ee998ed51b23dae9dJim Grosbach // FIXME: The below assumes PIC relocation model and that the function 113451f5b67395780b8421f4aa6ee998ed51b23dae9dJim Grosbach // is Thumb mode (t1 or t2). PCAdjustment would be 8 for ARM mode PIC, and 113551f5b67395780b8421f4aa6ee998ed51b23dae9dJim Grosbach // zero for non-PIC in ARM or Thumb. The callers are all of thumb LDR 113651f5b67395780b8421f4aa6ee998ed51b23dae9dJim Grosbach // instructions, so that's probably OK, but is PIC always correct when 113751f5b67395780b8421f4aa6ee998ed51b23dae9dJim Grosbach // we get here? 113830ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen if (ACPV->isGlobalValue()) 11395bb779976a7d8e48408051ec2289fe69206dc072Bill Wendling NewCPV = ARMConstantPoolConstant:: 11405bb779976a7d8e48408051ec2289fe69206dc072Bill Wendling Create(cast<ARMConstantPoolConstant>(ACPV)->getGV(), PCLabelId, 11415bb779976a7d8e48408051ec2289fe69206dc072Bill Wendling ARMCP::CPValue, 4); 114230ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen else if (ACPV->isExtSymbol()) 1143fe31e673506ef9a1080eaa684b43b34178c6f447Bill Wendling NewCPV = ARMConstantPoolSymbol:: 1144fe31e673506ef9a1080eaa684b43b34178c6f447Bill Wendling Create(MF.getFunction()->getContext(), 1145fe31e673506ef9a1080eaa684b43b34178c6f447Bill Wendling cast<ARMConstantPoolSymbol>(ACPV)->getSymbol(), PCLabelId, 4); 114630ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen else if (ACPV->isBlockAddress()) 11475bb779976a7d8e48408051ec2289fe69206dc072Bill Wendling NewCPV = ARMConstantPoolConstant:: 11485bb779976a7d8e48408051ec2289fe69206dc072Bill Wendling Create(cast<ARMConstantPoolConstant>(ACPV)->getBlockAddress(), PCLabelId, 11495bb779976a7d8e48408051ec2289fe69206dc072Bill Wendling ARMCP::CPBlockAddress, 4); 115051f5b67395780b8421f4aa6ee998ed51b23dae9dJim Grosbach else if (ACPV->isLSDA()) 11515bb779976a7d8e48408051ec2289fe69206dc072Bill Wendling NewCPV = ARMConstantPoolConstant::Create(MF.getFunction(), PCLabelId, 11525bb779976a7d8e48408051ec2289fe69206dc072Bill Wendling ARMCP::CPLSDA, 4); 1153e00897c5a91febe90ba21082fc636be892bf9bf1Bill Wendling else if (ACPV->isMachineBasicBlock()) 11543320f2a3bfd4daec23ba7ceb50525140cc6316daBill Wendling NewCPV = ARMConstantPoolMBB:: 11553320f2a3bfd4daec23ba7ceb50525140cc6316daBill Wendling Create(MF.getFunction()->getContext(), 11563320f2a3bfd4daec23ba7ceb50525140cc6316daBill Wendling cast<ARMConstantPoolMBB>(ACPV)->getMBB(), PCLabelId, 4); 115730ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen else 115830ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen llvm_unreachable("Unexpected ARM constantpool value type!!"); 115930ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen CPI = MCP->getConstantPoolIndex(NewCPV, MCPE.getAlignment()); 116030ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen return PCLabelId; 116130ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen} 116230ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen 1163fdc834046efd427d474e3b899ec69354c05071e0Evan Chengvoid ARMBaseInstrInfo:: 1164fdc834046efd427d474e3b899ec69354c05071e0Evan ChengreMaterialize(MachineBasicBlock &MBB, 1165fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng MachineBasicBlock::iterator I, 1166fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng unsigned DestReg, unsigned SubIdx, 1167d57cdd5683ea926e489067364fb7ffe5fd5d35eeEvan Cheng const MachineInstr *Orig, 11689edf7deb37f0f97664f279040fa15d89f32e23d9Jakob Stoklund Olesen const TargetRegisterInfo &TRI) const { 1169fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng unsigned Opcode = Orig->getOpcode(); 1170fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng switch (Opcode) { 1171fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng default: { 1172fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig); 11739edf7deb37f0f97664f279040fa15d89f32e23d9Jakob Stoklund Olesen MI->substituteRegister(Orig->getOperand(0).getReg(), DestReg, SubIdx, TRI); 1174fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng MBB.insert(I, MI); 1175fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng break; 1176fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng } 1177fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng case ARM::tLDRpci_pic: 1178fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng case ARM::t2LDRpci_pic: { 1179fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng MachineFunction &MF = *MBB.getParent(); 1180fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng unsigned CPI = Orig->getOperand(1).getIndex(); 118130ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen unsigned PCLabelId = duplicateCPV(MF, CPI); 1182fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng MachineInstrBuilder MIB = BuildMI(MBB, I, Orig->getDebugLoc(), get(Opcode), 1183fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng DestReg) 1184fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng .addConstantPoolIndex(CPI).addImm(PCLabelId); 1185d7d030a44796adc73a6eaa939cd17e52047734c1Chris Lattner MIB->setMemRefs(Orig->memoperands_begin(), Orig->memoperands_end()); 1186fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng break; 1187fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng } 1188fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng } 1189fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng} 1190fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng 119130ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund OlesenMachineInstr * 119230ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund OlesenARMBaseInstrInfo::duplicate(MachineInstr *Orig, MachineFunction &MF) const { 119330ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen MachineInstr *MI = TargetInstrInfoImpl::duplicate(Orig, MF); 119430ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen switch(Orig->getOpcode()) { 119530ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen case ARM::tLDRpci_pic: 119630ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen case ARM::t2LDRpci_pic: { 119730ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen unsigned CPI = Orig->getOperand(1).getIndex(); 119830ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen unsigned PCLabelId = duplicateCPV(MF, CPI); 119930ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen Orig->getOperand(1).setIndex(CPI); 120030ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen Orig->getOperand(2).setImm(PCLabelId); 120130ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen break; 120230ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen } 120330ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen } 120430ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen return MI; 120530ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen} 120630ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen 1207506049f29f4f202a8e45feb916cc0264440a7f6dEvan Chengbool ARMBaseInstrInfo::produceSameValue(const MachineInstr *MI0, 12089fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng const MachineInstr *MI1, 12099fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng const MachineRegisterInfo *MRI) const { 1210d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng int Opcode = MI0->getOpcode(); 1211d7e3cc840b81b0438e47f05d9664137a198876dfEvan Cheng if (Opcode == ARM::t2LDRpci || 12129b82425cb0105fd5704f6b9bcd5e7693b05b1759Evan Cheng Opcode == ARM::t2LDRpci_pic || 12139b82425cb0105fd5704f6b9bcd5e7693b05b1759Evan Cheng Opcode == ARM::tLDRpci || 12149fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng Opcode == ARM::tLDRpci_pic || 121553519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng Opcode == ARM::MOV_ga_dyn || 121653519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng Opcode == ARM::MOV_ga_pcrel || 121753519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng Opcode == ARM::MOV_ga_pcrel_ldr || 121853519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng Opcode == ARM::t2MOV_ga_dyn || 121953519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng Opcode == ARM::t2MOV_ga_pcrel) { 1220d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng if (MI1->getOpcode() != Opcode) 1221d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng return false; 1222d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng if (MI0->getNumOperands() != MI1->getNumOperands()) 1223d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng return false; 1224d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng 1225d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng const MachineOperand &MO0 = MI0->getOperand(1); 1226d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng const MachineOperand &MO1 = MI1->getOperand(1); 1227d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng if (MO0.getOffset() != MO1.getOffset()) 1228d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng return false; 1229d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng 123053519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng if (Opcode == ARM::MOV_ga_dyn || 123153519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng Opcode == ARM::MOV_ga_pcrel || 123253519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng Opcode == ARM::MOV_ga_pcrel_ldr || 123353519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng Opcode == ARM::t2MOV_ga_dyn || 123453519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng Opcode == ARM::t2MOV_ga_pcrel) 12359fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng // Ignore the PC labels. 12369fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng return MO0.getGlobal() == MO1.getGlobal(); 12379fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng 1238d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng const MachineFunction *MF = MI0->getParent()->getParent(); 1239d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng const MachineConstantPool *MCP = MF->getConstantPool(); 1240d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng int CPI0 = MO0.getIndex(); 1241d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng int CPI1 = MO1.getIndex(); 1242d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng const MachineConstantPoolEntry &MCPE0 = MCP->getConstants()[CPI0]; 1243d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng const MachineConstantPoolEntry &MCPE1 = MCP->getConstants()[CPI1]; 1244d700617193f3d11deb83cd56c4ababbc8e0ea19fEvan Cheng bool isARMCP0 = MCPE0.isMachineConstantPoolEntry(); 1245d700617193f3d11deb83cd56c4ababbc8e0ea19fEvan Cheng bool isARMCP1 = MCPE1.isMachineConstantPoolEntry(); 1246d700617193f3d11deb83cd56c4ababbc8e0ea19fEvan Cheng if (isARMCP0 && isARMCP1) { 1247d700617193f3d11deb83cd56c4ababbc8e0ea19fEvan Cheng ARMConstantPoolValue *ACPV0 = 1248d700617193f3d11deb83cd56c4ababbc8e0ea19fEvan Cheng static_cast<ARMConstantPoolValue*>(MCPE0.Val.MachineCPVal); 1249d700617193f3d11deb83cd56c4ababbc8e0ea19fEvan Cheng ARMConstantPoolValue *ACPV1 = 1250d700617193f3d11deb83cd56c4ababbc8e0ea19fEvan Cheng static_cast<ARMConstantPoolValue*>(MCPE1.Val.MachineCPVal); 1251d700617193f3d11deb83cd56c4ababbc8e0ea19fEvan Cheng return ACPV0->hasSameValue(ACPV1); 1252d700617193f3d11deb83cd56c4ababbc8e0ea19fEvan Cheng } else if (!isARMCP0 && !isARMCP1) { 1253d700617193f3d11deb83cd56c4ababbc8e0ea19fEvan Cheng return MCPE0.Val.ConstVal == MCPE1.Val.ConstVal; 1254d700617193f3d11deb83cd56c4ababbc8e0ea19fEvan Cheng } 1255d700617193f3d11deb83cd56c4ababbc8e0ea19fEvan Cheng return false; 12569fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng } else if (Opcode == ARM::PICLDR) { 12579fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng if (MI1->getOpcode() != Opcode) 12589fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng return false; 12599fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng if (MI0->getNumOperands() != MI1->getNumOperands()) 12609fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng return false; 12619fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng 12629fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng unsigned Addr0 = MI0->getOperand(1).getReg(); 12639fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng unsigned Addr1 = MI1->getOperand(1).getReg(); 12649fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng if (Addr0 != Addr1) { 12659fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng if (!MRI || 12669fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng !TargetRegisterInfo::isVirtualRegister(Addr0) || 12679fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng !TargetRegisterInfo::isVirtualRegister(Addr1)) 12689fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng return false; 12699fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng 12709fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng // This assumes SSA form. 12719fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng MachineInstr *Def0 = MRI->getVRegDef(Addr0); 12729fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng MachineInstr *Def1 = MRI->getVRegDef(Addr1); 12739fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng // Check if the loaded value, e.g. a constantpool of a global address, are 12749fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng // the same. 12759fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng if (!produceSameValue(Def0, Def1, MRI)) 12769fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng return false; 12779fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng } 12789fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng 12799fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng for (unsigned i = 3, e = MI0->getNumOperands(); i != e; ++i) { 12809fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng // %vreg12<def> = PICLDR %vreg11, 0, pred:14, pred:%noreg 12819fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng const MachineOperand &MO0 = MI0->getOperand(i); 12829fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng const MachineOperand &MO1 = MI1->getOperand(i); 12839fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng if (!MO0.isIdenticalTo(MO1)) 12849fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng return false; 12859fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng } 12869fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng return true; 1287d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng } 1288d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng 1289506049f29f4f202a8e45feb916cc0264440a7f6dEvan Cheng return MI0->isIdenticalTo(MI1, MachineInstr::IgnoreVRegDefs); 1290d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng} 1291d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng 12924b722108e2cf8e77157e0879a23789cd44829933Bill Wendling/// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to 12934b722108e2cf8e77157e0879a23789cd44829933Bill Wendling/// determine if two loads are loading from the same base address. It should 12944b722108e2cf8e77157e0879a23789cd44829933Bill Wendling/// only return true if the base pointers are the same and the only differences 12954b722108e2cf8e77157e0879a23789cd44829933Bill Wendling/// between the two addresses is the offset. It also returns the offsets by 12964b722108e2cf8e77157e0879a23789cd44829933Bill Wendling/// reference. 12974b722108e2cf8e77157e0879a23789cd44829933Bill Wendlingbool ARMBaseInstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, 12984b722108e2cf8e77157e0879a23789cd44829933Bill Wendling int64_t &Offset1, 12994b722108e2cf8e77157e0879a23789cd44829933Bill Wendling int64_t &Offset2) const { 13004b722108e2cf8e77157e0879a23789cd44829933Bill Wendling // Don't worry about Thumb: just ARM and Thumb2. 13014b722108e2cf8e77157e0879a23789cd44829933Bill Wendling if (Subtarget.isThumb1Only()) return false; 13024b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 13034b722108e2cf8e77157e0879a23789cd44829933Bill Wendling if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode()) 13044b722108e2cf8e77157e0879a23789cd44829933Bill Wendling return false; 13054b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 13064b722108e2cf8e77157e0879a23789cd44829933Bill Wendling switch (Load1->getMachineOpcode()) { 13074b722108e2cf8e77157e0879a23789cd44829933Bill Wendling default: 13084b722108e2cf8e77157e0879a23789cd44829933Bill Wendling return false; 13093e5561247202bae994dd259a2d8dc4eff8f799f3Jim Grosbach case ARM::LDRi12: 1310c1d30212e911d1e55ff6b25bffefb503708883c3Jim Grosbach case ARM::LDRBi12: 13114b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::LDRD: 13124b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::LDRH: 13134b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::LDRSB: 13144b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::LDRSH: 13154b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::VLDRD: 13164b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::VLDRS: 13174b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::t2LDRi8: 13184b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::t2LDRDi8: 13194b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::t2LDRSHi8: 13204b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::t2LDRi12: 13214b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::t2LDRSHi12: 13224b722108e2cf8e77157e0879a23789cd44829933Bill Wendling break; 13234b722108e2cf8e77157e0879a23789cd44829933Bill Wendling } 13244b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 13254b722108e2cf8e77157e0879a23789cd44829933Bill Wendling switch (Load2->getMachineOpcode()) { 13264b722108e2cf8e77157e0879a23789cd44829933Bill Wendling default: 13274b722108e2cf8e77157e0879a23789cd44829933Bill Wendling return false; 13283e5561247202bae994dd259a2d8dc4eff8f799f3Jim Grosbach case ARM::LDRi12: 1329c1d30212e911d1e55ff6b25bffefb503708883c3Jim Grosbach case ARM::LDRBi12: 13304b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::LDRD: 13314b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::LDRH: 13324b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::LDRSB: 13334b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::LDRSH: 13344b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::VLDRD: 13354b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::VLDRS: 13364b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::t2LDRi8: 13374b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::t2LDRDi8: 13384b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::t2LDRSHi8: 13394b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::t2LDRi12: 13404b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::t2LDRSHi12: 13414b722108e2cf8e77157e0879a23789cd44829933Bill Wendling break; 13424b722108e2cf8e77157e0879a23789cd44829933Bill Wendling } 13434b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 13444b722108e2cf8e77157e0879a23789cd44829933Bill Wendling // Check if base addresses and chain operands match. 13454b722108e2cf8e77157e0879a23789cd44829933Bill Wendling if (Load1->getOperand(0) != Load2->getOperand(0) || 13464b722108e2cf8e77157e0879a23789cd44829933Bill Wendling Load1->getOperand(4) != Load2->getOperand(4)) 13474b722108e2cf8e77157e0879a23789cd44829933Bill Wendling return false; 13484b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 13494b722108e2cf8e77157e0879a23789cd44829933Bill Wendling // Index should be Reg0. 13504b722108e2cf8e77157e0879a23789cd44829933Bill Wendling if (Load1->getOperand(3) != Load2->getOperand(3)) 13514b722108e2cf8e77157e0879a23789cd44829933Bill Wendling return false; 13524b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 13534b722108e2cf8e77157e0879a23789cd44829933Bill Wendling // Determine the offsets. 13544b722108e2cf8e77157e0879a23789cd44829933Bill Wendling if (isa<ConstantSDNode>(Load1->getOperand(1)) && 13554b722108e2cf8e77157e0879a23789cd44829933Bill Wendling isa<ConstantSDNode>(Load2->getOperand(1))) { 13564b722108e2cf8e77157e0879a23789cd44829933Bill Wendling Offset1 = cast<ConstantSDNode>(Load1->getOperand(1))->getSExtValue(); 13574b722108e2cf8e77157e0879a23789cd44829933Bill Wendling Offset2 = cast<ConstantSDNode>(Load2->getOperand(1))->getSExtValue(); 13584b722108e2cf8e77157e0879a23789cd44829933Bill Wendling return true; 13594b722108e2cf8e77157e0879a23789cd44829933Bill Wendling } 13604b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 13614b722108e2cf8e77157e0879a23789cd44829933Bill Wendling return false; 13624b722108e2cf8e77157e0879a23789cd44829933Bill Wendling} 13634b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 13644b722108e2cf8e77157e0879a23789cd44829933Bill Wendling/// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to 13657a2bdde0a0eebcd2125055e0eacaca040f0b766cChris Lattner/// determine (in conjunction with areLoadsFromSameBasePtr) if two loads should 13664b722108e2cf8e77157e0879a23789cd44829933Bill Wendling/// be scheduled togther. On some targets if two loads are loading from 13674b722108e2cf8e77157e0879a23789cd44829933Bill Wendling/// addresses in the same cache line, it's better if they are scheduled 13684b722108e2cf8e77157e0879a23789cd44829933Bill Wendling/// together. This function takes two integers that represent the load offsets 13694b722108e2cf8e77157e0879a23789cd44829933Bill Wendling/// from the common base address. It returns true if it decides it's desirable 13704b722108e2cf8e77157e0879a23789cd44829933Bill Wendling/// to schedule the two loads together. "NumLoads" is the number of loads that 13714b722108e2cf8e77157e0879a23789cd44829933Bill Wendling/// have already been scheduled after Load1. 13724b722108e2cf8e77157e0879a23789cd44829933Bill Wendlingbool ARMBaseInstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, 13734b722108e2cf8e77157e0879a23789cd44829933Bill Wendling int64_t Offset1, int64_t Offset2, 13744b722108e2cf8e77157e0879a23789cd44829933Bill Wendling unsigned NumLoads) const { 13754b722108e2cf8e77157e0879a23789cd44829933Bill Wendling // Don't worry about Thumb: just ARM and Thumb2. 13764b722108e2cf8e77157e0879a23789cd44829933Bill Wendling if (Subtarget.isThumb1Only()) return false; 13774b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 13784b722108e2cf8e77157e0879a23789cd44829933Bill Wendling assert(Offset2 > Offset1); 13794b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 13804b722108e2cf8e77157e0879a23789cd44829933Bill Wendling if ((Offset2 - Offset1) / 8 > 64) 13814b722108e2cf8e77157e0879a23789cd44829933Bill Wendling return false; 13824b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 13834b722108e2cf8e77157e0879a23789cd44829933Bill Wendling if (Load1->getMachineOpcode() != Load2->getMachineOpcode()) 13844b722108e2cf8e77157e0879a23789cd44829933Bill Wendling return false; // FIXME: overly conservative? 13854b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 13864b722108e2cf8e77157e0879a23789cd44829933Bill Wendling // Four loads in a row should be sufficient. 13874b722108e2cf8e77157e0879a23789cd44829933Bill Wendling if (NumLoads >= 3) 13884b722108e2cf8e77157e0879a23789cd44829933Bill Wendling return false; 13894b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 13904b722108e2cf8e77157e0879a23789cd44829933Bill Wendling return true; 13914b722108e2cf8e77157e0879a23789cd44829933Bill Wendling} 13924b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 139386050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Chengbool ARMBaseInstrInfo::isSchedulingBoundary(const MachineInstr *MI, 139486050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng const MachineBasicBlock *MBB, 139586050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng const MachineFunction &MF) const { 139657bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach // Debug info is never a scheduling boundary. It's necessary to be explicit 139757bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach // due to the special treatment of IT instructions below, otherwise a 139857bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach // dbg_value followed by an IT will result in the IT instruction being 139957bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach // considered a scheduling hazard, which is wrong. It should be the actual 140057bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach // instruction preceding the dbg_value instruction(s), just like it is 140157bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach // when debug info is not present. 140257bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach if (MI->isDebugValue()) 140357bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach return false; 140457bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach 140586050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // Terminators and labels can't be scheduled around. 14065a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng if (MI->isTerminator() || MI->isLabel()) 140786050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng return true; 140886050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng 140986050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // Treat the start of the IT block as a scheduling boundary, but schedule 141086050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // t2IT along with all instructions following it. 141186050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // FIXME: This is a big hammer. But the alternative is to add all potential 141286050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // true and anti dependencies to IT block instructions as implicit operands 141386050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // to the t2IT instruction. The added compile time and complexity does not 141486050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // seem worth it. 141586050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng MachineBasicBlock::const_iterator I = MI; 141657bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach // Make sure to skip any dbg_value instructions 141757bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach while (++I != MBB->end() && I->isDebugValue()) 141857bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach ; 141957bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach if (I != MBB->end() && I->getOpcode() == ARM::t2IT) 142086050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng return true; 142186050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng 142286050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // Don't attempt to schedule around any instruction that defines 142386050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // a stack-oriented pointer, as it's unlikely to be profitable. This 142486050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // saves compile time, because it doesn't require every single 142586050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // stack slot reference to depend on the instruction that does the 142686050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // modification. 1427a1aa8db51715bdd21770fbe4f7d7abf2c5d28829Jakob Stoklund Olesen // Calls don't actually change the stack pointer, even if they have imp-defs. 1428209600bb8830036f981238494ab0188c25364837Jakob Stoklund Olesen // No ARM calling conventions change the stack pointer. (X86 calling 1429209600bb8830036f981238494ab0188c25364837Jakob Stoklund Olesen // conventions sometimes do). 1430a1aa8db51715bdd21770fbe4f7d7abf2c5d28829Jakob Stoklund Olesen if (!MI->isCall() && MI->definesRegister(ARM::SP)) 143186050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng return true; 143286050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng 143386050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng return false; 143486050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng} 143586050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng 1436f81b7f6069b27c0a515070dcb392f6828437412fJakub Staszakbool ARMBaseInstrInfo:: 1437f81b7f6069b27c0a515070dcb392f6828437412fJakub StaszakisProfitableToIfCvt(MachineBasicBlock &MBB, 1438f81b7f6069b27c0a515070dcb392f6828437412fJakub Staszak unsigned NumCycles, unsigned ExtraPredCycles, 1439f81b7f6069b27c0a515070dcb392f6828437412fJakub Staszak const BranchProbability &Probability) const { 14405876db7a66fcc4ec4444a9f3e387c1cdc8baf9e5Cameron Zwarich if (!NumCycles) 144113151432edace19ee867a93b5c14573df4f75d24Evan Cheng return false; 14422bbb76909126db5bed6bde84b16d94ab5de4d372Michael J. Spencer 1443b20b85168c0e9819e6545f08281e9b83c82108f0Owen Anderson // Attempt to estimate the relative costs of predication versus branching. 1444f81b7f6069b27c0a515070dcb392f6828437412fJakub Staszak unsigned UnpredCost = Probability.getNumerator() * NumCycles; 1445f81b7f6069b27c0a515070dcb392f6828437412fJakub Staszak UnpredCost /= Probability.getDenominator(); 1446f81b7f6069b27c0a515070dcb392f6828437412fJakub Staszak UnpredCost += 1; // The branch itself 1447f81b7f6069b27c0a515070dcb392f6828437412fJakub Staszak UnpredCost += Subtarget.getMispredictionPenalty() / 10; 14482bbb76909126db5bed6bde84b16d94ab5de4d372Michael J. Spencer 1449f81b7f6069b27c0a515070dcb392f6828437412fJakub Staszak return (NumCycles + ExtraPredCycles) <= UnpredCost; 145013151432edace19ee867a93b5c14573df4f75d24Evan Cheng} 14512bbb76909126db5bed6bde84b16d94ab5de4d372Michael J. Spencer 145213151432edace19ee867a93b5c14573df4f75d24Evan Chengbool ARMBaseInstrInfo:: 14538239daf7c83a65a189c352cce3191cdc3bbfe151Evan ChengisProfitableToIfCvt(MachineBasicBlock &TMBB, 14548239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng unsigned TCycles, unsigned TExtra, 14558239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng MachineBasicBlock &FMBB, 14568239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng unsigned FCycles, unsigned FExtra, 1457f81b7f6069b27c0a515070dcb392f6828437412fJakub Staszak const BranchProbability &Probability) const { 14588239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng if (!TCycles || !FCycles) 1459b20b85168c0e9819e6545f08281e9b83c82108f0Owen Anderson return false; 14602bbb76909126db5bed6bde84b16d94ab5de4d372Michael J. Spencer 1461b20b85168c0e9819e6545f08281e9b83c82108f0Owen Anderson // Attempt to estimate the relative costs of predication versus branching. 1462f81b7f6069b27c0a515070dcb392f6828437412fJakub Staszak unsigned TUnpredCost = Probability.getNumerator() * TCycles; 1463f81b7f6069b27c0a515070dcb392f6828437412fJakub Staszak TUnpredCost /= Probability.getDenominator(); 1464e23dc9c0ef50b0a1934c04c1786f3a0478d62f41Andrew Trick 1465f81b7f6069b27c0a515070dcb392f6828437412fJakub Staszak uint32_t Comp = Probability.getDenominator() - Probability.getNumerator(); 1466f81b7f6069b27c0a515070dcb392f6828437412fJakub Staszak unsigned FUnpredCost = Comp * FCycles; 1467f81b7f6069b27c0a515070dcb392f6828437412fJakub Staszak FUnpredCost /= Probability.getDenominator(); 1468f81b7f6069b27c0a515070dcb392f6828437412fJakub Staszak 1469f81b7f6069b27c0a515070dcb392f6828437412fJakub Staszak unsigned UnpredCost = TUnpredCost + FUnpredCost; 1470f81b7f6069b27c0a515070dcb392f6828437412fJakub Staszak UnpredCost += 1; // The branch itself 1471f81b7f6069b27c0a515070dcb392f6828437412fJakub Staszak UnpredCost += Subtarget.getMispredictionPenalty() / 10; 1472f81b7f6069b27c0a515070dcb392f6828437412fJakub Staszak 1473f81b7f6069b27c0a515070dcb392f6828437412fJakub Staszak return (TCycles + FCycles + TExtra + FExtra) <= UnpredCost; 147413151432edace19ee867a93b5c14573df4f75d24Evan Cheng} 147513151432edace19ee867a93b5c14573df4f75d24Evan Cheng 14768fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng/// getInstrPredicate - If instruction is predicated, returns its predicate 14778fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng/// condition, otherwise returns AL. It also returns the condition code 14788fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng/// register by reference. 14795adb66a646e2ec32265263739f5b01c3f50c176aEvan ChengARMCC::CondCodes 14805adb66a646e2ec32265263739f5b01c3f50c176aEvan Chengllvm::getInstrPredicate(const MachineInstr *MI, unsigned &PredReg) { 14818fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng int PIdx = MI->findFirstPredOperandIdx(); 14828fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng if (PIdx == -1) { 14838fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng PredReg = 0; 14848fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng return ARMCC::AL; 14858fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng } 14868fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng 14878fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng PredReg = MI->getOperand(PIdx+1).getReg(); 14888fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng return (ARMCC::CondCodes)MI->getOperand(PIdx).getImm(); 14898fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng} 14908fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng 14918fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng 14926495f63945e8dbde81f03a1dc2ab421993b9a495Evan Chengint llvm::getMatchingCondBranchOpcode(int Opc) { 14935ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng if (Opc == ARM::B) 14945ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng return ARM::Bcc; 14954d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie if (Opc == ARM::tB) 14965ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng return ARM::tBcc; 14974d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie if (Opc == ARM::t2B) 14984d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie return ARM::t2Bcc; 14995ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng 15005ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng llvm_unreachable("Unknown unconditional branch opcode!"); 15015ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng} 15025ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng 1503c5041cac7d3aeaa7350abadf2a7ada92e8da27dcJakob Stoklund Olesen/// commuteInstruction - Handle commutable instructions. 1504c5041cac7d3aeaa7350abadf2a7ada92e8da27dcJakob Stoklund OlesenMachineInstr * 1505c5041cac7d3aeaa7350abadf2a7ada92e8da27dcJakob Stoklund OlesenARMBaseInstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const { 1506c5041cac7d3aeaa7350abadf2a7ada92e8da27dcJakob Stoklund Olesen switch (MI->getOpcode()) { 1507c5041cac7d3aeaa7350abadf2a7ada92e8da27dcJakob Stoklund Olesen case ARM::MOVCCr: 1508c5041cac7d3aeaa7350abadf2a7ada92e8da27dcJakob Stoklund Olesen case ARM::t2MOVCCr: { 1509c5041cac7d3aeaa7350abadf2a7ada92e8da27dcJakob Stoklund Olesen // MOVCC can be commuted by inverting the condition. 1510c5041cac7d3aeaa7350abadf2a7ada92e8da27dcJakob Stoklund Olesen unsigned PredReg = 0; 1511c5041cac7d3aeaa7350abadf2a7ada92e8da27dcJakob Stoklund Olesen ARMCC::CondCodes CC = getInstrPredicate(MI, PredReg); 1512c5041cac7d3aeaa7350abadf2a7ada92e8da27dcJakob Stoklund Olesen // MOVCC AL can't be inverted. Shouldn't happen. 1513c5041cac7d3aeaa7350abadf2a7ada92e8da27dcJakob Stoklund Olesen if (CC == ARMCC::AL || PredReg != ARM::CPSR) 1514c5041cac7d3aeaa7350abadf2a7ada92e8da27dcJakob Stoklund Olesen return NULL; 1515c5041cac7d3aeaa7350abadf2a7ada92e8da27dcJakob Stoklund Olesen MI = TargetInstrInfoImpl::commuteInstruction(MI, NewMI); 1516c5041cac7d3aeaa7350abadf2a7ada92e8da27dcJakob Stoklund Olesen if (!MI) 1517c5041cac7d3aeaa7350abadf2a7ada92e8da27dcJakob Stoklund Olesen return NULL; 1518c5041cac7d3aeaa7350abadf2a7ada92e8da27dcJakob Stoklund Olesen // After swapping the MOVCC operands, also invert the condition. 1519c5041cac7d3aeaa7350abadf2a7ada92e8da27dcJakob Stoklund Olesen MI->getOperand(MI->findFirstPredOperandIdx()) 1520c5041cac7d3aeaa7350abadf2a7ada92e8da27dcJakob Stoklund Olesen .setImm(ARMCC::getOppositeCondition(CC)); 1521c5041cac7d3aeaa7350abadf2a7ada92e8da27dcJakob Stoklund Olesen return MI; 1522c5041cac7d3aeaa7350abadf2a7ada92e8da27dcJakob Stoklund Olesen } 1523c5041cac7d3aeaa7350abadf2a7ada92e8da27dcJakob Stoklund Olesen } 1524c5041cac7d3aeaa7350abadf2a7ada92e8da27dcJakob Stoklund Olesen return TargetInstrInfoImpl::commuteInstruction(MI, NewMI); 1525c5041cac7d3aeaa7350abadf2a7ada92e8da27dcJakob Stoklund Olesen} 15266495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 15273be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick/// Map pseudo instructions that imply an 'S' bit onto real opcodes. Whether the 15283be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick/// instruction is encoded with an 'S' bit is determined by the optional CPSR 15293be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick/// def operand. 15303be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick/// 15313be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick/// This will go away once we can teach tblgen how to set the optional CPSR def 15323be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick/// operand itself. 15333be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trickstruct AddSubFlagsOpcodePair { 15343be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick unsigned PseudoOpc; 15353be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick unsigned MachineOpc; 15363be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick}; 15373be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick 15383be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trickstatic AddSubFlagsOpcodePair AddSubFlagsOpcodeMap[] = { 15393be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick {ARM::ADDSri, ARM::ADDri}, 15403be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick {ARM::ADDSrr, ARM::ADDrr}, 15413be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick {ARM::ADDSrsi, ARM::ADDrsi}, 15423be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick {ARM::ADDSrsr, ARM::ADDrsr}, 15433be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick 15443be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick {ARM::SUBSri, ARM::SUBri}, 15453be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick {ARM::SUBSrr, ARM::SUBrr}, 15463be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick {ARM::SUBSrsi, ARM::SUBrsi}, 15473be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick {ARM::SUBSrsr, ARM::SUBrsr}, 15483be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick 15493be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick {ARM::RSBSri, ARM::RSBri}, 15503be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick {ARM::RSBSrsi, ARM::RSBrsi}, 15513be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick {ARM::RSBSrsr, ARM::RSBrsr}, 15523be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick 15533be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick {ARM::t2ADDSri, ARM::t2ADDri}, 15543be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick {ARM::t2ADDSrr, ARM::t2ADDrr}, 15553be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick {ARM::t2ADDSrs, ARM::t2ADDrs}, 15563be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick 15573be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick {ARM::t2SUBSri, ARM::t2SUBri}, 15583be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick {ARM::t2SUBSrr, ARM::t2SUBrr}, 15593be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick {ARM::t2SUBSrs, ARM::t2SUBrs}, 15603be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick 15613be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick {ARM::t2RSBSri, ARM::t2RSBri}, 15623be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick {ARM::t2RSBSrs, ARM::t2RSBrs}, 15633be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick}; 15643be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick 15653be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trickunsigned llvm::convertAddSubFlagsOpcode(unsigned OldOpc) { 15663be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick static const int NPairs = 15673be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick sizeof(AddSubFlagsOpcodeMap) / sizeof(AddSubFlagsOpcodePair); 15683be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick for (AddSubFlagsOpcodePair *OpcPair = &AddSubFlagsOpcodeMap[0], 15693be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick *End = &AddSubFlagsOpcodeMap[NPairs]; OpcPair != End; ++OpcPair) { 15703be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick if (OldOpc == OpcPair->PseudoOpc) { 15713be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick return OpcPair->MachineOpc; 15723be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick } 15733be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick } 15743be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick return 0; 15753be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick} 15763be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick 15776495f63945e8dbde81f03a1dc2ab421993b9a495Evan Chengvoid llvm::emitARMRegPlusImmediate(MachineBasicBlock &MBB, 15786495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MachineBasicBlock::iterator &MBBI, DebugLoc dl, 15796495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned DestReg, unsigned BaseReg, int NumBytes, 15806495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ARMCC::CondCodes Pred, unsigned PredReg, 158157caad7a33ff145b71545f10dcfbbf2fd0f595d3Anton Korobeynikov const ARMBaseInstrInfo &TII, unsigned MIFlags) { 15826495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng bool isSub = NumBytes < 0; 15836495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (isSub) NumBytes = -NumBytes; 15846495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 15856495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng while (NumBytes) { 15866495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned RotAmt = ARM_AM::getSOImmValRotate(NumBytes); 15876495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned ThisVal = NumBytes & ARM_AM::rotr32(0xFF, RotAmt); 15886495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng assert(ThisVal && "Didn't extract field correctly"); 15896495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 15906495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // We will handle these bits from offset, clear them. 15916495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng NumBytes &= ~ThisVal; 15926495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 15936495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng assert(ARM_AM::getSOImmVal(ThisVal) != -1 && "Bit extraction didn't work?"); 15946495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 15956495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Build the new ADD / SUB. 15966495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned Opc = isSub ? ARM::SUBri : ARM::ADDri; 15976495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg) 15986495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng .addReg(BaseReg, RegState::Kill).addImm(ThisVal) 159957caad7a33ff145b71545f10dcfbbf2fd0f595d3Anton Korobeynikov .addImm((unsigned)Pred).addReg(PredReg).addReg(0) 160057caad7a33ff145b71545f10dcfbbf2fd0f595d3Anton Korobeynikov .setMIFlags(MIFlags); 16016495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng BaseReg = DestReg; 16026495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 16036495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng} 16046495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 1605cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Chengbool llvm::rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx, 1606cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng unsigned FrameReg, int &Offset, 1607cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng const ARMBaseInstrInfo &TII) { 16086495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned Opcode = MI.getOpcode(); 1609e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng const MCInstrDesc &Desc = MI.getDesc(); 16106495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask); 16116495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng bool isSub = false; 1612764ab52dd80310a205c9888bf166d09dab858f90Jim Grosbach 16136495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Memory operands in inline assembly always use AddrMode2. 16146495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (Opcode == ARM::INLINEASM) 16156495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng AddrMode = ARMII::AddrMode2; 1616764ab52dd80310a205c9888bf166d09dab858f90Jim Grosbach 16176495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (Opcode == ARM::ADDri) { 16186495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng Offset += MI.getOperand(FrameRegIdx+1).getImm(); 16196495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (Offset == 0) { 16206495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Turn it into a move. 16216495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MI.setDesc(TII.get(ARM::MOVr)); 16226495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false); 16236495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MI.RemoveOperand(FrameRegIdx+1); 1624cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng Offset = 0; 1625cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng return true; 16266495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } else if (Offset < 0) { 16276495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng Offset = -Offset; 16286495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng isSub = true; 16296495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MI.setDesc(TII.get(ARM::SUBri)); 16306495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 16316495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 16326495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Common case: small offset, fits into instruction. 16336495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (ARM_AM::getSOImmVal(Offset) != -1) { 16346495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Replace the FrameIndex with sp / fp 16356495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false); 16366495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset); 1637cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng Offset = 0; 1638cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng return true; 16396495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 16406495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 16416495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Otherwise, pull as much of the immedidate into this ADDri/SUBri 16426495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // as possible. 16436495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned RotAmt = ARM_AM::getSOImmValRotate(Offset); 16446495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xFF, RotAmt); 16456495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 16466495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // We will handle these bits from offset, clear them. 16476495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng Offset &= ~ThisImmVal; 16486495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 16496495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Get the properly encoded SOImmVal field. 16506495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng assert(ARM_AM::getSOImmVal(ThisImmVal) != -1 && 16516495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng "Bit extraction didn't work?"); 16526495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MI.getOperand(FrameRegIdx+1).ChangeToImmediate(ThisImmVal); 16536495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } else { 16546495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned ImmIdx = 0; 16556495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng int InstrOffs = 0; 16566495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned NumBits = 0; 16576495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned Scale = 1; 16586495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng switch (AddrMode) { 16593e5561247202bae994dd259a2d8dc4eff8f799f3Jim Grosbach case ARMII::AddrMode_i12: { 16603e5561247202bae994dd259a2d8dc4eff8f799f3Jim Grosbach ImmIdx = FrameRegIdx + 1; 16613e5561247202bae994dd259a2d8dc4eff8f799f3Jim Grosbach InstrOffs = MI.getOperand(ImmIdx).getImm(); 16623e5561247202bae994dd259a2d8dc4eff8f799f3Jim Grosbach NumBits = 12; 16633e5561247202bae994dd259a2d8dc4eff8f799f3Jim Grosbach break; 16643e5561247202bae994dd259a2d8dc4eff8f799f3Jim Grosbach } 16656495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng case ARMII::AddrMode2: { 16666495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ImmIdx = FrameRegIdx+2; 16676495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng InstrOffs = ARM_AM::getAM2Offset(MI.getOperand(ImmIdx).getImm()); 16686495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (ARM_AM::getAM2Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub) 16696495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng InstrOffs *= -1; 16706495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng NumBits = 12; 16716495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng break; 16726495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 16736495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng case ARMII::AddrMode3: { 16746495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ImmIdx = FrameRegIdx+2; 16756495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng InstrOffs = ARM_AM::getAM3Offset(MI.getOperand(ImmIdx).getImm()); 16766495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (ARM_AM::getAM3Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub) 16776495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng InstrOffs *= -1; 16786495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng NumBits = 8; 16796495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng break; 16806495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 1681baf31088f1472f48ea5ae81f0b93636cc44ca444Anton Korobeynikov case ARMII::AddrMode4: 1682a44321776ecd96fa0344335d3027758be3386e45Jim Grosbach case ARMII::AddrMode6: 1683cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng // Can't fold any offset even if it's zero. 1684cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng return false; 16856495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng case ARMII::AddrMode5: { 16866495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ImmIdx = FrameRegIdx+1; 16876495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng InstrOffs = ARM_AM::getAM5Offset(MI.getOperand(ImmIdx).getImm()); 16886495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (ARM_AM::getAM5Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub) 16896495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng InstrOffs *= -1; 16906495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng NumBits = 8; 16916495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng Scale = 4; 16926495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng break; 16936495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 16946495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng default: 16956495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng llvm_unreachable("Unsupported addressing mode!"); 16966495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 16976495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 16986495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng Offset += InstrOffs * Scale; 16996495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!"); 17006495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (Offset < 0) { 17016495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng Offset = -Offset; 17026495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng isSub = true; 17036495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 17046495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 17056495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Attempt to fold address comp. if opcode has offset bits 17066495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (NumBits > 0) { 17076495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Common case: small offset, fits into instruction. 17086495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MachineOperand &ImmOp = MI.getOperand(ImmIdx); 17096495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng int ImmedOffset = Offset / Scale; 17106495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned Mask = (1 << NumBits) - 1; 17116495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if ((unsigned)Offset <= Mask * Scale) { 17126495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Replace the FrameIndex with sp 17136495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false); 171477aee8e22c36257716c2df2f275724765704f20cJim Grosbach // FIXME: When addrmode2 goes away, this will simplify (like the 171577aee8e22c36257716c2df2f275724765704f20cJim Grosbach // T2 version), as the LDR.i12 versions don't need the encoding 171677aee8e22c36257716c2df2f275724765704f20cJim Grosbach // tricks for the offset value. 171777aee8e22c36257716c2df2f275724765704f20cJim Grosbach if (isSub) { 171877aee8e22c36257716c2df2f275724765704f20cJim Grosbach if (AddrMode == ARMII::AddrMode_i12) 171977aee8e22c36257716c2df2f275724765704f20cJim Grosbach ImmedOffset = -ImmedOffset; 172077aee8e22c36257716c2df2f275724765704f20cJim Grosbach else 172177aee8e22c36257716c2df2f275724765704f20cJim Grosbach ImmedOffset |= 1 << NumBits; 172277aee8e22c36257716c2df2f275724765704f20cJim Grosbach } 17236495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ImmOp.ChangeToImmediate(ImmedOffset); 1724cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng Offset = 0; 1725cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng return true; 17266495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 1727764ab52dd80310a205c9888bf166d09dab858f90Jim Grosbach 17286495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Otherwise, it didn't fit. Pull in what we can to simplify the immed. 17296495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ImmedOffset = ImmedOffset & Mask; 1730063efbf569e46776093ddf50099c98fdbb362167Jim Grosbach if (isSub) { 1731063efbf569e46776093ddf50099c98fdbb362167Jim Grosbach if (AddrMode == ARMII::AddrMode_i12) 1732063efbf569e46776093ddf50099c98fdbb362167Jim Grosbach ImmedOffset = -ImmedOffset; 1733063efbf569e46776093ddf50099c98fdbb362167Jim Grosbach else 1734063efbf569e46776093ddf50099c98fdbb362167Jim Grosbach ImmedOffset |= 1 << NumBits; 1735063efbf569e46776093ddf50099c98fdbb362167Jim Grosbach } 17366495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ImmOp.ChangeToImmediate(ImmedOffset); 17376495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng Offset &= ~(Mask*Scale); 17386495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 17396495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 17406495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 1741cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng Offset = (isSub) ? -Offset : Offset; 1742cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng return Offset == 0; 17436495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng} 1744e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling 1745e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendlingbool ARMBaseInstrInfo:: 1746a99c3e9acd95f5fbfb611e3f807240cd74001142Eric ChristopherAnalyzeCompare(const MachineInstr *MI, unsigned &SrcReg, int &CmpMask, 1747a99c3e9acd95f5fbfb611e3f807240cd74001142Eric Christopher int &CmpValue) const { 1748e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling switch (MI->getOpcode()) { 1749e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling default: break; 175038ae997e63e3e1bb2c8679e01ea74cf8fd0be893Bill Wendling case ARM::CMPri: 1751e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling case ARM::t2CMPri: 1752e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling SrcReg = MI->getOperand(0).getReg(); 175304ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif CmpMask = ~0; 1754e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling CmpValue = MI->getOperand(1).getImm(); 1755e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling return true; 1756247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren case ARM::CMPrr: 1757247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren case ARM::t2CMPrr: 1758247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren SrcReg = MI->getOperand(0).getReg(); 1759247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren CmpMask = ~0; 1760247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren CmpValue = 0; 1761247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren return true; 176204ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif case ARM::TSTri: 176304ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif case ARM::t2TSTri: 176404ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif SrcReg = MI->getOperand(0).getReg(); 176504ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif CmpMask = MI->getOperand(1).getImm(); 176604ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif CmpValue = 0; 176704ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif return true; 176804ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif } 176904ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif 177004ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif return false; 177104ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif} 177204ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif 177305642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif/// isSuitableForMask - Identify a suitable 'and' instruction that 177405642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif/// operates on the given source register and applies the same mask 177505642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif/// as a 'tst' instruction. Provide a limited look-through for copies. 177605642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif/// When successful, MI will hold the found instruction. 177705642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greifstatic bool isSuitableForMask(MachineInstr *&MI, unsigned SrcReg, 17788ff9bb189ce188452e6cae6ed65cb2745814126cGabor Greif int CmpMask, bool CommonUse) { 177905642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif switch (MI->getOpcode()) { 178004ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif case ARM::ANDri: 178104ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif case ARM::t2ANDri: 178205642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif if (CmpMask != MI->getOperand(2).getImm()) 17838ff9bb189ce188452e6cae6ed65cb2745814126cGabor Greif return false; 178405642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif if (SrcReg == MI->getOperand(CommonUse ? 1 : 0).getReg()) 178504ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif return true; 178604ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif break; 178705642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif case ARM::COPY: { 178805642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif // Walk down one instruction which is potentially an 'and'. 178905642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif const MachineInstr &Copy = *MI; 1790f000a7a212590bfd45e23c05bff5e1b683d25dd6Michael J. Spencer MachineBasicBlock::iterator AND( 1791f000a7a212590bfd45e23c05bff5e1b683d25dd6Michael J. Spencer llvm::next(MachineBasicBlock::iterator(MI))); 179205642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif if (AND == MI->getParent()->end()) return false; 179305642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif MI = AND; 179405642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif return isSuitableForMask(MI, Copy.getOperand(0).getReg(), 179505642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif CmpMask, true); 179605642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif } 1797e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling } 1798e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling 1799e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling return false; 1800e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling} 1801e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling 1802a65568676d0d9d53dd4aae8f1c58271bb4cfff10Bill Wendling/// OptimizeCompareInstr - Convert the instruction supplying the argument to the 1803247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren/// comparison into one that sets the zero bit in the flags register. Convert 1804247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren/// the SUBrr(r1,r2)|Subri(r1,CmpValue) instruction into one that sets the flags 1805247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren/// register and remove the CMPrr(r1,r2)|CMPrr(r2,r1)|CMPri(r1,CmpValue) 1806247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren/// instruction. 1807e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendlingbool ARMBaseInstrInfo:: 180804ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor GreifOptimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, int CmpMask, 1809eb96a2f6c03c0ec97c56a3493ac38024afacc774Evan Cheng int CmpValue, const MachineRegisterInfo *MRI) const { 181092ad57f066e9f256e4e3d72febf152e68caa80c7Bill Wendling 1811b41ee96d76ccf1eec2fd898def4cfd7c16868708Bill Wendling MachineRegisterInfo::def_iterator DI = MRI->def_begin(SrcReg); 1812b41ee96d76ccf1eec2fd898def4cfd7c16868708Bill Wendling if (llvm::next(DI) != MRI->def_end()) 181392ad57f066e9f256e4e3d72febf152e68caa80c7Bill Wendling // Only support one definition. 181492ad57f066e9f256e4e3d72febf152e68caa80c7Bill Wendling return false; 181592ad57f066e9f256e4e3d72febf152e68caa80c7Bill Wendling 181692ad57f066e9f256e4e3d72febf152e68caa80c7Bill Wendling MachineInstr *MI = &*DI; 181792ad57f066e9f256e4e3d72febf152e68caa80c7Bill Wendling 181804ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif // Masked compares sometimes use the same register as the corresponding 'and'. 181904ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif if (CmpMask != ~0) { 182005642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif if (!isSuitableForMask(MI, SrcReg, CmpMask, false)) { 182104ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif MI = 0; 1822b41ee96d76ccf1eec2fd898def4cfd7c16868708Bill Wendling for (MachineRegisterInfo::use_iterator UI = MRI->use_begin(SrcReg), 1823b41ee96d76ccf1eec2fd898def4cfd7c16868708Bill Wendling UE = MRI->use_end(); UI != UE; ++UI) { 182404ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif if (UI->getParent() != CmpInstr->getParent()) continue; 182505642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif MachineInstr *PotentialAND = &*UI; 18268ff9bb189ce188452e6cae6ed65cb2745814126cGabor Greif if (!isSuitableForMask(PotentialAND, SrcReg, CmpMask, true)) 182704ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif continue; 182805642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif MI = PotentialAND; 182904ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif break; 183004ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif } 183104ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif if (!MI) return false; 183204ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif } 183304ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif } 183404ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif 1835247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren // Get ready to iterate backward from CmpInstr. 1836247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren MachineBasicBlock::iterator I = CmpInstr, E = MI, 1837247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren B = CmpInstr->getParent()->begin(); 18380aa38b9381a5be42abd4f5ca5baa8c2930d148d3Bill Wendling 18390aa38b9381a5be42abd4f5ca5baa8c2930d148d3Bill Wendling // Early exit if CmpInstr is at the beginning of the BB. 18400aa38b9381a5be42abd4f5ca5baa8c2930d148d3Bill Wendling if (I == B) return false; 18410aa38b9381a5be42abd4f5ca5baa8c2930d148d3Bill Wendling 1842247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren // There are two possible candidates which can be changed to set CPSR: 1843247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren // One is MI, the other is a SUB instruction. 1844247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren // For CMPrr(r1,r2), we are looking for SUB(r1,r2) or SUB(r2,r1). 1845247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren // For CMPri(r1, CmpValue), we are looking for SUBri(r1, CmpValue). 1846247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren MachineInstr *Sub = NULL; 1847247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren unsigned SrcReg2 = 0; 1848247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren if (CmpInstr->getOpcode() == ARM::CMPrr || 1849247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren CmpInstr->getOpcode() == ARM::t2CMPrr) { 1850247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren SrcReg2 = CmpInstr->getOperand(1).getReg(); 1851247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren // MI is not a candidate for CMPrr. 1852247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren MI = NULL; 1853247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren } else if (MI->getParent() != CmpInstr->getParent() || CmpValue != 0) { 1854247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren // Conservatively refuse to convert an instruction which isn't in the same 1855247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren // BB as the comparison. 1856247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren // For CMPri, we need to check Sub, thus we can't return here. 1857247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren if(CmpInstr->getOpcode() == ARM::CMPri || 1858247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren CmpInstr->getOpcode() == ARM::t2CMPri) 1859247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren MI = NULL; 1860247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren else 1861247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren return false; 1862247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren } 1863247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren 1864247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren // Check that CPSR isn't set between the comparison instruction and the one we 1865247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren // want to change. At the same time, search for Sub. 1866e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling --I; 1867e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling for (; I != E; --I) { 1868e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling const MachineInstr &Instr = *I; 1869e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling 1870e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling for (unsigned IO = 0, EO = Instr.getNumOperands(); IO != EO; ++IO) { 1871e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling const MachineOperand &MO = Instr.getOperand(IO); 18722420b558de5d291d8503c1339004e5b5bf99a48aJakob Stoklund Olesen if (MO.isRegMask() && MO.clobbersPhysReg(ARM::CPSR)) 18732420b558de5d291d8503c1339004e5b5bf99a48aJakob Stoklund Olesen return false; 187440a5eb18b031fa1a5e9697e21e251e613d441cc5Bill Wendling if (!MO.isReg()) continue; 1875e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling 187640a5eb18b031fa1a5e9697e21e251e613d441cc5Bill Wendling // This instruction modifies or uses CPSR after the one we want to 187740a5eb18b031fa1a5e9697e21e251e613d441cc5Bill Wendling // change. We can't do this transformation. 1878e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling if (MO.getReg() == ARM::CPSR) 1879e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling return false; 1880e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling } 1881691e64a54ce899409abe7c131d15ed75e3c1fef5Evan Cheng 1882247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren // Check whether the current instruction is SUB(r1, r2) or SUB(r2, r1). 1883247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren if (SrcReg2 != 0 && Instr.getOpcode() == ARM::SUBrr && 1884247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren ((Instr.getOperand(1).getReg() == SrcReg && 1885247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren Instr.getOperand(2).getReg() == SrcReg2) || 1886247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren (Instr.getOperand(1).getReg() == SrcReg2 && 1887247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren Instr.getOperand(2).getReg() == SrcReg))) { 1888247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren Sub = &*I; 1889247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren break; 1890247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren } 1891247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren 1892247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren // Check whether the current instruction is SUBri(r1, CmpValue). 1893247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren if ((CmpInstr->getOpcode() == ARM::CMPri || 1894247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren CmpInstr->getOpcode() == ARM::t2CMPri) && 1895247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren Instr.getOpcode() == ARM::SUBri && CmpValue != 0 && 1896247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren Instr.getOperand(1).getReg() == SrcReg && 1897247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren Instr.getOperand(2).getImm() == CmpValue) { 1898247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren Sub = &*I; 1899247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren break; 1900247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren } 1901247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren 1902691e64a54ce899409abe7c131d15ed75e3c1fef5Evan Cheng if (I == B) 1903691e64a54ce899409abe7c131d15ed75e3c1fef5Evan Cheng // The 'and' is below the comparison instruction. 1904691e64a54ce899409abe7c131d15ed75e3c1fef5Evan Cheng return false; 1905e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling } 1906e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling 1907247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren // Return false if no candidates exist. 1908247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren if (!MI && !Sub) 1909247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren return false; 1910247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren 1911247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren // The single candidate is called MI. 1912247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren if (!MI) MI = Sub; 1913247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren 1914e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling switch (MI->getOpcode()) { 1915e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling default: break; 1916ca3f6a3925e9a6e91022aa211bdc1b6e3f2ff41fCameron Zwarich case ARM::RSBrr: 1917df298c9ea64eb335f63fc075d8ef6306682ffe75Owen Anderson case ARM::RSBri: 1918ca3f6a3925e9a6e91022aa211bdc1b6e3f2ff41fCameron Zwarich case ARM::RSCrr: 1919df298c9ea64eb335f63fc075d8ef6306682ffe75Owen Anderson case ARM::RSCri: 1920ca3f6a3925e9a6e91022aa211bdc1b6e3f2ff41fCameron Zwarich case ARM::ADDrr: 192138ae997e63e3e1bb2c8679e01ea74cf8fd0be893Bill Wendling case ARM::ADDri: 1922ca3f6a3925e9a6e91022aa211bdc1b6e3f2ff41fCameron Zwarich case ARM::ADCrr: 1923df298c9ea64eb335f63fc075d8ef6306682ffe75Owen Anderson case ARM::ADCri: 1924ca3f6a3925e9a6e91022aa211bdc1b6e3f2ff41fCameron Zwarich case ARM::SUBrr: 192538ae997e63e3e1bb2c8679e01ea74cf8fd0be893Bill Wendling case ARM::SUBri: 1926ca3f6a3925e9a6e91022aa211bdc1b6e3f2ff41fCameron Zwarich case ARM::SBCrr: 1927df298c9ea64eb335f63fc075d8ef6306682ffe75Owen Anderson case ARM::SBCri: 1928df298c9ea64eb335f63fc075d8ef6306682ffe75Owen Anderson case ARM::t2RSBri: 1929ca3f6a3925e9a6e91022aa211bdc1b6e3f2ff41fCameron Zwarich case ARM::t2ADDrr: 193038ae997e63e3e1bb2c8679e01ea74cf8fd0be893Bill Wendling case ARM::t2ADDri: 1931ca3f6a3925e9a6e91022aa211bdc1b6e3f2ff41fCameron Zwarich case ARM::t2ADCrr: 1932df298c9ea64eb335f63fc075d8ef6306682ffe75Owen Anderson case ARM::t2ADCri: 1933ca3f6a3925e9a6e91022aa211bdc1b6e3f2ff41fCameron Zwarich case ARM::t2SUBrr: 1934df298c9ea64eb335f63fc075d8ef6306682ffe75Owen Anderson case ARM::t2SUBri: 1935ca3f6a3925e9a6e91022aa211bdc1b6e3f2ff41fCameron Zwarich case ARM::t2SBCrr: 1936b485de5d8c3fe0c62c0b07f63f64bd10f6803c17Cameron Zwarich case ARM::t2SBCri: 1937b485de5d8c3fe0c62c0b07f63f64bd10f6803c17Cameron Zwarich case ARM::ANDrr: 1938b485de5d8c3fe0c62c0b07f63f64bd10f6803c17Cameron Zwarich case ARM::ANDri: 1939b485de5d8c3fe0c62c0b07f63f64bd10f6803c17Cameron Zwarich case ARM::t2ANDrr: 19400cb11ac32fc09c5db42fb801db242ac9fb51f6b1Cameron Zwarich case ARM::t2ANDri: 19410cb11ac32fc09c5db42fb801db242ac9fb51f6b1Cameron Zwarich case ARM::ORRrr: 19420cb11ac32fc09c5db42fb801db242ac9fb51f6b1Cameron Zwarich case ARM::ORRri: 19430cb11ac32fc09c5db42fb801db242ac9fb51f6b1Cameron Zwarich case ARM::t2ORRrr: 19440cb11ac32fc09c5db42fb801db242ac9fb51f6b1Cameron Zwarich case ARM::t2ORRri: 19450cb11ac32fc09c5db42fb801db242ac9fb51f6b1Cameron Zwarich case ARM::EORrr: 19460cb11ac32fc09c5db42fb801db242ac9fb51f6b1Cameron Zwarich case ARM::EORri: 19470cb11ac32fc09c5db42fb801db242ac9fb51f6b1Cameron Zwarich case ARM::t2EORrr: 19480cb11ac32fc09c5db42fb801db242ac9fb51f6b1Cameron Zwarich case ARM::t2EORri: { 1949247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren // Scan forward for the use of CPSR 1950247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren // When checking against MI: if it's a conditional code requires 19512c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng // checking of V bit, then this is not safe to do. If we can't find the 19522c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng // CPSR use (i.e. used in another block), then it's not safe to perform 19532c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng // the optimization. 1954247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren // When checking against Sub, we handle the condition codes GE, LT, GT, LE. 1955247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren SmallVector<MachineOperand*, 4> OperandsToUpdate; 19562c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng bool isSafe = false; 19572c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng I = CmpInstr; 1958247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren E = CmpInstr->getParent()->end(); 19592c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng while (!isSafe && ++I != E) { 19602c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng const MachineInstr &Instr = *I; 19612c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng for (unsigned IO = 0, EO = Instr.getNumOperands(); 19622c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng !isSafe && IO != EO; ++IO) { 19632c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng const MachineOperand &MO = Instr.getOperand(IO); 19642420b558de5d291d8503c1339004e5b5bf99a48aJakob Stoklund Olesen if (MO.isRegMask() && MO.clobbersPhysReg(ARM::CPSR)) { 19652420b558de5d291d8503c1339004e5b5bf99a48aJakob Stoklund Olesen isSafe = true; 19662420b558de5d291d8503c1339004e5b5bf99a48aJakob Stoklund Olesen break; 19672420b558de5d291d8503c1339004e5b5bf99a48aJakob Stoklund Olesen } 19682c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng if (!MO.isReg() || MO.getReg() != ARM::CPSR) 19692c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng continue; 19702c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng if (MO.isDef()) { 19712c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng isSafe = true; 19722c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng break; 19732c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng } 19742c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng // Condition code is after the operand before CPSR. 19752c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng ARMCC::CondCodes CC = (ARMCC::CondCodes)Instr.getOperand(IO-1).getImm(); 1976247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren if (Sub) 1977247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren switch (CC) { 1978247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren default: 1979247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren return false; 1980247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren case ARMCC::GE: 1981247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren case ARMCC::LT: 1982247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren case ARMCC::GT: 1983247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren case ARMCC::LE: 1984247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren // If we have SUB(r1, r2) and CMP(r2, r1), the condition code based 1985247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren // on CMP needs to be updated to be based on SUB. 1986247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren // Push the condition code operands to OperandsToUpdate. 1987247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren // If it is safe to remove CmpInstr, the condition code of these 1988247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren // operands will be modified. 1989247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren if (SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 && 1990247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren Sub->getOperand(2).getReg() == SrcReg) 1991247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren OperandsToUpdate.push_back(&((*I).getOperand(IO-1))); 1992247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren break; 1993247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren } 1994247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren else 1995247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren switch (CC) { 1996247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren default: 1997247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren isSafe = true; 1998247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren break; 1999247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren case ARMCC::VS: 2000247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren case ARMCC::VC: 2001247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren case ARMCC::GE: 2002247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren case ARMCC::LT: 2003247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren case ARMCC::GT: 2004247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren case ARMCC::LE: 2005247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren return false; 2006247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren } 20072c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng } 20082c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng } 20092c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng 2010247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren // If the candidate is Sub, we may exit the loop at end of the basic block. 2011247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren // In that case, it is still safe to remove CmpInstr. 2012247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren if (!isSafe && !Sub) 20132c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng return false; 20142c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng 20153642e64c114e636548888c72c21ae023ee0121a7Evan Cheng // Toggle the optional operand to CPSR. 20163642e64c114e636548888c72c21ae023ee0121a7Evan Cheng MI->getOperand(5).setReg(ARM::CPSR); 20173642e64c114e636548888c72c21ae023ee0121a7Evan Cheng MI->getOperand(5).setIsDef(true); 2018e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling CmpInstr->eraseFromParent(); 2019247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren 2020247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren // Modify the condition code of operands in OperandsToUpdate. 2021247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren // Since we have SUB(r1, r2) and CMP(r2, r1), the condition code needs to 2022247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren // be changed from r2 > r1 to r1 < r2, from r2 < r1 to r1 > r2, etc. 2023247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren for (unsigned i = 0; i < OperandsToUpdate.size(); i++) { 2024247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren ARMCC::CondCodes CC = (ARMCC::CondCodes)OperandsToUpdate[i]->getImm(); 2025247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren ARMCC::CondCodes NewCC; 2026247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren switch(CC) { 2027247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren default: break; 2028247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren case ARMCC::GE: NewCC = ARMCC::LE; break; 2029247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren case ARMCC::LT: NewCC = ARMCC::GT; break; 2030247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren case ARMCC::GT: NewCC = ARMCC::LT; break; 2031247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren case ARMCC::LE: NewCC = ARMCC::GT; break; 2032247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren } 2033247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren OperandsToUpdate[i]->setImm(NewCC); 2034247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren } 2035e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling return true; 2036e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling } 2037b485de5d8c3fe0c62c0b07f63f64bd10f6803c17Cameron Zwarich } 2038e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling 2039e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling return false; 2040e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling} 20415f54ce347368105260be2cec497b6a4199dc5789Evan Cheng 2042c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Chengbool ARMBaseInstrInfo::FoldImmediate(MachineInstr *UseMI, 2043c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng MachineInstr *DefMI, unsigned Reg, 2044c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng MachineRegisterInfo *MRI) const { 2045c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng // Fold large immediates into add, sub, or, xor. 2046c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng unsigned DefOpc = DefMI->getOpcode(); 2047c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng if (DefOpc != ARM::t2MOVi32imm && DefOpc != ARM::MOVi32imm) 2048c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng return false; 2049c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng if (!DefMI->getOperand(1).isImm()) 2050c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng // Could be t2MOVi32imm <ga:xx> 2051c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng return false; 2052c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng 2053c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng if (!MRI->hasOneNonDBGUse(Reg)) 2054c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng return false; 2055c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng 2056e279f5953e9c3d934248cd4d2f24b6179ad9d2e6Evan Cheng const MCInstrDesc &DefMCID = DefMI->getDesc(); 2057e279f5953e9c3d934248cd4d2f24b6179ad9d2e6Evan Cheng if (DefMCID.hasOptionalDef()) { 2058e279f5953e9c3d934248cd4d2f24b6179ad9d2e6Evan Cheng unsigned NumOps = DefMCID.getNumOperands(); 2059e279f5953e9c3d934248cd4d2f24b6179ad9d2e6Evan Cheng const MachineOperand &MO = DefMI->getOperand(NumOps-1); 2060e279f5953e9c3d934248cd4d2f24b6179ad9d2e6Evan Cheng if (MO.getReg() == ARM::CPSR && !MO.isDead()) 2061e279f5953e9c3d934248cd4d2f24b6179ad9d2e6Evan Cheng // If DefMI defines CPSR and it is not dead, it's obviously not safe 2062e279f5953e9c3d934248cd4d2f24b6179ad9d2e6Evan Cheng // to delete DefMI. 2063e279f5953e9c3d934248cd4d2f24b6179ad9d2e6Evan Cheng return false; 2064e279f5953e9c3d934248cd4d2f24b6179ad9d2e6Evan Cheng } 2065e279f5953e9c3d934248cd4d2f24b6179ad9d2e6Evan Cheng 2066e279f5953e9c3d934248cd4d2f24b6179ad9d2e6Evan Cheng const MCInstrDesc &UseMCID = UseMI->getDesc(); 2067e279f5953e9c3d934248cd4d2f24b6179ad9d2e6Evan Cheng if (UseMCID.hasOptionalDef()) { 2068e279f5953e9c3d934248cd4d2f24b6179ad9d2e6Evan Cheng unsigned NumOps = UseMCID.getNumOperands(); 2069e279f5953e9c3d934248cd4d2f24b6179ad9d2e6Evan Cheng if (UseMI->getOperand(NumOps-1).getReg() == ARM::CPSR) 2070e279f5953e9c3d934248cd4d2f24b6179ad9d2e6Evan Cheng // If the instruction sets the flag, do not attempt this optimization 2071e279f5953e9c3d934248cd4d2f24b6179ad9d2e6Evan Cheng // since it may change the semantics of the code. 2072e279f5953e9c3d934248cd4d2f24b6179ad9d2e6Evan Cheng return false; 2073e279f5953e9c3d934248cd4d2f24b6179ad9d2e6Evan Cheng } 2074e279f5953e9c3d934248cd4d2f24b6179ad9d2e6Evan Cheng 2075c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng unsigned UseOpc = UseMI->getOpcode(); 20765c71c7a13715ed6f5bfdd5497172ddec316b68b0Evan Cheng unsigned NewUseOpc = 0; 2077c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng uint32_t ImmVal = (uint32_t)DefMI->getOperand(1).getImm(); 20785c71c7a13715ed6f5bfdd5497172ddec316b68b0Evan Cheng uint32_t SOImmValV1 = 0, SOImmValV2 = 0; 2079c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng bool Commute = false; 2080c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng switch (UseOpc) { 2081c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng default: return false; 2082c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::SUBrr: 2083c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::ADDrr: 2084c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::ORRrr: 2085c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::EORrr: 2086c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::t2SUBrr: 2087c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::t2ADDrr: 2088c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::t2ORRrr: 2089c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::t2EORrr: { 2090c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng Commute = UseMI->getOperand(2).getReg() != Reg; 2091c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng switch (UseOpc) { 2092c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng default: break; 2093c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::SUBrr: { 2094c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng if (Commute) 2095c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng return false; 2096c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng ImmVal = -ImmVal; 2097c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng NewUseOpc = ARM::SUBri; 2098c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng // Fallthrough 2099c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng } 2100c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::ADDrr: 2101c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::ORRrr: 2102c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::EORrr: { 2103c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng if (!ARM_AM::isSOImmTwoPartVal(ImmVal)) 2104c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng return false; 2105c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng SOImmValV1 = (uint32_t)ARM_AM::getSOImmTwoPartFirst(ImmVal); 2106c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng SOImmValV2 = (uint32_t)ARM_AM::getSOImmTwoPartSecond(ImmVal); 2107c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng switch (UseOpc) { 2108c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng default: break; 2109c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::ADDrr: NewUseOpc = ARM::ADDri; break; 2110c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::ORRrr: NewUseOpc = ARM::ORRri; break; 2111c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::EORrr: NewUseOpc = ARM::EORri; break; 2112c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng } 2113c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng break; 2114c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng } 2115c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::t2SUBrr: { 2116c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng if (Commute) 2117c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng return false; 2118c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng ImmVal = -ImmVal; 2119c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng NewUseOpc = ARM::t2SUBri; 2120c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng // Fallthrough 2121c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng } 2122c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::t2ADDrr: 2123c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::t2ORRrr: 2124c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::t2EORrr: { 2125c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng if (!ARM_AM::isT2SOImmTwoPartVal(ImmVal)) 2126c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng return false; 2127c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng SOImmValV1 = (uint32_t)ARM_AM::getT2SOImmTwoPartFirst(ImmVal); 2128c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng SOImmValV2 = (uint32_t)ARM_AM::getT2SOImmTwoPartSecond(ImmVal); 2129c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng switch (UseOpc) { 2130c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng default: break; 2131c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::t2ADDrr: NewUseOpc = ARM::t2ADDri; break; 2132c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::t2ORRrr: NewUseOpc = ARM::t2ORRri; break; 2133c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::t2EORrr: NewUseOpc = ARM::t2EORri; break; 2134c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng } 2135c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng break; 2136c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng } 2137c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng } 2138c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng } 2139c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng } 2140c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng 2141c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng unsigned OpIdx = Commute ? 2 : 1; 2142c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng unsigned Reg1 = UseMI->getOperand(OpIdx).getReg(); 2143c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng bool isKill = UseMI->getOperand(OpIdx).isKill(); 2144c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng unsigned NewReg = MRI->createVirtualRegister(MRI->getRegClass(Reg)); 2145c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng AddDefaultCC(AddDefaultPred(BuildMI(*UseMI->getParent(), 2146ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng UseMI, UseMI->getDebugLoc(), 2147c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng get(NewUseOpc), NewReg) 2148c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng .addReg(Reg1, getKillRegState(isKill)) 2149c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng .addImm(SOImmValV1))); 2150c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng UseMI->setDesc(get(NewUseOpc)); 2151c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng UseMI->getOperand(1).setReg(NewReg); 2152c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng UseMI->getOperand(1).setIsKill(); 2153c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng UseMI->getOperand(2).ChangeToImmediate(SOImmValV2); 2154c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng DefMI->eraseFromParent(); 2155c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng return true; 2156c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng} 2157c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng 21585f54ce347368105260be2cec497b6a4199dc5789Evan Chengunsigned 21598239daf7c83a65a189c352cce3191cdc3bbfe151Evan ChengARMBaseInstrInfo::getNumMicroOps(const InstrItineraryData *ItinData, 21608239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng const MachineInstr *MI) const { 21613ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng if (!ItinData || ItinData->isEmpty()) 21625f54ce347368105260be2cec497b6a4199dc5789Evan Cheng return 1; 21635f54ce347368105260be2cec497b6a4199dc5789Evan Cheng 2164e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng const MCInstrDesc &Desc = MI->getDesc(); 21655f54ce347368105260be2cec497b6a4199dc5789Evan Cheng unsigned Class = Desc.getSchedClass(); 2166064312de8641043b084603aa9a6b409bc794eed2Bob Wilson unsigned UOps = ItinData->Itineraries[Class].NumMicroOps; 21675f54ce347368105260be2cec497b6a4199dc5789Evan Cheng if (UOps) 21685f54ce347368105260be2cec497b6a4199dc5789Evan Cheng return UOps; 21695f54ce347368105260be2cec497b6a4199dc5789Evan Cheng 21705f54ce347368105260be2cec497b6a4199dc5789Evan Cheng unsigned Opc = MI->getOpcode(); 21715f54ce347368105260be2cec497b6a4199dc5789Evan Cheng switch (Opc) { 21725f54ce347368105260be2cec497b6a4199dc5789Evan Cheng default: 21735f54ce347368105260be2cec497b6a4199dc5789Evan Cheng llvm_unreachable("Unexpected multi-uops instruction!"); 217473fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMQIA: 217573fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMQIA: 21765f54ce347368105260be2cec497b6a4199dc5789Evan Cheng return 2; 21775f54ce347368105260be2cec497b6a4199dc5789Evan Cheng 21785f54ce347368105260be2cec497b6a4199dc5789Evan Cheng // The number of uOps for load / store multiple are determined by the number 21795f54ce347368105260be2cec497b6a4199dc5789Evan Cheng // registers. 21806e8f4c404825b79f9b9176483653f1aa927dfbdeAndrew Trick // 21813ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng // On Cortex-A8, each pair of register loads / stores can be scheduled on the 21823ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng // same cycle. The scheduling for the first load / store must be done 21833ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng // separately by assuming the the address is not 64-bit aligned. 218473fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling // 21853ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng // On Cortex-A9, the formula is simply (#reg / 2) + (#reg % 2). If the address 218673fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling // is not 64-bit aligned, then AGU would take an extra cycle. For VFP / NEON 218773fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling // load / store multiple, the formula is (#reg / 2) + (#reg % 2) + 1. 218873fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMDIA: 218973fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMDIA_UPD: 219073fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMDDB_UPD: 219173fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMSIA: 219273fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMSIA_UPD: 219373fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMSDB_UPD: 219473fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMDIA: 219573fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMDIA_UPD: 219673fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMDDB_UPD: 219773fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMSIA: 219873fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMSIA_UPD: 219973fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMSDB_UPD: { 22005f54ce347368105260be2cec497b6a4199dc5789Evan Cheng unsigned NumRegs = MI->getNumOperands() - Desc.getNumOperands(); 22015f54ce347368105260be2cec497b6a4199dc5789Evan Cheng return (NumRegs / 2) + (NumRegs % 2) + 1; 22025f54ce347368105260be2cec497b6a4199dc5789Evan Cheng } 220373fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling 220473fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMIA_RET: 220573fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMIA: 220673fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMDA: 220773fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMDB: 220873fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMIB: 220973fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMIA_UPD: 221073fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMDA_UPD: 221173fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMDB_UPD: 221273fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMIB_UPD: 221373fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::STMIA: 221473fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::STMDA: 221573fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::STMDB: 221673fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::STMIB: 221773fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::STMIA_UPD: 221873fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::STMDA_UPD: 221973fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::STMDB_UPD: 222073fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::STMIB_UPD: 222173fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::tLDMIA: 222273fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::tLDMIA_UPD: 222373fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::tSTMIA_UPD: 22245f54ce347368105260be2cec497b6a4199dc5789Evan Cheng case ARM::tPOP_RET: 22255f54ce347368105260be2cec497b6a4199dc5789Evan Cheng case ARM::tPOP: 22265f54ce347368105260be2cec497b6a4199dc5789Evan Cheng case ARM::tPUSH: 222773fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2LDMIA_RET: 222873fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2LDMIA: 222973fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2LDMDB: 223073fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2LDMIA_UPD: 223173fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2LDMDB_UPD: 223273fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2STMIA: 223373fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2STMDB: 223473fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2STMIA_UPD: 223573fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2STMDB_UPD: { 22363ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng unsigned NumRegs = MI->getNumOperands() - Desc.getNumOperands() + 1; 22373ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng if (Subtarget.isCortexA8()) { 22388239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng if (NumRegs < 4) 22398239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng return 2; 22408239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng // 4 registers would be issued: 2, 2. 22418239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng // 5 registers would be issued: 2, 2, 1. 22428239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng UOps = (NumRegs / 2); 22438239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng if (NumRegs % 2) 22448239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng ++UOps; 22458239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng return UOps; 22463ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng } else if (Subtarget.isCortexA9()) { 22473ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng UOps = (NumRegs / 2); 22483ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng // If there are odd number of registers or if it's not 64-bit aligned, 22493ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng // then it takes an extra AGU (Address Generation Unit) cycle. 22503ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng if ((NumRegs % 2) || 22513ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng !MI->hasOneMemOperand() || 22523ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng (*MI->memoperands_begin())->getAlignment() < 8) 22533ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng ++UOps; 22543ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng return UOps; 22553ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng } else { 22563ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng // Assume the worst. 22573ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng return NumRegs; 22582bbb76909126db5bed6bde84b16d94ab5de4d372Michael J. Spencer } 22595f54ce347368105260be2cec497b6a4199dc5789Evan Cheng } 22605f54ce347368105260be2cec497b6a4199dc5789Evan Cheng } 22615f54ce347368105260be2cec497b6a4199dc5789Evan Cheng} 2262a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng 2263a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Chengint 2264344d9db97062736cd66da6c07baa9108b6cfa419Evan ChengARMBaseInstrInfo::getVLDMDefCycle(const InstrItineraryData *ItinData, 2265e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng const MCInstrDesc &DefMCID, 2266344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng unsigned DefClass, 2267344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng unsigned DefIdx, unsigned DefAlign) const { 2268e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng int RegNo = (int)(DefIdx+1) - DefMCID.getNumOperands() + 1; 2269344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng if (RegNo <= 0) 2270344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // Def is the address writeback. 2271344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng return ItinData->getOperandCycle(DefClass, DefIdx); 2272344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng 2273344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng int DefCycle; 2274344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng if (Subtarget.isCortexA8()) { 2275344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // (regno / 2) + (regno % 2) + 1 2276344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng DefCycle = RegNo / 2 + 1; 2277344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng if (RegNo % 2) 2278344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng ++DefCycle; 2279344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng } else if (Subtarget.isCortexA9()) { 2280344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng DefCycle = RegNo; 2281344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng bool isSLoad = false; 228273fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling 2283e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng switch (DefMCID.getOpcode()) { 2284344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng default: break; 228573fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMSIA: 228673fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMSIA_UPD: 228773fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMSDB_UPD: 2288344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng isSLoad = true; 2289344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng break; 2290344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng } 229173fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling 2292344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // If there are odd number of 'S' registers or if it's not 64-bit aligned, 2293344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // then it takes an extra cycle. 2294344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng if ((isSLoad && (RegNo % 2)) || DefAlign < 8) 2295344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng ++DefCycle; 2296344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng } else { 2297344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // Assume the worst. 2298344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng DefCycle = RegNo + 2; 2299344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng } 2300344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng 2301344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng return DefCycle; 2302344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng} 2303344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng 2304344d9db97062736cd66da6c07baa9108b6cfa419Evan Chengint 2305344d9db97062736cd66da6c07baa9108b6cfa419Evan ChengARMBaseInstrInfo::getLDMDefCycle(const InstrItineraryData *ItinData, 2306e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng const MCInstrDesc &DefMCID, 2307344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng unsigned DefClass, 2308344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng unsigned DefIdx, unsigned DefAlign) const { 2309e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng int RegNo = (int)(DefIdx+1) - DefMCID.getNumOperands() + 1; 2310344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng if (RegNo <= 0) 2311344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // Def is the address writeback. 2312344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng return ItinData->getOperandCycle(DefClass, DefIdx); 2313344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng 2314344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng int DefCycle; 2315344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng if (Subtarget.isCortexA8()) { 2316344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // 4 registers would be issued: 1, 2, 1. 2317344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // 5 registers would be issued: 1, 2, 2. 2318344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng DefCycle = RegNo / 2; 2319344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng if (DefCycle < 1) 2320344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng DefCycle = 1; 2321344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // Result latency is issue cycle + 2: E2. 2322344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng DefCycle += 2; 2323344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng } else if (Subtarget.isCortexA9()) { 2324344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng DefCycle = (RegNo / 2); 2325344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // If there are odd number of registers or if it's not 64-bit aligned, 2326344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // then it takes an extra AGU (Address Generation Unit) cycle. 2327344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng if ((RegNo % 2) || DefAlign < 8) 2328344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng ++DefCycle; 2329344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // Result latency is AGU cycles + 2. 2330344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng DefCycle += 2; 2331344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng } else { 2332344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // Assume the worst. 2333344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng DefCycle = RegNo + 2; 2334344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng } 2335344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng 2336344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng return DefCycle; 2337344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng} 2338344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng 2339344d9db97062736cd66da6c07baa9108b6cfa419Evan Chengint 2340344d9db97062736cd66da6c07baa9108b6cfa419Evan ChengARMBaseInstrInfo::getVSTMUseCycle(const InstrItineraryData *ItinData, 2341e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng const MCInstrDesc &UseMCID, 2342344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng unsigned UseClass, 2343344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng unsigned UseIdx, unsigned UseAlign) const { 2344e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng int RegNo = (int)(UseIdx+1) - UseMCID.getNumOperands() + 1; 2345344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng if (RegNo <= 0) 2346344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng return ItinData->getOperandCycle(UseClass, UseIdx); 2347344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng 2348344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng int UseCycle; 2349344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng if (Subtarget.isCortexA8()) { 2350344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // (regno / 2) + (regno % 2) + 1 2351344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng UseCycle = RegNo / 2 + 1; 2352344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng if (RegNo % 2) 2353344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng ++UseCycle; 2354344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng } else if (Subtarget.isCortexA9()) { 2355344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng UseCycle = RegNo; 2356344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng bool isSStore = false; 235773fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling 2358e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng switch (UseMCID.getOpcode()) { 2359344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng default: break; 236073fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMSIA: 236173fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMSIA_UPD: 236273fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMSDB_UPD: 2363344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng isSStore = true; 2364344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng break; 2365344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng } 236673fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling 2367344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // If there are odd number of 'S' registers or if it's not 64-bit aligned, 2368344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // then it takes an extra cycle. 2369344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng if ((isSStore && (RegNo % 2)) || UseAlign < 8) 2370344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng ++UseCycle; 2371344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng } else { 2372344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // Assume the worst. 2373344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng UseCycle = RegNo + 2; 2374344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng } 2375344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng 2376344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng return UseCycle; 2377344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng} 2378344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng 2379344d9db97062736cd66da6c07baa9108b6cfa419Evan Chengint 2380344d9db97062736cd66da6c07baa9108b6cfa419Evan ChengARMBaseInstrInfo::getSTMUseCycle(const InstrItineraryData *ItinData, 2381e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng const MCInstrDesc &UseMCID, 2382344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng unsigned UseClass, 2383344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng unsigned UseIdx, unsigned UseAlign) const { 2384e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng int RegNo = (int)(UseIdx+1) - UseMCID.getNumOperands() + 1; 2385344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng if (RegNo <= 0) 2386344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng return ItinData->getOperandCycle(UseClass, UseIdx); 2387344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng 2388344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng int UseCycle; 2389344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng if (Subtarget.isCortexA8()) { 2390344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng UseCycle = RegNo / 2; 2391344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng if (UseCycle < 2) 2392344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng UseCycle = 2; 2393344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // Read in E3. 2394344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng UseCycle += 2; 2395344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng } else if (Subtarget.isCortexA9()) { 2396344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng UseCycle = (RegNo / 2); 2397344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // If there are odd number of registers or if it's not 64-bit aligned, 2398344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // then it takes an extra AGU (Address Generation Unit) cycle. 2399344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng if ((RegNo % 2) || UseAlign < 8) 2400344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng ++UseCycle; 2401344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng } else { 2402344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // Assume the worst. 2403344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng UseCycle = 1; 2404344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng } 2405344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng return UseCycle; 2406344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng} 2407344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng 2408344d9db97062736cd66da6c07baa9108b6cfa419Evan Chengint 2409a0792de66c8364d47b0a688c7f408efb7b10f31bEvan ChengARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData, 2410e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng const MCInstrDesc &DefMCID, 2411a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng unsigned DefIdx, unsigned DefAlign, 2412e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng const MCInstrDesc &UseMCID, 2413a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng unsigned UseIdx, unsigned UseAlign) const { 2414e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng unsigned DefClass = DefMCID.getSchedClass(); 2415e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng unsigned UseClass = UseMCID.getSchedClass(); 2416a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng 2417e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng if (DefIdx < DefMCID.getNumDefs() && UseIdx < UseMCID.getNumOperands()) 2418a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx); 2419a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng 2420a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng // This may be a def / use of a variable_ops instruction, the operand 2421a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng // latency might be determinable dynamically. Let the target try to 2422a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng // figure it out. 24239e08ee5d16b596078e20787f0b5f36121f099333Evan Cheng int DefCycle = -1; 24247e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng bool LdmBypass = false; 2425e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng switch (DefMCID.getOpcode()) { 2426a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng default: 2427a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng DefCycle = ItinData->getOperandCycle(DefClass, DefIdx); 2428a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng break; 242973fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling 243073fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMDIA: 243173fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMDIA_UPD: 243273fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMDDB_UPD: 243373fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMSIA: 243473fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMSIA_UPD: 243573fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMSDB_UPD: 2436e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng DefCycle = getVLDMDefCycle(ItinData, DefMCID, DefClass, DefIdx, DefAlign); 24375a50ceeaea980962c1982ad535226c7ab06c971cEvan Cheng break; 243873fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling 243973fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMIA_RET: 244073fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMIA: 244173fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMDA: 244273fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMDB: 244373fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMIB: 244473fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMIA_UPD: 244573fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMDA_UPD: 244673fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMDB_UPD: 244773fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMIB_UPD: 244873fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::tLDMIA: 244973fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::tLDMIA_UPD: 2450a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng case ARM::tPUSH: 245173fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2LDMIA_RET: 245273fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2LDMIA: 245373fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2LDMDB: 245473fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2LDMIA_UPD: 245573fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2LDMDB_UPD: 2456a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng LdmBypass = 1; 2457e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng DefCycle = getLDMDefCycle(ItinData, DefMCID, DefClass, DefIdx, DefAlign); 2458344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng break; 2459a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng } 2460a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng 2461a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng if (DefCycle == -1) 2462a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng // We can't seem to determine the result latency of the def, assume it's 2. 2463a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng DefCycle = 2; 2464a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng 2465a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng int UseCycle = -1; 2466e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng switch (UseMCID.getOpcode()) { 2467a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng default: 2468a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng UseCycle = ItinData->getOperandCycle(UseClass, UseIdx); 2469a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng break; 247073fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling 247173fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMDIA: 247273fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMDIA_UPD: 247373fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMDDB_UPD: 247473fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMSIA: 247573fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMSIA_UPD: 247673fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMSDB_UPD: 2477e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng UseCycle = getVSTMUseCycle(ItinData, UseMCID, UseClass, UseIdx, UseAlign); 24785a50ceeaea980962c1982ad535226c7ab06c971cEvan Cheng break; 247973fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling 248073fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::STMIA: 248173fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::STMDA: 248273fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::STMDB: 248373fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::STMIB: 248473fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::STMIA_UPD: 248573fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::STMDA_UPD: 248673fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::STMDB_UPD: 248773fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::STMIB_UPD: 248873fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::tSTMIA_UPD: 2489a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng case ARM::tPOP_RET: 2490a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng case ARM::tPOP: 249173fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2STMIA: 249273fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2STMDB: 249373fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2STMIA_UPD: 249473fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2STMDB_UPD: 2495e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng UseCycle = getSTMUseCycle(ItinData, UseMCID, UseClass, UseIdx, UseAlign); 24965a50ceeaea980962c1982ad535226c7ab06c971cEvan Cheng break; 2497a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng } 2498a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng 2499a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng if (UseCycle == -1) 2500a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng // Assume it's read in the first stage. 2501a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng UseCycle = 1; 2502a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng 2503a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng UseCycle = DefCycle - UseCycle + 1; 2504a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng if (UseCycle > 0) { 2505a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng if (LdmBypass) { 2506a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng // It's a variable_ops instruction so we can't use DefIdx here. Just use 2507a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng // first def operand. 2508e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng if (ItinData->hasPipelineForwarding(DefClass, DefMCID.getNumOperands()-1, 2509a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng UseClass, UseIdx)) 2510a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng --UseCycle; 2511a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng } else if (ItinData->hasPipelineForwarding(DefClass, DefIdx, 251273fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling UseClass, UseIdx)) { 2513a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng --UseCycle; 251473fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling } 2515a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng } 2516a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng 2517a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng return UseCycle; 2518a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng} 2519a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng 2520ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Chengstatic const MachineInstr *getBundledDefMI(const TargetRegisterInfo *TRI, 2521020f4106f820648fd7e91956859844a80de13974Evan Cheng const MachineInstr *MI, unsigned Reg, 2522ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng unsigned &DefIdx, unsigned &Dist) { 2523ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng Dist = 0; 2524ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng 2525ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng MachineBasicBlock::const_iterator I = MI; ++I; 2526ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng MachineBasicBlock::const_instr_iterator II = 2527ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng llvm::prior(I.getInstrIterator()); 2528ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng assert(II->isInsideBundle() && "Empty bundle?"); 2529ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng 2530ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng int Idx = -1; 2531ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng while (II->isInsideBundle()) { 2532ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng Idx = II->findRegisterDefOperandIdx(Reg, false, true, TRI); 2533ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng if (Idx != -1) 2534ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng break; 2535ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng --II; 2536ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng ++Dist; 2537ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng } 2538ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng 2539ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng assert(Idx != -1 && "Cannot find bundled definition!"); 2540ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng DefIdx = Idx; 2541ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng return II; 2542ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng} 2543ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng 2544ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Chengstatic const MachineInstr *getBundledUseMI(const TargetRegisterInfo *TRI, 2545020f4106f820648fd7e91956859844a80de13974Evan Cheng const MachineInstr *MI, unsigned Reg, 2546ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng unsigned &UseIdx, unsigned &Dist) { 2547ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng Dist = 0; 2548ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng 2549ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng MachineBasicBlock::const_instr_iterator II = MI; ++II; 2550ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng assert(II->isInsideBundle() && "Empty bundle?"); 2551ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end(); 2552ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng 2553ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng // FIXME: This doesn't properly handle multiple uses. 2554ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng int Idx = -1; 2555ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng while (II != E && II->isInsideBundle()) { 2556ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng Idx = II->findRegisterUseOperandIdx(Reg, false, TRI); 2557ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng if (Idx != -1) 2558ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng break; 2559ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng if (II->getOpcode() != ARM::t2IT) 2560ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng ++Dist; 2561ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng ++II; 2562ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng } 2563ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng 2564020f4106f820648fd7e91956859844a80de13974Evan Cheng if (Idx == -1) { 2565020f4106f820648fd7e91956859844a80de13974Evan Cheng Dist = 0; 2566020f4106f820648fd7e91956859844a80de13974Evan Cheng return 0; 2567020f4106f820648fd7e91956859844a80de13974Evan Cheng } 2568020f4106f820648fd7e91956859844a80de13974Evan Cheng 2569ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng UseIdx = Idx; 2570ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng return II; 2571ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng} 2572ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng 2573a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Chengint 2574a0792de66c8364d47b0a688c7f408efb7b10f31bEvan ChengARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData, 2575a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng const MachineInstr *DefMI, unsigned DefIdx, 2576a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng const MachineInstr *UseMI, unsigned UseIdx) const { 2577a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng if (DefMI->isCopyLike() || DefMI->isInsertSubreg() || 2578a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng DefMI->isRegSequence() || DefMI->isImplicitDef()) 2579a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng return 1; 2580a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng 2581a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng if (!ItinData || ItinData->isEmpty()) 25825a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng return DefMI->mayLoad() ? 3 : 1; 2583a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng 2584ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng const MCInstrDesc *DefMCID = &DefMI->getDesc(); 2585ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng const MCInstrDesc *UseMCID = &UseMI->getDesc(); 2586dd9dd6f857604abdeb5213648ffe50c10ccc59b9Evan Cheng const MachineOperand &DefMO = DefMI->getOperand(DefIdx); 2587020f4106f820648fd7e91956859844a80de13974Evan Cheng unsigned Reg = DefMO.getReg(); 2588020f4106f820648fd7e91956859844a80de13974Evan Cheng if (Reg == ARM::CPSR) { 2589e09206d4d7683e2a421104c5cb83f7808ba4b06eEvan Cheng if (DefMI->getOpcode() == ARM::FMSTAT) { 2590e09206d4d7683e2a421104c5cb83f7808ba4b06eEvan Cheng // fpscr -> cpsr stalls over 20 cycles on A8 (and earlier?) 2591e09206d4d7683e2a421104c5cb83f7808ba4b06eEvan Cheng return Subtarget.isCortexA9() ? 1 : 20; 2592e09206d4d7683e2a421104c5cb83f7808ba4b06eEvan Cheng } 2593e09206d4d7683e2a421104c5cb83f7808ba4b06eEvan Cheng 2594dd9dd6f857604abdeb5213648ffe50c10ccc59b9Evan Cheng // CPSR set and branch can be paired in the same cycle. 25955a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng if (UseMI->isBranch()) 2596e09206d4d7683e2a421104c5cb83f7808ba4b06eEvan Cheng return 0; 2597ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng 2598ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng // Otherwise it takes the instruction latency (generally one). 2599ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng int Latency = getInstrLatency(ItinData, DefMI); 2600020f4106f820648fd7e91956859844a80de13974Evan Cheng 2601020f4106f820648fd7e91956859844a80de13974Evan Cheng // For Thumb2 and -Os, prefer scheduling CPSR setting instruction close to 2602020f4106f820648fd7e91956859844a80de13974Evan Cheng // its uses. Instructions which are otherwise scheduled between them may 2603020f4106f820648fd7e91956859844a80de13974Evan Cheng // incur a code size penalty (not able to use the CPSR setting 16-bit 2604020f4106f820648fd7e91956859844a80de13974Evan Cheng // instructions). 2605020f4106f820648fd7e91956859844a80de13974Evan Cheng if (Latency > 0 && Subtarget.isThumb2()) { 2606020f4106f820648fd7e91956859844a80de13974Evan Cheng const MachineFunction *MF = DefMI->getParent()->getParent(); 2607020f4106f820648fd7e91956859844a80de13974Evan Cheng if (MF->getFunction()->hasFnAttr(Attribute::OptimizeForSize)) 2608020f4106f820648fd7e91956859844a80de13974Evan Cheng --Latency; 2609020f4106f820648fd7e91956859844a80de13974Evan Cheng } 2610ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng return Latency; 2611e09206d4d7683e2a421104c5cb83f7808ba4b06eEvan Cheng } 2612dd9dd6f857604abdeb5213648ffe50c10ccc59b9Evan Cheng 2613a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng unsigned DefAlign = DefMI->hasOneMemOperand() 2614a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng ? (*DefMI->memoperands_begin())->getAlignment() : 0; 2615a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng unsigned UseAlign = UseMI->hasOneMemOperand() 2616a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng ? (*UseMI->memoperands_begin())->getAlignment() : 0; 2617ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng 2618ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng unsigned DefAdj = 0; 2619ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng if (DefMI->isBundle()) { 2620020f4106f820648fd7e91956859844a80de13974Evan Cheng DefMI = getBundledDefMI(&getRegisterInfo(), DefMI, Reg, DefIdx, DefAdj); 2621ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng if (DefMI->isCopyLike() || DefMI->isInsertSubreg() || 2622ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng DefMI->isRegSequence() || DefMI->isImplicitDef()) 2623ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng return 1; 2624ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng DefMCID = &DefMI->getDesc(); 2625ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng } 2626ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng unsigned UseAdj = 0; 2627ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng if (UseMI->isBundle()) { 2628020f4106f820648fd7e91956859844a80de13974Evan Cheng unsigned NewUseIdx; 2629020f4106f820648fd7e91956859844a80de13974Evan Cheng const MachineInstr *NewUseMI = getBundledUseMI(&getRegisterInfo(), UseMI, 2630020f4106f820648fd7e91956859844a80de13974Evan Cheng Reg, NewUseIdx, UseAdj); 2631020f4106f820648fd7e91956859844a80de13974Evan Cheng if (NewUseMI) { 2632020f4106f820648fd7e91956859844a80de13974Evan Cheng UseMI = NewUseMI; 2633020f4106f820648fd7e91956859844a80de13974Evan Cheng UseIdx = NewUseIdx; 2634020f4106f820648fd7e91956859844a80de13974Evan Cheng UseMCID = &UseMI->getDesc(); 2635020f4106f820648fd7e91956859844a80de13974Evan Cheng } 2636ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng } 2637ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng 2638ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng int Latency = getOperandLatency(ItinData, *DefMCID, DefIdx, DefAlign, 2639ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng *UseMCID, UseIdx, UseAlign); 2640ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng int Adj = DefAdj + UseAdj; 2641ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng if (Adj) { 2642ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng Latency -= (int)(DefAdj + UseAdj); 2643ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng if (Latency < 1) 2644ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng return 1; 2645ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng } 26467e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng 26477e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng if (Latency > 1 && 26487e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng (Subtarget.isCortexA8() || Subtarget.isCortexA9())) { 26497e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng // FIXME: Shifter op hack: no shift (i.e. [r +/- r]) or [r + r << 2] 26507e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng // variants are one cycle cheaper. 2651ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng switch (DefMCID->getOpcode()) { 26527e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng default: break; 26537e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng case ARM::LDRrs: 26547e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng case ARM::LDRBrs: { 26557e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng unsigned ShOpVal = DefMI->getOperand(3).getImm(); 26567e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal); 26577e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng if (ShImm == 0 || 26587e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng (ShImm == 2 && ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl)) 26597e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng --Latency; 26607e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng break; 26617e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng } 26627e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng case ARM::t2LDRs: 26637e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng case ARM::t2LDRBs: 26647e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng case ARM::t2LDRHs: 26657e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng case ARM::t2LDRSHs: { 26667e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng // Thumb2 mode: lsl only. 26677e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng unsigned ShAmt = DefMI->getOperand(3).getImm(); 26687e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng if (ShAmt == 0 || ShAmt == 2) 26697e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng --Latency; 26707e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng break; 26717e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng } 26727e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng } 26737e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng } 26747e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng 267575b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng if (DefAlign < 8 && Subtarget.isCortexA9()) 2676ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng switch (DefMCID->getOpcode()) { 267775b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng default: break; 267875b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1q8: 267975b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1q16: 268075b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1q32: 268175b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1q64: 268210b90a9bbf7dcae1568c03a03f9606f5395f2144Jim Grosbach case ARM::VLD1q8wb_fixed: 268310b90a9bbf7dcae1568c03a03f9606f5395f2144Jim Grosbach case ARM::VLD1q16wb_fixed: 268410b90a9bbf7dcae1568c03a03f9606f5395f2144Jim Grosbach case ARM::VLD1q32wb_fixed: 268510b90a9bbf7dcae1568c03a03f9606f5395f2144Jim Grosbach case ARM::VLD1q64wb_fixed: 268610b90a9bbf7dcae1568c03a03f9606f5395f2144Jim Grosbach case ARM::VLD1q8wb_register: 268710b90a9bbf7dcae1568c03a03f9606f5395f2144Jim Grosbach case ARM::VLD1q16wb_register: 268810b90a9bbf7dcae1568c03a03f9606f5395f2144Jim Grosbach case ARM::VLD1q32wb_register: 268910b90a9bbf7dcae1568c03a03f9606f5395f2144Jim Grosbach case ARM::VLD1q64wb_register: 269075b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2d8: 269175b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2d16: 269275b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2d32: 269375b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2q8: 269475b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2q16: 269575b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2q32: 2696a4e3c7fc4ba2d55695b0484480685698132eba20Jim Grosbach case ARM::VLD2d8wb_fixed: 2697a4e3c7fc4ba2d55695b0484480685698132eba20Jim Grosbach case ARM::VLD2d16wb_fixed: 2698a4e3c7fc4ba2d55695b0484480685698132eba20Jim Grosbach case ARM::VLD2d32wb_fixed: 2699a4e3c7fc4ba2d55695b0484480685698132eba20Jim Grosbach case ARM::VLD2q8wb_fixed: 2700a4e3c7fc4ba2d55695b0484480685698132eba20Jim Grosbach case ARM::VLD2q16wb_fixed: 2701a4e3c7fc4ba2d55695b0484480685698132eba20Jim Grosbach case ARM::VLD2q32wb_fixed: 2702a4e3c7fc4ba2d55695b0484480685698132eba20Jim Grosbach case ARM::VLD2d8wb_register: 2703a4e3c7fc4ba2d55695b0484480685698132eba20Jim Grosbach case ARM::VLD2d16wb_register: 2704a4e3c7fc4ba2d55695b0484480685698132eba20Jim Grosbach case ARM::VLD2d32wb_register: 2705a4e3c7fc4ba2d55695b0484480685698132eba20Jim Grosbach case ARM::VLD2q8wb_register: 2706a4e3c7fc4ba2d55695b0484480685698132eba20Jim Grosbach case ARM::VLD2q16wb_register: 2707a4e3c7fc4ba2d55695b0484480685698132eba20Jim Grosbach case ARM::VLD2q32wb_register: 270875b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3d8: 270975b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3d16: 271075b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3d32: 271175b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1d64T: 271275b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3d8_UPD: 271375b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3d16_UPD: 271475b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3d32_UPD: 27155921675ff5ea632ab1e6d7aa5d1f263b858bbafaJim Grosbach case ARM::VLD1d64Twb_fixed: 27165921675ff5ea632ab1e6d7aa5d1f263b858bbafaJim Grosbach case ARM::VLD1d64Twb_register: 271775b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3q8_UPD: 271875b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3q16_UPD: 271975b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3q32_UPD: 272075b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4d8: 272175b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4d16: 272275b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4d32: 272375b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1d64Q: 272475b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4d8_UPD: 272575b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4d16_UPD: 272675b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4d32_UPD: 2727399cdca4d201f7232126c3a0643669971ede780aJim Grosbach case ARM::VLD1d64Qwb_fixed: 2728399cdca4d201f7232126c3a0643669971ede780aJim Grosbach case ARM::VLD1d64Qwb_register: 272975b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4q8_UPD: 273075b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4q16_UPD: 273175b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4q32_UPD: 273275b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1DUPq8: 273375b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1DUPq16: 273475b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1DUPq32: 2735096334e25ea68ac970942ecb680a82fbb8ad206cJim Grosbach case ARM::VLD1DUPq8wb_fixed: 2736096334e25ea68ac970942ecb680a82fbb8ad206cJim Grosbach case ARM::VLD1DUPq16wb_fixed: 2737096334e25ea68ac970942ecb680a82fbb8ad206cJim Grosbach case ARM::VLD1DUPq32wb_fixed: 2738096334e25ea68ac970942ecb680a82fbb8ad206cJim Grosbach case ARM::VLD1DUPq8wb_register: 2739096334e25ea68ac970942ecb680a82fbb8ad206cJim Grosbach case ARM::VLD1DUPq16wb_register: 2740096334e25ea68ac970942ecb680a82fbb8ad206cJim Grosbach case ARM::VLD1DUPq32wb_register: 274175b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2DUPd8: 274275b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2DUPd16: 274375b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2DUPd32: 2744e6949b13997e6d31aa4719a0e80c4b6b405e42a9Jim Grosbach case ARM::VLD2DUPd8wb_fixed: 2745e6949b13997e6d31aa4719a0e80c4b6b405e42a9Jim Grosbach case ARM::VLD2DUPd16wb_fixed: 2746e6949b13997e6d31aa4719a0e80c4b6b405e42a9Jim Grosbach case ARM::VLD2DUPd32wb_fixed: 2747e6949b13997e6d31aa4719a0e80c4b6b405e42a9Jim Grosbach case ARM::VLD2DUPd8wb_register: 2748e6949b13997e6d31aa4719a0e80c4b6b405e42a9Jim Grosbach case ARM::VLD2DUPd16wb_register: 2749e6949b13997e6d31aa4719a0e80c4b6b405e42a9Jim Grosbach case ARM::VLD2DUPd32wb_register: 275075b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4DUPd8: 275175b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4DUPd16: 275275b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4DUPd32: 275375b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4DUPd8_UPD: 275475b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4DUPd16_UPD: 275575b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4DUPd32_UPD: 275675b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1LNd8: 275775b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1LNd16: 275875b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1LNd32: 275975b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1LNd8_UPD: 276075b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1LNd16_UPD: 276175b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1LNd32_UPD: 276275b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2LNd8: 276375b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2LNd16: 276475b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2LNd32: 276575b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2LNq16: 276675b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2LNq32: 276775b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2LNd8_UPD: 276875b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2LNd16_UPD: 276975b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2LNd32_UPD: 277075b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2LNq16_UPD: 277175b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2LNq32_UPD: 277275b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4LNd8: 277375b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4LNd16: 277475b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4LNd32: 277575b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4LNq16: 277675b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4LNq32: 277775b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4LNd8_UPD: 277875b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4LNd16_UPD: 277975b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4LNd32_UPD: 278075b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4LNq16_UPD: 278175b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4LNq32_UPD: 278275b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng // If the address is not 64-bit aligned, the latencies of these 278375b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng // instructions increases by one. 278475b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng ++Latency; 278575b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng break; 278675b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng } 278775b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng 27887e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng return Latency; 2789a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng} 2790a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng 2791a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Chengint 2792a0792de66c8364d47b0a688c7f408efb7b10f31bEvan ChengARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData, 2793a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng SDNode *DefNode, unsigned DefIdx, 2794a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng SDNode *UseNode, unsigned UseIdx) const { 2795a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng if (!DefNode->isMachineOpcode()) 2796a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng return 1; 2797a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng 2798e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng const MCInstrDesc &DefMCID = get(DefNode->getMachineOpcode()); 2799c8bfd1d78ff9a307d1d4cb57cce4549b538e60f4Andrew Trick 2800e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng if (isZeroCost(DefMCID.Opcode)) 2801c8bfd1d78ff9a307d1d4cb57cce4549b538e60f4Andrew Trick return 0; 2802c8bfd1d78ff9a307d1d4cb57cce4549b538e60f4Andrew Trick 2803a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng if (!ItinData || ItinData->isEmpty()) 2804e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng return DefMCID.mayLoad() ? 3 : 1; 2805a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng 2806089751535d6e9adf65842e2ca5867bf9a70e1e95Evan Cheng if (!UseNode->isMachineOpcode()) { 2807e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng int Latency = ItinData->getOperandCycle(DefMCID.getSchedClass(), DefIdx); 2808089751535d6e9adf65842e2ca5867bf9a70e1e95Evan Cheng if (Subtarget.isCortexA9()) 2809089751535d6e9adf65842e2ca5867bf9a70e1e95Evan Cheng return Latency <= 2 ? 1 : Latency - 1; 2810089751535d6e9adf65842e2ca5867bf9a70e1e95Evan Cheng else 2811089751535d6e9adf65842e2ca5867bf9a70e1e95Evan Cheng return Latency <= 3 ? 1 : Latency - 2; 2812089751535d6e9adf65842e2ca5867bf9a70e1e95Evan Cheng } 2813a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng 2814e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng const MCInstrDesc &UseMCID = get(UseNode->getMachineOpcode()); 2815a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng const MachineSDNode *DefMN = dyn_cast<MachineSDNode>(DefNode); 2816a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng unsigned DefAlign = !DefMN->memoperands_empty() 2817a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng ? (*DefMN->memoperands_begin())->getAlignment() : 0; 2818a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng const MachineSDNode *UseMN = dyn_cast<MachineSDNode>(UseNode); 2819a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng unsigned UseAlign = !UseMN->memoperands_empty() 2820a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng ? (*UseMN->memoperands_begin())->getAlignment() : 0; 2821e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng int Latency = getOperandLatency(ItinData, DefMCID, DefIdx, DefAlign, 2822e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng UseMCID, UseIdx, UseAlign); 28237e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng 28247e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng if (Latency > 1 && 28257e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng (Subtarget.isCortexA8() || Subtarget.isCortexA9())) { 28267e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng // FIXME: Shifter op hack: no shift (i.e. [r +/- r]) or [r + r << 2] 28277e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng // variants are one cycle cheaper. 2828e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng switch (DefMCID.getOpcode()) { 28297e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng default: break; 28307e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng case ARM::LDRrs: 28317e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng case ARM::LDRBrs: { 28327e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng unsigned ShOpVal = 28337e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng cast<ConstantSDNode>(DefNode->getOperand(2))->getZExtValue(); 28347e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal); 28357e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng if (ShImm == 0 || 28367e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng (ShImm == 2 && ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl)) 28377e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng --Latency; 28387e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng break; 28397e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng } 28407e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng case ARM::t2LDRs: 28417e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng case ARM::t2LDRBs: 28427e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng case ARM::t2LDRHs: 28437e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng case ARM::t2LDRSHs: { 28447e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng // Thumb2 mode: lsl only. 28457e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng unsigned ShAmt = 28467e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng cast<ConstantSDNode>(DefNode->getOperand(2))->getZExtValue(); 28477e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng if (ShAmt == 0 || ShAmt == 2) 28487e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng --Latency; 28497e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng break; 28507e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng } 28517e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng } 28527e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng } 28537e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng 285475b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng if (DefAlign < 8 && Subtarget.isCortexA9()) 2855e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng switch (DefMCID.getOpcode()) { 285675b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng default: break; 285728f08c93e75d291695ea89b9004145103292e85bJim Grosbach case ARM::VLD1q8: 285828f08c93e75d291695ea89b9004145103292e85bJim Grosbach case ARM::VLD1q16: 285928f08c93e75d291695ea89b9004145103292e85bJim Grosbach case ARM::VLD1q32: 286028f08c93e75d291695ea89b9004145103292e85bJim Grosbach case ARM::VLD1q64: 286128f08c93e75d291695ea89b9004145103292e85bJim Grosbach case ARM::VLD1q8wb_register: 286228f08c93e75d291695ea89b9004145103292e85bJim Grosbach case ARM::VLD1q16wb_register: 286328f08c93e75d291695ea89b9004145103292e85bJim Grosbach case ARM::VLD1q32wb_register: 286428f08c93e75d291695ea89b9004145103292e85bJim Grosbach case ARM::VLD1q64wb_register: 286528f08c93e75d291695ea89b9004145103292e85bJim Grosbach case ARM::VLD1q8wb_fixed: 286628f08c93e75d291695ea89b9004145103292e85bJim Grosbach case ARM::VLD1q16wb_fixed: 286728f08c93e75d291695ea89b9004145103292e85bJim Grosbach case ARM::VLD1q32wb_fixed: 286828f08c93e75d291695ea89b9004145103292e85bJim Grosbach case ARM::VLD1q64wb_fixed: 286928f08c93e75d291695ea89b9004145103292e85bJim Grosbach case ARM::VLD2d8: 287028f08c93e75d291695ea89b9004145103292e85bJim Grosbach case ARM::VLD2d16: 287128f08c93e75d291695ea89b9004145103292e85bJim Grosbach case ARM::VLD2d32: 287275b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2q8Pseudo: 287375b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2q16Pseudo: 287475b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2q32Pseudo: 287528f08c93e75d291695ea89b9004145103292e85bJim Grosbach case ARM::VLD2d8wb_fixed: 287628f08c93e75d291695ea89b9004145103292e85bJim Grosbach case ARM::VLD2d16wb_fixed: 287728f08c93e75d291695ea89b9004145103292e85bJim Grosbach case ARM::VLD2d32wb_fixed: 2878a4e3c7fc4ba2d55695b0484480685698132eba20Jim Grosbach case ARM::VLD2q8PseudoWB_fixed: 2879a4e3c7fc4ba2d55695b0484480685698132eba20Jim Grosbach case ARM::VLD2q16PseudoWB_fixed: 2880a4e3c7fc4ba2d55695b0484480685698132eba20Jim Grosbach case ARM::VLD2q32PseudoWB_fixed: 288128f08c93e75d291695ea89b9004145103292e85bJim Grosbach case ARM::VLD2d8wb_register: 288228f08c93e75d291695ea89b9004145103292e85bJim Grosbach case ARM::VLD2d16wb_register: 288328f08c93e75d291695ea89b9004145103292e85bJim Grosbach case ARM::VLD2d32wb_register: 2884a4e3c7fc4ba2d55695b0484480685698132eba20Jim Grosbach case ARM::VLD2q8PseudoWB_register: 2885a4e3c7fc4ba2d55695b0484480685698132eba20Jim Grosbach case ARM::VLD2q16PseudoWB_register: 2886a4e3c7fc4ba2d55695b0484480685698132eba20Jim Grosbach case ARM::VLD2q32PseudoWB_register: 288775b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3d8Pseudo: 288875b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3d16Pseudo: 288975b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3d32Pseudo: 289075b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1d64TPseudo: 289175b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3d8Pseudo_UPD: 289275b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3d16Pseudo_UPD: 289375b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3d32Pseudo_UPD: 289475b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3q8Pseudo_UPD: 289575b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3q16Pseudo_UPD: 289675b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3q32Pseudo_UPD: 289775b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3q8oddPseudo: 289875b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3q16oddPseudo: 289975b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3q32oddPseudo: 290075b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3q8oddPseudo_UPD: 290175b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3q16oddPseudo_UPD: 290275b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3q32oddPseudo_UPD: 290375b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4d8Pseudo: 290475b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4d16Pseudo: 290575b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4d32Pseudo: 290675b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1d64QPseudo: 290775b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4d8Pseudo_UPD: 290875b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4d16Pseudo_UPD: 290975b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4d32Pseudo_UPD: 291075b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4q8Pseudo_UPD: 291175b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4q16Pseudo_UPD: 291275b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4q32Pseudo_UPD: 291375b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4q8oddPseudo: 291475b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4q16oddPseudo: 291575b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4q32oddPseudo: 291675b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4q8oddPseudo_UPD: 291775b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4q16oddPseudo_UPD: 291875b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4q32oddPseudo_UPD: 2919c0fc450f0754508871bc70f21e528bf2f1520da1Jim Grosbach case ARM::VLD1DUPq8: 2920c0fc450f0754508871bc70f21e528bf2f1520da1Jim Grosbach case ARM::VLD1DUPq16: 2921c0fc450f0754508871bc70f21e528bf2f1520da1Jim Grosbach case ARM::VLD1DUPq32: 2922c0fc450f0754508871bc70f21e528bf2f1520da1Jim Grosbach case ARM::VLD1DUPq8wb_fixed: 2923c0fc450f0754508871bc70f21e528bf2f1520da1Jim Grosbach case ARM::VLD1DUPq16wb_fixed: 2924c0fc450f0754508871bc70f21e528bf2f1520da1Jim Grosbach case ARM::VLD1DUPq32wb_fixed: 2925c0fc450f0754508871bc70f21e528bf2f1520da1Jim Grosbach case ARM::VLD1DUPq8wb_register: 2926c0fc450f0754508871bc70f21e528bf2f1520da1Jim Grosbach case ARM::VLD1DUPq16wb_register: 2927c0fc450f0754508871bc70f21e528bf2f1520da1Jim Grosbach case ARM::VLD1DUPq32wb_register: 2928c0fc450f0754508871bc70f21e528bf2f1520da1Jim Grosbach case ARM::VLD2DUPd8: 2929c0fc450f0754508871bc70f21e528bf2f1520da1Jim Grosbach case ARM::VLD2DUPd16: 2930c0fc450f0754508871bc70f21e528bf2f1520da1Jim Grosbach case ARM::VLD2DUPd32: 2931c0fc450f0754508871bc70f21e528bf2f1520da1Jim Grosbach case ARM::VLD2DUPd8wb_fixed: 2932c0fc450f0754508871bc70f21e528bf2f1520da1Jim Grosbach case ARM::VLD2DUPd16wb_fixed: 2933c0fc450f0754508871bc70f21e528bf2f1520da1Jim Grosbach case ARM::VLD2DUPd32wb_fixed: 2934c0fc450f0754508871bc70f21e528bf2f1520da1Jim Grosbach case ARM::VLD2DUPd8wb_register: 2935c0fc450f0754508871bc70f21e528bf2f1520da1Jim Grosbach case ARM::VLD2DUPd16wb_register: 2936c0fc450f0754508871bc70f21e528bf2f1520da1Jim Grosbach case ARM::VLD2DUPd32wb_register: 293775b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4DUPd8Pseudo: 293875b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4DUPd16Pseudo: 293975b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4DUPd32Pseudo: 294075b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4DUPd8Pseudo_UPD: 294175b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4DUPd16Pseudo_UPD: 294275b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4DUPd32Pseudo_UPD: 294375b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1LNq8Pseudo: 294475b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1LNq16Pseudo: 294575b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1LNq32Pseudo: 294675b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1LNq8Pseudo_UPD: 294775b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1LNq16Pseudo_UPD: 294875b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1LNq32Pseudo_UPD: 294975b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2LNd8Pseudo: 295075b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2LNd16Pseudo: 295175b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2LNd32Pseudo: 295275b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2LNq16Pseudo: 295375b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2LNq32Pseudo: 295475b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2LNd8Pseudo_UPD: 295575b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2LNd16Pseudo_UPD: 295675b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2LNd32Pseudo_UPD: 295775b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2LNq16Pseudo_UPD: 295875b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2LNq32Pseudo_UPD: 295975b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4LNd8Pseudo: 296075b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4LNd16Pseudo: 296175b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4LNd32Pseudo: 296275b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4LNq16Pseudo: 296375b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4LNq32Pseudo: 296475b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4LNd8Pseudo_UPD: 296575b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4LNd16Pseudo_UPD: 296675b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4LNd32Pseudo_UPD: 296775b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4LNq16Pseudo_UPD: 296875b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4LNq32Pseudo_UPD: 296975b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng // If the address is not 64-bit aligned, the latencies of these 297075b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng // instructions increases by one. 297175b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng ++Latency; 297275b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng break; 297375b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng } 297475b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng 29757e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng return Latency; 2976a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng} 29772312842de0c641107dd04d7e056d02491cc781caEvan Cheng 2978020f4106f820648fd7e91956859844a80de13974Evan Chengunsigned 2979020f4106f820648fd7e91956859844a80de13974Evan ChengARMBaseInstrInfo::getOutputLatency(const InstrItineraryData *ItinData, 2980020f4106f820648fd7e91956859844a80de13974Evan Cheng const MachineInstr *DefMI, unsigned DefIdx, 2981020f4106f820648fd7e91956859844a80de13974Evan Cheng const MachineInstr *DepMI) const { 2982020f4106f820648fd7e91956859844a80de13974Evan Cheng unsigned Reg = DefMI->getOperand(DefIdx).getReg(); 2983020f4106f820648fd7e91956859844a80de13974Evan Cheng if (DepMI->readsRegister(Reg, &getRegisterInfo()) || !isPredicated(DepMI)) 2984020f4106f820648fd7e91956859844a80de13974Evan Cheng return 1; 2985020f4106f820648fd7e91956859844a80de13974Evan Cheng 2986020f4106f820648fd7e91956859844a80de13974Evan Cheng // If the second MI is predicated, then there is an implicit use dependency. 2987020f4106f820648fd7e91956859844a80de13974Evan Cheng return getOperandLatency(ItinData, DefMI, DefIdx, DepMI, 2988020f4106f820648fd7e91956859844a80de13974Evan Cheng DepMI->getNumOperands()); 2989020f4106f820648fd7e91956859844a80de13974Evan Cheng} 2990020f4106f820648fd7e91956859844a80de13974Evan Cheng 29918239daf7c83a65a189c352cce3191cdc3bbfe151Evan Chengint ARMBaseInstrInfo::getInstrLatency(const InstrItineraryData *ItinData, 29928239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng const MachineInstr *MI, 29938239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng unsigned *PredCost) const { 29948239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng if (MI->isCopyLike() || MI->isInsertSubreg() || 29958239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng MI->isRegSequence() || MI->isImplicitDef()) 29968239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng return 1; 29978239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng 29988239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng if (!ItinData || ItinData->isEmpty()) 29998239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng return 1; 30008239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng 3001ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng if (MI->isBundle()) { 3002ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng int Latency = 0; 3003ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng MachineBasicBlock::const_instr_iterator I = MI; 3004ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end(); 3005ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng while (++I != E && I->isInsideBundle()) { 3006ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng if (I->getOpcode() != ARM::t2IT) 3007ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng Latency += getInstrLatency(ItinData, I, PredCost); 3008ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng } 3009ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng return Latency; 3010ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng } 3011ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng 3012e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng const MCInstrDesc &MCID = MI->getDesc(); 3013e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng unsigned Class = MCID.getSchedClass(); 30148239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng unsigned UOps = ItinData->Itineraries[Class].NumMicroOps; 30158c3b87cf19df5631125254784d57446b80e12397Jakob Stoklund Olesen if (PredCost && (MCID.isCall() || MCID.hasImplicitDefOfPhysReg(ARM::CPSR))) 30168239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng // When predicated, CPSR is an additional source operand for CPSR updating 30178239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng // instructions, this apparently increases their latencies. 30188239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng *PredCost = 1; 30198239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng if (UOps) 30208239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng return ItinData->getStageLatency(Class); 30218239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng return getNumMicroOps(ItinData, MI); 30228239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng} 30238239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng 30248239daf7c83a65a189c352cce3191cdc3bbfe151Evan Chengint ARMBaseInstrInfo::getInstrLatency(const InstrItineraryData *ItinData, 30258239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng SDNode *Node) const { 30268239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng if (!Node->isMachineOpcode()) 30278239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng return 1; 30288239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng 30298239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng if (!ItinData || ItinData->isEmpty()) 30308239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng return 1; 30318239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng 30328239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng unsigned Opcode = Node->getMachineOpcode(); 30338239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng switch (Opcode) { 30348239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng default: 30358239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng return ItinData->getStageLatency(get(Opcode).getSchedClass()); 303673fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMQIA: 303773fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMQIA: 30388239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng return 2; 30398b3ca6216d62bf3f729c2e122dcfeb7c4d7500dcEric Christopher } 30408239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng} 30418239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng 30422312842de0c641107dd04d7e056d02491cc781caEvan Chengbool ARMBaseInstrInfo:: 30432312842de0c641107dd04d7e056d02491cc781caEvan ChenghasHighOperandLatency(const InstrItineraryData *ItinData, 30442312842de0c641107dd04d7e056d02491cc781caEvan Cheng const MachineRegisterInfo *MRI, 30452312842de0c641107dd04d7e056d02491cc781caEvan Cheng const MachineInstr *DefMI, unsigned DefIdx, 30462312842de0c641107dd04d7e056d02491cc781caEvan Cheng const MachineInstr *UseMI, unsigned UseIdx) const { 30472312842de0c641107dd04d7e056d02491cc781caEvan Cheng unsigned DDomain = DefMI->getDesc().TSFlags & ARMII::DomainMask; 30482312842de0c641107dd04d7e056d02491cc781caEvan Cheng unsigned UDomain = UseMI->getDesc().TSFlags & ARMII::DomainMask; 30492312842de0c641107dd04d7e056d02491cc781caEvan Cheng if (Subtarget.isCortexA8() && 30502312842de0c641107dd04d7e056d02491cc781caEvan Cheng (DDomain == ARMII::DomainVFP || UDomain == ARMII::DomainVFP)) 30512312842de0c641107dd04d7e056d02491cc781caEvan Cheng // CortexA8 VFP instructions are not pipelined. 30522312842de0c641107dd04d7e056d02491cc781caEvan Cheng return true; 30532312842de0c641107dd04d7e056d02491cc781caEvan Cheng 30542312842de0c641107dd04d7e056d02491cc781caEvan Cheng // Hoist VFP / NEON instructions with 4 or higher latency. 30552312842de0c641107dd04d7e056d02491cc781caEvan Cheng int Latency = getOperandLatency(ItinData, DefMI, DefIdx, UseMI, UseIdx); 30562312842de0c641107dd04d7e056d02491cc781caEvan Cheng if (Latency <= 3) 30572312842de0c641107dd04d7e056d02491cc781caEvan Cheng return false; 30582312842de0c641107dd04d7e056d02491cc781caEvan Cheng return DDomain == ARMII::DomainVFP || DDomain == ARMII::DomainNEON || 30592312842de0c641107dd04d7e056d02491cc781caEvan Cheng UDomain == ARMII::DomainVFP || UDomain == ARMII::DomainNEON; 30602312842de0c641107dd04d7e056d02491cc781caEvan Cheng} 3061c8141dfc7f983cb04e65d8acd6bcbdc8e4b8a0aeEvan Cheng 3062c8141dfc7f983cb04e65d8acd6bcbdc8e4b8a0aeEvan Chengbool ARMBaseInstrInfo:: 3063c8141dfc7f983cb04e65d8acd6bcbdc8e4b8a0aeEvan ChenghasLowDefLatency(const InstrItineraryData *ItinData, 3064c8141dfc7f983cb04e65d8acd6bcbdc8e4b8a0aeEvan Cheng const MachineInstr *DefMI, unsigned DefIdx) const { 3065c8141dfc7f983cb04e65d8acd6bcbdc8e4b8a0aeEvan Cheng if (!ItinData || ItinData->isEmpty()) 3066c8141dfc7f983cb04e65d8acd6bcbdc8e4b8a0aeEvan Cheng return false; 3067c8141dfc7f983cb04e65d8acd6bcbdc8e4b8a0aeEvan Cheng 3068c8141dfc7f983cb04e65d8acd6bcbdc8e4b8a0aeEvan Cheng unsigned DDomain = DefMI->getDesc().TSFlags & ARMII::DomainMask; 3069c8141dfc7f983cb04e65d8acd6bcbdc8e4b8a0aeEvan Cheng if (DDomain == ARMII::DomainGeneral) { 3070c8141dfc7f983cb04e65d8acd6bcbdc8e4b8a0aeEvan Cheng unsigned DefClass = DefMI->getDesc().getSchedClass(); 3071c8141dfc7f983cb04e65d8acd6bcbdc8e4b8a0aeEvan Cheng int DefCycle = ItinData->getOperandCycle(DefClass, DefIdx); 3072c8141dfc7f983cb04e65d8acd6bcbdc8e4b8a0aeEvan Cheng return (DefCycle != -1 && DefCycle <= 2); 3073c8141dfc7f983cb04e65d8acd6bcbdc8e4b8a0aeEvan Cheng } 3074c8141dfc7f983cb04e65d8acd6bcbdc8e4b8a0aeEvan Cheng return false; 3075c8141dfc7f983cb04e65d8acd6bcbdc8e4b8a0aeEvan Cheng} 307648575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng 30773be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trickbool ARMBaseInstrInfo::verifyInstruction(const MachineInstr *MI, 30783be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick StringRef &ErrInfo) const { 30793be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick if (convertAddSubFlagsOpcode(MI->getOpcode())) { 30803be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick ErrInfo = "Pseudo flag setting opcodes only exist in Selection DAG"; 30813be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick return false; 30823be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick } 30833be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick return true; 30843be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick} 30853be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick 308648575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Chengbool 308748575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan ChengARMBaseInstrInfo::isFpMLxInstruction(unsigned Opcode, unsigned &MulOpc, 308848575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng unsigned &AddSubOpc, 308948575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng bool &NegAcc, bool &HasLane) const { 309048575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng DenseMap<unsigned, unsigned>::const_iterator I = MLxEntryMap.find(Opcode); 309148575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng if (I == MLxEntryMap.end()) 309248575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng return false; 309348575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng 309448575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng const ARM_MLxEntry &Entry = ARM_MLxTable[I->second]; 309548575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng MulOpc = Entry.MulOpc; 309648575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng AddSubOpc = Entry.AddSubOpc; 309748575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng NegAcc = Entry.NegAcc; 309848575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng HasLane = Entry.HasLane; 309948575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng return true; 310048575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng} 310113fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen 310213fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen//===----------------------------------------------------------------------===// 310313fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen// Execution domains. 310413fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen//===----------------------------------------------------------------------===// 310513fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen// 310613fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen// Some instructions go down the NEON pipeline, some go down the VFP pipeline, 310713fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen// and some can go down both. The vmov instructions go down the VFP pipeline, 310813fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen// but they can be changed to vorr equivalents that are executed by the NEON 310913fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen// pipeline. 311013fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen// 311113fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen// We use the following execution domain numbering: 311213fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen// 31138bb3d3cb30df06bdcb3ef5a208e3e59f4eeb4868Jakob Stoklund Olesenenum ARMExeDomain { 31148bb3d3cb30df06bdcb3ef5a208e3e59f4eeb4868Jakob Stoklund Olesen ExeGeneric = 0, 31158bb3d3cb30df06bdcb3ef5a208e3e59f4eeb4868Jakob Stoklund Olesen ExeVFP = 1, 31168bb3d3cb30df06bdcb3ef5a208e3e59f4eeb4868Jakob Stoklund Olesen ExeNEON = 2 31178bb3d3cb30df06bdcb3ef5a208e3e59f4eeb4868Jakob Stoklund Olesen}; 311813fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen// 311913fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen// Also see ARMInstrFormats.td and Domain* enums in ARMBaseInfo.h 312013fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen// 312113fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesenstd::pair<uint16_t, uint16_t> 312213fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund OlesenARMBaseInstrInfo::getExecutionDomain(const MachineInstr *MI) const { 312313fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen // VMOVD is a VFP instruction, but can be changed to NEON if it isn't 312413fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen // predicated. 312513fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen if (MI->getOpcode() == ARM::VMOVD && !isPredicated(MI)) 31268bb3d3cb30df06bdcb3ef5a208e3e59f4eeb4868Jakob Stoklund Olesen return std::make_pair(ExeVFP, (1<<ExeVFP) | (1<<ExeNEON)); 312713fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen 312813fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen // No other instructions can be swizzled, so just determine their domain. 312913fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen unsigned Domain = MI->getDesc().TSFlags & ARMII::DomainMask; 313013fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen 313113fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen if (Domain & ARMII::DomainNEON) 31328bb3d3cb30df06bdcb3ef5a208e3e59f4eeb4868Jakob Stoklund Olesen return std::make_pair(ExeNEON, 0); 313313fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen 313413fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen // Certain instructions can go either way on Cortex-A8. 313513fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen // Treat them as NEON instructions. 313613fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen if ((Domain & ARMII::DomainNEONA8) && Subtarget.isCortexA8()) 31378bb3d3cb30df06bdcb3ef5a208e3e59f4eeb4868Jakob Stoklund Olesen return std::make_pair(ExeNEON, 0); 313813fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen 313913fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen if (Domain & ARMII::DomainVFP) 31408bb3d3cb30df06bdcb3ef5a208e3e59f4eeb4868Jakob Stoklund Olesen return std::make_pair(ExeVFP, 0); 314113fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen 31428bb3d3cb30df06bdcb3ef5a208e3e59f4eeb4868Jakob Stoklund Olesen return std::make_pair(ExeGeneric, 0); 314313fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen} 314413fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen 314513fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesenvoid 314613fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund OlesenARMBaseInstrInfo::setExecutionDomain(MachineInstr *MI, unsigned Domain) const { 314713fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen // We only know how to change VMOVD into VORR. 314813fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen assert(MI->getOpcode() == ARM::VMOVD && "Can only swizzle VMOVD"); 31498bb3d3cb30df06bdcb3ef5a208e3e59f4eeb4868Jakob Stoklund Olesen if (Domain != ExeNEON) 315013fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen return; 315113fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen 31528bb3d3cb30df06bdcb3ef5a208e3e59f4eeb4868Jakob Stoklund Olesen // Zap the predicate operands. 31538bb3d3cb30df06bdcb3ef5a208e3e59f4eeb4868Jakob Stoklund Olesen assert(!isPredicated(MI) && "Cannot predicate a VORRd"); 31548bb3d3cb30df06bdcb3ef5a208e3e59f4eeb4868Jakob Stoklund Olesen MI->RemoveOperand(3); 31558bb3d3cb30df06bdcb3ef5a208e3e59f4eeb4868Jakob Stoklund Olesen MI->RemoveOperand(2); 31568bb3d3cb30df06bdcb3ef5a208e3e59f4eeb4868Jakob Stoklund Olesen 315713fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen // Change to a VORRd which requires two identical use operands. 315813fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen MI->setDesc(get(ARM::VORRd)); 31598bb3d3cb30df06bdcb3ef5a208e3e59f4eeb4868Jakob Stoklund Olesen 31608bb3d3cb30df06bdcb3ef5a208e3e59f4eeb4868Jakob Stoklund Olesen // Add the extra source operand and new predicates. 31618bb3d3cb30df06bdcb3ef5a208e3e59f4eeb4868Jakob Stoklund Olesen // This will go before any implicit ops. 31621c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen AddDefaultPred(MachineInstrBuilder(MI).addOperand(MI->getOperand(1))); 316313fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen} 3164c01810eeb7227010f73cb39e3c4fa0197a3c4ef0Jim Grosbach 3165c01810eeb7227010f73cb39e3c4fa0197a3c4ef0Jim Grosbachbool ARMBaseInstrInfo::hasNOP() const { 3166c01810eeb7227010f73cb39e3c4fa0197a3c4ef0Jim Grosbach return (Subtarget.getFeatureBits() & ARM::HasV6T2Ops) != 0; 3167c01810eeb7227010f73cb39e3c4fa0197a3c4ef0Jim Grosbach} 3168