ARMBaseInstrInfo.cpp revision 2d15d641aa8aa9e48c268170f1a9825bb9926fc7
131d157ae1ac2cd9c787dc3c1d28e64c682803844Jia Liu//===-- ARMBaseInstrInfo.cpp - ARM Instruction Information ----------------===// 2334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// 3334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// The LLVM Compiler Infrastructure 4334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// 5334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// This file is distributed under the University of Illinois Open Source 6334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// License. See LICENSE.TXT for details. 7334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// 8334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin//===----------------------------------------------------------------------===// 9334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// 10334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// This file contains the Base ARM implementation of the TargetInstrInfo class. 11334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// 12334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin//===----------------------------------------------------------------------===// 13334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 14334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "ARMBaseInstrInfo.h" 15334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "ARM.h" 160e5233a9e5ee9385c6a940e3985194d77bee0bbbCraig Topper#include "ARMBaseRegisterInfo.h" 17d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng#include "ARMConstantPoolValue.h" 1848575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng#include "ARMHazardRecognizer.h" 19334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "ARMMachineFunctionInfo.h" 20ee04a6d3a40c3017124e3fd89a0db473a2824498Evan Cheng#include "MCTargetDesc/ARMAddressingModes.h" 21fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng#include "llvm/Constants.h" 22fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng#include "llvm/Function.h" 23fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng#include "llvm/GlobalValue.h" 24334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "llvm/CodeGen/LiveVariables.h" 25d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng#include "llvm/CodeGen/MachineConstantPool.h" 26334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "llvm/CodeGen/MachineFrameInfo.h" 27334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "llvm/CodeGen/MachineInstrBuilder.h" 28334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "llvm/CodeGen/MachineJumpTableInfo.h" 29249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov#include "llvm/CodeGen/MachineMemOperand.h" 302457f2c66184e978d4ed8fa9e2128effff26cb0bEvan Cheng#include "llvm/CodeGen/MachineRegisterInfo.h" 31ee04a6d3a40c3017124e3fd89a0db473a2824498Evan Cheng#include "llvm/CodeGen/SelectionDAGNodes.h" 32af76e592c7f9deff0e55c13dbb4a34f07f1c7f64Chris Lattner#include "llvm/MC/MCAsmInfo.h" 33f81b7f6069b27c0a515070dcb392f6828437412fJakub Staszak#include "llvm/Support/BranchProbability.h" 34334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "llvm/Support/CommandLine.h" 35f95215f551949d5e5adfbf4753aa833b9009b77aAnton Korobeynikov#include "llvm/Support/Debug.h" 36c25e7581b9b8088910da31702d4ca21c4734c6d7Torok Edwin#include "llvm/Support/ErrorHandling.h" 3740a5eb18b031fa1a5e9697e21e251e613d441cc5Bill Wendling#include "llvm/ADT/STLExtras.h" 3822fee2dff4c43b551aefa44a96ca74fcade6bfacEvan Cheng 394db3cffe94a5285239cc0056f939c6b74a5ca0b6Evan Cheng#define GET_INSTRINFO_CTOR 4022fee2dff4c43b551aefa44a96ca74fcade6bfacEvan Cheng#include "ARMGenInstrInfo.inc" 4122fee2dff4c43b551aefa44a96ca74fcade6bfacEvan Cheng 42334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinusing namespace llvm; 43334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 44334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinstatic cl::opt<bool> 45334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinEnableARM3Addr("enable-arm-3-addr-conv", cl::Hidden, 46334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin cl::desc("Enable ARM 2-addr to 3-addr conv")); 47334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 4861545829832ba0375249c42c84843d0b62c8f55fJakob Stoklund Olesenstatic cl::opt<bool> 493805d85e38c29d9106c758b63851eb847201f315Jakob Stoklund OlesenWidenVMOVS("widen-vmovs", cl::Hidden, cl::init(true), 5061545829832ba0375249c42c84843d0b62c8f55fJakob Stoklund Olesen cl::desc("Widen ARM vmovs to vmovd when possible")); 5161545829832ba0375249c42c84843d0b62c8f55fJakob Stoklund Olesen 52eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilsonstatic cl::opt<unsigned> 53eb1641d54a7eda7717304bc4d55d059208d8ebedBob WilsonSwiftPartialUpdateClearance("swift-partial-update-clearance", 54eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson cl::Hidden, cl::init(12), 55eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson cl::desc("Clearance before partial register updates")); 56eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson 5748575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng/// ARM_MLxEntry - Record information about MLA / MLS instructions. 5848575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Chengstruct ARM_MLxEntry { 59cd2859eef83708c00330c94f6842499b48d5ed02Craig Topper uint16_t MLxOpc; // MLA / MLS opcode 60cd2859eef83708c00330c94f6842499b48d5ed02Craig Topper uint16_t MulOpc; // Expanded multiplication opcode 61cd2859eef83708c00330c94f6842499b48d5ed02Craig Topper uint16_t AddSubOpc; // Expanded add / sub opcode 6248575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng bool NegAcc; // True if the acc is negated before the add / sub. 6348575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng bool HasLane; // True if instruction has an extra "lane" operand. 6448575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng}; 6548575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng 6648575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Chengstatic const ARM_MLxEntry ARM_MLxTable[] = { 6748575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng // MLxOpc, MulOpc, AddSubOpc, NegAcc, HasLane 6848575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng // fp scalar ops 6948575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng { ARM::VMLAS, ARM::VMULS, ARM::VADDS, false, false }, 7048575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng { ARM::VMLSS, ARM::VMULS, ARM::VSUBS, false, false }, 7148575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng { ARM::VMLAD, ARM::VMULD, ARM::VADDD, false, false }, 7248575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng { ARM::VMLSD, ARM::VMULD, ARM::VSUBD, false, false }, 7348575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng { ARM::VNMLAS, ARM::VNMULS, ARM::VSUBS, true, false }, 7448575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng { ARM::VNMLSS, ARM::VMULS, ARM::VSUBS, true, false }, 7548575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng { ARM::VNMLAD, ARM::VNMULD, ARM::VSUBD, true, false }, 7648575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng { ARM::VNMLSD, ARM::VMULD, ARM::VSUBD, true, false }, 7748575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng 7848575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng // fp SIMD ops 7948575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng { ARM::VMLAfd, ARM::VMULfd, ARM::VADDfd, false, false }, 8048575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng { ARM::VMLSfd, ARM::VMULfd, ARM::VSUBfd, false, false }, 8148575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng { ARM::VMLAfq, ARM::VMULfq, ARM::VADDfq, false, false }, 8248575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng { ARM::VMLSfq, ARM::VMULfq, ARM::VSUBfq, false, false }, 8348575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng { ARM::VMLAslfd, ARM::VMULslfd, ARM::VADDfd, false, true }, 8448575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng { ARM::VMLSslfd, ARM::VMULslfd, ARM::VSUBfd, false, true }, 8548575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng { ARM::VMLAslfq, ARM::VMULslfq, ARM::VADDfq, false, true }, 8648575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng { ARM::VMLSslfq, ARM::VMULslfq, ARM::VSUBfq, false, true }, 8748575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng}; 8848575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng 89f95215f551949d5e5adfbf4753aa833b9009b77aAnton KorobeynikovARMBaseInstrInfo::ARMBaseInstrInfo(const ARMSubtarget& STI) 904db3cffe94a5285239cc0056f939c6b74a5ca0b6Evan Cheng : ARMGenInstrInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP), 91f95215f551949d5e5adfbf4753aa833b9009b77aAnton Korobeynikov Subtarget(STI) { 9248575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng for (unsigned i = 0, e = array_lengthof(ARM_MLxTable); i != e; ++i) { 9348575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng if (!MLxEntryMap.insert(std::make_pair(ARM_MLxTable[i].MLxOpc, i)).second) 9448575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng assert(false && "Duplicated entries?"); 9548575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng MLxHazardOpcodes.insert(ARM_MLxTable[i].AddSubOpc); 9648575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng MLxHazardOpcodes.insert(ARM_MLxTable[i].MulOpc); 9748575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng } 9848575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng} 9948575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng 1002da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick// Use a ScoreboardHazardRecognizer for prepass ARM scheduling. TargetInstrImpl 1012da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick// currently defaults to no prepass hazard recognizer. 10248575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan ChengScheduleHazardRecognizer *ARMBaseInstrInfo:: 1032da8bc8a5f7705ac131184cd247f48500da0d74eAndrew TrickCreateTargetHazardRecognizer(const TargetMachine *TM, 1042da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick const ScheduleDAG *DAG) const { 105c8bfd1d78ff9a307d1d4cb57cce4549b538e60f4Andrew Trick if (usePreRAHazardRecognizer()) { 1062da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick const InstrItineraryData *II = TM->getInstrItineraryData(); 1072da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick return new ScoreboardHazardRecognizer(II, DAG, "pre-RA-sched"); 1082da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick } 1092da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick return TargetInstrInfoImpl::CreateTargetHazardRecognizer(TM, DAG); 1102da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick} 1112da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick 1122da8bc8a5f7705ac131184cd247f48500da0d74eAndrew TrickScheduleHazardRecognizer *ARMBaseInstrInfo:: 1132da8bc8a5f7705ac131184cd247f48500da0d74eAndrew TrickCreateTargetPostRAHazardRecognizer(const InstrItineraryData *II, 1142da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick const ScheduleDAG *DAG) const { 11548575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng if (Subtarget.isThumb2() || Subtarget.hasVFP2()) 11648575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng return (ScheduleHazardRecognizer *) 1172da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick new ARMHazardRecognizer(II, *this, getRegisterInfo(), Subtarget, DAG); 1182da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick return TargetInstrInfoImpl::CreateTargetPostRAHazardRecognizer(II, DAG); 119334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 120334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 121334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinMachineInstr * 122334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinARMBaseInstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI, 123334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineBasicBlock::iterator &MBBI, 124334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin LiveVariables *LV) const { 12578703ddafe3d037f75d8ca188e4829d238289ac3Evan Cheng // FIXME: Thumb2 support. 12678703ddafe3d037f75d8ca188e4829d238289ac3Evan Cheng 127334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (!EnableARM3Addr) 128334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return NULL; 129334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 130334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineInstr *MI = MBBI; 131334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineFunction &MF = *MI->getParent()->getParent(); 13299405df044f2c584242e711cc9023ec90356da82Bruno Cardoso Lopes uint64_t TSFlags = MI->getDesc().TSFlags; 133334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool isPre = false; 134334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin switch ((TSFlags & ARMII::IndexModeMask) >> ARMII::IndexModeShift) { 135334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin default: return NULL; 136334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMII::IndexModePre: 137334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin isPre = true; 138334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin break; 139334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMII::IndexModePost: 140334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin break; 141334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 142334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 143334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Try splitting an indexed load/store to an un-indexed one plus an add/sub 144334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // operation. 145334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned MemOpc = getUnindexedOpcode(MI->getOpcode()); 146334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (MemOpc == 0) 147334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return NULL; 148334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 149334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineInstr *UpdateMI = NULL; 150334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineInstr *MemMI = NULL; 151334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned AddrMode = (TSFlags & ARMII::AddrModeMask); 152e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng const MCInstrDesc &MCID = MI->getDesc(); 153e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng unsigned NumOps = MCID.getNumOperands(); 1545a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng bool isLoad = !MI->mayStore(); 155334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const MachineOperand &WB = isLoad ? MI->getOperand(1) : MI->getOperand(0); 156334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const MachineOperand &Base = MI->getOperand(2); 157334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const MachineOperand &Offset = MI->getOperand(NumOps-3); 158334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned WBReg = WB.getReg(); 159334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned BaseReg = Base.getReg(); 160334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned OffReg = Offset.getReg(); 161334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned OffImm = MI->getOperand(NumOps-2).getImm(); 162334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin ARMCC::CondCodes Pred = (ARMCC::CondCodes)MI->getOperand(NumOps-1).getImm(); 163334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin switch (AddrMode) { 164bc2198133a1836598b54b943420748e75d5dea94Craig Topper default: llvm_unreachable("Unknown indexed op!"); 165334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMII::AddrMode2: { 166334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool isSub = ARM_AM::getAM2Op(OffImm) == ARM_AM::sub; 167334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned Amt = ARM_AM::getAM2Offset(OffImm); 168334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (OffReg == 0) { 169e7cbe4118b7ddf05032ff8772a98c51e1637bb5cEvan Cheng if (ARM_AM::getSOImmVal(Amt) == -1) 170334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Can't encode it in a so_imm operand. This transformation will 171334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // add more than 1 instruction. Abandon! 172334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return NULL; 173334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin UpdateMI = BuildMI(MF, MI->getDebugLoc(), 17478703ddafe3d037f75d8ca188e4829d238289ac3Evan Cheng get(isSub ? ARM::SUBri : ARM::ADDri), WBReg) 175e7cbe4118b7ddf05032ff8772a98c51e1637bb5cEvan Cheng .addReg(BaseReg).addImm(Amt) 176334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addImm(Pred).addReg(0).addReg(0); 177334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } else if (Amt != 0) { 178334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin ARM_AM::ShiftOpc ShOpc = ARM_AM::getAM2ShiftOpc(OffImm); 179334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned SOOpc = ARM_AM::getSORegOpc(ShOpc, Amt); 180334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin UpdateMI = BuildMI(MF, MI->getDebugLoc(), 18192a202213bb4c20301abf6ab64e46df3695e60bfOwen Anderson get(isSub ? ARM::SUBrsi : ARM::ADDrsi), WBReg) 182334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(BaseReg).addReg(OffReg).addReg(0).addImm(SOOpc) 183334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addImm(Pred).addReg(0).addReg(0); 184334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } else 185334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin UpdateMI = BuildMI(MF, MI->getDebugLoc(), 18678703ddafe3d037f75d8ca188e4829d238289ac3Evan Cheng get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg) 187334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(BaseReg).addReg(OffReg) 188334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addImm(Pred).addReg(0).addReg(0); 189334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin break; 190334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 191334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMII::AddrMode3 : { 192334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool isSub = ARM_AM::getAM3Op(OffImm) == ARM_AM::sub; 193334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned Amt = ARM_AM::getAM3Offset(OffImm); 194334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (OffReg == 0) 195334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Immediate is 8-bits. It's guaranteed to fit in a so_imm operand. 196334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin UpdateMI = BuildMI(MF, MI->getDebugLoc(), 19778703ddafe3d037f75d8ca188e4829d238289ac3Evan Cheng get(isSub ? ARM::SUBri : ARM::ADDri), WBReg) 198334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(BaseReg).addImm(Amt) 199334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addImm(Pred).addReg(0).addReg(0); 200334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin else 201334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin UpdateMI = BuildMI(MF, MI->getDebugLoc(), 20278703ddafe3d037f75d8ca188e4829d238289ac3Evan Cheng get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg) 203334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(BaseReg).addReg(OffReg) 204334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addImm(Pred).addReg(0).addReg(0); 205334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin break; 206334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 207334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 208334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 209334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin std::vector<MachineInstr*> NewMIs; 210334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (isPre) { 211334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (isLoad) 212334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MemMI = BuildMI(MF, MI->getDebugLoc(), 213334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin get(MemOpc), MI->getOperand(0).getReg()) 2143e5561247202bae994dd259a2d8dc4eff8f799f3Jim Grosbach .addReg(WBReg).addImm(0).addImm(Pred); 215334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin else 216334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MemMI = BuildMI(MF, MI->getDebugLoc(), 217334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin get(MemOpc)).addReg(MI->getOperand(1).getReg()) 218334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(WBReg).addReg(0).addImm(0).addImm(Pred); 219334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin NewMIs.push_back(MemMI); 220334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin NewMIs.push_back(UpdateMI); 221334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } else { 222334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (isLoad) 223334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MemMI = BuildMI(MF, MI->getDebugLoc(), 224334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin get(MemOpc), MI->getOperand(0).getReg()) 2253e5561247202bae994dd259a2d8dc4eff8f799f3Jim Grosbach .addReg(BaseReg).addImm(0).addImm(Pred); 226334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin else 227334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MemMI = BuildMI(MF, MI->getDebugLoc(), 228334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin get(MemOpc)).addReg(MI->getOperand(1).getReg()) 229334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred); 230334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (WB.isDead()) 231334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin UpdateMI->getOperand(0).setIsDead(); 232334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin NewMIs.push_back(UpdateMI); 233334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin NewMIs.push_back(MemMI); 234334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 235334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 236334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Transfer LiveVariables states, kill / dead info. 237334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (LV) { 238334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 239334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineOperand &MO = MI->getOperand(i); 240c9df025e33ac435adb3b3318d237c36ca7cec659Jakob Stoklund Olesen if (MO.isReg() && TargetRegisterInfo::isVirtualRegister(MO.getReg())) { 241334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned Reg = MO.getReg(); 242334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 243334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin LiveVariables::VarInfo &VI = LV->getVarInfo(Reg); 244334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (MO.isDef()) { 245334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineInstr *NewMI = (Reg == WBReg) ? UpdateMI : MemMI; 246334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (MO.isDead()) 247334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin LV->addVirtualRegisterDead(Reg, NewMI); 248334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 249334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (MO.isUse() && MO.isKill()) { 250334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin for (unsigned j = 0; j < 2; ++j) { 251334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Look at the two new MI's in reverse order. 252334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineInstr *NewMI = NewMIs[j]; 253334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (!NewMI->readsRegister(Reg)) 254334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin continue; 255334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin LV->addVirtualRegisterKilled(Reg, NewMI); 256334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (VI.removeKill(MI)) 257334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin VI.Kills.push_back(NewMI); 258334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin break; 259334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 260334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 261334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 262334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 263334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 264334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 265334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MFI->insert(MBBI, NewMIs[1]); 266334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MFI->insert(MBBI, NewMIs[0]); 267334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return NewMIs[0]; 268334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 269334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 270334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// Branch analysis. 271334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinbool 272334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinARMBaseInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB, 273334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineBasicBlock *&FBB, 274334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin SmallVectorImpl<MachineOperand> &Cond, 275334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool AllowModify) const { 276334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // If the block has no terminators, it just falls into the block after it. 277334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineBasicBlock::iterator I = MBB.end(); 27893d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen if (I == MBB.begin()) 27993d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen return false; 28093d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen --I; 28193d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen while (I->isDebugValue()) { 28293d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen if (I == MBB.begin()) 28393d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen return false; 28493d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen --I; 28593d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen } 28693d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen if (!isUnpredicatedTerminator(I)) 287334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 288334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 289334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Get the last instruction in the block. 290334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineInstr *LastInst = I; 291334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 292334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // If there is only one terminator instruction, process it. 293334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned LastOpc = LastInst->getOpcode(); 294334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) { 2955ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng if (isUncondBranchOpcode(LastOpc)) { 296334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin TBB = LastInst->getOperand(0).getMBB(); 297334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 298334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 2995ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng if (isCondBranchOpcode(LastOpc)) { 300334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Block ends with fall-through condbranch. 301334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin TBB = LastInst->getOperand(0).getMBB(); 302334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin Cond.push_back(LastInst->getOperand(1)); 303334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin Cond.push_back(LastInst->getOperand(2)); 304334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 305334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 306334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; // Can't handle indirect branch. 307334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 308334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 309334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Get the instruction before it if it is a terminator. 310334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineInstr *SecondLastInst = I; 311108c8724663354050dc09bb1262c3e4511adf82fEvan Cheng unsigned SecondLastOpc = SecondLastInst->getOpcode(); 312108c8724663354050dc09bb1262c3e4511adf82fEvan Cheng 313108c8724663354050dc09bb1262c3e4511adf82fEvan Cheng // If AllowModify is true and the block ends with two or more unconditional 314108c8724663354050dc09bb1262c3e4511adf82fEvan Cheng // branches, delete all but the first unconditional branch. 315108c8724663354050dc09bb1262c3e4511adf82fEvan Cheng if (AllowModify && isUncondBranchOpcode(LastOpc)) { 316108c8724663354050dc09bb1262c3e4511adf82fEvan Cheng while (isUncondBranchOpcode(SecondLastOpc)) { 317108c8724663354050dc09bb1262c3e4511adf82fEvan Cheng LastInst->eraseFromParent(); 318108c8724663354050dc09bb1262c3e4511adf82fEvan Cheng LastInst = SecondLastInst; 319108c8724663354050dc09bb1262c3e4511adf82fEvan Cheng LastOpc = LastInst->getOpcode(); 320676e258366dd17a0b4ee6ac66914237ce181202eEvan Cheng if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) { 321676e258366dd17a0b4ee6ac66914237ce181202eEvan Cheng // Return now the only terminator is an unconditional branch. 322676e258366dd17a0b4ee6ac66914237ce181202eEvan Cheng TBB = LastInst->getOperand(0).getMBB(); 323676e258366dd17a0b4ee6ac66914237ce181202eEvan Cheng return false; 324676e258366dd17a0b4ee6ac66914237ce181202eEvan Cheng } else { 325108c8724663354050dc09bb1262c3e4511adf82fEvan Cheng SecondLastInst = I; 326108c8724663354050dc09bb1262c3e4511adf82fEvan Cheng SecondLastOpc = SecondLastInst->getOpcode(); 327108c8724663354050dc09bb1262c3e4511adf82fEvan Cheng } 328108c8724663354050dc09bb1262c3e4511adf82fEvan Cheng } 329108c8724663354050dc09bb1262c3e4511adf82fEvan Cheng } 330334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 331334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // If there are three terminators, we don't know what sort of block this is. 332334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(--I)) 333334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; 334334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 3355ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng // If the block ends with a B and a Bcc, handle it. 3365ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng if (isCondBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) { 337334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin TBB = SecondLastInst->getOperand(0).getMBB(); 338334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin Cond.push_back(SecondLastInst->getOperand(1)); 339334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin Cond.push_back(SecondLastInst->getOperand(2)); 340334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin FBB = LastInst->getOperand(0).getMBB(); 341334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 342334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 343334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 344334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // If the block ends with two unconditional branches, handle it. The second 345334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // one is not executed, so remove it. 3465ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng if (isUncondBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) { 347334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin TBB = SecondLastInst->getOperand(0).getMBB(); 348334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin I = LastInst; 349334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (AllowModify) 350334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin I->eraseFromParent(); 351334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 352334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 353334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 354334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // ...likewise if it ends with a branch table followed by an unconditional 355334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // branch. The branch folder can create these, and we must get rid of them for 356334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // correctness of Thumb constant islands. 3578d4de5abfa1bcd974554ea14904ebf7af289e84dBob Wilson if ((isJumpTableBranchOpcode(SecondLastOpc) || 3588d4de5abfa1bcd974554ea14904ebf7af289e84dBob Wilson isIndirectBranchOpcode(SecondLastOpc)) && 3595ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng isUncondBranchOpcode(LastOpc)) { 360334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin I = LastInst; 361334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (AllowModify) 362334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin I->eraseFromParent(); 363334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; 364334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 365334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 366334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Otherwise, can't handle this. 367334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; 368334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 369334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 370334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 371334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinunsigned ARMBaseInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const { 372334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineBasicBlock::iterator I = MBB.end(); 373334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (I == MBB.begin()) return 0; 374334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin --I; 37593d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen while (I->isDebugValue()) { 37693d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen if (I == MBB.begin()) 37793d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen return 0; 37893d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen --I; 37993d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen } 3805ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng if (!isUncondBranchOpcode(I->getOpcode()) && 3815ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng !isCondBranchOpcode(I->getOpcode())) 382334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 0; 383334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 384334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Remove the branch. 385334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin I->eraseFromParent(); 386334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 387334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin I = MBB.end(); 388334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 389334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (I == MBB.begin()) return 1; 390334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin --I; 3915ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng if (!isCondBranchOpcode(I->getOpcode())) 392334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 1; 393334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 394334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Remove the branch. 395334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin I->eraseFromParent(); 396334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 2; 397334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 398334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 399334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinunsigned 400334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinARMBaseInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 4013bf912593301152b65accb9d9c37a95172f1df5aStuart Hastings MachineBasicBlock *FBB, 4023bf912593301152b65accb9d9c37a95172f1df5aStuart Hastings const SmallVectorImpl<MachineOperand> &Cond, 4033bf912593301152b65accb9d9c37a95172f1df5aStuart Hastings DebugLoc DL) const { 4046495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ARMFunctionInfo *AFI = MBB.getParent()->getInfo<ARMFunctionInfo>(); 4056495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng int BOpc = !AFI->isThumbFunction() 4066495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ? ARM::B : (AFI->isThumb2Function() ? ARM::t2B : ARM::tB); 4076495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng int BccOpc = !AFI->isThumbFunction() 4086495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ? ARM::Bcc : (AFI->isThumb2Function() ? ARM::t2Bcc : ARM::tBcc); 40951f6a7abf27fc92c3d8904c2334feab8b498e8e9Owen Anderson bool isThumb = AFI->isThumbFunction() || AFI->isThumb2Function(); 410e23dc9c0ef50b0a1934c04c1786f3a0478d62f41Andrew Trick 411334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Shouldn't be a fall through. 412334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin assert(TBB && "InsertBranch must not be told to insert a fallthrough"); 413334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin assert((Cond.size() == 2 || Cond.size() == 0) && 414334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin "ARM branch conditions have two components!"); 415334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 416334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (FBB == 0) { 417112fb73502d54dd7dd61ae2de24c92d4df181294Owen Anderson if (Cond.empty()) { // Unconditional branch? 41851f6a7abf27fc92c3d8904c2334feab8b498e8e9Owen Anderson if (isThumb) 41951f6a7abf27fc92c3d8904c2334feab8b498e8e9Owen Anderson BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB).addImm(ARMCC::AL).addReg(0); 42051f6a7abf27fc92c3d8904c2334feab8b498e8e9Owen Anderson else 42151f6a7abf27fc92c3d8904c2334feab8b498e8e9Owen Anderson BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB); 422112fb73502d54dd7dd61ae2de24c92d4df181294Owen Anderson } else 4233bf912593301152b65accb9d9c37a95172f1df5aStuart Hastings BuildMI(&MBB, DL, get(BccOpc)).addMBB(TBB) 424334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()); 425334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 1; 426334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 427334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 428334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Two-way conditional branch. 4293bf912593301152b65accb9d9c37a95172f1df5aStuart Hastings BuildMI(&MBB, DL, get(BccOpc)).addMBB(TBB) 430334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()); 43151f6a7abf27fc92c3d8904c2334feab8b498e8e9Owen Anderson if (isThumb) 43251f6a7abf27fc92c3d8904c2334feab8b498e8e9Owen Anderson BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB).addImm(ARMCC::AL).addReg(0); 43351f6a7abf27fc92c3d8904c2334feab8b498e8e9Owen Anderson else 43451f6a7abf27fc92c3d8904c2334feab8b498e8e9Owen Anderson BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB); 435334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 2; 436334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 437334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 438334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinbool ARMBaseInstrInfo:: 439334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const { 440334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin ARMCC::CondCodes CC = (ARMCC::CondCodes)(int)Cond[0].getImm(); 441334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin Cond[0].setImm(ARMCC::getOppositeCondition(CC)); 442334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 443334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 444334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 445ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Chengbool ARMBaseInstrInfo::isPredicated(const MachineInstr *MI) const { 446ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng if (MI->isBundle()) { 447ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng MachineBasicBlock::const_instr_iterator I = MI; 448ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end(); 449ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng while (++I != E && I->isInsideBundle()) { 450ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng int PIdx = I->findFirstPredOperandIdx(); 451ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng if (PIdx != -1 && I->getOperand(PIdx).getImm() != ARMCC::AL) 452ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng return true; 453ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng } 454ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng return false; 455ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng } 456ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng 457ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng int PIdx = MI->findFirstPredOperandIdx(); 458ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng return PIdx != -1 && MI->getOperand(PIdx).getImm() != ARMCC::AL; 459ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng} 460ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng 461334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinbool ARMBaseInstrInfo:: 462334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinPredicateInstruction(MachineInstr *MI, 463334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const SmallVectorImpl<MachineOperand> &Pred) const { 464334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned Opc = MI->getOpcode(); 4655ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng if (isUncondBranchOpcode(Opc)) { 4665ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng MI->setDesc(get(getMatchingCondBranchOpcode(Opc))); 467334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI->addOperand(MachineOperand::CreateImm(Pred[0].getImm())); 468334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI->addOperand(MachineOperand::CreateReg(Pred[1].getReg(), false)); 469334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; 470334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 471334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 472334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin int PIdx = MI->findFirstPredOperandIdx(); 473334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (PIdx != -1) { 474334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineOperand &PMO = MI->getOperand(PIdx); 475334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin PMO.setImm(Pred[0].getImm()); 476334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI->getOperand(PIdx+1).setReg(Pred[1].getReg()); 477334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; 478334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 479334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 480334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 481334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 482334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinbool ARMBaseInstrInfo:: 483334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinSubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1, 484334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const SmallVectorImpl<MachineOperand> &Pred2) const { 485334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (Pred1.size() > 2 || Pred2.size() > 2) 486334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 487334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 488334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin ARMCC::CondCodes CC1 = (ARMCC::CondCodes)Pred1[0].getImm(); 489334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin ARMCC::CondCodes CC2 = (ARMCC::CondCodes)Pred2[0].getImm(); 490334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (CC1 == CC2) 491334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; 492334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 493334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin switch (CC1) { 494334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin default: 495334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 496334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMCC::AL: 497334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; 498334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMCC::HS: 499334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return CC2 == ARMCC::HI; 500334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMCC::LS: 501334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return CC2 == ARMCC::LO || CC2 == ARMCC::EQ; 502334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMCC::GE: 503334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return CC2 == ARMCC::GT; 504334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMCC::LE: 505334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return CC2 == ARMCC::LT; 506334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 507334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 508334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 509334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinbool ARMBaseInstrInfo::DefinesPredicate(MachineInstr *MI, 510334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin std::vector<MachineOperand> &Pred) const { 511334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool Found = false; 512334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 513334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const MachineOperand &MO = MI->getOperand(i); 5142420b558de5d291d8503c1339004e5b5bf99a48aJakob Stoklund Olesen if ((MO.isRegMask() && MO.clobbersPhysReg(ARM::CPSR)) || 5152420b558de5d291d8503c1339004e5b5bf99a48aJakob Stoklund Olesen (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR)) { 516334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin Pred.push_back(MO); 517334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin Found = true; 518334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 519334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 520334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 521334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return Found; 522334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 523334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 524ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng/// isPredicable - Return true if the specified instruction can be predicated. 525ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng/// By default, this returns true for every instruction with a 526ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng/// PredicateOperand. 527ac0869dc8a7986855c5557cc67d4709600158ef5Evan Chengbool ARMBaseInstrInfo::isPredicable(MachineInstr *MI) const { 5285a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng if (!MI->isPredicable()) 529ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng return false; 530ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng 5315a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng if ((MI->getDesc().TSFlags & ARMII::DomainMask) == ARMII::DomainNEON) { 532ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng ARMFunctionInfo *AFI = 533ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng MI->getParent()->getParent()->getInfo<ARMFunctionInfo>(); 534d7f0810c934a7d13acb28c42d737ce58ec990ea8Evan Cheng return AFI->isThumb2Function(); 535ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng } 536ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng return true; 537ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng} 538334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 53956856b1f46ec1f073ceef4e826c544b8b1691608Chris Lattner/// FIXME: Works around a gcc miscompilation with -fstrict-aliasing. 54019e57025d458d3cb50804fd821fd89b868a819bdChandler CarruthLLVM_ATTRIBUTE_NOINLINE 541334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinstatic unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT, 54256856b1f46ec1f073ceef4e826c544b8b1691608Chris Lattner unsigned JTI); 543334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinstatic unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT, 544334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned JTI) { 54556856b1f46ec1f073ceef4e826c544b8b1691608Chris Lattner assert(JTI < JT.size()); 546334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return JT[JTI].MBBs.size(); 547334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 548334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 549334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin/// GetInstSize - Return the size of the specified MachineInstr. 550334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin/// 551334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinunsigned ARMBaseInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const { 552334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const MachineBasicBlock &MBB = *MI->getParent(); 553334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const MachineFunction *MF = MBB.getParent(); 55433adcfb4d217f5f23d9bde8ba02b8e48f9605fc5Chris Lattner const MCAsmInfo *MAI = MF->getTarget().getMCAsmInfo(); 555334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 556e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng const MCInstrDesc &MCID = MI->getDesc(); 55716884415db751c75f2133bd04921393c792b1158Owen Anderson if (MCID.getSize()) 55816884415db751c75f2133bd04921393c792b1158Owen Anderson return MCID.getSize(); 559334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 5604d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie // If this machine instr is an inline asm, measure it. 5614d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie if (MI->getOpcode() == ARM::INLINEASM) 5624d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie return getInlineAsmLength(MI->getOperand(0).getSymbolName(), *MAI); 5634d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie if (MI->isLabel()) 5644d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie return 0; 5654d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie unsigned Opc = MI->getOpcode(); 5664d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie switch (Opc) { 5674d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie case TargetOpcode::IMPLICIT_DEF: 5684d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie case TargetOpcode::KILL: 5694d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie case TargetOpcode::PROLOG_LABEL: 5704d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie case TargetOpcode::EH_LABEL: 5714d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie case TargetOpcode::DBG_VALUE: 5724d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie return 0; 5734d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie case TargetOpcode::BUNDLE: 5744d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie return getInstBundleLength(MI); 5754d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie case ARM::MOVi16_ga_pcrel: 5764d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie case ARM::MOVTi16_ga_pcrel: 5774d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie case ARM::t2MOVi16_ga_pcrel: 5784d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie case ARM::t2MOVTi16_ga_pcrel: 5794d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie return 4; 5804d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie case ARM::MOVi32imm: 5814d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie case ARM::t2MOVi32imm: 5824d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie return 8; 5834d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie case ARM::CONSTPOOL_ENTRY: 5844d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie // If this machine instr is a constant pool entry, its size is recorded as 5854d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie // operand #2. 5864d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie return MI->getOperand(2).getImm(); 5874d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie case ARM::Int_eh_sjlj_longjmp: 5884d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie return 16; 5894d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie case ARM::tInt_eh_sjlj_longjmp: 5904d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie return 10; 5914d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie case ARM::Int_eh_sjlj_setjmp: 5924d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie case ARM::Int_eh_sjlj_setjmp_nofp: 5934d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie return 20; 5944d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie case ARM::tInt_eh_sjlj_setjmp: 5954d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie case ARM::t2Int_eh_sjlj_setjmp: 5964d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie case ARM::t2Int_eh_sjlj_setjmp_nofp: 5974d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie return 12; 5984d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie case ARM::BR_JTr: 5994d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie case ARM::BR_JTm: 6004d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie case ARM::BR_JTadd: 6014d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie case ARM::tBR_JTr: 6024d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie case ARM::t2BR_JT: 6034d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie case ARM::t2TBB_JT: 6044d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie case ARM::t2TBH_JT: { 6054d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie // These are jumptable branches, i.e. a branch followed by an inlined 6064d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie // jumptable. The size is 4 + 4 * number of entries. For TBB, each 6074d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie // entry is one byte; TBH two byte each. 6084d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie unsigned EntrySize = (Opc == ARM::t2TBB_JT) 6094d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie ? 1 : ((Opc == ARM::t2TBH_JT) ? 2 : 4); 6104d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie unsigned NumOps = MCID.getNumOperands(); 6114d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie MachineOperand JTOP = 6124d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie MI->getOperand(NumOps - (MI->isPredicable() ? 3 : 2)); 6134d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie unsigned JTI = JTOP.getIndex(); 6144d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo(); 6154d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie assert(MJTI != 0); 6164d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables(); 6174d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie assert(JTI < JT.size()); 6184d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie // Thumb instructions are 2 byte aligned, but JT entries are 4 byte 6194d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie // 4 aligned. The assembler / linker may add 2 byte padding just before 6204d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie // the JT entries. The size does not include this padding; the 6214d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie // constant islands pass does separate bookkeeping for it. 6224d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie // FIXME: If we know the size of the function is less than (1 << 16) *2 6234d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie // bytes, we can use 16-bit entries instead. Then there won't be an 6244d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie // alignment issue. 6254d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie unsigned InstSize = (Opc == ARM::tBR_JTr || Opc == ARM::t2BR_JT) ? 2 : 4; 6264d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie unsigned NumEntries = getNumJTEntries(JT, JTI); 6274d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie if (Opc == ARM::t2TBB_JT && (NumEntries & 1)) 6284d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie // Make sure the instruction that follows TBB is 2-byte aligned. 6294d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie // FIXME: Constant island pass should insert an "ALIGN" instruction 6304d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie // instead. 6314d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie ++NumEntries; 6324d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie return NumEntries * EntrySize + InstSize; 6334d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie } 6344d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie default: 6354d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie // Otherwise, pseudo-instruction sizes are zero. 6364d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie return 0; 6374d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie } 638334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 639334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 640ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Chengunsigned ARMBaseInstrInfo::getInstBundleLength(const MachineInstr *MI) const { 641ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng unsigned Size = 0; 642ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng MachineBasicBlock::const_instr_iterator I = MI; 643ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end(); 644ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng while (++I != E && I->isInsideBundle()) { 645ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng assert(!I->isBundle() && "No nested bundle!"); 646ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng Size += GetInstSizeInBytes(&*I); 647ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng } 648ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng return Size; 649ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng} 650ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng 651ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesenvoid ARMBaseInstrInfo::copyPhysReg(MachineBasicBlock &MBB, 652ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen MachineBasicBlock::iterator I, DebugLoc DL, 653ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen unsigned DestReg, unsigned SrcReg, 654ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen bool KillSrc) const { 655ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen bool GPRDest = ARM::GPRRegClass.contains(DestReg); 656ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen bool GPRSrc = ARM::GPRRegClass.contains(SrcReg); 657ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen 658ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen if (GPRDest && GPRSrc) { 659ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen AddDefaultCC(AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::MOVr), DestReg) 660ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen .addReg(SrcReg, getKillRegState(KillSrc)))); 661ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen return; 6627bfdca0206f51132b26094c6f83a5ac97ee0f943David Goodwin } 663334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 664ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen bool SPRDest = ARM::SPRRegClass.contains(DestReg); 665ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen bool SPRSrc = ARM::SPRRegClass.contains(SrcReg); 666ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen 667e5038e191db82d4d92fdeec1b5bce5cae21f6d8fChad Rosier unsigned Opc = 0; 668142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen if (SPRDest && SPRSrc) 669ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen Opc = ARM::VMOVS; 670142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen else if (GPRDest && SPRSrc) 671ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen Opc = ARM::VMOVRS; 672ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen else if (SPRDest && GPRSrc) 673ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen Opc = ARM::VMOVSR; 674ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen else if (ARM::DPRRegClass.contains(DestReg, SrcReg)) 675ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen Opc = ARM::VMOVD; 676ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen else if (ARM::QPRRegClass.contains(DestReg, SrcReg)) 67743967a97cf9a296623e1cf5ed643e2f40b7e5766Owen Anderson Opc = ARM::VORRq; 678e5038e191db82d4d92fdeec1b5bce5cae21f6d8fChad Rosier 679e5038e191db82d4d92fdeec1b5bce5cae21f6d8fChad Rosier if (Opc) { 680e5038e191db82d4d92fdeec1b5bce5cae21f6d8fChad Rosier MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc), DestReg); 68143967a97cf9a296623e1cf5ed643e2f40b7e5766Owen Anderson MIB.addReg(SrcReg, getKillRegState(KillSrc)); 682e5038e191db82d4d92fdeec1b5bce5cae21f6d8fChad Rosier if (Opc == ARM::VORRq) 683e5038e191db82d4d92fdeec1b5bce5cae21f6d8fChad Rosier MIB.addReg(SrcReg, getKillRegState(KillSrc)); 684fea95c6bade86fcfa5bd07efdda9bd902f53be8cChad Rosier AddDefaultPred(MIB); 685e5038e191db82d4d92fdeec1b5bce5cae21f6d8fChad Rosier return; 686e5038e191db82d4d92fdeec1b5bce5cae21f6d8fChad Rosier } 687e5038e191db82d4d92fdeec1b5bce5cae21f6d8fChad Rosier 68885bdf2e76a0351468f231f48069c64bc6938f140Jakob Stoklund Olesen // Handle register classes that require multiple instructions. 68985bdf2e76a0351468f231f48069c64bc6938f140Jakob Stoklund Olesen unsigned BeginIdx = 0; 69085bdf2e76a0351468f231f48069c64bc6938f140Jakob Stoklund Olesen unsigned SubRegs = 0; 6917611a88b58e0a6960cdb5c72dc18a6c93e44cdc2Andrew Trick int Spacing = 1; 69285bdf2e76a0351468f231f48069c64bc6938f140Jakob Stoklund Olesen 69385bdf2e76a0351468f231f48069c64bc6938f140Jakob Stoklund Olesen // Use VORRq when possible. 69485bdf2e76a0351468f231f48069c64bc6938f140Jakob Stoklund Olesen if (ARM::QQPRRegClass.contains(DestReg, SrcReg)) 69585bdf2e76a0351468f231f48069c64bc6938f140Jakob Stoklund Olesen Opc = ARM::VORRq, BeginIdx = ARM::qsub_0, SubRegs = 2; 69685bdf2e76a0351468f231f48069c64bc6938f140Jakob Stoklund Olesen else if (ARM::QQQQPRRegClass.contains(DestReg, SrcReg)) 69785bdf2e76a0351468f231f48069c64bc6938f140Jakob Stoklund Olesen Opc = ARM::VORRq, BeginIdx = ARM::qsub_0, SubRegs = 4; 69885bdf2e76a0351468f231f48069c64bc6938f140Jakob Stoklund Olesen // Fall back to VMOVD. 69985bdf2e76a0351468f231f48069c64bc6938f140Jakob Stoklund Olesen else if (ARM::DPairRegClass.contains(DestReg, SrcReg)) 70085bdf2e76a0351468f231f48069c64bc6938f140Jakob Stoklund Olesen Opc = ARM::VMOVD, BeginIdx = ARM::dsub_0, SubRegs = 2; 70185bdf2e76a0351468f231f48069c64bc6938f140Jakob Stoklund Olesen else if (ARM::DTripleRegClass.contains(DestReg, SrcReg)) 70285bdf2e76a0351468f231f48069c64bc6938f140Jakob Stoklund Olesen Opc = ARM::VMOVD, BeginIdx = ARM::dsub_0, SubRegs = 3; 70385bdf2e76a0351468f231f48069c64bc6938f140Jakob Stoklund Olesen else if (ARM::DQuadRegClass.contains(DestReg, SrcReg)) 70485bdf2e76a0351468f231f48069c64bc6938f140Jakob Stoklund Olesen Opc = ARM::VMOVD, BeginIdx = ARM::dsub_0, SubRegs = 4; 70585bdf2e76a0351468f231f48069c64bc6938f140Jakob Stoklund Olesen 70685bdf2e76a0351468f231f48069c64bc6938f140Jakob Stoklund Olesen else if (ARM::DPairSpcRegClass.contains(DestReg, SrcReg)) 70785bdf2e76a0351468f231f48069c64bc6938f140Jakob Stoklund Olesen Opc = ARM::VMOVD, BeginIdx = ARM::dsub_0, SubRegs = 2, Spacing = 2; 70885bdf2e76a0351468f231f48069c64bc6938f140Jakob Stoklund Olesen else if (ARM::DTripleSpcRegClass.contains(DestReg, SrcReg)) 70985bdf2e76a0351468f231f48069c64bc6938f140Jakob Stoklund Olesen Opc = ARM::VMOVD, BeginIdx = ARM::dsub_0, SubRegs = 3, Spacing = 2; 71085bdf2e76a0351468f231f48069c64bc6938f140Jakob Stoklund Olesen else if (ARM::DQuadSpcRegClass.contains(DestReg, SrcReg)) 71185bdf2e76a0351468f231f48069c64bc6938f140Jakob Stoklund Olesen Opc = ARM::VMOVD, BeginIdx = ARM::dsub_0, SubRegs = 4, Spacing = 2; 71285bdf2e76a0351468f231f48069c64bc6938f140Jakob Stoklund Olesen 7137611a88b58e0a6960cdb5c72dc18a6c93e44cdc2Andrew Trick assert(Opc && "Impossible reg-to-reg copy"); 714d79dedd458c1de07fbc568ea8c3b4194e94df48eAndrew Trick 715d79dedd458c1de07fbc568ea8c3b4194e94df48eAndrew Trick const TargetRegisterInfo *TRI = &getRegisterInfo(); 716d79dedd458c1de07fbc568ea8c3b4194e94df48eAndrew Trick MachineInstrBuilder Mov; 717f26e43df26bb7b0c7bf4853477e36611e2c90deaAndrew Trick 718f26e43df26bb7b0c7bf4853477e36611e2c90deaAndrew Trick // Copy register tuples backward when the first Dest reg overlaps with SrcReg. 719f26e43df26bb7b0c7bf4853477e36611e2c90deaAndrew Trick if (TRI->regsOverlap(SrcReg, TRI->getSubReg(DestReg, BeginIdx))) { 720f26e43df26bb7b0c7bf4853477e36611e2c90deaAndrew Trick BeginIdx = BeginIdx + ((SubRegs-1)*Spacing); 721f26e43df26bb7b0c7bf4853477e36611e2c90deaAndrew Trick Spacing = -Spacing; 722f26e43df26bb7b0c7bf4853477e36611e2c90deaAndrew Trick } 723f26e43df26bb7b0c7bf4853477e36611e2c90deaAndrew Trick#ifndef NDEBUG 724f26e43df26bb7b0c7bf4853477e36611e2c90deaAndrew Trick SmallSet<unsigned, 4> DstRegs; 725f26e43df26bb7b0c7bf4853477e36611e2c90deaAndrew Trick#endif 726d79dedd458c1de07fbc568ea8c3b4194e94df48eAndrew Trick for (unsigned i = 0; i != SubRegs; ++i) { 727d79dedd458c1de07fbc568ea8c3b4194e94df48eAndrew Trick unsigned Dst = TRI->getSubReg(DestReg, BeginIdx + i*Spacing); 728d79dedd458c1de07fbc568ea8c3b4194e94df48eAndrew Trick unsigned Src = TRI->getSubReg(SrcReg, BeginIdx + i*Spacing); 729d79dedd458c1de07fbc568ea8c3b4194e94df48eAndrew Trick assert(Dst && Src && "Bad sub-register"); 730f26e43df26bb7b0c7bf4853477e36611e2c90deaAndrew Trick#ifndef NDEBUG 731f26e43df26bb7b0c7bf4853477e36611e2c90deaAndrew Trick assert(!DstRegs.count(Src) && "destructive vector copy"); 7327611a88b58e0a6960cdb5c72dc18a6c93e44cdc2Andrew Trick DstRegs.insert(Dst); 733f26e43df26bb7b0c7bf4853477e36611e2c90deaAndrew Trick#endif 734d79dedd458c1de07fbc568ea8c3b4194e94df48eAndrew Trick Mov = BuildMI(MBB, I, I->getDebugLoc(), get(Opc), Dst) 735d79dedd458c1de07fbc568ea8c3b4194e94df48eAndrew Trick .addReg(Src); 736d79dedd458c1de07fbc568ea8c3b4194e94df48eAndrew Trick // VORR takes two source operands. 737d79dedd458c1de07fbc568ea8c3b4194e94df48eAndrew Trick if (Opc == ARM::VORRq) 738d79dedd458c1de07fbc568ea8c3b4194e94df48eAndrew Trick Mov.addReg(Src); 739d79dedd458c1de07fbc568ea8c3b4194e94df48eAndrew Trick Mov = AddDefaultPred(Mov); 740e5038e191db82d4d92fdeec1b5bce5cae21f6d8fChad Rosier } 741d79dedd458c1de07fbc568ea8c3b4194e94df48eAndrew Trick // Add implicit super-register defs and kills to the last instruction. 742d79dedd458c1de07fbc568ea8c3b4194e94df48eAndrew Trick Mov->addRegisterDefined(DestReg, TRI); 743d79dedd458c1de07fbc568ea8c3b4194e94df48eAndrew Trick if (KillSrc) 744d79dedd458c1de07fbc568ea8c3b4194e94df48eAndrew Trick Mov->addRegisterKilled(SrcReg, TRI); 745334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 746334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 747c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Chengstatic const 748c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan ChengMachineInstrBuilder &AddDReg(MachineInstrBuilder &MIB, 749c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Cheng unsigned Reg, unsigned SubIdx, unsigned State, 750c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Cheng const TargetRegisterInfo *TRI) { 751c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Cheng if (!SubIdx) 752c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Cheng return MIB.addReg(Reg, State); 753c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Cheng 754c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Cheng if (TargetRegisterInfo::isPhysicalRegister(Reg)) 755c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Cheng return MIB.addReg(TRI->getSubReg(Reg, SubIdx), State); 756c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Cheng return MIB.addReg(Reg, State, SubIdx); 757c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Cheng} 758c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Cheng 759334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinvoid ARMBaseInstrInfo:: 760334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinstoreRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 761334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned SrcReg, bool isKill, int FI, 762746ad69e088176819981b4b2c5ac8dcd49f5e60eEvan Cheng const TargetRegisterClass *RC, 763746ad69e088176819981b4b2c5ac8dcd49f5e60eEvan Cheng const TargetRegisterInfo *TRI) const { 764c7f3ace20c325521c68335a1689645b43b06ddf0Chris Lattner DebugLoc DL; 765334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (I != MBB.end()) DL = I->getDebugLoc(); 766249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MachineFunction &MF = *MBB.getParent(); 767249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MachineFrameInfo &MFI = *MF.getFrameInfo(); 76831bc849123011b8eae6bb3c79876d9a3c26a6a1dJim Grosbach unsigned Align = MFI.getObjectAlignment(FI); 769249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov 770249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MachineMemOperand *MMO = 771978e0dfe46e481bfb1281e683aa308329e879e95Jay Foad MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FI), 77259db5496f4fc2ef6111569e542f8b65480ef14c1Chris Lattner MachineMemOperand::MOStore, 773249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MFI.getObjectSize(FI), 77431bc849123011b8eae6bb3c79876d9a3c26a6a1dJim Grosbach Align); 775334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 776e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson switch (RC->getSize()) { 777e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson case 4: 778e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson if (ARM::GPRRegClass.hasSubClassEq(RC)) { 779e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::STRi12)) 780334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(SrcReg, getKillRegState(isKill)) 7817e3383c007f53b3a00675af225e428cb66ddf404Jim Grosbach .addFrameIndex(FI).addImm(0).addMemOperand(MMO)); 782e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson } else if (ARM::SPRRegClass.hasSubClassEq(RC)) { 783e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTRS)) 784d31c5496d7e1580058b5c6fbc8fd537a641ea590Evan Cheng .addReg(SrcReg, getKillRegState(isKill)) 785d31c5496d7e1580058b5c6fbc8fd537a641ea590Evan Cheng .addFrameIndex(FI).addImm(0).addMemOperand(MMO)); 786e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson } else 787e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson llvm_unreachable("Unknown reg class!"); 788e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson break; 789e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson case 8: 790e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson if (ARM::DPRRegClass.hasSubClassEq(RC)) { 791e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTRD)) 792334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(SrcReg, getKillRegState(isKill)) 793249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov .addFrameIndex(FI).addImm(0).addMemOperand(MMO)); 794e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson } else 795e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson llvm_unreachable("Unknown reg class!"); 796e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson break; 797e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson case 16: 7985b2f9136644c58ae32e00d8317540692a697d1c9Jakob Stoklund Olesen if (ARM::DPairRegClass.hasSubClassEq(RC)) { 7997255a4e1332ccb69918ebe041dff05f9e4e5815dJakob Stoklund Olesen // Use aligned spills if the stack can be realigned. 8007255a4e1332ccb69918ebe041dff05f9e4e5815dJakob Stoklund Olesen if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) { 80128f08c93e75d291695ea89b9004145103292e85bJim Grosbach AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1q64)) 802f967ca0eaf30325cabe3c1971bf0dba16cf1b027Bob Wilson .addFrameIndex(FI).addImm(16) 80369b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng .addReg(SrcReg, getKillRegState(isKill)) 80469b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng .addMemOperand(MMO)); 805e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson } else { 806e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMQIA)) 80769b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng .addReg(SrcReg, getKillRegState(isKill)) 80869b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng .addFrameIndex(FI) 80969b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng .addMemOperand(MMO)); 810e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson } 811e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson } else 812e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson llvm_unreachable("Unknown reg class!"); 813e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson break; 814b58d7d03125526c152ade0c75be302b3c9eab997Anton Korobeynikov case 24: 815b58d7d03125526c152ade0c75be302b3c9eab997Anton Korobeynikov if (ARM::DTripleRegClass.hasSubClassEq(RC)) { 816b58d7d03125526c152ade0c75be302b3c9eab997Anton Korobeynikov // Use aligned spills if the stack can be realigned. 817b58d7d03125526c152ade0c75be302b3c9eab997Anton Korobeynikov if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) { 818b58d7d03125526c152ade0c75be302b3c9eab997Anton Korobeynikov AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1d64TPseudo)) 819b58d7d03125526c152ade0c75be302b3c9eab997Anton Korobeynikov .addFrameIndex(FI).addImm(16) 820b58d7d03125526c152ade0c75be302b3c9eab997Anton Korobeynikov .addReg(SrcReg, getKillRegState(isKill)) 821b58d7d03125526c152ade0c75be302b3c9eab997Anton Korobeynikov .addMemOperand(MMO)); 822b58d7d03125526c152ade0c75be302b3c9eab997Anton Korobeynikov } else { 823b58d7d03125526c152ade0c75be302b3c9eab997Anton Korobeynikov MachineInstrBuilder MIB = 824b58d7d03125526c152ade0c75be302b3c9eab997Anton Korobeynikov AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMDIA)) 825b58d7d03125526c152ade0c75be302b3c9eab997Anton Korobeynikov .addFrameIndex(FI)) 826b58d7d03125526c152ade0c75be302b3c9eab997Anton Korobeynikov .addMemOperand(MMO); 827b58d7d03125526c152ade0c75be302b3c9eab997Anton Korobeynikov MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI); 828b58d7d03125526c152ade0c75be302b3c9eab997Anton Korobeynikov MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI); 829b58d7d03125526c152ade0c75be302b3c9eab997Anton Korobeynikov AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI); 830b58d7d03125526c152ade0c75be302b3c9eab997Anton Korobeynikov } 831b58d7d03125526c152ade0c75be302b3c9eab997Anton Korobeynikov } else 832b58d7d03125526c152ade0c75be302b3c9eab997Anton Korobeynikov llvm_unreachable("Unknown reg class!"); 833b58d7d03125526c152ade0c75be302b3c9eab997Anton Korobeynikov break; 834e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson case 32: 835b58d7d03125526c152ade0c75be302b3c9eab997Anton Korobeynikov if (ARM::QQPRRegClass.hasSubClassEq(RC) || ARM::DQuadRegClass.hasSubClassEq(RC)) { 836e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) { 837e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson // FIXME: It's possible to only store part of the QQ register if the 838e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson // spilled def has a sub-register index. 839e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1d64QPseudo)) 840168f382dc67e5940cabdb28dc933c4f91cdd3137Bob Wilson .addFrameIndex(FI).addImm(16) 841168f382dc67e5940cabdb28dc933c4f91cdd3137Bob Wilson .addReg(SrcReg, getKillRegState(isKill)) 842168f382dc67e5940cabdb28dc933c4f91cdd3137Bob Wilson .addMemOperand(MMO)); 843e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson } else { 844e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson MachineInstrBuilder MIB = 845e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMDIA)) 84673fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling .addFrameIndex(FI)) 847e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson .addMemOperand(MMO); 848e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI); 849e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI); 850e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI); 851e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI); 852e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson } 853e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson } else 854e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson llvm_unreachable("Unknown reg class!"); 855e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson break; 856e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson case 64: 857e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson if (ARM::QQQQPRRegClass.hasSubClassEq(RC)) { 858e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson MachineInstrBuilder MIB = 859e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMDIA)) 860e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson .addFrameIndex(FI)) 861e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson .addMemOperand(MMO); 862e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI); 863e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI); 864e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI); 865e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson MIB = AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI); 866e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson MIB = AddDReg(MIB, SrcReg, ARM::dsub_4, 0, TRI); 867e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson MIB = AddDReg(MIB, SrcReg, ARM::dsub_5, 0, TRI); 868e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson MIB = AddDReg(MIB, SrcReg, ARM::dsub_6, 0, TRI); 869e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson AddDReg(MIB, SrcReg, ARM::dsub_7, 0, TRI); 870e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson } else 871e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson llvm_unreachable("Unknown reg class!"); 872e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson break; 873e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson default: 874e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson llvm_unreachable("Unknown reg class!"); 875334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 876334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 877334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 87834327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesenunsigned 87934327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund OlesenARMBaseInstrInfo::isStoreToStackSlot(const MachineInstr *MI, 88034327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen int &FrameIndex) const { 88134327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen switch (MI->getOpcode()) { 88234327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen default: break; 8837e3383c007f53b3a00675af225e428cb66ddf404Jim Grosbach case ARM::STRrs: 88434327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen case ARM::t2STRs: // FIXME: don't use t2STRs to access frame. 88534327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen if (MI->getOperand(1).isFI() && 88634327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen MI->getOperand(2).isReg() && 88734327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen MI->getOperand(3).isImm() && 88834327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen MI->getOperand(2).getReg() == 0 && 88934327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen MI->getOperand(3).getImm() == 0) { 89034327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen FrameIndex = MI->getOperand(1).getIndex(); 89134327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen return MI->getOperand(0).getReg(); 89234327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen } 89334327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen break; 8947e3383c007f53b3a00675af225e428cb66ddf404Jim Grosbach case ARM::STRi12: 89534327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen case ARM::t2STRi12: 89674472b4bf963c424da04f42dffdb94c85ef964bcJim Grosbach case ARM::tSTRspi: 89734327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen case ARM::VSTRD: 89834327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen case ARM::VSTRS: 89934327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen if (MI->getOperand(1).isFI() && 90034327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen MI->getOperand(2).isImm() && 90134327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen MI->getOperand(2).getImm() == 0) { 90234327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen FrameIndex = MI->getOperand(1).getIndex(); 90334327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen return MI->getOperand(0).getReg(); 90434327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen } 90534327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen break; 90628f08c93e75d291695ea89b9004145103292e85bJim Grosbach case ARM::VST1q64: 907161474d198d44ab505861c1ec55f022b27314b35Anton Korobeynikov case ARM::VST1d64TPseudo: 908161474d198d44ab505861c1ec55f022b27314b35Anton Korobeynikov case ARM::VST1d64QPseudo: 909d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen if (MI->getOperand(0).isFI() && 910d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen MI->getOperand(2).getSubReg() == 0) { 911d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen FrameIndex = MI->getOperand(0).getIndex(); 912d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen return MI->getOperand(2).getReg(); 913d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen } 91431bbc51ac9245bc82c933c9db8358ca9bb558ac5Jakob Stoklund Olesen break; 91573fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMQIA: 916d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen if (MI->getOperand(1).isFI() && 917d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen MI->getOperand(0).getSubReg() == 0) { 918d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen FrameIndex = MI->getOperand(1).getIndex(); 919d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen return MI->getOperand(0).getReg(); 920d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen } 921d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen break; 92234327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen } 92334327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen 92434327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen return 0; 92534327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen} 92634327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen 92736ee0e640554b8cc6ad1658fc3049e05d9967160Jakob Stoklund Olesenunsigned ARMBaseInstrInfo::isStoreToStackSlotPostFE(const MachineInstr *MI, 92836ee0e640554b8cc6ad1658fc3049e05d9967160Jakob Stoklund Olesen int &FrameIndex) const { 92936ee0e640554b8cc6ad1658fc3049e05d9967160Jakob Stoklund Olesen const MachineMemOperand *Dummy; 9305a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng return MI->mayStore() && hasStoreToStackSlot(MI, Dummy, FrameIndex); 93136ee0e640554b8cc6ad1658fc3049e05d9967160Jakob Stoklund Olesen} 93236ee0e640554b8cc6ad1658fc3049e05d9967160Jakob Stoklund Olesen 933334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinvoid ARMBaseInstrInfo:: 934334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinloadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 935334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned DestReg, int FI, 936746ad69e088176819981b4b2c5ac8dcd49f5e60eEvan Cheng const TargetRegisterClass *RC, 937746ad69e088176819981b4b2c5ac8dcd49f5e60eEvan Cheng const TargetRegisterInfo *TRI) const { 938c7f3ace20c325521c68335a1689645b43b06ddf0Chris Lattner DebugLoc DL; 939334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (I != MBB.end()) DL = I->getDebugLoc(); 940249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MachineFunction &MF = *MBB.getParent(); 941249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MachineFrameInfo &MFI = *MF.getFrameInfo(); 94231bc849123011b8eae6bb3c79876d9a3c26a6a1dJim Grosbach unsigned Align = MFI.getObjectAlignment(FI); 943249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MachineMemOperand *MMO = 94459db5496f4fc2ef6111569e542f8b65480ef14c1Chris Lattner MF.getMachineMemOperand( 945978e0dfe46e481bfb1281e683aa308329e879e95Jay Foad MachinePointerInfo::getFixedStack(FI), 94659db5496f4fc2ef6111569e542f8b65480ef14c1Chris Lattner MachineMemOperand::MOLoad, 947249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MFI.getObjectSize(FI), 94831bc849123011b8eae6bb3c79876d9a3c26a6a1dJim Grosbach Align); 949334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 950e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson switch (RC->getSize()) { 951e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson case 4: 952e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson if (ARM::GPRRegClass.hasSubClassEq(RC)) { 953e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::LDRi12), DestReg) 9543e5561247202bae994dd259a2d8dc4eff8f799f3Jim Grosbach .addFrameIndex(FI).addImm(0).addMemOperand(MMO)); 955e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson 956e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson } else if (ARM::SPRRegClass.hasSubClassEq(RC)) { 957e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRS), DestReg) 958d31c5496d7e1580058b5c6fbc8fd537a641ea590Evan Cheng .addFrameIndex(FI).addImm(0).addMemOperand(MMO)); 959e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson } else 960e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson llvm_unreachable("Unknown reg class!"); 961ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson break; 962e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson case 8: 963e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson if (ARM::DPRRegClass.hasSubClassEq(RC)) { 964e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRD), DestReg) 965249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov .addFrameIndex(FI).addImm(0).addMemOperand(MMO)); 966e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson } else 967e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson llvm_unreachable("Unknown reg class!"); 968ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson break; 969e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson case 16: 9705b2f9136644c58ae32e00d8317540692a697d1c9Jakob Stoklund Olesen if (ARM::DPairRegClass.hasSubClassEq(RC)) { 9717255a4e1332ccb69918ebe041dff05f9e4e5815dJakob Stoklund Olesen if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) { 97228f08c93e75d291695ea89b9004145103292e85bJim Grosbach AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1q64), DestReg) 973f967ca0eaf30325cabe3c1971bf0dba16cf1b027Bob Wilson .addFrameIndex(FI).addImm(16) 97469b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng .addMemOperand(MMO)); 975e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson } else { 976e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMQIA), DestReg) 977e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson .addFrameIndex(FI) 978e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson .addMemOperand(MMO)); 979e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson } 980e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson } else 981e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson llvm_unreachable("Unknown reg class!"); 982ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson break; 983b58d7d03125526c152ade0c75be302b3c9eab997Anton Korobeynikov case 24: 984b58d7d03125526c152ade0c75be302b3c9eab997Anton Korobeynikov if (ARM::DTripleRegClass.hasSubClassEq(RC)) { 985b58d7d03125526c152ade0c75be302b3c9eab997Anton Korobeynikov if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) { 986b58d7d03125526c152ade0c75be302b3c9eab997Anton Korobeynikov AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1d64TPseudo), DestReg) 987b58d7d03125526c152ade0c75be302b3c9eab997Anton Korobeynikov .addFrameIndex(FI).addImm(16) 988b58d7d03125526c152ade0c75be302b3c9eab997Anton Korobeynikov .addMemOperand(MMO)); 989b58d7d03125526c152ade0c75be302b3c9eab997Anton Korobeynikov } else { 990b58d7d03125526c152ade0c75be302b3c9eab997Anton Korobeynikov MachineInstrBuilder MIB = 991b58d7d03125526c152ade0c75be302b3c9eab997Anton Korobeynikov AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMDIA)) 992b58d7d03125526c152ade0c75be302b3c9eab997Anton Korobeynikov .addFrameIndex(FI) 993b58d7d03125526c152ade0c75be302b3c9eab997Anton Korobeynikov .addMemOperand(MMO)); 994b58d7d03125526c152ade0c75be302b3c9eab997Anton Korobeynikov MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI); 995b58d7d03125526c152ade0c75be302b3c9eab997Anton Korobeynikov MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI); 996b58d7d03125526c152ade0c75be302b3c9eab997Anton Korobeynikov MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI); 997b58d7d03125526c152ade0c75be302b3c9eab997Anton Korobeynikov if (TargetRegisterInfo::isPhysicalRegister(DestReg)) 998b58d7d03125526c152ade0c75be302b3c9eab997Anton Korobeynikov MIB.addReg(DestReg, RegState::ImplicitDefine); 999b58d7d03125526c152ade0c75be302b3c9eab997Anton Korobeynikov } 1000b58d7d03125526c152ade0c75be302b3c9eab997Anton Korobeynikov } else 1001b58d7d03125526c152ade0c75be302b3c9eab997Anton Korobeynikov llvm_unreachable("Unknown reg class!"); 1002b58d7d03125526c152ade0c75be302b3c9eab997Anton Korobeynikov break; 1003b58d7d03125526c152ade0c75be302b3c9eab997Anton Korobeynikov case 32: 1004b58d7d03125526c152ade0c75be302b3c9eab997Anton Korobeynikov if (ARM::QQPRRegClass.hasSubClassEq(RC) || ARM::DQuadRegClass.hasSubClassEq(RC)) { 1005e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) { 1006e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1d64QPseudo), DestReg) 1007168f382dc67e5940cabdb28dc933c4f91cdd3137Bob Wilson .addFrameIndex(FI).addImm(16) 1008168f382dc67e5940cabdb28dc933c4f91cdd3137Bob Wilson .addMemOperand(MMO)); 1009e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson } else { 1010e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson MachineInstrBuilder MIB = 101173fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMDIA)) 101273fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling .addFrameIndex(FI)) 1013e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson .addMemOperand(MMO); 1014fce711cb65716f86b4e150f42cbb597bbecf7dbeJakob Stoklund Olesen MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI); 1015fce711cb65716f86b4e150f42cbb597bbecf7dbeJakob Stoklund Olesen MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI); 1016fce711cb65716f86b4e150f42cbb597bbecf7dbeJakob Stoklund Olesen MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI); 1017fce711cb65716f86b4e150f42cbb597bbecf7dbeJakob Stoklund Olesen MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::DefineNoRead, TRI); 10183247af294996ff8588077c06505b64966ad41542Jakob Stoklund Olesen if (TargetRegisterInfo::isPhysicalRegister(DestReg)) 10193247af294996ff8588077c06505b64966ad41542Jakob Stoklund Olesen MIB.addReg(DestReg, RegState::ImplicitDefine); 1020e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson } 1021e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson } else 1022e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson llvm_unreachable("Unknown reg class!"); 1023ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson break; 1024e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson case 64: 1025e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson if (ARM::QQQQPRRegClass.hasSubClassEq(RC)) { 1026e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson MachineInstrBuilder MIB = 102773fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMDIA)) 102873fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling .addFrameIndex(FI)) 1029e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson .addMemOperand(MMO); 1030fce711cb65716f86b4e150f42cbb597bbecf7dbeJakob Stoklund Olesen MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI); 1031fce711cb65716f86b4e150f42cbb597bbecf7dbeJakob Stoklund Olesen MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI); 1032fce711cb65716f86b4e150f42cbb597bbecf7dbeJakob Stoklund Olesen MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI); 1033fce711cb65716f86b4e150f42cbb597bbecf7dbeJakob Stoklund Olesen MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::DefineNoRead, TRI); 1034fce711cb65716f86b4e150f42cbb597bbecf7dbeJakob Stoklund Olesen MIB = AddDReg(MIB, DestReg, ARM::dsub_4, RegState::DefineNoRead, TRI); 1035fce711cb65716f86b4e150f42cbb597bbecf7dbeJakob Stoklund Olesen MIB = AddDReg(MIB, DestReg, ARM::dsub_5, RegState::DefineNoRead, TRI); 1036fce711cb65716f86b4e150f42cbb597bbecf7dbeJakob Stoklund Olesen MIB = AddDReg(MIB, DestReg, ARM::dsub_6, RegState::DefineNoRead, TRI); 1037fce711cb65716f86b4e150f42cbb597bbecf7dbeJakob Stoklund Olesen MIB = AddDReg(MIB, DestReg, ARM::dsub_7, RegState::DefineNoRead, TRI); 10383247af294996ff8588077c06505b64966ad41542Jakob Stoklund Olesen if (TargetRegisterInfo::isPhysicalRegister(DestReg)) 10393247af294996ff8588077c06505b64966ad41542Jakob Stoklund Olesen MIB.addReg(DestReg, RegState::ImplicitDefine); 1040e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson } else 1041e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson llvm_unreachable("Unknown reg class!"); 1042ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson break; 1043ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson default: 1044ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson llvm_unreachable("Unknown regclass!"); 1045334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 1046334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 1047334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 104834327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesenunsigned 104934327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund OlesenARMBaseInstrInfo::isLoadFromStackSlot(const MachineInstr *MI, 105034327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen int &FrameIndex) const { 105134327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen switch (MI->getOpcode()) { 105234327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen default: break; 10533e5561247202bae994dd259a2d8dc4eff8f799f3Jim Grosbach case ARM::LDRrs: 105434327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen case ARM::t2LDRs: // FIXME: don't use t2LDRs to access frame. 105534327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen if (MI->getOperand(1).isFI() && 105634327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen MI->getOperand(2).isReg() && 105734327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen MI->getOperand(3).isImm() && 105834327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen MI->getOperand(2).getReg() == 0 && 105934327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen MI->getOperand(3).getImm() == 0) { 106034327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen FrameIndex = MI->getOperand(1).getIndex(); 106134327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen return MI->getOperand(0).getReg(); 106234327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen } 106334327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen break; 10643e5561247202bae994dd259a2d8dc4eff8f799f3Jim Grosbach case ARM::LDRi12: 106534327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen case ARM::t2LDRi12: 106674472b4bf963c424da04f42dffdb94c85ef964bcJim Grosbach case ARM::tLDRspi: 106734327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen case ARM::VLDRD: 106834327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen case ARM::VLDRS: 106934327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen if (MI->getOperand(1).isFI() && 107034327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen MI->getOperand(2).isImm() && 107134327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen MI->getOperand(2).getImm() == 0) { 107234327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen FrameIndex = MI->getOperand(1).getIndex(); 1073d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen return MI->getOperand(0).getReg(); 1074d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen } 1075d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen break; 107628f08c93e75d291695ea89b9004145103292e85bJim Grosbach case ARM::VLD1q64: 1077161474d198d44ab505861c1ec55f022b27314b35Anton Korobeynikov case ARM::VLD1d64TPseudo: 1078161474d198d44ab505861c1ec55f022b27314b35Anton Korobeynikov case ARM::VLD1d64QPseudo: 1079d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen if (MI->getOperand(1).isFI() && 1080d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen MI->getOperand(0).getSubReg() == 0) { 1081d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen FrameIndex = MI->getOperand(1).getIndex(); 108206f264e504d75f0426eea55b9f9e36c780d8a4fcJakob Stoklund Olesen return MI->getOperand(0).getReg(); 108306f264e504d75f0426eea55b9f9e36c780d8a4fcJakob Stoklund Olesen } 108406f264e504d75f0426eea55b9f9e36c780d8a4fcJakob Stoklund Olesen break; 108573fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMQIA: 108606f264e504d75f0426eea55b9f9e36c780d8a4fcJakob Stoklund Olesen if (MI->getOperand(1).isFI() && 108706f264e504d75f0426eea55b9f9e36c780d8a4fcJakob Stoklund Olesen MI->getOperand(0).getSubReg() == 0) { 108806f264e504d75f0426eea55b9f9e36c780d8a4fcJakob Stoklund Olesen FrameIndex = MI->getOperand(1).getIndex(); 108934327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen return MI->getOperand(0).getReg(); 109034327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen } 109134327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen break; 109234327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen } 109334327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen 109434327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen return 0; 109534327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen} 109634327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen 109736ee0e640554b8cc6ad1658fc3049e05d9967160Jakob Stoklund Olesenunsigned ARMBaseInstrInfo::isLoadFromStackSlotPostFE(const MachineInstr *MI, 109836ee0e640554b8cc6ad1658fc3049e05d9967160Jakob Stoklund Olesen int &FrameIndex) const { 109936ee0e640554b8cc6ad1658fc3049e05d9967160Jakob Stoklund Olesen const MachineMemOperand *Dummy; 11005a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng return MI->mayLoad() && hasLoadFromStackSlot(MI, Dummy, FrameIndex); 110136ee0e640554b8cc6ad1658fc3049e05d9967160Jakob Stoklund Olesen} 110236ee0e640554b8cc6ad1658fc3049e05d9967160Jakob Stoklund Olesen 1103142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesenbool ARMBaseInstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const{ 1104142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen // This hook gets to expand COPY instructions before they become 1105142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen // copyPhysReg() calls. Look for VMOVS instructions that can legally be 1106142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen // widened to VMOVD. We prefer the VMOVD when possible because it may be 1107142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen // changed into a VORR that can go down the NEON pipeline. 1108142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen if (!WidenVMOVS || !MI->isCopy()) 1109142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen return false; 1110142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen 1111142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen // Look for a copy between even S-registers. That is where we keep floats 1112142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen // when using NEON v2f32 instructions for f32 arithmetic. 1113142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen unsigned DstRegS = MI->getOperand(0).getReg(); 1114142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen unsigned SrcRegS = MI->getOperand(1).getReg(); 1115142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen if (!ARM::SPRRegClass.contains(DstRegS, SrcRegS)) 1116142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen return false; 1117142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen 1118142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen const TargetRegisterInfo *TRI = &getRegisterInfo(); 1119142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen unsigned DstRegD = TRI->getMatchingSuperReg(DstRegS, ARM::ssub_0, 1120142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen &ARM::DPRRegClass); 1121142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen unsigned SrcRegD = TRI->getMatchingSuperReg(SrcRegS, ARM::ssub_0, 1122142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen &ARM::DPRRegClass); 1123142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen if (!DstRegD || !SrcRegD) 1124142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen return false; 1125142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen 1126142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen // We want to widen this into a DstRegD = VMOVD SrcRegD copy. This is only 1127142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen // legal if the COPY already defines the full DstRegD, and it isn't a 1128142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen // sub-register insertion. 1129142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen if (!MI->definesRegister(DstRegD, TRI) || MI->readsRegister(DstRegD, TRI)) 1130142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen return false; 1131142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen 11321c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen // A dead copy shouldn't show up here, but reject it just in case. 11331c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen if (MI->getOperand(0).isDead()) 11341c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen return false; 11351c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen 11361c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen // All clear, widen the COPY. 1137142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen DEBUG(dbgs() << "widening: " << *MI); 11381c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen 11391c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen // Get rid of the old <imp-def> of DstRegD. Leave it if it defines a Q-reg 11401c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen // or some other super-register. 11411c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen int ImpDefIdx = MI->findRegisterDefOperandIdx(DstRegD); 11421c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen if (ImpDefIdx != -1) 11431c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen MI->RemoveOperand(ImpDefIdx); 11441c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen 11451c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen // Change the opcode and operands. 1146142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen MI->setDesc(get(ARM::VMOVD)); 1147142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen MI->getOperand(0).setReg(DstRegD); 1148142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen MI->getOperand(1).setReg(SrcRegD); 1149142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen AddDefaultPred(MachineInstrBuilder(MI)); 11501c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen 11511c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen // We are now reading SrcRegD instead of SrcRegS. This may upset the 11521c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen // register scavenger and machine verifier, so we need to indicate that we 11531c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen // are reading an undefined value from SrcRegD, but a proper value from 11541c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen // SrcRegS. 11551c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen MI->getOperand(1).setIsUndef(); 11561c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen MachineInstrBuilder(MI).addReg(SrcRegS, RegState::Implicit); 11571c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen 11581c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen // SrcRegD may actually contain an unrelated value in the ssub_1 11591c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen // sub-register. Don't kill it. Only kill the ssub_0 sub-register. 11601c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen if (MI->getOperand(1).isKill()) { 11611c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen MI->getOperand(1).setIsKill(false); 11621c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen MI->addRegisterKilled(SrcRegS, TRI, true); 11631c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen } 11641c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen 1165142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen DEBUG(dbgs() << "replaced by: " << *MI); 1166142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen return true; 1167142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen} 1168142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen 116962b50656ceb854eb0be265d63b2a1d46e7400d8aEvan ChengMachineInstr* 117062b50656ceb854eb0be265d63b2a1d46e7400d8aEvan ChengARMBaseInstrInfo::emitFrameIndexDebugValue(MachineFunction &MF, 11718601a3d4decff0a380e059b037dabf71075497d3Evan Cheng int FrameIx, uint64_t Offset, 117262b50656ceb854eb0be265d63b2a1d46e7400d8aEvan Cheng const MDNode *MDPtr, 117362b50656ceb854eb0be265d63b2a1d46e7400d8aEvan Cheng DebugLoc DL) const { 117462b50656ceb854eb0be265d63b2a1d46e7400d8aEvan Cheng MachineInstrBuilder MIB = BuildMI(MF, DL, get(ARM::DBG_VALUE)) 117562b50656ceb854eb0be265d63b2a1d46e7400d8aEvan Cheng .addFrameIndex(FrameIx).addImm(0).addImm(Offset).addMetadata(MDPtr); 117662b50656ceb854eb0be265d63b2a1d46e7400d8aEvan Cheng return &*MIB; 117762b50656ceb854eb0be265d63b2a1d46e7400d8aEvan Cheng} 117862b50656ceb854eb0be265d63b2a1d46e7400d8aEvan Cheng 117930ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen/// Create a copy of a const pool value. Update CPI to the new index and return 118030ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen/// the label UID. 118130ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesenstatic unsigned duplicateCPV(MachineFunction &MF, unsigned &CPI) { 118230ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen MachineConstantPool *MCP = MF.getConstantPool(); 118330ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 118430ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen 118530ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPI]; 118630ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen assert(MCPE.isMachineConstantPoolEntry() && 118730ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen "Expecting a machine constantpool entry!"); 118830ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen ARMConstantPoolValue *ACPV = 118930ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal); 119030ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen 11915de5d4b6d0eb3fd379fa571d82f6fa764460b3b8Evan Cheng unsigned PCLabelId = AFI->createPICLabelUId(); 119230ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen ARMConstantPoolValue *NewCPV = 0; 119351f5b67395780b8421f4aa6ee998ed51b23dae9dJim Grosbach // FIXME: The below assumes PIC relocation model and that the function 119451f5b67395780b8421f4aa6ee998ed51b23dae9dJim Grosbach // is Thumb mode (t1 or t2). PCAdjustment would be 8 for ARM mode PIC, and 119551f5b67395780b8421f4aa6ee998ed51b23dae9dJim Grosbach // zero for non-PIC in ARM or Thumb. The callers are all of thumb LDR 119651f5b67395780b8421f4aa6ee998ed51b23dae9dJim Grosbach // instructions, so that's probably OK, but is PIC always correct when 119751f5b67395780b8421f4aa6ee998ed51b23dae9dJim Grosbach // we get here? 119830ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen if (ACPV->isGlobalValue()) 11995bb779976a7d8e48408051ec2289fe69206dc072Bill Wendling NewCPV = ARMConstantPoolConstant:: 12005bb779976a7d8e48408051ec2289fe69206dc072Bill Wendling Create(cast<ARMConstantPoolConstant>(ACPV)->getGV(), PCLabelId, 12015bb779976a7d8e48408051ec2289fe69206dc072Bill Wendling ARMCP::CPValue, 4); 120230ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen else if (ACPV->isExtSymbol()) 1203fe31e673506ef9a1080eaa684b43b34178c6f447Bill Wendling NewCPV = ARMConstantPoolSymbol:: 1204fe31e673506ef9a1080eaa684b43b34178c6f447Bill Wendling Create(MF.getFunction()->getContext(), 1205fe31e673506ef9a1080eaa684b43b34178c6f447Bill Wendling cast<ARMConstantPoolSymbol>(ACPV)->getSymbol(), PCLabelId, 4); 120630ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen else if (ACPV->isBlockAddress()) 12075bb779976a7d8e48408051ec2289fe69206dc072Bill Wendling NewCPV = ARMConstantPoolConstant:: 12085bb779976a7d8e48408051ec2289fe69206dc072Bill Wendling Create(cast<ARMConstantPoolConstant>(ACPV)->getBlockAddress(), PCLabelId, 12095bb779976a7d8e48408051ec2289fe69206dc072Bill Wendling ARMCP::CPBlockAddress, 4); 121051f5b67395780b8421f4aa6ee998ed51b23dae9dJim Grosbach else if (ACPV->isLSDA()) 12115bb779976a7d8e48408051ec2289fe69206dc072Bill Wendling NewCPV = ARMConstantPoolConstant::Create(MF.getFunction(), PCLabelId, 12125bb779976a7d8e48408051ec2289fe69206dc072Bill Wendling ARMCP::CPLSDA, 4); 1213e00897c5a91febe90ba21082fc636be892bf9bf1Bill Wendling else if (ACPV->isMachineBasicBlock()) 12143320f2a3bfd4daec23ba7ceb50525140cc6316daBill Wendling NewCPV = ARMConstantPoolMBB:: 12153320f2a3bfd4daec23ba7ceb50525140cc6316daBill Wendling Create(MF.getFunction()->getContext(), 12163320f2a3bfd4daec23ba7ceb50525140cc6316daBill Wendling cast<ARMConstantPoolMBB>(ACPV)->getMBB(), PCLabelId, 4); 121730ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen else 121830ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen llvm_unreachable("Unexpected ARM constantpool value type!!"); 121930ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen CPI = MCP->getConstantPoolIndex(NewCPV, MCPE.getAlignment()); 122030ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen return PCLabelId; 122130ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen} 122230ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen 1223fdc834046efd427d474e3b899ec69354c05071e0Evan Chengvoid ARMBaseInstrInfo:: 1224fdc834046efd427d474e3b899ec69354c05071e0Evan ChengreMaterialize(MachineBasicBlock &MBB, 1225fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng MachineBasicBlock::iterator I, 1226fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng unsigned DestReg, unsigned SubIdx, 1227d57cdd5683ea926e489067364fb7ffe5fd5d35eeEvan Cheng const MachineInstr *Orig, 12289edf7deb37f0f97664f279040fa15d89f32e23d9Jakob Stoklund Olesen const TargetRegisterInfo &TRI) const { 1229fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng unsigned Opcode = Orig->getOpcode(); 1230fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng switch (Opcode) { 1231fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng default: { 1232fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig); 12339edf7deb37f0f97664f279040fa15d89f32e23d9Jakob Stoklund Olesen MI->substituteRegister(Orig->getOperand(0).getReg(), DestReg, SubIdx, TRI); 1234fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng MBB.insert(I, MI); 1235fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng break; 1236fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng } 1237fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng case ARM::tLDRpci_pic: 1238fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng case ARM::t2LDRpci_pic: { 1239fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng MachineFunction &MF = *MBB.getParent(); 1240fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng unsigned CPI = Orig->getOperand(1).getIndex(); 124130ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen unsigned PCLabelId = duplicateCPV(MF, CPI); 1242fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng MachineInstrBuilder MIB = BuildMI(MBB, I, Orig->getDebugLoc(), get(Opcode), 1243fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng DestReg) 1244fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng .addConstantPoolIndex(CPI).addImm(PCLabelId); 1245d7d030a44796adc73a6eaa939cd17e52047734c1Chris Lattner MIB->setMemRefs(Orig->memoperands_begin(), Orig->memoperands_end()); 1246fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng break; 1247fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng } 1248fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng } 1249fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng} 1250fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng 125130ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund OlesenMachineInstr * 125230ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund OlesenARMBaseInstrInfo::duplicate(MachineInstr *Orig, MachineFunction &MF) const { 125330ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen MachineInstr *MI = TargetInstrInfoImpl::duplicate(Orig, MF); 125430ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen switch(Orig->getOpcode()) { 125530ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen case ARM::tLDRpci_pic: 125630ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen case ARM::t2LDRpci_pic: { 125730ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen unsigned CPI = Orig->getOperand(1).getIndex(); 125830ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen unsigned PCLabelId = duplicateCPV(MF, CPI); 125930ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen Orig->getOperand(1).setIndex(CPI); 126030ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen Orig->getOperand(2).setImm(PCLabelId); 126130ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen break; 126230ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen } 126330ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen } 126430ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen return MI; 126530ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen} 126630ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen 1267506049f29f4f202a8e45feb916cc0264440a7f6dEvan Chengbool ARMBaseInstrInfo::produceSameValue(const MachineInstr *MI0, 12689fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng const MachineInstr *MI1, 12699fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng const MachineRegisterInfo *MRI) const { 1270d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng int Opcode = MI0->getOpcode(); 1271d7e3cc840b81b0438e47f05d9664137a198876dfEvan Cheng if (Opcode == ARM::t2LDRpci || 12729b82425cb0105fd5704f6b9bcd5e7693b05b1759Evan Cheng Opcode == ARM::t2LDRpci_pic || 12739b82425cb0105fd5704f6b9bcd5e7693b05b1759Evan Cheng Opcode == ARM::tLDRpci || 12749fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng Opcode == ARM::tLDRpci_pic || 127553519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng Opcode == ARM::MOV_ga_dyn || 127653519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng Opcode == ARM::MOV_ga_pcrel || 127753519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng Opcode == ARM::MOV_ga_pcrel_ldr || 127853519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng Opcode == ARM::t2MOV_ga_dyn || 127953519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng Opcode == ARM::t2MOV_ga_pcrel) { 1280d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng if (MI1->getOpcode() != Opcode) 1281d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng return false; 1282d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng if (MI0->getNumOperands() != MI1->getNumOperands()) 1283d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng return false; 1284d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng 1285d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng const MachineOperand &MO0 = MI0->getOperand(1); 1286d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng const MachineOperand &MO1 = MI1->getOperand(1); 1287d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng if (MO0.getOffset() != MO1.getOffset()) 1288d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng return false; 1289d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng 129053519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng if (Opcode == ARM::MOV_ga_dyn || 129153519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng Opcode == ARM::MOV_ga_pcrel || 129253519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng Opcode == ARM::MOV_ga_pcrel_ldr || 129353519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng Opcode == ARM::t2MOV_ga_dyn || 129453519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng Opcode == ARM::t2MOV_ga_pcrel) 12959fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng // Ignore the PC labels. 12969fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng return MO0.getGlobal() == MO1.getGlobal(); 12979fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng 1298d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng const MachineFunction *MF = MI0->getParent()->getParent(); 1299d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng const MachineConstantPool *MCP = MF->getConstantPool(); 1300d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng int CPI0 = MO0.getIndex(); 1301d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng int CPI1 = MO1.getIndex(); 1302d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng const MachineConstantPoolEntry &MCPE0 = MCP->getConstants()[CPI0]; 1303d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng const MachineConstantPoolEntry &MCPE1 = MCP->getConstants()[CPI1]; 1304d700617193f3d11deb83cd56c4ababbc8e0ea19fEvan Cheng bool isARMCP0 = MCPE0.isMachineConstantPoolEntry(); 1305d700617193f3d11deb83cd56c4ababbc8e0ea19fEvan Cheng bool isARMCP1 = MCPE1.isMachineConstantPoolEntry(); 1306d700617193f3d11deb83cd56c4ababbc8e0ea19fEvan Cheng if (isARMCP0 && isARMCP1) { 1307d700617193f3d11deb83cd56c4ababbc8e0ea19fEvan Cheng ARMConstantPoolValue *ACPV0 = 1308d700617193f3d11deb83cd56c4ababbc8e0ea19fEvan Cheng static_cast<ARMConstantPoolValue*>(MCPE0.Val.MachineCPVal); 1309d700617193f3d11deb83cd56c4ababbc8e0ea19fEvan Cheng ARMConstantPoolValue *ACPV1 = 1310d700617193f3d11deb83cd56c4ababbc8e0ea19fEvan Cheng static_cast<ARMConstantPoolValue*>(MCPE1.Val.MachineCPVal); 1311d700617193f3d11deb83cd56c4ababbc8e0ea19fEvan Cheng return ACPV0->hasSameValue(ACPV1); 1312d700617193f3d11deb83cd56c4ababbc8e0ea19fEvan Cheng } else if (!isARMCP0 && !isARMCP1) { 1313d700617193f3d11deb83cd56c4ababbc8e0ea19fEvan Cheng return MCPE0.Val.ConstVal == MCPE1.Val.ConstVal; 1314d700617193f3d11deb83cd56c4ababbc8e0ea19fEvan Cheng } 1315d700617193f3d11deb83cd56c4ababbc8e0ea19fEvan Cheng return false; 13169fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng } else if (Opcode == ARM::PICLDR) { 13179fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng if (MI1->getOpcode() != Opcode) 13189fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng return false; 13199fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng if (MI0->getNumOperands() != MI1->getNumOperands()) 13209fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng return false; 13219fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng 13229fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng unsigned Addr0 = MI0->getOperand(1).getReg(); 13239fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng unsigned Addr1 = MI1->getOperand(1).getReg(); 13249fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng if (Addr0 != Addr1) { 13259fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng if (!MRI || 13269fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng !TargetRegisterInfo::isVirtualRegister(Addr0) || 13279fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng !TargetRegisterInfo::isVirtualRegister(Addr1)) 13289fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng return false; 13299fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng 13309fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng // This assumes SSA form. 13319fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng MachineInstr *Def0 = MRI->getVRegDef(Addr0); 13329fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng MachineInstr *Def1 = MRI->getVRegDef(Addr1); 13339fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng // Check if the loaded value, e.g. a constantpool of a global address, are 13349fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng // the same. 13359fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng if (!produceSameValue(Def0, Def1, MRI)) 13369fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng return false; 13379fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng } 13389fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng 13399fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng for (unsigned i = 3, e = MI0->getNumOperands(); i != e; ++i) { 13409fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng // %vreg12<def> = PICLDR %vreg11, 0, pred:14, pred:%noreg 13419fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng const MachineOperand &MO0 = MI0->getOperand(i); 13429fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng const MachineOperand &MO1 = MI1->getOperand(i); 13439fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng if (!MO0.isIdenticalTo(MO1)) 13449fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng return false; 13459fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng } 13469fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng return true; 1347d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng } 1348d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng 1349506049f29f4f202a8e45feb916cc0264440a7f6dEvan Cheng return MI0->isIdenticalTo(MI1, MachineInstr::IgnoreVRegDefs); 1350d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng} 1351d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng 13524b722108e2cf8e77157e0879a23789cd44829933Bill Wendling/// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to 13534b722108e2cf8e77157e0879a23789cd44829933Bill Wendling/// determine if two loads are loading from the same base address. It should 13544b722108e2cf8e77157e0879a23789cd44829933Bill Wendling/// only return true if the base pointers are the same and the only differences 13554b722108e2cf8e77157e0879a23789cd44829933Bill Wendling/// between the two addresses is the offset. It also returns the offsets by 13564b722108e2cf8e77157e0879a23789cd44829933Bill Wendling/// reference. 13574b722108e2cf8e77157e0879a23789cd44829933Bill Wendlingbool ARMBaseInstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, 13584b722108e2cf8e77157e0879a23789cd44829933Bill Wendling int64_t &Offset1, 13594b722108e2cf8e77157e0879a23789cd44829933Bill Wendling int64_t &Offset2) const { 13604b722108e2cf8e77157e0879a23789cd44829933Bill Wendling // Don't worry about Thumb: just ARM and Thumb2. 13614b722108e2cf8e77157e0879a23789cd44829933Bill Wendling if (Subtarget.isThumb1Only()) return false; 13624b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 13634b722108e2cf8e77157e0879a23789cd44829933Bill Wendling if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode()) 13644b722108e2cf8e77157e0879a23789cd44829933Bill Wendling return false; 13654b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 13664b722108e2cf8e77157e0879a23789cd44829933Bill Wendling switch (Load1->getMachineOpcode()) { 13674b722108e2cf8e77157e0879a23789cd44829933Bill Wendling default: 13684b722108e2cf8e77157e0879a23789cd44829933Bill Wendling return false; 13693e5561247202bae994dd259a2d8dc4eff8f799f3Jim Grosbach case ARM::LDRi12: 1370c1d30212e911d1e55ff6b25bffefb503708883c3Jim Grosbach case ARM::LDRBi12: 13714b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::LDRD: 13724b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::LDRH: 13734b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::LDRSB: 13744b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::LDRSH: 13754b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::VLDRD: 13764b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::VLDRS: 13774b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::t2LDRi8: 13784b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::t2LDRDi8: 13794b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::t2LDRSHi8: 13804b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::t2LDRi12: 13814b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::t2LDRSHi12: 13824b722108e2cf8e77157e0879a23789cd44829933Bill Wendling break; 13834b722108e2cf8e77157e0879a23789cd44829933Bill Wendling } 13844b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 13854b722108e2cf8e77157e0879a23789cd44829933Bill Wendling switch (Load2->getMachineOpcode()) { 13864b722108e2cf8e77157e0879a23789cd44829933Bill Wendling default: 13874b722108e2cf8e77157e0879a23789cd44829933Bill Wendling return false; 13883e5561247202bae994dd259a2d8dc4eff8f799f3Jim Grosbach case ARM::LDRi12: 1389c1d30212e911d1e55ff6b25bffefb503708883c3Jim Grosbach case ARM::LDRBi12: 13904b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::LDRD: 13914b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::LDRH: 13924b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::LDRSB: 13934b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::LDRSH: 13944b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::VLDRD: 13954b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::VLDRS: 13964b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::t2LDRi8: 13974b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::t2LDRSHi8: 13984b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::t2LDRi12: 13994b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::t2LDRSHi12: 14004b722108e2cf8e77157e0879a23789cd44829933Bill Wendling break; 14014b722108e2cf8e77157e0879a23789cd44829933Bill Wendling } 14024b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 14034b722108e2cf8e77157e0879a23789cd44829933Bill Wendling // Check if base addresses and chain operands match. 14044b722108e2cf8e77157e0879a23789cd44829933Bill Wendling if (Load1->getOperand(0) != Load2->getOperand(0) || 14054b722108e2cf8e77157e0879a23789cd44829933Bill Wendling Load1->getOperand(4) != Load2->getOperand(4)) 14064b722108e2cf8e77157e0879a23789cd44829933Bill Wendling return false; 14074b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 14084b722108e2cf8e77157e0879a23789cd44829933Bill Wendling // Index should be Reg0. 14094b722108e2cf8e77157e0879a23789cd44829933Bill Wendling if (Load1->getOperand(3) != Load2->getOperand(3)) 14104b722108e2cf8e77157e0879a23789cd44829933Bill Wendling return false; 14114b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 14124b722108e2cf8e77157e0879a23789cd44829933Bill Wendling // Determine the offsets. 14134b722108e2cf8e77157e0879a23789cd44829933Bill Wendling if (isa<ConstantSDNode>(Load1->getOperand(1)) && 14144b722108e2cf8e77157e0879a23789cd44829933Bill Wendling isa<ConstantSDNode>(Load2->getOperand(1))) { 14154b722108e2cf8e77157e0879a23789cd44829933Bill Wendling Offset1 = cast<ConstantSDNode>(Load1->getOperand(1))->getSExtValue(); 14164b722108e2cf8e77157e0879a23789cd44829933Bill Wendling Offset2 = cast<ConstantSDNode>(Load2->getOperand(1))->getSExtValue(); 14174b722108e2cf8e77157e0879a23789cd44829933Bill Wendling return true; 14184b722108e2cf8e77157e0879a23789cd44829933Bill Wendling } 14194b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 14204b722108e2cf8e77157e0879a23789cd44829933Bill Wendling return false; 14214b722108e2cf8e77157e0879a23789cd44829933Bill Wendling} 14224b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 14234b722108e2cf8e77157e0879a23789cd44829933Bill Wendling/// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to 14247a2bdde0a0eebcd2125055e0eacaca040f0b766cChris Lattner/// determine (in conjunction with areLoadsFromSameBasePtr) if two loads should 14254b722108e2cf8e77157e0879a23789cd44829933Bill Wendling/// be scheduled togther. On some targets if two loads are loading from 14264b722108e2cf8e77157e0879a23789cd44829933Bill Wendling/// addresses in the same cache line, it's better if they are scheduled 14274b722108e2cf8e77157e0879a23789cd44829933Bill Wendling/// together. This function takes two integers that represent the load offsets 14284b722108e2cf8e77157e0879a23789cd44829933Bill Wendling/// from the common base address. It returns true if it decides it's desirable 14294b722108e2cf8e77157e0879a23789cd44829933Bill Wendling/// to schedule the two loads together. "NumLoads" is the number of loads that 14304b722108e2cf8e77157e0879a23789cd44829933Bill Wendling/// have already been scheduled after Load1. 14314b722108e2cf8e77157e0879a23789cd44829933Bill Wendlingbool ARMBaseInstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, 14324b722108e2cf8e77157e0879a23789cd44829933Bill Wendling int64_t Offset1, int64_t Offset2, 14334b722108e2cf8e77157e0879a23789cd44829933Bill Wendling unsigned NumLoads) const { 14344b722108e2cf8e77157e0879a23789cd44829933Bill Wendling // Don't worry about Thumb: just ARM and Thumb2. 14354b722108e2cf8e77157e0879a23789cd44829933Bill Wendling if (Subtarget.isThumb1Only()) return false; 14364b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 14374b722108e2cf8e77157e0879a23789cd44829933Bill Wendling assert(Offset2 > Offset1); 14384b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 14394b722108e2cf8e77157e0879a23789cd44829933Bill Wendling if ((Offset2 - Offset1) / 8 > 64) 14404b722108e2cf8e77157e0879a23789cd44829933Bill Wendling return false; 14414b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 14424b722108e2cf8e77157e0879a23789cd44829933Bill Wendling if (Load1->getMachineOpcode() != Load2->getMachineOpcode()) 14434b722108e2cf8e77157e0879a23789cd44829933Bill Wendling return false; // FIXME: overly conservative? 14444b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 14454b722108e2cf8e77157e0879a23789cd44829933Bill Wendling // Four loads in a row should be sufficient. 14464b722108e2cf8e77157e0879a23789cd44829933Bill Wendling if (NumLoads >= 3) 14474b722108e2cf8e77157e0879a23789cd44829933Bill Wendling return false; 14484b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 14494b722108e2cf8e77157e0879a23789cd44829933Bill Wendling return true; 14504b722108e2cf8e77157e0879a23789cd44829933Bill Wendling} 14514b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 145286050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Chengbool ARMBaseInstrInfo::isSchedulingBoundary(const MachineInstr *MI, 145386050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng const MachineBasicBlock *MBB, 145486050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng const MachineFunction &MF) const { 145557bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach // Debug info is never a scheduling boundary. It's necessary to be explicit 145657bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach // due to the special treatment of IT instructions below, otherwise a 145757bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach // dbg_value followed by an IT will result in the IT instruction being 145857bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach // considered a scheduling hazard, which is wrong. It should be the actual 145957bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach // instruction preceding the dbg_value instruction(s), just like it is 146057bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach // when debug info is not present. 146157bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach if (MI->isDebugValue()) 146257bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach return false; 146357bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach 146486050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // Terminators and labels can't be scheduled around. 14655a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng if (MI->isTerminator() || MI->isLabel()) 146686050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng return true; 146786050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng 146886050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // Treat the start of the IT block as a scheduling boundary, but schedule 146986050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // t2IT along with all instructions following it. 147086050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // FIXME: This is a big hammer. But the alternative is to add all potential 147186050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // true and anti dependencies to IT block instructions as implicit operands 147286050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // to the t2IT instruction. The added compile time and complexity does not 147386050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // seem worth it. 147486050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng MachineBasicBlock::const_iterator I = MI; 147557bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach // Make sure to skip any dbg_value instructions 147657bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach while (++I != MBB->end() && I->isDebugValue()) 147757bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach ; 147857bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach if (I != MBB->end() && I->getOpcode() == ARM::t2IT) 147986050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng return true; 148086050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng 148186050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // Don't attempt to schedule around any instruction that defines 148286050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // a stack-oriented pointer, as it's unlikely to be profitable. This 148386050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // saves compile time, because it doesn't require every single 148486050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // stack slot reference to depend on the instruction that does the 148586050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // modification. 1486a1aa8db51715bdd21770fbe4f7d7abf2c5d28829Jakob Stoklund Olesen // Calls don't actually change the stack pointer, even if they have imp-defs. 1487209600bb8830036f981238494ab0188c25364837Jakob Stoklund Olesen // No ARM calling conventions change the stack pointer. (X86 calling 1488209600bb8830036f981238494ab0188c25364837Jakob Stoklund Olesen // conventions sometimes do). 1489a1aa8db51715bdd21770fbe4f7d7abf2c5d28829Jakob Stoklund Olesen if (!MI->isCall() && MI->definesRegister(ARM::SP)) 149086050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng return true; 149186050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng 149286050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng return false; 149386050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng} 149486050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng 1495f81b7f6069b27c0a515070dcb392f6828437412fJakub Staszakbool ARMBaseInstrInfo:: 1496f81b7f6069b27c0a515070dcb392f6828437412fJakub StaszakisProfitableToIfCvt(MachineBasicBlock &MBB, 1497f81b7f6069b27c0a515070dcb392f6828437412fJakub Staszak unsigned NumCycles, unsigned ExtraPredCycles, 1498f81b7f6069b27c0a515070dcb392f6828437412fJakub Staszak const BranchProbability &Probability) const { 14995876db7a66fcc4ec4444a9f3e387c1cdc8baf9e5Cameron Zwarich if (!NumCycles) 150013151432edace19ee867a93b5c14573df4f75d24Evan Cheng return false; 15012bbb76909126db5bed6bde84b16d94ab5de4d372Michael J. Spencer 1502b20b85168c0e9819e6545f08281e9b83c82108f0Owen Anderson // Attempt to estimate the relative costs of predication versus branching. 1503f81b7f6069b27c0a515070dcb392f6828437412fJakub Staszak unsigned UnpredCost = Probability.getNumerator() * NumCycles; 1504f81b7f6069b27c0a515070dcb392f6828437412fJakub Staszak UnpredCost /= Probability.getDenominator(); 1505f81b7f6069b27c0a515070dcb392f6828437412fJakub Staszak UnpredCost += 1; // The branch itself 1506f81b7f6069b27c0a515070dcb392f6828437412fJakub Staszak UnpredCost += Subtarget.getMispredictionPenalty() / 10; 15072bbb76909126db5bed6bde84b16d94ab5de4d372Michael J. Spencer 1508f81b7f6069b27c0a515070dcb392f6828437412fJakub Staszak return (NumCycles + ExtraPredCycles) <= UnpredCost; 150913151432edace19ee867a93b5c14573df4f75d24Evan Cheng} 15102bbb76909126db5bed6bde84b16d94ab5de4d372Michael J. Spencer 151113151432edace19ee867a93b5c14573df4f75d24Evan Chengbool ARMBaseInstrInfo:: 15128239daf7c83a65a189c352cce3191cdc3bbfe151Evan ChengisProfitableToIfCvt(MachineBasicBlock &TMBB, 15138239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng unsigned TCycles, unsigned TExtra, 15148239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng MachineBasicBlock &FMBB, 15158239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng unsigned FCycles, unsigned FExtra, 1516f81b7f6069b27c0a515070dcb392f6828437412fJakub Staszak const BranchProbability &Probability) const { 15178239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng if (!TCycles || !FCycles) 1518b20b85168c0e9819e6545f08281e9b83c82108f0Owen Anderson return false; 15192bbb76909126db5bed6bde84b16d94ab5de4d372Michael J. Spencer 1520b20b85168c0e9819e6545f08281e9b83c82108f0Owen Anderson // Attempt to estimate the relative costs of predication versus branching. 1521f81b7f6069b27c0a515070dcb392f6828437412fJakub Staszak unsigned TUnpredCost = Probability.getNumerator() * TCycles; 1522f81b7f6069b27c0a515070dcb392f6828437412fJakub Staszak TUnpredCost /= Probability.getDenominator(); 1523e23dc9c0ef50b0a1934c04c1786f3a0478d62f41Andrew Trick 1524f81b7f6069b27c0a515070dcb392f6828437412fJakub Staszak uint32_t Comp = Probability.getDenominator() - Probability.getNumerator(); 1525f81b7f6069b27c0a515070dcb392f6828437412fJakub Staszak unsigned FUnpredCost = Comp * FCycles; 1526f81b7f6069b27c0a515070dcb392f6828437412fJakub Staszak FUnpredCost /= Probability.getDenominator(); 1527f81b7f6069b27c0a515070dcb392f6828437412fJakub Staszak 1528f81b7f6069b27c0a515070dcb392f6828437412fJakub Staszak unsigned UnpredCost = TUnpredCost + FUnpredCost; 1529f81b7f6069b27c0a515070dcb392f6828437412fJakub Staszak UnpredCost += 1; // The branch itself 1530f81b7f6069b27c0a515070dcb392f6828437412fJakub Staszak UnpredCost += Subtarget.getMispredictionPenalty() / 10; 1531f81b7f6069b27c0a515070dcb392f6828437412fJakub Staszak 1532f81b7f6069b27c0a515070dcb392f6828437412fJakub Staszak return (TCycles + FCycles + TExtra + FExtra) <= UnpredCost; 153313151432edace19ee867a93b5c14573df4f75d24Evan Cheng} 153413151432edace19ee867a93b5c14573df4f75d24Evan Cheng 1535eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilsonbool 1536eb1641d54a7eda7717304bc4d55d059208d8ebedBob WilsonARMBaseInstrInfo::isProfitableToUnpredicate(MachineBasicBlock &TMBB, 1537eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson MachineBasicBlock &FMBB) const { 1538eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson // Reduce false anti-dependencies to let Swift's out-of-order execution 1539eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson // engine do its thing. 1540eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson return Subtarget.isSwift(); 1541eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson} 1542eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson 15438fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng/// getInstrPredicate - If instruction is predicated, returns its predicate 15448fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng/// condition, otherwise returns AL. It also returns the condition code 15458fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng/// register by reference. 15465adb66a646e2ec32265263739f5b01c3f50c176aEvan ChengARMCC::CondCodes 15475adb66a646e2ec32265263739f5b01c3f50c176aEvan Chengllvm::getInstrPredicate(const MachineInstr *MI, unsigned &PredReg) { 15488fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng int PIdx = MI->findFirstPredOperandIdx(); 15498fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng if (PIdx == -1) { 15508fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng PredReg = 0; 15518fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng return ARMCC::AL; 15528fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng } 15538fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng 15548fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng PredReg = MI->getOperand(PIdx+1).getReg(); 15558fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng return (ARMCC::CondCodes)MI->getOperand(PIdx).getImm(); 15568fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng} 15578fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng 15588fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng 15596495f63945e8dbde81f03a1dc2ab421993b9a495Evan Chengint llvm::getMatchingCondBranchOpcode(int Opc) { 15605ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng if (Opc == ARM::B) 15615ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng return ARM::Bcc; 15624d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie if (Opc == ARM::tB) 15635ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng return ARM::tBcc; 15644d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie if (Opc == ARM::t2B) 15654d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie return ARM::t2Bcc; 15665ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng 15675ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng llvm_unreachable("Unknown unconditional branch opcode!"); 15685ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng} 15695ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng 1570c5041cac7d3aeaa7350abadf2a7ada92e8da27dcJakob Stoklund Olesen/// commuteInstruction - Handle commutable instructions. 1571c5041cac7d3aeaa7350abadf2a7ada92e8da27dcJakob Stoklund OlesenMachineInstr * 1572c5041cac7d3aeaa7350abadf2a7ada92e8da27dcJakob Stoklund OlesenARMBaseInstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const { 1573c5041cac7d3aeaa7350abadf2a7ada92e8da27dcJakob Stoklund Olesen switch (MI->getOpcode()) { 1574c5041cac7d3aeaa7350abadf2a7ada92e8da27dcJakob Stoklund Olesen case ARM::MOVCCr: 1575c5041cac7d3aeaa7350abadf2a7ada92e8da27dcJakob Stoklund Olesen case ARM::t2MOVCCr: { 1576c5041cac7d3aeaa7350abadf2a7ada92e8da27dcJakob Stoklund Olesen // MOVCC can be commuted by inverting the condition. 1577c5041cac7d3aeaa7350abadf2a7ada92e8da27dcJakob Stoklund Olesen unsigned PredReg = 0; 1578c5041cac7d3aeaa7350abadf2a7ada92e8da27dcJakob Stoklund Olesen ARMCC::CondCodes CC = getInstrPredicate(MI, PredReg); 1579c5041cac7d3aeaa7350abadf2a7ada92e8da27dcJakob Stoklund Olesen // MOVCC AL can't be inverted. Shouldn't happen. 1580c5041cac7d3aeaa7350abadf2a7ada92e8da27dcJakob Stoklund Olesen if (CC == ARMCC::AL || PredReg != ARM::CPSR) 1581c5041cac7d3aeaa7350abadf2a7ada92e8da27dcJakob Stoklund Olesen return NULL; 1582c5041cac7d3aeaa7350abadf2a7ada92e8da27dcJakob Stoklund Olesen MI = TargetInstrInfoImpl::commuteInstruction(MI, NewMI); 1583c5041cac7d3aeaa7350abadf2a7ada92e8da27dcJakob Stoklund Olesen if (!MI) 1584c5041cac7d3aeaa7350abadf2a7ada92e8da27dcJakob Stoklund Olesen return NULL; 1585c5041cac7d3aeaa7350abadf2a7ada92e8da27dcJakob Stoklund Olesen // After swapping the MOVCC operands, also invert the condition. 1586c5041cac7d3aeaa7350abadf2a7ada92e8da27dcJakob Stoklund Olesen MI->getOperand(MI->findFirstPredOperandIdx()) 1587c5041cac7d3aeaa7350abadf2a7ada92e8da27dcJakob Stoklund Olesen .setImm(ARMCC::getOppositeCondition(CC)); 1588c5041cac7d3aeaa7350abadf2a7ada92e8da27dcJakob Stoklund Olesen return MI; 1589c5041cac7d3aeaa7350abadf2a7ada92e8da27dcJakob Stoklund Olesen } 1590c5041cac7d3aeaa7350abadf2a7ada92e8da27dcJakob Stoklund Olesen } 1591c5041cac7d3aeaa7350abadf2a7ada92e8da27dcJakob Stoklund Olesen return TargetInstrInfoImpl::commuteInstruction(MI, NewMI); 1592c5041cac7d3aeaa7350abadf2a7ada92e8da27dcJakob Stoklund Olesen} 15936495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 15942860b7ea3a1d60213ee7228bd274bc4f8b170772Jakob Stoklund Olesen/// Identify instructions that can be folded into a MOVCC instruction, and 1595098c6a547fe540b3bbace4c3d4713f400c67b8a9Jakob Stoklund Olesen/// return the defining instruction. 1596098c6a547fe540b3bbace4c3d4713f400c67b8a9Jakob Stoklund Olesenstatic MachineInstr *canFoldIntoMOVCC(unsigned Reg, 1597098c6a547fe540b3bbace4c3d4713f400c67b8a9Jakob Stoklund Olesen const MachineRegisterInfo &MRI, 1598098c6a547fe540b3bbace4c3d4713f400c67b8a9Jakob Stoklund Olesen const TargetInstrInfo *TII) { 15992860b7ea3a1d60213ee7228bd274bc4f8b170772Jakob Stoklund Olesen if (!TargetRegisterInfo::isVirtualRegister(Reg)) 16002860b7ea3a1d60213ee7228bd274bc4f8b170772Jakob Stoklund Olesen return 0; 16012860b7ea3a1d60213ee7228bd274bc4f8b170772Jakob Stoklund Olesen if (!MRI.hasOneNonDBGUse(Reg)) 16022860b7ea3a1d60213ee7228bd274bc4f8b170772Jakob Stoklund Olesen return 0; 1603098c6a547fe540b3bbace4c3d4713f400c67b8a9Jakob Stoklund Olesen MachineInstr *MI = MRI.getVRegDef(Reg); 16042860b7ea3a1d60213ee7228bd274bc4f8b170772Jakob Stoklund Olesen if (!MI) 16052860b7ea3a1d60213ee7228bd274bc4f8b170772Jakob Stoklund Olesen return 0; 1606098c6a547fe540b3bbace4c3d4713f400c67b8a9Jakob Stoklund Olesen // MI is folded into the MOVCC by predicating it. 1607098c6a547fe540b3bbace4c3d4713f400c67b8a9Jakob Stoklund Olesen if (!MI->isPredicable()) 1608098c6a547fe540b3bbace4c3d4713f400c67b8a9Jakob Stoklund Olesen return 0; 16092860b7ea3a1d60213ee7228bd274bc4f8b170772Jakob Stoklund Olesen // Check if MI has any non-dead defs or physreg uses. This also detects 16102860b7ea3a1d60213ee7228bd274bc4f8b170772Jakob Stoklund Olesen // predicated instructions which will be reading CPSR. 16112860b7ea3a1d60213ee7228bd274bc4f8b170772Jakob Stoklund Olesen for (unsigned i = 1, e = MI->getNumOperands(); i != e; ++i) { 16122860b7ea3a1d60213ee7228bd274bc4f8b170772Jakob Stoklund Olesen const MachineOperand &MO = MI->getOperand(i); 1613a7fb3f68047556a7355e1f1080fb3d1ca9eb7078Jakob Stoklund Olesen // Reject frame index operands, PEI can't handle the predicated pseudos. 1614a7fb3f68047556a7355e1f1080fb3d1ca9eb7078Jakob Stoklund Olesen if (MO.isFI() || MO.isCPI() || MO.isJTI()) 1615a7fb3f68047556a7355e1f1080fb3d1ca9eb7078Jakob Stoklund Olesen return 0; 16162860b7ea3a1d60213ee7228bd274bc4f8b170772Jakob Stoklund Olesen if (!MO.isReg()) 16172860b7ea3a1d60213ee7228bd274bc4f8b170772Jakob Stoklund Olesen continue; 1618098c6a547fe540b3bbace4c3d4713f400c67b8a9Jakob Stoklund Olesen // MI can't have any tied operands, that would conflict with predication. 1619098c6a547fe540b3bbace4c3d4713f400c67b8a9Jakob Stoklund Olesen if (MO.isTied()) 1620098c6a547fe540b3bbace4c3d4713f400c67b8a9Jakob Stoklund Olesen return 0; 16212860b7ea3a1d60213ee7228bd274bc4f8b170772Jakob Stoklund Olesen if (TargetRegisterInfo::isPhysicalRegister(MO.getReg())) 16222860b7ea3a1d60213ee7228bd274bc4f8b170772Jakob Stoklund Olesen return 0; 16232860b7ea3a1d60213ee7228bd274bc4f8b170772Jakob Stoklund Olesen if (MO.isDef() && !MO.isDead()) 16242860b7ea3a1d60213ee7228bd274bc4f8b170772Jakob Stoklund Olesen return 0; 16252860b7ea3a1d60213ee7228bd274bc4f8b170772Jakob Stoklund Olesen } 1626098c6a547fe540b3bbace4c3d4713f400c67b8a9Jakob Stoklund Olesen bool DontMoveAcrossStores = true; 1627098c6a547fe540b3bbace4c3d4713f400c67b8a9Jakob Stoklund Olesen if (!MI->isSafeToMove(TII, /* AliasAnalysis = */ 0, DontMoveAcrossStores)) 1628098c6a547fe540b3bbace4c3d4713f400c67b8a9Jakob Stoklund Olesen return 0; 1629098c6a547fe540b3bbace4c3d4713f400c67b8a9Jakob Stoklund Olesen return MI; 16302860b7ea3a1d60213ee7228bd274bc4f8b170772Jakob Stoklund Olesen} 16312860b7ea3a1d60213ee7228bd274bc4f8b170772Jakob Stoklund Olesen 1632053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesenbool ARMBaseInstrInfo::analyzeSelect(const MachineInstr *MI, 1633053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen SmallVectorImpl<MachineOperand> &Cond, 1634053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen unsigned &TrueOp, unsigned &FalseOp, 1635053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen bool &Optimizable) const { 1636053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen assert((MI->getOpcode() == ARM::MOVCCr || MI->getOpcode() == ARM::t2MOVCCr) && 1637053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen "Unknown select instruction"); 1638053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen // MOVCC operands: 1639053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen // 0: Def. 1640053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen // 1: True use. 1641053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen // 2: False use. 1642053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen // 3: Condition code. 1643053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen // 4: CPSR use. 1644053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen TrueOp = 1; 1645053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen FalseOp = 2; 1646053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen Cond.push_back(MI->getOperand(3)); 1647053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen Cond.push_back(MI->getOperand(4)); 1648053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen // We can always fold a def. 1649053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen Optimizable = true; 1650053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen return false; 1651053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen} 1652053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen 1653053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund OlesenMachineInstr *ARMBaseInstrInfo::optimizeSelect(MachineInstr *MI, 1654053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen bool PreferFalse) const { 1655053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen assert((MI->getOpcode() == ARM::MOVCCr || MI->getOpcode() == ARM::t2MOVCCr) && 1656053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen "Unknown select instruction"); 1657053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen const MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo(); 1658098c6a547fe540b3bbace4c3d4713f400c67b8a9Jakob Stoklund Olesen MachineInstr *DefMI = canFoldIntoMOVCC(MI->getOperand(2).getReg(), MRI, this); 1659098c6a547fe540b3bbace4c3d4713f400c67b8a9Jakob Stoklund Olesen bool Invert = !DefMI; 1660098c6a547fe540b3bbace4c3d4713f400c67b8a9Jakob Stoklund Olesen if (!DefMI) 1661098c6a547fe540b3bbace4c3d4713f400c67b8a9Jakob Stoklund Olesen DefMI = canFoldIntoMOVCC(MI->getOperand(1).getReg(), MRI, this); 1662098c6a547fe540b3bbace4c3d4713f400c67b8a9Jakob Stoklund Olesen if (!DefMI) 1663053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen return 0; 1664053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen 1665053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen // Create a new predicated version of DefMI. 1666053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen // Rfalse is the first use. 1667053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen MachineInstrBuilder NewMI = BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), 1668098c6a547fe540b3bbace4c3d4713f400c67b8a9Jakob Stoklund Olesen DefMI->getDesc(), 1669098c6a547fe540b3bbace4c3d4713f400c67b8a9Jakob Stoklund Olesen MI->getOperand(0).getReg()); 1670053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen 1671053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen // Copy all the DefMI operands, excluding its (null) predicate. 1672053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen const MCInstrDesc &DefDesc = DefMI->getDesc(); 1673053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen for (unsigned i = 1, e = DefDesc.getNumOperands(); 1674053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen i != e && !DefDesc.OpInfo[i].isPredicate(); ++i) 1675053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen NewMI.addOperand(DefMI->getOperand(i)); 1676053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen 1677053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen unsigned CondCode = MI->getOperand(3).getImm(); 1678053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen if (Invert) 1679053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen NewMI.addImm(ARMCC::getOppositeCondition(ARMCC::CondCodes(CondCode))); 1680053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen else 1681053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen NewMI.addImm(CondCode); 1682053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen NewMI.addOperand(MI->getOperand(4)); 1683053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen 1684053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen // DefMI is not the -S version that sets CPSR, so add an optional %noreg. 1685053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen if (NewMI->hasOptionalDef()) 1686053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen AddDefaultCC(NewMI); 1687053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen 1688098c6a547fe540b3bbace4c3d4713f400c67b8a9Jakob Stoklund Olesen // The output register value when the predicate is false is an implicit 1689098c6a547fe540b3bbace4c3d4713f400c67b8a9Jakob Stoklund Olesen // register operand tied to the first def. 1690098c6a547fe540b3bbace4c3d4713f400c67b8a9Jakob Stoklund Olesen // The tie makes the register allocator ensure the FalseReg is allocated the 1691098c6a547fe540b3bbace4c3d4713f400c67b8a9Jakob Stoklund Olesen // same register as operand 0. 1692098c6a547fe540b3bbace4c3d4713f400c67b8a9Jakob Stoklund Olesen MachineOperand FalseReg = MI->getOperand(Invert ? 2 : 1); 1693098c6a547fe540b3bbace4c3d4713f400c67b8a9Jakob Stoklund Olesen FalseReg.setImplicit(); 1694098c6a547fe540b3bbace4c3d4713f400c67b8a9Jakob Stoklund Olesen NewMI->addOperand(FalseReg); 1695098c6a547fe540b3bbace4c3d4713f400c67b8a9Jakob Stoklund Olesen NewMI->tieOperands(0, NewMI->getNumOperands() - 1); 1696098c6a547fe540b3bbace4c3d4713f400c67b8a9Jakob Stoklund Olesen 1697053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen // The caller will erase MI, but not DefMI. 1698053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen DefMI->eraseFromParent(); 1699053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen return NewMI; 1700053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen} 1701053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen 17023be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick/// Map pseudo instructions that imply an 'S' bit onto real opcodes. Whether the 17033be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick/// instruction is encoded with an 'S' bit is determined by the optional CPSR 17043be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick/// def operand. 17053be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick/// 17063be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick/// This will go away once we can teach tblgen how to set the optional CPSR def 17073be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick/// operand itself. 17083be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trickstruct AddSubFlagsOpcodePair { 1709cd2859eef83708c00330c94f6842499b48d5ed02Craig Topper uint16_t PseudoOpc; 1710cd2859eef83708c00330c94f6842499b48d5ed02Craig Topper uint16_t MachineOpc; 17113be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick}; 17123be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick 1713cd2859eef83708c00330c94f6842499b48d5ed02Craig Topperstatic const AddSubFlagsOpcodePair AddSubFlagsOpcodeMap[] = { 17143be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick {ARM::ADDSri, ARM::ADDri}, 17153be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick {ARM::ADDSrr, ARM::ADDrr}, 17163be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick {ARM::ADDSrsi, ARM::ADDrsi}, 17173be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick {ARM::ADDSrsr, ARM::ADDrsr}, 17183be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick 17193be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick {ARM::SUBSri, ARM::SUBri}, 17203be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick {ARM::SUBSrr, ARM::SUBrr}, 17213be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick {ARM::SUBSrsi, ARM::SUBrsi}, 17223be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick {ARM::SUBSrsr, ARM::SUBrsr}, 17233be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick 17243be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick {ARM::RSBSri, ARM::RSBri}, 17253be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick {ARM::RSBSrsi, ARM::RSBrsi}, 17263be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick {ARM::RSBSrsr, ARM::RSBrsr}, 17273be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick 17283be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick {ARM::t2ADDSri, ARM::t2ADDri}, 17293be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick {ARM::t2ADDSrr, ARM::t2ADDrr}, 17303be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick {ARM::t2ADDSrs, ARM::t2ADDrs}, 17313be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick 17323be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick {ARM::t2SUBSri, ARM::t2SUBri}, 17333be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick {ARM::t2SUBSrr, ARM::t2SUBrr}, 17343be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick {ARM::t2SUBSrs, ARM::t2SUBrs}, 17353be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick 17363be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick {ARM::t2RSBSri, ARM::t2RSBri}, 17373be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick {ARM::t2RSBSrs, ARM::t2RSBrs}, 17383be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick}; 17393be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick 17403be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trickunsigned llvm::convertAddSubFlagsOpcode(unsigned OldOpc) { 1741cd2859eef83708c00330c94f6842499b48d5ed02Craig Topper for (unsigned i = 0, e = array_lengthof(AddSubFlagsOpcodeMap); i != e; ++i) 1742cd2859eef83708c00330c94f6842499b48d5ed02Craig Topper if (OldOpc == AddSubFlagsOpcodeMap[i].PseudoOpc) 1743cd2859eef83708c00330c94f6842499b48d5ed02Craig Topper return AddSubFlagsOpcodeMap[i].MachineOpc; 17443be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick return 0; 17453be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick} 17463be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick 17476495f63945e8dbde81f03a1dc2ab421993b9a495Evan Chengvoid llvm::emitARMRegPlusImmediate(MachineBasicBlock &MBB, 17486495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MachineBasicBlock::iterator &MBBI, DebugLoc dl, 17496495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned DestReg, unsigned BaseReg, int NumBytes, 17506495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ARMCC::CondCodes Pred, unsigned PredReg, 175157caad7a33ff145b71545f10dcfbbf2fd0f595d3Anton Korobeynikov const ARMBaseInstrInfo &TII, unsigned MIFlags) { 17526495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng bool isSub = NumBytes < 0; 17536495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (isSub) NumBytes = -NumBytes; 17546495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 17556495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng while (NumBytes) { 17566495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned RotAmt = ARM_AM::getSOImmValRotate(NumBytes); 17576495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned ThisVal = NumBytes & ARM_AM::rotr32(0xFF, RotAmt); 17586495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng assert(ThisVal && "Didn't extract field correctly"); 17596495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 17606495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // We will handle these bits from offset, clear them. 17616495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng NumBytes &= ~ThisVal; 17626495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 17636495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng assert(ARM_AM::getSOImmVal(ThisVal) != -1 && "Bit extraction didn't work?"); 17646495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 17656495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Build the new ADD / SUB. 17666495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned Opc = isSub ? ARM::SUBri : ARM::ADDri; 17676495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg) 17686495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng .addReg(BaseReg, RegState::Kill).addImm(ThisVal) 176957caad7a33ff145b71545f10dcfbbf2fd0f595d3Anton Korobeynikov .addImm((unsigned)Pred).addReg(PredReg).addReg(0) 177057caad7a33ff145b71545f10dcfbbf2fd0f595d3Anton Korobeynikov .setMIFlags(MIFlags); 17716495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng BaseReg = DestReg; 17726495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 17736495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng} 17746495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 1775cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Chengbool llvm::rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx, 1776cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng unsigned FrameReg, int &Offset, 1777cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng const ARMBaseInstrInfo &TII) { 17786495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned Opcode = MI.getOpcode(); 1779e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng const MCInstrDesc &Desc = MI.getDesc(); 17806495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask); 17816495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng bool isSub = false; 1782764ab52dd80310a205c9888bf166d09dab858f90Jim Grosbach 17836495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Memory operands in inline assembly always use AddrMode2. 17846495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (Opcode == ARM::INLINEASM) 17856495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng AddrMode = ARMII::AddrMode2; 1786764ab52dd80310a205c9888bf166d09dab858f90Jim Grosbach 17876495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (Opcode == ARM::ADDri) { 17886495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng Offset += MI.getOperand(FrameRegIdx+1).getImm(); 17896495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (Offset == 0) { 17906495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Turn it into a move. 17916495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MI.setDesc(TII.get(ARM::MOVr)); 17926495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false); 17936495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MI.RemoveOperand(FrameRegIdx+1); 1794cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng Offset = 0; 1795cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng return true; 17966495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } else if (Offset < 0) { 17976495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng Offset = -Offset; 17986495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng isSub = true; 17996495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MI.setDesc(TII.get(ARM::SUBri)); 18006495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 18016495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 18026495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Common case: small offset, fits into instruction. 18036495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (ARM_AM::getSOImmVal(Offset) != -1) { 18046495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Replace the FrameIndex with sp / fp 18056495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false); 18066495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset); 1807cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng Offset = 0; 1808cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng return true; 18096495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 18106495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 18116495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Otherwise, pull as much of the immedidate into this ADDri/SUBri 18126495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // as possible. 18136495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned RotAmt = ARM_AM::getSOImmValRotate(Offset); 18146495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xFF, RotAmt); 18156495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 18166495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // We will handle these bits from offset, clear them. 18176495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng Offset &= ~ThisImmVal; 18186495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 18196495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Get the properly encoded SOImmVal field. 18206495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng assert(ARM_AM::getSOImmVal(ThisImmVal) != -1 && 18216495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng "Bit extraction didn't work?"); 18226495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MI.getOperand(FrameRegIdx+1).ChangeToImmediate(ThisImmVal); 18236495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } else { 18246495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned ImmIdx = 0; 18256495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng int InstrOffs = 0; 18266495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned NumBits = 0; 18276495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned Scale = 1; 18286495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng switch (AddrMode) { 18293e5561247202bae994dd259a2d8dc4eff8f799f3Jim Grosbach case ARMII::AddrMode_i12: { 18303e5561247202bae994dd259a2d8dc4eff8f799f3Jim Grosbach ImmIdx = FrameRegIdx + 1; 18313e5561247202bae994dd259a2d8dc4eff8f799f3Jim Grosbach InstrOffs = MI.getOperand(ImmIdx).getImm(); 18323e5561247202bae994dd259a2d8dc4eff8f799f3Jim Grosbach NumBits = 12; 18333e5561247202bae994dd259a2d8dc4eff8f799f3Jim Grosbach break; 18343e5561247202bae994dd259a2d8dc4eff8f799f3Jim Grosbach } 18356495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng case ARMII::AddrMode2: { 18366495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ImmIdx = FrameRegIdx+2; 18376495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng InstrOffs = ARM_AM::getAM2Offset(MI.getOperand(ImmIdx).getImm()); 18386495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (ARM_AM::getAM2Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub) 18396495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng InstrOffs *= -1; 18406495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng NumBits = 12; 18416495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng break; 18426495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 18436495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng case ARMII::AddrMode3: { 18446495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ImmIdx = FrameRegIdx+2; 18456495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng InstrOffs = ARM_AM::getAM3Offset(MI.getOperand(ImmIdx).getImm()); 18466495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (ARM_AM::getAM3Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub) 18476495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng InstrOffs *= -1; 18486495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng NumBits = 8; 18496495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng break; 18506495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 1851baf31088f1472f48ea5ae81f0b93636cc44ca444Anton Korobeynikov case ARMII::AddrMode4: 1852a44321776ecd96fa0344335d3027758be3386e45Jim Grosbach case ARMII::AddrMode6: 1853cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng // Can't fold any offset even if it's zero. 1854cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng return false; 18556495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng case ARMII::AddrMode5: { 18566495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ImmIdx = FrameRegIdx+1; 18576495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng InstrOffs = ARM_AM::getAM5Offset(MI.getOperand(ImmIdx).getImm()); 18586495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (ARM_AM::getAM5Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub) 18596495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng InstrOffs *= -1; 18606495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng NumBits = 8; 18616495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng Scale = 4; 18626495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng break; 18636495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 18646495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng default: 18656495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng llvm_unreachable("Unsupported addressing mode!"); 18666495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 18676495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 18686495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng Offset += InstrOffs * Scale; 18696495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!"); 18706495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (Offset < 0) { 18716495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng Offset = -Offset; 18726495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng isSub = true; 18736495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 18746495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 18756495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Attempt to fold address comp. if opcode has offset bits 18766495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (NumBits > 0) { 18776495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Common case: small offset, fits into instruction. 18786495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MachineOperand &ImmOp = MI.getOperand(ImmIdx); 18796495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng int ImmedOffset = Offset / Scale; 18806495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned Mask = (1 << NumBits) - 1; 18816495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if ((unsigned)Offset <= Mask * Scale) { 18826495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Replace the FrameIndex with sp 18836495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false); 188477aee8e22c36257716c2df2f275724765704f20cJim Grosbach // FIXME: When addrmode2 goes away, this will simplify (like the 188577aee8e22c36257716c2df2f275724765704f20cJim Grosbach // T2 version), as the LDR.i12 versions don't need the encoding 188677aee8e22c36257716c2df2f275724765704f20cJim Grosbach // tricks for the offset value. 188777aee8e22c36257716c2df2f275724765704f20cJim Grosbach if (isSub) { 188877aee8e22c36257716c2df2f275724765704f20cJim Grosbach if (AddrMode == ARMII::AddrMode_i12) 188977aee8e22c36257716c2df2f275724765704f20cJim Grosbach ImmedOffset = -ImmedOffset; 189077aee8e22c36257716c2df2f275724765704f20cJim Grosbach else 189177aee8e22c36257716c2df2f275724765704f20cJim Grosbach ImmedOffset |= 1 << NumBits; 189277aee8e22c36257716c2df2f275724765704f20cJim Grosbach } 18936495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ImmOp.ChangeToImmediate(ImmedOffset); 1894cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng Offset = 0; 1895cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng return true; 18966495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 1897764ab52dd80310a205c9888bf166d09dab858f90Jim Grosbach 18986495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Otherwise, it didn't fit. Pull in what we can to simplify the immed. 18996495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ImmedOffset = ImmedOffset & Mask; 1900063efbf569e46776093ddf50099c98fdbb362167Jim Grosbach if (isSub) { 1901063efbf569e46776093ddf50099c98fdbb362167Jim Grosbach if (AddrMode == ARMII::AddrMode_i12) 1902063efbf569e46776093ddf50099c98fdbb362167Jim Grosbach ImmedOffset = -ImmedOffset; 1903063efbf569e46776093ddf50099c98fdbb362167Jim Grosbach else 1904063efbf569e46776093ddf50099c98fdbb362167Jim Grosbach ImmedOffset |= 1 << NumBits; 1905063efbf569e46776093ddf50099c98fdbb362167Jim Grosbach } 19066495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ImmOp.ChangeToImmediate(ImmedOffset); 19076495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng Offset &= ~(Mask*Scale); 19086495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 19096495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 19106495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 1911cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng Offset = (isSub) ? -Offset : Offset; 1912cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng return Offset == 0; 19136495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng} 1914e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling 1915de7266c611b37ec050efb53b73166081a98cea13Manman Ren/// analyzeCompare - For a comparison instruction, return the source registers 1916de7266c611b37ec050efb53b73166081a98cea13Manman Ren/// in SrcReg and SrcReg2 if having two register operands, and the value it 1917de7266c611b37ec050efb53b73166081a98cea13Manman Ren/// compares against in CmpValue. Return true if the comparison instruction 1918de7266c611b37ec050efb53b73166081a98cea13Manman Ren/// can be analyzed. 1919e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendlingbool ARMBaseInstrInfo:: 1920de7266c611b37ec050efb53b73166081a98cea13Manman RenanalyzeCompare(const MachineInstr *MI, unsigned &SrcReg, unsigned &SrcReg2, 1921de7266c611b37ec050efb53b73166081a98cea13Manman Ren int &CmpMask, int &CmpValue) const { 1922e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling switch (MI->getOpcode()) { 1923e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling default: break; 192438ae997e63e3e1bb2c8679e01ea74cf8fd0be893Bill Wendling case ARM::CMPri: 1925e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling case ARM::t2CMPri: 1926e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling SrcReg = MI->getOperand(0).getReg(); 1927de7266c611b37ec050efb53b73166081a98cea13Manman Ren SrcReg2 = 0; 192804ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif CmpMask = ~0; 1929e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling CmpValue = MI->getOperand(1).getImm(); 1930e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling return true; 1931247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren case ARM::CMPrr: 1932247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren case ARM::t2CMPrr: 1933247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren SrcReg = MI->getOperand(0).getReg(); 1934de7266c611b37ec050efb53b73166081a98cea13Manman Ren SrcReg2 = MI->getOperand(1).getReg(); 1935247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren CmpMask = ~0; 1936247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren CmpValue = 0; 1937247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren return true; 193804ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif case ARM::TSTri: 193904ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif case ARM::t2TSTri: 194004ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif SrcReg = MI->getOperand(0).getReg(); 1941de7266c611b37ec050efb53b73166081a98cea13Manman Ren SrcReg2 = 0; 194204ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif CmpMask = MI->getOperand(1).getImm(); 194304ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif CmpValue = 0; 194404ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif return true; 194504ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif } 194604ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif 194704ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif return false; 194804ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif} 194904ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif 195005642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif/// isSuitableForMask - Identify a suitable 'and' instruction that 195105642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif/// operates on the given source register and applies the same mask 195205642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif/// as a 'tst' instruction. Provide a limited look-through for copies. 195305642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif/// When successful, MI will hold the found instruction. 195405642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greifstatic bool isSuitableForMask(MachineInstr *&MI, unsigned SrcReg, 19558ff9bb189ce188452e6cae6ed65cb2745814126cGabor Greif int CmpMask, bool CommonUse) { 195605642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif switch (MI->getOpcode()) { 195704ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif case ARM::ANDri: 195804ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif case ARM::t2ANDri: 195905642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif if (CmpMask != MI->getOperand(2).getImm()) 19608ff9bb189ce188452e6cae6ed65cb2745814126cGabor Greif return false; 196105642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif if (SrcReg == MI->getOperand(CommonUse ? 1 : 0).getReg()) 196204ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif return true; 196304ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif break; 196405642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif case ARM::COPY: { 196505642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif // Walk down one instruction which is potentially an 'and'. 196605642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif const MachineInstr &Copy = *MI; 1967f000a7a212590bfd45e23c05bff5e1b683d25dd6Michael J. Spencer MachineBasicBlock::iterator AND( 1968f000a7a212590bfd45e23c05bff5e1b683d25dd6Michael J. Spencer llvm::next(MachineBasicBlock::iterator(MI))); 196905642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif if (AND == MI->getParent()->end()) return false; 197005642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif MI = AND; 197105642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif return isSuitableForMask(MI, Copy.getOperand(0).getReg(), 197205642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif CmpMask, true); 197305642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif } 1974e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling } 1975e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling 1976e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling return false; 1977e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling} 1978e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling 197976c6ccbd4cee0637c961e32435177ab89e931fedManman Ren/// getSwappedCondition - assume the flags are set by MI(a,b), return 198076c6ccbd4cee0637c961e32435177ab89e931fedManman Ren/// the condition code if we modify the instructions such that flags are 198176c6ccbd4cee0637c961e32435177ab89e931fedManman Ren/// set by MI(b,a). 198276c6ccbd4cee0637c961e32435177ab89e931fedManman Reninline static ARMCC::CondCodes getSwappedCondition(ARMCC::CondCodes CC) { 198376c6ccbd4cee0637c961e32435177ab89e931fedManman Ren switch (CC) { 198476c6ccbd4cee0637c961e32435177ab89e931fedManman Ren default: return ARMCC::AL; 198576c6ccbd4cee0637c961e32435177ab89e931fedManman Ren case ARMCC::EQ: return ARMCC::EQ; 198676c6ccbd4cee0637c961e32435177ab89e931fedManman Ren case ARMCC::NE: return ARMCC::NE; 198776c6ccbd4cee0637c961e32435177ab89e931fedManman Ren case ARMCC::HS: return ARMCC::LS; 198876c6ccbd4cee0637c961e32435177ab89e931fedManman Ren case ARMCC::LO: return ARMCC::HI; 198976c6ccbd4cee0637c961e32435177ab89e931fedManman Ren case ARMCC::HI: return ARMCC::LO; 199076c6ccbd4cee0637c961e32435177ab89e931fedManman Ren case ARMCC::LS: return ARMCC::HS; 199176c6ccbd4cee0637c961e32435177ab89e931fedManman Ren case ARMCC::GE: return ARMCC::LE; 199276c6ccbd4cee0637c961e32435177ab89e931fedManman Ren case ARMCC::LT: return ARMCC::GT; 199376c6ccbd4cee0637c961e32435177ab89e931fedManman Ren case ARMCC::GT: return ARMCC::LT; 199476c6ccbd4cee0637c961e32435177ab89e931fedManman Ren case ARMCC::LE: return ARMCC::GE; 199576c6ccbd4cee0637c961e32435177ab89e931fedManman Ren } 199676c6ccbd4cee0637c961e32435177ab89e931fedManman Ren} 199776c6ccbd4cee0637c961e32435177ab89e931fedManman Ren 199876c6ccbd4cee0637c961e32435177ab89e931fedManman Ren/// isRedundantFlagInstr - check whether the first instruction, whose only 199976c6ccbd4cee0637c961e32435177ab89e931fedManman Ren/// purpose is to update flags, can be made redundant. 200076c6ccbd4cee0637c961e32435177ab89e931fedManman Ren/// CMPrr can be made redundant by SUBrr if the operands are the same. 200176c6ccbd4cee0637c961e32435177ab89e931fedManman Ren/// CMPri can be made redundant by SUBri if the operands are the same. 200276c6ccbd4cee0637c961e32435177ab89e931fedManman Ren/// This function can be extended later on. 200376c6ccbd4cee0637c961e32435177ab89e931fedManman Reninline static bool isRedundantFlagInstr(MachineInstr *CmpI, unsigned SrcReg, 200476c6ccbd4cee0637c961e32435177ab89e931fedManman Ren unsigned SrcReg2, int ImmValue, 200576c6ccbd4cee0637c961e32435177ab89e931fedManman Ren MachineInstr *OI) { 200676c6ccbd4cee0637c961e32435177ab89e931fedManman Ren if ((CmpI->getOpcode() == ARM::CMPrr || 200776c6ccbd4cee0637c961e32435177ab89e931fedManman Ren CmpI->getOpcode() == ARM::t2CMPrr) && 200876c6ccbd4cee0637c961e32435177ab89e931fedManman Ren (OI->getOpcode() == ARM::SUBrr || 200976c6ccbd4cee0637c961e32435177ab89e931fedManman Ren OI->getOpcode() == ARM::t2SUBrr) && 201076c6ccbd4cee0637c961e32435177ab89e931fedManman Ren ((OI->getOperand(1).getReg() == SrcReg && 201176c6ccbd4cee0637c961e32435177ab89e931fedManman Ren OI->getOperand(2).getReg() == SrcReg2) || 201276c6ccbd4cee0637c961e32435177ab89e931fedManman Ren (OI->getOperand(1).getReg() == SrcReg2 && 201376c6ccbd4cee0637c961e32435177ab89e931fedManman Ren OI->getOperand(2).getReg() == SrcReg))) 201476c6ccbd4cee0637c961e32435177ab89e931fedManman Ren return true; 201576c6ccbd4cee0637c961e32435177ab89e931fedManman Ren 201676c6ccbd4cee0637c961e32435177ab89e931fedManman Ren if ((CmpI->getOpcode() == ARM::CMPri || 201776c6ccbd4cee0637c961e32435177ab89e931fedManman Ren CmpI->getOpcode() == ARM::t2CMPri) && 201876c6ccbd4cee0637c961e32435177ab89e931fedManman Ren (OI->getOpcode() == ARM::SUBri || 201976c6ccbd4cee0637c961e32435177ab89e931fedManman Ren OI->getOpcode() == ARM::t2SUBri) && 202076c6ccbd4cee0637c961e32435177ab89e931fedManman Ren OI->getOperand(1).getReg() == SrcReg && 202176c6ccbd4cee0637c961e32435177ab89e931fedManman Ren OI->getOperand(2).getImm() == ImmValue) 202276c6ccbd4cee0637c961e32435177ab89e931fedManman Ren return true; 202376c6ccbd4cee0637c961e32435177ab89e931fedManman Ren return false; 202476c6ccbd4cee0637c961e32435177ab89e931fedManman Ren} 202576c6ccbd4cee0637c961e32435177ab89e931fedManman Ren 2026de7266c611b37ec050efb53b73166081a98cea13Manman Ren/// optimizeCompareInstr - Convert the instruction supplying the argument to the 2027de7266c611b37ec050efb53b73166081a98cea13Manman Ren/// comparison into one that sets the zero bit in the flags register; 2028de7266c611b37ec050efb53b73166081a98cea13Manman Ren/// Remove a redundant Compare instruction if an earlier instruction can set the 2029de7266c611b37ec050efb53b73166081a98cea13Manman Ren/// flags in the same way as Compare. 2030de7266c611b37ec050efb53b73166081a98cea13Manman Ren/// E.g. SUBrr(r1,r2) and CMPrr(r1,r2). We also handle the case where two 2031de7266c611b37ec050efb53b73166081a98cea13Manman Ren/// operands are swapped: SUBrr(r1,r2) and CMPrr(r2,r1), by updating the 2032de7266c611b37ec050efb53b73166081a98cea13Manman Ren/// condition code of instructions which use the flags. 2033e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendlingbool ARMBaseInstrInfo:: 2034de7266c611b37ec050efb53b73166081a98cea13Manman RenoptimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, unsigned SrcReg2, 2035de7266c611b37ec050efb53b73166081a98cea13Manman Ren int CmpMask, int CmpValue, 2036de7266c611b37ec050efb53b73166081a98cea13Manman Ren const MachineRegisterInfo *MRI) const { 203776c6ccbd4cee0637c961e32435177ab89e931fedManman Ren // Get the unique definition of SrcReg. 203876c6ccbd4cee0637c961e32435177ab89e931fedManman Ren MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg); 203976c6ccbd4cee0637c961e32435177ab89e931fedManman Ren if (!MI) return false; 204092ad57f066e9f256e4e3d72febf152e68caa80c7Bill Wendling 204104ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif // Masked compares sometimes use the same register as the corresponding 'and'. 204204ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif if (CmpMask != ~0) { 2043519daf5d2dd80614ac4e529b199e6f3e595bfc80Jakob Stoklund Olesen if (!isSuitableForMask(MI, SrcReg, CmpMask, false) || isPredicated(MI)) { 204404ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif MI = 0; 2045b41ee96d76ccf1eec2fd898def4cfd7c16868708Bill Wendling for (MachineRegisterInfo::use_iterator UI = MRI->use_begin(SrcReg), 2046b41ee96d76ccf1eec2fd898def4cfd7c16868708Bill Wendling UE = MRI->use_end(); UI != UE; ++UI) { 204704ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif if (UI->getParent() != CmpInstr->getParent()) continue; 204805642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif MachineInstr *PotentialAND = &*UI; 2049519daf5d2dd80614ac4e529b199e6f3e595bfc80Jakob Stoklund Olesen if (!isSuitableForMask(PotentialAND, SrcReg, CmpMask, true) || 2050519daf5d2dd80614ac4e529b199e6f3e595bfc80Jakob Stoklund Olesen isPredicated(PotentialAND)) 205104ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif continue; 205205642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif MI = PotentialAND; 205304ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif break; 205404ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif } 205504ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif if (!MI) return false; 205604ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif } 205704ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif } 205804ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif 2059247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren // Get ready to iterate backward from CmpInstr. 2060247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren MachineBasicBlock::iterator I = CmpInstr, E = MI, 2061247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren B = CmpInstr->getParent()->begin(); 20620aa38b9381a5be42abd4f5ca5baa8c2930d148d3Bill Wendling 20630aa38b9381a5be42abd4f5ca5baa8c2930d148d3Bill Wendling // Early exit if CmpInstr is at the beginning of the BB. 20640aa38b9381a5be42abd4f5ca5baa8c2930d148d3Bill Wendling if (I == B) return false; 20650aa38b9381a5be42abd4f5ca5baa8c2930d148d3Bill Wendling 2066247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren // There are two possible candidates which can be changed to set CPSR: 2067247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren // One is MI, the other is a SUB instruction. 2068247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren // For CMPrr(r1,r2), we are looking for SUB(r1,r2) or SUB(r2,r1). 2069247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren // For CMPri(r1, CmpValue), we are looking for SUBri(r1, CmpValue). 2070247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren MachineInstr *Sub = NULL; 2071de7266c611b37ec050efb53b73166081a98cea13Manman Ren if (SrcReg2 != 0) 2072247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren // MI is not a candidate for CMPrr. 2073247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren MI = NULL; 2074de7266c611b37ec050efb53b73166081a98cea13Manman Ren else if (MI->getParent() != CmpInstr->getParent() || CmpValue != 0) { 2075247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren // Conservatively refuse to convert an instruction which isn't in the same 2076247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren // BB as the comparison. 2077247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren // For CMPri, we need to check Sub, thus we can't return here. 20784949e98cccb98abb0ba3f67c22be757d446ab108Manman Ren if (CmpInstr->getOpcode() == ARM::CMPri || 2079247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren CmpInstr->getOpcode() == ARM::t2CMPri) 2080247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren MI = NULL; 2081247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren else 2082247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren return false; 2083247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren } 2084247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren 2085247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren // Check that CPSR isn't set between the comparison instruction and the one we 2086247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren // want to change. At the same time, search for Sub. 208776c6ccbd4cee0637c961e32435177ab89e931fedManman Ren const TargetRegisterInfo *TRI = &getRegisterInfo(); 2088e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling --I; 2089e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling for (; I != E; --I) { 2090e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling const MachineInstr &Instr = *I; 2091e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling 209276c6ccbd4cee0637c961e32435177ab89e931fedManman Ren if (Instr.modifiesRegister(ARM::CPSR, TRI) || 209376c6ccbd4cee0637c961e32435177ab89e931fedManman Ren Instr.readsRegister(ARM::CPSR, TRI)) 209440a5eb18b031fa1a5e9697e21e251e613d441cc5Bill Wendling // This instruction modifies or uses CPSR after the one we want to 209540a5eb18b031fa1a5e9697e21e251e613d441cc5Bill Wendling // change. We can't do this transformation. 209676c6ccbd4cee0637c961e32435177ab89e931fedManman Ren return false; 2097247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren 209876c6ccbd4cee0637c961e32435177ab89e931fedManman Ren // Check whether CmpInstr can be made redundant by the current instruction. 209976c6ccbd4cee0637c961e32435177ab89e931fedManman Ren if (isRedundantFlagInstr(CmpInstr, SrcReg, SrcReg2, CmpValue, &*I)) { 2100247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren Sub = &*I; 2101247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren break; 2102247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren } 2103247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren 2104691e64a54ce899409abe7c131d15ed75e3c1fef5Evan Cheng if (I == B) 2105691e64a54ce899409abe7c131d15ed75e3c1fef5Evan Cheng // The 'and' is below the comparison instruction. 2106691e64a54ce899409abe7c131d15ed75e3c1fef5Evan Cheng return false; 2107e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling } 2108e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling 2109247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren // Return false if no candidates exist. 2110247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren if (!MI && !Sub) 2111247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren return false; 2112247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren 2113247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren // The single candidate is called MI. 2114247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren if (!MI) MI = Sub; 2115247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren 2116519daf5d2dd80614ac4e529b199e6f3e595bfc80Jakob Stoklund Olesen // We can't use a predicated instruction - it doesn't always write the flags. 2117519daf5d2dd80614ac4e529b199e6f3e595bfc80Jakob Stoklund Olesen if (isPredicated(MI)) 2118519daf5d2dd80614ac4e529b199e6f3e595bfc80Jakob Stoklund Olesen return false; 2119519daf5d2dd80614ac4e529b199e6f3e595bfc80Jakob Stoklund Olesen 2120e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling switch (MI->getOpcode()) { 2121e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling default: break; 2122ca3f6a3925e9a6e91022aa211bdc1b6e3f2ff41fCameron Zwarich case ARM::RSBrr: 2123df298c9ea64eb335f63fc075d8ef6306682ffe75Owen Anderson case ARM::RSBri: 2124ca3f6a3925e9a6e91022aa211bdc1b6e3f2ff41fCameron Zwarich case ARM::RSCrr: 2125df298c9ea64eb335f63fc075d8ef6306682ffe75Owen Anderson case ARM::RSCri: 2126ca3f6a3925e9a6e91022aa211bdc1b6e3f2ff41fCameron Zwarich case ARM::ADDrr: 212738ae997e63e3e1bb2c8679e01ea74cf8fd0be893Bill Wendling case ARM::ADDri: 2128ca3f6a3925e9a6e91022aa211bdc1b6e3f2ff41fCameron Zwarich case ARM::ADCrr: 2129df298c9ea64eb335f63fc075d8ef6306682ffe75Owen Anderson case ARM::ADCri: 2130ca3f6a3925e9a6e91022aa211bdc1b6e3f2ff41fCameron Zwarich case ARM::SUBrr: 213138ae997e63e3e1bb2c8679e01ea74cf8fd0be893Bill Wendling case ARM::SUBri: 2132ca3f6a3925e9a6e91022aa211bdc1b6e3f2ff41fCameron Zwarich case ARM::SBCrr: 2133df298c9ea64eb335f63fc075d8ef6306682ffe75Owen Anderson case ARM::SBCri: 2134df298c9ea64eb335f63fc075d8ef6306682ffe75Owen Anderson case ARM::t2RSBri: 2135ca3f6a3925e9a6e91022aa211bdc1b6e3f2ff41fCameron Zwarich case ARM::t2ADDrr: 213638ae997e63e3e1bb2c8679e01ea74cf8fd0be893Bill Wendling case ARM::t2ADDri: 2137ca3f6a3925e9a6e91022aa211bdc1b6e3f2ff41fCameron Zwarich case ARM::t2ADCrr: 2138df298c9ea64eb335f63fc075d8ef6306682ffe75Owen Anderson case ARM::t2ADCri: 2139ca3f6a3925e9a6e91022aa211bdc1b6e3f2ff41fCameron Zwarich case ARM::t2SUBrr: 2140df298c9ea64eb335f63fc075d8ef6306682ffe75Owen Anderson case ARM::t2SUBri: 2141ca3f6a3925e9a6e91022aa211bdc1b6e3f2ff41fCameron Zwarich case ARM::t2SBCrr: 2142b485de5d8c3fe0c62c0b07f63f64bd10f6803c17Cameron Zwarich case ARM::t2SBCri: 2143b485de5d8c3fe0c62c0b07f63f64bd10f6803c17Cameron Zwarich case ARM::ANDrr: 2144b485de5d8c3fe0c62c0b07f63f64bd10f6803c17Cameron Zwarich case ARM::ANDri: 2145b485de5d8c3fe0c62c0b07f63f64bd10f6803c17Cameron Zwarich case ARM::t2ANDrr: 21460cb11ac32fc09c5db42fb801db242ac9fb51f6b1Cameron Zwarich case ARM::t2ANDri: 21470cb11ac32fc09c5db42fb801db242ac9fb51f6b1Cameron Zwarich case ARM::ORRrr: 21480cb11ac32fc09c5db42fb801db242ac9fb51f6b1Cameron Zwarich case ARM::ORRri: 21490cb11ac32fc09c5db42fb801db242ac9fb51f6b1Cameron Zwarich case ARM::t2ORRrr: 21500cb11ac32fc09c5db42fb801db242ac9fb51f6b1Cameron Zwarich case ARM::t2ORRri: 21510cb11ac32fc09c5db42fb801db242ac9fb51f6b1Cameron Zwarich case ARM::EORrr: 21520cb11ac32fc09c5db42fb801db242ac9fb51f6b1Cameron Zwarich case ARM::EORri: 21530cb11ac32fc09c5db42fb801db242ac9fb51f6b1Cameron Zwarich case ARM::t2EORrr: 21540cb11ac32fc09c5db42fb801db242ac9fb51f6b1Cameron Zwarich case ARM::t2EORri: { 2155247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren // Scan forward for the use of CPSR 2156247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren // When checking against MI: if it's a conditional code requires 215745ed19499b8f7025d9acf91cc37fbf6ea63abc4fManman Ren // checking of V bit, then this is not safe to do. 215845ed19499b8f7025d9acf91cc37fbf6ea63abc4fManman Ren // It is safe to remove CmpInstr if CPSR is redefined or killed. 215945ed19499b8f7025d9acf91cc37fbf6ea63abc4fManman Ren // If we are done with the basic block, we need to check whether CPSR is 216045ed19499b8f7025d9acf91cc37fbf6ea63abc4fManman Ren // live-out. 216176c6ccbd4cee0637c961e32435177ab89e931fedManman Ren SmallVector<std::pair<MachineOperand*, ARMCC::CondCodes>, 4> 216276c6ccbd4cee0637c961e32435177ab89e931fedManman Ren OperandsToUpdate; 21632c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng bool isSafe = false; 21642c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng I = CmpInstr; 2165247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren E = CmpInstr->getParent()->end(); 21662c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng while (!isSafe && ++I != E) { 21672c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng const MachineInstr &Instr = *I; 21682c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng for (unsigned IO = 0, EO = Instr.getNumOperands(); 21692c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng !isSafe && IO != EO; ++IO) { 21702c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng const MachineOperand &MO = Instr.getOperand(IO); 21712420b558de5d291d8503c1339004e5b5bf99a48aJakob Stoklund Olesen if (MO.isRegMask() && MO.clobbersPhysReg(ARM::CPSR)) { 21722420b558de5d291d8503c1339004e5b5bf99a48aJakob Stoklund Olesen isSafe = true; 21732420b558de5d291d8503c1339004e5b5bf99a48aJakob Stoklund Olesen break; 21742420b558de5d291d8503c1339004e5b5bf99a48aJakob Stoklund Olesen } 21752c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng if (!MO.isReg() || MO.getReg() != ARM::CPSR) 21762c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng continue; 21772c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng if (MO.isDef()) { 21782c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng isSafe = true; 21792c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng break; 21802c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng } 21812c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng // Condition code is after the operand before CPSR. 21822c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng ARMCC::CondCodes CC = (ARMCC::CondCodes)Instr.getOperand(IO-1).getImm(); 218376c6ccbd4cee0637c961e32435177ab89e931fedManman Ren if (Sub) { 218476c6ccbd4cee0637c961e32435177ab89e931fedManman Ren ARMCC::CondCodes NewCC = getSwappedCondition(CC); 218576c6ccbd4cee0637c961e32435177ab89e931fedManman Ren if (NewCC == ARMCC::AL) 2186247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren return false; 218776c6ccbd4cee0637c961e32435177ab89e931fedManman Ren // If we have SUB(r1, r2) and CMP(r2, r1), the condition code based 218876c6ccbd4cee0637c961e32435177ab89e931fedManman Ren // on CMP needs to be updated to be based on SUB. 218976c6ccbd4cee0637c961e32435177ab89e931fedManman Ren // Push the condition code operands to OperandsToUpdate. 219076c6ccbd4cee0637c961e32435177ab89e931fedManman Ren // If it is safe to remove CmpInstr, the condition code of these 219176c6ccbd4cee0637c961e32435177ab89e931fedManman Ren // operands will be modified. 219276c6ccbd4cee0637c961e32435177ab89e931fedManman Ren if (SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 && 219376c6ccbd4cee0637c961e32435177ab89e931fedManman Ren Sub->getOperand(2).getReg() == SrcReg) 219476c6ccbd4cee0637c961e32435177ab89e931fedManman Ren OperandsToUpdate.push_back(std::make_pair(&((*I).getOperand(IO-1)), 219576c6ccbd4cee0637c961e32435177ab89e931fedManman Ren NewCC)); 219676c6ccbd4cee0637c961e32435177ab89e931fedManman Ren } 2197247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren else 2198247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren switch (CC) { 2199247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren default: 22009af64303fa887a3d9b75e715787ba587c3f18139Manman Ren // CPSR can be used multiple times, we should continue. 2201247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren break; 2202247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren case ARMCC::VS: 2203247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren case ARMCC::VC: 2204247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren case ARMCC::GE: 2205247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren case ARMCC::LT: 2206247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren case ARMCC::GT: 2207247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren case ARMCC::LE: 2208247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren return false; 2209247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren } 22102c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng } 22112c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng } 22122c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng 221345ed19499b8f7025d9acf91cc37fbf6ea63abc4fManman Ren // If CPSR is not killed nor re-defined, we should check whether it is 221445ed19499b8f7025d9acf91cc37fbf6ea63abc4fManman Ren // live-out. If it is live-out, do not optimize. 221545ed19499b8f7025d9acf91cc37fbf6ea63abc4fManman Ren if (!isSafe) { 221645ed19499b8f7025d9acf91cc37fbf6ea63abc4fManman Ren MachineBasicBlock *MBB = CmpInstr->getParent(); 221745ed19499b8f7025d9acf91cc37fbf6ea63abc4fManman Ren for (MachineBasicBlock::succ_iterator SI = MBB->succ_begin(), 221845ed19499b8f7025d9acf91cc37fbf6ea63abc4fManman Ren SE = MBB->succ_end(); SI != SE; ++SI) 221945ed19499b8f7025d9acf91cc37fbf6ea63abc4fManman Ren if ((*SI)->isLiveIn(ARM::CPSR)) 222045ed19499b8f7025d9acf91cc37fbf6ea63abc4fManman Ren return false; 222145ed19499b8f7025d9acf91cc37fbf6ea63abc4fManman Ren } 22222c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng 22233642e64c114e636548888c72c21ae023ee0121a7Evan Cheng // Toggle the optional operand to CPSR. 22243642e64c114e636548888c72c21ae023ee0121a7Evan Cheng MI->getOperand(5).setReg(ARM::CPSR); 22253642e64c114e636548888c72c21ae023ee0121a7Evan Cheng MI->getOperand(5).setIsDef(true); 2226519daf5d2dd80614ac4e529b199e6f3e595bfc80Jakob Stoklund Olesen assert(!isPredicated(MI) && "Can't use flags from predicated instruction"); 2227e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling CmpInstr->eraseFromParent(); 2228247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren 2229247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren // Modify the condition code of operands in OperandsToUpdate. 2230247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren // Since we have SUB(r1, r2) and CMP(r2, r1), the condition code needs to 2231247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren // be changed from r2 > r1 to r1 < r2, from r2 < r1 to r1 > r2, etc. 223276c6ccbd4cee0637c961e32435177ab89e931fedManman Ren for (unsigned i = 0, e = OperandsToUpdate.size(); i < e; i++) 223376c6ccbd4cee0637c961e32435177ab89e931fedManman Ren OperandsToUpdate[i].first->setImm(OperandsToUpdate[i].second); 2234e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling return true; 2235e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling } 2236b485de5d8c3fe0c62c0b07f63f64bd10f6803c17Cameron Zwarich } 2237e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling 2238e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling return false; 2239e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling} 22405f54ce347368105260be2cec497b6a4199dc5789Evan Cheng 2241c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Chengbool ARMBaseInstrInfo::FoldImmediate(MachineInstr *UseMI, 2242c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng MachineInstr *DefMI, unsigned Reg, 2243c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng MachineRegisterInfo *MRI) const { 2244c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng // Fold large immediates into add, sub, or, xor. 2245c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng unsigned DefOpc = DefMI->getOpcode(); 2246c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng if (DefOpc != ARM::t2MOVi32imm && DefOpc != ARM::MOVi32imm) 2247c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng return false; 2248c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng if (!DefMI->getOperand(1).isImm()) 2249c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng // Could be t2MOVi32imm <ga:xx> 2250c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng return false; 2251c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng 2252c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng if (!MRI->hasOneNonDBGUse(Reg)) 2253c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng return false; 2254c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng 2255e279f5953e9c3d934248cd4d2f24b6179ad9d2e6Evan Cheng const MCInstrDesc &DefMCID = DefMI->getDesc(); 2256e279f5953e9c3d934248cd4d2f24b6179ad9d2e6Evan Cheng if (DefMCID.hasOptionalDef()) { 2257e279f5953e9c3d934248cd4d2f24b6179ad9d2e6Evan Cheng unsigned NumOps = DefMCID.getNumOperands(); 2258e279f5953e9c3d934248cd4d2f24b6179ad9d2e6Evan Cheng const MachineOperand &MO = DefMI->getOperand(NumOps-1); 2259e279f5953e9c3d934248cd4d2f24b6179ad9d2e6Evan Cheng if (MO.getReg() == ARM::CPSR && !MO.isDead()) 2260e279f5953e9c3d934248cd4d2f24b6179ad9d2e6Evan Cheng // If DefMI defines CPSR and it is not dead, it's obviously not safe 2261e279f5953e9c3d934248cd4d2f24b6179ad9d2e6Evan Cheng // to delete DefMI. 2262e279f5953e9c3d934248cd4d2f24b6179ad9d2e6Evan Cheng return false; 2263e279f5953e9c3d934248cd4d2f24b6179ad9d2e6Evan Cheng } 2264e279f5953e9c3d934248cd4d2f24b6179ad9d2e6Evan Cheng 2265e279f5953e9c3d934248cd4d2f24b6179ad9d2e6Evan Cheng const MCInstrDesc &UseMCID = UseMI->getDesc(); 2266e279f5953e9c3d934248cd4d2f24b6179ad9d2e6Evan Cheng if (UseMCID.hasOptionalDef()) { 2267e279f5953e9c3d934248cd4d2f24b6179ad9d2e6Evan Cheng unsigned NumOps = UseMCID.getNumOperands(); 2268e279f5953e9c3d934248cd4d2f24b6179ad9d2e6Evan Cheng if (UseMI->getOperand(NumOps-1).getReg() == ARM::CPSR) 2269e279f5953e9c3d934248cd4d2f24b6179ad9d2e6Evan Cheng // If the instruction sets the flag, do not attempt this optimization 2270e279f5953e9c3d934248cd4d2f24b6179ad9d2e6Evan Cheng // since it may change the semantics of the code. 2271e279f5953e9c3d934248cd4d2f24b6179ad9d2e6Evan Cheng return false; 2272e279f5953e9c3d934248cd4d2f24b6179ad9d2e6Evan Cheng } 2273e279f5953e9c3d934248cd4d2f24b6179ad9d2e6Evan Cheng 2274c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng unsigned UseOpc = UseMI->getOpcode(); 22755c71c7a13715ed6f5bfdd5497172ddec316b68b0Evan Cheng unsigned NewUseOpc = 0; 2276c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng uint32_t ImmVal = (uint32_t)DefMI->getOperand(1).getImm(); 22775c71c7a13715ed6f5bfdd5497172ddec316b68b0Evan Cheng uint32_t SOImmValV1 = 0, SOImmValV2 = 0; 2278c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng bool Commute = false; 2279c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng switch (UseOpc) { 2280c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng default: return false; 2281c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::SUBrr: 2282c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::ADDrr: 2283c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::ORRrr: 2284c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::EORrr: 2285c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::t2SUBrr: 2286c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::t2ADDrr: 2287c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::t2ORRrr: 2288c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::t2EORrr: { 2289c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng Commute = UseMI->getOperand(2).getReg() != Reg; 2290c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng switch (UseOpc) { 2291c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng default: break; 2292c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::SUBrr: { 2293c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng if (Commute) 2294c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng return false; 2295c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng ImmVal = -ImmVal; 2296c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng NewUseOpc = ARM::SUBri; 2297c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng // Fallthrough 2298c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng } 2299c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::ADDrr: 2300c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::ORRrr: 2301c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::EORrr: { 2302c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng if (!ARM_AM::isSOImmTwoPartVal(ImmVal)) 2303c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng return false; 2304c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng SOImmValV1 = (uint32_t)ARM_AM::getSOImmTwoPartFirst(ImmVal); 2305c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng SOImmValV2 = (uint32_t)ARM_AM::getSOImmTwoPartSecond(ImmVal); 2306c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng switch (UseOpc) { 2307c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng default: break; 2308c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::ADDrr: NewUseOpc = ARM::ADDri; break; 2309c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::ORRrr: NewUseOpc = ARM::ORRri; break; 2310c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::EORrr: NewUseOpc = ARM::EORri; break; 2311c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng } 2312c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng break; 2313c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng } 2314c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::t2SUBrr: { 2315c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng if (Commute) 2316c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng return false; 2317c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng ImmVal = -ImmVal; 2318c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng NewUseOpc = ARM::t2SUBri; 2319c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng // Fallthrough 2320c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng } 2321c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::t2ADDrr: 2322c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::t2ORRrr: 2323c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::t2EORrr: { 2324c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng if (!ARM_AM::isT2SOImmTwoPartVal(ImmVal)) 2325c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng return false; 2326c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng SOImmValV1 = (uint32_t)ARM_AM::getT2SOImmTwoPartFirst(ImmVal); 2327c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng SOImmValV2 = (uint32_t)ARM_AM::getT2SOImmTwoPartSecond(ImmVal); 2328c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng switch (UseOpc) { 2329c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng default: break; 2330c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::t2ADDrr: NewUseOpc = ARM::t2ADDri; break; 2331c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::t2ORRrr: NewUseOpc = ARM::t2ORRri; break; 2332c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::t2EORrr: NewUseOpc = ARM::t2EORri; break; 2333c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng } 2334c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng break; 2335c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng } 2336c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng } 2337c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng } 2338c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng } 2339c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng 2340c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng unsigned OpIdx = Commute ? 2 : 1; 2341c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng unsigned Reg1 = UseMI->getOperand(OpIdx).getReg(); 2342c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng bool isKill = UseMI->getOperand(OpIdx).isKill(); 2343c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng unsigned NewReg = MRI->createVirtualRegister(MRI->getRegClass(Reg)); 2344c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng AddDefaultCC(AddDefaultPred(BuildMI(*UseMI->getParent(), 2345ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng UseMI, UseMI->getDebugLoc(), 2346c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng get(NewUseOpc), NewReg) 2347c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng .addReg(Reg1, getKillRegState(isKill)) 2348c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng .addImm(SOImmValV1))); 2349c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng UseMI->setDesc(get(NewUseOpc)); 2350c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng UseMI->getOperand(1).setReg(NewReg); 2351c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng UseMI->getOperand(1).setIsKill(); 2352c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng UseMI->getOperand(2).ChangeToImmediate(SOImmValV2); 2353c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng DefMI->eraseFromParent(); 2354c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng return true; 2355c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng} 2356c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng 2357eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilsonstatic unsigned getNumMicroOpsSwiftLdSt(const InstrItineraryData *ItinData, 2358eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson const MachineInstr *MI) { 2359eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson switch (MI->getOpcode()) { 2360eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson default: { 2361eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson const MCInstrDesc &Desc = MI->getDesc(); 2362eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson int UOps = ItinData->getNumMicroOps(Desc.getSchedClass()); 2363eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson assert(UOps >= 0 && "bad # UOps"); 2364eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson return UOps; 2365eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson } 2366eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson 2367eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::LDRrs: 2368eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::LDRBrs: 2369eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::STRrs: 2370eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::STRBrs: { 2371eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson unsigned ShOpVal = MI->getOperand(3).getImm(); 2372eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson bool isSub = ARM_AM::getAM2Op(ShOpVal) == ARM_AM::sub; 2373eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal); 2374eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson if (!isSub && 2375eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson (ShImm == 0 || 2376eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson ((ShImm == 1 || ShImm == 2 || ShImm == 3) && 2377eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl))) 2378eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson return 1; 2379eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson return 2; 2380eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson } 2381eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson 2382eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::LDRH: 2383eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::STRH: { 2384eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson if (!MI->getOperand(2).getReg()) 2385eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson return 1; 2386eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson 2387eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson unsigned ShOpVal = MI->getOperand(3).getImm(); 2388eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson bool isSub = ARM_AM::getAM2Op(ShOpVal) == ARM_AM::sub; 2389eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal); 2390eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson if (!isSub && 2391eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson (ShImm == 0 || 2392eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson ((ShImm == 1 || ShImm == 2 || ShImm == 3) && 2393eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl))) 2394eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson return 1; 2395eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson return 2; 2396eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson } 2397eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson 2398eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::LDRSB: 2399eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::LDRSH: 2400eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson return (ARM_AM::getAM3Op(MI->getOperand(3).getImm()) == ARM_AM::sub) ? 3:2; 2401eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson 2402eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::LDRSB_POST: 2403eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::LDRSH_POST: { 2404eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson unsigned Rt = MI->getOperand(0).getReg(); 2405eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson unsigned Rm = MI->getOperand(3).getReg(); 2406eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson return (Rt == Rm) ? 4 : 3; 2407eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson } 2408eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson 2409eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::LDR_PRE_REG: 2410eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::LDRB_PRE_REG: { 2411eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson unsigned Rt = MI->getOperand(0).getReg(); 2412eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson unsigned Rm = MI->getOperand(3).getReg(); 2413eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson if (Rt == Rm) 2414eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson return 3; 2415eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson unsigned ShOpVal = MI->getOperand(4).getImm(); 2416eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson bool isSub = ARM_AM::getAM2Op(ShOpVal) == ARM_AM::sub; 2417eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal); 2418eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson if (!isSub && 2419eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson (ShImm == 0 || 2420eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson ((ShImm == 1 || ShImm == 2 || ShImm == 3) && 2421eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl))) 2422eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson return 2; 2423eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson return 3; 2424eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson } 2425eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson 2426eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::STR_PRE_REG: 2427eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::STRB_PRE_REG: { 2428eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson unsigned ShOpVal = MI->getOperand(4).getImm(); 2429eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson bool isSub = ARM_AM::getAM2Op(ShOpVal) == ARM_AM::sub; 2430eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal); 2431eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson if (!isSub && 2432eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson (ShImm == 0 || 2433eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson ((ShImm == 1 || ShImm == 2 || ShImm == 3) && 2434eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl))) 2435eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson return 2; 2436eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson return 3; 2437eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson } 2438eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson 2439eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::LDRH_PRE: 2440eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::STRH_PRE: { 2441eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson unsigned Rt = MI->getOperand(0).getReg(); 2442eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson unsigned Rm = MI->getOperand(3).getReg(); 2443eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson if (!Rm) 2444eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson return 2; 2445eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson if (Rt == Rm) 2446eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson return 3; 2447eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson return (ARM_AM::getAM3Op(MI->getOperand(4).getImm()) == ARM_AM::sub) 2448eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson ? 3 : 2; 2449eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson } 2450eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson 2451eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::LDR_POST_REG: 2452eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::LDRB_POST_REG: 2453eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::LDRH_POST: { 2454eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson unsigned Rt = MI->getOperand(0).getReg(); 2455eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson unsigned Rm = MI->getOperand(3).getReg(); 2456eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson return (Rt == Rm) ? 3 : 2; 2457eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson } 2458eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson 2459eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::LDR_PRE_IMM: 2460eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::LDRB_PRE_IMM: 2461eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::LDR_POST_IMM: 2462eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::LDRB_POST_IMM: 2463eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::STRB_POST_IMM: 2464eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::STRB_POST_REG: 2465eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::STRB_PRE_IMM: 2466eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::STRH_POST: 2467eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::STR_POST_IMM: 2468eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::STR_POST_REG: 2469eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::STR_PRE_IMM: 2470eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson return 2; 2471eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson 2472eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::LDRSB_PRE: 2473eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::LDRSH_PRE: { 2474eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson unsigned Rm = MI->getOperand(3).getReg(); 2475eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson if (Rm == 0) 2476eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson return 3; 2477eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson unsigned Rt = MI->getOperand(0).getReg(); 2478eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson if (Rt == Rm) 2479eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson return 4; 2480eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson unsigned ShOpVal = MI->getOperand(4).getImm(); 2481eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson bool isSub = ARM_AM::getAM2Op(ShOpVal) == ARM_AM::sub; 2482eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal); 2483eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson if (!isSub && 2484eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson (ShImm == 0 || 2485eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson ((ShImm == 1 || ShImm == 2 || ShImm == 3) && 2486eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl))) 2487eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson return 3; 2488eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson return 4; 2489eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson } 2490eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson 2491eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::LDRD: { 2492eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson unsigned Rt = MI->getOperand(0).getReg(); 2493eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson unsigned Rn = MI->getOperand(2).getReg(); 2494eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson unsigned Rm = MI->getOperand(3).getReg(); 2495eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson if (Rm) 2496eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson return (ARM_AM::getAM3Op(MI->getOperand(4).getImm()) == ARM_AM::sub) ?4:3; 2497eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson return (Rt == Rn) ? 3 : 2; 2498eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson } 2499eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson 2500eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::STRD: { 2501eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson unsigned Rm = MI->getOperand(3).getReg(); 2502eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson if (Rm) 2503eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson return (ARM_AM::getAM3Op(MI->getOperand(4).getImm()) == ARM_AM::sub) ?4:3; 2504eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson return 2; 2505eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson } 2506eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson 2507eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::LDRD_POST: 2508eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::t2LDRD_POST: 2509eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson return 3; 2510eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson 2511eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::STRD_POST: 2512eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::t2STRD_POST: 2513eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson return 4; 2514eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson 2515eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::LDRD_PRE: { 2516eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson unsigned Rt = MI->getOperand(0).getReg(); 2517eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson unsigned Rn = MI->getOperand(3).getReg(); 2518eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson unsigned Rm = MI->getOperand(4).getReg(); 2519eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson if (Rm) 2520eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson return (ARM_AM::getAM3Op(MI->getOperand(5).getImm()) == ARM_AM::sub) ?5:4; 2521eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson return (Rt == Rn) ? 4 : 3; 2522eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson } 2523eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson 2524eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::t2LDRD_PRE: { 2525eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson unsigned Rt = MI->getOperand(0).getReg(); 2526eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson unsigned Rn = MI->getOperand(3).getReg(); 2527eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson return (Rt == Rn) ? 4 : 3; 2528eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson } 2529eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson 2530eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::STRD_PRE: { 2531eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson unsigned Rm = MI->getOperand(4).getReg(); 2532eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson if (Rm) 2533eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson return (ARM_AM::getAM3Op(MI->getOperand(5).getImm()) == ARM_AM::sub) ?5:4; 2534eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson return 3; 2535eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson } 2536eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson 2537eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::t2STRD_PRE: 2538eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson return 3; 2539eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson 2540eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::t2LDR_POST: 2541eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::t2LDRB_POST: 2542eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::t2LDRB_PRE: 2543eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::t2LDRSBi12: 2544eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::t2LDRSBi8: 2545eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::t2LDRSBpci: 2546eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::t2LDRSBs: 2547eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::t2LDRH_POST: 2548eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::t2LDRH_PRE: 2549eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::t2LDRSBT: 2550eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::t2LDRSB_POST: 2551eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::t2LDRSB_PRE: 2552eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::t2LDRSH_POST: 2553eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::t2LDRSH_PRE: 2554eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::t2LDRSHi12: 2555eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::t2LDRSHi8: 2556eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::t2LDRSHpci: 2557eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::t2LDRSHs: 2558eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson return 2; 2559eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson 2560eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::t2LDRDi8: { 2561eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson unsigned Rt = MI->getOperand(0).getReg(); 2562eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson unsigned Rn = MI->getOperand(2).getReg(); 2563eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson return (Rt == Rn) ? 3 : 2; 2564eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson } 2565eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson 2566eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::t2STRB_POST: 2567eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::t2STRB_PRE: 2568eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::t2STRBs: 2569eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::t2STRDi8: 2570eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::t2STRH_POST: 2571eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::t2STRH_PRE: 2572eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::t2STRHs: 2573eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::t2STR_POST: 2574eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::t2STR_PRE: 2575eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::t2STRs: 2576eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson return 2; 2577eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson } 2578eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson} 2579eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson 25809eed53379f19f836769a0c4a14042eeb1b587769Andrew Trick// Return the number of 32-bit words loaded by LDM or stored by STM. If this 25819eed53379f19f836769a0c4a14042eeb1b587769Andrew Trick// can't be easily determined return 0 (missing MachineMemOperand). 25829eed53379f19f836769a0c4a14042eeb1b587769Andrew Trick// 25839eed53379f19f836769a0c4a14042eeb1b587769Andrew Trick// FIXME: The current MachineInstr design does not support relying on machine 25849eed53379f19f836769a0c4a14042eeb1b587769Andrew Trick// mem operands to determine the width of a memory access. Instead, we expect 25859eed53379f19f836769a0c4a14042eeb1b587769Andrew Trick// the target to provide this information based on the instruction opcode and 25869eed53379f19f836769a0c4a14042eeb1b587769Andrew Trick// operands. However, using MachineMemOperand is a the best solution now for 25879eed53379f19f836769a0c4a14042eeb1b587769Andrew Trick// two reasons: 25889eed53379f19f836769a0c4a14042eeb1b587769Andrew Trick// 25899eed53379f19f836769a0c4a14042eeb1b587769Andrew Trick// 1) getNumMicroOps tries to infer LDM memory width from the total number of MI 25909eed53379f19f836769a0c4a14042eeb1b587769Andrew Trick// operands. This is much more dangerous than using the MachineMemOperand 25919eed53379f19f836769a0c4a14042eeb1b587769Andrew Trick// sizes because CodeGen passes can insert/remove optional machine operands. In 25929eed53379f19f836769a0c4a14042eeb1b587769Andrew Trick// fact, it's totally incorrect for preRA passes and appears to be wrong for 25939eed53379f19f836769a0c4a14042eeb1b587769Andrew Trick// postRA passes as well. 25949eed53379f19f836769a0c4a14042eeb1b587769Andrew Trick// 25959eed53379f19f836769a0c4a14042eeb1b587769Andrew Trick// 2) getNumLDMAddresses is only used by the scheduling machine model and any 25969eed53379f19f836769a0c4a14042eeb1b587769Andrew Trick// machine model that calls this should handle the unknown (zero size) case. 25979eed53379f19f836769a0c4a14042eeb1b587769Andrew Trick// 25989eed53379f19f836769a0c4a14042eeb1b587769Andrew Trick// Long term, we should require a target hook that verifies MachineMemOperand 25999eed53379f19f836769a0c4a14042eeb1b587769Andrew Trick// sizes during MC lowering. That target hook should be local to MC lowering 26009eed53379f19f836769a0c4a14042eeb1b587769Andrew Trick// because we can't ensure that it is aware of other MI forms. Doing this will 26019eed53379f19f836769a0c4a14042eeb1b587769Andrew Trick// ensure that MachineMemOperands are correctly propagated through all passes. 26029eed53379f19f836769a0c4a14042eeb1b587769Andrew Trickunsigned ARMBaseInstrInfo::getNumLDMAddresses(const MachineInstr *MI) const { 26039eed53379f19f836769a0c4a14042eeb1b587769Andrew Trick unsigned Size = 0; 26049eed53379f19f836769a0c4a14042eeb1b587769Andrew Trick for (MachineInstr::mmo_iterator I = MI->memoperands_begin(), 26059eed53379f19f836769a0c4a14042eeb1b587769Andrew Trick E = MI->memoperands_end(); I != E; ++I) { 26069eed53379f19f836769a0c4a14042eeb1b587769Andrew Trick Size += (*I)->getSize(); 26079eed53379f19f836769a0c4a14042eeb1b587769Andrew Trick } 26089eed53379f19f836769a0c4a14042eeb1b587769Andrew Trick return Size / 4; 26099eed53379f19f836769a0c4a14042eeb1b587769Andrew Trick} 26109eed53379f19f836769a0c4a14042eeb1b587769Andrew Trick 26115f54ce347368105260be2cec497b6a4199dc5789Evan Chengunsigned 26128239daf7c83a65a189c352cce3191cdc3bbfe151Evan ChengARMBaseInstrInfo::getNumMicroOps(const InstrItineraryData *ItinData, 26138239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng const MachineInstr *MI) const { 26143ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng if (!ItinData || ItinData->isEmpty()) 26155f54ce347368105260be2cec497b6a4199dc5789Evan Cheng return 1; 26165f54ce347368105260be2cec497b6a4199dc5789Evan Cheng 2617e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng const MCInstrDesc &Desc = MI->getDesc(); 26185f54ce347368105260be2cec497b6a4199dc5789Evan Cheng unsigned Class = Desc.getSchedClass(); 2619218ee74a011c0d350099c452810da0bd57a15047Andrew Trick int ItinUOps = ItinData->getNumMicroOps(Class); 2620eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson if (ItinUOps >= 0) { 2621eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson if (Subtarget.isSwift() && (Desc.mayLoad() || Desc.mayStore())) 2622eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson return getNumMicroOpsSwiftLdSt(ItinData, MI); 2623eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson 2624218ee74a011c0d350099c452810da0bd57a15047Andrew Trick return ItinUOps; 2625eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson } 26265f54ce347368105260be2cec497b6a4199dc5789Evan Cheng 26275f54ce347368105260be2cec497b6a4199dc5789Evan Cheng unsigned Opc = MI->getOpcode(); 26285f54ce347368105260be2cec497b6a4199dc5789Evan Cheng switch (Opc) { 26295f54ce347368105260be2cec497b6a4199dc5789Evan Cheng default: 26305f54ce347368105260be2cec497b6a4199dc5789Evan Cheng llvm_unreachable("Unexpected multi-uops instruction!"); 263173fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMQIA: 263273fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMQIA: 26335f54ce347368105260be2cec497b6a4199dc5789Evan Cheng return 2; 26345f54ce347368105260be2cec497b6a4199dc5789Evan Cheng 26355f54ce347368105260be2cec497b6a4199dc5789Evan Cheng // The number of uOps for load / store multiple are determined by the number 26365f54ce347368105260be2cec497b6a4199dc5789Evan Cheng // registers. 26376e8f4c404825b79f9b9176483653f1aa927dfbdeAndrew Trick // 26383ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng // On Cortex-A8, each pair of register loads / stores can be scheduled on the 26393ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng // same cycle. The scheduling for the first load / store must be done 2640c8e41c591741b3da1077f7000274ad040bef8002Sylvestre Ledru // separately by assuming the address is not 64-bit aligned. 264173fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling // 26423ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng // On Cortex-A9, the formula is simply (#reg / 2) + (#reg % 2). If the address 264373fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling // is not 64-bit aligned, then AGU would take an extra cycle. For VFP / NEON 264473fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling // load / store multiple, the formula is (#reg / 2) + (#reg % 2) + 1. 264573fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMDIA: 264673fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMDIA_UPD: 264773fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMDDB_UPD: 264873fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMSIA: 264973fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMSIA_UPD: 265073fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMSDB_UPD: 265173fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMDIA: 265273fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMDIA_UPD: 265373fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMDDB_UPD: 265473fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMSIA: 265573fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMSIA_UPD: 265673fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMSDB_UPD: { 26575f54ce347368105260be2cec497b6a4199dc5789Evan Cheng unsigned NumRegs = MI->getNumOperands() - Desc.getNumOperands(); 26585f54ce347368105260be2cec497b6a4199dc5789Evan Cheng return (NumRegs / 2) + (NumRegs % 2) + 1; 26595f54ce347368105260be2cec497b6a4199dc5789Evan Cheng } 266073fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling 266173fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMIA_RET: 266273fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMIA: 266373fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMDA: 266473fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMDB: 266573fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMIB: 266673fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMIA_UPD: 266773fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMDA_UPD: 266873fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMDB_UPD: 266973fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMIB_UPD: 267073fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::STMIA: 267173fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::STMDA: 267273fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::STMDB: 267373fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::STMIB: 267473fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::STMIA_UPD: 267573fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::STMDA_UPD: 267673fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::STMDB_UPD: 267773fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::STMIB_UPD: 267873fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::tLDMIA: 267973fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::tLDMIA_UPD: 268073fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::tSTMIA_UPD: 26815f54ce347368105260be2cec497b6a4199dc5789Evan Cheng case ARM::tPOP_RET: 26825f54ce347368105260be2cec497b6a4199dc5789Evan Cheng case ARM::tPOP: 26835f54ce347368105260be2cec497b6a4199dc5789Evan Cheng case ARM::tPUSH: 268473fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2LDMIA_RET: 268573fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2LDMIA: 268673fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2LDMDB: 268773fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2LDMIA_UPD: 268873fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2LDMDB_UPD: 268973fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2STMIA: 269073fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2STMDB: 269173fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2STMIA_UPD: 269273fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2STMDB_UPD: { 26933ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng unsigned NumRegs = MI->getNumOperands() - Desc.getNumOperands() + 1; 2694eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson if (Subtarget.isSwift()) { 2695eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson // rdar://8402126 2696eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson int UOps = 1 + NumRegs; // One for address computation, one for each ld / st. 2697eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson switch (Opc) { 2698eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson default: break; 2699eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::VLDMDIA_UPD: 2700eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::VLDMDDB_UPD: 2701eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::VLDMSIA_UPD: 2702eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::VLDMSDB_UPD: 2703eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::VSTMDIA_UPD: 2704eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::VSTMDDB_UPD: 2705eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::VSTMSIA_UPD: 2706eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::VSTMSDB_UPD: 2707eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::LDMIA_UPD: 2708eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::LDMDA_UPD: 2709eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::LDMDB_UPD: 2710eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::LDMIB_UPD: 2711eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::STMIA_UPD: 2712eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::STMDA_UPD: 2713eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::STMDB_UPD: 2714eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::STMIB_UPD: 2715eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::tLDMIA_UPD: 2716eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::tSTMIA_UPD: 2717eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::t2LDMIA_UPD: 2718eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::t2LDMDB_UPD: 2719eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::t2STMIA_UPD: 2720eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::t2STMDB_UPD: 2721eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson ++UOps; // One for base register writeback. 2722eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson break; 2723eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::LDMIA_RET: 2724eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::tPOP_RET: 2725eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::t2LDMIA_RET: 2726eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson UOps += 2; // One for base reg wb, one for write to pc. 2727eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson break; 2728eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson } 2729eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson return UOps; 2730eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson } else if (Subtarget.isCortexA8()) { 27318239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng if (NumRegs < 4) 27328239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng return 2; 27338239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng // 4 registers would be issued: 2, 2. 27348239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng // 5 registers would be issued: 2, 2, 1. 2735218ee74a011c0d350099c452810da0bd57a15047Andrew Trick int A8UOps = (NumRegs / 2); 27368239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng if (NumRegs % 2) 2737218ee74a011c0d350099c452810da0bd57a15047Andrew Trick ++A8UOps; 2738218ee74a011c0d350099c452810da0bd57a15047Andrew Trick return A8UOps; 2739eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson } else if (Subtarget.isLikeA9() || Subtarget.isSwift()) { 2740218ee74a011c0d350099c452810da0bd57a15047Andrew Trick int A9UOps = (NumRegs / 2); 27413ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng // If there are odd number of registers or if it's not 64-bit aligned, 27423ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng // then it takes an extra AGU (Address Generation Unit) cycle. 27433ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng if ((NumRegs % 2) || 27443ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng !MI->hasOneMemOperand() || 27453ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng (*MI->memoperands_begin())->getAlignment() < 8) 2746218ee74a011c0d350099c452810da0bd57a15047Andrew Trick ++A9UOps; 2747218ee74a011c0d350099c452810da0bd57a15047Andrew Trick return A9UOps; 27483ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng } else { 27493ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng // Assume the worst. 27503ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng return NumRegs; 27512bbb76909126db5bed6bde84b16d94ab5de4d372Michael J. Spencer } 27525f54ce347368105260be2cec497b6a4199dc5789Evan Cheng } 27535f54ce347368105260be2cec497b6a4199dc5789Evan Cheng } 27545f54ce347368105260be2cec497b6a4199dc5789Evan Cheng} 2755a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng 2756a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Chengint 2757344d9db97062736cd66da6c07baa9108b6cfa419Evan ChengARMBaseInstrInfo::getVLDMDefCycle(const InstrItineraryData *ItinData, 2758e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng const MCInstrDesc &DefMCID, 2759344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng unsigned DefClass, 2760344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng unsigned DefIdx, unsigned DefAlign) const { 2761e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng int RegNo = (int)(DefIdx+1) - DefMCID.getNumOperands() + 1; 2762344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng if (RegNo <= 0) 2763344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // Def is the address writeback. 2764344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng return ItinData->getOperandCycle(DefClass, DefIdx); 2765344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng 2766344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng int DefCycle; 2767344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng if (Subtarget.isCortexA8()) { 2768344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // (regno / 2) + (regno % 2) + 1 2769344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng DefCycle = RegNo / 2 + 1; 2770344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng if (RegNo % 2) 2771344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng ++DefCycle; 2772eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson } else if (Subtarget.isLikeA9() || Subtarget.isSwift()) { 2773344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng DefCycle = RegNo; 2774344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng bool isSLoad = false; 277573fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling 2776e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng switch (DefMCID.getOpcode()) { 2777344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng default: break; 277873fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMSIA: 277973fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMSIA_UPD: 278073fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMSDB_UPD: 2781344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng isSLoad = true; 2782344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng break; 2783344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng } 278473fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling 2785344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // If there are odd number of 'S' registers or if it's not 64-bit aligned, 2786344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // then it takes an extra cycle. 2787344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng if ((isSLoad && (RegNo % 2)) || DefAlign < 8) 2788344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng ++DefCycle; 2789344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng } else { 2790344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // Assume the worst. 2791344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng DefCycle = RegNo + 2; 2792344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng } 2793344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng 2794344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng return DefCycle; 2795344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng} 2796344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng 2797344d9db97062736cd66da6c07baa9108b6cfa419Evan Chengint 2798344d9db97062736cd66da6c07baa9108b6cfa419Evan ChengARMBaseInstrInfo::getLDMDefCycle(const InstrItineraryData *ItinData, 2799e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng const MCInstrDesc &DefMCID, 2800344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng unsigned DefClass, 2801344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng unsigned DefIdx, unsigned DefAlign) const { 2802e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng int RegNo = (int)(DefIdx+1) - DefMCID.getNumOperands() + 1; 2803344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng if (RegNo <= 0) 2804344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // Def is the address writeback. 2805344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng return ItinData->getOperandCycle(DefClass, DefIdx); 2806344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng 2807344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng int DefCycle; 2808344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng if (Subtarget.isCortexA8()) { 2809344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // 4 registers would be issued: 1, 2, 1. 2810344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // 5 registers would be issued: 1, 2, 2. 2811344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng DefCycle = RegNo / 2; 2812344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng if (DefCycle < 1) 2813344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng DefCycle = 1; 2814344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // Result latency is issue cycle + 2: E2. 2815344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng DefCycle += 2; 2816eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson } else if (Subtarget.isLikeA9() || Subtarget.isSwift()) { 2817344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng DefCycle = (RegNo / 2); 2818344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // If there are odd number of registers or if it's not 64-bit aligned, 2819344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // then it takes an extra AGU (Address Generation Unit) cycle. 2820344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng if ((RegNo % 2) || DefAlign < 8) 2821344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng ++DefCycle; 2822344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // Result latency is AGU cycles + 2. 2823344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng DefCycle += 2; 2824344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng } else { 2825344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // Assume the worst. 2826344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng DefCycle = RegNo + 2; 2827344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng } 2828344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng 2829344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng return DefCycle; 2830344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng} 2831344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng 2832344d9db97062736cd66da6c07baa9108b6cfa419Evan Chengint 2833344d9db97062736cd66da6c07baa9108b6cfa419Evan ChengARMBaseInstrInfo::getVSTMUseCycle(const InstrItineraryData *ItinData, 2834e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng const MCInstrDesc &UseMCID, 2835344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng unsigned UseClass, 2836344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng unsigned UseIdx, unsigned UseAlign) const { 2837e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng int RegNo = (int)(UseIdx+1) - UseMCID.getNumOperands() + 1; 2838344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng if (RegNo <= 0) 2839344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng return ItinData->getOperandCycle(UseClass, UseIdx); 2840344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng 2841344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng int UseCycle; 2842344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng if (Subtarget.isCortexA8()) { 2843344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // (regno / 2) + (regno % 2) + 1 2844344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng UseCycle = RegNo / 2 + 1; 2845344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng if (RegNo % 2) 2846344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng ++UseCycle; 2847eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson } else if (Subtarget.isLikeA9() || Subtarget.isSwift()) { 2848344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng UseCycle = RegNo; 2849344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng bool isSStore = false; 285073fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling 2851e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng switch (UseMCID.getOpcode()) { 2852344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng default: break; 285373fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMSIA: 285473fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMSIA_UPD: 285573fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMSDB_UPD: 2856344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng isSStore = true; 2857344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng break; 2858344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng } 285973fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling 2860344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // If there are odd number of 'S' registers or if it's not 64-bit aligned, 2861344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // then it takes an extra cycle. 2862344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng if ((isSStore && (RegNo % 2)) || UseAlign < 8) 2863344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng ++UseCycle; 2864344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng } else { 2865344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // Assume the worst. 2866344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng UseCycle = RegNo + 2; 2867344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng } 2868344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng 2869344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng return UseCycle; 2870344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng} 2871344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng 2872344d9db97062736cd66da6c07baa9108b6cfa419Evan Chengint 2873344d9db97062736cd66da6c07baa9108b6cfa419Evan ChengARMBaseInstrInfo::getSTMUseCycle(const InstrItineraryData *ItinData, 2874e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng const MCInstrDesc &UseMCID, 2875344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng unsigned UseClass, 2876344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng unsigned UseIdx, unsigned UseAlign) const { 2877e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng int RegNo = (int)(UseIdx+1) - UseMCID.getNumOperands() + 1; 2878344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng if (RegNo <= 0) 2879344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng return ItinData->getOperandCycle(UseClass, UseIdx); 2880344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng 2881344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng int UseCycle; 2882344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng if (Subtarget.isCortexA8()) { 2883344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng UseCycle = RegNo / 2; 2884344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng if (UseCycle < 2) 2885344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng UseCycle = 2; 2886344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // Read in E3. 2887344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng UseCycle += 2; 2888eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson } else if (Subtarget.isLikeA9() || Subtarget.isSwift()) { 2889344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng UseCycle = (RegNo / 2); 2890344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // If there are odd number of registers or if it's not 64-bit aligned, 2891344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // then it takes an extra AGU (Address Generation Unit) cycle. 2892344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng if ((RegNo % 2) || UseAlign < 8) 2893344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng ++UseCycle; 2894344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng } else { 2895344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // Assume the worst. 2896344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng UseCycle = 1; 2897344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng } 2898344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng return UseCycle; 2899344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng} 2900344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng 2901344d9db97062736cd66da6c07baa9108b6cfa419Evan Chengint 2902a0792de66c8364d47b0a688c7f408efb7b10f31bEvan ChengARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData, 2903e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng const MCInstrDesc &DefMCID, 2904a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng unsigned DefIdx, unsigned DefAlign, 2905e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng const MCInstrDesc &UseMCID, 2906a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng unsigned UseIdx, unsigned UseAlign) const { 2907e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng unsigned DefClass = DefMCID.getSchedClass(); 2908e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng unsigned UseClass = UseMCID.getSchedClass(); 2909a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng 2910e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng if (DefIdx < DefMCID.getNumDefs() && UseIdx < UseMCID.getNumOperands()) 2911a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx); 2912a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng 2913a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng // This may be a def / use of a variable_ops instruction, the operand 2914a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng // latency might be determinable dynamically. Let the target try to 2915a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng // figure it out. 29169e08ee5d16b596078e20787f0b5f36121f099333Evan Cheng int DefCycle = -1; 29177e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng bool LdmBypass = false; 2918e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng switch (DefMCID.getOpcode()) { 2919a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng default: 2920a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng DefCycle = ItinData->getOperandCycle(DefClass, DefIdx); 2921a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng break; 292273fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling 292373fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMDIA: 292473fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMDIA_UPD: 292573fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMDDB_UPD: 292673fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMSIA: 292773fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMSIA_UPD: 292873fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMSDB_UPD: 2929e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng DefCycle = getVLDMDefCycle(ItinData, DefMCID, DefClass, DefIdx, DefAlign); 29305a50ceeaea980962c1982ad535226c7ab06c971cEvan Cheng break; 293173fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling 293273fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMIA_RET: 293373fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMIA: 293473fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMDA: 293573fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMDB: 293673fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMIB: 293773fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMIA_UPD: 293873fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMDA_UPD: 293973fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMDB_UPD: 294073fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMIB_UPD: 294173fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::tLDMIA: 294273fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::tLDMIA_UPD: 2943a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng case ARM::tPUSH: 294473fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2LDMIA_RET: 294573fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2LDMIA: 294673fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2LDMDB: 294773fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2LDMIA_UPD: 294873fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2LDMDB_UPD: 2949a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng LdmBypass = 1; 2950e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng DefCycle = getLDMDefCycle(ItinData, DefMCID, DefClass, DefIdx, DefAlign); 2951344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng break; 2952a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng } 2953a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng 2954a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng if (DefCycle == -1) 2955a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng // We can't seem to determine the result latency of the def, assume it's 2. 2956a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng DefCycle = 2; 2957a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng 2958a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng int UseCycle = -1; 2959e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng switch (UseMCID.getOpcode()) { 2960a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng default: 2961a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng UseCycle = ItinData->getOperandCycle(UseClass, UseIdx); 2962a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng break; 296373fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling 296473fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMDIA: 296573fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMDIA_UPD: 296673fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMDDB_UPD: 296773fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMSIA: 296873fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMSIA_UPD: 296973fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMSDB_UPD: 2970e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng UseCycle = getVSTMUseCycle(ItinData, UseMCID, UseClass, UseIdx, UseAlign); 29715a50ceeaea980962c1982ad535226c7ab06c971cEvan Cheng break; 297273fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling 297373fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::STMIA: 297473fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::STMDA: 297573fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::STMDB: 297673fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::STMIB: 297773fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::STMIA_UPD: 297873fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::STMDA_UPD: 297973fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::STMDB_UPD: 298073fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::STMIB_UPD: 298173fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::tSTMIA_UPD: 2982a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng case ARM::tPOP_RET: 2983a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng case ARM::tPOP: 298473fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2STMIA: 298573fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2STMDB: 298673fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2STMIA_UPD: 298773fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2STMDB_UPD: 2988e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng UseCycle = getSTMUseCycle(ItinData, UseMCID, UseClass, UseIdx, UseAlign); 29895a50ceeaea980962c1982ad535226c7ab06c971cEvan Cheng break; 2990a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng } 2991a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng 2992a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng if (UseCycle == -1) 2993a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng // Assume it's read in the first stage. 2994a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng UseCycle = 1; 2995a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng 2996a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng UseCycle = DefCycle - UseCycle + 1; 2997a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng if (UseCycle > 0) { 2998a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng if (LdmBypass) { 2999a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng // It's a variable_ops instruction so we can't use DefIdx here. Just use 3000a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng // first def operand. 3001e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng if (ItinData->hasPipelineForwarding(DefClass, DefMCID.getNumOperands()-1, 3002a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng UseClass, UseIdx)) 3003a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng --UseCycle; 3004a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng } else if (ItinData->hasPipelineForwarding(DefClass, DefIdx, 300573fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling UseClass, UseIdx)) { 3006a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng --UseCycle; 300773fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling } 3008a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng } 3009a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng 3010a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng return UseCycle; 3011a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng} 3012a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng 3013ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Chengstatic const MachineInstr *getBundledDefMI(const TargetRegisterInfo *TRI, 3014020f4106f820648fd7e91956859844a80de13974Evan Cheng const MachineInstr *MI, unsigned Reg, 3015ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng unsigned &DefIdx, unsigned &Dist) { 3016ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng Dist = 0; 3017ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng 3018ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng MachineBasicBlock::const_iterator I = MI; ++I; 3019ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng MachineBasicBlock::const_instr_iterator II = 3020ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng llvm::prior(I.getInstrIterator()); 3021ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng assert(II->isInsideBundle() && "Empty bundle?"); 3022ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng 3023ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng int Idx = -1; 3024ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng while (II->isInsideBundle()) { 3025ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng Idx = II->findRegisterDefOperandIdx(Reg, false, true, TRI); 3026ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng if (Idx != -1) 3027ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng break; 3028ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng --II; 3029ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng ++Dist; 3030ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng } 3031ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng 3032ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng assert(Idx != -1 && "Cannot find bundled definition!"); 3033ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng DefIdx = Idx; 3034ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng return II; 3035ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng} 3036ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng 3037ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Chengstatic const MachineInstr *getBundledUseMI(const TargetRegisterInfo *TRI, 3038020f4106f820648fd7e91956859844a80de13974Evan Cheng const MachineInstr *MI, unsigned Reg, 3039ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng unsigned &UseIdx, unsigned &Dist) { 3040ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng Dist = 0; 3041ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng 3042ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng MachineBasicBlock::const_instr_iterator II = MI; ++II; 3043ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng assert(II->isInsideBundle() && "Empty bundle?"); 3044ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end(); 3045ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng 3046ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng // FIXME: This doesn't properly handle multiple uses. 3047ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng int Idx = -1; 3048ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng while (II != E && II->isInsideBundle()) { 3049ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng Idx = II->findRegisterUseOperandIdx(Reg, false, TRI); 3050ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng if (Idx != -1) 3051ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng break; 3052ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng if (II->getOpcode() != ARM::t2IT) 3053ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng ++Dist; 3054ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng ++II; 3055ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng } 3056ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng 3057020f4106f820648fd7e91956859844a80de13974Evan Cheng if (Idx == -1) { 3058020f4106f820648fd7e91956859844a80de13974Evan Cheng Dist = 0; 3059020f4106f820648fd7e91956859844a80de13974Evan Cheng return 0; 3060020f4106f820648fd7e91956859844a80de13974Evan Cheng } 3061020f4106f820648fd7e91956859844a80de13974Evan Cheng 3062ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng UseIdx = Idx; 3063ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng return II; 3064ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng} 3065ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng 306668b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick/// Return the number of cycles to add to (or subtract from) the static 306768b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick/// itinerary based on the def opcode and alignment. The caller will ensure that 306868b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick/// adjusted latency is at least one cycle. 306968b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trickstatic int adjustDefLatency(const ARMSubtarget &Subtarget, 307068b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick const MachineInstr *DefMI, 307168b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick const MCInstrDesc *DefMCID, unsigned DefAlign) { 307268b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick int Adjust = 0; 3073616471d4bfe4717fa86259ff4534703357b3b723Silviu Baranga if (Subtarget.isCortexA8() || Subtarget.isLikeA9()) { 30747e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng // FIXME: Shifter op hack: no shift (i.e. [r +/- r]) or [r + r << 2] 30757e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng // variants are one cycle cheaper. 3076ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng switch (DefMCID->getOpcode()) { 30777e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng default: break; 3078cff9baa95273bc279bf5fadb9e27afbd25cca20bJakob Stoklund Olesen case ARM::LDRrs: 3079cff9baa95273bc279bf5fadb9e27afbd25cca20bJakob Stoklund Olesen case ARM::LDRBrs: { 30807e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng unsigned ShOpVal = DefMI->getOperand(3).getImm(); 30817e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal); 30827e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng if (ShImm == 0 || 30837e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng (ShImm == 2 && ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl)) 308468b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick --Adjust; 30857e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng break; 30867e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng } 3087cff9baa95273bc279bf5fadb9e27afbd25cca20bJakob Stoklund Olesen case ARM::t2LDRs: 3088cff9baa95273bc279bf5fadb9e27afbd25cca20bJakob Stoklund Olesen case ARM::t2LDRBs: 3089cff9baa95273bc279bf5fadb9e27afbd25cca20bJakob Stoklund Olesen case ARM::t2LDRHs: 30907e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng case ARM::t2LDRSHs: { 30917e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng // Thumb2 mode: lsl only. 30927e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng unsigned ShAmt = DefMI->getOperand(3).getImm(); 30937e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng if (ShAmt == 0 || ShAmt == 2) 309468b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick --Adjust; 30957e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng break; 30967e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng } 30977e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng } 3098eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson } else if (Subtarget.isSwift()) { 3099eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson // FIXME: Properly handle all of the latency adjustments for address 3100eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson // writeback. 3101eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson switch (DefMCID->getOpcode()) { 3102eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson default: break; 3103eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::LDRrs: 3104eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::LDRBrs: { 3105eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson unsigned ShOpVal = DefMI->getOperand(3).getImm(); 3106eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson bool isSub = ARM_AM::getAM2Op(ShOpVal) == ARM_AM::sub; 3107eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal); 3108eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson if (!isSub && 3109eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson (ShImm == 0 || 3110eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson ((ShImm == 1 || ShImm == 2 || ShImm == 3) && 3111eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl))) 3112eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson Adjust -= 2; 3113eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson else if (!isSub && 3114eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson ShImm == 1 && ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsr) 3115eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson --Adjust; 3116eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson break; 3117eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson } 3118eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::t2LDRs: 3119eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::t2LDRBs: 3120eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::t2LDRHs: 3121eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::t2LDRSHs: { 3122eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson // Thumb2 mode: lsl only. 3123eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson unsigned ShAmt = DefMI->getOperand(3).getImm(); 3124eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson if (ShAmt == 0 || ShAmt == 1 || ShAmt == 2 || ShAmt == 3) 3125eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson Adjust -= 2; 3126eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson break; 3127eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson } 3128eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson } 31297e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng } 31307e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng 3131616471d4bfe4717fa86259ff4534703357b3b723Silviu Baranga if (DefAlign < 8 && Subtarget.isLikeA9()) { 3132ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng switch (DefMCID->getOpcode()) { 313375b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng default: break; 313475b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1q8: 313575b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1q16: 313675b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1q32: 313775b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1q64: 313810b90a9bbf7dcae1568c03a03f9606f5395f2144Jim Grosbach case ARM::VLD1q8wb_fixed: 313910b90a9bbf7dcae1568c03a03f9606f5395f2144Jim Grosbach case ARM::VLD1q16wb_fixed: 314010b90a9bbf7dcae1568c03a03f9606f5395f2144Jim Grosbach case ARM::VLD1q32wb_fixed: 314110b90a9bbf7dcae1568c03a03f9606f5395f2144Jim Grosbach case ARM::VLD1q64wb_fixed: 314210b90a9bbf7dcae1568c03a03f9606f5395f2144Jim Grosbach case ARM::VLD1q8wb_register: 314310b90a9bbf7dcae1568c03a03f9606f5395f2144Jim Grosbach case ARM::VLD1q16wb_register: 314410b90a9bbf7dcae1568c03a03f9606f5395f2144Jim Grosbach case ARM::VLD1q32wb_register: 314510b90a9bbf7dcae1568c03a03f9606f5395f2144Jim Grosbach case ARM::VLD1q64wb_register: 314675b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2d8: 314775b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2d16: 314875b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2d32: 314975b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2q8: 315075b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2q16: 315175b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2q32: 3152a4e3c7fc4ba2d55695b0484480685698132eba20Jim Grosbach case ARM::VLD2d8wb_fixed: 3153a4e3c7fc4ba2d55695b0484480685698132eba20Jim Grosbach case ARM::VLD2d16wb_fixed: 3154a4e3c7fc4ba2d55695b0484480685698132eba20Jim Grosbach case ARM::VLD2d32wb_fixed: 3155a4e3c7fc4ba2d55695b0484480685698132eba20Jim Grosbach case ARM::VLD2q8wb_fixed: 3156a4e3c7fc4ba2d55695b0484480685698132eba20Jim Grosbach case ARM::VLD2q16wb_fixed: 3157a4e3c7fc4ba2d55695b0484480685698132eba20Jim Grosbach case ARM::VLD2q32wb_fixed: 3158a4e3c7fc4ba2d55695b0484480685698132eba20Jim Grosbach case ARM::VLD2d8wb_register: 3159a4e3c7fc4ba2d55695b0484480685698132eba20Jim Grosbach case ARM::VLD2d16wb_register: 3160a4e3c7fc4ba2d55695b0484480685698132eba20Jim Grosbach case ARM::VLD2d32wb_register: 3161a4e3c7fc4ba2d55695b0484480685698132eba20Jim Grosbach case ARM::VLD2q8wb_register: 3162a4e3c7fc4ba2d55695b0484480685698132eba20Jim Grosbach case ARM::VLD2q16wb_register: 3163a4e3c7fc4ba2d55695b0484480685698132eba20Jim Grosbach case ARM::VLD2q32wb_register: 316475b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3d8: 316575b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3d16: 316675b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3d32: 316775b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1d64T: 316875b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3d8_UPD: 316975b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3d16_UPD: 317075b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3d32_UPD: 31715921675ff5ea632ab1e6d7aa5d1f263b858bbafaJim Grosbach case ARM::VLD1d64Twb_fixed: 31725921675ff5ea632ab1e6d7aa5d1f263b858bbafaJim Grosbach case ARM::VLD1d64Twb_register: 317375b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3q8_UPD: 317475b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3q16_UPD: 317575b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3q32_UPD: 317675b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4d8: 317775b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4d16: 317875b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4d32: 317975b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1d64Q: 318075b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4d8_UPD: 318175b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4d16_UPD: 318275b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4d32_UPD: 3183399cdca4d201f7232126c3a0643669971ede780aJim Grosbach case ARM::VLD1d64Qwb_fixed: 3184399cdca4d201f7232126c3a0643669971ede780aJim Grosbach case ARM::VLD1d64Qwb_register: 318575b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4q8_UPD: 318675b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4q16_UPD: 318775b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4q32_UPD: 318875b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1DUPq8: 318975b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1DUPq16: 319075b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1DUPq32: 3191096334e25ea68ac970942ecb680a82fbb8ad206cJim Grosbach case ARM::VLD1DUPq8wb_fixed: 3192096334e25ea68ac970942ecb680a82fbb8ad206cJim Grosbach case ARM::VLD1DUPq16wb_fixed: 3193096334e25ea68ac970942ecb680a82fbb8ad206cJim Grosbach case ARM::VLD1DUPq32wb_fixed: 3194096334e25ea68ac970942ecb680a82fbb8ad206cJim Grosbach case ARM::VLD1DUPq8wb_register: 3195096334e25ea68ac970942ecb680a82fbb8ad206cJim Grosbach case ARM::VLD1DUPq16wb_register: 3196096334e25ea68ac970942ecb680a82fbb8ad206cJim Grosbach case ARM::VLD1DUPq32wb_register: 319775b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2DUPd8: 319875b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2DUPd16: 319975b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2DUPd32: 3200e6949b13997e6d31aa4719a0e80c4b6b405e42a9Jim Grosbach case ARM::VLD2DUPd8wb_fixed: 3201e6949b13997e6d31aa4719a0e80c4b6b405e42a9Jim Grosbach case ARM::VLD2DUPd16wb_fixed: 3202e6949b13997e6d31aa4719a0e80c4b6b405e42a9Jim Grosbach case ARM::VLD2DUPd32wb_fixed: 3203e6949b13997e6d31aa4719a0e80c4b6b405e42a9Jim Grosbach case ARM::VLD2DUPd8wb_register: 3204e6949b13997e6d31aa4719a0e80c4b6b405e42a9Jim Grosbach case ARM::VLD2DUPd16wb_register: 3205e6949b13997e6d31aa4719a0e80c4b6b405e42a9Jim Grosbach case ARM::VLD2DUPd32wb_register: 320675b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4DUPd8: 320775b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4DUPd16: 320875b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4DUPd32: 320975b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4DUPd8_UPD: 321075b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4DUPd16_UPD: 321175b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4DUPd32_UPD: 321275b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1LNd8: 321375b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1LNd16: 321475b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1LNd32: 321575b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1LNd8_UPD: 321675b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1LNd16_UPD: 321775b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1LNd32_UPD: 321875b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2LNd8: 321975b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2LNd16: 322075b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2LNd32: 322175b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2LNq16: 322275b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2LNq32: 322375b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2LNd8_UPD: 322475b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2LNd16_UPD: 322575b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2LNd32_UPD: 322675b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2LNq16_UPD: 322775b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2LNq32_UPD: 322875b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4LNd8: 322975b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4LNd16: 323075b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4LNd32: 323175b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4LNq16: 323275b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4LNq32: 323375b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4LNd8_UPD: 323475b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4LNd16_UPD: 323575b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4LNd32_UPD: 323675b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4LNq16_UPD: 323775b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4LNq32_UPD: 323875b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng // If the address is not 64-bit aligned, the latencies of these 323975b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng // instructions increases by one. 324068b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick ++Adjust; 324175b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng break; 324275b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng } 324368b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick } 324468b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick return Adjust; 324568b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick} 324668b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick 324775b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng 324868b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick 324968b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trickint 325068b16541cc58411c7b0607ca4c0fb497222b668dAndrew TrickARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData, 325168b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick const MachineInstr *DefMI, unsigned DefIdx, 325268b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick const MachineInstr *UseMI, 325368b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick unsigned UseIdx) const { 325468b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick // No operand latency. The caller may fall back to getInstrLatency. 325568b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick if (!ItinData || ItinData->isEmpty()) 325668b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick return -1; 325768b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick 325868b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick const MachineOperand &DefMO = DefMI->getOperand(DefIdx); 325968b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick unsigned Reg = DefMO.getReg(); 326068b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick const MCInstrDesc *DefMCID = &DefMI->getDesc(); 326168b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick const MCInstrDesc *UseMCID = &UseMI->getDesc(); 326268b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick 326368b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick unsigned DefAdj = 0; 326468b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick if (DefMI->isBundle()) { 326568b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick DefMI = getBundledDefMI(&getRegisterInfo(), DefMI, Reg, DefIdx, DefAdj); 326668b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick DefMCID = &DefMI->getDesc(); 326768b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick } 326868b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick if (DefMI->isCopyLike() || DefMI->isInsertSubreg() || 326968b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick DefMI->isRegSequence() || DefMI->isImplicitDef()) { 327068b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick return 1; 327168b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick } 327268b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick 327368b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick unsigned UseAdj = 0; 327468b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick if (UseMI->isBundle()) { 327568b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick unsigned NewUseIdx; 327668b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick const MachineInstr *NewUseMI = getBundledUseMI(&getRegisterInfo(), UseMI, 327768b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick Reg, NewUseIdx, UseAdj); 3278e2b32bb20ee76f24708b3c9e19b6fbc651c25637Andrew Trick if (!NewUseMI) 3279e2b32bb20ee76f24708b3c9e19b6fbc651c25637Andrew Trick return -1; 3280e2b32bb20ee76f24708b3c9e19b6fbc651c25637Andrew Trick 3281e2b32bb20ee76f24708b3c9e19b6fbc651c25637Andrew Trick UseMI = NewUseMI; 3282e2b32bb20ee76f24708b3c9e19b6fbc651c25637Andrew Trick UseIdx = NewUseIdx; 3283e2b32bb20ee76f24708b3c9e19b6fbc651c25637Andrew Trick UseMCID = &UseMI->getDesc(); 328468b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick } 328568b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick 328668b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick if (Reg == ARM::CPSR) { 328768b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick if (DefMI->getOpcode() == ARM::FMSTAT) { 328868b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick // fpscr -> cpsr stalls over 20 cycles on A8 (and earlier?) 3289616471d4bfe4717fa86259ff4534703357b3b723Silviu Baranga return Subtarget.isLikeA9() ? 1 : 20; 329068b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick } 329168b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick 329268b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick // CPSR set and branch can be paired in the same cycle. 329368b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick if (UseMI->isBranch()) 329468b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick return 0; 329568b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick 329668b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick // Otherwise it takes the instruction latency (generally one). 329768b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick unsigned Latency = getInstrLatency(ItinData, DefMI); 329868b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick 329968b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick // For Thumb2 and -Os, prefer scheduling CPSR setting instruction close to 330068b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick // its uses. Instructions which are otherwise scheduled between them may 330168b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick // incur a code size penalty (not able to use the CPSR setting 16-bit 330268b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick // instructions). 330368b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick if (Latency > 0 && Subtarget.isThumb2()) { 330468b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick const MachineFunction *MF = DefMI->getParent()->getParent(); 33056765834754cbb3cb0f15b4b15e98c5e73fa50066Bill Wendling if (MF->getFunction()->getFnAttributes(). 33066765834754cbb3cb0f15b4b15e98c5e73fa50066Bill Wendling hasAttribute(Attributes::OptimizeForSize)) 330768b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick --Latency; 330868b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick } 330968b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick return Latency; 331068b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick } 331168b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick 3312e2b32bb20ee76f24708b3c9e19b6fbc651c25637Andrew Trick if (DefMO.isImplicit() || UseMI->getOperand(UseIdx).isImplicit()) 3313e2b32bb20ee76f24708b3c9e19b6fbc651c25637Andrew Trick return -1; 3314e2b32bb20ee76f24708b3c9e19b6fbc651c25637Andrew Trick 331568b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick unsigned DefAlign = DefMI->hasOneMemOperand() 331668b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick ? (*DefMI->memoperands_begin())->getAlignment() : 0; 331768b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick unsigned UseAlign = UseMI->hasOneMemOperand() 331868b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick ? (*UseMI->memoperands_begin())->getAlignment() : 0; 331968b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick 332068b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick // Get the itinerary's latency if possible, and handle variable_ops. 332168b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick int Latency = getOperandLatency(ItinData, *DefMCID, DefIdx, DefAlign, 332268b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick *UseMCID, UseIdx, UseAlign); 332368b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick // Unable to find operand latency. The caller may resort to getInstrLatency. 332468b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick if (Latency < 0) 332568b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick return Latency; 332668b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick 332768b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick // Adjust for IT block position. 332868b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick int Adj = DefAdj + UseAdj; 332968b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick 333068b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick // Adjust for dynamic def-side opcode variants not captured by the itinerary. 333168b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick Adj += adjustDefLatency(Subtarget, DefMI, DefMCID, DefAlign); 333268b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick if (Adj >= 0 || (int)Latency > -Adj) { 333368b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick return Latency + Adj; 333468b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick } 333568b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick // Return the itinerary latency, which may be zero but not less than zero. 33367e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng return Latency; 3337a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng} 3338a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng 3339a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Chengint 3340a0792de66c8364d47b0a688c7f408efb7b10f31bEvan ChengARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData, 3341a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng SDNode *DefNode, unsigned DefIdx, 3342a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng SDNode *UseNode, unsigned UseIdx) const { 3343a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng if (!DefNode->isMachineOpcode()) 3344a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng return 1; 3345a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng 3346e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng const MCInstrDesc &DefMCID = get(DefNode->getMachineOpcode()); 3347c8bfd1d78ff9a307d1d4cb57cce4549b538e60f4Andrew Trick 3348e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng if (isZeroCost(DefMCID.Opcode)) 3349c8bfd1d78ff9a307d1d4cb57cce4549b538e60f4Andrew Trick return 0; 3350c8bfd1d78ff9a307d1d4cb57cce4549b538e60f4Andrew Trick 3351a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng if (!ItinData || ItinData->isEmpty()) 3352e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng return DefMCID.mayLoad() ? 3 : 1; 3353a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng 3354089751535d6e9adf65842e2ca5867bf9a70e1e95Evan Cheng if (!UseNode->isMachineOpcode()) { 3355e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng int Latency = ItinData->getOperandCycle(DefMCID.getSchedClass(), DefIdx); 3356eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson if (Subtarget.isLikeA9() || Subtarget.isSwift()) 3357089751535d6e9adf65842e2ca5867bf9a70e1e95Evan Cheng return Latency <= 2 ? 1 : Latency - 1; 3358089751535d6e9adf65842e2ca5867bf9a70e1e95Evan Cheng else 3359089751535d6e9adf65842e2ca5867bf9a70e1e95Evan Cheng return Latency <= 3 ? 1 : Latency - 2; 3360089751535d6e9adf65842e2ca5867bf9a70e1e95Evan Cheng } 3361a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng 3362e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng const MCInstrDesc &UseMCID = get(UseNode->getMachineOpcode()); 3363a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng const MachineSDNode *DefMN = dyn_cast<MachineSDNode>(DefNode); 3364a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng unsigned DefAlign = !DefMN->memoperands_empty() 3365a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng ? (*DefMN->memoperands_begin())->getAlignment() : 0; 3366a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng const MachineSDNode *UseMN = dyn_cast<MachineSDNode>(UseNode); 3367a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng unsigned UseAlign = !UseMN->memoperands_empty() 3368a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng ? (*UseMN->memoperands_begin())->getAlignment() : 0; 3369e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng int Latency = getOperandLatency(ItinData, DefMCID, DefIdx, DefAlign, 3370e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng UseMCID, UseIdx, UseAlign); 33717e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng 33727e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng if (Latency > 1 && 3373616471d4bfe4717fa86259ff4534703357b3b723Silviu Baranga (Subtarget.isCortexA8() || Subtarget.isLikeA9())) { 33747e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng // FIXME: Shifter op hack: no shift (i.e. [r +/- r]) or [r + r << 2] 33757e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng // variants are one cycle cheaper. 3376e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng switch (DefMCID.getOpcode()) { 33777e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng default: break; 3378cff9baa95273bc279bf5fadb9e27afbd25cca20bJakob Stoklund Olesen case ARM::LDRrs: 3379cff9baa95273bc279bf5fadb9e27afbd25cca20bJakob Stoklund Olesen case ARM::LDRBrs: { 33807e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng unsigned ShOpVal = 33817e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng cast<ConstantSDNode>(DefNode->getOperand(2))->getZExtValue(); 33827e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal); 33837e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng if (ShImm == 0 || 33847e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng (ShImm == 2 && ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl)) 33857e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng --Latency; 33867e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng break; 33877e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng } 3388cff9baa95273bc279bf5fadb9e27afbd25cca20bJakob Stoklund Olesen case ARM::t2LDRs: 3389cff9baa95273bc279bf5fadb9e27afbd25cca20bJakob Stoklund Olesen case ARM::t2LDRBs: 3390cff9baa95273bc279bf5fadb9e27afbd25cca20bJakob Stoklund Olesen case ARM::t2LDRHs: 33917e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng case ARM::t2LDRSHs: { 33927e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng // Thumb2 mode: lsl only. 33937e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng unsigned ShAmt = 33947e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng cast<ConstantSDNode>(DefNode->getOperand(2))->getZExtValue(); 33957e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng if (ShAmt == 0 || ShAmt == 2) 33967e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng --Latency; 33977e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng break; 33987e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng } 33997e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng } 3400eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson } else if (DefIdx == 0 && Latency > 2 && Subtarget.isSwift()) { 3401eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson // FIXME: Properly handle all of the latency adjustments for address 3402eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson // writeback. 3403eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson switch (DefMCID.getOpcode()) { 3404eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson default: break; 3405eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::LDRrs: 3406eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::LDRBrs: { 3407eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson unsigned ShOpVal = 3408eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson cast<ConstantSDNode>(DefNode->getOperand(2))->getZExtValue(); 3409eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal); 3410eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson if (ShImm == 0 || 3411eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson ((ShImm == 1 || ShImm == 2 || ShImm == 3) && 3412eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl)) 3413eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson Latency -= 2; 3414eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson else if (ShImm == 1 && ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsr) 3415eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson --Latency; 3416eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson break; 3417eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson } 3418eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::t2LDRs: 3419eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::t2LDRBs: 3420eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::t2LDRHs: 3421eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::t2LDRSHs: { 3422eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson // Thumb2 mode: lsl 0-3 only. 3423eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson Latency -= 2; 3424eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson break; 3425eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson } 3426eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson } 34277e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng } 34287e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng 3429616471d4bfe4717fa86259ff4534703357b3b723Silviu Baranga if (DefAlign < 8 && Subtarget.isLikeA9()) 3430e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng switch (DefMCID.getOpcode()) { 343175b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng default: break; 343228f08c93e75d291695ea89b9004145103292e85bJim Grosbach case ARM::VLD1q8: 343328f08c93e75d291695ea89b9004145103292e85bJim Grosbach case ARM::VLD1q16: 343428f08c93e75d291695ea89b9004145103292e85bJim Grosbach case ARM::VLD1q32: 343528f08c93e75d291695ea89b9004145103292e85bJim Grosbach case ARM::VLD1q64: 343628f08c93e75d291695ea89b9004145103292e85bJim Grosbach case ARM::VLD1q8wb_register: 343728f08c93e75d291695ea89b9004145103292e85bJim Grosbach case ARM::VLD1q16wb_register: 343828f08c93e75d291695ea89b9004145103292e85bJim Grosbach case ARM::VLD1q32wb_register: 343928f08c93e75d291695ea89b9004145103292e85bJim Grosbach case ARM::VLD1q64wb_register: 344028f08c93e75d291695ea89b9004145103292e85bJim Grosbach case ARM::VLD1q8wb_fixed: 344128f08c93e75d291695ea89b9004145103292e85bJim Grosbach case ARM::VLD1q16wb_fixed: 344228f08c93e75d291695ea89b9004145103292e85bJim Grosbach case ARM::VLD1q32wb_fixed: 344328f08c93e75d291695ea89b9004145103292e85bJim Grosbach case ARM::VLD1q64wb_fixed: 344428f08c93e75d291695ea89b9004145103292e85bJim Grosbach case ARM::VLD2d8: 344528f08c93e75d291695ea89b9004145103292e85bJim Grosbach case ARM::VLD2d16: 344628f08c93e75d291695ea89b9004145103292e85bJim Grosbach case ARM::VLD2d32: 344775b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2q8Pseudo: 344875b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2q16Pseudo: 344975b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2q32Pseudo: 345028f08c93e75d291695ea89b9004145103292e85bJim Grosbach case ARM::VLD2d8wb_fixed: 345128f08c93e75d291695ea89b9004145103292e85bJim Grosbach case ARM::VLD2d16wb_fixed: 345228f08c93e75d291695ea89b9004145103292e85bJim Grosbach case ARM::VLD2d32wb_fixed: 3453a4e3c7fc4ba2d55695b0484480685698132eba20Jim Grosbach case ARM::VLD2q8PseudoWB_fixed: 3454a4e3c7fc4ba2d55695b0484480685698132eba20Jim Grosbach case ARM::VLD2q16PseudoWB_fixed: 3455a4e3c7fc4ba2d55695b0484480685698132eba20Jim Grosbach case ARM::VLD2q32PseudoWB_fixed: 345628f08c93e75d291695ea89b9004145103292e85bJim Grosbach case ARM::VLD2d8wb_register: 345728f08c93e75d291695ea89b9004145103292e85bJim Grosbach case ARM::VLD2d16wb_register: 345828f08c93e75d291695ea89b9004145103292e85bJim Grosbach case ARM::VLD2d32wb_register: 3459a4e3c7fc4ba2d55695b0484480685698132eba20Jim Grosbach case ARM::VLD2q8PseudoWB_register: 3460a4e3c7fc4ba2d55695b0484480685698132eba20Jim Grosbach case ARM::VLD2q16PseudoWB_register: 3461a4e3c7fc4ba2d55695b0484480685698132eba20Jim Grosbach case ARM::VLD2q32PseudoWB_register: 346275b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3d8Pseudo: 346375b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3d16Pseudo: 346475b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3d32Pseudo: 346575b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1d64TPseudo: 346675b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3d8Pseudo_UPD: 346775b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3d16Pseudo_UPD: 346875b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3d32Pseudo_UPD: 346975b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3q8Pseudo_UPD: 347075b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3q16Pseudo_UPD: 347175b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3q32Pseudo_UPD: 347275b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3q8oddPseudo: 347375b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3q16oddPseudo: 347475b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3q32oddPseudo: 347575b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3q8oddPseudo_UPD: 347675b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3q16oddPseudo_UPD: 347775b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3q32oddPseudo_UPD: 347875b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4d8Pseudo: 347975b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4d16Pseudo: 348075b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4d32Pseudo: 348175b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1d64QPseudo: 348275b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4d8Pseudo_UPD: 348375b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4d16Pseudo_UPD: 348475b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4d32Pseudo_UPD: 348575b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4q8Pseudo_UPD: 348675b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4q16Pseudo_UPD: 348775b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4q32Pseudo_UPD: 348875b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4q8oddPseudo: 348975b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4q16oddPseudo: 349075b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4q32oddPseudo: 349175b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4q8oddPseudo_UPD: 349275b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4q16oddPseudo_UPD: 349375b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4q32oddPseudo_UPD: 3494c0fc450f0754508871bc70f21e528bf2f1520da1Jim Grosbach case ARM::VLD1DUPq8: 3495c0fc450f0754508871bc70f21e528bf2f1520da1Jim Grosbach case ARM::VLD1DUPq16: 3496c0fc450f0754508871bc70f21e528bf2f1520da1Jim Grosbach case ARM::VLD1DUPq32: 3497c0fc450f0754508871bc70f21e528bf2f1520da1Jim Grosbach case ARM::VLD1DUPq8wb_fixed: 3498c0fc450f0754508871bc70f21e528bf2f1520da1Jim Grosbach case ARM::VLD1DUPq16wb_fixed: 3499c0fc450f0754508871bc70f21e528bf2f1520da1Jim Grosbach case ARM::VLD1DUPq32wb_fixed: 3500c0fc450f0754508871bc70f21e528bf2f1520da1Jim Grosbach case ARM::VLD1DUPq8wb_register: 3501c0fc450f0754508871bc70f21e528bf2f1520da1Jim Grosbach case ARM::VLD1DUPq16wb_register: 3502c0fc450f0754508871bc70f21e528bf2f1520da1Jim Grosbach case ARM::VLD1DUPq32wb_register: 3503c0fc450f0754508871bc70f21e528bf2f1520da1Jim Grosbach case ARM::VLD2DUPd8: 3504c0fc450f0754508871bc70f21e528bf2f1520da1Jim Grosbach case ARM::VLD2DUPd16: 3505c0fc450f0754508871bc70f21e528bf2f1520da1Jim Grosbach case ARM::VLD2DUPd32: 3506c0fc450f0754508871bc70f21e528bf2f1520da1Jim Grosbach case ARM::VLD2DUPd8wb_fixed: 3507c0fc450f0754508871bc70f21e528bf2f1520da1Jim Grosbach case ARM::VLD2DUPd16wb_fixed: 3508c0fc450f0754508871bc70f21e528bf2f1520da1Jim Grosbach case ARM::VLD2DUPd32wb_fixed: 3509c0fc450f0754508871bc70f21e528bf2f1520da1Jim Grosbach case ARM::VLD2DUPd8wb_register: 3510c0fc450f0754508871bc70f21e528bf2f1520da1Jim Grosbach case ARM::VLD2DUPd16wb_register: 3511c0fc450f0754508871bc70f21e528bf2f1520da1Jim Grosbach case ARM::VLD2DUPd32wb_register: 351275b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4DUPd8Pseudo: 351375b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4DUPd16Pseudo: 351475b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4DUPd32Pseudo: 351575b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4DUPd8Pseudo_UPD: 351675b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4DUPd16Pseudo_UPD: 351775b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4DUPd32Pseudo_UPD: 351875b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1LNq8Pseudo: 351975b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1LNq16Pseudo: 352075b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1LNq32Pseudo: 352175b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1LNq8Pseudo_UPD: 352275b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1LNq16Pseudo_UPD: 352375b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1LNq32Pseudo_UPD: 352475b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2LNd8Pseudo: 352575b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2LNd16Pseudo: 352675b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2LNd32Pseudo: 352775b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2LNq16Pseudo: 352875b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2LNq32Pseudo: 352975b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2LNd8Pseudo_UPD: 353075b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2LNd16Pseudo_UPD: 353175b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2LNd32Pseudo_UPD: 353275b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2LNq16Pseudo_UPD: 353375b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2LNq32Pseudo_UPD: 353475b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4LNd8Pseudo: 353575b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4LNd16Pseudo: 353675b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4LNd32Pseudo: 353775b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4LNq16Pseudo: 353875b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4LNq32Pseudo: 353975b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4LNd8Pseudo_UPD: 354075b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4LNd16Pseudo_UPD: 354175b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4LNd32Pseudo_UPD: 354275b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4LNq16Pseudo_UPD: 354375b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4LNq32Pseudo_UPD: 354475b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng // If the address is not 64-bit aligned, the latencies of these 354575b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng // instructions increases by one. 354675b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng ++Latency; 354775b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng break; 354875b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng } 354975b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng 35507e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng return Latency; 3551a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng} 35522312842de0c641107dd04d7e056d02491cc781caEvan Cheng 3553020f4106f820648fd7e91956859844a80de13974Evan Chengunsigned 3554020f4106f820648fd7e91956859844a80de13974Evan ChengARMBaseInstrInfo::getOutputLatency(const InstrItineraryData *ItinData, 3555020f4106f820648fd7e91956859844a80de13974Evan Cheng const MachineInstr *DefMI, unsigned DefIdx, 3556020f4106f820648fd7e91956859844a80de13974Evan Cheng const MachineInstr *DepMI) const { 3557020f4106f820648fd7e91956859844a80de13974Evan Cheng unsigned Reg = DefMI->getOperand(DefIdx).getReg(); 3558020f4106f820648fd7e91956859844a80de13974Evan Cheng if (DepMI->readsRegister(Reg, &getRegisterInfo()) || !isPredicated(DepMI)) 3559020f4106f820648fd7e91956859844a80de13974Evan Cheng return 1; 3560020f4106f820648fd7e91956859844a80de13974Evan Cheng 3561020f4106f820648fd7e91956859844a80de13974Evan Cheng // If the second MI is predicated, then there is an implicit use dependency. 3562ef2d9e59aba381c42e018df9c26f9025c1995a64Andrew Trick return getInstrLatency(ItinData, DefMI); 3563020f4106f820648fd7e91956859844a80de13974Evan Cheng} 3564020f4106f820648fd7e91956859844a80de13974Evan Cheng 3565b7e0289fb320c8440ba5eed121a8b932dbd806a2Andrew Trickunsigned ARMBaseInstrInfo::getInstrLatency(const InstrItineraryData *ItinData, 3566b7e0289fb320c8440ba5eed121a8b932dbd806a2Andrew Trick const MachineInstr *MI, 3567b7e0289fb320c8440ba5eed121a8b932dbd806a2Andrew Trick unsigned *PredCost) const { 35688239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng if (MI->isCopyLike() || MI->isInsertSubreg() || 35698239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng MI->isRegSequence() || MI->isImplicitDef()) 35708239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng return 1; 35718239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng 3572ed7a51e69209af87f3749d5f95740f69a1dc7711Andrew Trick // An instruction scheduler typically runs on unbundled instructions, however 3573ed7a51e69209af87f3749d5f95740f69a1dc7711Andrew Trick // other passes may query the latency of a bundled instruction. 3574ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng if (MI->isBundle()) { 3575ed7a51e69209af87f3749d5f95740f69a1dc7711Andrew Trick unsigned Latency = 0; 3576ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng MachineBasicBlock::const_instr_iterator I = MI; 3577ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end(); 3578ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng while (++I != E && I->isInsideBundle()) { 3579ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng if (I->getOpcode() != ARM::t2IT) 3580ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng Latency += getInstrLatency(ItinData, I, PredCost); 3581ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng } 3582ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng return Latency; 3583ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng } 3584ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng 3585e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng const MCInstrDesc &MCID = MI->getDesc(); 3586ed7a51e69209af87f3749d5f95740f69a1dc7711Andrew Trick if (PredCost && (MCID.isCall() || MCID.hasImplicitDefOfPhysReg(ARM::CPSR))) { 35878239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng // When predicated, CPSR is an additional source operand for CPSR updating 35888239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng // instructions, this apparently increases their latencies. 35898239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng *PredCost = 1; 3590ed7a51e69209af87f3749d5f95740f69a1dc7711Andrew Trick } 3591ed7a51e69209af87f3749d5f95740f69a1dc7711Andrew Trick // Be sure to call getStageLatency for an empty itinerary in case it has a 3592ed7a51e69209af87f3749d5f95740f69a1dc7711Andrew Trick // valid MinLatency property. 3593ed7a51e69209af87f3749d5f95740f69a1dc7711Andrew Trick if (!ItinData) 3594ed7a51e69209af87f3749d5f95740f69a1dc7711Andrew Trick return MI->mayLoad() ? 3 : 1; 3595ed7a51e69209af87f3749d5f95740f69a1dc7711Andrew Trick 3596ed7a51e69209af87f3749d5f95740f69a1dc7711Andrew Trick unsigned Class = MCID.getSchedClass(); 3597ed7a51e69209af87f3749d5f95740f69a1dc7711Andrew Trick 3598ed7a51e69209af87f3749d5f95740f69a1dc7711Andrew Trick // For instructions with variable uops, use uops as latency. 359914ccc7b963861a856b593cc4fff62decd8ce248aAndrew Trick if (!ItinData->isEmpty() && ItinData->getNumMicroOps(Class) < 0) 3600ed7a51e69209af87f3749d5f95740f69a1dc7711Andrew Trick return getNumMicroOps(ItinData, MI); 360114ccc7b963861a856b593cc4fff62decd8ce248aAndrew Trick 3602ed7a51e69209af87f3749d5f95740f69a1dc7711Andrew Trick // For the common case, fall back on the itinerary's latency. 360368b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick unsigned Latency = ItinData->getStageLatency(Class); 360468b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick 360568b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick // Adjust for dynamic def-side opcode variants not captured by the itinerary. 360668b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick unsigned DefAlign = MI->hasOneMemOperand() 360768b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick ? (*MI->memoperands_begin())->getAlignment() : 0; 360868b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick int Adj = adjustDefLatency(Subtarget, MI, &MCID, DefAlign); 360968b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick if (Adj >= 0 || (int)Latency > -Adj) { 361068b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick return Latency + Adj; 361168b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick } 361268b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick return Latency; 36138239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng} 36148239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng 36158239daf7c83a65a189c352cce3191cdc3bbfe151Evan Chengint ARMBaseInstrInfo::getInstrLatency(const InstrItineraryData *ItinData, 36168239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng SDNode *Node) const { 36178239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng if (!Node->isMachineOpcode()) 36188239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng return 1; 36198239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng 36208239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng if (!ItinData || ItinData->isEmpty()) 36218239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng return 1; 36228239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng 36238239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng unsigned Opcode = Node->getMachineOpcode(); 36248239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng switch (Opcode) { 36258239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng default: 36268239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng return ItinData->getStageLatency(get(Opcode).getSchedClass()); 362773fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMQIA: 362873fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMQIA: 36298239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng return 2; 36308b3ca6216d62bf3f729c2e122dcfeb7c4d7500dcEric Christopher } 36318239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng} 36328239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng 36332312842de0c641107dd04d7e056d02491cc781caEvan Chengbool ARMBaseInstrInfo:: 36342312842de0c641107dd04d7e056d02491cc781caEvan ChenghasHighOperandLatency(const InstrItineraryData *ItinData, 36352312842de0c641107dd04d7e056d02491cc781caEvan Cheng const MachineRegisterInfo *MRI, 36362312842de0c641107dd04d7e056d02491cc781caEvan Cheng const MachineInstr *DefMI, unsigned DefIdx, 36372312842de0c641107dd04d7e056d02491cc781caEvan Cheng const MachineInstr *UseMI, unsigned UseIdx) const { 36382312842de0c641107dd04d7e056d02491cc781caEvan Cheng unsigned DDomain = DefMI->getDesc().TSFlags & ARMII::DomainMask; 36392312842de0c641107dd04d7e056d02491cc781caEvan Cheng unsigned UDomain = UseMI->getDesc().TSFlags & ARMII::DomainMask; 36402312842de0c641107dd04d7e056d02491cc781caEvan Cheng if (Subtarget.isCortexA8() && 36412312842de0c641107dd04d7e056d02491cc781caEvan Cheng (DDomain == ARMII::DomainVFP || UDomain == ARMII::DomainVFP)) 36422312842de0c641107dd04d7e056d02491cc781caEvan Cheng // CortexA8 VFP instructions are not pipelined. 36432312842de0c641107dd04d7e056d02491cc781caEvan Cheng return true; 36442312842de0c641107dd04d7e056d02491cc781caEvan Cheng 36452312842de0c641107dd04d7e056d02491cc781caEvan Cheng // Hoist VFP / NEON instructions with 4 or higher latency. 3646397f4e3583b36b23047fec06b1648f0771cd6fe3Andrew Trick int Latency = computeOperandLatency(ItinData, DefMI, DefIdx, UseMI, UseIdx, 3647397f4e3583b36b23047fec06b1648f0771cd6fe3Andrew Trick /*FindMin=*/false); 3648f377071bf8393d35797107c753da3e84aea94ebeAndrew Trick if (Latency < 0) 3649f377071bf8393d35797107c753da3e84aea94ebeAndrew Trick Latency = getInstrLatency(ItinData, DefMI); 36502312842de0c641107dd04d7e056d02491cc781caEvan Cheng if (Latency <= 3) 36512312842de0c641107dd04d7e056d02491cc781caEvan Cheng return false; 36522312842de0c641107dd04d7e056d02491cc781caEvan Cheng return DDomain == ARMII::DomainVFP || DDomain == ARMII::DomainNEON || 36532312842de0c641107dd04d7e056d02491cc781caEvan Cheng UDomain == ARMII::DomainVFP || UDomain == ARMII::DomainNEON; 36542312842de0c641107dd04d7e056d02491cc781caEvan Cheng} 3655c8141dfc7f983cb04e65d8acd6bcbdc8e4b8a0aeEvan Cheng 3656c8141dfc7f983cb04e65d8acd6bcbdc8e4b8a0aeEvan Chengbool ARMBaseInstrInfo:: 3657c8141dfc7f983cb04e65d8acd6bcbdc8e4b8a0aeEvan ChenghasLowDefLatency(const InstrItineraryData *ItinData, 3658c8141dfc7f983cb04e65d8acd6bcbdc8e4b8a0aeEvan Cheng const MachineInstr *DefMI, unsigned DefIdx) const { 3659c8141dfc7f983cb04e65d8acd6bcbdc8e4b8a0aeEvan Cheng if (!ItinData || ItinData->isEmpty()) 3660c8141dfc7f983cb04e65d8acd6bcbdc8e4b8a0aeEvan Cheng return false; 3661c8141dfc7f983cb04e65d8acd6bcbdc8e4b8a0aeEvan Cheng 3662c8141dfc7f983cb04e65d8acd6bcbdc8e4b8a0aeEvan Cheng unsigned DDomain = DefMI->getDesc().TSFlags & ARMII::DomainMask; 3663c8141dfc7f983cb04e65d8acd6bcbdc8e4b8a0aeEvan Cheng if (DDomain == ARMII::DomainGeneral) { 3664c8141dfc7f983cb04e65d8acd6bcbdc8e4b8a0aeEvan Cheng unsigned DefClass = DefMI->getDesc().getSchedClass(); 3665c8141dfc7f983cb04e65d8acd6bcbdc8e4b8a0aeEvan Cheng int DefCycle = ItinData->getOperandCycle(DefClass, DefIdx); 3666c8141dfc7f983cb04e65d8acd6bcbdc8e4b8a0aeEvan Cheng return (DefCycle != -1 && DefCycle <= 2); 3667c8141dfc7f983cb04e65d8acd6bcbdc8e4b8a0aeEvan Cheng } 3668c8141dfc7f983cb04e65d8acd6bcbdc8e4b8a0aeEvan Cheng return false; 3669c8141dfc7f983cb04e65d8acd6bcbdc8e4b8a0aeEvan Cheng} 367048575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng 36713be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trickbool ARMBaseInstrInfo::verifyInstruction(const MachineInstr *MI, 36723be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick StringRef &ErrInfo) const { 36733be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick if (convertAddSubFlagsOpcode(MI->getOpcode())) { 36743be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick ErrInfo = "Pseudo flag setting opcodes only exist in Selection DAG"; 36753be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick return false; 36763be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick } 36773be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick return true; 36783be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick} 36793be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick 368048575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Chengbool 368148575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan ChengARMBaseInstrInfo::isFpMLxInstruction(unsigned Opcode, unsigned &MulOpc, 368248575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng unsigned &AddSubOpc, 368348575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng bool &NegAcc, bool &HasLane) const { 368448575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng DenseMap<unsigned, unsigned>::const_iterator I = MLxEntryMap.find(Opcode); 368548575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng if (I == MLxEntryMap.end()) 368648575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng return false; 368748575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng 368848575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng const ARM_MLxEntry &Entry = ARM_MLxTable[I->second]; 368948575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng MulOpc = Entry.MulOpc; 369048575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng AddSubOpc = Entry.AddSubOpc; 369148575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng NegAcc = Entry.NegAcc; 369248575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng HasLane = Entry.HasLane; 369348575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng return true; 369448575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng} 369513fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen 369613fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen//===----------------------------------------------------------------------===// 369713fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen// Execution domains. 369813fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen//===----------------------------------------------------------------------===// 369913fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen// 370013fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen// Some instructions go down the NEON pipeline, some go down the VFP pipeline, 370113fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen// and some can go down both. The vmov instructions go down the VFP pipeline, 370213fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen// but they can be changed to vorr equivalents that are executed by the NEON 370313fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen// pipeline. 370413fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen// 370513fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen// We use the following execution domain numbering: 370613fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen// 37078bb3d3cb30df06bdcb3ef5a208e3e59f4eeb4868Jakob Stoklund Olesenenum ARMExeDomain { 37088bb3d3cb30df06bdcb3ef5a208e3e59f4eeb4868Jakob Stoklund Olesen ExeGeneric = 0, 37098bb3d3cb30df06bdcb3ef5a208e3e59f4eeb4868Jakob Stoklund Olesen ExeVFP = 1, 37108bb3d3cb30df06bdcb3ef5a208e3e59f4eeb4868Jakob Stoklund Olesen ExeNEON = 2 37118bb3d3cb30df06bdcb3ef5a208e3e59f4eeb4868Jakob Stoklund Olesen}; 371213fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen// 371313fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen// Also see ARMInstrFormats.td and Domain* enums in ARMBaseInfo.h 371413fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen// 371513fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesenstd::pair<uint16_t, uint16_t> 371613fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund OlesenARMBaseInstrInfo::getExecutionDomain(const MachineInstr *MI) const { 37173c8ad92455ff06c8e69085702ef1f13944eab4ddTim Northover // VMOVD, VMOVRS and VMOVSR are VFP instructions, but can be changed to NEON 37183c8ad92455ff06c8e69085702ef1f13944eab4ddTim Northover // if they are not predicated. 371913fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen if (MI->getOpcode() == ARM::VMOVD && !isPredicated(MI)) 37208bb3d3cb30df06bdcb3ef5a208e3e59f4eeb4868Jakob Stoklund Olesen return std::make_pair(ExeVFP, (1<<ExeVFP) | (1<<ExeNEON)); 372113fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen 3722616471d4bfe4717fa86259ff4534703357b3b723Silviu Baranga // A9-like cores are particularly picky about mixing the two and want these 37233c8ad92455ff06c8e69085702ef1f13944eab4ddTim Northover // converted. 3724616471d4bfe4717fa86259ff4534703357b3b723Silviu Baranga if (Subtarget.isLikeA9() && !isPredicated(MI) && 37253c8ad92455ff06c8e69085702ef1f13944eab4ddTim Northover (MI->getOpcode() == ARM::VMOVRS || 3726c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover MI->getOpcode() == ARM::VMOVSR || 3727c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover MI->getOpcode() == ARM::VMOVS)) 37283c8ad92455ff06c8e69085702ef1f13944eab4ddTim Northover return std::make_pair(ExeVFP, (1<<ExeVFP) | (1<<ExeNEON)); 37293c8ad92455ff06c8e69085702ef1f13944eab4ddTim Northover 373013fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen // No other instructions can be swizzled, so just determine their domain. 373113fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen unsigned Domain = MI->getDesc().TSFlags & ARMII::DomainMask; 373213fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen 373313fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen if (Domain & ARMII::DomainNEON) 37348bb3d3cb30df06bdcb3ef5a208e3e59f4eeb4868Jakob Stoklund Olesen return std::make_pair(ExeNEON, 0); 373513fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen 373613fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen // Certain instructions can go either way on Cortex-A8. 373713fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen // Treat them as NEON instructions. 373813fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen if ((Domain & ARMII::DomainNEONA8) && Subtarget.isCortexA8()) 37398bb3d3cb30df06bdcb3ef5a208e3e59f4eeb4868Jakob Stoklund Olesen return std::make_pair(ExeNEON, 0); 374013fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen 374113fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen if (Domain & ARMII::DomainVFP) 37428bb3d3cb30df06bdcb3ef5a208e3e59f4eeb4868Jakob Stoklund Olesen return std::make_pair(ExeVFP, 0); 374313fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen 37448bb3d3cb30df06bdcb3ef5a208e3e59f4eeb4868Jakob Stoklund Olesen return std::make_pair(ExeGeneric, 0); 374513fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen} 374613fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen 374720599ea4bced03634a54b52e98d261018366f279Tim Northoverstatic unsigned getCorrespondingDRegAndLane(const TargetRegisterInfo *TRI, 374820599ea4bced03634a54b52e98d261018366f279Tim Northover unsigned SReg, unsigned &Lane) { 374920599ea4bced03634a54b52e98d261018366f279Tim Northover unsigned DReg = TRI->getMatchingSuperReg(SReg, ARM::ssub_0, &ARM::DPRRegClass); 375020599ea4bced03634a54b52e98d261018366f279Tim Northover Lane = 0; 375120599ea4bced03634a54b52e98d261018366f279Tim Northover 375220599ea4bced03634a54b52e98d261018366f279Tim Northover if (DReg != ARM::NoRegister) 375320599ea4bced03634a54b52e98d261018366f279Tim Northover return DReg; 375420599ea4bced03634a54b52e98d261018366f279Tim Northover 375520599ea4bced03634a54b52e98d261018366f279Tim Northover Lane = 1; 375620599ea4bced03634a54b52e98d261018366f279Tim Northover DReg = TRI->getMatchingSuperReg(SReg, ARM::ssub_1, &ARM::DPRRegClass); 375720599ea4bced03634a54b52e98d261018366f279Tim Northover 375820599ea4bced03634a54b52e98d261018366f279Tim Northover assert(DReg && "S-register with no D super-register?"); 375920599ea4bced03634a54b52e98d261018366f279Tim Northover return DReg; 376020599ea4bced03634a54b52e98d261018366f279Tim Northover} 376120599ea4bced03634a54b52e98d261018366f279Tim Northover 37622d15d641aa8aa9e48c268170f1a9825bb9926fc7Andrew Trick/// getImplicitSPRUseForDPRUse - Given a use of a DPR register and lane, 376397ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy/// set ImplicitSReg to a register number that must be marked as implicit-use or 376497ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy/// zero if no register needs to be defined as implicit-use. 376597ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy/// 376697ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy/// If the function cannot determine if an SPR should be marked implicit use or 376797ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy/// not, it returns false. 376897ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy/// 376997ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy/// This function handles cases where an instruction is being modified from taking 37702d15d641aa8aa9e48c268170f1a9825bb9926fc7Andrew Trick/// an SPR to a DPR[Lane]. A use of the DPR is being added, which may conflict 377197ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy/// with an earlier def of an SPR corresponding to DPR[Lane^1] (i.e. the other 377297ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy/// lane of the DPR). 377397ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy/// 377497ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy/// If the other SPR is defined, an implicit-use of it should be added. Else, 377597ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy/// (including the case where the DPR itself is defined), it should not. 37762d15d641aa8aa9e48c268170f1a9825bb9926fc7Andrew Trick/// 377797ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloystatic bool getImplicitSPRUseForDPRUse(const TargetRegisterInfo *TRI, 377897ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy MachineInstr *MI, 377997ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy unsigned DReg, unsigned Lane, 378097ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy unsigned &ImplicitSReg) { 378197ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy // If the DPR is defined or used already, the other SPR lane will be chained 378297ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy // correctly, so there is nothing to be done. 378397ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy if (MI->definesRegister(DReg, TRI) || MI->readsRegister(DReg, TRI)) { 378497ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy ImplicitSReg = 0; 378597ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy return true; 378697ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy } 378797ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy 378897ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy // Otherwise we need to go searching to see if the SPR is set explicitly. 378997ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy ImplicitSReg = TRI->getSubReg(DReg, 379097ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy (Lane & 1) ? ARM::ssub_0 : ARM::ssub_1); 379197ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy MachineBasicBlock::LivenessQueryResult LQR = 379297ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy MI->getParent()->computeRegisterLiveness(TRI, ImplicitSReg, MI); 379397ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy 379497ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy if (LQR == MachineBasicBlock::LQR_Live) 379597ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy return true; 379697ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy else if (LQR == MachineBasicBlock::LQR_Unknown) 379797ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy return false; 379897ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy 379997ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy // If the register is known not to be live, there is no need to add an 380097ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy // implicit-use. 380197ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy ImplicitSReg = 0; 380297ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy return true; 380397ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy} 380420599ea4bced03634a54b52e98d261018366f279Tim Northover 380513fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesenvoid 380613fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund OlesenARMBaseInstrInfo::setExecutionDomain(MachineInstr *MI, unsigned Domain) const { 38073c8ad92455ff06c8e69085702ef1f13944eab4ddTim Northover unsigned DstReg, SrcReg, DReg; 38083c8ad92455ff06c8e69085702ef1f13944eab4ddTim Northover unsigned Lane; 38093c8ad92455ff06c8e69085702ef1f13944eab4ddTim Northover MachineInstrBuilder MIB(MI); 38103c8ad92455ff06c8e69085702ef1f13944eab4ddTim Northover const TargetRegisterInfo *TRI = &getRegisterInfo(); 38113c8ad92455ff06c8e69085702ef1f13944eab4ddTim Northover switch (MI->getOpcode()) { 38123c8ad92455ff06c8e69085702ef1f13944eab4ddTim Northover default: 38133c8ad92455ff06c8e69085702ef1f13944eab4ddTim Northover llvm_unreachable("cannot handle opcode!"); 38143c8ad92455ff06c8e69085702ef1f13944eab4ddTim Northover break; 38153c8ad92455ff06c8e69085702ef1f13944eab4ddTim Northover case ARM::VMOVD: 38163c8ad92455ff06c8e69085702ef1f13944eab4ddTim Northover if (Domain != ExeNEON) 38173c8ad92455ff06c8e69085702ef1f13944eab4ddTim Northover break; 38183c8ad92455ff06c8e69085702ef1f13944eab4ddTim Northover 38193c8ad92455ff06c8e69085702ef1f13944eab4ddTim Northover // Zap the predicate operands. 38203c8ad92455ff06c8e69085702ef1f13944eab4ddTim Northover assert(!isPredicated(MI) && "Cannot predicate a VORRd"); 38213c8ad92455ff06c8e69085702ef1f13944eab4ddTim Northover 382220599ea4bced03634a54b52e98d261018366f279Tim Northover // Source instruction is %DDst = VMOVD %DSrc, 14, %noreg (; implicits) 382320599ea4bced03634a54b52e98d261018366f279Tim Northover DstReg = MI->getOperand(0).getReg(); 382420599ea4bced03634a54b52e98d261018366f279Tim Northover SrcReg = MI->getOperand(1).getReg(); 38253c8ad92455ff06c8e69085702ef1f13944eab4ddTim Northover 382620599ea4bced03634a54b52e98d261018366f279Tim Northover for (unsigned i = MI->getDesc().getNumOperands(); i; --i) 382720599ea4bced03634a54b52e98d261018366f279Tim Northover MI->RemoveOperand(i-1); 382820599ea4bced03634a54b52e98d261018366f279Tim Northover 382920599ea4bced03634a54b52e98d261018366f279Tim Northover // Change to a %DDst = VORRd %DSrc, %DSrc, 14, %noreg (; implicits) 383020599ea4bced03634a54b52e98d261018366f279Tim Northover MI->setDesc(get(ARM::VORRd)); 383120599ea4bced03634a54b52e98d261018366f279Tim Northover AddDefaultPred(MIB.addReg(DstReg, RegState::Define) 383220599ea4bced03634a54b52e98d261018366f279Tim Northover .addReg(SrcReg) 383320599ea4bced03634a54b52e98d261018366f279Tim Northover .addReg(SrcReg)); 38343c8ad92455ff06c8e69085702ef1f13944eab4ddTim Northover break; 38353c8ad92455ff06c8e69085702ef1f13944eab4ddTim Northover case ARM::VMOVRS: 38363c8ad92455ff06c8e69085702ef1f13944eab4ddTim Northover if (Domain != ExeNEON) 38373c8ad92455ff06c8e69085702ef1f13944eab4ddTim Northover break; 38383c8ad92455ff06c8e69085702ef1f13944eab4ddTim Northover assert(!isPredicated(MI) && "Cannot predicate a VGETLN"); 38393c8ad92455ff06c8e69085702ef1f13944eab4ddTim Northover 384020599ea4bced03634a54b52e98d261018366f279Tim Northover // Source instruction is %RDst = VMOVRS %SSrc, 14, %noreg (; implicits) 38413c8ad92455ff06c8e69085702ef1f13944eab4ddTim Northover DstReg = MI->getOperand(0).getReg(); 38423c8ad92455ff06c8e69085702ef1f13944eab4ddTim Northover SrcReg = MI->getOperand(1).getReg(); 384313fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen 384420599ea4bced03634a54b52e98d261018366f279Tim Northover for (unsigned i = MI->getDesc().getNumOperands(); i; --i) 384520599ea4bced03634a54b52e98d261018366f279Tim Northover MI->RemoveOperand(i-1); 38463c8ad92455ff06c8e69085702ef1f13944eab4ddTim Northover 384720599ea4bced03634a54b52e98d261018366f279Tim Northover DReg = getCorrespondingDRegAndLane(TRI, SrcReg, Lane); 38483c8ad92455ff06c8e69085702ef1f13944eab4ddTim Northover 384920599ea4bced03634a54b52e98d261018366f279Tim Northover // Convert to %RDst = VGETLNi32 %DSrc, Lane, 14, %noreg (; imps) 385020599ea4bced03634a54b52e98d261018366f279Tim Northover // Note that DSrc has been widened and the other lane may be undef, which 385120599ea4bced03634a54b52e98d261018366f279Tim Northover // contaminates the entire register. 38523c8ad92455ff06c8e69085702ef1f13944eab4ddTim Northover MI->setDesc(get(ARM::VGETLNi32)); 385320599ea4bced03634a54b52e98d261018366f279Tim Northover AddDefaultPred(MIB.addReg(DstReg, RegState::Define) 385420599ea4bced03634a54b52e98d261018366f279Tim Northover .addReg(DReg, RegState::Undef) 385520599ea4bced03634a54b52e98d261018366f279Tim Northover .addImm(Lane)); 38563c8ad92455ff06c8e69085702ef1f13944eab4ddTim Northover 385720599ea4bced03634a54b52e98d261018366f279Tim Northover // The old source should be an implicit use, otherwise we might think it 385820599ea4bced03634a54b52e98d261018366f279Tim Northover // was dead before here. 38593c8ad92455ff06c8e69085702ef1f13944eab4ddTim Northover MIB.addReg(SrcReg, RegState::Implicit); 38603c8ad92455ff06c8e69085702ef1f13944eab4ddTim Northover break; 386197ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy case ARM::VMOVSR: { 38623c8ad92455ff06c8e69085702ef1f13944eab4ddTim Northover if (Domain != ExeNEON) 38633c8ad92455ff06c8e69085702ef1f13944eab4ddTim Northover break; 38643c8ad92455ff06c8e69085702ef1f13944eab4ddTim Northover assert(!isPredicated(MI) && "Cannot predicate a VSETLN"); 38653c8ad92455ff06c8e69085702ef1f13944eab4ddTim Northover 386620599ea4bced03634a54b52e98d261018366f279Tim Northover // Source instruction is %SDst = VMOVSR %RSrc, 14, %noreg (; implicits) 38673c8ad92455ff06c8e69085702ef1f13944eab4ddTim Northover DstReg = MI->getOperand(0).getReg(); 38683c8ad92455ff06c8e69085702ef1f13944eab4ddTim Northover SrcReg = MI->getOperand(1).getReg(); 38693c8ad92455ff06c8e69085702ef1f13944eab4ddTim Northover 387020599ea4bced03634a54b52e98d261018366f279Tim Northover DReg = getCorrespondingDRegAndLane(TRI, DstReg, Lane); 38713c8ad92455ff06c8e69085702ef1f13944eab4ddTim Northover 387297ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy unsigned ImplicitSReg; 387397ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy if (!getImplicitSPRUseForDPRUse(TRI, MI, DReg, Lane, ImplicitSReg)) 387497ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy break; 387589f49808ee79eebbc3267b6c595514d4ca1f3247Tim Northover 38767bebddf55ece46995f310d79195afb4e5b239886Tim Northover for (unsigned i = MI->getDesc().getNumOperands(); i; --i) 38777bebddf55ece46995f310d79195afb4e5b239886Tim Northover MI->RemoveOperand(i-1); 38787bebddf55ece46995f310d79195afb4e5b239886Tim Northover 387920599ea4bced03634a54b52e98d261018366f279Tim Northover // Convert to %DDst = VSETLNi32 %DDst, %RSrc, Lane, 14, %noreg (; imps) 388020599ea4bced03634a54b52e98d261018366f279Tim Northover // Again DDst may be undefined at the beginning of this instruction. 388120599ea4bced03634a54b52e98d261018366f279Tim Northover MI->setDesc(get(ARM::VSETLNi32)); 388289f49808ee79eebbc3267b6c595514d4ca1f3247Tim Northover MIB.addReg(DReg, RegState::Define) 388389f49808ee79eebbc3267b6c595514d4ca1f3247Tim Northover .addReg(DReg, getUndefRegState(!MI->readsRegister(DReg, TRI))) 388489f49808ee79eebbc3267b6c595514d4ca1f3247Tim Northover .addReg(SrcReg) 388589f49808ee79eebbc3267b6c595514d4ca1f3247Tim Northover .addImm(Lane); 388689f49808ee79eebbc3267b6c595514d4ca1f3247Tim Northover AddDefaultPred(MIB); 3887c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover 388889f49808ee79eebbc3267b6c595514d4ca1f3247Tim Northover // The narrower destination must be marked as set to keep previous chains 388989f49808ee79eebbc3267b6c595514d4ca1f3247Tim Northover // in place. 389020599ea4bced03634a54b52e98d261018366f279Tim Northover MIB.addReg(DstReg, RegState::Define | RegState::Implicit); 389197ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy if (ImplicitSReg != 0) 389297ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy MIB.addReg(ImplicitSReg, RegState::Implicit); 38933c8ad92455ff06c8e69085702ef1f13944eab4ddTim Northover break; 389497ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy } 3895c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover case ARM::VMOVS: { 3896c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover if (Domain != ExeNEON) 3897c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover break; 3898c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover 3899c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover // Source instruction is %SDst = VMOVS %SSrc, 14, %noreg (; implicits) 3900c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover DstReg = MI->getOperand(0).getReg(); 3901c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover SrcReg = MI->getOperand(1).getReg(); 3902c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover 3903c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover unsigned DstLane = 0, SrcLane = 0, DDst, DSrc; 3904c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover DDst = getCorrespondingDRegAndLane(TRI, DstReg, DstLane); 3905c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover DSrc = getCorrespondingDRegAndLane(TRI, SrcReg, SrcLane); 3906c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover 390797ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy unsigned ImplicitSReg; 390897ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy if (!getImplicitSPRUseForDPRUse(TRI, MI, DSrc, SrcLane, ImplicitSReg)) 390997ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy break; 391089f49808ee79eebbc3267b6c595514d4ca1f3247Tim Northover 39117bebddf55ece46995f310d79195afb4e5b239886Tim Northover for (unsigned i = MI->getDesc().getNumOperands(); i; --i) 39127bebddf55ece46995f310d79195afb4e5b239886Tim Northover MI->RemoveOperand(i-1); 39137bebddf55ece46995f310d79195afb4e5b239886Tim Northover 3914c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover if (DSrc == DDst) { 3915c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover // Destination can be: 3916c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover // %DDst = VDUPLN32d %DDst, Lane, 14, %noreg (; implicits) 3917c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover MI->setDesc(get(ARM::VDUPLN32d)); 391889f49808ee79eebbc3267b6c595514d4ca1f3247Tim Northover MIB.addReg(DDst, RegState::Define) 391989f49808ee79eebbc3267b6c595514d4ca1f3247Tim Northover .addReg(DDst, getUndefRegState(!MI->readsRegister(DDst, TRI))) 392089f49808ee79eebbc3267b6c595514d4ca1f3247Tim Northover .addImm(SrcLane); 392189f49808ee79eebbc3267b6c595514d4ca1f3247Tim Northover AddDefaultPred(MIB); 3922c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover 3923c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover // Neither the source or the destination are naturally represented any 3924c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover // more, so add them in manually. 3925c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover MIB.addReg(DstReg, RegState::Implicit | RegState::Define); 3926c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover MIB.addReg(SrcReg, RegState::Implicit); 392797ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy if (ImplicitSReg != 0) 392897ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy MIB.addReg(ImplicitSReg, RegState::Implicit); 3929c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover break; 3930c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover } 3931c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover 3932c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover // In general there's no single instruction that can perform an S <-> S 3933c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover // move in NEON space, but a pair of VEXT instructions *can* do the 3934c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover // job. It turns out that the VEXTs needed will only use DSrc once, with 3935c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover // the position based purely on the combination of lane-0 and lane-1 3936c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover // involved. For example 3937c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover // vmov s0, s2 -> vext.32 d0, d0, d1, #1 vext.32 d0, d0, d0, #1 3938c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover // vmov s1, s3 -> vext.32 d0, d1, d0, #1 vext.32 d0, d0, d0, #1 3939c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover // vmov s0, s3 -> vext.32 d0, d0, d0, #1 vext.32 d0, d1, d0, #1 3940c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover // vmov s1, s2 -> vext.32 d0, d0, d0, #1 vext.32 d0, d0, d1, #1 3941c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover // 3942c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover // Pattern of the MachineInstrs is: 3943c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover // %DDst = VEXTd32 %DSrc1, %DSrc2, Lane, 14, %noreg (;implicits) 3944c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover MachineInstrBuilder NewMIB; 3945c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover NewMIB = BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), 3946c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover get(ARM::VEXTd32), DDst); 394789f49808ee79eebbc3267b6c595514d4ca1f3247Tim Northover 394889f49808ee79eebbc3267b6c595514d4ca1f3247Tim Northover // On the first instruction, both DSrc and DDst may be <undef> if present. 394989f49808ee79eebbc3267b6c595514d4ca1f3247Tim Northover // Specifically when the original instruction didn't have them as an 395089f49808ee79eebbc3267b6c595514d4ca1f3247Tim Northover // <imp-use>. 395189f49808ee79eebbc3267b6c595514d4ca1f3247Tim Northover unsigned CurReg = SrcLane == 1 && DstLane == 1 ? DSrc : DDst; 395289f49808ee79eebbc3267b6c595514d4ca1f3247Tim Northover bool CurUndef = !MI->readsRegister(CurReg, TRI); 395389f49808ee79eebbc3267b6c595514d4ca1f3247Tim Northover NewMIB.addReg(CurReg, getUndefRegState(CurUndef)); 395489f49808ee79eebbc3267b6c595514d4ca1f3247Tim Northover 395589f49808ee79eebbc3267b6c595514d4ca1f3247Tim Northover CurReg = SrcLane == 0 && DstLane == 0 ? DSrc : DDst; 395689f49808ee79eebbc3267b6c595514d4ca1f3247Tim Northover CurUndef = !MI->readsRegister(CurReg, TRI); 395789f49808ee79eebbc3267b6c595514d4ca1f3247Tim Northover NewMIB.addReg(CurReg, getUndefRegState(CurUndef)); 395889f49808ee79eebbc3267b6c595514d4ca1f3247Tim Northover 3959c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover NewMIB.addImm(1); 3960c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover AddDefaultPred(NewMIB); 3961c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover 3962c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover if (SrcLane == DstLane) 3963c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover NewMIB.addReg(SrcReg, RegState::Implicit); 3964c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover 3965c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover MI->setDesc(get(ARM::VEXTd32)); 3966c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover MIB.addReg(DDst, RegState::Define); 396789f49808ee79eebbc3267b6c595514d4ca1f3247Tim Northover 396889f49808ee79eebbc3267b6c595514d4ca1f3247Tim Northover // On the second instruction, DDst has definitely been defined above, so 396989f49808ee79eebbc3267b6c595514d4ca1f3247Tim Northover // it is not <undef>. DSrc, if present, can be <undef> as above. 397089f49808ee79eebbc3267b6c595514d4ca1f3247Tim Northover CurReg = SrcLane == 1 && DstLane == 0 ? DSrc : DDst; 397189f49808ee79eebbc3267b6c595514d4ca1f3247Tim Northover CurUndef = CurReg == DSrc && !MI->readsRegister(CurReg, TRI); 397289f49808ee79eebbc3267b6c595514d4ca1f3247Tim Northover MIB.addReg(CurReg, getUndefRegState(CurUndef)); 397389f49808ee79eebbc3267b6c595514d4ca1f3247Tim Northover 397489f49808ee79eebbc3267b6c595514d4ca1f3247Tim Northover CurReg = SrcLane == 0 && DstLane == 1 ? DSrc : DDst; 397589f49808ee79eebbc3267b6c595514d4ca1f3247Tim Northover CurUndef = CurReg == DSrc && !MI->readsRegister(CurReg, TRI); 397689f49808ee79eebbc3267b6c595514d4ca1f3247Tim Northover MIB.addReg(CurReg, getUndefRegState(CurUndef)); 397789f49808ee79eebbc3267b6c595514d4ca1f3247Tim Northover 3978c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover MIB.addImm(1); 3979c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover AddDefaultPred(MIB); 3980c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover 3981c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover if (SrcLane != DstLane) 3982c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover MIB.addReg(SrcReg, RegState::Implicit); 3983c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover 3984c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover // As before, the original destination is no longer represented, add it 3985c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover // implicitly. 3986c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover MIB.addReg(DstReg, RegState::Define | RegState::Implicit); 398797ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy if (ImplicitSReg != 0) 398897ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy MIB.addReg(ImplicitSReg, RegState::Implicit); 3989c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover break; 3990c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover } 39913c8ad92455ff06c8e69085702ef1f13944eab4ddTim Northover } 39928bb3d3cb30df06bdcb3ef5a208e3e59f4eeb4868Jakob Stoklund Olesen 399313fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen} 3994c01810eeb7227010f73cb39e3c4fa0197a3c4ef0Jim Grosbach 3995eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson//===----------------------------------------------------------------------===// 3996eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson// Partial register updates 3997eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson//===----------------------------------------------------------------------===// 3998eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson// 3999eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson// Swift renames NEON registers with 64-bit granularity. That means any 4000eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson// instruction writing an S-reg implicitly reads the containing D-reg. The 4001eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson// problem is mostly avoided by translating f32 operations to v2f32 operations 4002eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson// on D-registers, but f32 loads are still a problem. 4003eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson// 4004eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson// These instructions can load an f32 into a NEON register: 4005eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson// 4006eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson// VLDRS - Only writes S, partial D update. 4007eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson// VLD1LNd32 - Writes all D-regs, explicit partial D update, 2 uops. 4008eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson// VLD1DUPd32 - Writes all D-regs, no partial reg update, 2 uops. 4009eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson// 4010eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson// FCONSTD can be used as a dependency-breaking instruction. 4011eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson 4012eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson 4013eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilsonunsigned ARMBaseInstrInfo:: 4014eb1641d54a7eda7717304bc4d55d059208d8ebedBob WilsongetPartialRegUpdateClearance(const MachineInstr *MI, 4015eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson unsigned OpNum, 4016eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson const TargetRegisterInfo *TRI) const { 4017eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson // Only Swift has partial register update problems. 4018eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson if (!SwiftPartialUpdateClearance || !Subtarget.isSwift()) 4019eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson return 0; 4020eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson 4021eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson assert(TRI && "Need TRI instance"); 4022eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson 4023eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson const MachineOperand &MO = MI->getOperand(OpNum); 4024eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson if (MO.readsReg()) 4025eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson return 0; 4026eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson unsigned Reg = MO.getReg(); 4027eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson int UseOp = -1; 4028eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson 4029eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson switch(MI->getOpcode()) { 4030eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson // Normal instructions writing only an S-register. 4031eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::VLDRS: 4032eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::FCONSTS: 4033eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::VMOVSR: 4034eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson // rdar://problem/8791586 4035eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::VMOVv8i8: 4036eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::VMOVv4i16: 4037eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::VMOVv2i32: 4038eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::VMOVv2f32: 4039eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::VMOVv1i64: 4040eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson UseOp = MI->findRegisterUseOperandIdx(Reg, false, TRI); 4041eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson break; 4042eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson 4043eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson // Explicitly reads the dependency. 4044eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::VLD1LNd32: 4045eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson UseOp = 1; 4046eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson break; 4047eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson default: 4048eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson return 0; 4049eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson } 4050eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson 4051eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson // If this instruction actually reads a value from Reg, there is no unwanted 4052eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson // dependency. 4053eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson if (UseOp != -1 && MI->getOperand(UseOp).readsReg()) 4054eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson return 0; 4055eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson 4056eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson // We must be able to clobber the whole D-reg. 4057eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson if (TargetRegisterInfo::isVirtualRegister(Reg)) { 4058eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson // Virtual register must be a foo:ssub_0<def,undef> operand. 4059eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson if (!MO.getSubReg() || MI->readsVirtualRegister(Reg)) 4060eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson return 0; 4061eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson } else if (ARM::SPRRegClass.contains(Reg)) { 4062eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson // Physical register: MI must define the full D-reg. 4063eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson unsigned DReg = TRI->getMatchingSuperReg(Reg, ARM::ssub_0, 4064eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson &ARM::DPRRegClass); 4065eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson if (!DReg || !MI->definesRegister(DReg, TRI)) 4066eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson return 0; 4067eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson } 4068eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson 4069eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson // MI has an unwanted D-register dependency. 4070eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson // Avoid defs in the previous N instructrions. 4071eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson return SwiftPartialUpdateClearance; 4072eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson} 4073eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson 4074eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson// Break a partial register dependency after getPartialRegUpdateClearance 4075eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson// returned non-zero. 4076eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilsonvoid ARMBaseInstrInfo:: 4077eb1641d54a7eda7717304bc4d55d059208d8ebedBob WilsonbreakPartialRegDependency(MachineBasicBlock::iterator MI, 4078eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson unsigned OpNum, 4079eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson const TargetRegisterInfo *TRI) const { 4080eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson assert(MI && OpNum < MI->getDesc().getNumDefs() && "OpNum is not a def"); 4081eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson assert(TRI && "Need TRI instance"); 4082eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson 4083eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson const MachineOperand &MO = MI->getOperand(OpNum); 4084eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson unsigned Reg = MO.getReg(); 4085eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson assert(TargetRegisterInfo::isPhysicalRegister(Reg) && 4086eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson "Can't break virtual register dependencies."); 4087eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson unsigned DReg = Reg; 4088eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson 4089eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson // If MI defines an S-reg, find the corresponding D super-register. 4090eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson if (ARM::SPRRegClass.contains(Reg)) { 4091eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson DReg = ARM::D0 + (Reg - ARM::S0) / 2; 4092eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson assert(TRI->isSuperRegister(Reg, DReg) && "Register enums broken"); 4093eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson } 4094eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson 4095eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson assert(ARM::DPRRegClass.contains(DReg) && "Can only break D-reg deps"); 4096eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson assert(MI->definesRegister(DReg, TRI) && "MI doesn't clobber full D-reg"); 4097eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson 4098eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson // FIXME: In some cases, VLDRS can be changed to a VLD1DUPd32 which defines 4099eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson // the full D-register by loading the same value to both lanes. The 4100eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson // instruction is micro-coded with 2 uops, so don't do this until we can 4101eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson // properly schedule micro-coded instuctions. The dispatcher stalls cause 4102eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson // too big regressions. 4103eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson 4104eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson // Insert the dependency-breaking FCONSTD before MI. 4105eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson // 96 is the encoding of 0.5, but the actual value doesn't matter here. 4106eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson AddDefaultPred(BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), 4107eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson get(ARM::FCONSTD), DReg).addImm(96)); 4108eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson MI->addRegisterKilled(DReg, TRI, true); 4109eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson} 4110eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson 4111c01810eeb7227010f73cb39e3c4fa0197a3c4ef0Jim Grosbachbool ARMBaseInstrInfo::hasNOP() const { 4112c01810eeb7227010f73cb39e3c4fa0197a3c4ef0Jim Grosbach return (Subtarget.getFeatureBits() & ARM::HasV6T2Ops) != 0; 4113c01810eeb7227010f73cb39e3c4fa0197a3c4ef0Jim Grosbach} 4114