ARMBaseInstrInfo.cpp revision 2da8bc8a5f7705ac131184cd247f48500da0d74e
131c24bf5b39cc8391d4cfdbf8cf5163975fdb81eJim Grosbach//===- ARMBaseInstrInfo.cpp - ARM Instruction Information -------*- C++ -*-===// 2334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// 3334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// The LLVM Compiler Infrastructure 4334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// 5334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// This file is distributed under the University of Illinois Open Source 6334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// License. See LICENSE.TXT for details. 7334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// 8334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin//===----------------------------------------------------------------------===// 9334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// 10334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// This file contains the Base ARM implementation of the TargetInstrInfo class. 11334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// 12334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin//===----------------------------------------------------------------------===// 13334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 14334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "ARMBaseInstrInfo.h" 15334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "ARM.h" 16334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "ARMAddressingModes.h" 17d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng#include "ARMConstantPoolValue.h" 1848575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng#include "ARMHazardRecognizer.h" 19334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "ARMMachineFunctionInfo.h" 20f95215f551949d5e5adfbf4753aa833b9009b77aAnton Korobeynikov#include "ARMRegisterInfo.h" 214dbbe3433f7339ed277af55037ff6847f484e5abChris Lattner#include "ARMGenInstrInfo.inc" 22fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng#include "llvm/Constants.h" 23fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng#include "llvm/Function.h" 24fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng#include "llvm/GlobalValue.h" 25334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "llvm/CodeGen/LiveVariables.h" 26d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng#include "llvm/CodeGen/MachineConstantPool.h" 27334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "llvm/CodeGen/MachineFrameInfo.h" 28334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "llvm/CodeGen/MachineInstrBuilder.h" 29334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "llvm/CodeGen/MachineJumpTableInfo.h" 30249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov#include "llvm/CodeGen/MachineMemOperand.h" 312457f2c66184e978d4ed8fa9e2128effff26cb0bEvan Cheng#include "llvm/CodeGen/MachineRegisterInfo.h" 32249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov#include "llvm/CodeGen/PseudoSourceValue.h" 33af76e592c7f9deff0e55c13dbb4a34f07f1c7f64Chris Lattner#include "llvm/MC/MCAsmInfo.h" 34334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "llvm/Support/CommandLine.h" 35f95215f551949d5e5adfbf4753aa833b9009b77aAnton Korobeynikov#include "llvm/Support/Debug.h" 36c25e7581b9b8088910da31702d4ca21c4734c6d7Torok Edwin#include "llvm/Support/ErrorHandling.h" 3740a5eb18b031fa1a5e9697e21e251e613d441cc5Bill Wendling#include "llvm/ADT/STLExtras.h" 38334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinusing namespace llvm; 39334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 40334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinstatic cl::opt<bool> 41334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinEnableARM3Addr("enable-arm-3-addr-conv", cl::Hidden, 42334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin cl::desc("Enable ARM 2-addr to 3-addr conv")); 43334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 442da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick// Other targets already have a hazard recognizer enabled by default, so this 452da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick// flag currently only affects ARM. It will be generalized when it becomes a 462da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick// disabled flag. 472da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trickstatic cl::opt<bool> EnableHazardRecognizer( 482da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick "enable-sched-hazard", cl::Hidden, 492da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick cl::desc("Enable hazard detection during preRA scheduling"), 502da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick cl::init(false)); 5148575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng 5248575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng/// ARM_MLxEntry - Record information about MLA / MLS instructions. 5348575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Chengstruct ARM_MLxEntry { 5448575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng unsigned MLxOpc; // MLA / MLS opcode 5548575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng unsigned MulOpc; // Expanded multiplication opcode 5648575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng unsigned AddSubOpc; // Expanded add / sub opcode 5748575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng bool NegAcc; // True if the acc is negated before the add / sub. 5848575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng bool HasLane; // True if instruction has an extra "lane" operand. 5948575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng}; 6048575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng 6148575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Chengstatic const ARM_MLxEntry ARM_MLxTable[] = { 6248575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng // MLxOpc, MulOpc, AddSubOpc, NegAcc, HasLane 6348575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng // fp scalar ops 6448575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng { ARM::VMLAS, ARM::VMULS, ARM::VADDS, false, false }, 6548575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng { ARM::VMLSS, ARM::VMULS, ARM::VSUBS, false, false }, 6648575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng { ARM::VMLAD, ARM::VMULD, ARM::VADDD, false, false }, 6748575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng { ARM::VMLSD, ARM::VMULD, ARM::VSUBD, false, false }, 6848575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng { ARM::VNMLAS, ARM::VNMULS, ARM::VSUBS, true, false }, 6948575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng { ARM::VNMLSS, ARM::VMULS, ARM::VSUBS, true, false }, 7048575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng { ARM::VNMLAD, ARM::VNMULD, ARM::VSUBD, true, false }, 7148575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng { ARM::VNMLSD, ARM::VMULD, ARM::VSUBD, true, false }, 7248575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng 7348575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng // fp SIMD ops 7448575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng { ARM::VMLAfd, ARM::VMULfd, ARM::VADDfd, false, false }, 7548575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng { ARM::VMLSfd, ARM::VMULfd, ARM::VSUBfd, false, false }, 7648575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng { ARM::VMLAfq, ARM::VMULfq, ARM::VADDfq, false, false }, 7748575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng { ARM::VMLSfq, ARM::VMULfq, ARM::VSUBfq, false, false }, 7848575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng { ARM::VMLAslfd, ARM::VMULslfd, ARM::VADDfd, false, true }, 7948575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng { ARM::VMLSslfd, ARM::VMULslfd, ARM::VSUBfd, false, true }, 8048575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng { ARM::VMLAslfq, ARM::VMULslfq, ARM::VADDfq, false, true }, 8148575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng { ARM::VMLSslfq, ARM::VMULslfq, ARM::VSUBfq, false, true }, 8248575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng}; 8348575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng 84f95215f551949d5e5adfbf4753aa833b9009b77aAnton KorobeynikovARMBaseInstrInfo::ARMBaseInstrInfo(const ARMSubtarget& STI) 85f95215f551949d5e5adfbf4753aa833b9009b77aAnton Korobeynikov : TargetInstrInfoImpl(ARMInsts, array_lengthof(ARMInsts)), 86f95215f551949d5e5adfbf4753aa833b9009b77aAnton Korobeynikov Subtarget(STI) { 8748575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng for (unsigned i = 0, e = array_lengthof(ARM_MLxTable); i != e; ++i) { 8848575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng if (!MLxEntryMap.insert(std::make_pair(ARM_MLxTable[i].MLxOpc, i)).second) 8948575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng assert(false && "Duplicated entries?"); 9048575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng MLxHazardOpcodes.insert(ARM_MLxTable[i].AddSubOpc); 9148575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng MLxHazardOpcodes.insert(ARM_MLxTable[i].MulOpc); 9248575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng } 9348575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng} 9448575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng 952da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick// Use a ScoreboardHazardRecognizer for prepass ARM scheduling. TargetInstrImpl 962da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick// currently defaults to no prepass hazard recognizer. 9748575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan ChengScheduleHazardRecognizer *ARMBaseInstrInfo:: 982da8bc8a5f7705ac131184cd247f48500da0d74eAndrew TrickCreateTargetHazardRecognizer(const TargetMachine *TM, 992da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick const ScheduleDAG *DAG) const { 1002da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick if (EnableHazardRecognizer) { 1012da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick const InstrItineraryData *II = TM->getInstrItineraryData(); 1022da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick return new ScoreboardHazardRecognizer(II, DAG, "pre-RA-sched"); 1032da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick } 1042da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick return TargetInstrInfoImpl::CreateTargetHazardRecognizer(TM, DAG); 1052da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick} 1062da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick 1072da8bc8a5f7705ac131184cd247f48500da0d74eAndrew TrickScheduleHazardRecognizer *ARMBaseInstrInfo:: 1082da8bc8a5f7705ac131184cd247f48500da0d74eAndrew TrickCreateTargetPostRAHazardRecognizer(const InstrItineraryData *II, 1092da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick const ScheduleDAG *DAG) const { 11048575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng if (Subtarget.isThumb2() || Subtarget.hasVFP2()) 11148575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng return (ScheduleHazardRecognizer *) 1122da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick new ARMHazardRecognizer(II, *this, getRegisterInfo(), Subtarget, DAG); 1132da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick return TargetInstrInfoImpl::CreateTargetPostRAHazardRecognizer(II, DAG); 114334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 115334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 116334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinMachineInstr * 117334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinARMBaseInstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI, 118334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineBasicBlock::iterator &MBBI, 119334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin LiveVariables *LV) const { 12078703ddafe3d037f75d8ca188e4829d238289ac3Evan Cheng // FIXME: Thumb2 support. 12178703ddafe3d037f75d8ca188e4829d238289ac3Evan Cheng 122334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (!EnableARM3Addr) 123334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return NULL; 124334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 125334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineInstr *MI = MBBI; 126334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineFunction &MF = *MI->getParent()->getParent(); 12799405df044f2c584242e711cc9023ec90356da82Bruno Cardoso Lopes uint64_t TSFlags = MI->getDesc().TSFlags; 128334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool isPre = false; 129334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin switch ((TSFlags & ARMII::IndexModeMask) >> ARMII::IndexModeShift) { 130334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin default: return NULL; 131334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMII::IndexModePre: 132334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin isPre = true; 133334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin break; 134334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMII::IndexModePost: 135334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin break; 136334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 137334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 138334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Try splitting an indexed load/store to an un-indexed one plus an add/sub 139334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // operation. 140334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned MemOpc = getUnindexedOpcode(MI->getOpcode()); 141334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (MemOpc == 0) 142334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return NULL; 143334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 144334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineInstr *UpdateMI = NULL; 145334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineInstr *MemMI = NULL; 146334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned AddrMode = (TSFlags & ARMII::AddrModeMask); 147334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const TargetInstrDesc &TID = MI->getDesc(); 148334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned NumOps = TID.getNumOperands(); 149334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool isLoad = !TID.mayStore(); 150334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const MachineOperand &WB = isLoad ? MI->getOperand(1) : MI->getOperand(0); 151334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const MachineOperand &Base = MI->getOperand(2); 152334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const MachineOperand &Offset = MI->getOperand(NumOps-3); 153334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned WBReg = WB.getReg(); 154334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned BaseReg = Base.getReg(); 155334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned OffReg = Offset.getReg(); 156334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned OffImm = MI->getOperand(NumOps-2).getImm(); 157334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin ARMCC::CondCodes Pred = (ARMCC::CondCodes)MI->getOperand(NumOps-1).getImm(); 158334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin switch (AddrMode) { 159334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin default: 160334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin assert(false && "Unknown indexed op!"); 161334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return NULL; 162334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMII::AddrMode2: { 163334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool isSub = ARM_AM::getAM2Op(OffImm) == ARM_AM::sub; 164334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned Amt = ARM_AM::getAM2Offset(OffImm); 165334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (OffReg == 0) { 166e7cbe4118b7ddf05032ff8772a98c51e1637bb5cEvan Cheng if (ARM_AM::getSOImmVal(Amt) == -1) 167334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Can't encode it in a so_imm operand. This transformation will 168334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // add more than 1 instruction. Abandon! 169334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return NULL; 170334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin UpdateMI = BuildMI(MF, MI->getDebugLoc(), 17178703ddafe3d037f75d8ca188e4829d238289ac3Evan Cheng get(isSub ? ARM::SUBri : ARM::ADDri), WBReg) 172e7cbe4118b7ddf05032ff8772a98c51e1637bb5cEvan Cheng .addReg(BaseReg).addImm(Amt) 173334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addImm(Pred).addReg(0).addReg(0); 174334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } else if (Amt != 0) { 175334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin ARM_AM::ShiftOpc ShOpc = ARM_AM::getAM2ShiftOpc(OffImm); 176334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned SOOpc = ARM_AM::getSORegOpc(ShOpc, Amt); 177334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin UpdateMI = BuildMI(MF, MI->getDebugLoc(), 17878703ddafe3d037f75d8ca188e4829d238289ac3Evan Cheng get(isSub ? ARM::SUBrs : ARM::ADDrs), WBReg) 179334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(BaseReg).addReg(OffReg).addReg(0).addImm(SOOpc) 180334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addImm(Pred).addReg(0).addReg(0); 181334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } else 182334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin UpdateMI = BuildMI(MF, MI->getDebugLoc(), 18378703ddafe3d037f75d8ca188e4829d238289ac3Evan Cheng get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg) 184334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(BaseReg).addReg(OffReg) 185334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addImm(Pred).addReg(0).addReg(0); 186334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin break; 187334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 188334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMII::AddrMode3 : { 189334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool isSub = ARM_AM::getAM3Op(OffImm) == ARM_AM::sub; 190334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned Amt = ARM_AM::getAM3Offset(OffImm); 191334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (OffReg == 0) 192334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Immediate is 8-bits. It's guaranteed to fit in a so_imm operand. 193334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin UpdateMI = BuildMI(MF, MI->getDebugLoc(), 19478703ddafe3d037f75d8ca188e4829d238289ac3Evan Cheng get(isSub ? ARM::SUBri : ARM::ADDri), WBReg) 195334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(BaseReg).addImm(Amt) 196334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addImm(Pred).addReg(0).addReg(0); 197334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin else 198334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin UpdateMI = BuildMI(MF, MI->getDebugLoc(), 19978703ddafe3d037f75d8ca188e4829d238289ac3Evan Cheng get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg) 200334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(BaseReg).addReg(OffReg) 201334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addImm(Pred).addReg(0).addReg(0); 202334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin break; 203334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 204334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 205334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 206334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin std::vector<MachineInstr*> NewMIs; 207334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (isPre) { 208334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (isLoad) 209334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MemMI = BuildMI(MF, MI->getDebugLoc(), 210334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin get(MemOpc), MI->getOperand(0).getReg()) 2113e5561247202bae994dd259a2d8dc4eff8f799f3Jim Grosbach .addReg(WBReg).addImm(0).addImm(Pred); 212334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin else 213334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MemMI = BuildMI(MF, MI->getDebugLoc(), 214334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin get(MemOpc)).addReg(MI->getOperand(1).getReg()) 215334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(WBReg).addReg(0).addImm(0).addImm(Pred); 216334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin NewMIs.push_back(MemMI); 217334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin NewMIs.push_back(UpdateMI); 218334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } else { 219334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (isLoad) 220334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MemMI = BuildMI(MF, MI->getDebugLoc(), 221334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin get(MemOpc), MI->getOperand(0).getReg()) 2223e5561247202bae994dd259a2d8dc4eff8f799f3Jim Grosbach .addReg(BaseReg).addImm(0).addImm(Pred); 223334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin else 224334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MemMI = BuildMI(MF, MI->getDebugLoc(), 225334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin get(MemOpc)).addReg(MI->getOperand(1).getReg()) 226334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred); 227334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (WB.isDead()) 228334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin UpdateMI->getOperand(0).setIsDead(); 229334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin NewMIs.push_back(UpdateMI); 230334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin NewMIs.push_back(MemMI); 231334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 232334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 233334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Transfer LiveVariables states, kill / dead info. 234334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (LV) { 235334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 236334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineOperand &MO = MI->getOperand(i); 237334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (MO.isReg() && MO.getReg() && 238334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin TargetRegisterInfo::isVirtualRegister(MO.getReg())) { 239334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned Reg = MO.getReg(); 240334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 241334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin LiveVariables::VarInfo &VI = LV->getVarInfo(Reg); 242334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (MO.isDef()) { 243334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineInstr *NewMI = (Reg == WBReg) ? UpdateMI : MemMI; 244334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (MO.isDead()) 245334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin LV->addVirtualRegisterDead(Reg, NewMI); 246334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 247334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (MO.isUse() && MO.isKill()) { 248334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin for (unsigned j = 0; j < 2; ++j) { 249334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Look at the two new MI's in reverse order. 250334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineInstr *NewMI = NewMIs[j]; 251334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (!NewMI->readsRegister(Reg)) 252334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin continue; 253334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin LV->addVirtualRegisterKilled(Reg, NewMI); 254334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (VI.removeKill(MI)) 255334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin VI.Kills.push_back(NewMI); 256334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin break; 257334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 258334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 259334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 260334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 261334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 262334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 263334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MFI->insert(MBBI, NewMIs[1]); 264334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MFI->insert(MBBI, NewMIs[0]); 265334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return NewMIs[0]; 266334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 267334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 268334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// Branch analysis. 269334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinbool 270334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinARMBaseInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB, 271334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineBasicBlock *&FBB, 272334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin SmallVectorImpl<MachineOperand> &Cond, 273334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool AllowModify) const { 274334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // If the block has no terminators, it just falls into the block after it. 275334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineBasicBlock::iterator I = MBB.end(); 27693d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen if (I == MBB.begin()) 27793d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen return false; 27893d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen --I; 27993d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen while (I->isDebugValue()) { 28093d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen if (I == MBB.begin()) 28193d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen return false; 28293d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen --I; 28393d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen } 28493d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen if (!isUnpredicatedTerminator(I)) 285334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 286334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 287334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Get the last instruction in the block. 288334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineInstr *LastInst = I; 289334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 290334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // If there is only one terminator instruction, process it. 291334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned LastOpc = LastInst->getOpcode(); 292334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) { 2935ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng if (isUncondBranchOpcode(LastOpc)) { 294334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin TBB = LastInst->getOperand(0).getMBB(); 295334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 296334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 2975ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng if (isCondBranchOpcode(LastOpc)) { 298334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Block ends with fall-through condbranch. 299334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin TBB = LastInst->getOperand(0).getMBB(); 300334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin Cond.push_back(LastInst->getOperand(1)); 301334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin Cond.push_back(LastInst->getOperand(2)); 302334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 303334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 304334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; // Can't handle indirect branch. 305334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 306334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 307334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Get the instruction before it if it is a terminator. 308334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineInstr *SecondLastInst = I; 309108c8724663354050dc09bb1262c3e4511adf82fEvan Cheng unsigned SecondLastOpc = SecondLastInst->getOpcode(); 310108c8724663354050dc09bb1262c3e4511adf82fEvan Cheng 311108c8724663354050dc09bb1262c3e4511adf82fEvan Cheng // If AllowModify is true and the block ends with two or more unconditional 312108c8724663354050dc09bb1262c3e4511adf82fEvan Cheng // branches, delete all but the first unconditional branch. 313108c8724663354050dc09bb1262c3e4511adf82fEvan Cheng if (AllowModify && isUncondBranchOpcode(LastOpc)) { 314108c8724663354050dc09bb1262c3e4511adf82fEvan Cheng while (isUncondBranchOpcode(SecondLastOpc)) { 315108c8724663354050dc09bb1262c3e4511adf82fEvan Cheng LastInst->eraseFromParent(); 316108c8724663354050dc09bb1262c3e4511adf82fEvan Cheng LastInst = SecondLastInst; 317108c8724663354050dc09bb1262c3e4511adf82fEvan Cheng LastOpc = LastInst->getOpcode(); 318676e258366dd17a0b4ee6ac66914237ce181202eEvan Cheng if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) { 319676e258366dd17a0b4ee6ac66914237ce181202eEvan Cheng // Return now the only terminator is an unconditional branch. 320676e258366dd17a0b4ee6ac66914237ce181202eEvan Cheng TBB = LastInst->getOperand(0).getMBB(); 321676e258366dd17a0b4ee6ac66914237ce181202eEvan Cheng return false; 322676e258366dd17a0b4ee6ac66914237ce181202eEvan Cheng } else { 323108c8724663354050dc09bb1262c3e4511adf82fEvan Cheng SecondLastInst = I; 324108c8724663354050dc09bb1262c3e4511adf82fEvan Cheng SecondLastOpc = SecondLastInst->getOpcode(); 325108c8724663354050dc09bb1262c3e4511adf82fEvan Cheng } 326108c8724663354050dc09bb1262c3e4511adf82fEvan Cheng } 327108c8724663354050dc09bb1262c3e4511adf82fEvan Cheng } 328334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 329334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // If there are three terminators, we don't know what sort of block this is. 330334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(--I)) 331334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; 332334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 3335ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng // If the block ends with a B and a Bcc, handle it. 3345ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng if (isCondBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) { 335334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin TBB = SecondLastInst->getOperand(0).getMBB(); 336334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin Cond.push_back(SecondLastInst->getOperand(1)); 337334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin Cond.push_back(SecondLastInst->getOperand(2)); 338334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin FBB = LastInst->getOperand(0).getMBB(); 339334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 340334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 341334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 342334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // If the block ends with two unconditional branches, handle it. The second 343334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // one is not executed, so remove it. 3445ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng if (isUncondBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) { 345334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin TBB = SecondLastInst->getOperand(0).getMBB(); 346334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin I = LastInst; 347334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (AllowModify) 348334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin I->eraseFromParent(); 349334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 350334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 351334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 352334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // ...likewise if it ends with a branch table followed by an unconditional 353334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // branch. The branch folder can create these, and we must get rid of them for 354334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // correctness of Thumb constant islands. 3558d4de5abfa1bcd974554ea14904ebf7af289e84dBob Wilson if ((isJumpTableBranchOpcode(SecondLastOpc) || 3568d4de5abfa1bcd974554ea14904ebf7af289e84dBob Wilson isIndirectBranchOpcode(SecondLastOpc)) && 3575ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng isUncondBranchOpcode(LastOpc)) { 358334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin I = LastInst; 359334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (AllowModify) 360334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin I->eraseFromParent(); 361334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; 362334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 363334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 364334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Otherwise, can't handle this. 365334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; 366334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 367334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 368334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 369334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinunsigned ARMBaseInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const { 370334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineBasicBlock::iterator I = MBB.end(); 371334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (I == MBB.begin()) return 0; 372334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin --I; 37393d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen while (I->isDebugValue()) { 37493d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen if (I == MBB.begin()) 37593d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen return 0; 37693d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen --I; 37793d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen } 3785ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng if (!isUncondBranchOpcode(I->getOpcode()) && 3795ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng !isCondBranchOpcode(I->getOpcode())) 380334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 0; 381334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 382334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Remove the branch. 383334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin I->eraseFromParent(); 384334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 385334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin I = MBB.end(); 386334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 387334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (I == MBB.begin()) return 1; 388334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin --I; 3895ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng if (!isCondBranchOpcode(I->getOpcode())) 390334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 1; 391334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 392334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Remove the branch. 393334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin I->eraseFromParent(); 394334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 2; 395334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 396334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 397334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinunsigned 398334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinARMBaseInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 3993bf912593301152b65accb9d9c37a95172f1df5aStuart Hastings MachineBasicBlock *FBB, 4003bf912593301152b65accb9d9c37a95172f1df5aStuart Hastings const SmallVectorImpl<MachineOperand> &Cond, 4013bf912593301152b65accb9d9c37a95172f1df5aStuart Hastings DebugLoc DL) const { 4026495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ARMFunctionInfo *AFI = MBB.getParent()->getInfo<ARMFunctionInfo>(); 4036495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng int BOpc = !AFI->isThumbFunction() 4046495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ? ARM::B : (AFI->isThumb2Function() ? ARM::t2B : ARM::tB); 4056495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng int BccOpc = !AFI->isThumbFunction() 4066495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ? ARM::Bcc : (AFI->isThumb2Function() ? ARM::t2Bcc : ARM::tBcc); 407334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 408334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Shouldn't be a fall through. 409334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin assert(TBB && "InsertBranch must not be told to insert a fallthrough"); 410334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin assert((Cond.size() == 2 || Cond.size() == 0) && 411334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin "ARM branch conditions have two components!"); 412334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 413334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (FBB == 0) { 414334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (Cond.empty()) // Unconditional branch? 4153bf912593301152b65accb9d9c37a95172f1df5aStuart Hastings BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB); 416334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin else 4173bf912593301152b65accb9d9c37a95172f1df5aStuart Hastings BuildMI(&MBB, DL, get(BccOpc)).addMBB(TBB) 418334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()); 419334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 1; 420334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 421334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 422334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Two-way conditional branch. 4233bf912593301152b65accb9d9c37a95172f1df5aStuart Hastings BuildMI(&MBB, DL, get(BccOpc)).addMBB(TBB) 424334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()); 4253bf912593301152b65accb9d9c37a95172f1df5aStuart Hastings BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB); 426334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 2; 427334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 428334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 429334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinbool ARMBaseInstrInfo:: 430334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const { 431334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin ARMCC::CondCodes CC = (ARMCC::CondCodes)(int)Cond[0].getImm(); 432334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin Cond[0].setImm(ARMCC::getOppositeCondition(CC)); 433334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 434334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 435334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 436334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinbool ARMBaseInstrInfo:: 437334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinPredicateInstruction(MachineInstr *MI, 438334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const SmallVectorImpl<MachineOperand> &Pred) const { 439334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned Opc = MI->getOpcode(); 4405ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng if (isUncondBranchOpcode(Opc)) { 4415ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng MI->setDesc(get(getMatchingCondBranchOpcode(Opc))); 442334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI->addOperand(MachineOperand::CreateImm(Pred[0].getImm())); 443334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI->addOperand(MachineOperand::CreateReg(Pred[1].getReg(), false)); 444334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; 445334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 446334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 447334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin int PIdx = MI->findFirstPredOperandIdx(); 448334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (PIdx != -1) { 449334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineOperand &PMO = MI->getOperand(PIdx); 450334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin PMO.setImm(Pred[0].getImm()); 451334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI->getOperand(PIdx+1).setReg(Pred[1].getReg()); 452334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; 453334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 454334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 455334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 456334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 457334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinbool ARMBaseInstrInfo:: 458334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinSubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1, 459334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const SmallVectorImpl<MachineOperand> &Pred2) const { 460334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (Pred1.size() > 2 || Pred2.size() > 2) 461334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 462334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 463334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin ARMCC::CondCodes CC1 = (ARMCC::CondCodes)Pred1[0].getImm(); 464334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin ARMCC::CondCodes CC2 = (ARMCC::CondCodes)Pred2[0].getImm(); 465334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (CC1 == CC2) 466334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; 467334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 468334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin switch (CC1) { 469334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin default: 470334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 471334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMCC::AL: 472334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; 473334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMCC::HS: 474334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return CC2 == ARMCC::HI; 475334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMCC::LS: 476334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return CC2 == ARMCC::LO || CC2 == ARMCC::EQ; 477334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMCC::GE: 478334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return CC2 == ARMCC::GT; 479334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMCC::LE: 480334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return CC2 == ARMCC::LT; 481334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 482334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 483334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 484334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinbool ARMBaseInstrInfo::DefinesPredicate(MachineInstr *MI, 485334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin std::vector<MachineOperand> &Pred) const { 4868fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng // FIXME: This confuses implicit_def with optional CPSR def. 487334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const TargetInstrDesc &TID = MI->getDesc(); 488334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (!TID.getImplicitDefs() && !TID.hasOptionalDef()) 489334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 490334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 491334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool Found = false; 492334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 493334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const MachineOperand &MO = MI->getOperand(i); 494334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (MO.isReg() && MO.getReg() == ARM::CPSR) { 495334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin Pred.push_back(MO); 496334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin Found = true; 497334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 498334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 499334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 500334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return Found; 501334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 502334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 503ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng/// isPredicable - Return true if the specified instruction can be predicated. 504ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng/// By default, this returns true for every instruction with a 505ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng/// PredicateOperand. 506ac0869dc8a7986855c5557cc67d4709600158ef5Evan Chengbool ARMBaseInstrInfo::isPredicable(MachineInstr *MI) const { 507ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng const TargetInstrDesc &TID = MI->getDesc(); 508ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng if (!TID.isPredicable()) 509ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng return false; 510ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng 511ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng if ((TID.TSFlags & ARMII::DomainMask) == ARMII::DomainNEON) { 512ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng ARMFunctionInfo *AFI = 513ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng MI->getParent()->getParent()->getInfo<ARMFunctionInfo>(); 514d7f0810c934a7d13acb28c42d737ce58ec990ea8Evan Cheng return AFI->isThumb2Function(); 515ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng } 516ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng return true; 517ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng} 518334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 51956856b1f46ec1f073ceef4e826c544b8b1691608Chris Lattner/// FIXME: Works around a gcc miscompilation with -fstrict-aliasing. 52019e57025d458d3cb50804fd821fd89b868a819bdChandler CarruthLLVM_ATTRIBUTE_NOINLINE 521334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinstatic unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT, 52256856b1f46ec1f073ceef4e826c544b8b1691608Chris Lattner unsigned JTI); 523334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinstatic unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT, 524334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned JTI) { 52556856b1f46ec1f073ceef4e826c544b8b1691608Chris Lattner assert(JTI < JT.size()); 526334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return JT[JTI].MBBs.size(); 527334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 528334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 529334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin/// GetInstSize - Return the size of the specified MachineInstr. 530334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin/// 531334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinunsigned ARMBaseInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const { 532334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const MachineBasicBlock &MBB = *MI->getParent(); 533334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const MachineFunction *MF = MBB.getParent(); 53433adcfb4d217f5f23d9bde8ba02b8e48f9605fc5Chris Lattner const MCAsmInfo *MAI = MF->getTarget().getMCAsmInfo(); 535334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 536334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Basic size info comes from the TSFlags field. 537334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const TargetInstrDesc &TID = MI->getDesc(); 53899405df044f2c584242e711cc9023ec90356da82Bruno Cardoso Lopes uint64_t TSFlags = TID.TSFlags; 539334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 540a0ee862f2e3a0d202244e02459ddcf0dca0e8607Evan Cheng unsigned Opc = MI->getOpcode(); 541334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin switch ((TSFlags & ARMII::SizeMask) >> ARMII::SizeShift) { 542334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin default: { 543334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // If this machine instr is an inline asm, measure it. 544334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (MI->getOpcode() == ARM::INLINEASM) 54533adcfb4d217f5f23d9bde8ba02b8e48f9605fc5Chris Lattner return getInlineAsmLength(MI->getOperand(0).getSymbolName(), *MAI); 546334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (MI->isLabel()) 547334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 0; 548a0ee862f2e3a0d202244e02459ddcf0dca0e8607Evan Cheng switch (Opc) { 549334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin default: 550c23197a26f34f559ea9797de51e187087c039c42Torok Edwin llvm_unreachable("Unknown or unset size field for instr!"); 551518bb53485df640d7b7e3f6b0544099020c42aa7Chris Lattner case TargetOpcode::IMPLICIT_DEF: 552518bb53485df640d7b7e3f6b0544099020c42aa7Chris Lattner case TargetOpcode::KILL: 5537431beaba2a01c3fe299c861b2ec85cbf1dc81c4Bill Wendling case TargetOpcode::PROLOG_LABEL: 554518bb53485df640d7b7e3f6b0544099020c42aa7Chris Lattner case TargetOpcode::EH_LABEL: 555375be7730a6f3dee7a6dc319ee6c355a11ac99adDale Johannesen case TargetOpcode::DBG_VALUE: 556334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 0; 557334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 558334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin break; 559334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 560789476240d6b6f8ad9366cadf790a82bd41bb0b3Evan Cheng case ARMII::Size8Bytes: return 8; // ARM instruction x 2. 561789476240d6b6f8ad9366cadf790a82bd41bb0b3Evan Cheng case ARMII::Size4Bytes: return 4; // ARM / Thumb2 instruction. 562789476240d6b6f8ad9366cadf790a82bd41bb0b3Evan Cheng case ARMII::Size2Bytes: return 2; // Thumb1 instruction. 563334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMII::SizeSpecial: { 564a0ee862f2e3a0d202244e02459ddcf0dca0e8607Evan Cheng switch (Opc) { 5653c38f96af2a5443d9f72fd078c2c98dd08746e51Jim Grosbach case ARM::MOVi32imm: 5663c38f96af2a5443d9f72fd078c2c98dd08746e51Jim Grosbach case ARM::t2MOVi32imm: 5673c38f96af2a5443d9f72fd078c2c98dd08746e51Jim Grosbach return 8; 568334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARM::CONSTPOOL_ENTRY: 569334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // If this machine instr is a constant pool entry, its size is recorded as 570334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // operand #2. 571334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return MI->getOperand(2).getImm(); 5725eb195153950bc7ebfc30649494a78b2096b5ef8Jim Grosbach case ARM::Int_eh_sjlj_longjmp: 5735eb195153950bc7ebfc30649494a78b2096b5ef8Jim Grosbach return 16; 5745eb195153950bc7ebfc30649494a78b2096b5ef8Jim Grosbach case ARM::tInt_eh_sjlj_longjmp: 5755eb195153950bc7ebfc30649494a78b2096b5ef8Jim Grosbach return 10; 576789476240d6b6f8ad9366cadf790a82bd41bb0b3Evan Cheng case ARM::Int_eh_sjlj_setjmp: 577d100755bab38784703f677b8b8eb174b624b346bJim Grosbach case ARM::Int_eh_sjlj_setjmp_nofp: 5780798eddd07b8dc827a4e6e9028c4c3a8d9444286Jim Grosbach return 20; 579d122874996a6faa8832569b632fd73a32ace7ae7Jim Grosbach case ARM::tInt_eh_sjlj_setjmp: 5805aa1684e5da9a85286bf7d29da419d261a70c2f2Jim Grosbach case ARM::t2Int_eh_sjlj_setjmp: 581d100755bab38784703f677b8b8eb174b624b346bJim Grosbach case ARM::t2Int_eh_sjlj_setjmp_nofp: 5820798eddd07b8dc827a4e6e9028c4c3a8d9444286Jim Grosbach return 12; 583334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARM::BR_JTr: 584334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARM::BR_JTm: 585334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARM::BR_JTadd: 586a0ee862f2e3a0d202244e02459ddcf0dca0e8607Evan Cheng case ARM::tBR_JTr: 587d26b14c34cbcee1448b86b524578fc51cc979023Evan Cheng case ARM::t2BR_JT: 588d092a87ba3f905a6801a0bdf816267329cf0391cJim Grosbach case ARM::t2TBB_JT: 589d092a87ba3f905a6801a0bdf816267329cf0391cJim Grosbach case ARM::t2TBH_JT: { 590334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // These are jumptable branches, i.e. a branch followed by an inlined 591d26b14c34cbcee1448b86b524578fc51cc979023Evan Cheng // jumptable. The size is 4 + 4 * number of entries. For TBB, each 592d26b14c34cbcee1448b86b524578fc51cc979023Evan Cheng // entry is one byte; TBH two byte each. 593d092a87ba3f905a6801a0bdf816267329cf0391cJim Grosbach unsigned EntrySize = (Opc == ARM::t2TBB_JT) 594d092a87ba3f905a6801a0bdf816267329cf0391cJim Grosbach ? 1 : ((Opc == ARM::t2TBH_JT) ? 2 : 4); 595334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned NumOps = TID.getNumOperands(); 596334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineOperand JTOP = 597334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI->getOperand(NumOps - (TID.isPredicable() ? 3 : 2)); 598334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned JTI = JTOP.getIndex(); 599334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo(); 600b1e803985d3378538ae9cff7eed4102c002d1e22Chris Lattner assert(MJTI != 0); 601334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables(); 602334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin assert(JTI < JT.size()); 603334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Thumb instructions are 2 byte aligned, but JT entries are 4 byte 604334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // 4 aligned. The assembler / linker may add 2 byte padding just before 605334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // the JT entries. The size does not include this padding; the 606334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // constant islands pass does separate bookkeeping for it. 607334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // FIXME: If we know the size of the function is less than (1 << 16) *2 608334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // bytes, we can use 16-bit entries instead. Then there won't be an 609334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // alignment issue. 61025f7cfc3cccba6f569f29f79ea533bae960b93c0Evan Cheng unsigned InstSize = (Opc == ARM::tBR_JTr || Opc == ARM::t2BR_JT) ? 2 : 4; 61125f7cfc3cccba6f569f29f79ea533bae960b93c0Evan Cheng unsigned NumEntries = getNumJTEntries(JT, JTI); 612d092a87ba3f905a6801a0bdf816267329cf0391cJim Grosbach if (Opc == ARM::t2TBB_JT && (NumEntries & 1)) 61325f7cfc3cccba6f569f29f79ea533bae960b93c0Evan Cheng // Make sure the instruction that follows TBB is 2-byte aligned. 61425f7cfc3cccba6f569f29f79ea533bae960b93c0Evan Cheng // FIXME: Constant island pass should insert an "ALIGN" instruction 61525f7cfc3cccba6f569f29f79ea533bae960b93c0Evan Cheng // instead. 61625f7cfc3cccba6f569f29f79ea533bae960b93c0Evan Cheng ++NumEntries; 61725f7cfc3cccba6f569f29f79ea533bae960b93c0Evan Cheng return NumEntries * EntrySize + InstSize; 618334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 619334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin default: 620334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Otherwise, pseudo-instruction sizes are zero. 621334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 0; 622334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 623334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 624334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 625334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 0; // Not reached 626334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 627334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 628ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesenvoid ARMBaseInstrInfo::copyPhysReg(MachineBasicBlock &MBB, 629ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen MachineBasicBlock::iterator I, DebugLoc DL, 630ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen unsigned DestReg, unsigned SrcReg, 631ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen bool KillSrc) const { 632ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen bool GPRDest = ARM::GPRRegClass.contains(DestReg); 633ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen bool GPRSrc = ARM::GPRRegClass.contains(SrcReg); 634ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen 635ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen if (GPRDest && GPRSrc) { 636ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen AddDefaultCC(AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::MOVr), DestReg) 637ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen .addReg(SrcReg, getKillRegState(KillSrc)))); 638ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen return; 6397bfdca0206f51132b26094c6f83a5ac97ee0f943David Goodwin } 640334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 641ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen bool SPRDest = ARM::SPRRegClass.contains(DestReg); 642ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen bool SPRSrc = ARM::SPRRegClass.contains(SrcReg); 643ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen 644ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen unsigned Opc; 645ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen if (SPRDest && SPRSrc) 646ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen Opc = ARM::VMOVS; 647ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen else if (GPRDest && SPRSrc) 648ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen Opc = ARM::VMOVRS; 649ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen else if (SPRDest && GPRSrc) 650ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen Opc = ARM::VMOVSR; 651ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen else if (ARM::DPRRegClass.contains(DestReg, SrcReg)) 652ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen Opc = ARM::VMOVD; 653ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen else if (ARM::QPRRegClass.contains(DestReg, SrcReg)) 654ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen Opc = ARM::VMOVQ; 655ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen else if (ARM::QQPRRegClass.contains(DestReg, SrcReg)) 656ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen Opc = ARM::VMOVQQ; 657ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen else if (ARM::QQQQPRRegClass.contains(DestReg, SrcReg)) 658ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen Opc = ARM::VMOVQQQQ; 659ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen else 660ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen llvm_unreachable("Impossible reg-to-reg copy"); 661ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen 662ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc), DestReg); 663ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen MIB.addReg(SrcReg, getKillRegState(KillSrc)); 664ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen if (Opc != ARM::VMOVQQ && Opc != ARM::VMOVQQQQ) 665ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen AddDefaultPred(MIB); 666334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 667334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 668c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Chengstatic const 669c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan ChengMachineInstrBuilder &AddDReg(MachineInstrBuilder &MIB, 670c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Cheng unsigned Reg, unsigned SubIdx, unsigned State, 671c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Cheng const TargetRegisterInfo *TRI) { 672c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Cheng if (!SubIdx) 673c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Cheng return MIB.addReg(Reg, State); 674c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Cheng 675c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Cheng if (TargetRegisterInfo::isPhysicalRegister(Reg)) 676c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Cheng return MIB.addReg(TRI->getSubReg(Reg, SubIdx), State); 677c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Cheng return MIB.addReg(Reg, State, SubIdx); 678c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Cheng} 679c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Cheng 680334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinvoid ARMBaseInstrInfo:: 681334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinstoreRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 682334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned SrcReg, bool isKill, int FI, 683746ad69e088176819981b4b2c5ac8dcd49f5e60eEvan Cheng const TargetRegisterClass *RC, 684746ad69e088176819981b4b2c5ac8dcd49f5e60eEvan Cheng const TargetRegisterInfo *TRI) const { 685c7f3ace20c325521c68335a1689645b43b06ddf0Chris Lattner DebugLoc DL; 686334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (I != MBB.end()) DL = I->getDebugLoc(); 687249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MachineFunction &MF = *MBB.getParent(); 688249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MachineFrameInfo &MFI = *MF.getFrameInfo(); 68931bc849123011b8eae6bb3c79876d9a3c26a6a1dJim Grosbach unsigned Align = MFI.getObjectAlignment(FI); 690249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov 691249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MachineMemOperand *MMO = 69259db5496f4fc2ef6111569e542f8b65480ef14c1Chris Lattner MF.getMachineMemOperand(MachinePointerInfo( 69359db5496f4fc2ef6111569e542f8b65480ef14c1Chris Lattner PseudoSourceValue::getFixedStack(FI)), 69459db5496f4fc2ef6111569e542f8b65480ef14c1Chris Lattner MachineMemOperand::MOStore, 695249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MFI.getObjectSize(FI), 69631bc849123011b8eae6bb3c79876d9a3c26a6a1dJim Grosbach Align); 697334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 6980eb0c7401c34c0b4604f732ce54db995eead14e6Bob Wilson // tGPR is used sometimes in ARM instructions that need to avoid using 6996ccfc507dc1f7ad8c8964193a2407264ca644f0dJim Grosbach // certain registers. Just treat it as GPR here. Likewise, rGPR. 7006ccfc507dc1f7ad8c8964193a2407264ca644f0dJim Grosbach if (RC == ARM::tGPRRegisterClass || RC == ARM::tcGPRRegisterClass 7016ccfc507dc1f7ad8c8964193a2407264ca644f0dJim Grosbach || RC == ARM::rGPRRegisterClass) 7020eb0c7401c34c0b4604f732ce54db995eead14e6Bob Wilson RC = ARM::GPRRegisterClass; 7030eb0c7401c34c0b4604f732ce54db995eead14e6Bob Wilson 704ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson switch (RC->getID()) { 705ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson case ARM::GPRRegClassID: 7067e3383c007f53b3a00675af225e428cb66ddf404Jim Grosbach AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::STRi12)) 707334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(SrcReg, getKillRegState(isKill)) 7087e3383c007f53b3a00675af225e428cb66ddf404Jim Grosbach .addFrameIndex(FI).addImm(0).addMemOperand(MMO)); 709ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson break; 710ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson case ARM::SPRRegClassID: 711d31c5496d7e1580058b5c6fbc8fd537a641ea590Evan Cheng AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTRS)) 712d31c5496d7e1580058b5c6fbc8fd537a641ea590Evan Cheng .addReg(SrcReg, getKillRegState(isKill)) 713d31c5496d7e1580058b5c6fbc8fd537a641ea590Evan Cheng .addFrameIndex(FI).addImm(0).addMemOperand(MMO)); 714ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson break; 715ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson case ARM::DPRRegClassID: 716ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson case ARM::DPR_VFP2RegClassID: 717ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson case ARM::DPR_8RegClassID: 718e5165490b7ba24bb2f3043399e0d60e7f3bcf8a5Jim Grosbach AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTRD)) 719334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(SrcReg, getKillRegState(isKill)) 720249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov .addFrameIndex(FI).addImm(0).addMemOperand(MMO)); 721ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson break; 722ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson case ARM::QPRRegClassID: 723ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson case ARM::QPR_VFP2RegClassID: 724ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson case ARM::QPR_8RegClassID: 7250cfcf93c95af91e809ef740eb0ab368477226b40Jim Grosbach if (Align >= 16 && getRegisterInfo().needsStackRealignment(MF)) { 726168f382dc67e5940cabdb28dc933c4f91cdd3137Bob Wilson AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1q64Pseudo)) 727f967ca0eaf30325cabe3c1971bf0dba16cf1b027Bob Wilson .addFrameIndex(FI).addImm(16) 72869b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng .addReg(SrcReg, getKillRegState(isKill)) 72969b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng .addMemOperand(MMO)); 73031bc849123011b8eae6bb3c79876d9a3c26a6a1dJim Grosbach } else { 73173fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMQIA)) 73269b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng .addReg(SrcReg, getKillRegState(isKill)) 73369b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng .addFrameIndex(FI) 73469b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng .addMemOperand(MMO)); 73531bc849123011b8eae6bb3c79876d9a3c26a6a1dJim Grosbach } 736ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson break; 737ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson case ARM::QQPRRegClassID: 738ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson case ARM::QQPR_VFP2RegClassID: 739435d4991779d6a47cadff4ea670b490d8507d6c4Evan Cheng if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) { 74022c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng // FIXME: It's possible to only store part of the QQ register if the 74122c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng // spilled def has a sub-register index. 742168f382dc67e5940cabdb28dc933c4f91cdd3137Bob Wilson AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1d64QPseudo)) 743168f382dc67e5940cabdb28dc933c4f91cdd3137Bob Wilson .addFrameIndex(FI).addImm(16) 744168f382dc67e5940cabdb28dc933c4f91cdd3137Bob Wilson .addReg(SrcReg, getKillRegState(isKill)) 745168f382dc67e5940cabdb28dc933c4f91cdd3137Bob Wilson .addMemOperand(MMO)); 746435d4991779d6a47cadff4ea670b490d8507d6c4Evan Cheng } else { 747435d4991779d6a47cadff4ea670b490d8507d6c4Evan Cheng MachineInstrBuilder MIB = 74873fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMDIA)) 74973fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling .addFrameIndex(FI)) 750435d4991779d6a47cadff4ea670b490d8507d6c4Evan Cheng .addMemOperand(MMO); 751558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI); 752558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI); 753558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI); 754558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI); 755435d4991779d6a47cadff4ea670b490d8507d6c4Evan Cheng } 756ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson break; 757ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson case ARM::QQQQPRRegClassID: { 75822c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng MachineInstrBuilder MIB = 75973fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMDIA)) 76073fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling .addFrameIndex(FI)) 76122c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng .addMemOperand(MMO); 762558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI); 763558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI); 764558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI); 765558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen MIB = AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI); 766558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen MIB = AddDReg(MIB, SrcReg, ARM::dsub_4, 0, TRI); 767558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen MIB = AddDReg(MIB, SrcReg, ARM::dsub_5, 0, TRI); 768558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen MIB = AddDReg(MIB, SrcReg, ARM::dsub_6, 0, TRI); 769558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen AddDReg(MIB, SrcReg, ARM::dsub_7, 0, TRI); 770ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson break; 771ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson } 772ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson default: 773ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson llvm_unreachable("Unknown regclass!"); 774334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 775334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 776334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 77734327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesenunsigned 77834327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund OlesenARMBaseInstrInfo::isStoreToStackSlot(const MachineInstr *MI, 77934327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen int &FrameIndex) const { 78034327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen switch (MI->getOpcode()) { 78134327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen default: break; 7827e3383c007f53b3a00675af225e428cb66ddf404Jim Grosbach case ARM::STRrs: 78334327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen case ARM::t2STRs: // FIXME: don't use t2STRs to access frame. 78434327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen if (MI->getOperand(1).isFI() && 78534327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen MI->getOperand(2).isReg() && 78634327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen MI->getOperand(3).isImm() && 78734327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen MI->getOperand(2).getReg() == 0 && 78834327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen MI->getOperand(3).getImm() == 0) { 78934327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen FrameIndex = MI->getOperand(1).getIndex(); 79034327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen return MI->getOperand(0).getReg(); 79134327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen } 79234327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen break; 7937e3383c007f53b3a00675af225e428cb66ddf404Jim Grosbach case ARM::STRi12: 79434327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen case ARM::t2STRi12: 79534327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen case ARM::tSpill: 79634327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen case ARM::VSTRD: 79734327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen case ARM::VSTRS: 79834327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen if (MI->getOperand(1).isFI() && 79934327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen MI->getOperand(2).isImm() && 80034327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen MI->getOperand(2).getImm() == 0) { 80134327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen FrameIndex = MI->getOperand(1).getIndex(); 80234327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen return MI->getOperand(0).getReg(); 80334327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen } 80434327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen break; 805d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen case ARM::VST1q64Pseudo: 806d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen if (MI->getOperand(0).isFI() && 807d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen MI->getOperand(2).getSubReg() == 0) { 808d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen FrameIndex = MI->getOperand(0).getIndex(); 809d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen return MI->getOperand(2).getReg(); 810d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen } 81131bbc51ac9245bc82c933c9db8358ca9bb558ac5Jakob Stoklund Olesen break; 81273fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMQIA: 813d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen if (MI->getOperand(1).isFI() && 814d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen MI->getOperand(0).getSubReg() == 0) { 815d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen FrameIndex = MI->getOperand(1).getIndex(); 816d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen return MI->getOperand(0).getReg(); 817d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen } 818d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen break; 81934327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen } 82034327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen 82134327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen return 0; 82234327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen} 82334327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen 824334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinvoid ARMBaseInstrInfo:: 825334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinloadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 826334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned DestReg, int FI, 827746ad69e088176819981b4b2c5ac8dcd49f5e60eEvan Cheng const TargetRegisterClass *RC, 828746ad69e088176819981b4b2c5ac8dcd49f5e60eEvan Cheng const TargetRegisterInfo *TRI) const { 829c7f3ace20c325521c68335a1689645b43b06ddf0Chris Lattner DebugLoc DL; 830334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (I != MBB.end()) DL = I->getDebugLoc(); 831249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MachineFunction &MF = *MBB.getParent(); 832249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MachineFrameInfo &MFI = *MF.getFrameInfo(); 83331bc849123011b8eae6bb3c79876d9a3c26a6a1dJim Grosbach unsigned Align = MFI.getObjectAlignment(FI); 834249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MachineMemOperand *MMO = 83559db5496f4fc2ef6111569e542f8b65480ef14c1Chris Lattner MF.getMachineMemOperand( 83659db5496f4fc2ef6111569e542f8b65480ef14c1Chris Lattner MachinePointerInfo(PseudoSourceValue::getFixedStack(FI)), 83759db5496f4fc2ef6111569e542f8b65480ef14c1Chris Lattner MachineMemOperand::MOLoad, 838249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MFI.getObjectSize(FI), 83931bc849123011b8eae6bb3c79876d9a3c26a6a1dJim Grosbach Align); 840334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 8410eb0c7401c34c0b4604f732ce54db995eead14e6Bob Wilson // tGPR is used sometimes in ARM instructions that need to avoid using 8420eb0c7401c34c0b4604f732ce54db995eead14e6Bob Wilson // certain registers. Just treat it as GPR here. 8436ccfc507dc1f7ad8c8964193a2407264ca644f0dJim Grosbach if (RC == ARM::tGPRRegisterClass || RC == ARM::tcGPRRegisterClass 8446ccfc507dc1f7ad8c8964193a2407264ca644f0dJim Grosbach || RC == ARM::rGPRRegisterClass) 8450eb0c7401c34c0b4604f732ce54db995eead14e6Bob Wilson RC = ARM::GPRRegisterClass; 8460eb0c7401c34c0b4604f732ce54db995eead14e6Bob Wilson 847ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson switch (RC->getID()) { 848ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson case ARM::GPRRegClassID: 8493e5561247202bae994dd259a2d8dc4eff8f799f3Jim Grosbach AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::LDRi12), DestReg) 8503e5561247202bae994dd259a2d8dc4eff8f799f3Jim Grosbach .addFrameIndex(FI).addImm(0).addMemOperand(MMO)); 851ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson break; 852ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson case ARM::SPRRegClassID: 853d31c5496d7e1580058b5c6fbc8fd537a641ea590Evan Cheng AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRS), DestReg) 854d31c5496d7e1580058b5c6fbc8fd537a641ea590Evan Cheng .addFrameIndex(FI).addImm(0).addMemOperand(MMO)); 855ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson break; 856ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson case ARM::DPRRegClassID: 857ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson case ARM::DPR_VFP2RegClassID: 858ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson case ARM::DPR_8RegClassID: 859e5165490b7ba24bb2f3043399e0d60e7f3bcf8a5Jim Grosbach AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRD), DestReg) 860249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov .addFrameIndex(FI).addImm(0).addMemOperand(MMO)); 861ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson break; 862ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson case ARM::QPRRegClassID: 863ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson case ARM::QPR_VFP2RegClassID: 864ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson case ARM::QPR_8RegClassID: 8650cfcf93c95af91e809ef740eb0ab368477226b40Jim Grosbach if (Align >= 16 && getRegisterInfo().needsStackRealignment(MF)) { 866168f382dc67e5940cabdb28dc933c4f91cdd3137Bob Wilson AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1q64Pseudo), DestReg) 867f967ca0eaf30325cabe3c1971bf0dba16cf1b027Bob Wilson .addFrameIndex(FI).addImm(16) 86869b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng .addMemOperand(MMO)); 86931bc849123011b8eae6bb3c79876d9a3c26a6a1dJim Grosbach } else { 87073fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMQIA), DestReg) 87169b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng .addFrameIndex(FI) 87269b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng .addMemOperand(MMO)); 87331bc849123011b8eae6bb3c79876d9a3c26a6a1dJim Grosbach } 874ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson break; 875ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson case ARM::QQPRRegClassID: 876ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson case ARM::QQPR_VFP2RegClassID: 877435d4991779d6a47cadff4ea670b490d8507d6c4Evan Cheng if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) { 878168f382dc67e5940cabdb28dc933c4f91cdd3137Bob Wilson AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1d64QPseudo), DestReg) 879168f382dc67e5940cabdb28dc933c4f91cdd3137Bob Wilson .addFrameIndex(FI).addImm(16) 880168f382dc67e5940cabdb28dc933c4f91cdd3137Bob Wilson .addMemOperand(MMO)); 881435d4991779d6a47cadff4ea670b490d8507d6c4Evan Cheng } else { 882435d4991779d6a47cadff4ea670b490d8507d6c4Evan Cheng MachineInstrBuilder MIB = 88373fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMDIA)) 88473fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling .addFrameIndex(FI)) 885435d4991779d6a47cadff4ea670b490d8507d6c4Evan Cheng .addMemOperand(MMO); 886558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::Define, TRI); 887558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::Define, TRI); 888558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::Define, TRI); 889558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen AddDReg(MIB, DestReg, ARM::dsub_3, RegState::Define, TRI); 890435d4991779d6a47cadff4ea670b490d8507d6c4Evan Cheng } 891ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson break; 892ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson case ARM::QQQQPRRegClassID: { 893ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson MachineInstrBuilder MIB = 89473fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMDIA)) 89573fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling .addFrameIndex(FI)) 896ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson .addMemOperand(MMO); 897ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::Define, TRI); 898ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::Define, TRI); 899ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::Define, TRI); 900ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::Define, TRI); 901ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson MIB = AddDReg(MIB, DestReg, ARM::dsub_4, RegState::Define, TRI); 902ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson MIB = AddDReg(MIB, DestReg, ARM::dsub_5, RegState::Define, TRI); 903ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson MIB = AddDReg(MIB, DestReg, ARM::dsub_6, RegState::Define, TRI); 904ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson AddDReg(MIB, DestReg, ARM::dsub_7, RegState::Define, TRI); 905ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson break; 906ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson } 907ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson default: 908ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson llvm_unreachable("Unknown regclass!"); 909334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 910334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 911334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 91234327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesenunsigned 91334327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund OlesenARMBaseInstrInfo::isLoadFromStackSlot(const MachineInstr *MI, 91434327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen int &FrameIndex) const { 91534327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen switch (MI->getOpcode()) { 91634327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen default: break; 9173e5561247202bae994dd259a2d8dc4eff8f799f3Jim Grosbach case ARM::LDRrs: 91834327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen case ARM::t2LDRs: // FIXME: don't use t2LDRs to access frame. 91934327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen if (MI->getOperand(1).isFI() && 92034327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen MI->getOperand(2).isReg() && 92134327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen MI->getOperand(3).isImm() && 92234327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen MI->getOperand(2).getReg() == 0 && 92334327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen MI->getOperand(3).getImm() == 0) { 92434327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen FrameIndex = MI->getOperand(1).getIndex(); 92534327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen return MI->getOperand(0).getReg(); 92634327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen } 92734327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen break; 9283e5561247202bae994dd259a2d8dc4eff8f799f3Jim Grosbach case ARM::LDRi12: 92934327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen case ARM::t2LDRi12: 93034327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen case ARM::tRestore: 93134327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen case ARM::VLDRD: 93234327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen case ARM::VLDRS: 93334327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen if (MI->getOperand(1).isFI() && 93434327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen MI->getOperand(2).isImm() && 93534327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen MI->getOperand(2).getImm() == 0) { 93634327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen FrameIndex = MI->getOperand(1).getIndex(); 937d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen return MI->getOperand(0).getReg(); 938d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen } 939d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen break; 940d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen case ARM::VLD1q64Pseudo: 941d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen if (MI->getOperand(1).isFI() && 942d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen MI->getOperand(0).getSubReg() == 0) { 943d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen FrameIndex = MI->getOperand(1).getIndex(); 94406f264e504d75f0426eea55b9f9e36c780d8a4fcJakob Stoklund Olesen return MI->getOperand(0).getReg(); 94506f264e504d75f0426eea55b9f9e36c780d8a4fcJakob Stoklund Olesen } 94606f264e504d75f0426eea55b9f9e36c780d8a4fcJakob Stoklund Olesen break; 94773fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMQIA: 94806f264e504d75f0426eea55b9f9e36c780d8a4fcJakob Stoklund Olesen if (MI->getOperand(1).isFI() && 94906f264e504d75f0426eea55b9f9e36c780d8a4fcJakob Stoklund Olesen MI->getOperand(0).getSubReg() == 0) { 95006f264e504d75f0426eea55b9f9e36c780d8a4fcJakob Stoklund Olesen FrameIndex = MI->getOperand(1).getIndex(); 95134327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen return MI->getOperand(0).getReg(); 95234327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen } 95334327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen break; 95434327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen } 95534327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen 95634327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen return 0; 95734327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen} 95834327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen 95962b50656ceb854eb0be265d63b2a1d46e7400d8aEvan ChengMachineInstr* 96062b50656ceb854eb0be265d63b2a1d46e7400d8aEvan ChengARMBaseInstrInfo::emitFrameIndexDebugValue(MachineFunction &MF, 9618601a3d4decff0a380e059b037dabf71075497d3Evan Cheng int FrameIx, uint64_t Offset, 96262b50656ceb854eb0be265d63b2a1d46e7400d8aEvan Cheng const MDNode *MDPtr, 96362b50656ceb854eb0be265d63b2a1d46e7400d8aEvan Cheng DebugLoc DL) const { 96462b50656ceb854eb0be265d63b2a1d46e7400d8aEvan Cheng MachineInstrBuilder MIB = BuildMI(MF, DL, get(ARM::DBG_VALUE)) 96562b50656ceb854eb0be265d63b2a1d46e7400d8aEvan Cheng .addFrameIndex(FrameIx).addImm(0).addImm(Offset).addMetadata(MDPtr); 96662b50656ceb854eb0be265d63b2a1d46e7400d8aEvan Cheng return &*MIB; 96762b50656ceb854eb0be265d63b2a1d46e7400d8aEvan Cheng} 96862b50656ceb854eb0be265d63b2a1d46e7400d8aEvan Cheng 96930ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen/// Create a copy of a const pool value. Update CPI to the new index and return 97030ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen/// the label UID. 97130ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesenstatic unsigned duplicateCPV(MachineFunction &MF, unsigned &CPI) { 97230ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen MachineConstantPool *MCP = MF.getConstantPool(); 97330ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 97430ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen 97530ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPI]; 97630ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen assert(MCPE.isMachineConstantPoolEntry() && 97730ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen "Expecting a machine constantpool entry!"); 97830ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen ARMConstantPoolValue *ACPV = 97930ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal); 98030ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen 98130ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen unsigned PCLabelId = AFI->createConstPoolEntryUId(); 98230ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen ARMConstantPoolValue *NewCPV = 0; 98351f5b67395780b8421f4aa6ee998ed51b23dae9dJim Grosbach // FIXME: The below assumes PIC relocation model and that the function 98451f5b67395780b8421f4aa6ee998ed51b23dae9dJim Grosbach // is Thumb mode (t1 or t2). PCAdjustment would be 8 for ARM mode PIC, and 98551f5b67395780b8421f4aa6ee998ed51b23dae9dJim Grosbach // zero for non-PIC in ARM or Thumb. The callers are all of thumb LDR 98651f5b67395780b8421f4aa6ee998ed51b23dae9dJim Grosbach // instructions, so that's probably OK, but is PIC always correct when 98751f5b67395780b8421f4aa6ee998ed51b23dae9dJim Grosbach // we get here? 98830ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen if (ACPV->isGlobalValue()) 98930ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen NewCPV = new ARMConstantPoolValue(ACPV->getGV(), PCLabelId, 99030ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen ARMCP::CPValue, 4); 99130ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen else if (ACPV->isExtSymbol()) 99230ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen NewCPV = new ARMConstantPoolValue(MF.getFunction()->getContext(), 99330ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen ACPV->getSymbol(), PCLabelId, 4); 99430ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen else if (ACPV->isBlockAddress()) 99530ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen NewCPV = new ARMConstantPoolValue(ACPV->getBlockAddress(), PCLabelId, 99630ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen ARMCP::CPBlockAddress, 4); 99751f5b67395780b8421f4aa6ee998ed51b23dae9dJim Grosbach else if (ACPV->isLSDA()) 99851f5b67395780b8421f4aa6ee998ed51b23dae9dJim Grosbach NewCPV = new ARMConstantPoolValue(MF.getFunction(), PCLabelId, 99951f5b67395780b8421f4aa6ee998ed51b23dae9dJim Grosbach ARMCP::CPLSDA, 4); 100030ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen else 100130ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen llvm_unreachable("Unexpected ARM constantpool value type!!"); 100230ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen CPI = MCP->getConstantPoolIndex(NewCPV, MCPE.getAlignment()); 100330ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen return PCLabelId; 100430ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen} 100530ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen 1006fdc834046efd427d474e3b899ec69354c05071e0Evan Chengvoid ARMBaseInstrInfo:: 1007fdc834046efd427d474e3b899ec69354c05071e0Evan ChengreMaterialize(MachineBasicBlock &MBB, 1008fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng MachineBasicBlock::iterator I, 1009fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng unsigned DestReg, unsigned SubIdx, 1010d57cdd5683ea926e489067364fb7ffe5fd5d35eeEvan Cheng const MachineInstr *Orig, 10119edf7deb37f0f97664f279040fa15d89f32e23d9Jakob Stoklund Olesen const TargetRegisterInfo &TRI) const { 1012fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng unsigned Opcode = Orig->getOpcode(); 1013fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng switch (Opcode) { 1014fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng default: { 1015fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig); 10169edf7deb37f0f97664f279040fa15d89f32e23d9Jakob Stoklund Olesen MI->substituteRegister(Orig->getOperand(0).getReg(), DestReg, SubIdx, TRI); 1017fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng MBB.insert(I, MI); 1018fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng break; 1019fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng } 1020fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng case ARM::tLDRpci_pic: 1021fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng case ARM::t2LDRpci_pic: { 1022fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng MachineFunction &MF = *MBB.getParent(); 1023fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng unsigned CPI = Orig->getOperand(1).getIndex(); 102430ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen unsigned PCLabelId = duplicateCPV(MF, CPI); 1025fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng MachineInstrBuilder MIB = BuildMI(MBB, I, Orig->getDebugLoc(), get(Opcode), 1026fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng DestReg) 1027fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng .addConstantPoolIndex(CPI).addImm(PCLabelId); 1028fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng (*MIB).setMemRefs(Orig->memoperands_begin(), Orig->memoperands_end()); 1029fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng break; 1030fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng } 1031fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng } 1032fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng} 1033fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng 103430ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund OlesenMachineInstr * 103530ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund OlesenARMBaseInstrInfo::duplicate(MachineInstr *Orig, MachineFunction &MF) const { 103630ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen MachineInstr *MI = TargetInstrInfoImpl::duplicate(Orig, MF); 103730ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen switch(Orig->getOpcode()) { 103830ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen case ARM::tLDRpci_pic: 103930ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen case ARM::t2LDRpci_pic: { 104030ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen unsigned CPI = Orig->getOperand(1).getIndex(); 104130ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen unsigned PCLabelId = duplicateCPV(MF, CPI); 104230ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen Orig->getOperand(1).setIndex(CPI); 104330ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen Orig->getOperand(2).setImm(PCLabelId); 104430ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen break; 104530ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen } 104630ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen } 104730ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen return MI; 104830ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen} 104930ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen 1050506049f29f4f202a8e45feb916cc0264440a7f6dEvan Chengbool ARMBaseInstrInfo::produceSameValue(const MachineInstr *MI0, 1051506049f29f4f202a8e45feb916cc0264440a7f6dEvan Cheng const MachineInstr *MI1) const { 1052d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng int Opcode = MI0->getOpcode(); 10539b82425cb0105fd5704f6b9bcd5e7693b05b1759Evan Cheng if (Opcode == ARM::t2LDRpci || 10549b82425cb0105fd5704f6b9bcd5e7693b05b1759Evan Cheng Opcode == ARM::t2LDRpci_pic || 10559b82425cb0105fd5704f6b9bcd5e7693b05b1759Evan Cheng Opcode == ARM::tLDRpci || 10569b82425cb0105fd5704f6b9bcd5e7693b05b1759Evan Cheng Opcode == ARM::tLDRpci_pic) { 1057d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng if (MI1->getOpcode() != Opcode) 1058d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng return false; 1059d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng if (MI0->getNumOperands() != MI1->getNumOperands()) 1060d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng return false; 1061d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng 1062d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng const MachineOperand &MO0 = MI0->getOperand(1); 1063d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng const MachineOperand &MO1 = MI1->getOperand(1); 1064d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng if (MO0.getOffset() != MO1.getOffset()) 1065d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng return false; 1066d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng 1067d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng const MachineFunction *MF = MI0->getParent()->getParent(); 1068d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng const MachineConstantPool *MCP = MF->getConstantPool(); 1069d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng int CPI0 = MO0.getIndex(); 1070d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng int CPI1 = MO1.getIndex(); 1071d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng const MachineConstantPoolEntry &MCPE0 = MCP->getConstants()[CPI0]; 1072d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng const MachineConstantPoolEntry &MCPE1 = MCP->getConstants()[CPI1]; 1073d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng ARMConstantPoolValue *ACPV0 = 1074d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng static_cast<ARMConstantPoolValue*>(MCPE0.Val.MachineCPVal); 1075d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng ARMConstantPoolValue *ACPV1 = 1076d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng static_cast<ARMConstantPoolValue*>(MCPE1.Val.MachineCPVal); 1077d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng return ACPV0->hasSameValue(ACPV1); 1078d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng } 1079d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng 1080506049f29f4f202a8e45feb916cc0264440a7f6dEvan Cheng return MI0->isIdenticalTo(MI1, MachineInstr::IgnoreVRegDefs); 1081d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng} 1082d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng 10834b722108e2cf8e77157e0879a23789cd44829933Bill Wendling/// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to 10844b722108e2cf8e77157e0879a23789cd44829933Bill Wendling/// determine if two loads are loading from the same base address. It should 10854b722108e2cf8e77157e0879a23789cd44829933Bill Wendling/// only return true if the base pointers are the same and the only differences 10864b722108e2cf8e77157e0879a23789cd44829933Bill Wendling/// between the two addresses is the offset. It also returns the offsets by 10874b722108e2cf8e77157e0879a23789cd44829933Bill Wendling/// reference. 10884b722108e2cf8e77157e0879a23789cd44829933Bill Wendlingbool ARMBaseInstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, 10894b722108e2cf8e77157e0879a23789cd44829933Bill Wendling int64_t &Offset1, 10904b722108e2cf8e77157e0879a23789cd44829933Bill Wendling int64_t &Offset2) const { 10914b722108e2cf8e77157e0879a23789cd44829933Bill Wendling // Don't worry about Thumb: just ARM and Thumb2. 10924b722108e2cf8e77157e0879a23789cd44829933Bill Wendling if (Subtarget.isThumb1Only()) return false; 10934b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 10944b722108e2cf8e77157e0879a23789cd44829933Bill Wendling if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode()) 10954b722108e2cf8e77157e0879a23789cd44829933Bill Wendling return false; 10964b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 10974b722108e2cf8e77157e0879a23789cd44829933Bill Wendling switch (Load1->getMachineOpcode()) { 10984b722108e2cf8e77157e0879a23789cd44829933Bill Wendling default: 10994b722108e2cf8e77157e0879a23789cd44829933Bill Wendling return false; 11003e5561247202bae994dd259a2d8dc4eff8f799f3Jim Grosbach case ARM::LDRi12: 1101c1d30212e911d1e55ff6b25bffefb503708883c3Jim Grosbach case ARM::LDRBi12: 11024b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::LDRD: 11034b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::LDRH: 11044b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::LDRSB: 11054b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::LDRSH: 11064b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::VLDRD: 11074b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::VLDRS: 11084b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::t2LDRi8: 11094b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::t2LDRDi8: 11104b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::t2LDRSHi8: 11114b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::t2LDRi12: 11124b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::t2LDRSHi12: 11134b722108e2cf8e77157e0879a23789cd44829933Bill Wendling break; 11144b722108e2cf8e77157e0879a23789cd44829933Bill Wendling } 11154b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 11164b722108e2cf8e77157e0879a23789cd44829933Bill Wendling switch (Load2->getMachineOpcode()) { 11174b722108e2cf8e77157e0879a23789cd44829933Bill Wendling default: 11184b722108e2cf8e77157e0879a23789cd44829933Bill Wendling return false; 11193e5561247202bae994dd259a2d8dc4eff8f799f3Jim Grosbach case ARM::LDRi12: 1120c1d30212e911d1e55ff6b25bffefb503708883c3Jim Grosbach case ARM::LDRBi12: 11214b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::LDRD: 11224b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::LDRH: 11234b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::LDRSB: 11244b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::LDRSH: 11254b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::VLDRD: 11264b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::VLDRS: 11274b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::t2LDRi8: 11284b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::t2LDRDi8: 11294b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::t2LDRSHi8: 11304b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::t2LDRi12: 11314b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::t2LDRSHi12: 11324b722108e2cf8e77157e0879a23789cd44829933Bill Wendling break; 11334b722108e2cf8e77157e0879a23789cd44829933Bill Wendling } 11344b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 11354b722108e2cf8e77157e0879a23789cd44829933Bill Wendling // Check if base addresses and chain operands match. 11364b722108e2cf8e77157e0879a23789cd44829933Bill Wendling if (Load1->getOperand(0) != Load2->getOperand(0) || 11374b722108e2cf8e77157e0879a23789cd44829933Bill Wendling Load1->getOperand(4) != Load2->getOperand(4)) 11384b722108e2cf8e77157e0879a23789cd44829933Bill Wendling return false; 11394b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 11404b722108e2cf8e77157e0879a23789cd44829933Bill Wendling // Index should be Reg0. 11414b722108e2cf8e77157e0879a23789cd44829933Bill Wendling if (Load1->getOperand(3) != Load2->getOperand(3)) 11424b722108e2cf8e77157e0879a23789cd44829933Bill Wendling return false; 11434b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 11444b722108e2cf8e77157e0879a23789cd44829933Bill Wendling // Determine the offsets. 11454b722108e2cf8e77157e0879a23789cd44829933Bill Wendling if (isa<ConstantSDNode>(Load1->getOperand(1)) && 11464b722108e2cf8e77157e0879a23789cd44829933Bill Wendling isa<ConstantSDNode>(Load2->getOperand(1))) { 11474b722108e2cf8e77157e0879a23789cd44829933Bill Wendling Offset1 = cast<ConstantSDNode>(Load1->getOperand(1))->getSExtValue(); 11484b722108e2cf8e77157e0879a23789cd44829933Bill Wendling Offset2 = cast<ConstantSDNode>(Load2->getOperand(1))->getSExtValue(); 11494b722108e2cf8e77157e0879a23789cd44829933Bill Wendling return true; 11504b722108e2cf8e77157e0879a23789cd44829933Bill Wendling } 11514b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 11524b722108e2cf8e77157e0879a23789cd44829933Bill Wendling return false; 11534b722108e2cf8e77157e0879a23789cd44829933Bill Wendling} 11544b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 11554b722108e2cf8e77157e0879a23789cd44829933Bill Wendling/// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to 11564b722108e2cf8e77157e0879a23789cd44829933Bill Wendling/// determine (in conjuction with areLoadsFromSameBasePtr) if two loads should 11574b722108e2cf8e77157e0879a23789cd44829933Bill Wendling/// be scheduled togther. On some targets if two loads are loading from 11584b722108e2cf8e77157e0879a23789cd44829933Bill Wendling/// addresses in the same cache line, it's better if they are scheduled 11594b722108e2cf8e77157e0879a23789cd44829933Bill Wendling/// together. This function takes two integers that represent the load offsets 11604b722108e2cf8e77157e0879a23789cd44829933Bill Wendling/// from the common base address. It returns true if it decides it's desirable 11614b722108e2cf8e77157e0879a23789cd44829933Bill Wendling/// to schedule the two loads together. "NumLoads" is the number of loads that 11624b722108e2cf8e77157e0879a23789cd44829933Bill Wendling/// have already been scheduled after Load1. 11634b722108e2cf8e77157e0879a23789cd44829933Bill Wendlingbool ARMBaseInstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, 11644b722108e2cf8e77157e0879a23789cd44829933Bill Wendling int64_t Offset1, int64_t Offset2, 11654b722108e2cf8e77157e0879a23789cd44829933Bill Wendling unsigned NumLoads) const { 11664b722108e2cf8e77157e0879a23789cd44829933Bill Wendling // Don't worry about Thumb: just ARM and Thumb2. 11674b722108e2cf8e77157e0879a23789cd44829933Bill Wendling if (Subtarget.isThumb1Only()) return false; 11684b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 11694b722108e2cf8e77157e0879a23789cd44829933Bill Wendling assert(Offset2 > Offset1); 11704b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 11714b722108e2cf8e77157e0879a23789cd44829933Bill Wendling if ((Offset2 - Offset1) / 8 > 64) 11724b722108e2cf8e77157e0879a23789cd44829933Bill Wendling return false; 11734b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 11744b722108e2cf8e77157e0879a23789cd44829933Bill Wendling if (Load1->getMachineOpcode() != Load2->getMachineOpcode()) 11754b722108e2cf8e77157e0879a23789cd44829933Bill Wendling return false; // FIXME: overly conservative? 11764b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 11774b722108e2cf8e77157e0879a23789cd44829933Bill Wendling // Four loads in a row should be sufficient. 11784b722108e2cf8e77157e0879a23789cd44829933Bill Wendling if (NumLoads >= 3) 11794b722108e2cf8e77157e0879a23789cd44829933Bill Wendling return false; 11804b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 11814b722108e2cf8e77157e0879a23789cd44829933Bill Wendling return true; 11824b722108e2cf8e77157e0879a23789cd44829933Bill Wendling} 11834b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 118486050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Chengbool ARMBaseInstrInfo::isSchedulingBoundary(const MachineInstr *MI, 118586050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng const MachineBasicBlock *MBB, 118686050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng const MachineFunction &MF) const { 118757bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach // Debug info is never a scheduling boundary. It's necessary to be explicit 118857bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach // due to the special treatment of IT instructions below, otherwise a 118957bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach // dbg_value followed by an IT will result in the IT instruction being 119057bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach // considered a scheduling hazard, which is wrong. It should be the actual 119157bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach // instruction preceding the dbg_value instruction(s), just like it is 119257bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach // when debug info is not present. 119357bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach if (MI->isDebugValue()) 119457bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach return false; 119557bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach 119686050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // Terminators and labels can't be scheduled around. 119786050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng if (MI->getDesc().isTerminator() || MI->isLabel()) 119886050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng return true; 119986050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng 120086050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // Treat the start of the IT block as a scheduling boundary, but schedule 120186050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // t2IT along with all instructions following it. 120286050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // FIXME: This is a big hammer. But the alternative is to add all potential 120386050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // true and anti dependencies to IT block instructions as implicit operands 120486050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // to the t2IT instruction. The added compile time and complexity does not 120586050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // seem worth it. 120686050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng MachineBasicBlock::const_iterator I = MI; 120757bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach // Make sure to skip any dbg_value instructions 120857bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach while (++I != MBB->end() && I->isDebugValue()) 120957bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach ; 121057bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach if (I != MBB->end() && I->getOpcode() == ARM::t2IT) 121186050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng return true; 121286050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng 121386050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // Don't attempt to schedule around any instruction that defines 121486050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // a stack-oriented pointer, as it's unlikely to be profitable. This 121586050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // saves compile time, because it doesn't require every single 121686050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // stack slot reference to depend on the instruction that does the 121786050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // modification. 121886050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng if (MI->definesRegister(ARM::SP)) 121986050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng return true; 122086050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng 122186050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng return false; 122286050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng} 122386050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng 1224b20b85168c0e9819e6545f08281e9b83c82108f0Owen Andersonbool ARMBaseInstrInfo::isProfitableToIfCvt(MachineBasicBlock &MBB, 12258239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng unsigned NumCyles, 12268239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng unsigned ExtraPredCycles, 1227e3cc84a43d6a4bb6c50f58f3dd8e60e28787509eOwen Anderson float Probability, 1228e3cc84a43d6a4bb6c50f58f3dd8e60e28787509eOwen Anderson float Confidence) const { 12298239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng if (!NumCyles) 123013151432edace19ee867a93b5c14573df4f75d24Evan Cheng return false; 12312bbb76909126db5bed6bde84b16d94ab5de4d372Michael J. Spencer 1232b20b85168c0e9819e6545f08281e9b83c82108f0Owen Anderson // Attempt to estimate the relative costs of predication versus branching. 12338239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng float UnpredCost = Probability * NumCyles; 1234654d5440a477b1f6c89b051107e041a331f78e27Owen Anderson UnpredCost += 1.0; // The branch itself 1235e3cc84a43d6a4bb6c50f58f3dd8e60e28787509eOwen Anderson UnpredCost += (1.0 - Confidence) * Subtarget.getMispredictionPenalty(); 12362bbb76909126db5bed6bde84b16d94ab5de4d372Michael J. Spencer 12378239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng return (float)(NumCyles + ExtraPredCycles) < UnpredCost; 123813151432edace19ee867a93b5c14573df4f75d24Evan Cheng} 12392bbb76909126db5bed6bde84b16d94ab5de4d372Michael J. Spencer 124013151432edace19ee867a93b5c14573df4f75d24Evan Chengbool ARMBaseInstrInfo:: 12418239daf7c83a65a189c352cce3191cdc3bbfe151Evan ChengisProfitableToIfCvt(MachineBasicBlock &TMBB, 12428239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng unsigned TCycles, unsigned TExtra, 12438239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng MachineBasicBlock &FMBB, 12448239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng unsigned FCycles, unsigned FExtra, 1245e3cc84a43d6a4bb6c50f58f3dd8e60e28787509eOwen Anderson float Probability, float Confidence) const { 12468239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng if (!TCycles || !FCycles) 1247b20b85168c0e9819e6545f08281e9b83c82108f0Owen Anderson return false; 12482bbb76909126db5bed6bde84b16d94ab5de4d372Michael J. Spencer 1249b20b85168c0e9819e6545f08281e9b83c82108f0Owen Anderson // Attempt to estimate the relative costs of predication versus branching. 12508239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng float UnpredCost = Probability * TCycles + (1.0 - Probability) * FCycles; 1251654d5440a477b1f6c89b051107e041a331f78e27Owen Anderson UnpredCost += 1.0; // The branch itself 1252e3cc84a43d6a4bb6c50f58f3dd8e60e28787509eOwen Anderson UnpredCost += (1.0 - Confidence) * Subtarget.getMispredictionPenalty(); 12532bbb76909126db5bed6bde84b16d94ab5de4d372Michael J. Spencer 12548239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng return (float)(TCycles + FCycles + TExtra + FExtra) < UnpredCost; 125513151432edace19ee867a93b5c14573df4f75d24Evan Cheng} 125613151432edace19ee867a93b5c14573df4f75d24Evan Cheng 12578fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng/// getInstrPredicate - If instruction is predicated, returns its predicate 12588fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng/// condition, otherwise returns AL. It also returns the condition code 12598fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng/// register by reference. 12605adb66a646e2ec32265263739f5b01c3f50c176aEvan ChengARMCC::CondCodes 12615adb66a646e2ec32265263739f5b01c3f50c176aEvan Chengllvm::getInstrPredicate(const MachineInstr *MI, unsigned &PredReg) { 12628fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng int PIdx = MI->findFirstPredOperandIdx(); 12638fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng if (PIdx == -1) { 12648fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng PredReg = 0; 12658fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng return ARMCC::AL; 12668fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng } 12678fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng 12688fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng PredReg = MI->getOperand(PIdx+1).getReg(); 12698fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng return (ARMCC::CondCodes)MI->getOperand(PIdx).getImm(); 12708fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng} 12718fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng 12728fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng 12736495f63945e8dbde81f03a1dc2ab421993b9a495Evan Chengint llvm::getMatchingCondBranchOpcode(int Opc) { 12745ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng if (Opc == ARM::B) 12755ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng return ARM::Bcc; 12765ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng else if (Opc == ARM::tB) 12775ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng return ARM::tBcc; 12785ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng else if (Opc == ARM::t2B) 12795ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng return ARM::t2Bcc; 12805ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng 12815ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng llvm_unreachable("Unknown unconditional branch opcode!"); 12825ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng return 0; 12835ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng} 12845ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng 12856495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 12866495f63945e8dbde81f03a1dc2ab421993b9a495Evan Chengvoid llvm::emitARMRegPlusImmediate(MachineBasicBlock &MBB, 12876495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MachineBasicBlock::iterator &MBBI, DebugLoc dl, 12886495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned DestReg, unsigned BaseReg, int NumBytes, 12896495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ARMCC::CondCodes Pred, unsigned PredReg, 12906495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng const ARMBaseInstrInfo &TII) { 12916495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng bool isSub = NumBytes < 0; 12926495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (isSub) NumBytes = -NumBytes; 12936495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 12946495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng while (NumBytes) { 12956495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned RotAmt = ARM_AM::getSOImmValRotate(NumBytes); 12966495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned ThisVal = NumBytes & ARM_AM::rotr32(0xFF, RotAmt); 12976495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng assert(ThisVal && "Didn't extract field correctly"); 12986495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 12996495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // We will handle these bits from offset, clear them. 13006495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng NumBytes &= ~ThisVal; 13016495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 13026495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng assert(ARM_AM::getSOImmVal(ThisVal) != -1 && "Bit extraction didn't work?"); 13036495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 13046495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Build the new ADD / SUB. 13056495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned Opc = isSub ? ARM::SUBri : ARM::ADDri; 13066495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg) 13076495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng .addReg(BaseReg, RegState::Kill).addImm(ThisVal) 13086495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng .addImm((unsigned)Pred).addReg(PredReg).addReg(0); 13096495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng BaseReg = DestReg; 13106495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 13116495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng} 13126495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 1313cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Chengbool llvm::rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx, 1314cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng unsigned FrameReg, int &Offset, 1315cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng const ARMBaseInstrInfo &TII) { 13166495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned Opcode = MI.getOpcode(); 13176495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng const TargetInstrDesc &Desc = MI.getDesc(); 13186495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask); 13196495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng bool isSub = false; 1320764ab52dd80310a205c9888bf166d09dab858f90Jim Grosbach 13216495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Memory operands in inline assembly always use AddrMode2. 13226495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (Opcode == ARM::INLINEASM) 13236495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng AddrMode = ARMII::AddrMode2; 1324764ab52dd80310a205c9888bf166d09dab858f90Jim Grosbach 13256495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (Opcode == ARM::ADDri) { 13266495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng Offset += MI.getOperand(FrameRegIdx+1).getImm(); 13276495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (Offset == 0) { 13286495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Turn it into a move. 13296495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MI.setDesc(TII.get(ARM::MOVr)); 13306495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false); 13316495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MI.RemoveOperand(FrameRegIdx+1); 1332cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng Offset = 0; 1333cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng return true; 13346495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } else if (Offset < 0) { 13356495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng Offset = -Offset; 13366495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng isSub = true; 13376495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MI.setDesc(TII.get(ARM::SUBri)); 13386495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 13396495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 13406495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Common case: small offset, fits into instruction. 13416495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (ARM_AM::getSOImmVal(Offset) != -1) { 13426495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Replace the FrameIndex with sp / fp 13436495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false); 13446495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset); 1345cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng Offset = 0; 1346cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng return true; 13476495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 13486495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 13496495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Otherwise, pull as much of the immedidate into this ADDri/SUBri 13506495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // as possible. 13516495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned RotAmt = ARM_AM::getSOImmValRotate(Offset); 13526495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xFF, RotAmt); 13536495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 13546495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // We will handle these bits from offset, clear them. 13556495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng Offset &= ~ThisImmVal; 13566495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 13576495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Get the properly encoded SOImmVal field. 13586495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng assert(ARM_AM::getSOImmVal(ThisImmVal) != -1 && 13596495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng "Bit extraction didn't work?"); 13606495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MI.getOperand(FrameRegIdx+1).ChangeToImmediate(ThisImmVal); 13616495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } else { 13626495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned ImmIdx = 0; 13636495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng int InstrOffs = 0; 13646495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned NumBits = 0; 13656495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned Scale = 1; 13666495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng switch (AddrMode) { 13673e5561247202bae994dd259a2d8dc4eff8f799f3Jim Grosbach case ARMII::AddrMode_i12: { 13683e5561247202bae994dd259a2d8dc4eff8f799f3Jim Grosbach ImmIdx = FrameRegIdx + 1; 13693e5561247202bae994dd259a2d8dc4eff8f799f3Jim Grosbach InstrOffs = MI.getOperand(ImmIdx).getImm(); 13703e5561247202bae994dd259a2d8dc4eff8f799f3Jim Grosbach NumBits = 12; 13713e5561247202bae994dd259a2d8dc4eff8f799f3Jim Grosbach break; 13723e5561247202bae994dd259a2d8dc4eff8f799f3Jim Grosbach } 13736495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng case ARMII::AddrMode2: { 13746495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ImmIdx = FrameRegIdx+2; 13756495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng InstrOffs = ARM_AM::getAM2Offset(MI.getOperand(ImmIdx).getImm()); 13766495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (ARM_AM::getAM2Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub) 13776495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng InstrOffs *= -1; 13786495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng NumBits = 12; 13796495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng break; 13806495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 13816495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng case ARMII::AddrMode3: { 13826495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ImmIdx = FrameRegIdx+2; 13836495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng InstrOffs = ARM_AM::getAM3Offset(MI.getOperand(ImmIdx).getImm()); 13846495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (ARM_AM::getAM3Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub) 13856495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng InstrOffs *= -1; 13866495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng NumBits = 8; 13876495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng break; 13886495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 1389baf31088f1472f48ea5ae81f0b93636cc44ca444Anton Korobeynikov case ARMII::AddrMode4: 1390a44321776ecd96fa0344335d3027758be3386e45Jim Grosbach case ARMII::AddrMode6: 1391cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng // Can't fold any offset even if it's zero. 1392cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng return false; 13936495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng case ARMII::AddrMode5: { 13946495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ImmIdx = FrameRegIdx+1; 13956495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng InstrOffs = ARM_AM::getAM5Offset(MI.getOperand(ImmIdx).getImm()); 13966495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (ARM_AM::getAM5Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub) 13976495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng InstrOffs *= -1; 13986495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng NumBits = 8; 13996495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng Scale = 4; 14006495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng break; 14016495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 14026495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng default: 14036495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng llvm_unreachable("Unsupported addressing mode!"); 14046495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng break; 14056495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 14066495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 14076495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng Offset += InstrOffs * Scale; 14086495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!"); 14096495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (Offset < 0) { 14106495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng Offset = -Offset; 14116495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng isSub = true; 14126495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 14136495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 14146495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Attempt to fold address comp. if opcode has offset bits 14156495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (NumBits > 0) { 14166495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Common case: small offset, fits into instruction. 14176495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MachineOperand &ImmOp = MI.getOperand(ImmIdx); 14186495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng int ImmedOffset = Offset / Scale; 14196495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned Mask = (1 << NumBits) - 1; 14206495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if ((unsigned)Offset <= Mask * Scale) { 14216495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Replace the FrameIndex with sp 14226495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false); 142377aee8e22c36257716c2df2f275724765704f20cJim Grosbach // FIXME: When addrmode2 goes away, this will simplify (like the 142477aee8e22c36257716c2df2f275724765704f20cJim Grosbach // T2 version), as the LDR.i12 versions don't need the encoding 142577aee8e22c36257716c2df2f275724765704f20cJim Grosbach // tricks for the offset value. 142677aee8e22c36257716c2df2f275724765704f20cJim Grosbach if (isSub) { 142777aee8e22c36257716c2df2f275724765704f20cJim Grosbach if (AddrMode == ARMII::AddrMode_i12) 142877aee8e22c36257716c2df2f275724765704f20cJim Grosbach ImmedOffset = -ImmedOffset; 142977aee8e22c36257716c2df2f275724765704f20cJim Grosbach else 143077aee8e22c36257716c2df2f275724765704f20cJim Grosbach ImmedOffset |= 1 << NumBits; 143177aee8e22c36257716c2df2f275724765704f20cJim Grosbach } 14326495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ImmOp.ChangeToImmediate(ImmedOffset); 1433cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng Offset = 0; 1434cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng return true; 14356495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 1436764ab52dd80310a205c9888bf166d09dab858f90Jim Grosbach 14376495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Otherwise, it didn't fit. Pull in what we can to simplify the immed. 14386495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ImmedOffset = ImmedOffset & Mask; 1439063efbf569e46776093ddf50099c98fdbb362167Jim Grosbach if (isSub) { 1440063efbf569e46776093ddf50099c98fdbb362167Jim Grosbach if (AddrMode == ARMII::AddrMode_i12) 1441063efbf569e46776093ddf50099c98fdbb362167Jim Grosbach ImmedOffset = -ImmedOffset; 1442063efbf569e46776093ddf50099c98fdbb362167Jim Grosbach else 1443063efbf569e46776093ddf50099c98fdbb362167Jim Grosbach ImmedOffset |= 1 << NumBits; 1444063efbf569e46776093ddf50099c98fdbb362167Jim Grosbach } 14456495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ImmOp.ChangeToImmediate(ImmedOffset); 14466495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng Offset &= ~(Mask*Scale); 14476495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 14486495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 14496495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 1450cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng Offset = (isSub) ? -Offset : Offset; 1451cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng return Offset == 0; 14526495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng} 1453e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling 1454e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendlingbool ARMBaseInstrInfo:: 1455a99c3e9acd95f5fbfb611e3f807240cd74001142Eric ChristopherAnalyzeCompare(const MachineInstr *MI, unsigned &SrcReg, int &CmpMask, 1456a99c3e9acd95f5fbfb611e3f807240cd74001142Eric Christopher int &CmpValue) const { 1457e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling switch (MI->getOpcode()) { 1458e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling default: break; 145938ae997e63e3e1bb2c8679e01ea74cf8fd0be893Bill Wendling case ARM::CMPri: 1460e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling case ARM::t2CMPri: 1461e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling SrcReg = MI->getOperand(0).getReg(); 146204ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif CmpMask = ~0; 1463e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling CmpValue = MI->getOperand(1).getImm(); 1464e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling return true; 146504ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif case ARM::TSTri: 146604ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif case ARM::t2TSTri: 146704ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif SrcReg = MI->getOperand(0).getReg(); 146804ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif CmpMask = MI->getOperand(1).getImm(); 146904ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif CmpValue = 0; 147004ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif return true; 147104ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif } 147204ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif 147304ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif return false; 147404ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif} 147504ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif 147605642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif/// isSuitableForMask - Identify a suitable 'and' instruction that 147705642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif/// operates on the given source register and applies the same mask 147805642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif/// as a 'tst' instruction. Provide a limited look-through for copies. 147905642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif/// When successful, MI will hold the found instruction. 148005642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greifstatic bool isSuitableForMask(MachineInstr *&MI, unsigned SrcReg, 14818ff9bb189ce188452e6cae6ed65cb2745814126cGabor Greif int CmpMask, bool CommonUse) { 148205642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif switch (MI->getOpcode()) { 148304ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif case ARM::ANDri: 148404ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif case ARM::t2ANDri: 148505642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif if (CmpMask != MI->getOperand(2).getImm()) 14868ff9bb189ce188452e6cae6ed65cb2745814126cGabor Greif return false; 148705642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif if (SrcReg == MI->getOperand(CommonUse ? 1 : 0).getReg()) 148804ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif return true; 148904ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif break; 149005642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif case ARM::COPY: { 149105642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif // Walk down one instruction which is potentially an 'and'. 149205642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif const MachineInstr &Copy = *MI; 1493f000a7a212590bfd45e23c05bff5e1b683d25dd6Michael J. Spencer MachineBasicBlock::iterator AND( 1494f000a7a212590bfd45e23c05bff5e1b683d25dd6Michael J. Spencer llvm::next(MachineBasicBlock::iterator(MI))); 149505642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif if (AND == MI->getParent()->end()) return false; 149605642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif MI = AND; 149705642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif return isSuitableForMask(MI, Copy.getOperand(0).getReg(), 149805642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif CmpMask, true); 149905642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif } 1500e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling } 1501e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling 1502e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling return false; 1503e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling} 1504e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling 1505a65568676d0d9d53dd4aae8f1c58271bb4cfff10Bill Wendling/// OptimizeCompareInstr - Convert the instruction supplying the argument to the 1506eb96a2f6c03c0ec97c56a3493ac38024afacc774Evan Cheng/// comparison into one that sets the zero bit in the flags register. 1507e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendlingbool ARMBaseInstrInfo:: 150804ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor GreifOptimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, int CmpMask, 1509eb96a2f6c03c0ec97c56a3493ac38024afacc774Evan Cheng int CmpValue, const MachineRegisterInfo *MRI) const { 15103665661a5708c8adc2727be38b56d1d87ddeb661Bill Wendling if (CmpValue != 0) 151192ad57f066e9f256e4e3d72febf152e68caa80c7Bill Wendling return false; 151292ad57f066e9f256e4e3d72febf152e68caa80c7Bill Wendling 1513b41ee96d76ccf1eec2fd898def4cfd7c16868708Bill Wendling MachineRegisterInfo::def_iterator DI = MRI->def_begin(SrcReg); 1514b41ee96d76ccf1eec2fd898def4cfd7c16868708Bill Wendling if (llvm::next(DI) != MRI->def_end()) 151592ad57f066e9f256e4e3d72febf152e68caa80c7Bill Wendling // Only support one definition. 151692ad57f066e9f256e4e3d72febf152e68caa80c7Bill Wendling return false; 151792ad57f066e9f256e4e3d72febf152e68caa80c7Bill Wendling 151892ad57f066e9f256e4e3d72febf152e68caa80c7Bill Wendling MachineInstr *MI = &*DI; 151992ad57f066e9f256e4e3d72febf152e68caa80c7Bill Wendling 152004ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif // Masked compares sometimes use the same register as the corresponding 'and'. 152104ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif if (CmpMask != ~0) { 152205642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif if (!isSuitableForMask(MI, SrcReg, CmpMask, false)) { 152304ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif MI = 0; 1524b41ee96d76ccf1eec2fd898def4cfd7c16868708Bill Wendling for (MachineRegisterInfo::use_iterator UI = MRI->use_begin(SrcReg), 1525b41ee96d76ccf1eec2fd898def4cfd7c16868708Bill Wendling UE = MRI->use_end(); UI != UE; ++UI) { 152604ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif if (UI->getParent() != CmpInstr->getParent()) continue; 152705642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif MachineInstr *PotentialAND = &*UI; 15288ff9bb189ce188452e6cae6ed65cb2745814126cGabor Greif if (!isSuitableForMask(PotentialAND, SrcReg, CmpMask, true)) 152904ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif continue; 153005642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif MI = PotentialAND; 153104ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif break; 153204ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif } 153304ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif if (!MI) return false; 153404ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif } 153504ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif } 153604ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif 1537e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling // Conservatively refuse to convert an instruction which isn't in the same BB 1538e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling // as the comparison. 1539e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling if (MI->getParent() != CmpInstr->getParent()) 1540e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling return false; 1541e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling 1542e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling // Check that CPSR isn't set between the comparison instruction and the one we 1543e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling // want to change. 1544691e64a54ce899409abe7c131d15ed75e3c1fef5Evan Cheng MachineBasicBlock::const_iterator I = CmpInstr, E = MI, 1545691e64a54ce899409abe7c131d15ed75e3c1fef5Evan Cheng B = MI->getParent()->begin(); 15460aa38b9381a5be42abd4f5ca5baa8c2930d148d3Bill Wendling 15470aa38b9381a5be42abd4f5ca5baa8c2930d148d3Bill Wendling // Early exit if CmpInstr is at the beginning of the BB. 15480aa38b9381a5be42abd4f5ca5baa8c2930d148d3Bill Wendling if (I == B) return false; 15490aa38b9381a5be42abd4f5ca5baa8c2930d148d3Bill Wendling 1550e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling --I; 1551e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling for (; I != E; --I) { 1552e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling const MachineInstr &Instr = *I; 1553e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling 1554e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling for (unsigned IO = 0, EO = Instr.getNumOperands(); IO != EO; ++IO) { 1555e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling const MachineOperand &MO = Instr.getOperand(IO); 155640a5eb18b031fa1a5e9697e21e251e613d441cc5Bill Wendling if (!MO.isReg()) continue; 1557e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling 155840a5eb18b031fa1a5e9697e21e251e613d441cc5Bill Wendling // This instruction modifies or uses CPSR after the one we want to 155940a5eb18b031fa1a5e9697e21e251e613d441cc5Bill Wendling // change. We can't do this transformation. 1560e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling if (MO.getReg() == ARM::CPSR) 1561e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling return false; 1562e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling } 1563691e64a54ce899409abe7c131d15ed75e3c1fef5Evan Cheng 1564691e64a54ce899409abe7c131d15ed75e3c1fef5Evan Cheng if (I == B) 1565691e64a54ce899409abe7c131d15ed75e3c1fef5Evan Cheng // The 'and' is below the comparison instruction. 1566691e64a54ce899409abe7c131d15ed75e3c1fef5Evan Cheng return false; 1567e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling } 1568e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling 1569e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling // Set the "zero" bit in CPSR. 1570e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling switch (MI->getOpcode()) { 1571e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling default: break; 157238ae997e63e3e1bb2c8679e01ea74cf8fd0be893Bill Wendling case ARM::ADDri: 15733a951829fef6a2cfca87611e94cf48e0136f81d5Bob Wilson case ARM::ANDri: 15743a951829fef6a2cfca87611e94cf48e0136f81d5Bob Wilson case ARM::t2ANDri: 157538ae997e63e3e1bb2c8679e01ea74cf8fd0be893Bill Wendling case ARM::SUBri: 157638ae997e63e3e1bb2c8679e01ea74cf8fd0be893Bill Wendling case ARM::t2ADDri: 1577ad422718f9b3224234f52e84d28d8a57a4e89987Bill Wendling case ARM::t2SUBri: 15783642e64c114e636548888c72c21ae023ee0121a7Evan Cheng // Toggle the optional operand to CPSR. 15793642e64c114e636548888c72c21ae023ee0121a7Evan Cheng MI->getOperand(5).setReg(ARM::CPSR); 15803642e64c114e636548888c72c21ae023ee0121a7Evan Cheng MI->getOperand(5).setIsDef(true); 1581e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling CmpInstr->eraseFromParent(); 1582e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling return true; 1583e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling } 1584e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling 1585e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling return false; 1586e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling} 15875f54ce347368105260be2cec497b6a4199dc5789Evan Cheng 1588c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Chengbool ARMBaseInstrInfo::FoldImmediate(MachineInstr *UseMI, 1589c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng MachineInstr *DefMI, unsigned Reg, 1590c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng MachineRegisterInfo *MRI) const { 1591c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng // Fold large immediates into add, sub, or, xor. 1592c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng unsigned DefOpc = DefMI->getOpcode(); 1593c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng if (DefOpc != ARM::t2MOVi32imm && DefOpc != ARM::MOVi32imm) 1594c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng return false; 1595c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng if (!DefMI->getOperand(1).isImm()) 1596c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng // Could be t2MOVi32imm <ga:xx> 1597c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng return false; 1598c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng 1599c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng if (!MRI->hasOneNonDBGUse(Reg)) 1600c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng return false; 1601c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng 1602c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng unsigned UseOpc = UseMI->getOpcode(); 16035c71c7a13715ed6f5bfdd5497172ddec316b68b0Evan Cheng unsigned NewUseOpc = 0; 1604c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng uint32_t ImmVal = (uint32_t)DefMI->getOperand(1).getImm(); 16055c71c7a13715ed6f5bfdd5497172ddec316b68b0Evan Cheng uint32_t SOImmValV1 = 0, SOImmValV2 = 0; 1606c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng bool Commute = false; 1607c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng switch (UseOpc) { 1608c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng default: return false; 1609c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::SUBrr: 1610c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::ADDrr: 1611c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::ORRrr: 1612c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::EORrr: 1613c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::t2SUBrr: 1614c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::t2ADDrr: 1615c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::t2ORRrr: 1616c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::t2EORrr: { 1617c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng Commute = UseMI->getOperand(2).getReg() != Reg; 1618c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng switch (UseOpc) { 1619c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng default: break; 1620c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::SUBrr: { 1621c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng if (Commute) 1622c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng return false; 1623c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng ImmVal = -ImmVal; 1624c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng NewUseOpc = ARM::SUBri; 1625c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng // Fallthrough 1626c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng } 1627c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::ADDrr: 1628c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::ORRrr: 1629c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::EORrr: { 1630c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng if (!ARM_AM::isSOImmTwoPartVal(ImmVal)) 1631c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng return false; 1632c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng SOImmValV1 = (uint32_t)ARM_AM::getSOImmTwoPartFirst(ImmVal); 1633c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng SOImmValV2 = (uint32_t)ARM_AM::getSOImmTwoPartSecond(ImmVal); 1634c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng switch (UseOpc) { 1635c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng default: break; 1636c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::ADDrr: NewUseOpc = ARM::ADDri; break; 1637c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::ORRrr: NewUseOpc = ARM::ORRri; break; 1638c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::EORrr: NewUseOpc = ARM::EORri; break; 1639c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng } 1640c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng break; 1641c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng } 1642c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::t2SUBrr: { 1643c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng if (Commute) 1644c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng return false; 1645c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng ImmVal = -ImmVal; 1646c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng NewUseOpc = ARM::t2SUBri; 1647c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng // Fallthrough 1648c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng } 1649c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::t2ADDrr: 1650c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::t2ORRrr: 1651c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::t2EORrr: { 1652c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng if (!ARM_AM::isT2SOImmTwoPartVal(ImmVal)) 1653c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng return false; 1654c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng SOImmValV1 = (uint32_t)ARM_AM::getT2SOImmTwoPartFirst(ImmVal); 1655c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng SOImmValV2 = (uint32_t)ARM_AM::getT2SOImmTwoPartSecond(ImmVal); 1656c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng switch (UseOpc) { 1657c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng default: break; 1658c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::t2ADDrr: NewUseOpc = ARM::t2ADDri; break; 1659c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::t2ORRrr: NewUseOpc = ARM::t2ORRri; break; 1660c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::t2EORrr: NewUseOpc = ARM::t2EORri; break; 1661c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng } 1662c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng break; 1663c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng } 1664c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng } 1665c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng } 1666c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng } 1667c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng 1668c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng unsigned OpIdx = Commute ? 2 : 1; 1669c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng unsigned Reg1 = UseMI->getOperand(OpIdx).getReg(); 1670c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng bool isKill = UseMI->getOperand(OpIdx).isKill(); 1671c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng unsigned NewReg = MRI->createVirtualRegister(MRI->getRegClass(Reg)); 1672c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng AddDefaultCC(AddDefaultPred(BuildMI(*UseMI->getParent(), 1673c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng *UseMI, UseMI->getDebugLoc(), 1674c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng get(NewUseOpc), NewReg) 1675c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng .addReg(Reg1, getKillRegState(isKill)) 1676c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng .addImm(SOImmValV1))); 1677c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng UseMI->setDesc(get(NewUseOpc)); 1678c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng UseMI->getOperand(1).setReg(NewReg); 1679c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng UseMI->getOperand(1).setIsKill(); 1680c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng UseMI->getOperand(2).ChangeToImmediate(SOImmValV2); 1681c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng DefMI->eraseFromParent(); 1682c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng return true; 1683c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng} 1684c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng 16855f54ce347368105260be2cec497b6a4199dc5789Evan Chengunsigned 16868239daf7c83a65a189c352cce3191cdc3bbfe151Evan ChengARMBaseInstrInfo::getNumMicroOps(const InstrItineraryData *ItinData, 16878239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng const MachineInstr *MI) const { 16883ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng if (!ItinData || ItinData->isEmpty()) 16895f54ce347368105260be2cec497b6a4199dc5789Evan Cheng return 1; 16905f54ce347368105260be2cec497b6a4199dc5789Evan Cheng 16915f54ce347368105260be2cec497b6a4199dc5789Evan Cheng const TargetInstrDesc &Desc = MI->getDesc(); 16925f54ce347368105260be2cec497b6a4199dc5789Evan Cheng unsigned Class = Desc.getSchedClass(); 1693064312de8641043b084603aa9a6b409bc794eed2Bob Wilson unsigned UOps = ItinData->Itineraries[Class].NumMicroOps; 16945f54ce347368105260be2cec497b6a4199dc5789Evan Cheng if (UOps) 16955f54ce347368105260be2cec497b6a4199dc5789Evan Cheng return UOps; 16965f54ce347368105260be2cec497b6a4199dc5789Evan Cheng 16975f54ce347368105260be2cec497b6a4199dc5789Evan Cheng unsigned Opc = MI->getOpcode(); 16985f54ce347368105260be2cec497b6a4199dc5789Evan Cheng switch (Opc) { 16995f54ce347368105260be2cec497b6a4199dc5789Evan Cheng default: 17005f54ce347368105260be2cec497b6a4199dc5789Evan Cheng llvm_unreachable("Unexpected multi-uops instruction!"); 17015f54ce347368105260be2cec497b6a4199dc5789Evan Cheng break; 170273fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMQIA: 170373fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMQDB: 170473fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMQIA: 170573fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMQDB: 17065f54ce347368105260be2cec497b6a4199dc5789Evan Cheng return 2; 17075f54ce347368105260be2cec497b6a4199dc5789Evan Cheng 17085f54ce347368105260be2cec497b6a4199dc5789Evan Cheng // The number of uOps for load / store multiple are determined by the number 17095f54ce347368105260be2cec497b6a4199dc5789Evan Cheng // registers. 17106e8f4c404825b79f9b9176483653f1aa927dfbdeAndrew Trick // 17113ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng // On Cortex-A8, each pair of register loads / stores can be scheduled on the 17123ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng // same cycle. The scheduling for the first load / store must be done 17133ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng // separately by assuming the the address is not 64-bit aligned. 171473fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling // 17153ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng // On Cortex-A9, the formula is simply (#reg / 2) + (#reg % 2). If the address 171673fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling // is not 64-bit aligned, then AGU would take an extra cycle. For VFP / NEON 171773fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling // load / store multiple, the formula is (#reg / 2) + (#reg % 2) + 1. 171873fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMDIA: 171973fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMDDB: 172073fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMDIA_UPD: 172173fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMDDB_UPD: 172273fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMSIA: 172373fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMSDB: 172473fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMSIA_UPD: 172573fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMSDB_UPD: 172673fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMDIA: 172773fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMDDB: 172873fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMDIA_UPD: 172973fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMDDB_UPD: 173073fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMSIA: 173173fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMSDB: 173273fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMSIA_UPD: 173373fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMSDB_UPD: { 17345f54ce347368105260be2cec497b6a4199dc5789Evan Cheng unsigned NumRegs = MI->getNumOperands() - Desc.getNumOperands(); 17355f54ce347368105260be2cec497b6a4199dc5789Evan Cheng return (NumRegs / 2) + (NumRegs % 2) + 1; 17365f54ce347368105260be2cec497b6a4199dc5789Evan Cheng } 173773fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling 173873fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMIA_RET: 173973fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMIA: 174073fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMDA: 174173fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMDB: 174273fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMIB: 174373fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMIA_UPD: 174473fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMDA_UPD: 174573fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMDB_UPD: 174673fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMIB_UPD: 174773fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::STMIA: 174873fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::STMDA: 174973fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::STMDB: 175073fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::STMIB: 175173fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::STMIA_UPD: 175273fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::STMDA_UPD: 175373fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::STMDB_UPD: 175473fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::STMIB_UPD: 175573fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::tLDMIA: 175673fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::tLDMIA_UPD: 175773fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::tSTMIA: 175873fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::tSTMIA_UPD: 17595f54ce347368105260be2cec497b6a4199dc5789Evan Cheng case ARM::tPOP_RET: 17605f54ce347368105260be2cec497b6a4199dc5789Evan Cheng case ARM::tPOP: 17615f54ce347368105260be2cec497b6a4199dc5789Evan Cheng case ARM::tPUSH: 176273fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2LDMIA_RET: 176373fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2LDMIA: 176473fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2LDMDB: 176573fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2LDMIA_UPD: 176673fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2LDMDB_UPD: 176773fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2STMIA: 176873fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2STMDB: 176973fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2STMIA_UPD: 177073fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2STMDB_UPD: { 17713ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng unsigned NumRegs = MI->getNumOperands() - Desc.getNumOperands() + 1; 17723ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng if (Subtarget.isCortexA8()) { 17738239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng if (NumRegs < 4) 17748239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng return 2; 17758239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng // 4 registers would be issued: 2, 2. 17768239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng // 5 registers would be issued: 2, 2, 1. 17778239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng UOps = (NumRegs / 2); 17788239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng if (NumRegs % 2) 17798239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng ++UOps; 17808239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng return UOps; 17813ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng } else if (Subtarget.isCortexA9()) { 17823ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng UOps = (NumRegs / 2); 17833ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng // If there are odd number of registers or if it's not 64-bit aligned, 17843ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng // then it takes an extra AGU (Address Generation Unit) cycle. 17853ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng if ((NumRegs % 2) || 17863ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng !MI->hasOneMemOperand() || 17873ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng (*MI->memoperands_begin())->getAlignment() < 8) 17883ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng ++UOps; 17893ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng return UOps; 17903ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng } else { 17913ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng // Assume the worst. 17923ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng return NumRegs; 17932bbb76909126db5bed6bde84b16d94ab5de4d372Michael J. Spencer } 17945f54ce347368105260be2cec497b6a4199dc5789Evan Cheng } 17955f54ce347368105260be2cec497b6a4199dc5789Evan Cheng } 17965f54ce347368105260be2cec497b6a4199dc5789Evan Cheng} 1797a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng 1798a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Chengint 1799344d9db97062736cd66da6c07baa9108b6cfa419Evan ChengARMBaseInstrInfo::getVLDMDefCycle(const InstrItineraryData *ItinData, 1800344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng const TargetInstrDesc &DefTID, 1801344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng unsigned DefClass, 1802344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng unsigned DefIdx, unsigned DefAlign) const { 1803344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng int RegNo = (int)(DefIdx+1) - DefTID.getNumOperands() + 1; 1804344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng if (RegNo <= 0) 1805344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // Def is the address writeback. 1806344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng return ItinData->getOperandCycle(DefClass, DefIdx); 1807344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng 1808344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng int DefCycle; 1809344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng if (Subtarget.isCortexA8()) { 1810344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // (regno / 2) + (regno % 2) + 1 1811344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng DefCycle = RegNo / 2 + 1; 1812344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng if (RegNo % 2) 1813344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng ++DefCycle; 1814344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng } else if (Subtarget.isCortexA9()) { 1815344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng DefCycle = RegNo; 1816344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng bool isSLoad = false; 181773fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling 1818344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng switch (DefTID.getOpcode()) { 1819344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng default: break; 182073fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMSIA: 182173fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMSDB: 182273fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMSIA_UPD: 182373fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMSDB_UPD: 1824344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng isSLoad = true; 1825344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng break; 1826344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng } 182773fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling 1828344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // If there are odd number of 'S' registers or if it's not 64-bit aligned, 1829344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // then it takes an extra cycle. 1830344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng if ((isSLoad && (RegNo % 2)) || DefAlign < 8) 1831344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng ++DefCycle; 1832344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng } else { 1833344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // Assume the worst. 1834344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng DefCycle = RegNo + 2; 1835344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng } 1836344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng 1837344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng return DefCycle; 1838344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng} 1839344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng 1840344d9db97062736cd66da6c07baa9108b6cfa419Evan Chengint 1841344d9db97062736cd66da6c07baa9108b6cfa419Evan ChengARMBaseInstrInfo::getLDMDefCycle(const InstrItineraryData *ItinData, 1842344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng const TargetInstrDesc &DefTID, 1843344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng unsigned DefClass, 1844344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng unsigned DefIdx, unsigned DefAlign) const { 1845344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng int RegNo = (int)(DefIdx+1) - DefTID.getNumOperands() + 1; 1846344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng if (RegNo <= 0) 1847344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // Def is the address writeback. 1848344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng return ItinData->getOperandCycle(DefClass, DefIdx); 1849344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng 1850344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng int DefCycle; 1851344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng if (Subtarget.isCortexA8()) { 1852344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // 4 registers would be issued: 1, 2, 1. 1853344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // 5 registers would be issued: 1, 2, 2. 1854344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng DefCycle = RegNo / 2; 1855344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng if (DefCycle < 1) 1856344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng DefCycle = 1; 1857344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // Result latency is issue cycle + 2: E2. 1858344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng DefCycle += 2; 1859344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng } else if (Subtarget.isCortexA9()) { 1860344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng DefCycle = (RegNo / 2); 1861344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // If there are odd number of registers or if it's not 64-bit aligned, 1862344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // then it takes an extra AGU (Address Generation Unit) cycle. 1863344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng if ((RegNo % 2) || DefAlign < 8) 1864344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng ++DefCycle; 1865344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // Result latency is AGU cycles + 2. 1866344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng DefCycle += 2; 1867344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng } else { 1868344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // Assume the worst. 1869344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng DefCycle = RegNo + 2; 1870344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng } 1871344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng 1872344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng return DefCycle; 1873344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng} 1874344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng 1875344d9db97062736cd66da6c07baa9108b6cfa419Evan Chengint 1876344d9db97062736cd66da6c07baa9108b6cfa419Evan ChengARMBaseInstrInfo::getVSTMUseCycle(const InstrItineraryData *ItinData, 1877344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng const TargetInstrDesc &UseTID, 1878344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng unsigned UseClass, 1879344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng unsigned UseIdx, unsigned UseAlign) const { 1880344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng int RegNo = (int)(UseIdx+1) - UseTID.getNumOperands() + 1; 1881344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng if (RegNo <= 0) 1882344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng return ItinData->getOperandCycle(UseClass, UseIdx); 1883344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng 1884344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng int UseCycle; 1885344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng if (Subtarget.isCortexA8()) { 1886344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // (regno / 2) + (regno % 2) + 1 1887344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng UseCycle = RegNo / 2 + 1; 1888344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng if (RegNo % 2) 1889344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng ++UseCycle; 1890344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng } else if (Subtarget.isCortexA9()) { 1891344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng UseCycle = RegNo; 1892344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng bool isSStore = false; 189373fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling 1894344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng switch (UseTID.getOpcode()) { 1895344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng default: break; 189673fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMSIA: 189773fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMSDB: 189873fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMSIA_UPD: 189973fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMSDB_UPD: 1900344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng isSStore = true; 1901344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng break; 1902344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng } 190373fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling 1904344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // If there are odd number of 'S' registers or if it's not 64-bit aligned, 1905344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // then it takes an extra cycle. 1906344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng if ((isSStore && (RegNo % 2)) || UseAlign < 8) 1907344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng ++UseCycle; 1908344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng } else { 1909344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // Assume the worst. 1910344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng UseCycle = RegNo + 2; 1911344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng } 1912344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng 1913344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng return UseCycle; 1914344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng} 1915344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng 1916344d9db97062736cd66da6c07baa9108b6cfa419Evan Chengint 1917344d9db97062736cd66da6c07baa9108b6cfa419Evan ChengARMBaseInstrInfo::getSTMUseCycle(const InstrItineraryData *ItinData, 1918344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng const TargetInstrDesc &UseTID, 1919344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng unsigned UseClass, 1920344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng unsigned UseIdx, unsigned UseAlign) const { 1921344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng int RegNo = (int)(UseIdx+1) - UseTID.getNumOperands() + 1; 1922344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng if (RegNo <= 0) 1923344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng return ItinData->getOperandCycle(UseClass, UseIdx); 1924344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng 1925344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng int UseCycle; 1926344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng if (Subtarget.isCortexA8()) { 1927344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng UseCycle = RegNo / 2; 1928344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng if (UseCycle < 2) 1929344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng UseCycle = 2; 1930344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // Read in E3. 1931344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng UseCycle += 2; 1932344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng } else if (Subtarget.isCortexA9()) { 1933344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng UseCycle = (RegNo / 2); 1934344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // If there are odd number of registers or if it's not 64-bit aligned, 1935344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // then it takes an extra AGU (Address Generation Unit) cycle. 1936344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng if ((RegNo % 2) || UseAlign < 8) 1937344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng ++UseCycle; 1938344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng } else { 1939344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // Assume the worst. 1940344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng UseCycle = 1; 1941344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng } 1942344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng return UseCycle; 1943344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng} 1944344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng 1945344d9db97062736cd66da6c07baa9108b6cfa419Evan Chengint 1946a0792de66c8364d47b0a688c7f408efb7b10f31bEvan ChengARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData, 1947a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng const TargetInstrDesc &DefTID, 1948a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng unsigned DefIdx, unsigned DefAlign, 1949a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng const TargetInstrDesc &UseTID, 1950a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng unsigned UseIdx, unsigned UseAlign) const { 1951a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng unsigned DefClass = DefTID.getSchedClass(); 1952a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng unsigned UseClass = UseTID.getSchedClass(); 1953a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng 1954a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng if (DefIdx < DefTID.getNumDefs() && UseIdx < UseTID.getNumOperands()) 1955a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx); 1956a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng 1957a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng // This may be a def / use of a variable_ops instruction, the operand 1958a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng // latency might be determinable dynamically. Let the target try to 1959a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng // figure it out. 19609e08ee5d16b596078e20787f0b5f36121f099333Evan Cheng int DefCycle = -1; 19617e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng bool LdmBypass = false; 1962a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng switch (DefTID.getOpcode()) { 1963a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng default: 1964a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng DefCycle = ItinData->getOperandCycle(DefClass, DefIdx); 1965a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng break; 196673fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling 196773fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMDIA: 196873fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMDDB: 196973fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMDIA_UPD: 197073fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMDDB_UPD: 197173fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMSIA: 197273fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMSDB: 197373fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMSIA_UPD: 197473fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMSDB_UPD: 1975344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng DefCycle = getVLDMDefCycle(ItinData, DefTID, DefClass, DefIdx, DefAlign); 19765a50ceeaea980962c1982ad535226c7ab06c971cEvan Cheng break; 197773fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling 197873fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMIA_RET: 197973fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMIA: 198073fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMDA: 198173fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMDB: 198273fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMIB: 198373fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMIA_UPD: 198473fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMDA_UPD: 198573fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMDB_UPD: 198673fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMIB_UPD: 198773fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::tLDMIA: 198873fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::tLDMIA_UPD: 1989a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng case ARM::tPUSH: 199073fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2LDMIA_RET: 199173fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2LDMIA: 199273fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2LDMDB: 199373fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2LDMIA_UPD: 199473fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2LDMDB_UPD: 1995a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng LdmBypass = 1; 1996344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng DefCycle = getLDMDefCycle(ItinData, DefTID, DefClass, DefIdx, DefAlign); 1997344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng break; 1998a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng } 1999a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng 2000a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng if (DefCycle == -1) 2001a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng // We can't seem to determine the result latency of the def, assume it's 2. 2002a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng DefCycle = 2; 2003a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng 2004a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng int UseCycle = -1; 2005a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng switch (UseTID.getOpcode()) { 2006a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng default: 2007a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng UseCycle = ItinData->getOperandCycle(UseClass, UseIdx); 2008a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng break; 200973fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling 201073fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMDIA: 201173fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMDDB: 201273fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMDIA_UPD: 201373fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMDDB_UPD: 201473fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMSIA: 201573fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMSDB: 201673fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMSIA_UPD: 201773fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMSDB_UPD: 2018344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng UseCycle = getVSTMUseCycle(ItinData, UseTID, UseClass, UseIdx, UseAlign); 20195a50ceeaea980962c1982ad535226c7ab06c971cEvan Cheng break; 202073fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling 202173fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::STMIA: 202273fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::STMDA: 202373fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::STMDB: 202473fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::STMIB: 202573fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::STMIA_UPD: 202673fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::STMDA_UPD: 202773fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::STMDB_UPD: 202873fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::STMIB_UPD: 202973fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::tSTMIA: 203073fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::tSTMIA_UPD: 2031a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng case ARM::tPOP_RET: 2032a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng case ARM::tPOP: 203373fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2STMIA: 203473fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2STMDB: 203573fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2STMIA_UPD: 203673fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2STMDB_UPD: 2037344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng UseCycle = getSTMUseCycle(ItinData, UseTID, UseClass, UseIdx, UseAlign); 20385a50ceeaea980962c1982ad535226c7ab06c971cEvan Cheng break; 2039a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng } 2040a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng 2041a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng if (UseCycle == -1) 2042a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng // Assume it's read in the first stage. 2043a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng UseCycle = 1; 2044a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng 2045a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng UseCycle = DefCycle - UseCycle + 1; 2046a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng if (UseCycle > 0) { 2047a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng if (LdmBypass) { 2048a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng // It's a variable_ops instruction so we can't use DefIdx here. Just use 2049a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng // first def operand. 2050a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng if (ItinData->hasPipelineForwarding(DefClass, DefTID.getNumOperands()-1, 2051a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng UseClass, UseIdx)) 2052a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng --UseCycle; 2053a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng } else if (ItinData->hasPipelineForwarding(DefClass, DefIdx, 205473fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling UseClass, UseIdx)) { 2055a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng --UseCycle; 205673fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling } 2057a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng } 2058a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng 2059a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng return UseCycle; 2060a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng} 2061a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng 2062a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Chengint 2063a0792de66c8364d47b0a688c7f408efb7b10f31bEvan ChengARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData, 2064a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng const MachineInstr *DefMI, unsigned DefIdx, 2065a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng const MachineInstr *UseMI, unsigned UseIdx) const { 2066a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng if (DefMI->isCopyLike() || DefMI->isInsertSubreg() || 2067a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng DefMI->isRegSequence() || DefMI->isImplicitDef()) 2068a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng return 1; 2069a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng 2070a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng const TargetInstrDesc &DefTID = DefMI->getDesc(); 2071a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng if (!ItinData || ItinData->isEmpty()) 2072a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng return DefTID.mayLoad() ? 3 : 1; 2073a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng 2074dd9dd6f857604abdeb5213648ffe50c10ccc59b9Evan Cheng 2075a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng const TargetInstrDesc &UseTID = UseMI->getDesc(); 2076dd9dd6f857604abdeb5213648ffe50c10ccc59b9Evan Cheng const MachineOperand &DefMO = DefMI->getOperand(DefIdx); 2077e09206d4d7683e2a421104c5cb83f7808ba4b06eEvan Cheng if (DefMO.getReg() == ARM::CPSR) { 2078e09206d4d7683e2a421104c5cb83f7808ba4b06eEvan Cheng if (DefMI->getOpcode() == ARM::FMSTAT) { 2079e09206d4d7683e2a421104c5cb83f7808ba4b06eEvan Cheng // fpscr -> cpsr stalls over 20 cycles on A8 (and earlier?) 2080e09206d4d7683e2a421104c5cb83f7808ba4b06eEvan Cheng return Subtarget.isCortexA9() ? 1 : 20; 2081e09206d4d7683e2a421104c5cb83f7808ba4b06eEvan Cheng } 2082e09206d4d7683e2a421104c5cb83f7808ba4b06eEvan Cheng 2083dd9dd6f857604abdeb5213648ffe50c10ccc59b9Evan Cheng // CPSR set and branch can be paired in the same cycle. 2084e09206d4d7683e2a421104c5cb83f7808ba4b06eEvan Cheng if (UseTID.isBranch()) 2085e09206d4d7683e2a421104c5cb83f7808ba4b06eEvan Cheng return 0; 2086e09206d4d7683e2a421104c5cb83f7808ba4b06eEvan Cheng } 2087dd9dd6f857604abdeb5213648ffe50c10ccc59b9Evan Cheng 2088a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng unsigned DefAlign = DefMI->hasOneMemOperand() 2089a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng ? (*DefMI->memoperands_begin())->getAlignment() : 0; 2090a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng unsigned UseAlign = UseMI->hasOneMemOperand() 2091a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng ? (*UseMI->memoperands_begin())->getAlignment() : 0; 20927e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng int Latency = getOperandLatency(ItinData, DefTID, DefIdx, DefAlign, 20937e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng UseTID, UseIdx, UseAlign); 20947e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng 20957e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng if (Latency > 1 && 20967e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng (Subtarget.isCortexA8() || Subtarget.isCortexA9())) { 20977e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng // FIXME: Shifter op hack: no shift (i.e. [r +/- r]) or [r + r << 2] 20987e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng // variants are one cycle cheaper. 20997e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng switch (DefTID.getOpcode()) { 21007e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng default: break; 21017e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng case ARM::LDRrs: 21027e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng case ARM::LDRBrs: { 21037e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng unsigned ShOpVal = DefMI->getOperand(3).getImm(); 21047e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal); 21057e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng if (ShImm == 0 || 21067e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng (ShImm == 2 && ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl)) 21077e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng --Latency; 21087e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng break; 21097e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng } 21107e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng case ARM::t2LDRs: 21117e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng case ARM::t2LDRBs: 21127e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng case ARM::t2LDRHs: 21137e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng case ARM::t2LDRSHs: { 21147e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng // Thumb2 mode: lsl only. 21157e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng unsigned ShAmt = DefMI->getOperand(3).getImm(); 21167e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng if (ShAmt == 0 || ShAmt == 2) 21177e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng --Latency; 21187e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng break; 21197e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng } 21207e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng } 21217e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng } 21227e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng 21237e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng return Latency; 2124a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng} 2125a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng 2126a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Chengint 2127a0792de66c8364d47b0a688c7f408efb7b10f31bEvan ChengARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData, 2128a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng SDNode *DefNode, unsigned DefIdx, 2129a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng SDNode *UseNode, unsigned UseIdx) const { 2130a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng if (!DefNode->isMachineOpcode()) 2131a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng return 1; 2132a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng 2133a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng const TargetInstrDesc &DefTID = get(DefNode->getMachineOpcode()); 2134a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng if (!ItinData || ItinData->isEmpty()) 2135a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng return DefTID.mayLoad() ? 3 : 1; 2136a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng 2137089751535d6e9adf65842e2ca5867bf9a70e1e95Evan Cheng if (!UseNode->isMachineOpcode()) { 2138089751535d6e9adf65842e2ca5867bf9a70e1e95Evan Cheng int Latency = ItinData->getOperandCycle(DefTID.getSchedClass(), DefIdx); 2139089751535d6e9adf65842e2ca5867bf9a70e1e95Evan Cheng if (Subtarget.isCortexA9()) 2140089751535d6e9adf65842e2ca5867bf9a70e1e95Evan Cheng return Latency <= 2 ? 1 : Latency - 1; 2141089751535d6e9adf65842e2ca5867bf9a70e1e95Evan Cheng else 2142089751535d6e9adf65842e2ca5867bf9a70e1e95Evan Cheng return Latency <= 3 ? 1 : Latency - 2; 2143089751535d6e9adf65842e2ca5867bf9a70e1e95Evan Cheng } 2144a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng 2145a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng const TargetInstrDesc &UseTID = get(UseNode->getMachineOpcode()); 2146a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng const MachineSDNode *DefMN = dyn_cast<MachineSDNode>(DefNode); 2147a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng unsigned DefAlign = !DefMN->memoperands_empty() 2148a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng ? (*DefMN->memoperands_begin())->getAlignment() : 0; 2149a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng const MachineSDNode *UseMN = dyn_cast<MachineSDNode>(UseNode); 2150a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng unsigned UseAlign = !UseMN->memoperands_empty() 2151a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng ? (*UseMN->memoperands_begin())->getAlignment() : 0; 21527e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng int Latency = getOperandLatency(ItinData, DefTID, DefIdx, DefAlign, 21537e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng UseTID, UseIdx, UseAlign); 21547e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng 21557e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng if (Latency > 1 && 21567e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng (Subtarget.isCortexA8() || Subtarget.isCortexA9())) { 21577e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng // FIXME: Shifter op hack: no shift (i.e. [r +/- r]) or [r + r << 2] 21587e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng // variants are one cycle cheaper. 21597e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng switch (DefTID.getOpcode()) { 21607e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng default: break; 21617e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng case ARM::LDRrs: 21627e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng case ARM::LDRBrs: { 21637e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng unsigned ShOpVal = 21647e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng cast<ConstantSDNode>(DefNode->getOperand(2))->getZExtValue(); 21657e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal); 21667e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng if (ShImm == 0 || 21677e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng (ShImm == 2 && ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl)) 21687e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng --Latency; 21697e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng break; 21707e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng } 21717e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng case ARM::t2LDRs: 21727e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng case ARM::t2LDRBs: 21737e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng case ARM::t2LDRHs: 21747e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng case ARM::t2LDRSHs: { 21757e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng // Thumb2 mode: lsl only. 21767e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng unsigned ShAmt = 21777e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng cast<ConstantSDNode>(DefNode->getOperand(2))->getZExtValue(); 21787e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng if (ShAmt == 0 || ShAmt == 2) 21797e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng --Latency; 21807e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng break; 21817e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng } 21827e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng } 21837e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng } 21847e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng 21857e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng return Latency; 2186a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng} 21872312842de0c641107dd04d7e056d02491cc781caEvan Cheng 21888239daf7c83a65a189c352cce3191cdc3bbfe151Evan Chengint ARMBaseInstrInfo::getInstrLatency(const InstrItineraryData *ItinData, 21898239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng const MachineInstr *MI, 21908239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng unsigned *PredCost) const { 21918239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng if (MI->isCopyLike() || MI->isInsertSubreg() || 21928239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng MI->isRegSequence() || MI->isImplicitDef()) 21938239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng return 1; 21948239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng 21958239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng if (!ItinData || ItinData->isEmpty()) 21968239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng return 1; 21978239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng 21988239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng const TargetInstrDesc &TID = MI->getDesc(); 21998239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng unsigned Class = TID.getSchedClass(); 22008239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng unsigned UOps = ItinData->Itineraries[Class].NumMicroOps; 22018239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng if (PredCost && TID.hasImplicitDefOfPhysReg(ARM::CPSR)) 22028239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng // When predicated, CPSR is an additional source operand for CPSR updating 22038239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng // instructions, this apparently increases their latencies. 22048239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng *PredCost = 1; 22058239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng if (UOps) 22068239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng return ItinData->getStageLatency(Class); 22078239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng return getNumMicroOps(ItinData, MI); 22088239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng} 22098239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng 22108239daf7c83a65a189c352cce3191cdc3bbfe151Evan Chengint ARMBaseInstrInfo::getInstrLatency(const InstrItineraryData *ItinData, 22118239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng SDNode *Node) const { 22128239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng if (!Node->isMachineOpcode()) 22138239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng return 1; 22148239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng 22158239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng if (!ItinData || ItinData->isEmpty()) 22168239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng return 1; 22178239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng 22188239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng unsigned Opcode = Node->getMachineOpcode(); 22198239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng switch (Opcode) { 22208239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng default: 22218239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng return ItinData->getStageLatency(get(Opcode).getSchedClass()); 222273fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMQIA: 222373fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMQDB: 222473fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMQIA: 222573fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMQDB: 22268239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng return 2; 22278b3ca6216d62bf3f729c2e122dcfeb7c4d7500dcEric Christopher } 22288239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng} 22298239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng 22302312842de0c641107dd04d7e056d02491cc781caEvan Chengbool ARMBaseInstrInfo:: 22312312842de0c641107dd04d7e056d02491cc781caEvan ChenghasHighOperandLatency(const InstrItineraryData *ItinData, 22322312842de0c641107dd04d7e056d02491cc781caEvan Cheng const MachineRegisterInfo *MRI, 22332312842de0c641107dd04d7e056d02491cc781caEvan Cheng const MachineInstr *DefMI, unsigned DefIdx, 22342312842de0c641107dd04d7e056d02491cc781caEvan Cheng const MachineInstr *UseMI, unsigned UseIdx) const { 22352312842de0c641107dd04d7e056d02491cc781caEvan Cheng unsigned DDomain = DefMI->getDesc().TSFlags & ARMII::DomainMask; 22362312842de0c641107dd04d7e056d02491cc781caEvan Cheng unsigned UDomain = UseMI->getDesc().TSFlags & ARMII::DomainMask; 22372312842de0c641107dd04d7e056d02491cc781caEvan Cheng if (Subtarget.isCortexA8() && 22382312842de0c641107dd04d7e056d02491cc781caEvan Cheng (DDomain == ARMII::DomainVFP || UDomain == ARMII::DomainVFP)) 22392312842de0c641107dd04d7e056d02491cc781caEvan Cheng // CortexA8 VFP instructions are not pipelined. 22402312842de0c641107dd04d7e056d02491cc781caEvan Cheng return true; 22412312842de0c641107dd04d7e056d02491cc781caEvan Cheng 22422312842de0c641107dd04d7e056d02491cc781caEvan Cheng // Hoist VFP / NEON instructions with 4 or higher latency. 22432312842de0c641107dd04d7e056d02491cc781caEvan Cheng int Latency = getOperandLatency(ItinData, DefMI, DefIdx, UseMI, UseIdx); 22442312842de0c641107dd04d7e056d02491cc781caEvan Cheng if (Latency <= 3) 22452312842de0c641107dd04d7e056d02491cc781caEvan Cheng return false; 22462312842de0c641107dd04d7e056d02491cc781caEvan Cheng return DDomain == ARMII::DomainVFP || DDomain == ARMII::DomainNEON || 22472312842de0c641107dd04d7e056d02491cc781caEvan Cheng UDomain == ARMII::DomainVFP || UDomain == ARMII::DomainNEON; 22482312842de0c641107dd04d7e056d02491cc781caEvan Cheng} 2249c8141dfc7f983cb04e65d8acd6bcbdc8e4b8a0aeEvan Cheng 2250c8141dfc7f983cb04e65d8acd6bcbdc8e4b8a0aeEvan Chengbool ARMBaseInstrInfo:: 2251c8141dfc7f983cb04e65d8acd6bcbdc8e4b8a0aeEvan ChenghasLowDefLatency(const InstrItineraryData *ItinData, 2252c8141dfc7f983cb04e65d8acd6bcbdc8e4b8a0aeEvan Cheng const MachineInstr *DefMI, unsigned DefIdx) const { 2253c8141dfc7f983cb04e65d8acd6bcbdc8e4b8a0aeEvan Cheng if (!ItinData || ItinData->isEmpty()) 2254c8141dfc7f983cb04e65d8acd6bcbdc8e4b8a0aeEvan Cheng return false; 2255c8141dfc7f983cb04e65d8acd6bcbdc8e4b8a0aeEvan Cheng 2256c8141dfc7f983cb04e65d8acd6bcbdc8e4b8a0aeEvan Cheng unsigned DDomain = DefMI->getDesc().TSFlags & ARMII::DomainMask; 2257c8141dfc7f983cb04e65d8acd6bcbdc8e4b8a0aeEvan Cheng if (DDomain == ARMII::DomainGeneral) { 2258c8141dfc7f983cb04e65d8acd6bcbdc8e4b8a0aeEvan Cheng unsigned DefClass = DefMI->getDesc().getSchedClass(); 2259c8141dfc7f983cb04e65d8acd6bcbdc8e4b8a0aeEvan Cheng int DefCycle = ItinData->getOperandCycle(DefClass, DefIdx); 2260c8141dfc7f983cb04e65d8acd6bcbdc8e4b8a0aeEvan Cheng return (DefCycle != -1 && DefCycle <= 2); 2261c8141dfc7f983cb04e65d8acd6bcbdc8e4b8a0aeEvan Cheng } 2262c8141dfc7f983cb04e65d8acd6bcbdc8e4b8a0aeEvan Cheng return false; 2263c8141dfc7f983cb04e65d8acd6bcbdc8e4b8a0aeEvan Cheng} 226448575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng 226548575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Chengbool 226648575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan ChengARMBaseInstrInfo::isFpMLxInstruction(unsigned Opcode, unsigned &MulOpc, 226748575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng unsigned &AddSubOpc, 226848575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng bool &NegAcc, bool &HasLane) const { 226948575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng DenseMap<unsigned, unsigned>::const_iterator I = MLxEntryMap.find(Opcode); 227048575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng if (I == MLxEntryMap.end()) 227148575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng return false; 227248575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng 227348575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng const ARM_MLxEntry &Entry = ARM_MLxTable[I->second]; 227448575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng MulOpc = Entry.MulOpc; 227548575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng AddSubOpc = Entry.AddSubOpc; 227648575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng NegAcc = Entry.NegAcc; 227748575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng HasLane = Entry.HasLane; 227848575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng return true; 227948575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng} 2280