ARMBaseInstrInfo.cpp revision 344d9db97062736cd66da6c07baa9108b6cfa419
131c24bf5b39cc8391d4cfdbf8cf5163975fdb81eJim Grosbach//===- ARMBaseInstrInfo.cpp - ARM Instruction Information -------*- C++ -*-===// 2334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// 3334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// The LLVM Compiler Infrastructure 4334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// 5334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// This file is distributed under the University of Illinois Open Source 6334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// License. See LICENSE.TXT for details. 7334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// 8334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin//===----------------------------------------------------------------------===// 9334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// 10334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// This file contains the Base ARM implementation of the TargetInstrInfo class. 11334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// 12334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin//===----------------------------------------------------------------------===// 13334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 14334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "ARMBaseInstrInfo.h" 15334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "ARM.h" 16334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "ARMAddressingModes.h" 17d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng#include "ARMConstantPoolValue.h" 18334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "ARMMachineFunctionInfo.h" 19f95215f551949d5e5adfbf4753aa833b9009b77aAnton Korobeynikov#include "ARMRegisterInfo.h" 204dbbe3433f7339ed277af55037ff6847f484e5abChris Lattner#include "ARMGenInstrInfo.inc" 21fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng#include "llvm/Constants.h" 22fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng#include "llvm/Function.h" 23fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng#include "llvm/GlobalValue.h" 24334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "llvm/ADT/STLExtras.h" 25334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "llvm/CodeGen/LiveVariables.h" 26d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng#include "llvm/CodeGen/MachineConstantPool.h" 27334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "llvm/CodeGen/MachineFrameInfo.h" 28334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "llvm/CodeGen/MachineInstrBuilder.h" 29334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "llvm/CodeGen/MachineJumpTableInfo.h" 30249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov#include "llvm/CodeGen/MachineMemOperand.h" 312457f2c66184e978d4ed8fa9e2128effff26cb0bEvan Cheng#include "llvm/CodeGen/MachineRegisterInfo.h" 32249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov#include "llvm/CodeGen/PseudoSourceValue.h" 33af76e592c7f9deff0e55c13dbb4a34f07f1c7f64Chris Lattner#include "llvm/MC/MCAsmInfo.h" 34334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "llvm/Support/CommandLine.h" 35f95215f551949d5e5adfbf4753aa833b9009b77aAnton Korobeynikov#include "llvm/Support/Debug.h" 36c25e7581b9b8088910da31702d4ca21c4734c6d7Torok Edwin#include "llvm/Support/ErrorHandling.h" 37334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinusing namespace llvm; 38334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 39334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinstatic cl::opt<bool> 40334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinEnableARM3Addr("enable-arm-3-addr-conv", cl::Hidden, 41334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin cl::desc("Enable ARM 2-addr to 3-addr conv")); 42334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 43b3c04ec956247a984b3113a01cfbfad91e5ca5b3Owen Andersonstatic cl::opt<bool> 4400d4f48168eae664e1f8fefc17a912c05b878513Owen AndersonOldARMIfCvt("old-arm-ifcvt", cl::Hidden, 45b3c04ec956247a984b3113a01cfbfad91e5ca5b3Owen Anderson cl::desc("Use old-style ARM if-conversion heuristics")); 46b3c04ec956247a984b3113a01cfbfad91e5ca5b3Owen Anderson 47f95215f551949d5e5adfbf4753aa833b9009b77aAnton KorobeynikovARMBaseInstrInfo::ARMBaseInstrInfo(const ARMSubtarget& STI) 48f95215f551949d5e5adfbf4753aa833b9009b77aAnton Korobeynikov : TargetInstrInfoImpl(ARMInsts, array_lengthof(ARMInsts)), 49f95215f551949d5e5adfbf4753aa833b9009b77aAnton Korobeynikov Subtarget(STI) { 50334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 51334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 52334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinMachineInstr * 53334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinARMBaseInstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI, 54334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineBasicBlock::iterator &MBBI, 55334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin LiveVariables *LV) const { 5678703ddafe3d037f75d8ca188e4829d238289ac3Evan Cheng // FIXME: Thumb2 support. 5778703ddafe3d037f75d8ca188e4829d238289ac3Evan Cheng 58334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (!EnableARM3Addr) 59334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return NULL; 60334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 61334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineInstr *MI = MBBI; 62334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineFunction &MF = *MI->getParent()->getParent(); 6399405df044f2c584242e711cc9023ec90356da82Bruno Cardoso Lopes uint64_t TSFlags = MI->getDesc().TSFlags; 64334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool isPre = false; 65334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin switch ((TSFlags & ARMII::IndexModeMask) >> ARMII::IndexModeShift) { 66334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin default: return NULL; 67334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMII::IndexModePre: 68334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin isPre = true; 69334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin break; 70334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMII::IndexModePost: 71334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin break; 72334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 73334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 74334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Try splitting an indexed load/store to an un-indexed one plus an add/sub 75334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // operation. 76334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned MemOpc = getUnindexedOpcode(MI->getOpcode()); 77334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (MemOpc == 0) 78334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return NULL; 79334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 80334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineInstr *UpdateMI = NULL; 81334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineInstr *MemMI = NULL; 82334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned AddrMode = (TSFlags & ARMII::AddrModeMask); 83334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const TargetInstrDesc &TID = MI->getDesc(); 84334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned NumOps = TID.getNumOperands(); 85334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool isLoad = !TID.mayStore(); 86334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const MachineOperand &WB = isLoad ? MI->getOperand(1) : MI->getOperand(0); 87334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const MachineOperand &Base = MI->getOperand(2); 88334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const MachineOperand &Offset = MI->getOperand(NumOps-3); 89334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned WBReg = WB.getReg(); 90334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned BaseReg = Base.getReg(); 91334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned OffReg = Offset.getReg(); 92334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned OffImm = MI->getOperand(NumOps-2).getImm(); 93334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin ARMCC::CondCodes Pred = (ARMCC::CondCodes)MI->getOperand(NumOps-1).getImm(); 94334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin switch (AddrMode) { 95334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin default: 96334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin assert(false && "Unknown indexed op!"); 97334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return NULL; 98334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMII::AddrMode2: { 99334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool isSub = ARM_AM::getAM2Op(OffImm) == ARM_AM::sub; 100334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned Amt = ARM_AM::getAM2Offset(OffImm); 101334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (OffReg == 0) { 102e7cbe4118b7ddf05032ff8772a98c51e1637bb5cEvan Cheng if (ARM_AM::getSOImmVal(Amt) == -1) 103334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Can't encode it in a so_imm operand. This transformation will 104334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // add more than 1 instruction. Abandon! 105334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return NULL; 106334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin UpdateMI = BuildMI(MF, MI->getDebugLoc(), 10778703ddafe3d037f75d8ca188e4829d238289ac3Evan Cheng get(isSub ? ARM::SUBri : ARM::ADDri), WBReg) 108e7cbe4118b7ddf05032ff8772a98c51e1637bb5cEvan Cheng .addReg(BaseReg).addImm(Amt) 109334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addImm(Pred).addReg(0).addReg(0); 110334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } else if (Amt != 0) { 111334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin ARM_AM::ShiftOpc ShOpc = ARM_AM::getAM2ShiftOpc(OffImm); 112334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned SOOpc = ARM_AM::getSORegOpc(ShOpc, Amt); 113334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin UpdateMI = BuildMI(MF, MI->getDebugLoc(), 11478703ddafe3d037f75d8ca188e4829d238289ac3Evan Cheng get(isSub ? ARM::SUBrs : ARM::ADDrs), WBReg) 115334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(BaseReg).addReg(OffReg).addReg(0).addImm(SOOpc) 116334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addImm(Pred).addReg(0).addReg(0); 117334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } else 118334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin UpdateMI = BuildMI(MF, MI->getDebugLoc(), 11978703ddafe3d037f75d8ca188e4829d238289ac3Evan Cheng get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg) 120334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(BaseReg).addReg(OffReg) 121334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addImm(Pred).addReg(0).addReg(0); 122334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin break; 123334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 124334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMII::AddrMode3 : { 125334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool isSub = ARM_AM::getAM3Op(OffImm) == ARM_AM::sub; 126334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned Amt = ARM_AM::getAM3Offset(OffImm); 127334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (OffReg == 0) 128334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Immediate is 8-bits. It's guaranteed to fit in a so_imm operand. 129334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin UpdateMI = BuildMI(MF, MI->getDebugLoc(), 13078703ddafe3d037f75d8ca188e4829d238289ac3Evan Cheng get(isSub ? ARM::SUBri : ARM::ADDri), WBReg) 131334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(BaseReg).addImm(Amt) 132334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addImm(Pred).addReg(0).addReg(0); 133334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin else 134334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin UpdateMI = BuildMI(MF, MI->getDebugLoc(), 13578703ddafe3d037f75d8ca188e4829d238289ac3Evan Cheng get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg) 136334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(BaseReg).addReg(OffReg) 137334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addImm(Pred).addReg(0).addReg(0); 138334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin break; 139334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 140334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 141334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 142334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin std::vector<MachineInstr*> NewMIs; 143334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (isPre) { 144334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (isLoad) 145334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MemMI = BuildMI(MF, MI->getDebugLoc(), 146334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin get(MemOpc), MI->getOperand(0).getReg()) 147334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(WBReg).addReg(0).addImm(0).addImm(Pred); 148334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin else 149334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MemMI = BuildMI(MF, MI->getDebugLoc(), 150334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin get(MemOpc)).addReg(MI->getOperand(1).getReg()) 151334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(WBReg).addReg(0).addImm(0).addImm(Pred); 152334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin NewMIs.push_back(MemMI); 153334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin NewMIs.push_back(UpdateMI); 154334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } else { 155334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (isLoad) 156334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MemMI = BuildMI(MF, MI->getDebugLoc(), 157334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin get(MemOpc), MI->getOperand(0).getReg()) 158334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred); 159334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin else 160334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MemMI = BuildMI(MF, MI->getDebugLoc(), 161334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin get(MemOpc)).addReg(MI->getOperand(1).getReg()) 162334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred); 163334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (WB.isDead()) 164334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin UpdateMI->getOperand(0).setIsDead(); 165334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin NewMIs.push_back(UpdateMI); 166334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin NewMIs.push_back(MemMI); 167334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 168334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 169334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Transfer LiveVariables states, kill / dead info. 170334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (LV) { 171334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 172334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineOperand &MO = MI->getOperand(i); 173334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (MO.isReg() && MO.getReg() && 174334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin TargetRegisterInfo::isVirtualRegister(MO.getReg())) { 175334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned Reg = MO.getReg(); 176334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 177334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin LiveVariables::VarInfo &VI = LV->getVarInfo(Reg); 178334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (MO.isDef()) { 179334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineInstr *NewMI = (Reg == WBReg) ? UpdateMI : MemMI; 180334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (MO.isDead()) 181334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin LV->addVirtualRegisterDead(Reg, NewMI); 182334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 183334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (MO.isUse() && MO.isKill()) { 184334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin for (unsigned j = 0; j < 2; ++j) { 185334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Look at the two new MI's in reverse order. 186334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineInstr *NewMI = NewMIs[j]; 187334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (!NewMI->readsRegister(Reg)) 188334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin continue; 189334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin LV->addVirtualRegisterKilled(Reg, NewMI); 190334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (VI.removeKill(MI)) 191334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin VI.Kills.push_back(NewMI); 192334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin break; 193334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 194334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 195334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 196334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 197334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 198334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 199334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MFI->insert(MBBI, NewMIs[1]); 200334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MFI->insert(MBBI, NewMIs[0]); 201334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return NewMIs[0]; 202334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 203334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 2042457f2c66184e978d4ed8fa9e2128effff26cb0bEvan Chengbool 2052457f2c66184e978d4ed8fa9e2128effff26cb0bEvan ChengARMBaseInstrInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB, 20618f30e6f5e80787808fe1455742452a5210afe07Jim Grosbach MachineBasicBlock::iterator MI, 20718f30e6f5e80787808fe1455742452a5210afe07Jim Grosbach const std::vector<CalleeSavedInfo> &CSI, 20818f30e6f5e80787808fe1455742452a5210afe07Jim Grosbach const TargetRegisterInfo *TRI) const { 2092457f2c66184e978d4ed8fa9e2128effff26cb0bEvan Cheng if (CSI.empty()) 2102457f2c66184e978d4ed8fa9e2128effff26cb0bEvan Cheng return false; 2112457f2c66184e978d4ed8fa9e2128effff26cb0bEvan Cheng 2122457f2c66184e978d4ed8fa9e2128effff26cb0bEvan Cheng DebugLoc DL; 2132457f2c66184e978d4ed8fa9e2128effff26cb0bEvan Cheng if (MI != MBB.end()) DL = MI->getDebugLoc(); 2142457f2c66184e978d4ed8fa9e2128effff26cb0bEvan Cheng 2152457f2c66184e978d4ed8fa9e2128effff26cb0bEvan Cheng for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 2162457f2c66184e978d4ed8fa9e2128effff26cb0bEvan Cheng unsigned Reg = CSI[i].getReg(); 2172457f2c66184e978d4ed8fa9e2128effff26cb0bEvan Cheng bool isKill = true; 2182457f2c66184e978d4ed8fa9e2128effff26cb0bEvan Cheng 2192457f2c66184e978d4ed8fa9e2128effff26cb0bEvan Cheng // Add the callee-saved register as live-in unless it's LR and 2202457f2c66184e978d4ed8fa9e2128effff26cb0bEvan Cheng // @llvm.returnaddress is called. If LR is returned for @llvm.returnaddress 2212457f2c66184e978d4ed8fa9e2128effff26cb0bEvan Cheng // then it's already added to the function and entry block live-in sets. 2222457f2c66184e978d4ed8fa9e2128effff26cb0bEvan Cheng if (Reg == ARM::LR) { 2232457f2c66184e978d4ed8fa9e2128effff26cb0bEvan Cheng MachineFunction &MF = *MBB.getParent(); 2242457f2c66184e978d4ed8fa9e2128effff26cb0bEvan Cheng if (MF.getFrameInfo()->isReturnAddressTaken() && 2252457f2c66184e978d4ed8fa9e2128effff26cb0bEvan Cheng MF.getRegInfo().isLiveIn(Reg)) 2262457f2c66184e978d4ed8fa9e2128effff26cb0bEvan Cheng isKill = false; 2272457f2c66184e978d4ed8fa9e2128effff26cb0bEvan Cheng } 2282457f2c66184e978d4ed8fa9e2128effff26cb0bEvan Cheng 2292457f2c66184e978d4ed8fa9e2128effff26cb0bEvan Cheng if (isKill) 2302457f2c66184e978d4ed8fa9e2128effff26cb0bEvan Cheng MBB.addLiveIn(Reg); 2312457f2c66184e978d4ed8fa9e2128effff26cb0bEvan Cheng 2322457f2c66184e978d4ed8fa9e2128effff26cb0bEvan Cheng // Insert the spill to the stack frame. The register is killed at the spill 2332bbb76909126db5bed6bde84b16d94ab5de4d372Michael J. Spencer // 23442d075c4fb21995265961501cec9ff6e3fb497ceRafael Espindola const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); 2352457f2c66184e978d4ed8fa9e2128effff26cb0bEvan Cheng storeRegToStackSlot(MBB, MI, Reg, isKill, 23642d075c4fb21995265961501cec9ff6e3fb497ceRafael Espindola CSI[i].getFrameIdx(), RC, TRI); 2372457f2c66184e978d4ed8fa9e2128effff26cb0bEvan Cheng } 2382457f2c66184e978d4ed8fa9e2128effff26cb0bEvan Cheng return true; 2392457f2c66184e978d4ed8fa9e2128effff26cb0bEvan Cheng} 2402457f2c66184e978d4ed8fa9e2128effff26cb0bEvan Cheng 241334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// Branch analysis. 242334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinbool 243334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinARMBaseInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB, 244334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineBasicBlock *&FBB, 245334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin SmallVectorImpl<MachineOperand> &Cond, 246334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool AllowModify) const { 247334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // If the block has no terminators, it just falls into the block after it. 248334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineBasicBlock::iterator I = MBB.end(); 24993d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen if (I == MBB.begin()) 25093d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen return false; 25193d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen --I; 25293d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen while (I->isDebugValue()) { 25393d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen if (I == MBB.begin()) 25493d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen return false; 25593d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen --I; 25693d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen } 25793d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen if (!isUnpredicatedTerminator(I)) 258334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 259334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 260334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Get the last instruction in the block. 261334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineInstr *LastInst = I; 262334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 263334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // If there is only one terminator instruction, process it. 264334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned LastOpc = LastInst->getOpcode(); 265334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) { 2665ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng if (isUncondBranchOpcode(LastOpc)) { 267334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin TBB = LastInst->getOperand(0).getMBB(); 268334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 269334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 2705ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng if (isCondBranchOpcode(LastOpc)) { 271334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Block ends with fall-through condbranch. 272334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin TBB = LastInst->getOperand(0).getMBB(); 273334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin Cond.push_back(LastInst->getOperand(1)); 274334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin Cond.push_back(LastInst->getOperand(2)); 275334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 276334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 277334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; // Can't handle indirect branch. 278334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 279334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 280334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Get the instruction before it if it is a terminator. 281334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineInstr *SecondLastInst = I; 282108c8724663354050dc09bb1262c3e4511adf82fEvan Cheng unsigned SecondLastOpc = SecondLastInst->getOpcode(); 283108c8724663354050dc09bb1262c3e4511adf82fEvan Cheng 284108c8724663354050dc09bb1262c3e4511adf82fEvan Cheng // If AllowModify is true and the block ends with two or more unconditional 285108c8724663354050dc09bb1262c3e4511adf82fEvan Cheng // branches, delete all but the first unconditional branch. 286108c8724663354050dc09bb1262c3e4511adf82fEvan Cheng if (AllowModify && isUncondBranchOpcode(LastOpc)) { 287108c8724663354050dc09bb1262c3e4511adf82fEvan Cheng while (isUncondBranchOpcode(SecondLastOpc)) { 288108c8724663354050dc09bb1262c3e4511adf82fEvan Cheng LastInst->eraseFromParent(); 289108c8724663354050dc09bb1262c3e4511adf82fEvan Cheng LastInst = SecondLastInst; 290108c8724663354050dc09bb1262c3e4511adf82fEvan Cheng LastOpc = LastInst->getOpcode(); 291676e258366dd17a0b4ee6ac66914237ce181202eEvan Cheng if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) { 292676e258366dd17a0b4ee6ac66914237ce181202eEvan Cheng // Return now the only terminator is an unconditional branch. 293676e258366dd17a0b4ee6ac66914237ce181202eEvan Cheng TBB = LastInst->getOperand(0).getMBB(); 294676e258366dd17a0b4ee6ac66914237ce181202eEvan Cheng return false; 295676e258366dd17a0b4ee6ac66914237ce181202eEvan Cheng } else { 296108c8724663354050dc09bb1262c3e4511adf82fEvan Cheng SecondLastInst = I; 297108c8724663354050dc09bb1262c3e4511adf82fEvan Cheng SecondLastOpc = SecondLastInst->getOpcode(); 298108c8724663354050dc09bb1262c3e4511adf82fEvan Cheng } 299108c8724663354050dc09bb1262c3e4511adf82fEvan Cheng } 300108c8724663354050dc09bb1262c3e4511adf82fEvan Cheng } 301334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 302334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // If there are three terminators, we don't know what sort of block this is. 303334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(--I)) 304334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; 305334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 3065ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng // If the block ends with a B and a Bcc, handle it. 3075ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng if (isCondBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) { 308334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin TBB = SecondLastInst->getOperand(0).getMBB(); 309334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin Cond.push_back(SecondLastInst->getOperand(1)); 310334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin Cond.push_back(SecondLastInst->getOperand(2)); 311334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin FBB = LastInst->getOperand(0).getMBB(); 312334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 313334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 314334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 315334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // If the block ends with two unconditional branches, handle it. The second 316334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // one is not executed, so remove it. 3175ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng if (isUncondBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) { 318334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin TBB = SecondLastInst->getOperand(0).getMBB(); 319334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin I = LastInst; 320334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (AllowModify) 321334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin I->eraseFromParent(); 322334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 323334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 324334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 325334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // ...likewise if it ends with a branch table followed by an unconditional 326334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // branch. The branch folder can create these, and we must get rid of them for 327334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // correctness of Thumb constant islands. 3288d4de5abfa1bcd974554ea14904ebf7af289e84dBob Wilson if ((isJumpTableBranchOpcode(SecondLastOpc) || 3298d4de5abfa1bcd974554ea14904ebf7af289e84dBob Wilson isIndirectBranchOpcode(SecondLastOpc)) && 3305ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng isUncondBranchOpcode(LastOpc)) { 331334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin I = LastInst; 332334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (AllowModify) 333334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin I->eraseFromParent(); 334334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; 335334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 336334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 337334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Otherwise, can't handle this. 338334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; 339334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 340334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 341334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 342334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinunsigned ARMBaseInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const { 343334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineBasicBlock::iterator I = MBB.end(); 344334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (I == MBB.begin()) return 0; 345334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin --I; 34693d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen while (I->isDebugValue()) { 34793d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen if (I == MBB.begin()) 34893d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen return 0; 34993d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen --I; 35093d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen } 3515ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng if (!isUncondBranchOpcode(I->getOpcode()) && 3525ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng !isCondBranchOpcode(I->getOpcode())) 353334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 0; 354334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 355334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Remove the branch. 356334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin I->eraseFromParent(); 357334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 358334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin I = MBB.end(); 359334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 360334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (I == MBB.begin()) return 1; 361334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin --I; 3625ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng if (!isCondBranchOpcode(I->getOpcode())) 363334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 1; 364334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 365334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Remove the branch. 366334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin I->eraseFromParent(); 367334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 2; 368334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 369334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 370334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinunsigned 371334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinARMBaseInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 3723bf912593301152b65accb9d9c37a95172f1df5aStuart Hastings MachineBasicBlock *FBB, 3733bf912593301152b65accb9d9c37a95172f1df5aStuart Hastings const SmallVectorImpl<MachineOperand> &Cond, 3743bf912593301152b65accb9d9c37a95172f1df5aStuart Hastings DebugLoc DL) const { 3756495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ARMFunctionInfo *AFI = MBB.getParent()->getInfo<ARMFunctionInfo>(); 3766495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng int BOpc = !AFI->isThumbFunction() 3776495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ? ARM::B : (AFI->isThumb2Function() ? ARM::t2B : ARM::tB); 3786495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng int BccOpc = !AFI->isThumbFunction() 3796495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ? ARM::Bcc : (AFI->isThumb2Function() ? ARM::t2Bcc : ARM::tBcc); 380334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 381334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Shouldn't be a fall through. 382334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin assert(TBB && "InsertBranch must not be told to insert a fallthrough"); 383334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin assert((Cond.size() == 2 || Cond.size() == 0) && 384334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin "ARM branch conditions have two components!"); 385334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 386334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (FBB == 0) { 387334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (Cond.empty()) // Unconditional branch? 3883bf912593301152b65accb9d9c37a95172f1df5aStuart Hastings BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB); 389334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin else 3903bf912593301152b65accb9d9c37a95172f1df5aStuart Hastings BuildMI(&MBB, DL, get(BccOpc)).addMBB(TBB) 391334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()); 392334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 1; 393334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 394334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 395334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Two-way conditional branch. 3963bf912593301152b65accb9d9c37a95172f1df5aStuart Hastings BuildMI(&MBB, DL, get(BccOpc)).addMBB(TBB) 397334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()); 3983bf912593301152b65accb9d9c37a95172f1df5aStuart Hastings BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB); 399334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 2; 400334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 401334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 402334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinbool ARMBaseInstrInfo:: 403334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const { 404334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin ARMCC::CondCodes CC = (ARMCC::CondCodes)(int)Cond[0].getImm(); 405334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin Cond[0].setImm(ARMCC::getOppositeCondition(CC)); 406334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 407334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 408334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 409334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinbool ARMBaseInstrInfo:: 410334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinPredicateInstruction(MachineInstr *MI, 411334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const SmallVectorImpl<MachineOperand> &Pred) const { 412334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned Opc = MI->getOpcode(); 4135ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng if (isUncondBranchOpcode(Opc)) { 4145ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng MI->setDesc(get(getMatchingCondBranchOpcode(Opc))); 415334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI->addOperand(MachineOperand::CreateImm(Pred[0].getImm())); 416334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI->addOperand(MachineOperand::CreateReg(Pred[1].getReg(), false)); 417334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; 418334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 419334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 420334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin int PIdx = MI->findFirstPredOperandIdx(); 421334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (PIdx != -1) { 422334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineOperand &PMO = MI->getOperand(PIdx); 423334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin PMO.setImm(Pred[0].getImm()); 424334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI->getOperand(PIdx+1).setReg(Pred[1].getReg()); 425334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; 426334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 427334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 428334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 429334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 430334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinbool ARMBaseInstrInfo:: 431334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinSubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1, 432334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const SmallVectorImpl<MachineOperand> &Pred2) const { 433334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (Pred1.size() > 2 || Pred2.size() > 2) 434334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 435334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 436334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin ARMCC::CondCodes CC1 = (ARMCC::CondCodes)Pred1[0].getImm(); 437334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin ARMCC::CondCodes CC2 = (ARMCC::CondCodes)Pred2[0].getImm(); 438334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (CC1 == CC2) 439334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; 440334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 441334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin switch (CC1) { 442334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin default: 443334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 444334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMCC::AL: 445334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; 446334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMCC::HS: 447334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return CC2 == ARMCC::HI; 448334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMCC::LS: 449334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return CC2 == ARMCC::LO || CC2 == ARMCC::EQ; 450334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMCC::GE: 451334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return CC2 == ARMCC::GT; 452334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMCC::LE: 453334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return CC2 == ARMCC::LT; 454334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 455334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 456334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 457334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinbool ARMBaseInstrInfo::DefinesPredicate(MachineInstr *MI, 458334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin std::vector<MachineOperand> &Pred) const { 4598fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng // FIXME: This confuses implicit_def with optional CPSR def. 460334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const TargetInstrDesc &TID = MI->getDesc(); 461334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (!TID.getImplicitDefs() && !TID.hasOptionalDef()) 462334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 463334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 464334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool Found = false; 465334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 466334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const MachineOperand &MO = MI->getOperand(i); 467334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (MO.isReg() && MO.getReg() == ARM::CPSR) { 468334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin Pred.push_back(MO); 469334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin Found = true; 470334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 471334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 472334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 473334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return Found; 474334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 475334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 476ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng/// isPredicable - Return true if the specified instruction can be predicated. 477ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng/// By default, this returns true for every instruction with a 478ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng/// PredicateOperand. 479ac0869dc8a7986855c5557cc67d4709600158ef5Evan Chengbool ARMBaseInstrInfo::isPredicable(MachineInstr *MI) const { 480ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng const TargetInstrDesc &TID = MI->getDesc(); 481ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng if (!TID.isPredicable()) 482ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng return false; 483ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng 484ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng if ((TID.TSFlags & ARMII::DomainMask) == ARMII::DomainNEON) { 485ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng ARMFunctionInfo *AFI = 486ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng MI->getParent()->getParent()->getInfo<ARMFunctionInfo>(); 487d7f0810c934a7d13acb28c42d737ce58ec990ea8Evan Cheng return AFI->isThumb2Function(); 488ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng } 489ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng return true; 490ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng} 491334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 49256856b1f46ec1f073ceef4e826c544b8b1691608Chris Lattner/// FIXME: Works around a gcc miscompilation with -fstrict-aliasing. 49356856b1f46ec1f073ceef4e826c544b8b1691608Chris LattnerDISABLE_INLINE 494334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinstatic unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT, 49556856b1f46ec1f073ceef4e826c544b8b1691608Chris Lattner unsigned JTI); 496334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinstatic unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT, 497334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned JTI) { 49856856b1f46ec1f073ceef4e826c544b8b1691608Chris Lattner assert(JTI < JT.size()); 499334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return JT[JTI].MBBs.size(); 500334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 501334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 502334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin/// GetInstSize - Return the size of the specified MachineInstr. 503334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin/// 504334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinunsigned ARMBaseInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const { 505334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const MachineBasicBlock &MBB = *MI->getParent(); 506334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const MachineFunction *MF = MBB.getParent(); 50733adcfb4d217f5f23d9bde8ba02b8e48f9605fc5Chris Lattner const MCAsmInfo *MAI = MF->getTarget().getMCAsmInfo(); 508334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 509334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Basic size info comes from the TSFlags field. 510334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const TargetInstrDesc &TID = MI->getDesc(); 51199405df044f2c584242e711cc9023ec90356da82Bruno Cardoso Lopes uint64_t TSFlags = TID.TSFlags; 512334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 513a0ee862f2e3a0d202244e02459ddcf0dca0e8607Evan Cheng unsigned Opc = MI->getOpcode(); 514334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin switch ((TSFlags & ARMII::SizeMask) >> ARMII::SizeShift) { 515334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin default: { 516334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // If this machine instr is an inline asm, measure it. 517334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (MI->getOpcode() == ARM::INLINEASM) 51833adcfb4d217f5f23d9bde8ba02b8e48f9605fc5Chris Lattner return getInlineAsmLength(MI->getOperand(0).getSymbolName(), *MAI); 519334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (MI->isLabel()) 520334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 0; 521a0ee862f2e3a0d202244e02459ddcf0dca0e8607Evan Cheng switch (Opc) { 522334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin default: 523c23197a26f34f559ea9797de51e187087c039c42Torok Edwin llvm_unreachable("Unknown or unset size field for instr!"); 524518bb53485df640d7b7e3f6b0544099020c42aa7Chris Lattner case TargetOpcode::IMPLICIT_DEF: 525518bb53485df640d7b7e3f6b0544099020c42aa7Chris Lattner case TargetOpcode::KILL: 5267431beaba2a01c3fe299c861b2ec85cbf1dc81c4Bill Wendling case TargetOpcode::PROLOG_LABEL: 527518bb53485df640d7b7e3f6b0544099020c42aa7Chris Lattner case TargetOpcode::EH_LABEL: 528375be7730a6f3dee7a6dc319ee6c355a11ac99adDale Johannesen case TargetOpcode::DBG_VALUE: 529334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 0; 530334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 531334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin break; 532334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 533789476240d6b6f8ad9366cadf790a82bd41bb0b3Evan Cheng case ARMII::Size8Bytes: return 8; // ARM instruction x 2. 534789476240d6b6f8ad9366cadf790a82bd41bb0b3Evan Cheng case ARMII::Size4Bytes: return 4; // ARM / Thumb2 instruction. 535789476240d6b6f8ad9366cadf790a82bd41bb0b3Evan Cheng case ARMII::Size2Bytes: return 2; // Thumb1 instruction. 536334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMII::SizeSpecial: { 537a0ee862f2e3a0d202244e02459ddcf0dca0e8607Evan Cheng switch (Opc) { 5383c38f96af2a5443d9f72fd078c2c98dd08746e51Jim Grosbach case ARM::MOVi32imm: 5393c38f96af2a5443d9f72fd078c2c98dd08746e51Jim Grosbach case ARM::t2MOVi32imm: 5403c38f96af2a5443d9f72fd078c2c98dd08746e51Jim Grosbach return 8; 541334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARM::CONSTPOOL_ENTRY: 542334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // If this machine instr is a constant pool entry, its size is recorded as 543334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // operand #2. 544334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return MI->getOperand(2).getImm(); 5455eb195153950bc7ebfc30649494a78b2096b5ef8Jim Grosbach case ARM::Int_eh_sjlj_longjmp: 5465eb195153950bc7ebfc30649494a78b2096b5ef8Jim Grosbach return 16; 5475eb195153950bc7ebfc30649494a78b2096b5ef8Jim Grosbach case ARM::tInt_eh_sjlj_longjmp: 5485eb195153950bc7ebfc30649494a78b2096b5ef8Jim Grosbach return 10; 549789476240d6b6f8ad9366cadf790a82bd41bb0b3Evan Cheng case ARM::Int_eh_sjlj_setjmp: 550d100755bab38784703f677b8b8eb174b624b346bJim Grosbach case ARM::Int_eh_sjlj_setjmp_nofp: 5510798eddd07b8dc827a4e6e9028c4c3a8d9444286Jim Grosbach return 20; 552d122874996a6faa8832569b632fd73a32ace7ae7Jim Grosbach case ARM::tInt_eh_sjlj_setjmp: 5535aa1684e5da9a85286bf7d29da419d261a70c2f2Jim Grosbach case ARM::t2Int_eh_sjlj_setjmp: 554d100755bab38784703f677b8b8eb174b624b346bJim Grosbach case ARM::t2Int_eh_sjlj_setjmp_nofp: 5550798eddd07b8dc827a4e6e9028c4c3a8d9444286Jim Grosbach return 12; 556334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARM::BR_JTr: 557334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARM::BR_JTm: 558334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARM::BR_JTadd: 559a0ee862f2e3a0d202244e02459ddcf0dca0e8607Evan Cheng case ARM::tBR_JTr: 560d26b14c34cbcee1448b86b524578fc51cc979023Evan Cheng case ARM::t2BR_JT: 561d26b14c34cbcee1448b86b524578fc51cc979023Evan Cheng case ARM::t2TBB: 562d26b14c34cbcee1448b86b524578fc51cc979023Evan Cheng case ARM::t2TBH: { 563334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // These are jumptable branches, i.e. a branch followed by an inlined 564d26b14c34cbcee1448b86b524578fc51cc979023Evan Cheng // jumptable. The size is 4 + 4 * number of entries. For TBB, each 565d26b14c34cbcee1448b86b524578fc51cc979023Evan Cheng // entry is one byte; TBH two byte each. 566a0ee862f2e3a0d202244e02459ddcf0dca0e8607Evan Cheng unsigned EntrySize = (Opc == ARM::t2TBB) 567a0ee862f2e3a0d202244e02459ddcf0dca0e8607Evan Cheng ? 1 : ((Opc == ARM::t2TBH) ? 2 : 4); 568334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned NumOps = TID.getNumOperands(); 569334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineOperand JTOP = 570334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI->getOperand(NumOps - (TID.isPredicable() ? 3 : 2)); 571334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned JTI = JTOP.getIndex(); 572334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo(); 573b1e803985d3378538ae9cff7eed4102c002d1e22Chris Lattner assert(MJTI != 0); 574334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables(); 575334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin assert(JTI < JT.size()); 576334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Thumb instructions are 2 byte aligned, but JT entries are 4 byte 577334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // 4 aligned. The assembler / linker may add 2 byte padding just before 578334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // the JT entries. The size does not include this padding; the 579334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // constant islands pass does separate bookkeeping for it. 580334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // FIXME: If we know the size of the function is less than (1 << 16) *2 581334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // bytes, we can use 16-bit entries instead. Then there won't be an 582334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // alignment issue. 58325f7cfc3cccba6f569f29f79ea533bae960b93c0Evan Cheng unsigned InstSize = (Opc == ARM::tBR_JTr || Opc == ARM::t2BR_JT) ? 2 : 4; 58425f7cfc3cccba6f569f29f79ea533bae960b93c0Evan Cheng unsigned NumEntries = getNumJTEntries(JT, JTI); 58525f7cfc3cccba6f569f29f79ea533bae960b93c0Evan Cheng if (Opc == ARM::t2TBB && (NumEntries & 1)) 58625f7cfc3cccba6f569f29f79ea533bae960b93c0Evan Cheng // Make sure the instruction that follows TBB is 2-byte aligned. 58725f7cfc3cccba6f569f29f79ea533bae960b93c0Evan Cheng // FIXME: Constant island pass should insert an "ALIGN" instruction 58825f7cfc3cccba6f569f29f79ea533bae960b93c0Evan Cheng // instead. 58925f7cfc3cccba6f569f29f79ea533bae960b93c0Evan Cheng ++NumEntries; 59025f7cfc3cccba6f569f29f79ea533bae960b93c0Evan Cheng return NumEntries * EntrySize + InstSize; 591334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 592334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin default: 593334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Otherwise, pseudo-instruction sizes are zero. 594334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 0; 595334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 596334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 597334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 598334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 0; // Not reached 599334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 600334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 601ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesenvoid ARMBaseInstrInfo::copyPhysReg(MachineBasicBlock &MBB, 602ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen MachineBasicBlock::iterator I, DebugLoc DL, 603ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen unsigned DestReg, unsigned SrcReg, 604ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen bool KillSrc) const { 605ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen bool GPRDest = ARM::GPRRegClass.contains(DestReg); 606ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen bool GPRSrc = ARM::GPRRegClass.contains(SrcReg); 607ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen 608ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen if (GPRDest && GPRSrc) { 609ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen AddDefaultCC(AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::MOVr), DestReg) 610ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen .addReg(SrcReg, getKillRegState(KillSrc)))); 611ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen return; 6127bfdca0206f51132b26094c6f83a5ac97ee0f943David Goodwin } 613334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 614ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen bool SPRDest = ARM::SPRRegClass.contains(DestReg); 615ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen bool SPRSrc = ARM::SPRRegClass.contains(SrcReg); 616ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen 617ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen unsigned Opc; 618ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen if (SPRDest && SPRSrc) 619ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen Opc = ARM::VMOVS; 620ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen else if (GPRDest && SPRSrc) 621ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen Opc = ARM::VMOVRS; 622ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen else if (SPRDest && GPRSrc) 623ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen Opc = ARM::VMOVSR; 624ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen else if (ARM::DPRRegClass.contains(DestReg, SrcReg)) 625ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen Opc = ARM::VMOVD; 626ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen else if (ARM::QPRRegClass.contains(DestReg, SrcReg)) 627ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen Opc = ARM::VMOVQ; 628ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen else if (ARM::QQPRRegClass.contains(DestReg, SrcReg)) 629ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen Opc = ARM::VMOVQQ; 630ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen else if (ARM::QQQQPRRegClass.contains(DestReg, SrcReg)) 631ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen Opc = ARM::VMOVQQQQ; 632ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen else 633ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen llvm_unreachable("Impossible reg-to-reg copy"); 634ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen 635ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc), DestReg); 636ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen MIB.addReg(SrcReg, getKillRegState(KillSrc)); 637ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen if (Opc != ARM::VMOVQQ && Opc != ARM::VMOVQQQQ) 638ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen AddDefaultPred(MIB); 639334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 640334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 641c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Chengstatic const 642c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan ChengMachineInstrBuilder &AddDReg(MachineInstrBuilder &MIB, 643c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Cheng unsigned Reg, unsigned SubIdx, unsigned State, 644c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Cheng const TargetRegisterInfo *TRI) { 645c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Cheng if (!SubIdx) 646c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Cheng return MIB.addReg(Reg, State); 647c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Cheng 648c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Cheng if (TargetRegisterInfo::isPhysicalRegister(Reg)) 649c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Cheng return MIB.addReg(TRI->getSubReg(Reg, SubIdx), State); 650c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Cheng return MIB.addReg(Reg, State, SubIdx); 651c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Cheng} 652c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Cheng 653334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinvoid ARMBaseInstrInfo:: 654334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinstoreRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 655334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned SrcReg, bool isKill, int FI, 656746ad69e088176819981b4b2c5ac8dcd49f5e60eEvan Cheng const TargetRegisterClass *RC, 657746ad69e088176819981b4b2c5ac8dcd49f5e60eEvan Cheng const TargetRegisterInfo *TRI) const { 658c7f3ace20c325521c68335a1689645b43b06ddf0Chris Lattner DebugLoc DL; 659334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (I != MBB.end()) DL = I->getDebugLoc(); 660249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MachineFunction &MF = *MBB.getParent(); 661249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MachineFrameInfo &MFI = *MF.getFrameInfo(); 66231bc849123011b8eae6bb3c79876d9a3c26a6a1dJim Grosbach unsigned Align = MFI.getObjectAlignment(FI); 663249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov 664249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MachineMemOperand *MMO = 66559db5496f4fc2ef6111569e542f8b65480ef14c1Chris Lattner MF.getMachineMemOperand(MachinePointerInfo( 66659db5496f4fc2ef6111569e542f8b65480ef14c1Chris Lattner PseudoSourceValue::getFixedStack(FI)), 66759db5496f4fc2ef6111569e542f8b65480ef14c1Chris Lattner MachineMemOperand::MOStore, 668249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MFI.getObjectSize(FI), 66931bc849123011b8eae6bb3c79876d9a3c26a6a1dJim Grosbach Align); 670334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 6710eb0c7401c34c0b4604f732ce54db995eead14e6Bob Wilson // tGPR is used sometimes in ARM instructions that need to avoid using 6726ccfc507dc1f7ad8c8964193a2407264ca644f0dJim Grosbach // certain registers. Just treat it as GPR here. Likewise, rGPR. 6736ccfc507dc1f7ad8c8964193a2407264ca644f0dJim Grosbach if (RC == ARM::tGPRRegisterClass || RC == ARM::tcGPRRegisterClass 6746ccfc507dc1f7ad8c8964193a2407264ca644f0dJim Grosbach || RC == ARM::rGPRRegisterClass) 6750eb0c7401c34c0b4604f732ce54db995eead14e6Bob Wilson RC = ARM::GPRRegisterClass; 6760eb0c7401c34c0b4604f732ce54db995eead14e6Bob Wilson 677ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson switch (RC->getID()) { 678ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson case ARM::GPRRegClassID: 6795732ca084aaa0cd26149e50dd4b487efff37fe41Evan Cheng AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::STR)) 680334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(SrcReg, getKillRegState(isKill)) 681249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov .addFrameIndex(FI).addReg(0).addImm(0).addMemOperand(MMO)); 682ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson break; 683ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson case ARM::SPRRegClassID: 684d31c5496d7e1580058b5c6fbc8fd537a641ea590Evan Cheng AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTRS)) 685d31c5496d7e1580058b5c6fbc8fd537a641ea590Evan Cheng .addReg(SrcReg, getKillRegState(isKill)) 686d31c5496d7e1580058b5c6fbc8fd537a641ea590Evan Cheng .addFrameIndex(FI).addImm(0).addMemOperand(MMO)); 687ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson break; 688ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson case ARM::DPRRegClassID: 689ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson case ARM::DPR_VFP2RegClassID: 690ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson case ARM::DPR_8RegClassID: 691e5165490b7ba24bb2f3043399e0d60e7f3bcf8a5Jim Grosbach AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTRD)) 692334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(SrcReg, getKillRegState(isKill)) 693249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov .addFrameIndex(FI).addImm(0).addMemOperand(MMO)); 694ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson break; 695ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson case ARM::QPRRegClassID: 696ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson case ARM::QPR_VFP2RegClassID: 697ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson case ARM::QPR_8RegClassID: 6980cfcf93c95af91e809ef740eb0ab368477226b40Jim Grosbach if (Align >= 16 && getRegisterInfo().needsStackRealignment(MF)) { 699168f382dc67e5940cabdb28dc933c4f91cdd3137Bob Wilson AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1q64Pseudo)) 700f967ca0eaf30325cabe3c1971bf0dba16cf1b027Bob Wilson .addFrameIndex(FI).addImm(16) 70169b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng .addReg(SrcReg, getKillRegState(isKill)) 70269b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng .addMemOperand(MMO)); 70331bc849123011b8eae6bb3c79876d9a3c26a6a1dJim Grosbach } else { 70469b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMQ)) 70569b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng .addReg(SrcReg, getKillRegState(isKill)) 70669b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng .addFrameIndex(FI) 707d4bfd54ec2947e73ab152c3c548e4dd4beb700baBob Wilson .addImm(ARM_AM::getAM4ModeImm(ARM_AM::ia)) 70869b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng .addMemOperand(MMO)); 70931bc849123011b8eae6bb3c79876d9a3c26a6a1dJim Grosbach } 710ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson break; 711ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson case ARM::QQPRRegClassID: 712ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson case ARM::QQPR_VFP2RegClassID: 713435d4991779d6a47cadff4ea670b490d8507d6c4Evan Cheng if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) { 71422c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng // FIXME: It's possible to only store part of the QQ register if the 71522c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng // spilled def has a sub-register index. 716168f382dc67e5940cabdb28dc933c4f91cdd3137Bob Wilson AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1d64QPseudo)) 717168f382dc67e5940cabdb28dc933c4f91cdd3137Bob Wilson .addFrameIndex(FI).addImm(16) 718168f382dc67e5940cabdb28dc933c4f91cdd3137Bob Wilson .addReg(SrcReg, getKillRegState(isKill)) 719168f382dc67e5940cabdb28dc933c4f91cdd3137Bob Wilson .addMemOperand(MMO)); 720435d4991779d6a47cadff4ea670b490d8507d6c4Evan Cheng } else { 721435d4991779d6a47cadff4ea670b490d8507d6c4Evan Cheng MachineInstrBuilder MIB = 722435d4991779d6a47cadff4ea670b490d8507d6c4Evan Cheng AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMD)) 723435d4991779d6a47cadff4ea670b490d8507d6c4Evan Cheng .addFrameIndex(FI) 724d4bfd54ec2947e73ab152c3c548e4dd4beb700baBob Wilson .addImm(ARM_AM::getAM4ModeImm(ARM_AM::ia))) 725435d4991779d6a47cadff4ea670b490d8507d6c4Evan Cheng .addMemOperand(MMO); 726558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI); 727558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI); 728558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI); 729558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI); 730435d4991779d6a47cadff4ea670b490d8507d6c4Evan Cheng } 731ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson break; 732ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson case ARM::QQQQPRRegClassID: { 73322c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng MachineInstrBuilder MIB = 73422c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMD)) 73522c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng .addFrameIndex(FI) 736d4bfd54ec2947e73ab152c3c548e4dd4beb700baBob Wilson .addImm(ARM_AM::getAM4ModeImm(ARM_AM::ia))) 73722c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng .addMemOperand(MMO); 738558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI); 739558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI); 740558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI); 741558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen MIB = AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI); 742558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen MIB = AddDReg(MIB, SrcReg, ARM::dsub_4, 0, TRI); 743558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen MIB = AddDReg(MIB, SrcReg, ARM::dsub_5, 0, TRI); 744558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen MIB = AddDReg(MIB, SrcReg, ARM::dsub_6, 0, TRI); 745558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen AddDReg(MIB, SrcReg, ARM::dsub_7, 0, TRI); 746ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson break; 747ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson } 748ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson default: 749ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson llvm_unreachable("Unknown regclass!"); 750334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 751334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 752334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 75334327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesenunsigned 75434327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund OlesenARMBaseInstrInfo::isStoreToStackSlot(const MachineInstr *MI, 75534327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen int &FrameIndex) const { 75634327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen switch (MI->getOpcode()) { 75734327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen default: break; 75834327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen case ARM::STR: 75934327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen case ARM::t2STRs: // FIXME: don't use t2STRs to access frame. 76034327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen if (MI->getOperand(1).isFI() && 76134327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen MI->getOperand(2).isReg() && 76234327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen MI->getOperand(3).isImm() && 76334327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen MI->getOperand(2).getReg() == 0 && 76434327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen MI->getOperand(3).getImm() == 0) { 76534327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen FrameIndex = MI->getOperand(1).getIndex(); 76634327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen return MI->getOperand(0).getReg(); 76734327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen } 76834327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen break; 76934327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen case ARM::t2STRi12: 77034327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen case ARM::tSpill: 77134327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen case ARM::VSTRD: 77234327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen case ARM::VSTRS: 77334327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen if (MI->getOperand(1).isFI() && 77434327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen MI->getOperand(2).isImm() && 77534327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen MI->getOperand(2).getImm() == 0) { 77634327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen FrameIndex = MI->getOperand(1).getIndex(); 77734327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen return MI->getOperand(0).getReg(); 77834327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen } 77934327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen break; 780d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen case ARM::VST1q64Pseudo: 781d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen if (MI->getOperand(0).isFI() && 782d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen MI->getOperand(2).getSubReg() == 0) { 783d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen FrameIndex = MI->getOperand(0).getIndex(); 784d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen return MI->getOperand(2).getReg(); 785d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen } 78631bbc51ac9245bc82c933c9db8358ca9bb558ac5Jakob Stoklund Olesen break; 787d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen case ARM::VSTMQ: 788d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen if (MI->getOperand(1).isFI() && 789d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen MI->getOperand(2).isImm() && 790d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen MI->getOperand(2).getImm() == ARM_AM::getAM4ModeImm(ARM_AM::ia) && 791d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen MI->getOperand(0).getSubReg() == 0) { 792d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen FrameIndex = MI->getOperand(1).getIndex(); 793d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen return MI->getOperand(0).getReg(); 794d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen } 795d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen break; 79634327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen } 79734327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen 79834327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen return 0; 79934327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen} 80034327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen 801334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinvoid ARMBaseInstrInfo:: 802334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinloadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 803334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned DestReg, int FI, 804746ad69e088176819981b4b2c5ac8dcd49f5e60eEvan Cheng const TargetRegisterClass *RC, 805746ad69e088176819981b4b2c5ac8dcd49f5e60eEvan Cheng const TargetRegisterInfo *TRI) const { 806c7f3ace20c325521c68335a1689645b43b06ddf0Chris Lattner DebugLoc DL; 807334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (I != MBB.end()) DL = I->getDebugLoc(); 808249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MachineFunction &MF = *MBB.getParent(); 809249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MachineFrameInfo &MFI = *MF.getFrameInfo(); 81031bc849123011b8eae6bb3c79876d9a3c26a6a1dJim Grosbach unsigned Align = MFI.getObjectAlignment(FI); 811249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MachineMemOperand *MMO = 81259db5496f4fc2ef6111569e542f8b65480ef14c1Chris Lattner MF.getMachineMemOperand( 81359db5496f4fc2ef6111569e542f8b65480ef14c1Chris Lattner MachinePointerInfo(PseudoSourceValue::getFixedStack(FI)), 81459db5496f4fc2ef6111569e542f8b65480ef14c1Chris Lattner MachineMemOperand::MOLoad, 815249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MFI.getObjectSize(FI), 81631bc849123011b8eae6bb3c79876d9a3c26a6a1dJim Grosbach Align); 817334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 8180eb0c7401c34c0b4604f732ce54db995eead14e6Bob Wilson // tGPR is used sometimes in ARM instructions that need to avoid using 8190eb0c7401c34c0b4604f732ce54db995eead14e6Bob Wilson // certain registers. Just treat it as GPR here. 8206ccfc507dc1f7ad8c8964193a2407264ca644f0dJim Grosbach if (RC == ARM::tGPRRegisterClass || RC == ARM::tcGPRRegisterClass 8216ccfc507dc1f7ad8c8964193a2407264ca644f0dJim Grosbach || RC == ARM::rGPRRegisterClass) 8220eb0c7401c34c0b4604f732ce54db995eead14e6Bob Wilson RC = ARM::GPRRegisterClass; 8230eb0c7401c34c0b4604f732ce54db995eead14e6Bob Wilson 824ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson switch (RC->getID()) { 825ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson case ARM::GPRRegClassID: 8265732ca084aaa0cd26149e50dd4b487efff37fe41Evan Cheng AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::LDR), DestReg) 827249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov .addFrameIndex(FI).addReg(0).addImm(0).addMemOperand(MMO)); 828ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson break; 829ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson case ARM::SPRRegClassID: 830d31c5496d7e1580058b5c6fbc8fd537a641ea590Evan Cheng AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRS), DestReg) 831d31c5496d7e1580058b5c6fbc8fd537a641ea590Evan Cheng .addFrameIndex(FI).addImm(0).addMemOperand(MMO)); 832ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson break; 833ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson case ARM::DPRRegClassID: 834ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson case ARM::DPR_VFP2RegClassID: 835ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson case ARM::DPR_8RegClassID: 836e5165490b7ba24bb2f3043399e0d60e7f3bcf8a5Jim Grosbach AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRD), DestReg) 837249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov .addFrameIndex(FI).addImm(0).addMemOperand(MMO)); 838ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson break; 839ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson case ARM::QPRRegClassID: 840ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson case ARM::QPR_VFP2RegClassID: 841ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson case ARM::QPR_8RegClassID: 8420cfcf93c95af91e809ef740eb0ab368477226b40Jim Grosbach if (Align >= 16 && getRegisterInfo().needsStackRealignment(MF)) { 843168f382dc67e5940cabdb28dc933c4f91cdd3137Bob Wilson AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1q64Pseudo), DestReg) 844f967ca0eaf30325cabe3c1971bf0dba16cf1b027Bob Wilson .addFrameIndex(FI).addImm(16) 84569b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng .addMemOperand(MMO)); 84631bc849123011b8eae6bb3c79876d9a3c26a6a1dJim Grosbach } else { 84769b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMQ), DestReg) 84869b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng .addFrameIndex(FI) 849d4bfd54ec2947e73ab152c3c548e4dd4beb700baBob Wilson .addImm(ARM_AM::getAM4ModeImm(ARM_AM::ia)) 85069b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng .addMemOperand(MMO)); 85131bc849123011b8eae6bb3c79876d9a3c26a6a1dJim Grosbach } 852ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson break; 853ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson case ARM::QQPRRegClassID: 854ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson case ARM::QQPR_VFP2RegClassID: 855435d4991779d6a47cadff4ea670b490d8507d6c4Evan Cheng if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) { 856168f382dc67e5940cabdb28dc933c4f91cdd3137Bob Wilson AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1d64QPseudo), DestReg) 857168f382dc67e5940cabdb28dc933c4f91cdd3137Bob Wilson .addFrameIndex(FI).addImm(16) 858168f382dc67e5940cabdb28dc933c4f91cdd3137Bob Wilson .addMemOperand(MMO)); 859435d4991779d6a47cadff4ea670b490d8507d6c4Evan Cheng } else { 860435d4991779d6a47cadff4ea670b490d8507d6c4Evan Cheng MachineInstrBuilder MIB = 861435d4991779d6a47cadff4ea670b490d8507d6c4Evan Cheng AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMD)) 862435d4991779d6a47cadff4ea670b490d8507d6c4Evan Cheng .addFrameIndex(FI) 863d4bfd54ec2947e73ab152c3c548e4dd4beb700baBob Wilson .addImm(ARM_AM::getAM4ModeImm(ARM_AM::ia))) 864435d4991779d6a47cadff4ea670b490d8507d6c4Evan Cheng .addMemOperand(MMO); 865558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::Define, TRI); 866558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::Define, TRI); 867558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::Define, TRI); 868558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen AddDReg(MIB, DestReg, ARM::dsub_3, RegState::Define, TRI); 869435d4991779d6a47cadff4ea670b490d8507d6c4Evan Cheng } 870ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson break; 871ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson case ARM::QQQQPRRegClassID: { 872ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson MachineInstrBuilder MIB = 873ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMD)) 874ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson .addFrameIndex(FI) 875d4bfd54ec2947e73ab152c3c548e4dd4beb700baBob Wilson .addImm(ARM_AM::getAM4ModeImm(ARM_AM::ia))) 876ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson .addMemOperand(MMO); 877ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::Define, TRI); 878ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::Define, TRI); 879ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::Define, TRI); 880ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::Define, TRI); 881ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson MIB = AddDReg(MIB, DestReg, ARM::dsub_4, RegState::Define, TRI); 882ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson MIB = AddDReg(MIB, DestReg, ARM::dsub_5, RegState::Define, TRI); 883ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson MIB = AddDReg(MIB, DestReg, ARM::dsub_6, RegState::Define, TRI); 884ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson AddDReg(MIB, DestReg, ARM::dsub_7, RegState::Define, TRI); 885ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson break; 886ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson } 887ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson default: 888ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson llvm_unreachable("Unknown regclass!"); 889334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 890334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 891334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 89234327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesenunsigned 89334327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund OlesenARMBaseInstrInfo::isLoadFromStackSlot(const MachineInstr *MI, 89434327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen int &FrameIndex) const { 89534327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen switch (MI->getOpcode()) { 89634327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen default: break; 89734327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen case ARM::LDR: 89834327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen case ARM::t2LDRs: // FIXME: don't use t2LDRs to access frame. 89934327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen if (MI->getOperand(1).isFI() && 90034327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen MI->getOperand(2).isReg() && 90134327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen MI->getOperand(3).isImm() && 90234327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen MI->getOperand(2).getReg() == 0 && 90334327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen MI->getOperand(3).getImm() == 0) { 90434327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen FrameIndex = MI->getOperand(1).getIndex(); 90534327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen return MI->getOperand(0).getReg(); 90634327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen } 90734327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen break; 90834327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen case ARM::t2LDRi12: 90934327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen case ARM::tRestore: 91034327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen case ARM::VLDRD: 91134327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen case ARM::VLDRS: 91234327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen if (MI->getOperand(1).isFI() && 91334327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen MI->getOperand(2).isImm() && 91434327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen MI->getOperand(2).getImm() == 0) { 91534327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen FrameIndex = MI->getOperand(1).getIndex(); 916d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen return MI->getOperand(0).getReg(); 917d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen } 918d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen break; 919d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen case ARM::VLD1q64Pseudo: 920d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen if (MI->getOperand(1).isFI() && 921d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen MI->getOperand(0).getSubReg() == 0) { 922d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen FrameIndex = MI->getOperand(1).getIndex(); 92306f264e504d75f0426eea55b9f9e36c780d8a4fcJakob Stoklund Olesen return MI->getOperand(0).getReg(); 92406f264e504d75f0426eea55b9f9e36c780d8a4fcJakob Stoklund Olesen } 92506f264e504d75f0426eea55b9f9e36c780d8a4fcJakob Stoklund Olesen break; 92606f264e504d75f0426eea55b9f9e36c780d8a4fcJakob Stoklund Olesen case ARM::VLDMQ: 92706f264e504d75f0426eea55b9f9e36c780d8a4fcJakob Stoklund Olesen if (MI->getOperand(1).isFI() && 92806f264e504d75f0426eea55b9f9e36c780d8a4fcJakob Stoklund Olesen MI->getOperand(2).isImm() && 92906f264e504d75f0426eea55b9f9e36c780d8a4fcJakob Stoklund Olesen MI->getOperand(2).getImm() == ARM_AM::getAM4ModeImm(ARM_AM::ia) && 93006f264e504d75f0426eea55b9f9e36c780d8a4fcJakob Stoklund Olesen MI->getOperand(0).getSubReg() == 0) { 93106f264e504d75f0426eea55b9f9e36c780d8a4fcJakob Stoklund Olesen FrameIndex = MI->getOperand(1).getIndex(); 93234327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen return MI->getOperand(0).getReg(); 93334327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen } 93434327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen break; 93534327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen } 93634327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen 93734327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen return 0; 93834327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen} 93934327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen 94062b50656ceb854eb0be265d63b2a1d46e7400d8aEvan ChengMachineInstr* 94162b50656ceb854eb0be265d63b2a1d46e7400d8aEvan ChengARMBaseInstrInfo::emitFrameIndexDebugValue(MachineFunction &MF, 9428601a3d4decff0a380e059b037dabf71075497d3Evan Cheng int FrameIx, uint64_t Offset, 94362b50656ceb854eb0be265d63b2a1d46e7400d8aEvan Cheng const MDNode *MDPtr, 94462b50656ceb854eb0be265d63b2a1d46e7400d8aEvan Cheng DebugLoc DL) const { 94562b50656ceb854eb0be265d63b2a1d46e7400d8aEvan Cheng MachineInstrBuilder MIB = BuildMI(MF, DL, get(ARM::DBG_VALUE)) 94662b50656ceb854eb0be265d63b2a1d46e7400d8aEvan Cheng .addFrameIndex(FrameIx).addImm(0).addImm(Offset).addMetadata(MDPtr); 94762b50656ceb854eb0be265d63b2a1d46e7400d8aEvan Cheng return &*MIB; 94862b50656ceb854eb0be265d63b2a1d46e7400d8aEvan Cheng} 94962b50656ceb854eb0be265d63b2a1d46e7400d8aEvan Cheng 95030ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen/// Create a copy of a const pool value. Update CPI to the new index and return 95130ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen/// the label UID. 95230ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesenstatic unsigned duplicateCPV(MachineFunction &MF, unsigned &CPI) { 95330ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen MachineConstantPool *MCP = MF.getConstantPool(); 95430ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 95530ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen 95630ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPI]; 95730ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen assert(MCPE.isMachineConstantPoolEntry() && 95830ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen "Expecting a machine constantpool entry!"); 95930ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen ARMConstantPoolValue *ACPV = 96030ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal); 96130ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen 96230ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen unsigned PCLabelId = AFI->createConstPoolEntryUId(); 96330ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen ARMConstantPoolValue *NewCPV = 0; 96451f5b67395780b8421f4aa6ee998ed51b23dae9dJim Grosbach // FIXME: The below assumes PIC relocation model and that the function 96551f5b67395780b8421f4aa6ee998ed51b23dae9dJim Grosbach // is Thumb mode (t1 or t2). PCAdjustment would be 8 for ARM mode PIC, and 96651f5b67395780b8421f4aa6ee998ed51b23dae9dJim Grosbach // zero for non-PIC in ARM or Thumb. The callers are all of thumb LDR 96751f5b67395780b8421f4aa6ee998ed51b23dae9dJim Grosbach // instructions, so that's probably OK, but is PIC always correct when 96851f5b67395780b8421f4aa6ee998ed51b23dae9dJim Grosbach // we get here? 96930ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen if (ACPV->isGlobalValue()) 97030ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen NewCPV = new ARMConstantPoolValue(ACPV->getGV(), PCLabelId, 97130ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen ARMCP::CPValue, 4); 97230ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen else if (ACPV->isExtSymbol()) 97330ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen NewCPV = new ARMConstantPoolValue(MF.getFunction()->getContext(), 97430ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen ACPV->getSymbol(), PCLabelId, 4); 97530ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen else if (ACPV->isBlockAddress()) 97630ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen NewCPV = new ARMConstantPoolValue(ACPV->getBlockAddress(), PCLabelId, 97730ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen ARMCP::CPBlockAddress, 4); 97851f5b67395780b8421f4aa6ee998ed51b23dae9dJim Grosbach else if (ACPV->isLSDA()) 97951f5b67395780b8421f4aa6ee998ed51b23dae9dJim Grosbach NewCPV = new ARMConstantPoolValue(MF.getFunction(), PCLabelId, 98051f5b67395780b8421f4aa6ee998ed51b23dae9dJim Grosbach ARMCP::CPLSDA, 4); 98130ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen else 98230ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen llvm_unreachable("Unexpected ARM constantpool value type!!"); 98330ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen CPI = MCP->getConstantPoolIndex(NewCPV, MCPE.getAlignment()); 98430ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen return PCLabelId; 98530ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen} 98630ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen 987fdc834046efd427d474e3b899ec69354c05071e0Evan Chengvoid ARMBaseInstrInfo:: 988fdc834046efd427d474e3b899ec69354c05071e0Evan ChengreMaterialize(MachineBasicBlock &MBB, 989fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng MachineBasicBlock::iterator I, 990fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng unsigned DestReg, unsigned SubIdx, 991d57cdd5683ea926e489067364fb7ffe5fd5d35eeEvan Cheng const MachineInstr *Orig, 9929edf7deb37f0f97664f279040fa15d89f32e23d9Jakob Stoklund Olesen const TargetRegisterInfo &TRI) const { 993fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng unsigned Opcode = Orig->getOpcode(); 994fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng switch (Opcode) { 995fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng default: { 996fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig); 9979edf7deb37f0f97664f279040fa15d89f32e23d9Jakob Stoklund Olesen MI->substituteRegister(Orig->getOperand(0).getReg(), DestReg, SubIdx, TRI); 998fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng MBB.insert(I, MI); 999fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng break; 1000fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng } 1001fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng case ARM::tLDRpci_pic: 1002fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng case ARM::t2LDRpci_pic: { 1003fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng MachineFunction &MF = *MBB.getParent(); 1004fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng unsigned CPI = Orig->getOperand(1).getIndex(); 100530ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen unsigned PCLabelId = duplicateCPV(MF, CPI); 1006fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng MachineInstrBuilder MIB = BuildMI(MBB, I, Orig->getDebugLoc(), get(Opcode), 1007fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng DestReg) 1008fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng .addConstantPoolIndex(CPI).addImm(PCLabelId); 1009fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng (*MIB).setMemRefs(Orig->memoperands_begin(), Orig->memoperands_end()); 1010fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng break; 1011fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng } 1012fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng } 1013fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng} 1014fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng 101530ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund OlesenMachineInstr * 101630ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund OlesenARMBaseInstrInfo::duplicate(MachineInstr *Orig, MachineFunction &MF) const { 101730ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen MachineInstr *MI = TargetInstrInfoImpl::duplicate(Orig, MF); 101830ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen switch(Orig->getOpcode()) { 101930ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen case ARM::tLDRpci_pic: 102030ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen case ARM::t2LDRpci_pic: { 102130ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen unsigned CPI = Orig->getOperand(1).getIndex(); 102230ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen unsigned PCLabelId = duplicateCPV(MF, CPI); 102330ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen Orig->getOperand(1).setIndex(CPI); 102430ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen Orig->getOperand(2).setImm(PCLabelId); 102530ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen break; 102630ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen } 102730ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen } 102830ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen return MI; 102930ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen} 103030ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen 1031506049f29f4f202a8e45feb916cc0264440a7f6dEvan Chengbool ARMBaseInstrInfo::produceSameValue(const MachineInstr *MI0, 1032506049f29f4f202a8e45feb916cc0264440a7f6dEvan Cheng const MachineInstr *MI1) const { 1033d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng int Opcode = MI0->getOpcode(); 10349b82425cb0105fd5704f6b9bcd5e7693b05b1759Evan Cheng if (Opcode == ARM::t2LDRpci || 10359b82425cb0105fd5704f6b9bcd5e7693b05b1759Evan Cheng Opcode == ARM::t2LDRpci_pic || 10369b82425cb0105fd5704f6b9bcd5e7693b05b1759Evan Cheng Opcode == ARM::tLDRpci || 10379b82425cb0105fd5704f6b9bcd5e7693b05b1759Evan Cheng Opcode == ARM::tLDRpci_pic) { 1038d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng if (MI1->getOpcode() != Opcode) 1039d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng return false; 1040d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng if (MI0->getNumOperands() != MI1->getNumOperands()) 1041d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng return false; 1042d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng 1043d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng const MachineOperand &MO0 = MI0->getOperand(1); 1044d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng const MachineOperand &MO1 = MI1->getOperand(1); 1045d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng if (MO0.getOffset() != MO1.getOffset()) 1046d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng return false; 1047d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng 1048d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng const MachineFunction *MF = MI0->getParent()->getParent(); 1049d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng const MachineConstantPool *MCP = MF->getConstantPool(); 1050d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng int CPI0 = MO0.getIndex(); 1051d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng int CPI1 = MO1.getIndex(); 1052d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng const MachineConstantPoolEntry &MCPE0 = MCP->getConstants()[CPI0]; 1053d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng const MachineConstantPoolEntry &MCPE1 = MCP->getConstants()[CPI1]; 1054d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng ARMConstantPoolValue *ACPV0 = 1055d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng static_cast<ARMConstantPoolValue*>(MCPE0.Val.MachineCPVal); 1056d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng ARMConstantPoolValue *ACPV1 = 1057d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng static_cast<ARMConstantPoolValue*>(MCPE1.Val.MachineCPVal); 1058d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng return ACPV0->hasSameValue(ACPV1); 1059d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng } 1060d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng 1061506049f29f4f202a8e45feb916cc0264440a7f6dEvan Cheng return MI0->isIdenticalTo(MI1, MachineInstr::IgnoreVRegDefs); 1062d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng} 1063d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng 10644b722108e2cf8e77157e0879a23789cd44829933Bill Wendling/// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to 10654b722108e2cf8e77157e0879a23789cd44829933Bill Wendling/// determine if two loads are loading from the same base address. It should 10664b722108e2cf8e77157e0879a23789cd44829933Bill Wendling/// only return true if the base pointers are the same and the only differences 10674b722108e2cf8e77157e0879a23789cd44829933Bill Wendling/// between the two addresses is the offset. It also returns the offsets by 10684b722108e2cf8e77157e0879a23789cd44829933Bill Wendling/// reference. 10694b722108e2cf8e77157e0879a23789cd44829933Bill Wendlingbool ARMBaseInstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, 10704b722108e2cf8e77157e0879a23789cd44829933Bill Wendling int64_t &Offset1, 10714b722108e2cf8e77157e0879a23789cd44829933Bill Wendling int64_t &Offset2) const { 10724b722108e2cf8e77157e0879a23789cd44829933Bill Wendling // Don't worry about Thumb: just ARM and Thumb2. 10734b722108e2cf8e77157e0879a23789cd44829933Bill Wendling if (Subtarget.isThumb1Only()) return false; 10744b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 10754b722108e2cf8e77157e0879a23789cd44829933Bill Wendling if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode()) 10764b722108e2cf8e77157e0879a23789cd44829933Bill Wendling return false; 10774b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 10784b722108e2cf8e77157e0879a23789cd44829933Bill Wendling switch (Load1->getMachineOpcode()) { 10794b722108e2cf8e77157e0879a23789cd44829933Bill Wendling default: 10804b722108e2cf8e77157e0879a23789cd44829933Bill Wendling return false; 10814b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::LDR: 10824b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::LDRB: 10834b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::LDRD: 10844b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::LDRH: 10854b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::LDRSB: 10864b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::LDRSH: 10874b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::VLDRD: 10884b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::VLDRS: 10894b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::t2LDRi8: 10904b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::t2LDRDi8: 10914b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::t2LDRSHi8: 10924b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::t2LDRi12: 10934b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::t2LDRSHi12: 10944b722108e2cf8e77157e0879a23789cd44829933Bill Wendling break; 10954b722108e2cf8e77157e0879a23789cd44829933Bill Wendling } 10964b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 10974b722108e2cf8e77157e0879a23789cd44829933Bill Wendling switch (Load2->getMachineOpcode()) { 10984b722108e2cf8e77157e0879a23789cd44829933Bill Wendling default: 10994b722108e2cf8e77157e0879a23789cd44829933Bill Wendling return false; 11004b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::LDR: 11014b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::LDRB: 11024b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::LDRD: 11034b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::LDRH: 11044b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::LDRSB: 11054b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::LDRSH: 11064b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::VLDRD: 11074b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::VLDRS: 11084b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::t2LDRi8: 11094b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::t2LDRDi8: 11104b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::t2LDRSHi8: 11114b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::t2LDRi12: 11124b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::t2LDRSHi12: 11134b722108e2cf8e77157e0879a23789cd44829933Bill Wendling break; 11144b722108e2cf8e77157e0879a23789cd44829933Bill Wendling } 11154b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 11164b722108e2cf8e77157e0879a23789cd44829933Bill Wendling // Check if base addresses and chain operands match. 11174b722108e2cf8e77157e0879a23789cd44829933Bill Wendling if (Load1->getOperand(0) != Load2->getOperand(0) || 11184b722108e2cf8e77157e0879a23789cd44829933Bill Wendling Load1->getOperand(4) != Load2->getOperand(4)) 11194b722108e2cf8e77157e0879a23789cd44829933Bill Wendling return false; 11204b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 11214b722108e2cf8e77157e0879a23789cd44829933Bill Wendling // Index should be Reg0. 11224b722108e2cf8e77157e0879a23789cd44829933Bill Wendling if (Load1->getOperand(3) != Load2->getOperand(3)) 11234b722108e2cf8e77157e0879a23789cd44829933Bill Wendling return false; 11244b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 11254b722108e2cf8e77157e0879a23789cd44829933Bill Wendling // Determine the offsets. 11264b722108e2cf8e77157e0879a23789cd44829933Bill Wendling if (isa<ConstantSDNode>(Load1->getOperand(1)) && 11274b722108e2cf8e77157e0879a23789cd44829933Bill Wendling isa<ConstantSDNode>(Load2->getOperand(1))) { 11284b722108e2cf8e77157e0879a23789cd44829933Bill Wendling Offset1 = cast<ConstantSDNode>(Load1->getOperand(1))->getSExtValue(); 11294b722108e2cf8e77157e0879a23789cd44829933Bill Wendling Offset2 = cast<ConstantSDNode>(Load2->getOperand(1))->getSExtValue(); 11304b722108e2cf8e77157e0879a23789cd44829933Bill Wendling return true; 11314b722108e2cf8e77157e0879a23789cd44829933Bill Wendling } 11324b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 11334b722108e2cf8e77157e0879a23789cd44829933Bill Wendling return false; 11344b722108e2cf8e77157e0879a23789cd44829933Bill Wendling} 11354b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 11364b722108e2cf8e77157e0879a23789cd44829933Bill Wendling/// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to 11374b722108e2cf8e77157e0879a23789cd44829933Bill Wendling/// determine (in conjuction with areLoadsFromSameBasePtr) if two loads should 11384b722108e2cf8e77157e0879a23789cd44829933Bill Wendling/// be scheduled togther. On some targets if two loads are loading from 11394b722108e2cf8e77157e0879a23789cd44829933Bill Wendling/// addresses in the same cache line, it's better if they are scheduled 11404b722108e2cf8e77157e0879a23789cd44829933Bill Wendling/// together. This function takes two integers that represent the load offsets 11414b722108e2cf8e77157e0879a23789cd44829933Bill Wendling/// from the common base address. It returns true if it decides it's desirable 11424b722108e2cf8e77157e0879a23789cd44829933Bill Wendling/// to schedule the two loads together. "NumLoads" is the number of loads that 11434b722108e2cf8e77157e0879a23789cd44829933Bill Wendling/// have already been scheduled after Load1. 11444b722108e2cf8e77157e0879a23789cd44829933Bill Wendlingbool ARMBaseInstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, 11454b722108e2cf8e77157e0879a23789cd44829933Bill Wendling int64_t Offset1, int64_t Offset2, 11464b722108e2cf8e77157e0879a23789cd44829933Bill Wendling unsigned NumLoads) const { 11474b722108e2cf8e77157e0879a23789cd44829933Bill Wendling // Don't worry about Thumb: just ARM and Thumb2. 11484b722108e2cf8e77157e0879a23789cd44829933Bill Wendling if (Subtarget.isThumb1Only()) return false; 11494b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 11504b722108e2cf8e77157e0879a23789cd44829933Bill Wendling assert(Offset2 > Offset1); 11514b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 11524b722108e2cf8e77157e0879a23789cd44829933Bill Wendling if ((Offset2 - Offset1) / 8 > 64) 11534b722108e2cf8e77157e0879a23789cd44829933Bill Wendling return false; 11544b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 11554b722108e2cf8e77157e0879a23789cd44829933Bill Wendling if (Load1->getMachineOpcode() != Load2->getMachineOpcode()) 11564b722108e2cf8e77157e0879a23789cd44829933Bill Wendling return false; // FIXME: overly conservative? 11574b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 11584b722108e2cf8e77157e0879a23789cd44829933Bill Wendling // Four loads in a row should be sufficient. 11594b722108e2cf8e77157e0879a23789cd44829933Bill Wendling if (NumLoads >= 3) 11604b722108e2cf8e77157e0879a23789cd44829933Bill Wendling return false; 11614b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 11624b722108e2cf8e77157e0879a23789cd44829933Bill Wendling return true; 11634b722108e2cf8e77157e0879a23789cd44829933Bill Wendling} 11644b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 116586050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Chengbool ARMBaseInstrInfo::isSchedulingBoundary(const MachineInstr *MI, 116686050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng const MachineBasicBlock *MBB, 116786050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng const MachineFunction &MF) const { 116857bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach // Debug info is never a scheduling boundary. It's necessary to be explicit 116957bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach // due to the special treatment of IT instructions below, otherwise a 117057bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach // dbg_value followed by an IT will result in the IT instruction being 117157bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach // considered a scheduling hazard, which is wrong. It should be the actual 117257bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach // instruction preceding the dbg_value instruction(s), just like it is 117357bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach // when debug info is not present. 117457bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach if (MI->isDebugValue()) 117557bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach return false; 117657bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach 117786050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // Terminators and labels can't be scheduled around. 117886050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng if (MI->getDesc().isTerminator() || MI->isLabel()) 117986050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng return true; 118086050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng 118186050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // Treat the start of the IT block as a scheduling boundary, but schedule 118286050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // t2IT along with all instructions following it. 118386050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // FIXME: This is a big hammer. But the alternative is to add all potential 118486050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // true and anti dependencies to IT block instructions as implicit operands 118586050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // to the t2IT instruction. The added compile time and complexity does not 118686050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // seem worth it. 118786050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng MachineBasicBlock::const_iterator I = MI; 118857bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach // Make sure to skip any dbg_value instructions 118957bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach while (++I != MBB->end() && I->isDebugValue()) 119057bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach ; 119157bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach if (I != MBB->end() && I->getOpcode() == ARM::t2IT) 119286050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng return true; 119386050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng 119486050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // Don't attempt to schedule around any instruction that defines 119586050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // a stack-oriented pointer, as it's unlikely to be profitable. This 119686050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // saves compile time, because it doesn't require every single 119786050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // stack slot reference to depend on the instruction that does the 119886050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // modification. 119986050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng if (MI->definesRegister(ARM::SP)) 120086050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng return true; 120186050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng 120286050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng return false; 120386050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng} 120486050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng 1205b20b85168c0e9819e6545f08281e9b83c82108f0Owen Andersonbool ARMBaseInstrInfo::isProfitableToIfCvt(MachineBasicBlock &MBB, 1206b20b85168c0e9819e6545f08281e9b83c82108f0Owen Anderson unsigned NumInstrs, 1207e3cc84a43d6a4bb6c50f58f3dd8e60e28787509eOwen Anderson float Probability, 1208e3cc84a43d6a4bb6c50f58f3dd8e60e28787509eOwen Anderson float Confidence) const { 120913151432edace19ee867a93b5c14573df4f75d24Evan Cheng if (!NumInstrs) 121013151432edace19ee867a93b5c14573df4f75d24Evan Cheng return false; 12112bbb76909126db5bed6bde84b16d94ab5de4d372Michael J. Spencer 1212b3c04ec956247a984b3113a01cfbfad91e5ca5b3Owen Anderson // Use old-style heuristics 121300d4f48168eae664e1f8fefc17a912c05b878513Owen Anderson if (OldARMIfCvt) { 1214b3c04ec956247a984b3113a01cfbfad91e5ca5b3Owen Anderson if (Subtarget.getCPUString() == "generic") 1215b3c04ec956247a984b3113a01cfbfad91e5ca5b3Owen Anderson // Generic (and overly aggressive) if-conversion limits for testing. 1216b3c04ec956247a984b3113a01cfbfad91e5ca5b3Owen Anderson return NumInstrs <= 10; 121700d4f48168eae664e1f8fefc17a912c05b878513Owen Anderson if (Subtarget.hasV7Ops()) 1218b3c04ec956247a984b3113a01cfbfad91e5ca5b3Owen Anderson return NumInstrs <= 3; 1219b3c04ec956247a984b3113a01cfbfad91e5ca5b3Owen Anderson return NumInstrs <= 2; 1220b3c04ec956247a984b3113a01cfbfad91e5ca5b3Owen Anderson } 12212bbb76909126db5bed6bde84b16d94ab5de4d372Michael J. Spencer 1222b20b85168c0e9819e6545f08281e9b83c82108f0Owen Anderson // Attempt to estimate the relative costs of predication versus branching. 1223b20b85168c0e9819e6545f08281e9b83c82108f0Owen Anderson float UnpredCost = Probability * NumInstrs; 1224654d5440a477b1f6c89b051107e041a331f78e27Owen Anderson UnpredCost += 1.0; // The branch itself 1225e3cc84a43d6a4bb6c50f58f3dd8e60e28787509eOwen Anderson UnpredCost += (1.0 - Confidence) * Subtarget.getMispredictionPenalty(); 12262bbb76909126db5bed6bde84b16d94ab5de4d372Michael J. Spencer 1227b20b85168c0e9819e6545f08281e9b83c82108f0Owen Anderson float PredCost = NumInstrs; 12282bbb76909126db5bed6bde84b16d94ab5de4d372Michael J. Spencer 1229b20b85168c0e9819e6545f08281e9b83c82108f0Owen Anderson return PredCost < UnpredCost; 12302bbb76909126db5bed6bde84b16d94ab5de4d372Michael J. Spencer 123113151432edace19ee867a93b5c14573df4f75d24Evan Cheng} 12322bbb76909126db5bed6bde84b16d94ab5de4d372Michael J. Spencer 123313151432edace19ee867a93b5c14573df4f75d24Evan Chengbool ARMBaseInstrInfo:: 123413151432edace19ee867a93b5c14573df4f75d24Evan ChengisProfitableToIfCvt(MachineBasicBlock &TMBB, unsigned NumT, 1235b20b85168c0e9819e6545f08281e9b83c82108f0Owen Anderson MachineBasicBlock &FMBB, unsigned NumF, 1236e3cc84a43d6a4bb6c50f58f3dd8e60e28787509eOwen Anderson float Probability, float Confidence) const { 1237b3c04ec956247a984b3113a01cfbfad91e5ca5b3Owen Anderson // Use old-style if-conversion heuristics 123800d4f48168eae664e1f8fefc17a912c05b878513Owen Anderson if (OldARMIfCvt) { 1239b3c04ec956247a984b3113a01cfbfad91e5ca5b3Owen Anderson return NumT && NumF && NumT <= 2 && NumF <= 2; 1240b3c04ec956247a984b3113a01cfbfad91e5ca5b3Owen Anderson } 1241b3c04ec956247a984b3113a01cfbfad91e5ca5b3Owen Anderson 1242b20b85168c0e9819e6545f08281e9b83c82108f0Owen Anderson if (!NumT || !NumF) 1243b20b85168c0e9819e6545f08281e9b83c82108f0Owen Anderson return false; 12442bbb76909126db5bed6bde84b16d94ab5de4d372Michael J. Spencer 1245b20b85168c0e9819e6545f08281e9b83c82108f0Owen Anderson // Attempt to estimate the relative costs of predication versus branching. 1246b20b85168c0e9819e6545f08281e9b83c82108f0Owen Anderson float UnpredCost = Probability * NumT + (1.0 - Probability) * NumF; 1247654d5440a477b1f6c89b051107e041a331f78e27Owen Anderson UnpredCost += 1.0; // The branch itself 1248e3cc84a43d6a4bb6c50f58f3dd8e60e28787509eOwen Anderson UnpredCost += (1.0 - Confidence) * Subtarget.getMispredictionPenalty(); 12492bbb76909126db5bed6bde84b16d94ab5de4d372Michael J. Spencer 1250b20b85168c0e9819e6545f08281e9b83c82108f0Owen Anderson float PredCost = NumT + NumF; 12512bbb76909126db5bed6bde84b16d94ab5de4d372Michael J. Spencer 1252b20b85168c0e9819e6545f08281e9b83c82108f0Owen Anderson return PredCost < UnpredCost; 125313151432edace19ee867a93b5c14573df4f75d24Evan Cheng} 125413151432edace19ee867a93b5c14573df4f75d24Evan Cheng 12558fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng/// getInstrPredicate - If instruction is predicated, returns its predicate 12568fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng/// condition, otherwise returns AL. It also returns the condition code 12578fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng/// register by reference. 12585adb66a646e2ec32265263739f5b01c3f50c176aEvan ChengARMCC::CondCodes 12595adb66a646e2ec32265263739f5b01c3f50c176aEvan Chengllvm::getInstrPredicate(const MachineInstr *MI, unsigned &PredReg) { 12608fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng int PIdx = MI->findFirstPredOperandIdx(); 12618fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng if (PIdx == -1) { 12628fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng PredReg = 0; 12638fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng return ARMCC::AL; 12648fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng } 12658fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng 12668fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng PredReg = MI->getOperand(PIdx+1).getReg(); 12678fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng return (ARMCC::CondCodes)MI->getOperand(PIdx).getImm(); 12688fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng} 12698fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng 12708fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng 12716495f63945e8dbde81f03a1dc2ab421993b9a495Evan Chengint llvm::getMatchingCondBranchOpcode(int Opc) { 12725ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng if (Opc == ARM::B) 12735ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng return ARM::Bcc; 12745ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng else if (Opc == ARM::tB) 12755ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng return ARM::tBcc; 12765ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng else if (Opc == ARM::t2B) 12775ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng return ARM::t2Bcc; 12785ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng 12795ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng llvm_unreachable("Unknown unconditional branch opcode!"); 12805ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng return 0; 12815ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng} 12825ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng 12836495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 12846495f63945e8dbde81f03a1dc2ab421993b9a495Evan Chengvoid llvm::emitARMRegPlusImmediate(MachineBasicBlock &MBB, 12856495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MachineBasicBlock::iterator &MBBI, DebugLoc dl, 12866495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned DestReg, unsigned BaseReg, int NumBytes, 12876495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ARMCC::CondCodes Pred, unsigned PredReg, 12886495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng const ARMBaseInstrInfo &TII) { 12896495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng bool isSub = NumBytes < 0; 12906495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (isSub) NumBytes = -NumBytes; 12916495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 12926495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng while (NumBytes) { 12936495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned RotAmt = ARM_AM::getSOImmValRotate(NumBytes); 12946495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned ThisVal = NumBytes & ARM_AM::rotr32(0xFF, RotAmt); 12956495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng assert(ThisVal && "Didn't extract field correctly"); 12966495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 12976495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // We will handle these bits from offset, clear them. 12986495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng NumBytes &= ~ThisVal; 12996495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 13006495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng assert(ARM_AM::getSOImmVal(ThisVal) != -1 && "Bit extraction didn't work?"); 13016495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 13026495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Build the new ADD / SUB. 13036495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned Opc = isSub ? ARM::SUBri : ARM::ADDri; 13046495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg) 13056495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng .addReg(BaseReg, RegState::Kill).addImm(ThisVal) 13066495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng .addImm((unsigned)Pred).addReg(PredReg).addReg(0); 13076495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng BaseReg = DestReg; 13086495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 13096495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng} 13106495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 1311cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Chengbool llvm::rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx, 1312cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng unsigned FrameReg, int &Offset, 1313cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng const ARMBaseInstrInfo &TII) { 13146495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned Opcode = MI.getOpcode(); 13156495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng const TargetInstrDesc &Desc = MI.getDesc(); 13166495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask); 13176495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng bool isSub = false; 1318764ab52dd80310a205c9888bf166d09dab858f90Jim Grosbach 13196495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Memory operands in inline assembly always use AddrMode2. 13206495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (Opcode == ARM::INLINEASM) 13216495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng AddrMode = ARMII::AddrMode2; 1322764ab52dd80310a205c9888bf166d09dab858f90Jim Grosbach 13236495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (Opcode == ARM::ADDri) { 13246495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng Offset += MI.getOperand(FrameRegIdx+1).getImm(); 13256495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (Offset == 0) { 13266495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Turn it into a move. 13276495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MI.setDesc(TII.get(ARM::MOVr)); 13286495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false); 13296495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MI.RemoveOperand(FrameRegIdx+1); 1330cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng Offset = 0; 1331cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng return true; 13326495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } else if (Offset < 0) { 13336495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng Offset = -Offset; 13346495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng isSub = true; 13356495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MI.setDesc(TII.get(ARM::SUBri)); 13366495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 13376495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 13386495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Common case: small offset, fits into instruction. 13396495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (ARM_AM::getSOImmVal(Offset) != -1) { 13406495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Replace the FrameIndex with sp / fp 13416495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false); 13426495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset); 1343cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng Offset = 0; 1344cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng return true; 13456495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 13466495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 13476495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Otherwise, pull as much of the immedidate into this ADDri/SUBri 13486495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // as possible. 13496495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned RotAmt = ARM_AM::getSOImmValRotate(Offset); 13506495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xFF, RotAmt); 13516495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 13526495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // We will handle these bits from offset, clear them. 13536495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng Offset &= ~ThisImmVal; 13546495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 13556495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Get the properly encoded SOImmVal field. 13566495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng assert(ARM_AM::getSOImmVal(ThisImmVal) != -1 && 13576495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng "Bit extraction didn't work?"); 13586495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MI.getOperand(FrameRegIdx+1).ChangeToImmediate(ThisImmVal); 13596495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } else { 13606495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned ImmIdx = 0; 13616495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng int InstrOffs = 0; 13626495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned NumBits = 0; 13636495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned Scale = 1; 13646495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng switch (AddrMode) { 13656495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng case ARMII::AddrMode2: { 13666495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ImmIdx = FrameRegIdx+2; 13676495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng InstrOffs = ARM_AM::getAM2Offset(MI.getOperand(ImmIdx).getImm()); 13686495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (ARM_AM::getAM2Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub) 13696495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng InstrOffs *= -1; 13706495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng NumBits = 12; 13716495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng break; 13726495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 13736495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng case ARMII::AddrMode3: { 13746495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ImmIdx = FrameRegIdx+2; 13756495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng InstrOffs = ARM_AM::getAM3Offset(MI.getOperand(ImmIdx).getImm()); 13766495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (ARM_AM::getAM3Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub) 13776495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng InstrOffs *= -1; 13786495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng NumBits = 8; 13796495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng break; 13806495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 1381baf31088f1472f48ea5ae81f0b93636cc44ca444Anton Korobeynikov case ARMII::AddrMode4: 1382a44321776ecd96fa0344335d3027758be3386e45Jim Grosbach case ARMII::AddrMode6: 1383cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng // Can't fold any offset even if it's zero. 1384cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng return false; 13856495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng case ARMII::AddrMode5: { 13866495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ImmIdx = FrameRegIdx+1; 13876495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng InstrOffs = ARM_AM::getAM5Offset(MI.getOperand(ImmIdx).getImm()); 13886495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (ARM_AM::getAM5Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub) 13896495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng InstrOffs *= -1; 13906495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng NumBits = 8; 13916495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng Scale = 4; 13926495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng break; 13936495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 13946495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng default: 13956495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng llvm_unreachable("Unsupported addressing mode!"); 13966495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng break; 13976495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 13986495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 13996495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng Offset += InstrOffs * Scale; 14006495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!"); 14016495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (Offset < 0) { 14026495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng Offset = -Offset; 14036495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng isSub = true; 14046495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 14056495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 14066495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Attempt to fold address comp. if opcode has offset bits 14076495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (NumBits > 0) { 14086495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Common case: small offset, fits into instruction. 14096495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MachineOperand &ImmOp = MI.getOperand(ImmIdx); 14106495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng int ImmedOffset = Offset / Scale; 14116495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned Mask = (1 << NumBits) - 1; 14126495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if ((unsigned)Offset <= Mask * Scale) { 14136495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Replace the FrameIndex with sp 14146495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false); 14156495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (isSub) 14166495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ImmedOffset |= 1 << NumBits; 14176495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ImmOp.ChangeToImmediate(ImmedOffset); 1418cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng Offset = 0; 1419cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng return true; 14206495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 1421764ab52dd80310a205c9888bf166d09dab858f90Jim Grosbach 14226495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Otherwise, it didn't fit. Pull in what we can to simplify the immed. 14236495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ImmedOffset = ImmedOffset & Mask; 14246495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (isSub) 14256495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ImmedOffset |= 1 << NumBits; 14266495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ImmOp.ChangeToImmediate(ImmedOffset); 14276495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng Offset &= ~(Mask*Scale); 14286495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 14296495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 14306495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 1431cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng Offset = (isSub) ? -Offset : Offset; 1432cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng return Offset == 0; 14336495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng} 1434e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling 1435e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendlingbool ARMBaseInstrInfo:: 1436a99c3e9acd95f5fbfb611e3f807240cd74001142Eric ChristopherAnalyzeCompare(const MachineInstr *MI, unsigned &SrcReg, int &CmpMask, 1437a99c3e9acd95f5fbfb611e3f807240cd74001142Eric Christopher int &CmpValue) const { 1438e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling switch (MI->getOpcode()) { 1439e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling default: break; 144038ae997e63e3e1bb2c8679e01ea74cf8fd0be893Bill Wendling case ARM::CMPri: 144138ae997e63e3e1bb2c8679e01ea74cf8fd0be893Bill Wendling case ARM::CMPzri: 1442e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling case ARM::t2CMPri: 1443e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling case ARM::t2CMPzri: 1444e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling SrcReg = MI->getOperand(0).getReg(); 144504ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif CmpMask = ~0; 1446e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling CmpValue = MI->getOperand(1).getImm(); 1447e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling return true; 144804ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif case ARM::TSTri: 144904ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif case ARM::t2TSTri: 145004ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif SrcReg = MI->getOperand(0).getReg(); 145104ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif CmpMask = MI->getOperand(1).getImm(); 145204ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif CmpValue = 0; 145304ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif return true; 145404ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif } 145504ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif 145604ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif return false; 145704ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif} 145804ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif 145905642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif/// isSuitableForMask - Identify a suitable 'and' instruction that 146005642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif/// operates on the given source register and applies the same mask 146105642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif/// as a 'tst' instruction. Provide a limited look-through for copies. 146205642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif/// When successful, MI will hold the found instruction. 146305642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greifstatic bool isSuitableForMask(MachineInstr *&MI, unsigned SrcReg, 14648ff9bb189ce188452e6cae6ed65cb2745814126cGabor Greif int CmpMask, bool CommonUse) { 146505642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif switch (MI->getOpcode()) { 146604ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif case ARM::ANDri: 146704ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif case ARM::t2ANDri: 146805642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif if (CmpMask != MI->getOperand(2).getImm()) 14698ff9bb189ce188452e6cae6ed65cb2745814126cGabor Greif return false; 147005642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif if (SrcReg == MI->getOperand(CommonUse ? 1 : 0).getReg()) 147104ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif return true; 147204ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif break; 147305642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif case ARM::COPY: { 147405642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif // Walk down one instruction which is potentially an 'and'. 147505642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif const MachineInstr &Copy = *MI; 1476f000a7a212590bfd45e23c05bff5e1b683d25dd6Michael J. Spencer MachineBasicBlock::iterator AND( 1477f000a7a212590bfd45e23c05bff5e1b683d25dd6Michael J. Spencer llvm::next(MachineBasicBlock::iterator(MI))); 147805642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif if (AND == MI->getParent()->end()) return false; 147905642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif MI = AND; 148005642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif return isSuitableForMask(MI, Copy.getOperand(0).getReg(), 148105642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif CmpMask, true); 148205642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif } 1483e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling } 1484e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling 1485e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling return false; 1486e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling} 1487e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling 1488a65568676d0d9d53dd4aae8f1c58271bb4cfff10Bill Wendling/// OptimizeCompareInstr - Convert the instruction supplying the argument to the 148992ad57f066e9f256e4e3d72febf152e68caa80c7Bill Wendling/// comparison into one that sets the zero bit in the flags register. Update the 149092ad57f066e9f256e4e3d72febf152e68caa80c7Bill Wendling/// iterator *only* if a transformation took place. 1491e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendlingbool ARMBaseInstrInfo:: 149204ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor GreifOptimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, int CmpMask, 149304ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif int CmpValue, MachineBasicBlock::iterator &MII) const { 14943665661a5708c8adc2727be38b56d1d87ddeb661Bill Wendling if (CmpValue != 0) 149592ad57f066e9f256e4e3d72febf152e68caa80c7Bill Wendling return false; 149692ad57f066e9f256e4e3d72febf152e68caa80c7Bill Wendling 149792ad57f066e9f256e4e3d72febf152e68caa80c7Bill Wendling MachineRegisterInfo &MRI = CmpInstr->getParent()->getParent()->getRegInfo(); 149892ad57f066e9f256e4e3d72febf152e68caa80c7Bill Wendling MachineRegisterInfo::def_iterator DI = MRI.def_begin(SrcReg); 149992ad57f066e9f256e4e3d72febf152e68caa80c7Bill Wendling if (llvm::next(DI) != MRI.def_end()) 150092ad57f066e9f256e4e3d72febf152e68caa80c7Bill Wendling // Only support one definition. 150192ad57f066e9f256e4e3d72febf152e68caa80c7Bill Wendling return false; 150292ad57f066e9f256e4e3d72febf152e68caa80c7Bill Wendling 150392ad57f066e9f256e4e3d72febf152e68caa80c7Bill Wendling MachineInstr *MI = &*DI; 150492ad57f066e9f256e4e3d72febf152e68caa80c7Bill Wendling 150504ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif // Masked compares sometimes use the same register as the corresponding 'and'. 150604ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif if (CmpMask != ~0) { 150705642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif if (!isSuitableForMask(MI, SrcReg, CmpMask, false)) { 150804ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif MI = 0; 150904ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif for (MachineRegisterInfo::use_iterator UI = MRI.use_begin(SrcReg), 151004ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif UE = MRI.use_end(); UI != UE; ++UI) { 151104ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif if (UI->getParent() != CmpInstr->getParent()) continue; 151205642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif MachineInstr *PotentialAND = &*UI; 15138ff9bb189ce188452e6cae6ed65cb2745814126cGabor Greif if (!isSuitableForMask(PotentialAND, SrcReg, CmpMask, true)) 151404ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif continue; 151505642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif MI = PotentialAND; 151604ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif break; 151704ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif } 151804ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif if (!MI) return false; 151904ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif } 152004ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif } 152104ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif 1522e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling // Conservatively refuse to convert an instruction which isn't in the same BB 1523e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling // as the comparison. 1524e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling if (MI->getParent() != CmpInstr->getParent()) 1525e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling return false; 1526e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling 1527e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling // Check that CPSR isn't set between the comparison instruction and the one we 1528e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling // want to change. 1529691e64a54ce899409abe7c131d15ed75e3c1fef5Evan Cheng MachineBasicBlock::const_iterator I = CmpInstr, E = MI, 1530691e64a54ce899409abe7c131d15ed75e3c1fef5Evan Cheng B = MI->getParent()->begin(); 1531e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling --I; 1532e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling for (; I != E; --I) { 1533e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling const MachineInstr &Instr = *I; 1534e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling 1535e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling for (unsigned IO = 0, EO = Instr.getNumOperands(); IO != EO; ++IO) { 1536e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling const MachineOperand &MO = Instr.getOperand(IO); 153775486dbf4e9611f2070bf13b874f78a5587ed7ffBill Wendling if (!MO.isReg() || !MO.isDef()) continue; 1538e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling 1539e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling // This instruction modifies CPSR before the one we want to change. We 1540e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling // can't do this transformation. 1541e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling if (MO.getReg() == ARM::CPSR) 1542e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling return false; 1543e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling } 1544691e64a54ce899409abe7c131d15ed75e3c1fef5Evan Cheng 1545691e64a54ce899409abe7c131d15ed75e3c1fef5Evan Cheng if (I == B) 1546691e64a54ce899409abe7c131d15ed75e3c1fef5Evan Cheng // The 'and' is below the comparison instruction. 1547691e64a54ce899409abe7c131d15ed75e3c1fef5Evan Cheng return false; 1548e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling } 1549e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling 1550e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling // Set the "zero" bit in CPSR. 1551e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling switch (MI->getOpcode()) { 1552e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling default: break; 155338ae997e63e3e1bb2c8679e01ea74cf8fd0be893Bill Wendling case ARM::ADDri: 15543a951829fef6a2cfca87611e94cf48e0136f81d5Bob Wilson case ARM::ANDri: 15553a951829fef6a2cfca87611e94cf48e0136f81d5Bob Wilson case ARM::t2ANDri: 155638ae997e63e3e1bb2c8679e01ea74cf8fd0be893Bill Wendling case ARM::SUBri: 155738ae997e63e3e1bb2c8679e01ea74cf8fd0be893Bill Wendling case ARM::t2ADDri: 1558ad422718f9b3224234f52e84d28d8a57a4e89987Bill Wendling case ARM::t2SUBri: 1559e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling MI->RemoveOperand(5); 1560ad422718f9b3224234f52e84d28d8a57a4e89987Bill Wendling MachineInstrBuilder(MI) 1561ad422718f9b3224234f52e84d28d8a57a4e89987Bill Wendling .addReg(ARM::CPSR, RegState::Define | RegState::Implicit); 1562220e240bdf3235252c2a1fc8fcc5d4b8e8117918Bill Wendling MII = llvm::next(MachineBasicBlock::iterator(CmpInstr)); 1563e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling CmpInstr->eraseFromParent(); 1564e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling return true; 1565e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling } 1566e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling 1567e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling return false; 1568e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling} 15695f54ce347368105260be2cec497b6a4199dc5789Evan Cheng 15705f54ce347368105260be2cec497b6a4199dc5789Evan Chengunsigned 15715f54ce347368105260be2cec497b6a4199dc5789Evan ChengARMBaseInstrInfo::getNumMicroOps(const MachineInstr *MI, 15723ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng const InstrItineraryData *ItinData) const { 15733ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng if (!ItinData || ItinData->isEmpty()) 15745f54ce347368105260be2cec497b6a4199dc5789Evan Cheng return 1; 15755f54ce347368105260be2cec497b6a4199dc5789Evan Cheng 15765f54ce347368105260be2cec497b6a4199dc5789Evan Cheng const TargetInstrDesc &Desc = MI->getDesc(); 15775f54ce347368105260be2cec497b6a4199dc5789Evan Cheng unsigned Class = Desc.getSchedClass(); 1578064312de8641043b084603aa9a6b409bc794eed2Bob Wilson unsigned UOps = ItinData->Itineraries[Class].NumMicroOps; 15795f54ce347368105260be2cec497b6a4199dc5789Evan Cheng if (UOps) 15805f54ce347368105260be2cec497b6a4199dc5789Evan Cheng return UOps; 15815f54ce347368105260be2cec497b6a4199dc5789Evan Cheng 15825f54ce347368105260be2cec497b6a4199dc5789Evan Cheng unsigned Opc = MI->getOpcode(); 15835f54ce347368105260be2cec497b6a4199dc5789Evan Cheng switch (Opc) { 15845f54ce347368105260be2cec497b6a4199dc5789Evan Cheng default: 15855f54ce347368105260be2cec497b6a4199dc5789Evan Cheng llvm_unreachable("Unexpected multi-uops instruction!"); 15865f54ce347368105260be2cec497b6a4199dc5789Evan Cheng break; 15873ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng case ARM::VLDMQ: 15885f54ce347368105260be2cec497b6a4199dc5789Evan Cheng case ARM::VSTMQ: 15895f54ce347368105260be2cec497b6a4199dc5789Evan Cheng return 2; 15905f54ce347368105260be2cec497b6a4199dc5789Evan Cheng 15915f54ce347368105260be2cec497b6a4199dc5789Evan Cheng // The number of uOps for load / store multiple are determined by the number 15925f54ce347368105260be2cec497b6a4199dc5789Evan Cheng // registers. 15933ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng // On Cortex-A8, each pair of register loads / stores can be scheduled on the 15943ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng // same cycle. The scheduling for the first load / store must be done 15953ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng // separately by assuming the the address is not 64-bit aligned. 15963ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng // On Cortex-A9, the formula is simply (#reg / 2) + (#reg % 2). If the address 15973ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng // is not 64-bit aligned, then AGU would take an extra cycle. 15983ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng // For VFP / NEON load / store multiple, the formula is 15995f54ce347368105260be2cec497b6a4199dc5789Evan Cheng // (#reg / 2) + (#reg % 2) + 1. 16005f54ce347368105260be2cec497b6a4199dc5789Evan Cheng case ARM::VLDMD: 16015f54ce347368105260be2cec497b6a4199dc5789Evan Cheng case ARM::VLDMS: 16025f54ce347368105260be2cec497b6a4199dc5789Evan Cheng case ARM::VLDMD_UPD: 16035f54ce347368105260be2cec497b6a4199dc5789Evan Cheng case ARM::VLDMS_UPD: 16045f54ce347368105260be2cec497b6a4199dc5789Evan Cheng case ARM::VSTMD: 16055f54ce347368105260be2cec497b6a4199dc5789Evan Cheng case ARM::VSTMS: 16065f54ce347368105260be2cec497b6a4199dc5789Evan Cheng case ARM::VSTMD_UPD: 16075f54ce347368105260be2cec497b6a4199dc5789Evan Cheng case ARM::VSTMS_UPD: { 16085f54ce347368105260be2cec497b6a4199dc5789Evan Cheng unsigned NumRegs = MI->getNumOperands() - Desc.getNumOperands(); 16095f54ce347368105260be2cec497b6a4199dc5789Evan Cheng return (NumRegs / 2) + (NumRegs % 2) + 1; 16105f54ce347368105260be2cec497b6a4199dc5789Evan Cheng } 16115f54ce347368105260be2cec497b6a4199dc5789Evan Cheng case ARM::LDM_RET: 16125f54ce347368105260be2cec497b6a4199dc5789Evan Cheng case ARM::LDM: 16135f54ce347368105260be2cec497b6a4199dc5789Evan Cheng case ARM::LDM_UPD: 16145f54ce347368105260be2cec497b6a4199dc5789Evan Cheng case ARM::STM: 16155f54ce347368105260be2cec497b6a4199dc5789Evan Cheng case ARM::STM_UPD: 16165f54ce347368105260be2cec497b6a4199dc5789Evan Cheng case ARM::tLDM: 16175f54ce347368105260be2cec497b6a4199dc5789Evan Cheng case ARM::tLDM_UPD: 16185f54ce347368105260be2cec497b6a4199dc5789Evan Cheng case ARM::tSTM_UPD: 16195f54ce347368105260be2cec497b6a4199dc5789Evan Cheng case ARM::tPOP_RET: 16205f54ce347368105260be2cec497b6a4199dc5789Evan Cheng case ARM::tPOP: 16215f54ce347368105260be2cec497b6a4199dc5789Evan Cheng case ARM::tPUSH: 16225f54ce347368105260be2cec497b6a4199dc5789Evan Cheng case ARM::t2LDM_RET: 16235f54ce347368105260be2cec497b6a4199dc5789Evan Cheng case ARM::t2LDM: 16245f54ce347368105260be2cec497b6a4199dc5789Evan Cheng case ARM::t2LDM_UPD: 16255f54ce347368105260be2cec497b6a4199dc5789Evan Cheng case ARM::t2STM: 16265f54ce347368105260be2cec497b6a4199dc5789Evan Cheng case ARM::t2STM_UPD: { 16273ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng unsigned NumRegs = MI->getNumOperands() - Desc.getNumOperands() + 1; 16283ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng if (Subtarget.isCortexA8()) { 16293ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng // 4 registers would be issued: 1, 2, 1. 16303ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng // 5 registers would be issued: 1, 2, 2. 16313ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng return 1 + (NumRegs / 2); 16323ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng } else if (Subtarget.isCortexA9()) { 16333ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng UOps = (NumRegs / 2); 16343ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng // If there are odd number of registers or if it's not 64-bit aligned, 16353ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng // then it takes an extra AGU (Address Generation Unit) cycle. 16363ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng if ((NumRegs % 2) || 16373ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng !MI->hasOneMemOperand() || 16383ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng (*MI->memoperands_begin())->getAlignment() < 8) 16393ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng ++UOps; 16403ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng return UOps; 16413ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng } else { 16423ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng // Assume the worst. 16433ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng return NumRegs; 16442bbb76909126db5bed6bde84b16d94ab5de4d372Michael J. Spencer } 16455f54ce347368105260be2cec497b6a4199dc5789Evan Cheng } 16465f54ce347368105260be2cec497b6a4199dc5789Evan Cheng } 16475f54ce347368105260be2cec497b6a4199dc5789Evan Cheng} 1648a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng 1649a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Chengint 1650344d9db97062736cd66da6c07baa9108b6cfa419Evan ChengARMBaseInstrInfo::getVLDMDefCycle(const InstrItineraryData *ItinData, 1651344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng const TargetInstrDesc &DefTID, 1652344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng unsigned DefClass, 1653344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng unsigned DefIdx, unsigned DefAlign) const { 1654344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng int RegNo = (int)(DefIdx+1) - DefTID.getNumOperands() + 1; 1655344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng if (RegNo <= 0) 1656344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // Def is the address writeback. 1657344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng return ItinData->getOperandCycle(DefClass, DefIdx); 1658344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng 1659344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng int DefCycle; 1660344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng if (Subtarget.isCortexA8()) { 1661344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // (regno / 2) + (regno % 2) + 1 1662344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng DefCycle = RegNo / 2 + 1; 1663344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng if (RegNo % 2) 1664344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng ++DefCycle; 1665344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng } else if (Subtarget.isCortexA9()) { 1666344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng DefCycle = RegNo; 1667344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng bool isSLoad = false; 1668344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng switch (DefTID.getOpcode()) { 1669344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng default: break; 1670344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng case ARM::VLDMS: 1671344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng case ARM::VLDMS_UPD: 1672344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng isSLoad = true; 1673344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng break; 1674344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng } 1675344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // If there are odd number of 'S' registers or if it's not 64-bit aligned, 1676344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // then it takes an extra cycle. 1677344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng if ((isSLoad && (RegNo % 2)) || DefAlign < 8) 1678344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng ++DefCycle; 1679344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng } else { 1680344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // Assume the worst. 1681344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng DefCycle = RegNo + 2; 1682344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng } 1683344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng 1684344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng return DefCycle; 1685344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng} 1686344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng 1687344d9db97062736cd66da6c07baa9108b6cfa419Evan Chengint 1688344d9db97062736cd66da6c07baa9108b6cfa419Evan ChengARMBaseInstrInfo::getLDMDefCycle(const InstrItineraryData *ItinData, 1689344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng const TargetInstrDesc &DefTID, 1690344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng unsigned DefClass, 1691344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng unsigned DefIdx, unsigned DefAlign) const { 1692344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng int RegNo = (int)(DefIdx+1) - DefTID.getNumOperands() + 1; 1693344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng if (RegNo <= 0) 1694344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // Def is the address writeback. 1695344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng return ItinData->getOperandCycle(DefClass, DefIdx); 1696344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng 1697344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng int DefCycle; 1698344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng if (Subtarget.isCortexA8()) { 1699344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // 4 registers would be issued: 1, 2, 1. 1700344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // 5 registers would be issued: 1, 2, 2. 1701344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng DefCycle = RegNo / 2; 1702344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng if (DefCycle < 1) 1703344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng DefCycle = 1; 1704344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // Result latency is issue cycle + 2: E2. 1705344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng DefCycle += 2; 1706344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng } else if (Subtarget.isCortexA9()) { 1707344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng DefCycle = (RegNo / 2); 1708344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // If there are odd number of registers or if it's not 64-bit aligned, 1709344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // then it takes an extra AGU (Address Generation Unit) cycle. 1710344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng if ((RegNo % 2) || DefAlign < 8) 1711344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng ++DefCycle; 1712344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // Result latency is AGU cycles + 2. 1713344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng DefCycle += 2; 1714344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng } else { 1715344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // Assume the worst. 1716344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng DefCycle = RegNo + 2; 1717344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng } 1718344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng 1719344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng return DefCycle; 1720344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng} 1721344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng 1722344d9db97062736cd66da6c07baa9108b6cfa419Evan Chengint 1723344d9db97062736cd66da6c07baa9108b6cfa419Evan ChengARMBaseInstrInfo::getVSTMUseCycle(const InstrItineraryData *ItinData, 1724344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng const TargetInstrDesc &UseTID, 1725344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng unsigned UseClass, 1726344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng unsigned UseIdx, unsigned UseAlign) const { 1727344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng int RegNo = (int)(UseIdx+1) - UseTID.getNumOperands() + 1; 1728344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng if (RegNo <= 0) 1729344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng return ItinData->getOperandCycle(UseClass, UseIdx); 1730344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng 1731344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng int UseCycle; 1732344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng if (Subtarget.isCortexA8()) { 1733344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // (regno / 2) + (regno % 2) + 1 1734344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng UseCycle = RegNo / 2 + 1; 1735344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng if (RegNo % 2) 1736344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng ++UseCycle; 1737344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng } else if (Subtarget.isCortexA9()) { 1738344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng UseCycle = RegNo; 1739344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng bool isSStore = false; 1740344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng switch (UseTID.getOpcode()) { 1741344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng default: break; 1742344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng case ARM::VSTMS: 1743344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng case ARM::VSTMS_UPD: 1744344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng isSStore = true; 1745344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng break; 1746344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng } 1747344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // If there are odd number of 'S' registers or if it's not 64-bit aligned, 1748344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // then it takes an extra cycle. 1749344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng if ((isSStore && (RegNo % 2)) || UseAlign < 8) 1750344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng ++UseCycle; 1751344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng } else { 1752344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // Assume the worst. 1753344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng UseCycle = RegNo + 2; 1754344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng } 1755344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng 1756344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng return UseCycle; 1757344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng} 1758344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng 1759344d9db97062736cd66da6c07baa9108b6cfa419Evan Chengint 1760344d9db97062736cd66da6c07baa9108b6cfa419Evan ChengARMBaseInstrInfo::getSTMUseCycle(const InstrItineraryData *ItinData, 1761344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng const TargetInstrDesc &UseTID, 1762344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng unsigned UseClass, 1763344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng unsigned UseIdx, unsigned UseAlign) const { 1764344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng int RegNo = (int)(UseIdx+1) - UseTID.getNumOperands() + 1; 1765344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng if (RegNo <= 0) 1766344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng return ItinData->getOperandCycle(UseClass, UseIdx); 1767344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng 1768344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng int UseCycle; 1769344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng if (Subtarget.isCortexA8()) { 1770344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng UseCycle = RegNo / 2; 1771344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng if (UseCycle < 2) 1772344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng UseCycle = 2; 1773344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // Read in E3. 1774344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng UseCycle += 2; 1775344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng } else if (Subtarget.isCortexA9()) { 1776344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng UseCycle = (RegNo / 2); 1777344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // If there are odd number of registers or if it's not 64-bit aligned, 1778344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // then it takes an extra AGU (Address Generation Unit) cycle. 1779344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng if ((RegNo % 2) || UseAlign < 8) 1780344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng ++UseCycle; 1781344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng } else { 1782344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // Assume the worst. 1783344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng UseCycle = 1; 1784344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng } 1785344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng return UseCycle; 1786344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng} 1787344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng 1788344d9db97062736cd66da6c07baa9108b6cfa419Evan Chengint 1789a0792de66c8364d47b0a688c7f408efb7b10f31bEvan ChengARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData, 1790a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng const TargetInstrDesc &DefTID, 1791a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng unsigned DefIdx, unsigned DefAlign, 1792a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng const TargetInstrDesc &UseTID, 1793a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng unsigned UseIdx, unsigned UseAlign) const { 1794a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng unsigned DefClass = DefTID.getSchedClass(); 1795a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng unsigned UseClass = UseTID.getSchedClass(); 1796a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng 1797a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng if (DefIdx < DefTID.getNumDefs() && UseIdx < UseTID.getNumOperands()) 1798a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx); 1799a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng 1800a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng // This may be a def / use of a variable_ops instruction, the operand 1801a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng // latency might be determinable dynamically. Let the target try to 1802a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng // figure it out. 1803a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng bool LdmBypass = false; 1804a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng int DefCycle = -1; 1805a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng switch (DefTID.getOpcode()) { 1806a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng default: 1807a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng DefCycle = ItinData->getOperandCycle(DefClass, DefIdx); 1808a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng break; 18095a50ceeaea980962c1982ad535226c7ab06c971cEvan Cheng case ARM::VLDMD: 18105a50ceeaea980962c1982ad535226c7ab06c971cEvan Cheng case ARM::VLDMS: 18115a50ceeaea980962c1982ad535226c7ab06c971cEvan Cheng case ARM::VLDMD_UPD: 18125a50ceeaea980962c1982ad535226c7ab06c971cEvan Cheng case ARM::VLDMS_UPD: { 1813344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng DefCycle = getVLDMDefCycle(ItinData, DefTID, DefClass, DefIdx, DefAlign); 18145a50ceeaea980962c1982ad535226c7ab06c971cEvan Cheng break; 18155a50ceeaea980962c1982ad535226c7ab06c971cEvan Cheng } 1816a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng case ARM::LDM_RET: 1817a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng case ARM::LDM: 1818a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng case ARM::LDM_UPD: 1819a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng case ARM::tLDM: 1820a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng case ARM::tLDM_UPD: 1821a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng case ARM::tPUSH: 1822a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng case ARM::t2LDM_RET: 1823a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng case ARM::t2LDM: 1824a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng case ARM::t2LDM_UPD: { 1825a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng LdmBypass = 1; 1826344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng DefCycle = getLDMDefCycle(ItinData, DefTID, DefClass, DefIdx, DefAlign); 1827344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng break; 1828a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng } 1829a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng } 1830a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng 1831a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng if (DefCycle == -1) 1832a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng // We can't seem to determine the result latency of the def, assume it's 2. 1833a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng DefCycle = 2; 1834a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng 1835a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng int UseCycle = -1; 1836a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng switch (UseTID.getOpcode()) { 1837a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng default: 1838a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng UseCycle = ItinData->getOperandCycle(UseClass, UseIdx); 1839a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng break; 18405a50ceeaea980962c1982ad535226c7ab06c971cEvan Cheng case ARM::VSTMD: 18415a50ceeaea980962c1982ad535226c7ab06c971cEvan Cheng case ARM::VSTMS: 18425a50ceeaea980962c1982ad535226c7ab06c971cEvan Cheng case ARM::VSTMD_UPD: 18435a50ceeaea980962c1982ad535226c7ab06c971cEvan Cheng case ARM::VSTMS_UPD: { 1844344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng UseCycle = getVSTMUseCycle(ItinData, UseTID, UseClass, UseIdx, UseAlign); 18455a50ceeaea980962c1982ad535226c7ab06c971cEvan Cheng break; 18465a50ceeaea980962c1982ad535226c7ab06c971cEvan Cheng } 1847a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng case ARM::STM: 1848a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng case ARM::STM_UPD: 1849a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng case ARM::tSTM_UPD: 1850a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng case ARM::tPOP_RET: 1851a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng case ARM::tPOP: 1852a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng case ARM::t2STM: 1853a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng case ARM::t2STM_UPD: { 1854344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng UseCycle = getSTMUseCycle(ItinData, UseTID, UseClass, UseIdx, UseAlign); 18555a50ceeaea980962c1982ad535226c7ab06c971cEvan Cheng break; 1856a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng } 1857a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng } 1858a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng 1859a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng if (UseCycle == -1) 1860a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng // Assume it's read in the first stage. 1861a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng UseCycle = 1; 1862a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng 1863a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng UseCycle = DefCycle - UseCycle + 1; 1864a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng if (UseCycle > 0) { 1865a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng if (LdmBypass) { 1866a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng // It's a variable_ops instruction so we can't use DefIdx here. Just use 1867a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng // first def operand. 1868a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng if (ItinData->hasPipelineForwarding(DefClass, DefTID.getNumOperands()-1, 1869a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng UseClass, UseIdx)) 1870a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng --UseCycle; 1871a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng } else if (ItinData->hasPipelineForwarding(DefClass, DefIdx, 1872a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng UseClass, UseIdx)) 1873a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng --UseCycle; 1874a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng } 1875a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng 1876a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng return UseCycle; 1877a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng} 1878a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng 1879a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Chengint 1880a0792de66c8364d47b0a688c7f408efb7b10f31bEvan ChengARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData, 1881a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng const MachineInstr *DefMI, unsigned DefIdx, 1882a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng const MachineInstr *UseMI, unsigned UseIdx) const { 1883a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng if (DefMI->isCopyLike() || DefMI->isInsertSubreg() || 1884a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng DefMI->isRegSequence() || DefMI->isImplicitDef()) 1885a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng return 1; 1886a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng 1887a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng const TargetInstrDesc &DefTID = DefMI->getDesc(); 1888a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng if (!ItinData || ItinData->isEmpty()) 1889a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng return DefTID.mayLoad() ? 3 : 1; 1890a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng 1891a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng const TargetInstrDesc &UseTID = UseMI->getDesc(); 1892a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng unsigned DefAlign = DefMI->hasOneMemOperand() 1893a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng ? (*DefMI->memoperands_begin())->getAlignment() : 0; 1894a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng unsigned UseAlign = UseMI->hasOneMemOperand() 1895a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng ? (*UseMI->memoperands_begin())->getAlignment() : 0; 1896a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng return getOperandLatency(ItinData, DefTID, DefIdx, DefAlign, 1897a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng UseTID, UseIdx, UseAlign); 1898a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng} 1899a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng 1900a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Chengint 1901a0792de66c8364d47b0a688c7f408efb7b10f31bEvan ChengARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData, 1902a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng SDNode *DefNode, unsigned DefIdx, 1903a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng SDNode *UseNode, unsigned UseIdx) const { 1904a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng if (!DefNode->isMachineOpcode()) 1905a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng return 1; 1906a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng 1907a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng const TargetInstrDesc &DefTID = get(DefNode->getMachineOpcode()); 1908a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng if (!ItinData || ItinData->isEmpty()) 1909a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng return DefTID.mayLoad() ? 3 : 1; 1910a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng 1911a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng if (!UseNode->isMachineOpcode()) 1912a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng return ItinData->getOperandCycle(DefTID.getSchedClass(), DefIdx); 1913a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng 1914a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng const TargetInstrDesc &UseTID = get(UseNode->getMachineOpcode()); 1915a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng const MachineSDNode *DefMN = dyn_cast<MachineSDNode>(DefNode); 1916a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng unsigned DefAlign = !DefMN->memoperands_empty() 1917a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng ? (*DefMN->memoperands_begin())->getAlignment() : 0; 1918a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng const MachineSDNode *UseMN = dyn_cast<MachineSDNode>(UseNode); 1919a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng unsigned UseAlign = !UseMN->memoperands_empty() 1920a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng ? (*UseMN->memoperands_begin())->getAlignment() : 0; 1921a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng return getOperandLatency(ItinData, DefTID, DefIdx, DefAlign, 1922a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng UseTID, UseIdx, UseAlign); 1923a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng} 1924