ARMBaseInstrInfo.cpp revision 48575f6ea7d5cd21ab29ca370f58fcf9ca31400b
131c24bf5b39cc8391d4cfdbf8cf5163975fdb81eJim Grosbach//===- ARMBaseInstrInfo.cpp - ARM Instruction Information -------*- C++ -*-===// 2334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// 3334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// The LLVM Compiler Infrastructure 4334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// 5334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// This file is distributed under the University of Illinois Open Source 6334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// License. See LICENSE.TXT for details. 7334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// 8334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin//===----------------------------------------------------------------------===// 9334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// 10334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// This file contains the Base ARM implementation of the TargetInstrInfo class. 11334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// 12334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin//===----------------------------------------------------------------------===// 13334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 14334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "ARMBaseInstrInfo.h" 15334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "ARM.h" 16334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "ARMAddressingModes.h" 17d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng#include "ARMConstantPoolValue.h" 1848575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng#include "ARMHazardRecognizer.h" 19334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "ARMMachineFunctionInfo.h" 20f95215f551949d5e5adfbf4753aa833b9009b77aAnton Korobeynikov#include "ARMRegisterInfo.h" 214dbbe3433f7339ed277af55037ff6847f484e5abChris Lattner#include "ARMGenInstrInfo.inc" 22fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng#include "llvm/Constants.h" 23fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng#include "llvm/Function.h" 24fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng#include "llvm/GlobalValue.h" 25334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "llvm/CodeGen/LiveVariables.h" 26d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng#include "llvm/CodeGen/MachineConstantPool.h" 27334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "llvm/CodeGen/MachineFrameInfo.h" 28334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "llvm/CodeGen/MachineInstrBuilder.h" 29334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "llvm/CodeGen/MachineJumpTableInfo.h" 30249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov#include "llvm/CodeGen/MachineMemOperand.h" 312457f2c66184e978d4ed8fa9e2128effff26cb0bEvan Cheng#include "llvm/CodeGen/MachineRegisterInfo.h" 32249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov#include "llvm/CodeGen/PseudoSourceValue.h" 33af76e592c7f9deff0e55c13dbb4a34f07f1c7f64Chris Lattner#include "llvm/MC/MCAsmInfo.h" 34334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "llvm/Support/CommandLine.h" 35f95215f551949d5e5adfbf4753aa833b9009b77aAnton Korobeynikov#include "llvm/Support/Debug.h" 36c25e7581b9b8088910da31702d4ca21c4734c6d7Torok Edwin#include "llvm/Support/ErrorHandling.h" 3740a5eb18b031fa1a5e9697e21e251e613d441cc5Bill Wendling#include "llvm/ADT/STLExtras.h" 38334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinusing namespace llvm; 39334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 40334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinstatic cl::opt<bool> 41334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinEnableARM3Addr("enable-arm-3-addr-conv", cl::Hidden, 42334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin cl::desc("Enable ARM 2-addr to 3-addr conv")); 43334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 4448575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng 4548575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng/// ARM_MLxEntry - Record information about MLA / MLS instructions. 4648575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Chengstruct ARM_MLxEntry { 4748575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng unsigned MLxOpc; // MLA / MLS opcode 4848575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng unsigned MulOpc; // Expanded multiplication opcode 4948575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng unsigned AddSubOpc; // Expanded add / sub opcode 5048575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng bool NegAcc; // True if the acc is negated before the add / sub. 5148575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng bool HasLane; // True if instruction has an extra "lane" operand. 5248575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng}; 5348575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng 5448575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Chengstatic const ARM_MLxEntry ARM_MLxTable[] = { 5548575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng // MLxOpc, MulOpc, AddSubOpc, NegAcc, HasLane 5648575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng // fp scalar ops 5748575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng { ARM::VMLAS, ARM::VMULS, ARM::VADDS, false, false }, 5848575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng { ARM::VMLSS, ARM::VMULS, ARM::VSUBS, false, false }, 5948575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng { ARM::VMLAD, ARM::VMULD, ARM::VADDD, false, false }, 6048575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng { ARM::VMLSD, ARM::VMULD, ARM::VSUBD, false, false }, 6148575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng { ARM::VMLAfd_sfp, ARM::VMULfd_sfp, ARM::VADDfd_sfp, false, false }, 6248575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng { ARM::VMLSfd_sfp, ARM::VMULfd_sfp, ARM::VSUBfd_sfp, false, false }, 6348575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng { ARM::VNMLAS, ARM::VNMULS, ARM::VSUBS, true, false }, 6448575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng { ARM::VNMLSS, ARM::VMULS, ARM::VSUBS, true, false }, 6548575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng { ARM::VNMLAD, ARM::VNMULD, ARM::VSUBD, true, false }, 6648575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng { ARM::VNMLSD, ARM::VMULD, ARM::VSUBD, true, false }, 6748575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng 6848575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng // fp SIMD ops 6948575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng { ARM::VMLAfd, ARM::VMULfd, ARM::VADDfd, false, false }, 7048575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng { ARM::VMLSfd, ARM::VMULfd, ARM::VSUBfd, false, false }, 7148575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng { ARM::VMLAfq, ARM::VMULfq, ARM::VADDfq, false, false }, 7248575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng { ARM::VMLSfq, ARM::VMULfq, ARM::VSUBfq, false, false }, 7348575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng { ARM::VMLAslfd, ARM::VMULslfd, ARM::VADDfd, false, true }, 7448575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng { ARM::VMLSslfd, ARM::VMULslfd, ARM::VSUBfd, false, true }, 7548575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng { ARM::VMLAslfq, ARM::VMULslfq, ARM::VADDfq, false, true }, 7648575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng { ARM::VMLSslfq, ARM::VMULslfq, ARM::VSUBfq, false, true }, 7748575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng}; 7848575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng 79f95215f551949d5e5adfbf4753aa833b9009b77aAnton KorobeynikovARMBaseInstrInfo::ARMBaseInstrInfo(const ARMSubtarget& STI) 80f95215f551949d5e5adfbf4753aa833b9009b77aAnton Korobeynikov : TargetInstrInfoImpl(ARMInsts, array_lengthof(ARMInsts)), 81f95215f551949d5e5adfbf4753aa833b9009b77aAnton Korobeynikov Subtarget(STI) { 8248575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng for (unsigned i = 0, e = array_lengthof(ARM_MLxTable); i != e; ++i) { 8348575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng if (!MLxEntryMap.insert(std::make_pair(ARM_MLxTable[i].MLxOpc, i)).second) 8448575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng assert(false && "Duplicated entries?"); 8548575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng MLxHazardOpcodes.insert(ARM_MLxTable[i].AddSubOpc); 8648575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng MLxHazardOpcodes.insert(ARM_MLxTable[i].MulOpc); 8748575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng } 8848575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng} 8948575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng 9048575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan ChengScheduleHazardRecognizer *ARMBaseInstrInfo:: 9148575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan ChengCreateTargetPostRAHazardRecognizer(const InstrItineraryData *II) const { 9248575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng if (Subtarget.isThumb2() || Subtarget.hasVFP2()) 9348575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng return (ScheduleHazardRecognizer *) 9448575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng new ARMHazardRecognizer(II, *this, getRegisterInfo(), Subtarget); 9548575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng return TargetInstrInfoImpl::CreateTargetPostRAHazardRecognizer(II); 96334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 97334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 98334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinMachineInstr * 99334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinARMBaseInstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI, 100334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineBasicBlock::iterator &MBBI, 101334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin LiveVariables *LV) const { 10278703ddafe3d037f75d8ca188e4829d238289ac3Evan Cheng // FIXME: Thumb2 support. 10378703ddafe3d037f75d8ca188e4829d238289ac3Evan Cheng 104334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (!EnableARM3Addr) 105334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return NULL; 106334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 107334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineInstr *MI = MBBI; 108334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineFunction &MF = *MI->getParent()->getParent(); 10999405df044f2c584242e711cc9023ec90356da82Bruno Cardoso Lopes uint64_t TSFlags = MI->getDesc().TSFlags; 110334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool isPre = false; 111334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin switch ((TSFlags & ARMII::IndexModeMask) >> ARMII::IndexModeShift) { 112334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin default: return NULL; 113334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMII::IndexModePre: 114334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin isPre = true; 115334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin break; 116334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMII::IndexModePost: 117334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin break; 118334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 119334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 120334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Try splitting an indexed load/store to an un-indexed one plus an add/sub 121334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // operation. 122334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned MemOpc = getUnindexedOpcode(MI->getOpcode()); 123334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (MemOpc == 0) 124334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return NULL; 125334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 126334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineInstr *UpdateMI = NULL; 127334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineInstr *MemMI = NULL; 128334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned AddrMode = (TSFlags & ARMII::AddrModeMask); 129334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const TargetInstrDesc &TID = MI->getDesc(); 130334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned NumOps = TID.getNumOperands(); 131334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool isLoad = !TID.mayStore(); 132334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const MachineOperand &WB = isLoad ? MI->getOperand(1) : MI->getOperand(0); 133334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const MachineOperand &Base = MI->getOperand(2); 134334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const MachineOperand &Offset = MI->getOperand(NumOps-3); 135334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned WBReg = WB.getReg(); 136334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned BaseReg = Base.getReg(); 137334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned OffReg = Offset.getReg(); 138334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned OffImm = MI->getOperand(NumOps-2).getImm(); 139334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin ARMCC::CondCodes Pred = (ARMCC::CondCodes)MI->getOperand(NumOps-1).getImm(); 140334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin switch (AddrMode) { 141334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin default: 142334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin assert(false && "Unknown indexed op!"); 143334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return NULL; 144334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMII::AddrMode2: { 145334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool isSub = ARM_AM::getAM2Op(OffImm) == ARM_AM::sub; 146334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned Amt = ARM_AM::getAM2Offset(OffImm); 147334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (OffReg == 0) { 148e7cbe4118b7ddf05032ff8772a98c51e1637bb5cEvan Cheng if (ARM_AM::getSOImmVal(Amt) == -1) 149334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Can't encode it in a so_imm operand. This transformation will 150334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // add more than 1 instruction. Abandon! 151334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return NULL; 152334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin UpdateMI = BuildMI(MF, MI->getDebugLoc(), 15378703ddafe3d037f75d8ca188e4829d238289ac3Evan Cheng get(isSub ? ARM::SUBri : ARM::ADDri), WBReg) 154e7cbe4118b7ddf05032ff8772a98c51e1637bb5cEvan Cheng .addReg(BaseReg).addImm(Amt) 155334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addImm(Pred).addReg(0).addReg(0); 156334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } else if (Amt != 0) { 157334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin ARM_AM::ShiftOpc ShOpc = ARM_AM::getAM2ShiftOpc(OffImm); 158334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned SOOpc = ARM_AM::getSORegOpc(ShOpc, Amt); 159334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin UpdateMI = BuildMI(MF, MI->getDebugLoc(), 16078703ddafe3d037f75d8ca188e4829d238289ac3Evan Cheng get(isSub ? ARM::SUBrs : ARM::ADDrs), WBReg) 161334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(BaseReg).addReg(OffReg).addReg(0).addImm(SOOpc) 162334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addImm(Pred).addReg(0).addReg(0); 163334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } else 164334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin UpdateMI = BuildMI(MF, MI->getDebugLoc(), 16578703ddafe3d037f75d8ca188e4829d238289ac3Evan Cheng get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg) 166334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(BaseReg).addReg(OffReg) 167334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addImm(Pred).addReg(0).addReg(0); 168334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin break; 169334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 170334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMII::AddrMode3 : { 171334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool isSub = ARM_AM::getAM3Op(OffImm) == ARM_AM::sub; 172334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned Amt = ARM_AM::getAM3Offset(OffImm); 173334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (OffReg == 0) 174334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Immediate is 8-bits. It's guaranteed to fit in a so_imm operand. 175334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin UpdateMI = BuildMI(MF, MI->getDebugLoc(), 17678703ddafe3d037f75d8ca188e4829d238289ac3Evan Cheng get(isSub ? ARM::SUBri : ARM::ADDri), WBReg) 177334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(BaseReg).addImm(Amt) 178334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addImm(Pred).addReg(0).addReg(0); 179334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin else 180334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin UpdateMI = BuildMI(MF, MI->getDebugLoc(), 18178703ddafe3d037f75d8ca188e4829d238289ac3Evan Cheng get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg) 182334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(BaseReg).addReg(OffReg) 183334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addImm(Pred).addReg(0).addReg(0); 184334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin break; 185334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 186334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 187334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 188334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin std::vector<MachineInstr*> NewMIs; 189334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (isPre) { 190334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (isLoad) 191334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MemMI = BuildMI(MF, MI->getDebugLoc(), 192334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin get(MemOpc), MI->getOperand(0).getReg()) 1933e5561247202bae994dd259a2d8dc4eff8f799f3Jim Grosbach .addReg(WBReg).addImm(0).addImm(Pred); 194334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin else 195334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MemMI = BuildMI(MF, MI->getDebugLoc(), 196334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin get(MemOpc)).addReg(MI->getOperand(1).getReg()) 197334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(WBReg).addReg(0).addImm(0).addImm(Pred); 198334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin NewMIs.push_back(MemMI); 199334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin NewMIs.push_back(UpdateMI); 200334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } else { 201334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (isLoad) 202334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MemMI = BuildMI(MF, MI->getDebugLoc(), 203334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin get(MemOpc), MI->getOperand(0).getReg()) 2043e5561247202bae994dd259a2d8dc4eff8f799f3Jim Grosbach .addReg(BaseReg).addImm(0).addImm(Pred); 205334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin else 206334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MemMI = BuildMI(MF, MI->getDebugLoc(), 207334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin get(MemOpc)).addReg(MI->getOperand(1).getReg()) 208334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred); 209334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (WB.isDead()) 210334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin UpdateMI->getOperand(0).setIsDead(); 211334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin NewMIs.push_back(UpdateMI); 212334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin NewMIs.push_back(MemMI); 213334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 214334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 215334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Transfer LiveVariables states, kill / dead info. 216334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (LV) { 217334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 218334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineOperand &MO = MI->getOperand(i); 219334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (MO.isReg() && MO.getReg() && 220334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin TargetRegisterInfo::isVirtualRegister(MO.getReg())) { 221334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned Reg = MO.getReg(); 222334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 223334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin LiveVariables::VarInfo &VI = LV->getVarInfo(Reg); 224334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (MO.isDef()) { 225334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineInstr *NewMI = (Reg == WBReg) ? UpdateMI : MemMI; 226334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (MO.isDead()) 227334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin LV->addVirtualRegisterDead(Reg, NewMI); 228334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 229334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (MO.isUse() && MO.isKill()) { 230334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin for (unsigned j = 0; j < 2; ++j) { 231334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Look at the two new MI's in reverse order. 232334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineInstr *NewMI = NewMIs[j]; 233334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (!NewMI->readsRegister(Reg)) 234334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin continue; 235334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin LV->addVirtualRegisterKilled(Reg, NewMI); 236334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (VI.removeKill(MI)) 237334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin VI.Kills.push_back(NewMI); 238334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin break; 239334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 240334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 241334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 242334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 243334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 244334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 245334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MFI->insert(MBBI, NewMIs[1]); 246334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MFI->insert(MBBI, NewMIs[0]); 247334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return NewMIs[0]; 248334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 249334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 250334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// Branch analysis. 251334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinbool 252334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinARMBaseInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB, 253334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineBasicBlock *&FBB, 254334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin SmallVectorImpl<MachineOperand> &Cond, 255334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool AllowModify) const { 256334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // If the block has no terminators, it just falls into the block after it. 257334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineBasicBlock::iterator I = MBB.end(); 25893d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen if (I == MBB.begin()) 25993d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen return false; 26093d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen --I; 26193d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen while (I->isDebugValue()) { 26293d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen if (I == MBB.begin()) 26393d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen return false; 26493d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen --I; 26593d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen } 26693d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen if (!isUnpredicatedTerminator(I)) 267334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 268334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 269334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Get the last instruction in the block. 270334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineInstr *LastInst = I; 271334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 272334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // If there is only one terminator instruction, process it. 273334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned LastOpc = LastInst->getOpcode(); 274334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) { 2755ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng if (isUncondBranchOpcode(LastOpc)) { 276334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin TBB = LastInst->getOperand(0).getMBB(); 277334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 278334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 2795ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng if (isCondBranchOpcode(LastOpc)) { 280334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Block ends with fall-through condbranch. 281334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin TBB = LastInst->getOperand(0).getMBB(); 282334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin Cond.push_back(LastInst->getOperand(1)); 283334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin Cond.push_back(LastInst->getOperand(2)); 284334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 285334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 286334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; // Can't handle indirect branch. 287334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 288334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 289334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Get the instruction before it if it is a terminator. 290334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineInstr *SecondLastInst = I; 291108c8724663354050dc09bb1262c3e4511adf82fEvan Cheng unsigned SecondLastOpc = SecondLastInst->getOpcode(); 292108c8724663354050dc09bb1262c3e4511adf82fEvan Cheng 293108c8724663354050dc09bb1262c3e4511adf82fEvan Cheng // If AllowModify is true and the block ends with two or more unconditional 294108c8724663354050dc09bb1262c3e4511adf82fEvan Cheng // branches, delete all but the first unconditional branch. 295108c8724663354050dc09bb1262c3e4511adf82fEvan Cheng if (AllowModify && isUncondBranchOpcode(LastOpc)) { 296108c8724663354050dc09bb1262c3e4511adf82fEvan Cheng while (isUncondBranchOpcode(SecondLastOpc)) { 297108c8724663354050dc09bb1262c3e4511adf82fEvan Cheng LastInst->eraseFromParent(); 298108c8724663354050dc09bb1262c3e4511adf82fEvan Cheng LastInst = SecondLastInst; 299108c8724663354050dc09bb1262c3e4511adf82fEvan Cheng LastOpc = LastInst->getOpcode(); 300676e258366dd17a0b4ee6ac66914237ce181202eEvan Cheng if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) { 301676e258366dd17a0b4ee6ac66914237ce181202eEvan Cheng // Return now the only terminator is an unconditional branch. 302676e258366dd17a0b4ee6ac66914237ce181202eEvan Cheng TBB = LastInst->getOperand(0).getMBB(); 303676e258366dd17a0b4ee6ac66914237ce181202eEvan Cheng return false; 304676e258366dd17a0b4ee6ac66914237ce181202eEvan Cheng } else { 305108c8724663354050dc09bb1262c3e4511adf82fEvan Cheng SecondLastInst = I; 306108c8724663354050dc09bb1262c3e4511adf82fEvan Cheng SecondLastOpc = SecondLastInst->getOpcode(); 307108c8724663354050dc09bb1262c3e4511adf82fEvan Cheng } 308108c8724663354050dc09bb1262c3e4511adf82fEvan Cheng } 309108c8724663354050dc09bb1262c3e4511adf82fEvan Cheng } 310334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 311334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // If there are three terminators, we don't know what sort of block this is. 312334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(--I)) 313334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; 314334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 3155ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng // If the block ends with a B and a Bcc, handle it. 3165ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng if (isCondBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) { 317334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin TBB = SecondLastInst->getOperand(0).getMBB(); 318334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin Cond.push_back(SecondLastInst->getOperand(1)); 319334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin Cond.push_back(SecondLastInst->getOperand(2)); 320334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin FBB = LastInst->getOperand(0).getMBB(); 321334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 322334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 323334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 324334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // If the block ends with two unconditional branches, handle it. The second 325334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // one is not executed, so remove it. 3265ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng if (isUncondBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) { 327334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin TBB = SecondLastInst->getOperand(0).getMBB(); 328334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin I = LastInst; 329334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (AllowModify) 330334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin I->eraseFromParent(); 331334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 332334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 333334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 334334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // ...likewise if it ends with a branch table followed by an unconditional 335334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // branch. The branch folder can create these, and we must get rid of them for 336334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // correctness of Thumb constant islands. 3378d4de5abfa1bcd974554ea14904ebf7af289e84dBob Wilson if ((isJumpTableBranchOpcode(SecondLastOpc) || 3388d4de5abfa1bcd974554ea14904ebf7af289e84dBob Wilson isIndirectBranchOpcode(SecondLastOpc)) && 3395ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng isUncondBranchOpcode(LastOpc)) { 340334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin I = LastInst; 341334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (AllowModify) 342334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin I->eraseFromParent(); 343334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; 344334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 345334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 346334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Otherwise, can't handle this. 347334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; 348334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 349334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 350334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 351334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinunsigned ARMBaseInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const { 352334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineBasicBlock::iterator I = MBB.end(); 353334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (I == MBB.begin()) return 0; 354334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin --I; 35593d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen while (I->isDebugValue()) { 35693d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen if (I == MBB.begin()) 35793d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen return 0; 35893d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen --I; 35993d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen } 3605ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng if (!isUncondBranchOpcode(I->getOpcode()) && 3615ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng !isCondBranchOpcode(I->getOpcode())) 362334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 0; 363334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 364334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Remove the branch. 365334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin I->eraseFromParent(); 366334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 367334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin I = MBB.end(); 368334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 369334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (I == MBB.begin()) return 1; 370334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin --I; 3715ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng if (!isCondBranchOpcode(I->getOpcode())) 372334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 1; 373334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 374334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Remove the branch. 375334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin I->eraseFromParent(); 376334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 2; 377334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 378334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 379334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinunsigned 380334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinARMBaseInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 3813bf912593301152b65accb9d9c37a95172f1df5aStuart Hastings MachineBasicBlock *FBB, 3823bf912593301152b65accb9d9c37a95172f1df5aStuart Hastings const SmallVectorImpl<MachineOperand> &Cond, 3833bf912593301152b65accb9d9c37a95172f1df5aStuart Hastings DebugLoc DL) const { 3846495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ARMFunctionInfo *AFI = MBB.getParent()->getInfo<ARMFunctionInfo>(); 3856495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng int BOpc = !AFI->isThumbFunction() 3866495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ? ARM::B : (AFI->isThumb2Function() ? ARM::t2B : ARM::tB); 3876495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng int BccOpc = !AFI->isThumbFunction() 3886495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ? ARM::Bcc : (AFI->isThumb2Function() ? ARM::t2Bcc : ARM::tBcc); 389334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 390334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Shouldn't be a fall through. 391334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin assert(TBB && "InsertBranch must not be told to insert a fallthrough"); 392334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin assert((Cond.size() == 2 || Cond.size() == 0) && 393334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin "ARM branch conditions have two components!"); 394334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 395334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (FBB == 0) { 396334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (Cond.empty()) // Unconditional branch? 3973bf912593301152b65accb9d9c37a95172f1df5aStuart Hastings BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB); 398334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin else 3993bf912593301152b65accb9d9c37a95172f1df5aStuart Hastings BuildMI(&MBB, DL, get(BccOpc)).addMBB(TBB) 400334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()); 401334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 1; 402334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 403334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 404334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Two-way conditional branch. 4053bf912593301152b65accb9d9c37a95172f1df5aStuart Hastings BuildMI(&MBB, DL, get(BccOpc)).addMBB(TBB) 406334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()); 4073bf912593301152b65accb9d9c37a95172f1df5aStuart Hastings BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB); 408334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 2; 409334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 410334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 411334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinbool ARMBaseInstrInfo:: 412334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const { 413334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin ARMCC::CondCodes CC = (ARMCC::CondCodes)(int)Cond[0].getImm(); 414334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin Cond[0].setImm(ARMCC::getOppositeCondition(CC)); 415334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 416334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 417334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 418334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinbool ARMBaseInstrInfo:: 419334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinPredicateInstruction(MachineInstr *MI, 420334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const SmallVectorImpl<MachineOperand> &Pred) const { 421334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned Opc = MI->getOpcode(); 4225ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng if (isUncondBranchOpcode(Opc)) { 4235ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng MI->setDesc(get(getMatchingCondBranchOpcode(Opc))); 424334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI->addOperand(MachineOperand::CreateImm(Pred[0].getImm())); 425334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI->addOperand(MachineOperand::CreateReg(Pred[1].getReg(), false)); 426334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; 427334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 428334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 429334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin int PIdx = MI->findFirstPredOperandIdx(); 430334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (PIdx != -1) { 431334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineOperand &PMO = MI->getOperand(PIdx); 432334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin PMO.setImm(Pred[0].getImm()); 433334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI->getOperand(PIdx+1).setReg(Pred[1].getReg()); 434334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; 435334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 436334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 437334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 438334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 439334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinbool ARMBaseInstrInfo:: 440334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinSubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1, 441334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const SmallVectorImpl<MachineOperand> &Pred2) const { 442334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (Pred1.size() > 2 || Pred2.size() > 2) 443334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 444334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 445334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin ARMCC::CondCodes CC1 = (ARMCC::CondCodes)Pred1[0].getImm(); 446334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin ARMCC::CondCodes CC2 = (ARMCC::CondCodes)Pred2[0].getImm(); 447334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (CC1 == CC2) 448334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; 449334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 450334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin switch (CC1) { 451334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin default: 452334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 453334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMCC::AL: 454334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; 455334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMCC::HS: 456334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return CC2 == ARMCC::HI; 457334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMCC::LS: 458334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return CC2 == ARMCC::LO || CC2 == ARMCC::EQ; 459334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMCC::GE: 460334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return CC2 == ARMCC::GT; 461334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMCC::LE: 462334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return CC2 == ARMCC::LT; 463334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 464334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 465334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 466334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinbool ARMBaseInstrInfo::DefinesPredicate(MachineInstr *MI, 467334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin std::vector<MachineOperand> &Pred) const { 4688fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng // FIXME: This confuses implicit_def with optional CPSR def. 469334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const TargetInstrDesc &TID = MI->getDesc(); 470334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (!TID.getImplicitDefs() && !TID.hasOptionalDef()) 471334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 472334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 473334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool Found = false; 474334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 475334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const MachineOperand &MO = MI->getOperand(i); 476334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (MO.isReg() && MO.getReg() == ARM::CPSR) { 477334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin Pred.push_back(MO); 478334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin Found = true; 479334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 480334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 481334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 482334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return Found; 483334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 484334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 485ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng/// isPredicable - Return true if the specified instruction can be predicated. 486ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng/// By default, this returns true for every instruction with a 487ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng/// PredicateOperand. 488ac0869dc8a7986855c5557cc67d4709600158ef5Evan Chengbool ARMBaseInstrInfo::isPredicable(MachineInstr *MI) const { 489ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng const TargetInstrDesc &TID = MI->getDesc(); 490ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng if (!TID.isPredicable()) 491ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng return false; 492ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng 493ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng if ((TID.TSFlags & ARMII::DomainMask) == ARMII::DomainNEON) { 494ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng ARMFunctionInfo *AFI = 495ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng MI->getParent()->getParent()->getInfo<ARMFunctionInfo>(); 496d7f0810c934a7d13acb28c42d737ce58ec990ea8Evan Cheng return AFI->isThumb2Function(); 497ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng } 498ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng return true; 499ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng} 500334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 50156856b1f46ec1f073ceef4e826c544b8b1691608Chris Lattner/// FIXME: Works around a gcc miscompilation with -fstrict-aliasing. 50219e57025d458d3cb50804fd821fd89b868a819bdChandler CarruthLLVM_ATTRIBUTE_NOINLINE 503334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinstatic unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT, 50456856b1f46ec1f073ceef4e826c544b8b1691608Chris Lattner unsigned JTI); 505334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinstatic unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT, 506334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned JTI) { 50756856b1f46ec1f073ceef4e826c544b8b1691608Chris Lattner assert(JTI < JT.size()); 508334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return JT[JTI].MBBs.size(); 509334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 510334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 511334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin/// GetInstSize - Return the size of the specified MachineInstr. 512334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin/// 513334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinunsigned ARMBaseInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const { 514334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const MachineBasicBlock &MBB = *MI->getParent(); 515334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const MachineFunction *MF = MBB.getParent(); 51633adcfb4d217f5f23d9bde8ba02b8e48f9605fc5Chris Lattner const MCAsmInfo *MAI = MF->getTarget().getMCAsmInfo(); 517334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 518334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Basic size info comes from the TSFlags field. 519334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const TargetInstrDesc &TID = MI->getDesc(); 52099405df044f2c584242e711cc9023ec90356da82Bruno Cardoso Lopes uint64_t TSFlags = TID.TSFlags; 521334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 522a0ee862f2e3a0d202244e02459ddcf0dca0e8607Evan Cheng unsigned Opc = MI->getOpcode(); 523334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin switch ((TSFlags & ARMII::SizeMask) >> ARMII::SizeShift) { 524334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin default: { 525334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // If this machine instr is an inline asm, measure it. 526334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (MI->getOpcode() == ARM::INLINEASM) 52733adcfb4d217f5f23d9bde8ba02b8e48f9605fc5Chris Lattner return getInlineAsmLength(MI->getOperand(0).getSymbolName(), *MAI); 528334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (MI->isLabel()) 529334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 0; 530a0ee862f2e3a0d202244e02459ddcf0dca0e8607Evan Cheng switch (Opc) { 531334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin default: 532c23197a26f34f559ea9797de51e187087c039c42Torok Edwin llvm_unreachable("Unknown or unset size field for instr!"); 533518bb53485df640d7b7e3f6b0544099020c42aa7Chris Lattner case TargetOpcode::IMPLICIT_DEF: 534518bb53485df640d7b7e3f6b0544099020c42aa7Chris Lattner case TargetOpcode::KILL: 5357431beaba2a01c3fe299c861b2ec85cbf1dc81c4Bill Wendling case TargetOpcode::PROLOG_LABEL: 536518bb53485df640d7b7e3f6b0544099020c42aa7Chris Lattner case TargetOpcode::EH_LABEL: 537375be7730a6f3dee7a6dc319ee6c355a11ac99adDale Johannesen case TargetOpcode::DBG_VALUE: 538334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 0; 539334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 540334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin break; 541334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 542789476240d6b6f8ad9366cadf790a82bd41bb0b3Evan Cheng case ARMII::Size8Bytes: return 8; // ARM instruction x 2. 543789476240d6b6f8ad9366cadf790a82bd41bb0b3Evan Cheng case ARMII::Size4Bytes: return 4; // ARM / Thumb2 instruction. 544789476240d6b6f8ad9366cadf790a82bd41bb0b3Evan Cheng case ARMII::Size2Bytes: return 2; // Thumb1 instruction. 545334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMII::SizeSpecial: { 546a0ee862f2e3a0d202244e02459ddcf0dca0e8607Evan Cheng switch (Opc) { 5473c38f96af2a5443d9f72fd078c2c98dd08746e51Jim Grosbach case ARM::MOVi32imm: 5483c38f96af2a5443d9f72fd078c2c98dd08746e51Jim Grosbach case ARM::t2MOVi32imm: 5493c38f96af2a5443d9f72fd078c2c98dd08746e51Jim Grosbach return 8; 550334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARM::CONSTPOOL_ENTRY: 551334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // If this machine instr is a constant pool entry, its size is recorded as 552334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // operand #2. 553334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return MI->getOperand(2).getImm(); 5545eb195153950bc7ebfc30649494a78b2096b5ef8Jim Grosbach case ARM::Int_eh_sjlj_longjmp: 5555eb195153950bc7ebfc30649494a78b2096b5ef8Jim Grosbach return 16; 5565eb195153950bc7ebfc30649494a78b2096b5ef8Jim Grosbach case ARM::tInt_eh_sjlj_longjmp: 5575eb195153950bc7ebfc30649494a78b2096b5ef8Jim Grosbach return 10; 558789476240d6b6f8ad9366cadf790a82bd41bb0b3Evan Cheng case ARM::Int_eh_sjlj_setjmp: 559d100755bab38784703f677b8b8eb174b624b346bJim Grosbach case ARM::Int_eh_sjlj_setjmp_nofp: 5600798eddd07b8dc827a4e6e9028c4c3a8d9444286Jim Grosbach return 20; 561d122874996a6faa8832569b632fd73a32ace7ae7Jim Grosbach case ARM::tInt_eh_sjlj_setjmp: 5625aa1684e5da9a85286bf7d29da419d261a70c2f2Jim Grosbach case ARM::t2Int_eh_sjlj_setjmp: 563d100755bab38784703f677b8b8eb174b624b346bJim Grosbach case ARM::t2Int_eh_sjlj_setjmp_nofp: 5640798eddd07b8dc827a4e6e9028c4c3a8d9444286Jim Grosbach return 12; 565334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARM::BR_JTr: 566334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARM::BR_JTm: 567334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARM::BR_JTadd: 568a0ee862f2e3a0d202244e02459ddcf0dca0e8607Evan Cheng case ARM::tBR_JTr: 569d26b14c34cbcee1448b86b524578fc51cc979023Evan Cheng case ARM::t2BR_JT: 570d092a87ba3f905a6801a0bdf816267329cf0391cJim Grosbach case ARM::t2TBB_JT: 571d092a87ba3f905a6801a0bdf816267329cf0391cJim Grosbach case ARM::t2TBH_JT: { 572334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // These are jumptable branches, i.e. a branch followed by an inlined 573d26b14c34cbcee1448b86b524578fc51cc979023Evan Cheng // jumptable. The size is 4 + 4 * number of entries. For TBB, each 574d26b14c34cbcee1448b86b524578fc51cc979023Evan Cheng // entry is one byte; TBH two byte each. 575d092a87ba3f905a6801a0bdf816267329cf0391cJim Grosbach unsigned EntrySize = (Opc == ARM::t2TBB_JT) 576d092a87ba3f905a6801a0bdf816267329cf0391cJim Grosbach ? 1 : ((Opc == ARM::t2TBH_JT) ? 2 : 4); 577334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned NumOps = TID.getNumOperands(); 578334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineOperand JTOP = 579334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI->getOperand(NumOps - (TID.isPredicable() ? 3 : 2)); 580334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned JTI = JTOP.getIndex(); 581334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo(); 582b1e803985d3378538ae9cff7eed4102c002d1e22Chris Lattner assert(MJTI != 0); 583334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables(); 584334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin assert(JTI < JT.size()); 585334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Thumb instructions are 2 byte aligned, but JT entries are 4 byte 586334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // 4 aligned. The assembler / linker may add 2 byte padding just before 587334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // the JT entries. The size does not include this padding; the 588334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // constant islands pass does separate bookkeeping for it. 589334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // FIXME: If we know the size of the function is less than (1 << 16) *2 590334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // bytes, we can use 16-bit entries instead. Then there won't be an 591334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // alignment issue. 59225f7cfc3cccba6f569f29f79ea533bae960b93c0Evan Cheng unsigned InstSize = (Opc == ARM::tBR_JTr || Opc == ARM::t2BR_JT) ? 2 : 4; 59325f7cfc3cccba6f569f29f79ea533bae960b93c0Evan Cheng unsigned NumEntries = getNumJTEntries(JT, JTI); 594d092a87ba3f905a6801a0bdf816267329cf0391cJim Grosbach if (Opc == ARM::t2TBB_JT && (NumEntries & 1)) 59525f7cfc3cccba6f569f29f79ea533bae960b93c0Evan Cheng // Make sure the instruction that follows TBB is 2-byte aligned. 59625f7cfc3cccba6f569f29f79ea533bae960b93c0Evan Cheng // FIXME: Constant island pass should insert an "ALIGN" instruction 59725f7cfc3cccba6f569f29f79ea533bae960b93c0Evan Cheng // instead. 59825f7cfc3cccba6f569f29f79ea533bae960b93c0Evan Cheng ++NumEntries; 59925f7cfc3cccba6f569f29f79ea533bae960b93c0Evan Cheng return NumEntries * EntrySize + InstSize; 600334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 601334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin default: 602334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Otherwise, pseudo-instruction sizes are zero. 603334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 0; 604334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 605334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 606334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 607334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 0; // Not reached 608334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 609334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 610ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesenvoid ARMBaseInstrInfo::copyPhysReg(MachineBasicBlock &MBB, 611ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen MachineBasicBlock::iterator I, DebugLoc DL, 612ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen unsigned DestReg, unsigned SrcReg, 613ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen bool KillSrc) const { 614ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen bool GPRDest = ARM::GPRRegClass.contains(DestReg); 615ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen bool GPRSrc = ARM::GPRRegClass.contains(SrcReg); 616ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen 617ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen if (GPRDest && GPRSrc) { 618ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen AddDefaultCC(AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::MOVr), DestReg) 619ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen .addReg(SrcReg, getKillRegState(KillSrc)))); 620ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen return; 6217bfdca0206f51132b26094c6f83a5ac97ee0f943David Goodwin } 622334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 623ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen bool SPRDest = ARM::SPRRegClass.contains(DestReg); 624ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen bool SPRSrc = ARM::SPRRegClass.contains(SrcReg); 625ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen 626ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen unsigned Opc; 627ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen if (SPRDest && SPRSrc) 628ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen Opc = ARM::VMOVS; 629ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen else if (GPRDest && SPRSrc) 630ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen Opc = ARM::VMOVRS; 631ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen else if (SPRDest && GPRSrc) 632ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen Opc = ARM::VMOVSR; 633ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen else if (ARM::DPRRegClass.contains(DestReg, SrcReg)) 634ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen Opc = ARM::VMOVD; 635ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen else if (ARM::QPRRegClass.contains(DestReg, SrcReg)) 636ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen Opc = ARM::VMOVQ; 637ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen else if (ARM::QQPRRegClass.contains(DestReg, SrcReg)) 638ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen Opc = ARM::VMOVQQ; 639ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen else if (ARM::QQQQPRRegClass.contains(DestReg, SrcReg)) 640ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen Opc = ARM::VMOVQQQQ; 641ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen else 642ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen llvm_unreachable("Impossible reg-to-reg copy"); 643ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen 644ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc), DestReg); 645ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen MIB.addReg(SrcReg, getKillRegState(KillSrc)); 646ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen if (Opc != ARM::VMOVQQ && Opc != ARM::VMOVQQQQ) 647ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen AddDefaultPred(MIB); 648334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 649334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 650c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Chengstatic const 651c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan ChengMachineInstrBuilder &AddDReg(MachineInstrBuilder &MIB, 652c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Cheng unsigned Reg, unsigned SubIdx, unsigned State, 653c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Cheng const TargetRegisterInfo *TRI) { 654c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Cheng if (!SubIdx) 655c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Cheng return MIB.addReg(Reg, State); 656c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Cheng 657c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Cheng if (TargetRegisterInfo::isPhysicalRegister(Reg)) 658c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Cheng return MIB.addReg(TRI->getSubReg(Reg, SubIdx), State); 659c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Cheng return MIB.addReg(Reg, State, SubIdx); 660c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Cheng} 661c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Cheng 662334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinvoid ARMBaseInstrInfo:: 663334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinstoreRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 664334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned SrcReg, bool isKill, int FI, 665746ad69e088176819981b4b2c5ac8dcd49f5e60eEvan Cheng const TargetRegisterClass *RC, 666746ad69e088176819981b4b2c5ac8dcd49f5e60eEvan Cheng const TargetRegisterInfo *TRI) const { 667c7f3ace20c325521c68335a1689645b43b06ddf0Chris Lattner DebugLoc DL; 668334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (I != MBB.end()) DL = I->getDebugLoc(); 669249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MachineFunction &MF = *MBB.getParent(); 670249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MachineFrameInfo &MFI = *MF.getFrameInfo(); 67131bc849123011b8eae6bb3c79876d9a3c26a6a1dJim Grosbach unsigned Align = MFI.getObjectAlignment(FI); 672249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov 673249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MachineMemOperand *MMO = 67459db5496f4fc2ef6111569e542f8b65480ef14c1Chris Lattner MF.getMachineMemOperand(MachinePointerInfo( 67559db5496f4fc2ef6111569e542f8b65480ef14c1Chris Lattner PseudoSourceValue::getFixedStack(FI)), 67659db5496f4fc2ef6111569e542f8b65480ef14c1Chris Lattner MachineMemOperand::MOStore, 677249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MFI.getObjectSize(FI), 67831bc849123011b8eae6bb3c79876d9a3c26a6a1dJim Grosbach Align); 679334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 6800eb0c7401c34c0b4604f732ce54db995eead14e6Bob Wilson // tGPR is used sometimes in ARM instructions that need to avoid using 6816ccfc507dc1f7ad8c8964193a2407264ca644f0dJim Grosbach // certain registers. Just treat it as GPR here. Likewise, rGPR. 6826ccfc507dc1f7ad8c8964193a2407264ca644f0dJim Grosbach if (RC == ARM::tGPRRegisterClass || RC == ARM::tcGPRRegisterClass 6836ccfc507dc1f7ad8c8964193a2407264ca644f0dJim Grosbach || RC == ARM::rGPRRegisterClass) 6840eb0c7401c34c0b4604f732ce54db995eead14e6Bob Wilson RC = ARM::GPRRegisterClass; 6850eb0c7401c34c0b4604f732ce54db995eead14e6Bob Wilson 686ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson switch (RC->getID()) { 687ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson case ARM::GPRRegClassID: 6887e3383c007f53b3a00675af225e428cb66ddf404Jim Grosbach AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::STRi12)) 689334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(SrcReg, getKillRegState(isKill)) 6907e3383c007f53b3a00675af225e428cb66ddf404Jim Grosbach .addFrameIndex(FI).addImm(0).addMemOperand(MMO)); 691ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson break; 692ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson case ARM::SPRRegClassID: 693d31c5496d7e1580058b5c6fbc8fd537a641ea590Evan Cheng AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTRS)) 694d31c5496d7e1580058b5c6fbc8fd537a641ea590Evan Cheng .addReg(SrcReg, getKillRegState(isKill)) 695d31c5496d7e1580058b5c6fbc8fd537a641ea590Evan Cheng .addFrameIndex(FI).addImm(0).addMemOperand(MMO)); 696ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson break; 697ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson case ARM::DPRRegClassID: 698ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson case ARM::DPR_VFP2RegClassID: 699ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson case ARM::DPR_8RegClassID: 700e5165490b7ba24bb2f3043399e0d60e7f3bcf8a5Jim Grosbach AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTRD)) 701334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(SrcReg, getKillRegState(isKill)) 702249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov .addFrameIndex(FI).addImm(0).addMemOperand(MMO)); 703ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson break; 704ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson case ARM::QPRRegClassID: 705ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson case ARM::QPR_VFP2RegClassID: 706ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson case ARM::QPR_8RegClassID: 7070cfcf93c95af91e809ef740eb0ab368477226b40Jim Grosbach if (Align >= 16 && getRegisterInfo().needsStackRealignment(MF)) { 708168f382dc67e5940cabdb28dc933c4f91cdd3137Bob Wilson AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1q64Pseudo)) 709f967ca0eaf30325cabe3c1971bf0dba16cf1b027Bob Wilson .addFrameIndex(FI).addImm(16) 71069b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng .addReg(SrcReg, getKillRegState(isKill)) 71169b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng .addMemOperand(MMO)); 71231bc849123011b8eae6bb3c79876d9a3c26a6a1dJim Grosbach } else { 71373fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMQIA)) 71469b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng .addReg(SrcReg, getKillRegState(isKill)) 71569b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng .addFrameIndex(FI) 71669b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng .addMemOperand(MMO)); 71731bc849123011b8eae6bb3c79876d9a3c26a6a1dJim Grosbach } 718ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson break; 719ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson case ARM::QQPRRegClassID: 720ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson case ARM::QQPR_VFP2RegClassID: 721435d4991779d6a47cadff4ea670b490d8507d6c4Evan Cheng if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) { 72222c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng // FIXME: It's possible to only store part of the QQ register if the 72322c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng // spilled def has a sub-register index. 724168f382dc67e5940cabdb28dc933c4f91cdd3137Bob Wilson AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1d64QPseudo)) 725168f382dc67e5940cabdb28dc933c4f91cdd3137Bob Wilson .addFrameIndex(FI).addImm(16) 726168f382dc67e5940cabdb28dc933c4f91cdd3137Bob Wilson .addReg(SrcReg, getKillRegState(isKill)) 727168f382dc67e5940cabdb28dc933c4f91cdd3137Bob Wilson .addMemOperand(MMO)); 728435d4991779d6a47cadff4ea670b490d8507d6c4Evan Cheng } else { 729435d4991779d6a47cadff4ea670b490d8507d6c4Evan Cheng MachineInstrBuilder MIB = 73073fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMDIA)) 73173fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling .addFrameIndex(FI)) 732435d4991779d6a47cadff4ea670b490d8507d6c4Evan Cheng .addMemOperand(MMO); 733558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI); 734558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI); 735558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI); 736558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI); 737435d4991779d6a47cadff4ea670b490d8507d6c4Evan Cheng } 738ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson break; 739ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson case ARM::QQQQPRRegClassID: { 74022c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng MachineInstrBuilder MIB = 74173fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMDIA)) 74273fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling .addFrameIndex(FI)) 74322c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng .addMemOperand(MMO); 744558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI); 745558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI); 746558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI); 747558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen MIB = AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI); 748558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen MIB = AddDReg(MIB, SrcReg, ARM::dsub_4, 0, TRI); 749558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen MIB = AddDReg(MIB, SrcReg, ARM::dsub_5, 0, TRI); 750558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen MIB = AddDReg(MIB, SrcReg, ARM::dsub_6, 0, TRI); 751558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen AddDReg(MIB, SrcReg, ARM::dsub_7, 0, TRI); 752ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson break; 753ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson } 754ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson default: 755ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson llvm_unreachable("Unknown regclass!"); 756334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 757334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 758334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 75934327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesenunsigned 76034327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund OlesenARMBaseInstrInfo::isStoreToStackSlot(const MachineInstr *MI, 76134327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen int &FrameIndex) const { 76234327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen switch (MI->getOpcode()) { 76334327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen default: break; 7647e3383c007f53b3a00675af225e428cb66ddf404Jim Grosbach case ARM::STRrs: 76534327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen case ARM::t2STRs: // FIXME: don't use t2STRs to access frame. 76634327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen if (MI->getOperand(1).isFI() && 76734327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen MI->getOperand(2).isReg() && 76834327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen MI->getOperand(3).isImm() && 76934327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen MI->getOperand(2).getReg() == 0 && 77034327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen MI->getOperand(3).getImm() == 0) { 77134327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen FrameIndex = MI->getOperand(1).getIndex(); 77234327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen return MI->getOperand(0).getReg(); 77334327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen } 77434327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen break; 7757e3383c007f53b3a00675af225e428cb66ddf404Jim Grosbach case ARM::STRi12: 77634327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen case ARM::t2STRi12: 77734327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen case ARM::tSpill: 77834327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen case ARM::VSTRD: 77934327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen case ARM::VSTRS: 78034327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen if (MI->getOperand(1).isFI() && 78134327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen MI->getOperand(2).isImm() && 78234327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen MI->getOperand(2).getImm() == 0) { 78334327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen FrameIndex = MI->getOperand(1).getIndex(); 78434327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen return MI->getOperand(0).getReg(); 78534327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen } 78634327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen break; 787d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen case ARM::VST1q64Pseudo: 788d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen if (MI->getOperand(0).isFI() && 789d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen MI->getOperand(2).getSubReg() == 0) { 790d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen FrameIndex = MI->getOperand(0).getIndex(); 791d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen return MI->getOperand(2).getReg(); 792d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen } 79331bbc51ac9245bc82c933c9db8358ca9bb558ac5Jakob Stoklund Olesen break; 79473fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMQIA: 795d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen if (MI->getOperand(1).isFI() && 796d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen MI->getOperand(0).getSubReg() == 0) { 797d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen FrameIndex = MI->getOperand(1).getIndex(); 798d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen return MI->getOperand(0).getReg(); 799d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen } 800d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen break; 80134327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen } 80234327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen 80334327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen return 0; 80434327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen} 80534327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen 806334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinvoid ARMBaseInstrInfo:: 807334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinloadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 808334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned DestReg, int FI, 809746ad69e088176819981b4b2c5ac8dcd49f5e60eEvan Cheng const TargetRegisterClass *RC, 810746ad69e088176819981b4b2c5ac8dcd49f5e60eEvan Cheng const TargetRegisterInfo *TRI) const { 811c7f3ace20c325521c68335a1689645b43b06ddf0Chris Lattner DebugLoc DL; 812334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (I != MBB.end()) DL = I->getDebugLoc(); 813249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MachineFunction &MF = *MBB.getParent(); 814249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MachineFrameInfo &MFI = *MF.getFrameInfo(); 81531bc849123011b8eae6bb3c79876d9a3c26a6a1dJim Grosbach unsigned Align = MFI.getObjectAlignment(FI); 816249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MachineMemOperand *MMO = 81759db5496f4fc2ef6111569e542f8b65480ef14c1Chris Lattner MF.getMachineMemOperand( 81859db5496f4fc2ef6111569e542f8b65480ef14c1Chris Lattner MachinePointerInfo(PseudoSourceValue::getFixedStack(FI)), 81959db5496f4fc2ef6111569e542f8b65480ef14c1Chris Lattner MachineMemOperand::MOLoad, 820249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MFI.getObjectSize(FI), 82131bc849123011b8eae6bb3c79876d9a3c26a6a1dJim Grosbach Align); 822334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 8230eb0c7401c34c0b4604f732ce54db995eead14e6Bob Wilson // tGPR is used sometimes in ARM instructions that need to avoid using 8240eb0c7401c34c0b4604f732ce54db995eead14e6Bob Wilson // certain registers. Just treat it as GPR here. 8256ccfc507dc1f7ad8c8964193a2407264ca644f0dJim Grosbach if (RC == ARM::tGPRRegisterClass || RC == ARM::tcGPRRegisterClass 8266ccfc507dc1f7ad8c8964193a2407264ca644f0dJim Grosbach || RC == ARM::rGPRRegisterClass) 8270eb0c7401c34c0b4604f732ce54db995eead14e6Bob Wilson RC = ARM::GPRRegisterClass; 8280eb0c7401c34c0b4604f732ce54db995eead14e6Bob Wilson 829ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson switch (RC->getID()) { 830ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson case ARM::GPRRegClassID: 8313e5561247202bae994dd259a2d8dc4eff8f799f3Jim Grosbach AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::LDRi12), DestReg) 8323e5561247202bae994dd259a2d8dc4eff8f799f3Jim Grosbach .addFrameIndex(FI).addImm(0).addMemOperand(MMO)); 833ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson break; 834ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson case ARM::SPRRegClassID: 835d31c5496d7e1580058b5c6fbc8fd537a641ea590Evan Cheng AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRS), DestReg) 836d31c5496d7e1580058b5c6fbc8fd537a641ea590Evan Cheng .addFrameIndex(FI).addImm(0).addMemOperand(MMO)); 837ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson break; 838ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson case ARM::DPRRegClassID: 839ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson case ARM::DPR_VFP2RegClassID: 840ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson case ARM::DPR_8RegClassID: 841e5165490b7ba24bb2f3043399e0d60e7f3bcf8a5Jim Grosbach AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRD), DestReg) 842249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov .addFrameIndex(FI).addImm(0).addMemOperand(MMO)); 843ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson break; 844ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson case ARM::QPRRegClassID: 845ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson case ARM::QPR_VFP2RegClassID: 846ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson case ARM::QPR_8RegClassID: 8470cfcf93c95af91e809ef740eb0ab368477226b40Jim Grosbach if (Align >= 16 && getRegisterInfo().needsStackRealignment(MF)) { 848168f382dc67e5940cabdb28dc933c4f91cdd3137Bob Wilson AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1q64Pseudo), DestReg) 849f967ca0eaf30325cabe3c1971bf0dba16cf1b027Bob Wilson .addFrameIndex(FI).addImm(16) 85069b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng .addMemOperand(MMO)); 85131bc849123011b8eae6bb3c79876d9a3c26a6a1dJim Grosbach } else { 85273fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMQIA), DestReg) 85369b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng .addFrameIndex(FI) 85469b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng .addMemOperand(MMO)); 85531bc849123011b8eae6bb3c79876d9a3c26a6a1dJim Grosbach } 856ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson break; 857ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson case ARM::QQPRRegClassID: 858ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson case ARM::QQPR_VFP2RegClassID: 859435d4991779d6a47cadff4ea670b490d8507d6c4Evan Cheng if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) { 860168f382dc67e5940cabdb28dc933c4f91cdd3137Bob Wilson AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1d64QPseudo), DestReg) 861168f382dc67e5940cabdb28dc933c4f91cdd3137Bob Wilson .addFrameIndex(FI).addImm(16) 862168f382dc67e5940cabdb28dc933c4f91cdd3137Bob Wilson .addMemOperand(MMO)); 863435d4991779d6a47cadff4ea670b490d8507d6c4Evan Cheng } else { 864435d4991779d6a47cadff4ea670b490d8507d6c4Evan Cheng MachineInstrBuilder MIB = 86573fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMDIA)) 86673fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling .addFrameIndex(FI)) 867435d4991779d6a47cadff4ea670b490d8507d6c4Evan Cheng .addMemOperand(MMO); 868558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::Define, TRI); 869558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::Define, TRI); 870558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::Define, TRI); 871558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen AddDReg(MIB, DestReg, ARM::dsub_3, RegState::Define, TRI); 872435d4991779d6a47cadff4ea670b490d8507d6c4Evan Cheng } 873ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson break; 874ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson case ARM::QQQQPRRegClassID: { 875ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson MachineInstrBuilder MIB = 87673fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMDIA)) 87773fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling .addFrameIndex(FI)) 878ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson .addMemOperand(MMO); 879ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::Define, TRI); 880ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::Define, TRI); 881ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::Define, TRI); 882ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::Define, TRI); 883ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson MIB = AddDReg(MIB, DestReg, ARM::dsub_4, RegState::Define, TRI); 884ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson MIB = AddDReg(MIB, DestReg, ARM::dsub_5, RegState::Define, TRI); 885ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson MIB = AddDReg(MIB, DestReg, ARM::dsub_6, RegState::Define, TRI); 886ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson AddDReg(MIB, DestReg, ARM::dsub_7, RegState::Define, TRI); 887ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson break; 888ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson } 889ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson default: 890ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson llvm_unreachable("Unknown regclass!"); 891334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 892334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 893334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 89434327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesenunsigned 89534327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund OlesenARMBaseInstrInfo::isLoadFromStackSlot(const MachineInstr *MI, 89634327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen int &FrameIndex) const { 89734327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen switch (MI->getOpcode()) { 89834327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen default: break; 8993e5561247202bae994dd259a2d8dc4eff8f799f3Jim Grosbach case ARM::LDRrs: 90034327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen case ARM::t2LDRs: // FIXME: don't use t2LDRs to access frame. 90134327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen if (MI->getOperand(1).isFI() && 90234327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen MI->getOperand(2).isReg() && 90334327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen MI->getOperand(3).isImm() && 90434327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen MI->getOperand(2).getReg() == 0 && 90534327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen MI->getOperand(3).getImm() == 0) { 90634327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen FrameIndex = MI->getOperand(1).getIndex(); 90734327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen return MI->getOperand(0).getReg(); 90834327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen } 90934327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen break; 9103e5561247202bae994dd259a2d8dc4eff8f799f3Jim Grosbach case ARM::LDRi12: 91134327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen case ARM::t2LDRi12: 91234327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen case ARM::tRestore: 91334327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen case ARM::VLDRD: 91434327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen case ARM::VLDRS: 91534327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen if (MI->getOperand(1).isFI() && 91634327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen MI->getOperand(2).isImm() && 91734327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen MI->getOperand(2).getImm() == 0) { 91834327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen FrameIndex = MI->getOperand(1).getIndex(); 919d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen return MI->getOperand(0).getReg(); 920d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen } 921d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen break; 922d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen case ARM::VLD1q64Pseudo: 923d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen if (MI->getOperand(1).isFI() && 924d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen MI->getOperand(0).getSubReg() == 0) { 925d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen FrameIndex = MI->getOperand(1).getIndex(); 92606f264e504d75f0426eea55b9f9e36c780d8a4fcJakob Stoklund Olesen return MI->getOperand(0).getReg(); 92706f264e504d75f0426eea55b9f9e36c780d8a4fcJakob Stoklund Olesen } 92806f264e504d75f0426eea55b9f9e36c780d8a4fcJakob Stoklund Olesen break; 92973fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMQIA: 93006f264e504d75f0426eea55b9f9e36c780d8a4fcJakob Stoklund Olesen if (MI->getOperand(1).isFI() && 93106f264e504d75f0426eea55b9f9e36c780d8a4fcJakob Stoklund Olesen MI->getOperand(0).getSubReg() == 0) { 93206f264e504d75f0426eea55b9f9e36c780d8a4fcJakob Stoklund Olesen FrameIndex = MI->getOperand(1).getIndex(); 93334327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen return MI->getOperand(0).getReg(); 93434327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen } 93534327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen break; 93634327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen } 93734327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen 93834327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen return 0; 93934327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen} 94034327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen 94162b50656ceb854eb0be265d63b2a1d46e7400d8aEvan ChengMachineInstr* 94262b50656ceb854eb0be265d63b2a1d46e7400d8aEvan ChengARMBaseInstrInfo::emitFrameIndexDebugValue(MachineFunction &MF, 9438601a3d4decff0a380e059b037dabf71075497d3Evan Cheng int FrameIx, uint64_t Offset, 94462b50656ceb854eb0be265d63b2a1d46e7400d8aEvan Cheng const MDNode *MDPtr, 94562b50656ceb854eb0be265d63b2a1d46e7400d8aEvan Cheng DebugLoc DL) const { 94662b50656ceb854eb0be265d63b2a1d46e7400d8aEvan Cheng MachineInstrBuilder MIB = BuildMI(MF, DL, get(ARM::DBG_VALUE)) 94762b50656ceb854eb0be265d63b2a1d46e7400d8aEvan Cheng .addFrameIndex(FrameIx).addImm(0).addImm(Offset).addMetadata(MDPtr); 94862b50656ceb854eb0be265d63b2a1d46e7400d8aEvan Cheng return &*MIB; 94962b50656ceb854eb0be265d63b2a1d46e7400d8aEvan Cheng} 95062b50656ceb854eb0be265d63b2a1d46e7400d8aEvan Cheng 95130ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen/// Create a copy of a const pool value. Update CPI to the new index and return 95230ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen/// the label UID. 95330ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesenstatic unsigned duplicateCPV(MachineFunction &MF, unsigned &CPI) { 95430ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen MachineConstantPool *MCP = MF.getConstantPool(); 95530ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 95630ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen 95730ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPI]; 95830ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen assert(MCPE.isMachineConstantPoolEntry() && 95930ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen "Expecting a machine constantpool entry!"); 96030ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen ARMConstantPoolValue *ACPV = 96130ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal); 96230ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen 96330ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen unsigned PCLabelId = AFI->createConstPoolEntryUId(); 96430ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen ARMConstantPoolValue *NewCPV = 0; 96551f5b67395780b8421f4aa6ee998ed51b23dae9dJim Grosbach // FIXME: The below assumes PIC relocation model and that the function 96651f5b67395780b8421f4aa6ee998ed51b23dae9dJim Grosbach // is Thumb mode (t1 or t2). PCAdjustment would be 8 for ARM mode PIC, and 96751f5b67395780b8421f4aa6ee998ed51b23dae9dJim Grosbach // zero for non-PIC in ARM or Thumb. The callers are all of thumb LDR 96851f5b67395780b8421f4aa6ee998ed51b23dae9dJim Grosbach // instructions, so that's probably OK, but is PIC always correct when 96951f5b67395780b8421f4aa6ee998ed51b23dae9dJim Grosbach // we get here? 97030ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen if (ACPV->isGlobalValue()) 97130ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen NewCPV = new ARMConstantPoolValue(ACPV->getGV(), PCLabelId, 97230ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen ARMCP::CPValue, 4); 97330ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen else if (ACPV->isExtSymbol()) 97430ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen NewCPV = new ARMConstantPoolValue(MF.getFunction()->getContext(), 97530ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen ACPV->getSymbol(), PCLabelId, 4); 97630ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen else if (ACPV->isBlockAddress()) 97730ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen NewCPV = new ARMConstantPoolValue(ACPV->getBlockAddress(), PCLabelId, 97830ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen ARMCP::CPBlockAddress, 4); 97951f5b67395780b8421f4aa6ee998ed51b23dae9dJim Grosbach else if (ACPV->isLSDA()) 98051f5b67395780b8421f4aa6ee998ed51b23dae9dJim Grosbach NewCPV = new ARMConstantPoolValue(MF.getFunction(), PCLabelId, 98151f5b67395780b8421f4aa6ee998ed51b23dae9dJim Grosbach ARMCP::CPLSDA, 4); 98230ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen else 98330ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen llvm_unreachable("Unexpected ARM constantpool value type!!"); 98430ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen CPI = MCP->getConstantPoolIndex(NewCPV, MCPE.getAlignment()); 98530ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen return PCLabelId; 98630ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen} 98730ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen 988fdc834046efd427d474e3b899ec69354c05071e0Evan Chengvoid ARMBaseInstrInfo:: 989fdc834046efd427d474e3b899ec69354c05071e0Evan ChengreMaterialize(MachineBasicBlock &MBB, 990fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng MachineBasicBlock::iterator I, 991fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng unsigned DestReg, unsigned SubIdx, 992d57cdd5683ea926e489067364fb7ffe5fd5d35eeEvan Cheng const MachineInstr *Orig, 9939edf7deb37f0f97664f279040fa15d89f32e23d9Jakob Stoklund Olesen const TargetRegisterInfo &TRI) const { 994fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng unsigned Opcode = Orig->getOpcode(); 995fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng switch (Opcode) { 996fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng default: { 997fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig); 9989edf7deb37f0f97664f279040fa15d89f32e23d9Jakob Stoklund Olesen MI->substituteRegister(Orig->getOperand(0).getReg(), DestReg, SubIdx, TRI); 999fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng MBB.insert(I, MI); 1000fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng break; 1001fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng } 1002fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng case ARM::tLDRpci_pic: 1003fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng case ARM::t2LDRpci_pic: { 1004fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng MachineFunction &MF = *MBB.getParent(); 1005fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng unsigned CPI = Orig->getOperand(1).getIndex(); 100630ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen unsigned PCLabelId = duplicateCPV(MF, CPI); 1007fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng MachineInstrBuilder MIB = BuildMI(MBB, I, Orig->getDebugLoc(), get(Opcode), 1008fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng DestReg) 1009fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng .addConstantPoolIndex(CPI).addImm(PCLabelId); 1010fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng (*MIB).setMemRefs(Orig->memoperands_begin(), Orig->memoperands_end()); 1011fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng break; 1012fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng } 1013fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng } 1014fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng} 1015fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng 101630ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund OlesenMachineInstr * 101730ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund OlesenARMBaseInstrInfo::duplicate(MachineInstr *Orig, MachineFunction &MF) const { 101830ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen MachineInstr *MI = TargetInstrInfoImpl::duplicate(Orig, MF); 101930ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen switch(Orig->getOpcode()) { 102030ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen case ARM::tLDRpci_pic: 102130ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen case ARM::t2LDRpci_pic: { 102230ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen unsigned CPI = Orig->getOperand(1).getIndex(); 102330ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen unsigned PCLabelId = duplicateCPV(MF, CPI); 102430ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen Orig->getOperand(1).setIndex(CPI); 102530ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen Orig->getOperand(2).setImm(PCLabelId); 102630ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen break; 102730ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen } 102830ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen } 102930ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen return MI; 103030ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen} 103130ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen 1032506049f29f4f202a8e45feb916cc0264440a7f6dEvan Chengbool ARMBaseInstrInfo::produceSameValue(const MachineInstr *MI0, 1033506049f29f4f202a8e45feb916cc0264440a7f6dEvan Cheng const MachineInstr *MI1) const { 1034d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng int Opcode = MI0->getOpcode(); 10359b82425cb0105fd5704f6b9bcd5e7693b05b1759Evan Cheng if (Opcode == ARM::t2LDRpci || 10369b82425cb0105fd5704f6b9bcd5e7693b05b1759Evan Cheng Opcode == ARM::t2LDRpci_pic || 10379b82425cb0105fd5704f6b9bcd5e7693b05b1759Evan Cheng Opcode == ARM::tLDRpci || 10389b82425cb0105fd5704f6b9bcd5e7693b05b1759Evan Cheng Opcode == ARM::tLDRpci_pic) { 1039d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng if (MI1->getOpcode() != Opcode) 1040d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng return false; 1041d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng if (MI0->getNumOperands() != MI1->getNumOperands()) 1042d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng return false; 1043d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng 1044d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng const MachineOperand &MO0 = MI0->getOperand(1); 1045d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng const MachineOperand &MO1 = MI1->getOperand(1); 1046d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng if (MO0.getOffset() != MO1.getOffset()) 1047d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng return false; 1048d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng 1049d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng const MachineFunction *MF = MI0->getParent()->getParent(); 1050d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng const MachineConstantPool *MCP = MF->getConstantPool(); 1051d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng int CPI0 = MO0.getIndex(); 1052d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng int CPI1 = MO1.getIndex(); 1053d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng const MachineConstantPoolEntry &MCPE0 = MCP->getConstants()[CPI0]; 1054d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng const MachineConstantPoolEntry &MCPE1 = MCP->getConstants()[CPI1]; 1055d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng ARMConstantPoolValue *ACPV0 = 1056d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng static_cast<ARMConstantPoolValue*>(MCPE0.Val.MachineCPVal); 1057d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng ARMConstantPoolValue *ACPV1 = 1058d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng static_cast<ARMConstantPoolValue*>(MCPE1.Val.MachineCPVal); 1059d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng return ACPV0->hasSameValue(ACPV1); 1060d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng } 1061d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng 1062506049f29f4f202a8e45feb916cc0264440a7f6dEvan Cheng return MI0->isIdenticalTo(MI1, MachineInstr::IgnoreVRegDefs); 1063d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng} 1064d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng 10654b722108e2cf8e77157e0879a23789cd44829933Bill Wendling/// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to 10664b722108e2cf8e77157e0879a23789cd44829933Bill Wendling/// determine if two loads are loading from the same base address. It should 10674b722108e2cf8e77157e0879a23789cd44829933Bill Wendling/// only return true if the base pointers are the same and the only differences 10684b722108e2cf8e77157e0879a23789cd44829933Bill Wendling/// between the two addresses is the offset. It also returns the offsets by 10694b722108e2cf8e77157e0879a23789cd44829933Bill Wendling/// reference. 10704b722108e2cf8e77157e0879a23789cd44829933Bill Wendlingbool ARMBaseInstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, 10714b722108e2cf8e77157e0879a23789cd44829933Bill Wendling int64_t &Offset1, 10724b722108e2cf8e77157e0879a23789cd44829933Bill Wendling int64_t &Offset2) const { 10734b722108e2cf8e77157e0879a23789cd44829933Bill Wendling // Don't worry about Thumb: just ARM and Thumb2. 10744b722108e2cf8e77157e0879a23789cd44829933Bill Wendling if (Subtarget.isThumb1Only()) return false; 10754b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 10764b722108e2cf8e77157e0879a23789cd44829933Bill Wendling if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode()) 10774b722108e2cf8e77157e0879a23789cd44829933Bill Wendling return false; 10784b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 10794b722108e2cf8e77157e0879a23789cd44829933Bill Wendling switch (Load1->getMachineOpcode()) { 10804b722108e2cf8e77157e0879a23789cd44829933Bill Wendling default: 10814b722108e2cf8e77157e0879a23789cd44829933Bill Wendling return false; 10823e5561247202bae994dd259a2d8dc4eff8f799f3Jim Grosbach case ARM::LDRi12: 1083c1d30212e911d1e55ff6b25bffefb503708883c3Jim Grosbach case ARM::LDRBi12: 10844b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::LDRD: 10854b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::LDRH: 10864b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::LDRSB: 10874b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::LDRSH: 10884b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::VLDRD: 10894b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::VLDRS: 10904b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::t2LDRi8: 10914b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::t2LDRDi8: 10924b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::t2LDRSHi8: 10934b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::t2LDRi12: 10944b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::t2LDRSHi12: 10954b722108e2cf8e77157e0879a23789cd44829933Bill Wendling break; 10964b722108e2cf8e77157e0879a23789cd44829933Bill Wendling } 10974b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 10984b722108e2cf8e77157e0879a23789cd44829933Bill Wendling switch (Load2->getMachineOpcode()) { 10994b722108e2cf8e77157e0879a23789cd44829933Bill Wendling default: 11004b722108e2cf8e77157e0879a23789cd44829933Bill Wendling return false; 11013e5561247202bae994dd259a2d8dc4eff8f799f3Jim Grosbach case ARM::LDRi12: 1102c1d30212e911d1e55ff6b25bffefb503708883c3Jim Grosbach case ARM::LDRBi12: 11034b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::LDRD: 11044b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::LDRH: 11054b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::LDRSB: 11064b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::LDRSH: 11074b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::VLDRD: 11084b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::VLDRS: 11094b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::t2LDRi8: 11104b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::t2LDRDi8: 11114b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::t2LDRSHi8: 11124b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::t2LDRi12: 11134b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::t2LDRSHi12: 11144b722108e2cf8e77157e0879a23789cd44829933Bill Wendling break; 11154b722108e2cf8e77157e0879a23789cd44829933Bill Wendling } 11164b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 11174b722108e2cf8e77157e0879a23789cd44829933Bill Wendling // Check if base addresses and chain operands match. 11184b722108e2cf8e77157e0879a23789cd44829933Bill Wendling if (Load1->getOperand(0) != Load2->getOperand(0) || 11194b722108e2cf8e77157e0879a23789cd44829933Bill Wendling Load1->getOperand(4) != Load2->getOperand(4)) 11204b722108e2cf8e77157e0879a23789cd44829933Bill Wendling return false; 11214b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 11224b722108e2cf8e77157e0879a23789cd44829933Bill Wendling // Index should be Reg0. 11234b722108e2cf8e77157e0879a23789cd44829933Bill Wendling if (Load1->getOperand(3) != Load2->getOperand(3)) 11244b722108e2cf8e77157e0879a23789cd44829933Bill Wendling return false; 11254b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 11264b722108e2cf8e77157e0879a23789cd44829933Bill Wendling // Determine the offsets. 11274b722108e2cf8e77157e0879a23789cd44829933Bill Wendling if (isa<ConstantSDNode>(Load1->getOperand(1)) && 11284b722108e2cf8e77157e0879a23789cd44829933Bill Wendling isa<ConstantSDNode>(Load2->getOperand(1))) { 11294b722108e2cf8e77157e0879a23789cd44829933Bill Wendling Offset1 = cast<ConstantSDNode>(Load1->getOperand(1))->getSExtValue(); 11304b722108e2cf8e77157e0879a23789cd44829933Bill Wendling Offset2 = cast<ConstantSDNode>(Load2->getOperand(1))->getSExtValue(); 11314b722108e2cf8e77157e0879a23789cd44829933Bill Wendling return true; 11324b722108e2cf8e77157e0879a23789cd44829933Bill Wendling } 11334b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 11344b722108e2cf8e77157e0879a23789cd44829933Bill Wendling return false; 11354b722108e2cf8e77157e0879a23789cd44829933Bill Wendling} 11364b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 11374b722108e2cf8e77157e0879a23789cd44829933Bill Wendling/// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to 11384b722108e2cf8e77157e0879a23789cd44829933Bill Wendling/// determine (in conjuction with areLoadsFromSameBasePtr) if two loads should 11394b722108e2cf8e77157e0879a23789cd44829933Bill Wendling/// be scheduled togther. On some targets if two loads are loading from 11404b722108e2cf8e77157e0879a23789cd44829933Bill Wendling/// addresses in the same cache line, it's better if they are scheduled 11414b722108e2cf8e77157e0879a23789cd44829933Bill Wendling/// together. This function takes two integers that represent the load offsets 11424b722108e2cf8e77157e0879a23789cd44829933Bill Wendling/// from the common base address. It returns true if it decides it's desirable 11434b722108e2cf8e77157e0879a23789cd44829933Bill Wendling/// to schedule the two loads together. "NumLoads" is the number of loads that 11444b722108e2cf8e77157e0879a23789cd44829933Bill Wendling/// have already been scheduled after Load1. 11454b722108e2cf8e77157e0879a23789cd44829933Bill Wendlingbool ARMBaseInstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, 11464b722108e2cf8e77157e0879a23789cd44829933Bill Wendling int64_t Offset1, int64_t Offset2, 11474b722108e2cf8e77157e0879a23789cd44829933Bill Wendling unsigned NumLoads) const { 11484b722108e2cf8e77157e0879a23789cd44829933Bill Wendling // Don't worry about Thumb: just ARM and Thumb2. 11494b722108e2cf8e77157e0879a23789cd44829933Bill Wendling if (Subtarget.isThumb1Only()) return false; 11504b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 11514b722108e2cf8e77157e0879a23789cd44829933Bill Wendling assert(Offset2 > Offset1); 11524b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 11534b722108e2cf8e77157e0879a23789cd44829933Bill Wendling if ((Offset2 - Offset1) / 8 > 64) 11544b722108e2cf8e77157e0879a23789cd44829933Bill Wendling return false; 11554b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 11564b722108e2cf8e77157e0879a23789cd44829933Bill Wendling if (Load1->getMachineOpcode() != Load2->getMachineOpcode()) 11574b722108e2cf8e77157e0879a23789cd44829933Bill Wendling return false; // FIXME: overly conservative? 11584b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 11594b722108e2cf8e77157e0879a23789cd44829933Bill Wendling // Four loads in a row should be sufficient. 11604b722108e2cf8e77157e0879a23789cd44829933Bill Wendling if (NumLoads >= 3) 11614b722108e2cf8e77157e0879a23789cd44829933Bill Wendling return false; 11624b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 11634b722108e2cf8e77157e0879a23789cd44829933Bill Wendling return true; 11644b722108e2cf8e77157e0879a23789cd44829933Bill Wendling} 11654b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 116686050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Chengbool ARMBaseInstrInfo::isSchedulingBoundary(const MachineInstr *MI, 116786050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng const MachineBasicBlock *MBB, 116886050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng const MachineFunction &MF) const { 116957bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach // Debug info is never a scheduling boundary. It's necessary to be explicit 117057bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach // due to the special treatment of IT instructions below, otherwise a 117157bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach // dbg_value followed by an IT will result in the IT instruction being 117257bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach // considered a scheduling hazard, which is wrong. It should be the actual 117357bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach // instruction preceding the dbg_value instruction(s), just like it is 117457bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach // when debug info is not present. 117557bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach if (MI->isDebugValue()) 117657bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach return false; 117757bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach 117886050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // Terminators and labels can't be scheduled around. 117986050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng if (MI->getDesc().isTerminator() || MI->isLabel()) 118086050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng return true; 118186050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng 118286050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // Treat the start of the IT block as a scheduling boundary, but schedule 118386050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // t2IT along with all instructions following it. 118486050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // FIXME: This is a big hammer. But the alternative is to add all potential 118586050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // true and anti dependencies to IT block instructions as implicit operands 118686050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // to the t2IT instruction. The added compile time and complexity does not 118786050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // seem worth it. 118886050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng MachineBasicBlock::const_iterator I = MI; 118957bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach // Make sure to skip any dbg_value instructions 119057bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach while (++I != MBB->end() && I->isDebugValue()) 119157bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach ; 119257bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach if (I != MBB->end() && I->getOpcode() == ARM::t2IT) 119386050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng return true; 119486050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng 119586050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // Don't attempt to schedule around any instruction that defines 119686050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // a stack-oriented pointer, as it's unlikely to be profitable. This 119786050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // saves compile time, because it doesn't require every single 119886050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // stack slot reference to depend on the instruction that does the 119986050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // modification. 120086050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng if (MI->definesRegister(ARM::SP)) 120186050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng return true; 120286050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng 120386050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng return false; 120486050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng} 120586050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng 1206b20b85168c0e9819e6545f08281e9b83c82108f0Owen Andersonbool ARMBaseInstrInfo::isProfitableToIfCvt(MachineBasicBlock &MBB, 12078239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng unsigned NumCyles, 12088239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng unsigned ExtraPredCycles, 1209e3cc84a43d6a4bb6c50f58f3dd8e60e28787509eOwen Anderson float Probability, 1210e3cc84a43d6a4bb6c50f58f3dd8e60e28787509eOwen Anderson float Confidence) const { 12118239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng if (!NumCyles) 121213151432edace19ee867a93b5c14573df4f75d24Evan Cheng return false; 12132bbb76909126db5bed6bde84b16d94ab5de4d372Michael J. Spencer 1214b20b85168c0e9819e6545f08281e9b83c82108f0Owen Anderson // Attempt to estimate the relative costs of predication versus branching. 12158239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng float UnpredCost = Probability * NumCyles; 1216654d5440a477b1f6c89b051107e041a331f78e27Owen Anderson UnpredCost += 1.0; // The branch itself 1217e3cc84a43d6a4bb6c50f58f3dd8e60e28787509eOwen Anderson UnpredCost += (1.0 - Confidence) * Subtarget.getMispredictionPenalty(); 12182bbb76909126db5bed6bde84b16d94ab5de4d372Michael J. Spencer 12198239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng return (float)(NumCyles + ExtraPredCycles) < UnpredCost; 122013151432edace19ee867a93b5c14573df4f75d24Evan Cheng} 12212bbb76909126db5bed6bde84b16d94ab5de4d372Michael J. Spencer 122213151432edace19ee867a93b5c14573df4f75d24Evan Chengbool ARMBaseInstrInfo:: 12238239daf7c83a65a189c352cce3191cdc3bbfe151Evan ChengisProfitableToIfCvt(MachineBasicBlock &TMBB, 12248239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng unsigned TCycles, unsigned TExtra, 12258239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng MachineBasicBlock &FMBB, 12268239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng unsigned FCycles, unsigned FExtra, 1227e3cc84a43d6a4bb6c50f58f3dd8e60e28787509eOwen Anderson float Probability, float Confidence) const { 12288239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng if (!TCycles || !FCycles) 1229b20b85168c0e9819e6545f08281e9b83c82108f0Owen Anderson return false; 12302bbb76909126db5bed6bde84b16d94ab5de4d372Michael J. Spencer 1231b20b85168c0e9819e6545f08281e9b83c82108f0Owen Anderson // Attempt to estimate the relative costs of predication versus branching. 12328239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng float UnpredCost = Probability * TCycles + (1.0 - Probability) * FCycles; 1233654d5440a477b1f6c89b051107e041a331f78e27Owen Anderson UnpredCost += 1.0; // The branch itself 1234e3cc84a43d6a4bb6c50f58f3dd8e60e28787509eOwen Anderson UnpredCost += (1.0 - Confidence) * Subtarget.getMispredictionPenalty(); 12352bbb76909126db5bed6bde84b16d94ab5de4d372Michael J. Spencer 12368239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng return (float)(TCycles + FCycles + TExtra + FExtra) < UnpredCost; 123713151432edace19ee867a93b5c14573df4f75d24Evan Cheng} 123813151432edace19ee867a93b5c14573df4f75d24Evan Cheng 12398fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng/// getInstrPredicate - If instruction is predicated, returns its predicate 12408fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng/// condition, otherwise returns AL. It also returns the condition code 12418fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng/// register by reference. 12425adb66a646e2ec32265263739f5b01c3f50c176aEvan ChengARMCC::CondCodes 12435adb66a646e2ec32265263739f5b01c3f50c176aEvan Chengllvm::getInstrPredicate(const MachineInstr *MI, unsigned &PredReg) { 12448fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng int PIdx = MI->findFirstPredOperandIdx(); 12458fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng if (PIdx == -1) { 12468fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng PredReg = 0; 12478fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng return ARMCC::AL; 12488fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng } 12498fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng 12508fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng PredReg = MI->getOperand(PIdx+1).getReg(); 12518fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng return (ARMCC::CondCodes)MI->getOperand(PIdx).getImm(); 12528fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng} 12538fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng 12548fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng 12556495f63945e8dbde81f03a1dc2ab421993b9a495Evan Chengint llvm::getMatchingCondBranchOpcode(int Opc) { 12565ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng if (Opc == ARM::B) 12575ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng return ARM::Bcc; 12585ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng else if (Opc == ARM::tB) 12595ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng return ARM::tBcc; 12605ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng else if (Opc == ARM::t2B) 12615ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng return ARM::t2Bcc; 12625ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng 12635ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng llvm_unreachable("Unknown unconditional branch opcode!"); 12645ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng return 0; 12655ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng} 12665ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng 12676495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 12686495f63945e8dbde81f03a1dc2ab421993b9a495Evan Chengvoid llvm::emitARMRegPlusImmediate(MachineBasicBlock &MBB, 12696495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MachineBasicBlock::iterator &MBBI, DebugLoc dl, 12706495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned DestReg, unsigned BaseReg, int NumBytes, 12716495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ARMCC::CondCodes Pred, unsigned PredReg, 12726495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng const ARMBaseInstrInfo &TII) { 12736495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng bool isSub = NumBytes < 0; 12746495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (isSub) NumBytes = -NumBytes; 12756495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 12766495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng while (NumBytes) { 12776495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned RotAmt = ARM_AM::getSOImmValRotate(NumBytes); 12786495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned ThisVal = NumBytes & ARM_AM::rotr32(0xFF, RotAmt); 12796495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng assert(ThisVal && "Didn't extract field correctly"); 12806495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 12816495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // We will handle these bits from offset, clear them. 12826495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng NumBytes &= ~ThisVal; 12836495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 12846495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng assert(ARM_AM::getSOImmVal(ThisVal) != -1 && "Bit extraction didn't work?"); 12856495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 12866495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Build the new ADD / SUB. 12876495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned Opc = isSub ? ARM::SUBri : ARM::ADDri; 12886495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg) 12896495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng .addReg(BaseReg, RegState::Kill).addImm(ThisVal) 12906495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng .addImm((unsigned)Pred).addReg(PredReg).addReg(0); 12916495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng BaseReg = DestReg; 12926495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 12936495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng} 12946495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 1295cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Chengbool llvm::rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx, 1296cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng unsigned FrameReg, int &Offset, 1297cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng const ARMBaseInstrInfo &TII) { 12986495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned Opcode = MI.getOpcode(); 12996495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng const TargetInstrDesc &Desc = MI.getDesc(); 13006495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask); 13016495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng bool isSub = false; 1302764ab52dd80310a205c9888bf166d09dab858f90Jim Grosbach 13036495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Memory operands in inline assembly always use AddrMode2. 13046495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (Opcode == ARM::INLINEASM) 13056495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng AddrMode = ARMII::AddrMode2; 1306764ab52dd80310a205c9888bf166d09dab858f90Jim Grosbach 13076495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (Opcode == ARM::ADDri) { 13086495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng Offset += MI.getOperand(FrameRegIdx+1).getImm(); 13096495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (Offset == 0) { 13106495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Turn it into a move. 13116495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MI.setDesc(TII.get(ARM::MOVr)); 13126495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false); 13136495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MI.RemoveOperand(FrameRegIdx+1); 1314cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng Offset = 0; 1315cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng return true; 13166495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } else if (Offset < 0) { 13176495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng Offset = -Offset; 13186495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng isSub = true; 13196495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MI.setDesc(TII.get(ARM::SUBri)); 13206495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 13216495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 13226495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Common case: small offset, fits into instruction. 13236495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (ARM_AM::getSOImmVal(Offset) != -1) { 13246495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Replace the FrameIndex with sp / fp 13256495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false); 13266495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset); 1327cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng Offset = 0; 1328cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng return true; 13296495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 13306495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 13316495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Otherwise, pull as much of the immedidate into this ADDri/SUBri 13326495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // as possible. 13336495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned RotAmt = ARM_AM::getSOImmValRotate(Offset); 13346495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xFF, RotAmt); 13356495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 13366495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // We will handle these bits from offset, clear them. 13376495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng Offset &= ~ThisImmVal; 13386495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 13396495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Get the properly encoded SOImmVal field. 13406495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng assert(ARM_AM::getSOImmVal(ThisImmVal) != -1 && 13416495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng "Bit extraction didn't work?"); 13426495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MI.getOperand(FrameRegIdx+1).ChangeToImmediate(ThisImmVal); 13436495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } else { 13446495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned ImmIdx = 0; 13456495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng int InstrOffs = 0; 13466495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned NumBits = 0; 13476495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned Scale = 1; 13486495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng switch (AddrMode) { 13493e5561247202bae994dd259a2d8dc4eff8f799f3Jim Grosbach case ARMII::AddrMode_i12: { 13503e5561247202bae994dd259a2d8dc4eff8f799f3Jim Grosbach ImmIdx = FrameRegIdx + 1; 13513e5561247202bae994dd259a2d8dc4eff8f799f3Jim Grosbach InstrOffs = MI.getOperand(ImmIdx).getImm(); 13523e5561247202bae994dd259a2d8dc4eff8f799f3Jim Grosbach NumBits = 12; 13533e5561247202bae994dd259a2d8dc4eff8f799f3Jim Grosbach break; 13543e5561247202bae994dd259a2d8dc4eff8f799f3Jim Grosbach } 13556495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng case ARMII::AddrMode2: { 13566495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ImmIdx = FrameRegIdx+2; 13576495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng InstrOffs = ARM_AM::getAM2Offset(MI.getOperand(ImmIdx).getImm()); 13586495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (ARM_AM::getAM2Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub) 13596495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng InstrOffs *= -1; 13606495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng NumBits = 12; 13616495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng break; 13626495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 13636495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng case ARMII::AddrMode3: { 13646495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ImmIdx = FrameRegIdx+2; 13656495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng InstrOffs = ARM_AM::getAM3Offset(MI.getOperand(ImmIdx).getImm()); 13666495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (ARM_AM::getAM3Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub) 13676495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng InstrOffs *= -1; 13686495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng NumBits = 8; 13696495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng break; 13706495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 1371baf31088f1472f48ea5ae81f0b93636cc44ca444Anton Korobeynikov case ARMII::AddrMode4: 1372a44321776ecd96fa0344335d3027758be3386e45Jim Grosbach case ARMII::AddrMode6: 1373cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng // Can't fold any offset even if it's zero. 1374cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng return false; 13756495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng case ARMII::AddrMode5: { 13766495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ImmIdx = FrameRegIdx+1; 13776495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng InstrOffs = ARM_AM::getAM5Offset(MI.getOperand(ImmIdx).getImm()); 13786495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (ARM_AM::getAM5Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub) 13796495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng InstrOffs *= -1; 13806495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng NumBits = 8; 13816495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng Scale = 4; 13826495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng break; 13836495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 13846495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng default: 13856495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng llvm_unreachable("Unsupported addressing mode!"); 13866495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng break; 13876495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 13886495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 13896495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng Offset += InstrOffs * Scale; 13906495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!"); 13916495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (Offset < 0) { 13926495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng Offset = -Offset; 13936495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng isSub = true; 13946495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 13956495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 13966495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Attempt to fold address comp. if opcode has offset bits 13976495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (NumBits > 0) { 13986495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Common case: small offset, fits into instruction. 13996495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MachineOperand &ImmOp = MI.getOperand(ImmIdx); 14006495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng int ImmedOffset = Offset / Scale; 14016495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned Mask = (1 << NumBits) - 1; 14026495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if ((unsigned)Offset <= Mask * Scale) { 14036495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Replace the FrameIndex with sp 14046495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false); 140577aee8e22c36257716c2df2f275724765704f20cJim Grosbach // FIXME: When addrmode2 goes away, this will simplify (like the 140677aee8e22c36257716c2df2f275724765704f20cJim Grosbach // T2 version), as the LDR.i12 versions don't need the encoding 140777aee8e22c36257716c2df2f275724765704f20cJim Grosbach // tricks for the offset value. 140877aee8e22c36257716c2df2f275724765704f20cJim Grosbach if (isSub) { 140977aee8e22c36257716c2df2f275724765704f20cJim Grosbach if (AddrMode == ARMII::AddrMode_i12) 141077aee8e22c36257716c2df2f275724765704f20cJim Grosbach ImmedOffset = -ImmedOffset; 141177aee8e22c36257716c2df2f275724765704f20cJim Grosbach else 141277aee8e22c36257716c2df2f275724765704f20cJim Grosbach ImmedOffset |= 1 << NumBits; 141377aee8e22c36257716c2df2f275724765704f20cJim Grosbach } 14146495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ImmOp.ChangeToImmediate(ImmedOffset); 1415cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng Offset = 0; 1416cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng return true; 14176495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 1418764ab52dd80310a205c9888bf166d09dab858f90Jim Grosbach 14196495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Otherwise, it didn't fit. Pull in what we can to simplify the immed. 14206495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ImmedOffset = ImmedOffset & Mask; 1421063efbf569e46776093ddf50099c98fdbb362167Jim Grosbach if (isSub) { 1422063efbf569e46776093ddf50099c98fdbb362167Jim Grosbach if (AddrMode == ARMII::AddrMode_i12) 1423063efbf569e46776093ddf50099c98fdbb362167Jim Grosbach ImmedOffset = -ImmedOffset; 1424063efbf569e46776093ddf50099c98fdbb362167Jim Grosbach else 1425063efbf569e46776093ddf50099c98fdbb362167Jim Grosbach ImmedOffset |= 1 << NumBits; 1426063efbf569e46776093ddf50099c98fdbb362167Jim Grosbach } 14276495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ImmOp.ChangeToImmediate(ImmedOffset); 14286495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng Offset &= ~(Mask*Scale); 14296495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 14306495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 14316495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 1432cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng Offset = (isSub) ? -Offset : Offset; 1433cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng return Offset == 0; 14346495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng} 1435e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling 1436e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendlingbool ARMBaseInstrInfo:: 1437a99c3e9acd95f5fbfb611e3f807240cd74001142Eric ChristopherAnalyzeCompare(const MachineInstr *MI, unsigned &SrcReg, int &CmpMask, 1438a99c3e9acd95f5fbfb611e3f807240cd74001142Eric Christopher int &CmpValue) const { 1439e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling switch (MI->getOpcode()) { 1440e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling default: break; 144138ae997e63e3e1bb2c8679e01ea74cf8fd0be893Bill Wendling case ARM::CMPri: 144238ae997e63e3e1bb2c8679e01ea74cf8fd0be893Bill Wendling case ARM::CMPzri: 1443e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling case ARM::t2CMPri: 1444e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling case ARM::t2CMPzri: 1445e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling SrcReg = MI->getOperand(0).getReg(); 144604ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif CmpMask = ~0; 1447e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling CmpValue = MI->getOperand(1).getImm(); 1448e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling return true; 144904ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif case ARM::TSTri: 145004ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif case ARM::t2TSTri: 145104ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif SrcReg = MI->getOperand(0).getReg(); 145204ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif CmpMask = MI->getOperand(1).getImm(); 145304ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif CmpValue = 0; 145404ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif return true; 145504ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif } 145604ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif 145704ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif return false; 145804ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif} 145904ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif 146005642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif/// isSuitableForMask - Identify a suitable 'and' instruction that 146105642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif/// operates on the given source register and applies the same mask 146205642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif/// as a 'tst' instruction. Provide a limited look-through for copies. 146305642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif/// When successful, MI will hold the found instruction. 146405642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greifstatic bool isSuitableForMask(MachineInstr *&MI, unsigned SrcReg, 14658ff9bb189ce188452e6cae6ed65cb2745814126cGabor Greif int CmpMask, bool CommonUse) { 146605642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif switch (MI->getOpcode()) { 146704ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif case ARM::ANDri: 146804ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif case ARM::t2ANDri: 146905642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif if (CmpMask != MI->getOperand(2).getImm()) 14708ff9bb189ce188452e6cae6ed65cb2745814126cGabor Greif return false; 147105642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif if (SrcReg == MI->getOperand(CommonUse ? 1 : 0).getReg()) 147204ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif return true; 147304ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif break; 147405642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif case ARM::COPY: { 147505642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif // Walk down one instruction which is potentially an 'and'. 147605642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif const MachineInstr &Copy = *MI; 1477f000a7a212590bfd45e23c05bff5e1b683d25dd6Michael J. Spencer MachineBasicBlock::iterator AND( 1478f000a7a212590bfd45e23c05bff5e1b683d25dd6Michael J. Spencer llvm::next(MachineBasicBlock::iterator(MI))); 147905642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif if (AND == MI->getParent()->end()) return false; 148005642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif MI = AND; 148105642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif return isSuitableForMask(MI, Copy.getOperand(0).getReg(), 148205642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif CmpMask, true); 148305642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif } 1484e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling } 1485e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling 1486e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling return false; 1487e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling} 1488e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling 1489a65568676d0d9d53dd4aae8f1c58271bb4cfff10Bill Wendling/// OptimizeCompareInstr - Convert the instruction supplying the argument to the 1490eb96a2f6c03c0ec97c56a3493ac38024afacc774Evan Cheng/// comparison into one that sets the zero bit in the flags register. 1491e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendlingbool ARMBaseInstrInfo:: 149204ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor GreifOptimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, int CmpMask, 1493eb96a2f6c03c0ec97c56a3493ac38024afacc774Evan Cheng int CmpValue, const MachineRegisterInfo *MRI) const { 14943665661a5708c8adc2727be38b56d1d87ddeb661Bill Wendling if (CmpValue != 0) 149592ad57f066e9f256e4e3d72febf152e68caa80c7Bill Wendling return false; 149692ad57f066e9f256e4e3d72febf152e68caa80c7Bill Wendling 1497b41ee96d76ccf1eec2fd898def4cfd7c16868708Bill Wendling MachineRegisterInfo::def_iterator DI = MRI->def_begin(SrcReg); 1498b41ee96d76ccf1eec2fd898def4cfd7c16868708Bill Wendling if (llvm::next(DI) != MRI->def_end()) 149992ad57f066e9f256e4e3d72febf152e68caa80c7Bill Wendling // Only support one definition. 150092ad57f066e9f256e4e3d72febf152e68caa80c7Bill Wendling return false; 150192ad57f066e9f256e4e3d72febf152e68caa80c7Bill Wendling 150292ad57f066e9f256e4e3d72febf152e68caa80c7Bill Wendling MachineInstr *MI = &*DI; 150392ad57f066e9f256e4e3d72febf152e68caa80c7Bill Wendling 150404ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif // Masked compares sometimes use the same register as the corresponding 'and'. 150504ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif if (CmpMask != ~0) { 150605642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif if (!isSuitableForMask(MI, SrcReg, CmpMask, false)) { 150704ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif MI = 0; 1508b41ee96d76ccf1eec2fd898def4cfd7c16868708Bill Wendling for (MachineRegisterInfo::use_iterator UI = MRI->use_begin(SrcReg), 1509b41ee96d76ccf1eec2fd898def4cfd7c16868708Bill Wendling UE = MRI->use_end(); UI != UE; ++UI) { 151004ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif if (UI->getParent() != CmpInstr->getParent()) continue; 151105642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif MachineInstr *PotentialAND = &*UI; 15128ff9bb189ce188452e6cae6ed65cb2745814126cGabor Greif if (!isSuitableForMask(PotentialAND, SrcReg, CmpMask, true)) 151304ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif continue; 151405642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif MI = PotentialAND; 151504ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif break; 151604ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif } 151704ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif if (!MI) return false; 151804ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif } 151904ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif } 152004ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif 1521e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling // Conservatively refuse to convert an instruction which isn't in the same BB 1522e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling // as the comparison. 1523e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling if (MI->getParent() != CmpInstr->getParent()) 1524e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling return false; 1525e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling 1526e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling // Check that CPSR isn't set between the comparison instruction and the one we 1527e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling // want to change. 1528691e64a54ce899409abe7c131d15ed75e3c1fef5Evan Cheng MachineBasicBlock::const_iterator I = CmpInstr, E = MI, 1529691e64a54ce899409abe7c131d15ed75e3c1fef5Evan Cheng B = MI->getParent()->begin(); 15300aa38b9381a5be42abd4f5ca5baa8c2930d148d3Bill Wendling 15310aa38b9381a5be42abd4f5ca5baa8c2930d148d3Bill Wendling // Early exit if CmpInstr is at the beginning of the BB. 15320aa38b9381a5be42abd4f5ca5baa8c2930d148d3Bill Wendling if (I == B) return false; 15330aa38b9381a5be42abd4f5ca5baa8c2930d148d3Bill Wendling 1534e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling --I; 1535e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling for (; I != E; --I) { 1536e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling const MachineInstr &Instr = *I; 1537e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling 1538e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling for (unsigned IO = 0, EO = Instr.getNumOperands(); IO != EO; ++IO) { 1539e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling const MachineOperand &MO = Instr.getOperand(IO); 154040a5eb18b031fa1a5e9697e21e251e613d441cc5Bill Wendling if (!MO.isReg()) continue; 1541e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling 154240a5eb18b031fa1a5e9697e21e251e613d441cc5Bill Wendling // This instruction modifies or uses CPSR after the one we want to 154340a5eb18b031fa1a5e9697e21e251e613d441cc5Bill Wendling // change. We can't do this transformation. 1544e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling if (MO.getReg() == ARM::CPSR) 1545e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling return false; 1546e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling } 1547691e64a54ce899409abe7c131d15ed75e3c1fef5Evan Cheng 1548691e64a54ce899409abe7c131d15ed75e3c1fef5Evan Cheng if (I == B) 1549691e64a54ce899409abe7c131d15ed75e3c1fef5Evan Cheng // The 'and' is below the comparison instruction. 1550691e64a54ce899409abe7c131d15ed75e3c1fef5Evan Cheng return false; 1551e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling } 1552e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling 1553e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling // Set the "zero" bit in CPSR. 1554e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling switch (MI->getOpcode()) { 1555e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling default: break; 155638ae997e63e3e1bb2c8679e01ea74cf8fd0be893Bill Wendling case ARM::ADDri: 15573a951829fef6a2cfca87611e94cf48e0136f81d5Bob Wilson case ARM::ANDri: 15583a951829fef6a2cfca87611e94cf48e0136f81d5Bob Wilson case ARM::t2ANDri: 155938ae997e63e3e1bb2c8679e01ea74cf8fd0be893Bill Wendling case ARM::SUBri: 156038ae997e63e3e1bb2c8679e01ea74cf8fd0be893Bill Wendling case ARM::t2ADDri: 1561ad422718f9b3224234f52e84d28d8a57a4e89987Bill Wendling case ARM::t2SUBri: 15623642e64c114e636548888c72c21ae023ee0121a7Evan Cheng // Toggle the optional operand to CPSR. 15633642e64c114e636548888c72c21ae023ee0121a7Evan Cheng MI->getOperand(5).setReg(ARM::CPSR); 15643642e64c114e636548888c72c21ae023ee0121a7Evan Cheng MI->getOperand(5).setIsDef(true); 1565e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling CmpInstr->eraseFromParent(); 1566e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling return true; 1567e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling } 1568e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling 1569e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling return false; 1570e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling} 15715f54ce347368105260be2cec497b6a4199dc5789Evan Cheng 1572c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Chengbool ARMBaseInstrInfo::FoldImmediate(MachineInstr *UseMI, 1573c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng MachineInstr *DefMI, unsigned Reg, 1574c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng MachineRegisterInfo *MRI) const { 1575c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng // Fold large immediates into add, sub, or, xor. 1576c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng unsigned DefOpc = DefMI->getOpcode(); 1577c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng if (DefOpc != ARM::t2MOVi32imm && DefOpc != ARM::MOVi32imm) 1578c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng return false; 1579c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng if (!DefMI->getOperand(1).isImm()) 1580c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng // Could be t2MOVi32imm <ga:xx> 1581c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng return false; 1582c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng 1583c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng if (!MRI->hasOneNonDBGUse(Reg)) 1584c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng return false; 1585c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng 1586c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng unsigned UseOpc = UseMI->getOpcode(); 15875c71c7a13715ed6f5bfdd5497172ddec316b68b0Evan Cheng unsigned NewUseOpc = 0; 1588c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng uint32_t ImmVal = (uint32_t)DefMI->getOperand(1).getImm(); 15895c71c7a13715ed6f5bfdd5497172ddec316b68b0Evan Cheng uint32_t SOImmValV1 = 0, SOImmValV2 = 0; 1590c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng bool Commute = false; 1591c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng switch (UseOpc) { 1592c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng default: return false; 1593c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::SUBrr: 1594c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::ADDrr: 1595c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::ORRrr: 1596c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::EORrr: 1597c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::t2SUBrr: 1598c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::t2ADDrr: 1599c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::t2ORRrr: 1600c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::t2EORrr: { 1601c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng Commute = UseMI->getOperand(2).getReg() != Reg; 1602c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng switch (UseOpc) { 1603c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng default: break; 1604c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::SUBrr: { 1605c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng if (Commute) 1606c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng return false; 1607c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng ImmVal = -ImmVal; 1608c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng NewUseOpc = ARM::SUBri; 1609c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng // Fallthrough 1610c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng } 1611c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::ADDrr: 1612c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::ORRrr: 1613c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::EORrr: { 1614c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng if (!ARM_AM::isSOImmTwoPartVal(ImmVal)) 1615c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng return false; 1616c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng SOImmValV1 = (uint32_t)ARM_AM::getSOImmTwoPartFirst(ImmVal); 1617c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng SOImmValV2 = (uint32_t)ARM_AM::getSOImmTwoPartSecond(ImmVal); 1618c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng switch (UseOpc) { 1619c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng default: break; 1620c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::ADDrr: NewUseOpc = ARM::ADDri; break; 1621c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::ORRrr: NewUseOpc = ARM::ORRri; break; 1622c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::EORrr: NewUseOpc = ARM::EORri; break; 1623c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng } 1624c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng break; 1625c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng } 1626c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::t2SUBrr: { 1627c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng if (Commute) 1628c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng return false; 1629c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng ImmVal = -ImmVal; 1630c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng NewUseOpc = ARM::t2SUBri; 1631c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng // Fallthrough 1632c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng } 1633c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::t2ADDrr: 1634c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::t2ORRrr: 1635c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::t2EORrr: { 1636c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng if (!ARM_AM::isT2SOImmTwoPartVal(ImmVal)) 1637c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng return false; 1638c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng SOImmValV1 = (uint32_t)ARM_AM::getT2SOImmTwoPartFirst(ImmVal); 1639c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng SOImmValV2 = (uint32_t)ARM_AM::getT2SOImmTwoPartSecond(ImmVal); 1640c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng switch (UseOpc) { 1641c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng default: break; 1642c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::t2ADDrr: NewUseOpc = ARM::t2ADDri; break; 1643c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::t2ORRrr: NewUseOpc = ARM::t2ORRri; break; 1644c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::t2EORrr: NewUseOpc = ARM::t2EORri; break; 1645c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng } 1646c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng break; 1647c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng } 1648c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng } 1649c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng } 1650c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng } 1651c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng 1652c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng unsigned OpIdx = Commute ? 2 : 1; 1653c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng unsigned Reg1 = UseMI->getOperand(OpIdx).getReg(); 1654c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng bool isKill = UseMI->getOperand(OpIdx).isKill(); 1655c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng unsigned NewReg = MRI->createVirtualRegister(MRI->getRegClass(Reg)); 1656c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng AddDefaultCC(AddDefaultPred(BuildMI(*UseMI->getParent(), 1657c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng *UseMI, UseMI->getDebugLoc(), 1658c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng get(NewUseOpc), NewReg) 1659c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng .addReg(Reg1, getKillRegState(isKill)) 1660c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng .addImm(SOImmValV1))); 1661c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng UseMI->setDesc(get(NewUseOpc)); 1662c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng UseMI->getOperand(1).setReg(NewReg); 1663c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng UseMI->getOperand(1).setIsKill(); 1664c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng UseMI->getOperand(2).ChangeToImmediate(SOImmValV2); 1665c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng DefMI->eraseFromParent(); 1666c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng return true; 1667c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng} 1668c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng 16695f54ce347368105260be2cec497b6a4199dc5789Evan Chengunsigned 16708239daf7c83a65a189c352cce3191cdc3bbfe151Evan ChengARMBaseInstrInfo::getNumMicroOps(const InstrItineraryData *ItinData, 16718239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng const MachineInstr *MI) const { 16723ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng if (!ItinData || ItinData->isEmpty()) 16735f54ce347368105260be2cec497b6a4199dc5789Evan Cheng return 1; 16745f54ce347368105260be2cec497b6a4199dc5789Evan Cheng 16755f54ce347368105260be2cec497b6a4199dc5789Evan Cheng const TargetInstrDesc &Desc = MI->getDesc(); 16765f54ce347368105260be2cec497b6a4199dc5789Evan Cheng unsigned Class = Desc.getSchedClass(); 1677064312de8641043b084603aa9a6b409bc794eed2Bob Wilson unsigned UOps = ItinData->Itineraries[Class].NumMicroOps; 16785f54ce347368105260be2cec497b6a4199dc5789Evan Cheng if (UOps) 16795f54ce347368105260be2cec497b6a4199dc5789Evan Cheng return UOps; 16805f54ce347368105260be2cec497b6a4199dc5789Evan Cheng 16815f54ce347368105260be2cec497b6a4199dc5789Evan Cheng unsigned Opc = MI->getOpcode(); 16825f54ce347368105260be2cec497b6a4199dc5789Evan Cheng switch (Opc) { 16835f54ce347368105260be2cec497b6a4199dc5789Evan Cheng default: 16845f54ce347368105260be2cec497b6a4199dc5789Evan Cheng llvm_unreachable("Unexpected multi-uops instruction!"); 16855f54ce347368105260be2cec497b6a4199dc5789Evan Cheng break; 168673fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMQIA: 168773fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMQDB: 168873fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMQIA: 168973fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMQDB: 16905f54ce347368105260be2cec497b6a4199dc5789Evan Cheng return 2; 16915f54ce347368105260be2cec497b6a4199dc5789Evan Cheng 16925f54ce347368105260be2cec497b6a4199dc5789Evan Cheng // The number of uOps for load / store multiple are determined by the number 16935f54ce347368105260be2cec497b6a4199dc5789Evan Cheng // registers. 169473fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling // 16953ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng // On Cortex-A8, each pair of register loads / stores can be scheduled on the 16963ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng // same cycle. The scheduling for the first load / store must be done 16973ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng // separately by assuming the the address is not 64-bit aligned. 169873fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling // 16993ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng // On Cortex-A9, the formula is simply (#reg / 2) + (#reg % 2). If the address 170073fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling // is not 64-bit aligned, then AGU would take an extra cycle. For VFP / NEON 170173fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling // load / store multiple, the formula is (#reg / 2) + (#reg % 2) + 1. 170273fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMDIA: 170373fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMDDB: 170473fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMDIA_UPD: 170573fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMDDB_UPD: 170673fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMSIA: 170773fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMSDB: 170873fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMSIA_UPD: 170973fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMSDB_UPD: 171073fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMDIA: 171173fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMDDB: 171273fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMDIA_UPD: 171373fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMDDB_UPD: 171473fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMSIA: 171573fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMSDB: 171673fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMSIA_UPD: 171773fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMSDB_UPD: { 17185f54ce347368105260be2cec497b6a4199dc5789Evan Cheng unsigned NumRegs = MI->getNumOperands() - Desc.getNumOperands(); 17195f54ce347368105260be2cec497b6a4199dc5789Evan Cheng return (NumRegs / 2) + (NumRegs % 2) + 1; 17205f54ce347368105260be2cec497b6a4199dc5789Evan Cheng } 172173fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling 172273fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMIA_RET: 172373fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMIA: 172473fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMDA: 172573fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMDB: 172673fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMIB: 172773fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMIA_UPD: 172873fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMDA_UPD: 172973fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMDB_UPD: 173073fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMIB_UPD: 173173fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::STMIA: 173273fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::STMDA: 173373fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::STMDB: 173473fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::STMIB: 173573fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::STMIA_UPD: 173673fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::STMDA_UPD: 173773fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::STMDB_UPD: 173873fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::STMIB_UPD: 173973fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::tLDMIA: 174073fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::tLDMIA_UPD: 174173fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::tSTMIA: 174273fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::tSTMIA_UPD: 17435f54ce347368105260be2cec497b6a4199dc5789Evan Cheng case ARM::tPOP_RET: 17445f54ce347368105260be2cec497b6a4199dc5789Evan Cheng case ARM::tPOP: 17455f54ce347368105260be2cec497b6a4199dc5789Evan Cheng case ARM::tPUSH: 174673fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2LDMIA_RET: 174773fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2LDMIA: 174873fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2LDMDB: 174973fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2LDMIA_UPD: 175073fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2LDMDB_UPD: 175173fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2STMIA: 175273fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2STMDB: 175373fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2STMIA_UPD: 175473fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2STMDB_UPD: { 17553ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng unsigned NumRegs = MI->getNumOperands() - Desc.getNumOperands() + 1; 17563ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng if (Subtarget.isCortexA8()) { 17578239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng if (NumRegs < 4) 17588239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng return 2; 17598239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng // 4 registers would be issued: 2, 2. 17608239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng // 5 registers would be issued: 2, 2, 1. 17618239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng UOps = (NumRegs / 2); 17628239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng if (NumRegs % 2) 17638239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng ++UOps; 17648239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng return UOps; 17653ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng } else if (Subtarget.isCortexA9()) { 17663ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng UOps = (NumRegs / 2); 17673ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng // If there are odd number of registers or if it's not 64-bit aligned, 17683ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng // then it takes an extra AGU (Address Generation Unit) cycle. 17693ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng if ((NumRegs % 2) || 17703ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng !MI->hasOneMemOperand() || 17713ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng (*MI->memoperands_begin())->getAlignment() < 8) 17723ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng ++UOps; 17733ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng return UOps; 17743ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng } else { 17753ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng // Assume the worst. 17763ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng return NumRegs; 17772bbb76909126db5bed6bde84b16d94ab5de4d372Michael J. Spencer } 17785f54ce347368105260be2cec497b6a4199dc5789Evan Cheng } 17795f54ce347368105260be2cec497b6a4199dc5789Evan Cheng } 17805f54ce347368105260be2cec497b6a4199dc5789Evan Cheng} 1781a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng 1782a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Chengint 1783344d9db97062736cd66da6c07baa9108b6cfa419Evan ChengARMBaseInstrInfo::getVLDMDefCycle(const InstrItineraryData *ItinData, 1784344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng const TargetInstrDesc &DefTID, 1785344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng unsigned DefClass, 1786344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng unsigned DefIdx, unsigned DefAlign) const { 1787344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng int RegNo = (int)(DefIdx+1) - DefTID.getNumOperands() + 1; 1788344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng if (RegNo <= 0) 1789344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // Def is the address writeback. 1790344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng return ItinData->getOperandCycle(DefClass, DefIdx); 1791344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng 1792344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng int DefCycle; 1793344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng if (Subtarget.isCortexA8()) { 1794344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // (regno / 2) + (regno % 2) + 1 1795344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng DefCycle = RegNo / 2 + 1; 1796344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng if (RegNo % 2) 1797344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng ++DefCycle; 1798344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng } else if (Subtarget.isCortexA9()) { 1799344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng DefCycle = RegNo; 1800344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng bool isSLoad = false; 180173fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling 1802344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng switch (DefTID.getOpcode()) { 1803344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng default: break; 180473fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMSIA: 180573fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMSDB: 180673fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMSIA_UPD: 180773fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMSDB_UPD: 1808344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng isSLoad = true; 1809344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng break; 1810344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng } 181173fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling 1812344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // If there are odd number of 'S' registers or if it's not 64-bit aligned, 1813344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // then it takes an extra cycle. 1814344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng if ((isSLoad && (RegNo % 2)) || DefAlign < 8) 1815344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng ++DefCycle; 1816344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng } else { 1817344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // Assume the worst. 1818344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng DefCycle = RegNo + 2; 1819344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng } 1820344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng 1821344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng return DefCycle; 1822344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng} 1823344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng 1824344d9db97062736cd66da6c07baa9108b6cfa419Evan Chengint 1825344d9db97062736cd66da6c07baa9108b6cfa419Evan ChengARMBaseInstrInfo::getLDMDefCycle(const InstrItineraryData *ItinData, 1826344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng const TargetInstrDesc &DefTID, 1827344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng unsigned DefClass, 1828344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng unsigned DefIdx, unsigned DefAlign) const { 1829344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng int RegNo = (int)(DefIdx+1) - DefTID.getNumOperands() + 1; 1830344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng if (RegNo <= 0) 1831344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // Def is the address writeback. 1832344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng return ItinData->getOperandCycle(DefClass, DefIdx); 1833344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng 1834344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng int DefCycle; 1835344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng if (Subtarget.isCortexA8()) { 1836344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // 4 registers would be issued: 1, 2, 1. 1837344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // 5 registers would be issued: 1, 2, 2. 1838344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng DefCycle = RegNo / 2; 1839344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng if (DefCycle < 1) 1840344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng DefCycle = 1; 1841344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // Result latency is issue cycle + 2: E2. 1842344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng DefCycle += 2; 1843344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng } else if (Subtarget.isCortexA9()) { 1844344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng DefCycle = (RegNo / 2); 1845344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // If there are odd number of registers or if it's not 64-bit aligned, 1846344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // then it takes an extra AGU (Address Generation Unit) cycle. 1847344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng if ((RegNo % 2) || DefAlign < 8) 1848344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng ++DefCycle; 1849344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // Result latency is AGU cycles + 2. 1850344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng DefCycle += 2; 1851344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng } else { 1852344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // Assume the worst. 1853344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng DefCycle = RegNo + 2; 1854344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng } 1855344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng 1856344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng return DefCycle; 1857344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng} 1858344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng 1859344d9db97062736cd66da6c07baa9108b6cfa419Evan Chengint 1860344d9db97062736cd66da6c07baa9108b6cfa419Evan ChengARMBaseInstrInfo::getVSTMUseCycle(const InstrItineraryData *ItinData, 1861344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng const TargetInstrDesc &UseTID, 1862344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng unsigned UseClass, 1863344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng unsigned UseIdx, unsigned UseAlign) const { 1864344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng int RegNo = (int)(UseIdx+1) - UseTID.getNumOperands() + 1; 1865344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng if (RegNo <= 0) 1866344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng return ItinData->getOperandCycle(UseClass, UseIdx); 1867344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng 1868344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng int UseCycle; 1869344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng if (Subtarget.isCortexA8()) { 1870344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // (regno / 2) + (regno % 2) + 1 1871344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng UseCycle = RegNo / 2 + 1; 1872344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng if (RegNo % 2) 1873344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng ++UseCycle; 1874344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng } else if (Subtarget.isCortexA9()) { 1875344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng UseCycle = RegNo; 1876344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng bool isSStore = false; 187773fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling 1878344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng switch (UseTID.getOpcode()) { 1879344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng default: break; 188073fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMSIA: 188173fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMSDB: 188273fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMSIA_UPD: 188373fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMSDB_UPD: 1884344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng isSStore = true; 1885344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng break; 1886344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng } 188773fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling 1888344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // If there are odd number of 'S' registers or if it's not 64-bit aligned, 1889344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // then it takes an extra cycle. 1890344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng if ((isSStore && (RegNo % 2)) || UseAlign < 8) 1891344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng ++UseCycle; 1892344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng } else { 1893344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // Assume the worst. 1894344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng UseCycle = RegNo + 2; 1895344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng } 1896344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng 1897344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng return UseCycle; 1898344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng} 1899344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng 1900344d9db97062736cd66da6c07baa9108b6cfa419Evan Chengint 1901344d9db97062736cd66da6c07baa9108b6cfa419Evan ChengARMBaseInstrInfo::getSTMUseCycle(const InstrItineraryData *ItinData, 1902344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng const TargetInstrDesc &UseTID, 1903344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng unsigned UseClass, 1904344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng unsigned UseIdx, unsigned UseAlign) const { 1905344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng int RegNo = (int)(UseIdx+1) - UseTID.getNumOperands() + 1; 1906344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng if (RegNo <= 0) 1907344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng return ItinData->getOperandCycle(UseClass, UseIdx); 1908344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng 1909344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng int UseCycle; 1910344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng if (Subtarget.isCortexA8()) { 1911344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng UseCycle = RegNo / 2; 1912344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng if (UseCycle < 2) 1913344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng UseCycle = 2; 1914344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // Read in E3. 1915344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng UseCycle += 2; 1916344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng } else if (Subtarget.isCortexA9()) { 1917344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng UseCycle = (RegNo / 2); 1918344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // If there are odd number of registers or if it's not 64-bit aligned, 1919344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // then it takes an extra AGU (Address Generation Unit) cycle. 1920344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng if ((RegNo % 2) || UseAlign < 8) 1921344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng ++UseCycle; 1922344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng } else { 1923344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // Assume the worst. 1924344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng UseCycle = 1; 1925344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng } 1926344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng return UseCycle; 1927344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng} 1928344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng 1929344d9db97062736cd66da6c07baa9108b6cfa419Evan Chengint 1930a0792de66c8364d47b0a688c7f408efb7b10f31bEvan ChengARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData, 1931a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng const TargetInstrDesc &DefTID, 1932a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng unsigned DefIdx, unsigned DefAlign, 1933a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng const TargetInstrDesc &UseTID, 1934a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng unsigned UseIdx, unsigned UseAlign) const { 1935a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng unsigned DefClass = DefTID.getSchedClass(); 1936a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng unsigned UseClass = UseTID.getSchedClass(); 1937a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng 1938a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng if (DefIdx < DefTID.getNumDefs() && UseIdx < UseTID.getNumOperands()) 1939a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx); 1940a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng 1941a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng // This may be a def / use of a variable_ops instruction, the operand 1942a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng // latency might be determinable dynamically. Let the target try to 1943a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng // figure it out. 19449e08ee5d16b596078e20787f0b5f36121f099333Evan Cheng int DefCycle = -1; 19457e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng bool LdmBypass = false; 1946a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng switch (DefTID.getOpcode()) { 1947a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng default: 1948a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng DefCycle = ItinData->getOperandCycle(DefClass, DefIdx); 1949a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng break; 195073fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling 195173fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMDIA: 195273fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMDDB: 195373fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMDIA_UPD: 195473fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMDDB_UPD: 195573fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMSIA: 195673fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMSDB: 195773fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMSIA_UPD: 195873fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMSDB_UPD: 1959344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng DefCycle = getVLDMDefCycle(ItinData, DefTID, DefClass, DefIdx, DefAlign); 19605a50ceeaea980962c1982ad535226c7ab06c971cEvan Cheng break; 196173fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling 196273fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMIA_RET: 196373fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMIA: 196473fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMDA: 196573fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMDB: 196673fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMIB: 196773fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMIA_UPD: 196873fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMDA_UPD: 196973fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMDB_UPD: 197073fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMIB_UPD: 197173fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::tLDMIA: 197273fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::tLDMIA_UPD: 1973a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng case ARM::tPUSH: 197473fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2LDMIA_RET: 197573fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2LDMIA: 197673fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2LDMDB: 197773fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2LDMIA_UPD: 197873fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2LDMDB_UPD: 1979a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng LdmBypass = 1; 1980344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng DefCycle = getLDMDefCycle(ItinData, DefTID, DefClass, DefIdx, DefAlign); 1981344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng break; 1982a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng } 1983a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng 1984a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng if (DefCycle == -1) 1985a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng // We can't seem to determine the result latency of the def, assume it's 2. 1986a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng DefCycle = 2; 1987a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng 1988a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng int UseCycle = -1; 1989a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng switch (UseTID.getOpcode()) { 1990a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng default: 1991a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng UseCycle = ItinData->getOperandCycle(UseClass, UseIdx); 1992a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng break; 199373fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling 199473fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMDIA: 199573fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMDDB: 199673fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMDIA_UPD: 199773fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMDDB_UPD: 199873fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMSIA: 199973fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMSDB: 200073fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMSIA_UPD: 200173fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMSDB_UPD: 2002344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng UseCycle = getVSTMUseCycle(ItinData, UseTID, UseClass, UseIdx, UseAlign); 20035a50ceeaea980962c1982ad535226c7ab06c971cEvan Cheng break; 200473fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling 200573fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::STMIA: 200673fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::STMDA: 200773fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::STMDB: 200873fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::STMIB: 200973fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::STMIA_UPD: 201073fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::STMDA_UPD: 201173fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::STMDB_UPD: 201273fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::STMIB_UPD: 201373fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::tSTMIA: 201473fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::tSTMIA_UPD: 2015a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng case ARM::tPOP_RET: 2016a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng case ARM::tPOP: 201773fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2STMIA: 201873fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2STMDB: 201973fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2STMIA_UPD: 202073fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2STMDB_UPD: 2021344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng UseCycle = getSTMUseCycle(ItinData, UseTID, UseClass, UseIdx, UseAlign); 20225a50ceeaea980962c1982ad535226c7ab06c971cEvan Cheng break; 2023a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng } 2024a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng 2025a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng if (UseCycle == -1) 2026a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng // Assume it's read in the first stage. 2027a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng UseCycle = 1; 2028a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng 2029a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng UseCycle = DefCycle - UseCycle + 1; 2030a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng if (UseCycle > 0) { 2031a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng if (LdmBypass) { 2032a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng // It's a variable_ops instruction so we can't use DefIdx here. Just use 2033a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng // first def operand. 2034a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng if (ItinData->hasPipelineForwarding(DefClass, DefTID.getNumOperands()-1, 2035a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng UseClass, UseIdx)) 2036a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng --UseCycle; 2037a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng } else if (ItinData->hasPipelineForwarding(DefClass, DefIdx, 203873fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling UseClass, UseIdx)) { 2039a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng --UseCycle; 204073fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling } 2041a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng } 2042a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng 2043a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng return UseCycle; 2044a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng} 2045a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng 2046a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Chengint 2047a0792de66c8364d47b0a688c7f408efb7b10f31bEvan ChengARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData, 2048a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng const MachineInstr *DefMI, unsigned DefIdx, 2049a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng const MachineInstr *UseMI, unsigned UseIdx) const { 2050a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng if (DefMI->isCopyLike() || DefMI->isInsertSubreg() || 2051a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng DefMI->isRegSequence() || DefMI->isImplicitDef()) 2052a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng return 1; 2053a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng 2054a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng const TargetInstrDesc &DefTID = DefMI->getDesc(); 2055a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng if (!ItinData || ItinData->isEmpty()) 2056a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng return DefTID.mayLoad() ? 3 : 1; 2057a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng 2058dd9dd6f857604abdeb5213648ffe50c10ccc59b9Evan Cheng 2059a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng const TargetInstrDesc &UseTID = UseMI->getDesc(); 2060dd9dd6f857604abdeb5213648ffe50c10ccc59b9Evan Cheng const MachineOperand &DefMO = DefMI->getOperand(DefIdx); 2061e09206d4d7683e2a421104c5cb83f7808ba4b06eEvan Cheng if (DefMO.getReg() == ARM::CPSR) { 2062e09206d4d7683e2a421104c5cb83f7808ba4b06eEvan Cheng if (DefMI->getOpcode() == ARM::FMSTAT) { 2063e09206d4d7683e2a421104c5cb83f7808ba4b06eEvan Cheng // fpscr -> cpsr stalls over 20 cycles on A8 (and earlier?) 2064e09206d4d7683e2a421104c5cb83f7808ba4b06eEvan Cheng return Subtarget.isCortexA9() ? 1 : 20; 2065e09206d4d7683e2a421104c5cb83f7808ba4b06eEvan Cheng } 2066e09206d4d7683e2a421104c5cb83f7808ba4b06eEvan Cheng 2067dd9dd6f857604abdeb5213648ffe50c10ccc59b9Evan Cheng // CPSR set and branch can be paired in the same cycle. 2068e09206d4d7683e2a421104c5cb83f7808ba4b06eEvan Cheng if (UseTID.isBranch()) 2069e09206d4d7683e2a421104c5cb83f7808ba4b06eEvan Cheng return 0; 2070e09206d4d7683e2a421104c5cb83f7808ba4b06eEvan Cheng } 2071dd9dd6f857604abdeb5213648ffe50c10ccc59b9Evan Cheng 2072a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng unsigned DefAlign = DefMI->hasOneMemOperand() 2073a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng ? (*DefMI->memoperands_begin())->getAlignment() : 0; 2074a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng unsigned UseAlign = UseMI->hasOneMemOperand() 2075a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng ? (*UseMI->memoperands_begin())->getAlignment() : 0; 20767e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng int Latency = getOperandLatency(ItinData, DefTID, DefIdx, DefAlign, 20777e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng UseTID, UseIdx, UseAlign); 20787e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng 20797e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng if (Latency > 1 && 20807e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng (Subtarget.isCortexA8() || Subtarget.isCortexA9())) { 20817e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng // FIXME: Shifter op hack: no shift (i.e. [r +/- r]) or [r + r << 2] 20827e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng // variants are one cycle cheaper. 20837e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng switch (DefTID.getOpcode()) { 20847e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng default: break; 20857e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng case ARM::LDRrs: 20867e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng case ARM::LDRBrs: { 20877e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng unsigned ShOpVal = DefMI->getOperand(3).getImm(); 20887e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal); 20897e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng if (ShImm == 0 || 20907e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng (ShImm == 2 && ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl)) 20917e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng --Latency; 20927e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng break; 20937e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng } 20947e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng case ARM::t2LDRs: 20957e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng case ARM::t2LDRBs: 20967e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng case ARM::t2LDRHs: 20977e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng case ARM::t2LDRSHs: { 20987e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng // Thumb2 mode: lsl only. 20997e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng unsigned ShAmt = DefMI->getOperand(3).getImm(); 21007e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng if (ShAmt == 0 || ShAmt == 2) 21017e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng --Latency; 21027e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng break; 21037e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng } 21047e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng } 21057e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng } 21067e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng 21077e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng return Latency; 2108a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng} 2109a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng 2110a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Chengint 2111a0792de66c8364d47b0a688c7f408efb7b10f31bEvan ChengARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData, 2112a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng SDNode *DefNode, unsigned DefIdx, 2113a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng SDNode *UseNode, unsigned UseIdx) const { 2114a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng if (!DefNode->isMachineOpcode()) 2115a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng return 1; 2116a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng 2117a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng const TargetInstrDesc &DefTID = get(DefNode->getMachineOpcode()); 2118a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng if (!ItinData || ItinData->isEmpty()) 2119a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng return DefTID.mayLoad() ? 3 : 1; 2120a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng 2121089751535d6e9adf65842e2ca5867bf9a70e1e95Evan Cheng if (!UseNode->isMachineOpcode()) { 2122089751535d6e9adf65842e2ca5867bf9a70e1e95Evan Cheng int Latency = ItinData->getOperandCycle(DefTID.getSchedClass(), DefIdx); 2123089751535d6e9adf65842e2ca5867bf9a70e1e95Evan Cheng if (Subtarget.isCortexA9()) 2124089751535d6e9adf65842e2ca5867bf9a70e1e95Evan Cheng return Latency <= 2 ? 1 : Latency - 1; 2125089751535d6e9adf65842e2ca5867bf9a70e1e95Evan Cheng else 2126089751535d6e9adf65842e2ca5867bf9a70e1e95Evan Cheng return Latency <= 3 ? 1 : Latency - 2; 2127089751535d6e9adf65842e2ca5867bf9a70e1e95Evan Cheng } 2128a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng 2129a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng const TargetInstrDesc &UseTID = get(UseNode->getMachineOpcode()); 2130a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng const MachineSDNode *DefMN = dyn_cast<MachineSDNode>(DefNode); 2131a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng unsigned DefAlign = !DefMN->memoperands_empty() 2132a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng ? (*DefMN->memoperands_begin())->getAlignment() : 0; 2133a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng const MachineSDNode *UseMN = dyn_cast<MachineSDNode>(UseNode); 2134a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng unsigned UseAlign = !UseMN->memoperands_empty() 2135a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng ? (*UseMN->memoperands_begin())->getAlignment() : 0; 21367e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng int Latency = getOperandLatency(ItinData, DefTID, DefIdx, DefAlign, 21377e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng UseTID, UseIdx, UseAlign); 21387e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng 21397e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng if (Latency > 1 && 21407e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng (Subtarget.isCortexA8() || Subtarget.isCortexA9())) { 21417e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng // FIXME: Shifter op hack: no shift (i.e. [r +/- r]) or [r + r << 2] 21427e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng // variants are one cycle cheaper. 21437e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng switch (DefTID.getOpcode()) { 21447e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng default: break; 21457e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng case ARM::LDRrs: 21467e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng case ARM::LDRBrs: { 21477e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng unsigned ShOpVal = 21487e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng cast<ConstantSDNode>(DefNode->getOperand(2))->getZExtValue(); 21497e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal); 21507e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng if (ShImm == 0 || 21517e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng (ShImm == 2 && ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl)) 21527e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng --Latency; 21537e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng break; 21547e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng } 21557e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng case ARM::t2LDRs: 21567e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng case ARM::t2LDRBs: 21577e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng case ARM::t2LDRHs: 21587e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng case ARM::t2LDRSHs: { 21597e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng // Thumb2 mode: lsl only. 21607e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng unsigned ShAmt = 21617e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng cast<ConstantSDNode>(DefNode->getOperand(2))->getZExtValue(); 21627e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng if (ShAmt == 0 || ShAmt == 2) 21637e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng --Latency; 21647e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng break; 21657e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng } 21667e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng } 21677e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng } 21687e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng 21697e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng return Latency; 2170a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng} 21712312842de0c641107dd04d7e056d02491cc781caEvan Cheng 21728239daf7c83a65a189c352cce3191cdc3bbfe151Evan Chengint ARMBaseInstrInfo::getInstrLatency(const InstrItineraryData *ItinData, 21738239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng const MachineInstr *MI, 21748239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng unsigned *PredCost) const { 21758239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng if (MI->isCopyLike() || MI->isInsertSubreg() || 21768239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng MI->isRegSequence() || MI->isImplicitDef()) 21778239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng return 1; 21788239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng 21798239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng if (!ItinData || ItinData->isEmpty()) 21808239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng return 1; 21818239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng 21828239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng const TargetInstrDesc &TID = MI->getDesc(); 21838239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng unsigned Class = TID.getSchedClass(); 21848239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng unsigned UOps = ItinData->Itineraries[Class].NumMicroOps; 21858239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng if (PredCost && TID.hasImplicitDefOfPhysReg(ARM::CPSR)) 21868239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng // When predicated, CPSR is an additional source operand for CPSR updating 21878239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng // instructions, this apparently increases their latencies. 21888239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng *PredCost = 1; 21898239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng if (UOps) 21908239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng return ItinData->getStageLatency(Class); 21918239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng return getNumMicroOps(ItinData, MI); 21928239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng} 21938239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng 21948239daf7c83a65a189c352cce3191cdc3bbfe151Evan Chengint ARMBaseInstrInfo::getInstrLatency(const InstrItineraryData *ItinData, 21958239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng SDNode *Node) const { 21968239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng if (!Node->isMachineOpcode()) 21978239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng return 1; 21988239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng 21998239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng if (!ItinData || ItinData->isEmpty()) 22008239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng return 1; 22018239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng 22028239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng unsigned Opcode = Node->getMachineOpcode(); 22038239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng switch (Opcode) { 22048239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng default: 22058239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng return ItinData->getStageLatency(get(Opcode).getSchedClass()); 220673fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMQIA: 220773fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMQDB: 220873fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMQIA: 220973fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMQDB: 22108239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng return 2; 22118b3ca6216d62bf3f729c2e122dcfeb7c4d7500dcEric Christopher } 22128239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng} 22138239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng 22142312842de0c641107dd04d7e056d02491cc781caEvan Chengbool ARMBaseInstrInfo:: 22152312842de0c641107dd04d7e056d02491cc781caEvan ChenghasHighOperandLatency(const InstrItineraryData *ItinData, 22162312842de0c641107dd04d7e056d02491cc781caEvan Cheng const MachineRegisterInfo *MRI, 22172312842de0c641107dd04d7e056d02491cc781caEvan Cheng const MachineInstr *DefMI, unsigned DefIdx, 22182312842de0c641107dd04d7e056d02491cc781caEvan Cheng const MachineInstr *UseMI, unsigned UseIdx) const { 22192312842de0c641107dd04d7e056d02491cc781caEvan Cheng unsigned DDomain = DefMI->getDesc().TSFlags & ARMII::DomainMask; 22202312842de0c641107dd04d7e056d02491cc781caEvan Cheng unsigned UDomain = UseMI->getDesc().TSFlags & ARMII::DomainMask; 22212312842de0c641107dd04d7e056d02491cc781caEvan Cheng if (Subtarget.isCortexA8() && 22222312842de0c641107dd04d7e056d02491cc781caEvan Cheng (DDomain == ARMII::DomainVFP || UDomain == ARMII::DomainVFP)) 22232312842de0c641107dd04d7e056d02491cc781caEvan Cheng // CortexA8 VFP instructions are not pipelined. 22242312842de0c641107dd04d7e056d02491cc781caEvan Cheng return true; 22252312842de0c641107dd04d7e056d02491cc781caEvan Cheng 22262312842de0c641107dd04d7e056d02491cc781caEvan Cheng // Hoist VFP / NEON instructions with 4 or higher latency. 22272312842de0c641107dd04d7e056d02491cc781caEvan Cheng int Latency = getOperandLatency(ItinData, DefMI, DefIdx, UseMI, UseIdx); 22282312842de0c641107dd04d7e056d02491cc781caEvan Cheng if (Latency <= 3) 22292312842de0c641107dd04d7e056d02491cc781caEvan Cheng return false; 22302312842de0c641107dd04d7e056d02491cc781caEvan Cheng return DDomain == ARMII::DomainVFP || DDomain == ARMII::DomainNEON || 22312312842de0c641107dd04d7e056d02491cc781caEvan Cheng UDomain == ARMII::DomainVFP || UDomain == ARMII::DomainNEON; 22322312842de0c641107dd04d7e056d02491cc781caEvan Cheng} 2233c8141dfc7f983cb04e65d8acd6bcbdc8e4b8a0aeEvan Cheng 2234c8141dfc7f983cb04e65d8acd6bcbdc8e4b8a0aeEvan Chengbool ARMBaseInstrInfo:: 2235c8141dfc7f983cb04e65d8acd6bcbdc8e4b8a0aeEvan ChenghasLowDefLatency(const InstrItineraryData *ItinData, 2236c8141dfc7f983cb04e65d8acd6bcbdc8e4b8a0aeEvan Cheng const MachineInstr *DefMI, unsigned DefIdx) const { 2237c8141dfc7f983cb04e65d8acd6bcbdc8e4b8a0aeEvan Cheng if (!ItinData || ItinData->isEmpty()) 2238c8141dfc7f983cb04e65d8acd6bcbdc8e4b8a0aeEvan Cheng return false; 2239c8141dfc7f983cb04e65d8acd6bcbdc8e4b8a0aeEvan Cheng 2240c8141dfc7f983cb04e65d8acd6bcbdc8e4b8a0aeEvan Cheng unsigned DDomain = DefMI->getDesc().TSFlags & ARMII::DomainMask; 2241c8141dfc7f983cb04e65d8acd6bcbdc8e4b8a0aeEvan Cheng if (DDomain == ARMII::DomainGeneral) { 2242c8141dfc7f983cb04e65d8acd6bcbdc8e4b8a0aeEvan Cheng unsigned DefClass = DefMI->getDesc().getSchedClass(); 2243c8141dfc7f983cb04e65d8acd6bcbdc8e4b8a0aeEvan Cheng int DefCycle = ItinData->getOperandCycle(DefClass, DefIdx); 2244c8141dfc7f983cb04e65d8acd6bcbdc8e4b8a0aeEvan Cheng return (DefCycle != -1 && DefCycle <= 2); 2245c8141dfc7f983cb04e65d8acd6bcbdc8e4b8a0aeEvan Cheng } 2246c8141dfc7f983cb04e65d8acd6bcbdc8e4b8a0aeEvan Cheng return false; 2247c8141dfc7f983cb04e65d8acd6bcbdc8e4b8a0aeEvan Cheng} 224848575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng 224948575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Chengbool 225048575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan ChengARMBaseInstrInfo::isFpMLxInstruction(unsigned Opcode, unsigned &MulOpc, 225148575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng unsigned &AddSubOpc, 225248575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng bool &NegAcc, bool &HasLane) const { 225348575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng DenseMap<unsigned, unsigned>::const_iterator I = MLxEntryMap.find(Opcode); 225448575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng if (I == MLxEntryMap.end()) 225548575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng return false; 225648575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng 225748575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng const ARM_MLxEntry &Entry = ARM_MLxTable[I->second]; 225848575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng MulOpc = Entry.MulOpc; 225948575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng AddSubOpc = Entry.AddSubOpc; 226048575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng NegAcc = Entry.NegAcc; 226148575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng HasLane = Entry.HasLane; 226248575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng return true; 226348575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng} 2264