ARMBaseInstrInfo.cpp revision 5a850beb2e3032e6ff3474ce5317f5454060328c
1334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin//===- ARMBaseInstrInfo.cpp - ARM Instruction Information -----------*- C++ -*-===// 2334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// 3334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// The LLVM Compiler Infrastructure 4334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// 5334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// This file is distributed under the University of Illinois Open Source 6334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// License. See LICENSE.TXT for details. 7334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// 8334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin//===----------------------------------------------------------------------===// 9334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// 10334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// This file contains the Base ARM implementation of the TargetInstrInfo class. 11334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// 12334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin//===----------------------------------------------------------------------===// 13334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 14334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "ARMBaseInstrInfo.h" 15334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "ARM.h" 16334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "ARMAddressingModes.h" 17334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "ARMGenInstrInfo.inc" 18334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "ARMMachineFunctionInfo.h" 19334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "llvm/ADT/STLExtras.h" 20334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "llvm/CodeGen/LiveVariables.h" 21334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "llvm/CodeGen/MachineFrameInfo.h" 22334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "llvm/CodeGen/MachineInstrBuilder.h" 23334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "llvm/CodeGen/MachineJumpTableInfo.h" 24249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov#include "llvm/CodeGen/MachineMemOperand.h" 25249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov#include "llvm/CodeGen/PseudoSourceValue.h" 26af76e592c7f9deff0e55c13dbb4a34f07f1c7f64Chris Lattner#include "llvm/MC/MCAsmInfo.h" 27334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "llvm/Support/CommandLine.h" 28c25e7581b9b8088910da31702d4ca21c4734c6d7Torok Edwin#include "llvm/Support/ErrorHandling.h" 29334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinusing namespace llvm; 30334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 31334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinstatic cl::opt<bool> 32334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinEnableARM3Addr("enable-arm-3-addr-conv", cl::Hidden, 33334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin cl::desc("Enable ARM 2-addr to 3-addr conv")); 34334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 35d90183d25dcbc0eabde56319fed4e8d6ace2e6ebChris LattnerARMBaseInstrInfo::ARMBaseInstrInfo() 366495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng : TargetInstrInfoImpl(ARMInsts, array_lengthof(ARMInsts)) { 37334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 38334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 39334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinMachineInstr * 40334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinARMBaseInstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI, 41334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineBasicBlock::iterator &MBBI, 42334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin LiveVariables *LV) const { 4378703ddafe3d037f75d8ca188e4829d238289ac3Evan Cheng // FIXME: Thumb2 support. 4478703ddafe3d037f75d8ca188e4829d238289ac3Evan Cheng 45334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (!EnableARM3Addr) 46334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return NULL; 47334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 48334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineInstr *MI = MBBI; 49334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineFunction &MF = *MI->getParent()->getParent(); 50334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned TSFlags = MI->getDesc().TSFlags; 51334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool isPre = false; 52334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin switch ((TSFlags & ARMII::IndexModeMask) >> ARMII::IndexModeShift) { 53334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin default: return NULL; 54334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMII::IndexModePre: 55334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin isPre = true; 56334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin break; 57334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMII::IndexModePost: 58334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin break; 59334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 60334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 61334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Try splitting an indexed load/store to an un-indexed one plus an add/sub 62334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // operation. 63334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned MemOpc = getUnindexedOpcode(MI->getOpcode()); 64334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (MemOpc == 0) 65334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return NULL; 66334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 67334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineInstr *UpdateMI = NULL; 68334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineInstr *MemMI = NULL; 69334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned AddrMode = (TSFlags & ARMII::AddrModeMask); 70334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const TargetInstrDesc &TID = MI->getDesc(); 71334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned NumOps = TID.getNumOperands(); 72334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool isLoad = !TID.mayStore(); 73334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const MachineOperand &WB = isLoad ? MI->getOperand(1) : MI->getOperand(0); 74334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const MachineOperand &Base = MI->getOperand(2); 75334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const MachineOperand &Offset = MI->getOperand(NumOps-3); 76334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned WBReg = WB.getReg(); 77334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned BaseReg = Base.getReg(); 78334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned OffReg = Offset.getReg(); 79334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned OffImm = MI->getOperand(NumOps-2).getImm(); 80334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin ARMCC::CondCodes Pred = (ARMCC::CondCodes)MI->getOperand(NumOps-1).getImm(); 81334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin switch (AddrMode) { 82334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin default: 83334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin assert(false && "Unknown indexed op!"); 84334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return NULL; 85334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMII::AddrMode2: { 86334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool isSub = ARM_AM::getAM2Op(OffImm) == ARM_AM::sub; 87334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned Amt = ARM_AM::getAM2Offset(OffImm); 88334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (OffReg == 0) { 89e7cbe4118b7ddf05032ff8772a98c51e1637bb5cEvan Cheng if (ARM_AM::getSOImmVal(Amt) == -1) 90334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Can't encode it in a so_imm operand. This transformation will 91334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // add more than 1 instruction. Abandon! 92334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return NULL; 93334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin UpdateMI = BuildMI(MF, MI->getDebugLoc(), 9478703ddafe3d037f75d8ca188e4829d238289ac3Evan Cheng get(isSub ? ARM::SUBri : ARM::ADDri), WBReg) 95e7cbe4118b7ddf05032ff8772a98c51e1637bb5cEvan Cheng .addReg(BaseReg).addImm(Amt) 96334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addImm(Pred).addReg(0).addReg(0); 97334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } else if (Amt != 0) { 98334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin ARM_AM::ShiftOpc ShOpc = ARM_AM::getAM2ShiftOpc(OffImm); 99334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned SOOpc = ARM_AM::getSORegOpc(ShOpc, Amt); 100334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin UpdateMI = BuildMI(MF, MI->getDebugLoc(), 10178703ddafe3d037f75d8ca188e4829d238289ac3Evan Cheng get(isSub ? ARM::SUBrs : ARM::ADDrs), WBReg) 102334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(BaseReg).addReg(OffReg).addReg(0).addImm(SOOpc) 103334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addImm(Pred).addReg(0).addReg(0); 104334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } else 105334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin UpdateMI = BuildMI(MF, MI->getDebugLoc(), 10678703ddafe3d037f75d8ca188e4829d238289ac3Evan Cheng get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg) 107334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(BaseReg).addReg(OffReg) 108334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addImm(Pred).addReg(0).addReg(0); 109334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin break; 110334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 111334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMII::AddrMode3 : { 112334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool isSub = ARM_AM::getAM3Op(OffImm) == ARM_AM::sub; 113334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned Amt = ARM_AM::getAM3Offset(OffImm); 114334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (OffReg == 0) 115334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Immediate is 8-bits. It's guaranteed to fit in a so_imm operand. 116334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin UpdateMI = BuildMI(MF, MI->getDebugLoc(), 11778703ddafe3d037f75d8ca188e4829d238289ac3Evan Cheng get(isSub ? ARM::SUBri : ARM::ADDri), WBReg) 118334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(BaseReg).addImm(Amt) 119334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addImm(Pred).addReg(0).addReg(0); 120334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin else 121334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin UpdateMI = BuildMI(MF, MI->getDebugLoc(), 12278703ddafe3d037f75d8ca188e4829d238289ac3Evan Cheng get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg) 123334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(BaseReg).addReg(OffReg) 124334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addImm(Pred).addReg(0).addReg(0); 125334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin break; 126334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 127334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 128334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 129334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin std::vector<MachineInstr*> NewMIs; 130334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (isPre) { 131334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (isLoad) 132334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MemMI = BuildMI(MF, MI->getDebugLoc(), 133334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin get(MemOpc), MI->getOperand(0).getReg()) 134334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(WBReg).addReg(0).addImm(0).addImm(Pred); 135334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin else 136334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MemMI = BuildMI(MF, MI->getDebugLoc(), 137334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin get(MemOpc)).addReg(MI->getOperand(1).getReg()) 138334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(WBReg).addReg(0).addImm(0).addImm(Pred); 139334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin NewMIs.push_back(MemMI); 140334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin NewMIs.push_back(UpdateMI); 141334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } else { 142334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (isLoad) 143334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MemMI = BuildMI(MF, MI->getDebugLoc(), 144334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin get(MemOpc), MI->getOperand(0).getReg()) 145334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred); 146334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin else 147334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MemMI = BuildMI(MF, MI->getDebugLoc(), 148334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin get(MemOpc)).addReg(MI->getOperand(1).getReg()) 149334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred); 150334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (WB.isDead()) 151334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin UpdateMI->getOperand(0).setIsDead(); 152334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin NewMIs.push_back(UpdateMI); 153334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin NewMIs.push_back(MemMI); 154334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 155334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 156334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Transfer LiveVariables states, kill / dead info. 157334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (LV) { 158334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 159334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineOperand &MO = MI->getOperand(i); 160334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (MO.isReg() && MO.getReg() && 161334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin TargetRegisterInfo::isVirtualRegister(MO.getReg())) { 162334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned Reg = MO.getReg(); 163334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 164334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin LiveVariables::VarInfo &VI = LV->getVarInfo(Reg); 165334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (MO.isDef()) { 166334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineInstr *NewMI = (Reg == WBReg) ? UpdateMI : MemMI; 167334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (MO.isDead()) 168334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin LV->addVirtualRegisterDead(Reg, NewMI); 169334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 170334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (MO.isUse() && MO.isKill()) { 171334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin for (unsigned j = 0; j < 2; ++j) { 172334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Look at the two new MI's in reverse order. 173334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineInstr *NewMI = NewMIs[j]; 174334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (!NewMI->readsRegister(Reg)) 175334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin continue; 176334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin LV->addVirtualRegisterKilled(Reg, NewMI); 177334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (VI.removeKill(MI)) 178334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin VI.Kills.push_back(NewMI); 179334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin break; 180334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 181334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 182334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 183334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 184334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 185334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 186334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MFI->insert(MBBI, NewMIs[1]); 187334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MFI->insert(MBBI, NewMIs[0]); 188334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return NewMIs[0]; 189334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 190334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 191334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// Branch analysis. 192334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinbool 193334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinARMBaseInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB, 194334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineBasicBlock *&FBB, 195334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin SmallVectorImpl<MachineOperand> &Cond, 196334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool AllowModify) const { 197334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // If the block has no terminators, it just falls into the block after it. 198334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineBasicBlock::iterator I = MBB.end(); 199334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) 200334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 201334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 202334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Get the last instruction in the block. 203334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineInstr *LastInst = I; 204334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 205334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // If there is only one terminator instruction, process it. 206334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned LastOpc = LastInst->getOpcode(); 207334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) { 2085ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng if (isUncondBranchOpcode(LastOpc)) { 209334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin TBB = LastInst->getOperand(0).getMBB(); 210334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 211334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 2125ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng if (isCondBranchOpcode(LastOpc)) { 213334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Block ends with fall-through condbranch. 214334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin TBB = LastInst->getOperand(0).getMBB(); 215334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin Cond.push_back(LastInst->getOperand(1)); 216334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin Cond.push_back(LastInst->getOperand(2)); 217334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 218334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 219334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; // Can't handle indirect branch. 220334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 221334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 222334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Get the instruction before it if it is a terminator. 223334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineInstr *SecondLastInst = I; 224334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 225334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // If there are three terminators, we don't know what sort of block this is. 226334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(--I)) 227334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; 228334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 2295ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng // If the block ends with a B and a Bcc, handle it. 230334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned SecondLastOpc = SecondLastInst->getOpcode(); 2315ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng if (isCondBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) { 232334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin TBB = SecondLastInst->getOperand(0).getMBB(); 233334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin Cond.push_back(SecondLastInst->getOperand(1)); 234334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin Cond.push_back(SecondLastInst->getOperand(2)); 235334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin FBB = LastInst->getOperand(0).getMBB(); 236334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 237334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 238334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 239334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // If the block ends with two unconditional branches, handle it. The second 240334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // one is not executed, so remove it. 2415ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng if (isUncondBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) { 242334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin TBB = SecondLastInst->getOperand(0).getMBB(); 243334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin I = LastInst; 244334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (AllowModify) 245334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin I->eraseFromParent(); 246334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 247334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 248334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 249334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // ...likewise if it ends with a branch table followed by an unconditional 250334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // branch. The branch folder can create these, and we must get rid of them for 251334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // correctness of Thumb constant islands. 25283e0e36be8390fee1235783731f6c64aa604b7eeEvan Cheng if (isJumpTableBranchOpcode(SecondLastOpc) && 2535ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng isUncondBranchOpcode(LastOpc)) { 254334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin I = LastInst; 255334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (AllowModify) 256334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin I->eraseFromParent(); 257334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; 258334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 259334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 260334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Otherwise, can't handle this. 261334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; 262334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 263334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 264334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 265334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinunsigned ARMBaseInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const { 266334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineBasicBlock::iterator I = MBB.end(); 267334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (I == MBB.begin()) return 0; 268334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin --I; 2695ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng if (!isUncondBranchOpcode(I->getOpcode()) && 2705ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng !isCondBranchOpcode(I->getOpcode())) 271334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 0; 272334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 273334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Remove the branch. 274334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin I->eraseFromParent(); 275334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 276334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin I = MBB.end(); 277334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 278334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (I == MBB.begin()) return 1; 279334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin --I; 2805ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng if (!isCondBranchOpcode(I->getOpcode())) 281334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 1; 282334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 283334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Remove the branch. 284334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin I->eraseFromParent(); 285334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 2; 286334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 287334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 288334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinunsigned 289334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinARMBaseInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 290334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineBasicBlock *FBB, 291334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const SmallVectorImpl<MachineOperand> &Cond) const { 292334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // FIXME this should probably have a DebugLoc argument 293334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin DebugLoc dl = DebugLoc::getUnknownLoc(); 2946495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 2956495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ARMFunctionInfo *AFI = MBB.getParent()->getInfo<ARMFunctionInfo>(); 2966495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng int BOpc = !AFI->isThumbFunction() 2976495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ? ARM::B : (AFI->isThumb2Function() ? ARM::t2B : ARM::tB); 2986495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng int BccOpc = !AFI->isThumbFunction() 2996495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ? ARM::Bcc : (AFI->isThumb2Function() ? ARM::t2Bcc : ARM::tBcc); 300334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 301334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Shouldn't be a fall through. 302334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin assert(TBB && "InsertBranch must not be told to insert a fallthrough"); 303334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin assert((Cond.size() == 2 || Cond.size() == 0) && 304334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin "ARM branch conditions have two components!"); 305334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 306334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (FBB == 0) { 307334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (Cond.empty()) // Unconditional branch? 308334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin BuildMI(&MBB, dl, get(BOpc)).addMBB(TBB); 309334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin else 310334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin BuildMI(&MBB, dl, get(BccOpc)).addMBB(TBB) 311334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()); 312334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 1; 313334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 314334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 315334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Two-way conditional branch. 316334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin BuildMI(&MBB, dl, get(BccOpc)).addMBB(TBB) 317334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()); 318334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin BuildMI(&MBB, dl, get(BOpc)).addMBB(FBB); 319334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 2; 320334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 321334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 322334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinbool ARMBaseInstrInfo:: 323334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const { 324334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin ARMCC::CondCodes CC = (ARMCC::CondCodes)(int)Cond[0].getImm(); 325334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin Cond[0].setImm(ARMCC::getOppositeCondition(CC)); 326334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 327334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 328334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 329334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinbool ARMBaseInstrInfo:: 330334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinPredicateInstruction(MachineInstr *MI, 331334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const SmallVectorImpl<MachineOperand> &Pred) const { 332334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned Opc = MI->getOpcode(); 3335ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng if (isUncondBranchOpcode(Opc)) { 3345ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng MI->setDesc(get(getMatchingCondBranchOpcode(Opc))); 335334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI->addOperand(MachineOperand::CreateImm(Pred[0].getImm())); 336334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI->addOperand(MachineOperand::CreateReg(Pred[1].getReg(), false)); 337334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; 338334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 339334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 340334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin int PIdx = MI->findFirstPredOperandIdx(); 341334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (PIdx != -1) { 342334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineOperand &PMO = MI->getOperand(PIdx); 343334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin PMO.setImm(Pred[0].getImm()); 344334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI->getOperand(PIdx+1).setReg(Pred[1].getReg()); 345334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; 346334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 347334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 348334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 349334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 350334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinbool ARMBaseInstrInfo:: 351334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinSubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1, 352334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const SmallVectorImpl<MachineOperand> &Pred2) const { 353334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (Pred1.size() > 2 || Pred2.size() > 2) 354334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 355334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 356334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin ARMCC::CondCodes CC1 = (ARMCC::CondCodes)Pred1[0].getImm(); 357334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin ARMCC::CondCodes CC2 = (ARMCC::CondCodes)Pred2[0].getImm(); 358334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (CC1 == CC2) 359334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; 360334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 361334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin switch (CC1) { 362334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin default: 363334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 364334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMCC::AL: 365334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; 366334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMCC::HS: 367334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return CC2 == ARMCC::HI; 368334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMCC::LS: 369334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return CC2 == ARMCC::LO || CC2 == ARMCC::EQ; 370334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMCC::GE: 371334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return CC2 == ARMCC::GT; 372334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMCC::LE: 373334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return CC2 == ARMCC::LT; 374334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 375334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 376334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 377334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinbool ARMBaseInstrInfo::DefinesPredicate(MachineInstr *MI, 378334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin std::vector<MachineOperand> &Pred) const { 3798fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng // FIXME: This confuses implicit_def with optional CPSR def. 380334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const TargetInstrDesc &TID = MI->getDesc(); 381334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (!TID.getImplicitDefs() && !TID.hasOptionalDef()) 382334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 383334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 384334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool Found = false; 385334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 386334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const MachineOperand &MO = MI->getOperand(i); 387334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (MO.isReg() && MO.getReg() == ARM::CPSR) { 388334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin Pred.push_back(MO); 389334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin Found = true; 390334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 391334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 392334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 393334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return Found; 394334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 395334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 396334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 397334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin/// FIXME: Works around a gcc miscompilation with -fstrict-aliasing 398334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinstatic unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT, 399334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned JTI) DISABLE_INLINE; 400334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinstatic unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT, 401334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned JTI) { 402334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return JT[JTI].MBBs.size(); 403334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 404334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 405334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin/// GetInstSize - Return the size of the specified MachineInstr. 406334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin/// 407334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinunsigned ARMBaseInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const { 408334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const MachineBasicBlock &MBB = *MI->getParent(); 409334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const MachineFunction *MF = MBB.getParent(); 41033adcfb4d217f5f23d9bde8ba02b8e48f9605fc5Chris Lattner const MCAsmInfo *MAI = MF->getTarget().getMCAsmInfo(); 411334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 412334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Basic size info comes from the TSFlags field. 413334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const TargetInstrDesc &TID = MI->getDesc(); 414334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned TSFlags = TID.TSFlags; 415334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 416a0ee862f2e3a0d202244e02459ddcf0dca0e8607Evan Cheng unsigned Opc = MI->getOpcode(); 417334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin switch ((TSFlags & ARMII::SizeMask) >> ARMII::SizeShift) { 418334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin default: { 419334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // If this machine instr is an inline asm, measure it. 420334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (MI->getOpcode() == ARM::INLINEASM) 42133adcfb4d217f5f23d9bde8ba02b8e48f9605fc5Chris Lattner return getInlineAsmLength(MI->getOperand(0).getSymbolName(), *MAI); 422334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (MI->isLabel()) 423334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 0; 424a0ee862f2e3a0d202244e02459ddcf0dca0e8607Evan Cheng switch (Opc) { 425334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin default: 426c23197a26f34f559ea9797de51e187087c039c42Torok Edwin llvm_unreachable("Unknown or unset size field for instr!"); 427334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case TargetInstrInfo::IMPLICIT_DEF: 42826207e5bf1123a793bd9b38bcda2f569a6b45ef2Jakob Stoklund Olesen case TargetInstrInfo::KILL: 429334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case TargetInstrInfo::DBG_LABEL: 430334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case TargetInstrInfo::EH_LABEL: 431334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 0; 432334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 433334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin break; 434334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 435789476240d6b6f8ad9366cadf790a82bd41bb0b3Evan Cheng case ARMII::Size8Bytes: return 8; // ARM instruction x 2. 436789476240d6b6f8ad9366cadf790a82bd41bb0b3Evan Cheng case ARMII::Size4Bytes: return 4; // ARM / Thumb2 instruction. 437789476240d6b6f8ad9366cadf790a82bd41bb0b3Evan Cheng case ARMII::Size2Bytes: return 2; // Thumb1 instruction. 438334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMII::SizeSpecial: { 439a0ee862f2e3a0d202244e02459ddcf0dca0e8607Evan Cheng switch (Opc) { 440334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARM::CONSTPOOL_ENTRY: 441334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // If this machine instr is a constant pool entry, its size is recorded as 442334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // operand #2. 443334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return MI->getOperand(2).getImm(); 444789476240d6b6f8ad9366cadf790a82bd41bb0b3Evan Cheng case ARM::Int_eh_sjlj_setjmp: 445cdc17ebc2b2e9e18ac516b9d246a5c5a3af227d3Jim Grosbach return 24; 4465aa1684e5da9a85286bf7d29da419d261a70c2f2Jim Grosbach case ARM::t2Int_eh_sjlj_setjmp: 4475aa1684e5da9a85286bf7d29da419d261a70c2f2Jim Grosbach return 20; 448334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARM::BR_JTr: 449334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARM::BR_JTm: 450334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARM::BR_JTadd: 451a0ee862f2e3a0d202244e02459ddcf0dca0e8607Evan Cheng case ARM::tBR_JTr: 452d26b14c34cbcee1448b86b524578fc51cc979023Evan Cheng case ARM::t2BR_JT: 453d26b14c34cbcee1448b86b524578fc51cc979023Evan Cheng case ARM::t2TBB: 454d26b14c34cbcee1448b86b524578fc51cc979023Evan Cheng case ARM::t2TBH: { 455334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // These are jumptable branches, i.e. a branch followed by an inlined 456d26b14c34cbcee1448b86b524578fc51cc979023Evan Cheng // jumptable. The size is 4 + 4 * number of entries. For TBB, each 457d26b14c34cbcee1448b86b524578fc51cc979023Evan Cheng // entry is one byte; TBH two byte each. 458a0ee862f2e3a0d202244e02459ddcf0dca0e8607Evan Cheng unsigned EntrySize = (Opc == ARM::t2TBB) 459a0ee862f2e3a0d202244e02459ddcf0dca0e8607Evan Cheng ? 1 : ((Opc == ARM::t2TBH) ? 2 : 4); 460334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned NumOps = TID.getNumOperands(); 461334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineOperand JTOP = 462334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI->getOperand(NumOps - (TID.isPredicable() ? 3 : 2)); 463334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned JTI = JTOP.getIndex(); 464334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo(); 465334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables(); 466334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin assert(JTI < JT.size()); 467334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Thumb instructions are 2 byte aligned, but JT entries are 4 byte 468334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // 4 aligned. The assembler / linker may add 2 byte padding just before 469334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // the JT entries. The size does not include this padding; the 470334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // constant islands pass does separate bookkeeping for it. 471334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // FIXME: If we know the size of the function is less than (1 << 16) *2 472334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // bytes, we can use 16-bit entries instead. Then there won't be an 473334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // alignment issue. 47425f7cfc3cccba6f569f29f79ea533bae960b93c0Evan Cheng unsigned InstSize = (Opc == ARM::tBR_JTr || Opc == ARM::t2BR_JT) ? 2 : 4; 47525f7cfc3cccba6f569f29f79ea533bae960b93c0Evan Cheng unsigned NumEntries = getNumJTEntries(JT, JTI); 47625f7cfc3cccba6f569f29f79ea533bae960b93c0Evan Cheng if (Opc == ARM::t2TBB && (NumEntries & 1)) 47725f7cfc3cccba6f569f29f79ea533bae960b93c0Evan Cheng // Make sure the instruction that follows TBB is 2-byte aligned. 47825f7cfc3cccba6f569f29f79ea533bae960b93c0Evan Cheng // FIXME: Constant island pass should insert an "ALIGN" instruction 47925f7cfc3cccba6f569f29f79ea533bae960b93c0Evan Cheng // instead. 48025f7cfc3cccba6f569f29f79ea533bae960b93c0Evan Cheng ++NumEntries; 48125f7cfc3cccba6f569f29f79ea533bae960b93c0Evan Cheng return NumEntries * EntrySize + InstSize; 482334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 483334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin default: 484334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Otherwise, pseudo-instruction sizes are zero. 485334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 0; 486334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 487334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 488334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 489334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 0; // Not reached 490334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 491334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 492334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin/// Return true if the instruction is a register to register move and 493334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin/// leave the source and dest operands in the passed parameters. 494334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin/// 495334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinbool 496334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinARMBaseInstrInfo::isMoveInstr(const MachineInstr &MI, 497334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned &SrcReg, unsigned &DstReg, 498334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned& SrcSubIdx, unsigned& DstSubIdx) const { 499334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin SrcSubIdx = DstSubIdx = 0; // No sub-registers. 500334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 50168e3c6ae49ff67cba98403e43b5bd0c2499caa41Evan Cheng switch (MI.getOpcode()) { 502dced03fc846fa7cd9558ecb8e33ca98ec29bdcf0Evan Cheng default: break; 50368e3c6ae49ff67cba98403e43b5bd0c2499caa41Evan Cheng case ARM::FCPYS: 50468e3c6ae49ff67cba98403e43b5bd0c2499caa41Evan Cheng case ARM::FCPYD: 50568e3c6ae49ff67cba98403e43b5bd0c2499caa41Evan Cheng case ARM::VMOVD: 50668e3c6ae49ff67cba98403e43b5bd0c2499caa41Evan Cheng case ARM::VMOVQ: { 507334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin SrcReg = MI.getOperand(1).getReg(); 508334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin DstReg = MI.getOperand(0).getReg(); 509334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; 510334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 51168e3c6ae49ff67cba98403e43b5bd0c2499caa41Evan Cheng case ARM::MOVr: 51268e3c6ae49ff67cba98403e43b5bd0c2499caa41Evan Cheng case ARM::tMOVr: 51368e3c6ae49ff67cba98403e43b5bd0c2499caa41Evan Cheng case ARM::tMOVgpr2tgpr: 51468e3c6ae49ff67cba98403e43b5bd0c2499caa41Evan Cheng case ARM::tMOVtgpr2gpr: 51568e3c6ae49ff67cba98403e43b5bd0c2499caa41Evan Cheng case ARM::tMOVgpr2gpr: 51668e3c6ae49ff67cba98403e43b5bd0c2499caa41Evan Cheng case ARM::t2MOVr: { 517334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin assert(MI.getDesc().getNumOperands() >= 2 && 518334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI.getOperand(0).isReg() && 519334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI.getOperand(1).isReg() && 520334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin "Invalid ARM MOV instruction"); 521334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin SrcReg = MI.getOperand(1).getReg(); 522334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin DstReg = MI.getOperand(0).getReg(); 523334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; 524334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 52568e3c6ae49ff67cba98403e43b5bd0c2499caa41Evan Cheng } 526334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 527334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 528334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 529334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 530764ab52dd80310a205c9888bf166d09dab858f90Jim Grosbachunsigned 531334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinARMBaseInstrInfo::isLoadFromStackSlot(const MachineInstr *MI, 532334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin int &FrameIndex) const { 533dced03fc846fa7cd9558ecb8e33ca98ec29bdcf0Evan Cheng switch (MI->getOpcode()) { 534dced03fc846fa7cd9558ecb8e33ca98ec29bdcf0Evan Cheng default: break; 535dced03fc846fa7cd9558ecb8e33ca98ec29bdcf0Evan Cheng case ARM::LDR: 536dced03fc846fa7cd9558ecb8e33ca98ec29bdcf0Evan Cheng case ARM::t2LDRs: // FIXME: don't use t2LDRs to access frame. 537334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (MI->getOperand(1).isFI() && 538334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI->getOperand(2).isReg() && 539334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI->getOperand(3).isImm() && 540334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI->getOperand(2).getReg() == 0 && 541334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI->getOperand(3).getImm() == 0) { 542334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin FrameIndex = MI->getOperand(1).getIndex(); 543334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return MI->getOperand(0).getReg(); 544334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 545dced03fc846fa7cd9558ecb8e33ca98ec29bdcf0Evan Cheng break; 546dced03fc846fa7cd9558ecb8e33ca98ec29bdcf0Evan Cheng case ARM::t2LDRi12: 547dced03fc846fa7cd9558ecb8e33ca98ec29bdcf0Evan Cheng case ARM::tRestore: 5485ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin if (MI->getOperand(1).isFI() && 5495ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin MI->getOperand(2).isImm() && 5505ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin MI->getOperand(2).getImm() == 0) { 5515ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin FrameIndex = MI->getOperand(1).getIndex(); 5525ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin return MI->getOperand(0).getReg(); 5535ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin } 554dced03fc846fa7cd9558ecb8e33ca98ec29bdcf0Evan Cheng break; 555dced03fc846fa7cd9558ecb8e33ca98ec29bdcf0Evan Cheng case ARM::FLDD: 556dced03fc846fa7cd9558ecb8e33ca98ec29bdcf0Evan Cheng case ARM::FLDS: 557334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (MI->getOperand(1).isFI() && 558334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI->getOperand(2).isImm() && 559334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI->getOperand(2).getImm() == 0) { 560334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin FrameIndex = MI->getOperand(1).getIndex(); 561334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return MI->getOperand(0).getReg(); 562334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 563dced03fc846fa7cd9558ecb8e33ca98ec29bdcf0Evan Cheng break; 564334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 565334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 566334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 0; 567334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 568334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 569334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinunsigned 570334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinARMBaseInstrInfo::isStoreToStackSlot(const MachineInstr *MI, 571334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin int &FrameIndex) const { 572dced03fc846fa7cd9558ecb8e33ca98ec29bdcf0Evan Cheng switch (MI->getOpcode()) { 573dced03fc846fa7cd9558ecb8e33ca98ec29bdcf0Evan Cheng default: break; 574dced03fc846fa7cd9558ecb8e33ca98ec29bdcf0Evan Cheng case ARM::STR: 575dced03fc846fa7cd9558ecb8e33ca98ec29bdcf0Evan Cheng case ARM::t2STRs: // FIXME: don't use t2STRs to access frame. 576334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (MI->getOperand(1).isFI() && 577334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI->getOperand(2).isReg() && 578334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI->getOperand(3).isImm() && 579334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI->getOperand(2).getReg() == 0 && 580334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI->getOperand(3).getImm() == 0) { 581334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin FrameIndex = MI->getOperand(1).getIndex(); 582334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return MI->getOperand(0).getReg(); 583334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 584dced03fc846fa7cd9558ecb8e33ca98ec29bdcf0Evan Cheng break; 585dced03fc846fa7cd9558ecb8e33ca98ec29bdcf0Evan Cheng case ARM::t2STRi12: 586dced03fc846fa7cd9558ecb8e33ca98ec29bdcf0Evan Cheng case ARM::tSpill: 5875ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin if (MI->getOperand(1).isFI() && 5885ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin MI->getOperand(2).isImm() && 5895ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin MI->getOperand(2).getImm() == 0) { 5905ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin FrameIndex = MI->getOperand(1).getIndex(); 5915ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin return MI->getOperand(0).getReg(); 5925ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin } 593dced03fc846fa7cd9558ecb8e33ca98ec29bdcf0Evan Cheng break; 594dced03fc846fa7cd9558ecb8e33ca98ec29bdcf0Evan Cheng case ARM::FSTD: 5951d2426c4701650846922d312eb742cc55385c721Evan Cheng case ARM::FSTS: 596334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (MI->getOperand(1).isFI() && 597334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI->getOperand(2).isImm() && 598334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI->getOperand(2).getImm() == 0) { 599334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin FrameIndex = MI->getOperand(1).getIndex(); 600334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return MI->getOperand(0).getReg(); 601334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 602dced03fc846fa7cd9558ecb8e33ca98ec29bdcf0Evan Cheng break; 603334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 604334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 605334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 0; 606334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 607334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 608334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinbool 609334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinARMBaseInstrInfo::copyRegToReg(MachineBasicBlock &MBB, 610334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineBasicBlock::iterator I, 611334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned DestReg, unsigned SrcReg, 612334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const TargetRegisterClass *DestRC, 613334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const TargetRegisterClass *SrcRC) const { 614334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin DebugLoc DL = DebugLoc::getUnknownLoc(); 615334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (I != MBB.end()) DL = I->getDebugLoc(); 616334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 617334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (DestRC != SrcRC) { 6186ca0b9e7220911a6d1fccf34e532e69c7e37cd2fAnton Korobeynikov // Allow DPR / DPR_VFP2 / DPR_8 cross-class copies 619e56f9085b1e96f0cc302c678f1c00877676e455eAnton Korobeynikov // Allow QPR / QPR_VFP2 cross-class copies 6206ca0b9e7220911a6d1fccf34e532e69c7e37cd2fAnton Korobeynikov if (DestRC == ARM::DPRRegisterClass) { 6216ca0b9e7220911a6d1fccf34e532e69c7e37cd2fAnton Korobeynikov if (SrcRC == ARM::DPR_VFP2RegisterClass || 6226ca0b9e7220911a6d1fccf34e532e69c7e37cd2fAnton Korobeynikov SrcRC == ARM::DPR_8RegisterClass) { 6236ca0b9e7220911a6d1fccf34e532e69c7e37cd2fAnton Korobeynikov } else 6246ca0b9e7220911a6d1fccf34e532e69c7e37cd2fAnton Korobeynikov return false; 6256ca0b9e7220911a6d1fccf34e532e69c7e37cd2fAnton Korobeynikov } else if (DestRC == ARM::DPR_VFP2RegisterClass) { 6266ca0b9e7220911a6d1fccf34e532e69c7e37cd2fAnton Korobeynikov if (SrcRC == ARM::DPRRegisterClass || 6276ca0b9e7220911a6d1fccf34e532e69c7e37cd2fAnton Korobeynikov SrcRC == ARM::DPR_8RegisterClass) { 6286ca0b9e7220911a6d1fccf34e532e69c7e37cd2fAnton Korobeynikov } else 6296ca0b9e7220911a6d1fccf34e532e69c7e37cd2fAnton Korobeynikov return false; 6306ca0b9e7220911a6d1fccf34e532e69c7e37cd2fAnton Korobeynikov } else if (DestRC == ARM::DPR_8RegisterClass) { 6316ca0b9e7220911a6d1fccf34e532e69c7e37cd2fAnton Korobeynikov if (SrcRC == ARM::DPRRegisterClass || 6326ca0b9e7220911a6d1fccf34e532e69c7e37cd2fAnton Korobeynikov SrcRC == ARM::DPR_VFP2RegisterClass) { 6336ca0b9e7220911a6d1fccf34e532e69c7e37cd2fAnton Korobeynikov } else 6346ca0b9e7220911a6d1fccf34e532e69c7e37cd2fAnton Korobeynikov return false; 635e56f9085b1e96f0cc302c678f1c00877676e455eAnton Korobeynikov } else if ((DestRC == ARM::QPRRegisterClass && 636e56f9085b1e96f0cc302c678f1c00877676e455eAnton Korobeynikov SrcRC == ARM::QPR_VFP2RegisterClass) || 637e56f9085b1e96f0cc302c678f1c00877676e455eAnton Korobeynikov (DestRC == ARM::QPR_VFP2RegisterClass && 638e56f9085b1e96f0cc302c678f1c00877676e455eAnton Korobeynikov SrcRC == ARM::QPRRegisterClass)) { 6396ca0b9e7220911a6d1fccf34e532e69c7e37cd2fAnton Korobeynikov } else 6407bfdca0206f51132b26094c6f83a5ac97ee0f943David Goodwin return false; 641334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 642334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 6437bfdca0206f51132b26094c6f83a5ac97ee0f943David Goodwin if (DestRC == ARM::GPRRegisterClass) { 64408b93c6a70ae59af375f205cfcffeaa3517577abEvan Cheng AddDefaultCC(AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::MOVr), 645dd6f63209cba0003e67470938830de2cb6917336Evan Cheng DestReg).addReg(SrcReg))); 6467bfdca0206f51132b26094c6f83a5ac97ee0f943David Goodwin } else if (DestRC == ARM::SPRRegisterClass) { 647b74bb1a7a471a77e793d90de158aa4bbc67fe94dEvan Cheng AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FCPYS), DestReg) 648334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(SrcReg)); 6497bfdca0206f51132b26094c6f83a5ac97ee0f943David Goodwin } else if ((DestRC == ARM::DPRRegisterClass) || 6506ca0b9e7220911a6d1fccf34e532e69c7e37cd2fAnton Korobeynikov (DestRC == ARM::DPR_VFP2RegisterClass) || 6516ca0b9e7220911a6d1fccf34e532e69c7e37cd2fAnton Korobeynikov (DestRC == ARM::DPR_8RegisterClass)) { 652b74bb1a7a471a77e793d90de158aa4bbc67fe94dEvan Cheng AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FCPYD), DestReg) 653334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(SrcReg)); 654e56f9085b1e96f0cc302c678f1c00877676e455eAnton Korobeynikov } else if (DestRC == ARM::QPRRegisterClass || 655e56f9085b1e96f0cc302c678f1c00877676e455eAnton Korobeynikov DestRC == ARM::QPR_VFP2RegisterClass) { 656b74bb1a7a471a77e793d90de158aa4bbc67fe94dEvan Cheng BuildMI(MBB, I, DL, get(ARM::VMOVQ), DestReg).addReg(SrcReg); 6577bfdca0206f51132b26094c6f83a5ac97ee0f943David Goodwin } else { 658334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 6597bfdca0206f51132b26094c6f83a5ac97ee0f943David Goodwin } 660334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 661334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; 662334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 663334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 664334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinvoid ARMBaseInstrInfo:: 665334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinstoreRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 666334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned SrcReg, bool isKill, int FI, 667334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const TargetRegisterClass *RC) const { 668334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin DebugLoc DL = DebugLoc::getUnknownLoc(); 669334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (I != MBB.end()) DL = I->getDebugLoc(); 670249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MachineFunction &MF = *MBB.getParent(); 671249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MachineFrameInfo &MFI = *MF.getFrameInfo(); 672249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov 673249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MachineMemOperand *MMO = 674ff89dcb06fbd103373436e2d0ae85f252fae2254Evan Cheng MF.getMachineMemOperand(PseudoSourceValue::getFixedStack(FI), 675249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MachineMemOperand::MOStore, 0, 676249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MFI.getObjectSize(FI), 677249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MFI.getObjectAlignment(FI)); 678334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 679334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (RC == ARM::GPRRegisterClass) { 6805732ca084aaa0cd26149e50dd4b487efff37fe41Evan Cheng AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::STR)) 681334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(SrcReg, getKillRegState(isKill)) 682249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov .addFrameIndex(FI).addReg(0).addImm(0).addMemOperand(MMO)); 6836ca0b9e7220911a6d1fccf34e532e69c7e37cd2fAnton Korobeynikov } else if (RC == ARM::DPRRegisterClass || 6846ca0b9e7220911a6d1fccf34e532e69c7e37cd2fAnton Korobeynikov RC == ARM::DPR_VFP2RegisterClass || 6856ca0b9e7220911a6d1fccf34e532e69c7e37cd2fAnton Korobeynikov RC == ARM::DPR_8RegisterClass) { 686b74bb1a7a471a77e793d90de158aa4bbc67fe94dEvan Cheng AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FSTD)) 687334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(SrcReg, getKillRegState(isKill)) 688249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov .addFrameIndex(FI).addImm(0).addMemOperand(MMO)); 689baf31088f1472f48ea5ae81f0b93636cc44ca444Anton Korobeynikov } else if (RC == ARM::SPRRegisterClass) { 690b74bb1a7a471a77e793d90de158aa4bbc67fe94dEvan Cheng AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FSTS)) 691334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(SrcReg, getKillRegState(isKill)) 692249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov .addFrameIndex(FI).addImm(0).addMemOperand(MMO)); 693baf31088f1472f48ea5ae81f0b93636cc44ca444Anton Korobeynikov } else { 694e56f9085b1e96f0cc302c678f1c00877676e455eAnton Korobeynikov assert((RC == ARM::QPRRegisterClass || 695e56f9085b1e96f0cc302c678f1c00877676e455eAnton Korobeynikov RC == ARM::QPR_VFP2RegisterClass) && "Unknown regclass!"); 696baf31088f1472f48ea5ae81f0b93636cc44ca444Anton Korobeynikov // FIXME: Neon instructions should support predicates 697baf31088f1472f48ea5ae81f0b93636cc44ca444Anton Korobeynikov BuildMI(MBB, I, DL, get(ARM::VSTRQ)).addReg(SrcReg, getKillRegState(isKill)) 698249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov .addFrameIndex(FI).addImm(0).addMemOperand(MMO); 699334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 700334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 701334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 702334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinvoid ARMBaseInstrInfo:: 703334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinloadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 704334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned DestReg, int FI, 705334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const TargetRegisterClass *RC) const { 706334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin DebugLoc DL = DebugLoc::getUnknownLoc(); 707334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (I != MBB.end()) DL = I->getDebugLoc(); 708249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MachineFunction &MF = *MBB.getParent(); 709249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MachineFrameInfo &MFI = *MF.getFrameInfo(); 710249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov 711249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MachineMemOperand *MMO = 712ff89dcb06fbd103373436e2d0ae85f252fae2254Evan Cheng MF.getMachineMemOperand(PseudoSourceValue::getFixedStack(FI), 713249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MachineMemOperand::MOLoad, 0, 714249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MFI.getObjectSize(FI), 715249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MFI.getObjectAlignment(FI)); 716334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 717334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (RC == ARM::GPRRegisterClass) { 7185732ca084aaa0cd26149e50dd4b487efff37fe41Evan Cheng AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::LDR), DestReg) 719249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov .addFrameIndex(FI).addReg(0).addImm(0).addMemOperand(MMO)); 7206ca0b9e7220911a6d1fccf34e532e69c7e37cd2fAnton Korobeynikov } else if (RC == ARM::DPRRegisterClass || 7216ca0b9e7220911a6d1fccf34e532e69c7e37cd2fAnton Korobeynikov RC == ARM::DPR_VFP2RegisterClass || 7226ca0b9e7220911a6d1fccf34e532e69c7e37cd2fAnton Korobeynikov RC == ARM::DPR_8RegisterClass) { 723b74bb1a7a471a77e793d90de158aa4bbc67fe94dEvan Cheng AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FLDD), DestReg) 724249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov .addFrameIndex(FI).addImm(0).addMemOperand(MMO)); 725baf31088f1472f48ea5ae81f0b93636cc44ca444Anton Korobeynikov } else if (RC == ARM::SPRRegisterClass) { 726b74bb1a7a471a77e793d90de158aa4bbc67fe94dEvan Cheng AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FLDS), DestReg) 727249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov .addFrameIndex(FI).addImm(0).addMemOperand(MMO)); 728baf31088f1472f48ea5ae81f0b93636cc44ca444Anton Korobeynikov } else { 729e56f9085b1e96f0cc302c678f1c00877676e455eAnton Korobeynikov assert((RC == ARM::QPRRegisterClass || 730e56f9085b1e96f0cc302c678f1c00877676e455eAnton Korobeynikov RC == ARM::QPR_VFP2RegisterClass) && "Unknown regclass!"); 731baf31088f1472f48ea5ae81f0b93636cc44ca444Anton Korobeynikov // FIXME: Neon instructions should support predicates 7325a850beb2e3032e6ff3474ce5317f5454060328cEvan Cheng BuildMI(MBB, I, DL, get(ARM::VLDRQ), DestReg).addFrameIndex(FI).addImm(0). 7335a850beb2e3032e6ff3474ce5317f5454060328cEvan Cheng addMemOperand(MMO); 734334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 735334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 736334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 737334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinMachineInstr *ARMBaseInstrInfo:: 738334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinfoldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI, 739334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const SmallVectorImpl<unsigned> &Ops, int FI) const { 740334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (Ops.size() != 1) return NULL; 741334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 742334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned OpNum = Ops[0]; 743334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned Opc = MI->getOpcode(); 744334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineInstr *NewMI = NULL; 74519068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng if (Opc == ARM::MOVr || Opc == ARM::t2MOVr) { 746334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // If it is updating CPSR, then it cannot be folded. 74719068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng if (MI->getOperand(4).getReg() == ARM::CPSR && !MI->getOperand(4).isDead()) 74819068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng return NULL; 74919068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng unsigned Pred = MI->getOperand(2).getImm(); 75019068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng unsigned PredReg = MI->getOperand(3).getReg(); 75119068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng if (OpNum == 0) { // move -> store 75219068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng unsigned SrcReg = MI->getOperand(1).getReg(); 75319068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng bool isKill = MI->getOperand(1).isKill(); 75419068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng bool isUndef = MI->getOperand(1).isUndef(); 75519068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng if (Opc == ARM::MOVr) 75619068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::STR)) 75719068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef)) 75819068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng .addFrameIndex(FI).addReg(0).addImm(0).addImm(Pred).addReg(PredReg); 75919068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng else // ARM::t2MOVr 76019068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::t2STRi12)) 76119068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef)) 76219068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg); 76319068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng } else { // move -> load 76419068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng unsigned DstReg = MI->getOperand(0).getReg(); 76519068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng bool isDead = MI->getOperand(0).isDead(); 76619068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng bool isUndef = MI->getOperand(0).isUndef(); 76719068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng if (Opc == ARM::MOVr) 76819068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::LDR)) 76919068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng .addReg(DstReg, 77019068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng RegState::Define | 77119068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng getDeadRegState(isDead) | 77219068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng getUndefRegState(isUndef)) 77319068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng .addFrameIndex(FI).addReg(0).addImm(0).addImm(Pred).addReg(PredReg); 77419068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng else // ARM::t2MOVr 77519068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::t2LDRi12)) 77619068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng .addReg(DstReg, 77719068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng RegState::Define | 77819068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng getDeadRegState(isDead) | 77919068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng getUndefRegState(isUndef)) 78019068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg); 781334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 78219068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng } else if (Opc == ARM::tMOVgpr2gpr || 78319068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng Opc == ARM::tMOVtgpr2gpr || 78419068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng Opc == ARM::tMOVgpr2tgpr) { 78519068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng if (OpNum == 0) { // move -> store 78619068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng unsigned SrcReg = MI->getOperand(1).getReg(); 78719068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng bool isKill = MI->getOperand(1).isKill(); 78819068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng bool isUndef = MI->getOperand(1).isUndef(); 78919068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::t2STRi12)) 79019068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef)) 79119068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng .addFrameIndex(FI).addImm(0).addImm(ARMCC::AL).addReg(0); 79219068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng } else { // move -> load 79319068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng unsigned DstReg = MI->getOperand(0).getReg(); 79419068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng bool isDead = MI->getOperand(0).isDead(); 79519068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng bool isUndef = MI->getOperand(0).isUndef(); 79619068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::t2LDRi12)) 79719068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng .addReg(DstReg, 79819068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng RegState::Define | 79919068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng getDeadRegState(isDead) | 80019068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng getUndefRegState(isUndef)) 80119068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng .addFrameIndex(FI).addImm(0).addImm(ARMCC::AL).addReg(0); 80219068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng } 80319068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng } else if (Opc == ARM::FCPYS) { 804334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned Pred = MI->getOperand(2).getImm(); 805334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned PredReg = MI->getOperand(3).getReg(); 806334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (OpNum == 0) { // move -> store 807334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned SrcReg = MI->getOperand(1).getReg(); 808334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool isKill = MI->getOperand(1).isKill(); 809334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool isUndef = MI->getOperand(1).isUndef(); 810b74bb1a7a471a77e793d90de158aa4bbc67fe94dEvan Cheng NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::FSTS)) 811334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef)) 812334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addFrameIndex(FI) 813334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addImm(0).addImm(Pred).addReg(PredReg); 814334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } else { // move -> load 815334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned DstReg = MI->getOperand(0).getReg(); 816334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool isDead = MI->getOperand(0).isDead(); 817334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool isUndef = MI->getOperand(0).isUndef(); 818b74bb1a7a471a77e793d90de158aa4bbc67fe94dEvan Cheng NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::FLDS)) 819334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(DstReg, 820334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin RegState::Define | 821334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin getDeadRegState(isDead) | 822334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin getUndefRegState(isUndef)) 823334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg); 824334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 825334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 826b74bb1a7a471a77e793d90de158aa4bbc67fe94dEvan Cheng else if (Opc == ARM::FCPYD) { 827334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned Pred = MI->getOperand(2).getImm(); 828334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned PredReg = MI->getOperand(3).getReg(); 829334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (OpNum == 0) { // move -> store 830334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned SrcReg = MI->getOperand(1).getReg(); 831334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool isKill = MI->getOperand(1).isKill(); 832334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool isUndef = MI->getOperand(1).isUndef(); 833b74bb1a7a471a77e793d90de158aa4bbc67fe94dEvan Cheng NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::FSTD)) 834334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef)) 835334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg); 836334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } else { // move -> load 837334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned DstReg = MI->getOperand(0).getReg(); 838334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool isDead = MI->getOperand(0).isDead(); 839334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool isUndef = MI->getOperand(0).isUndef(); 840b74bb1a7a471a77e793d90de158aa4bbc67fe94dEvan Cheng NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::FLDD)) 841334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(DstReg, 842334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin RegState::Define | 843334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin getDeadRegState(isDead) | 844334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin getUndefRegState(isUndef)) 845334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg); 846334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 847334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 848334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 849334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return NewMI; 850334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 851334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 852764ab52dd80310a205c9888bf166d09dab858f90Jim GrosbachMachineInstr* 853334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinARMBaseInstrInfo::foldMemoryOperandImpl(MachineFunction &MF, 854334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineInstr* MI, 855334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const SmallVectorImpl<unsigned> &Ops, 856334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineInstr* LoadMI) const { 8571f5c9887544ac2cb39d48e35cc6fa7a7b73ed3b0Evan Cheng // FIXME 858334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 0; 859334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 860334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 861334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinbool 862334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinARMBaseInstrInfo::canFoldMemoryOperand(const MachineInstr *MI, 863229464564243b24fb12cece515d727673e726994Evan Cheng const SmallVectorImpl<unsigned> &Ops) const { 864334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (Ops.size() != 1) return false; 865334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 866334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned Opc = MI->getOpcode(); 8675732ca084aaa0cd26149e50dd4b487efff37fe41Evan Cheng if (Opc == ARM::MOVr || Opc == ARM::t2MOVr) { 868334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // If it is updating CPSR, then it cannot be folded. 869229464564243b24fb12cece515d727673e726994Evan Cheng return MI->getOperand(4).getReg() != ARM::CPSR || 870229464564243b24fb12cece515d727673e726994Evan Cheng MI->getOperand(4).isDead(); 87119068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng } else if (Opc == ARM::tMOVgpr2gpr || 87219068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng Opc == ARM::tMOVtgpr2gpr || 87319068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng Opc == ARM::tMOVgpr2tgpr) { 87419068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng return true; 875b74bb1a7a471a77e793d90de158aa4bbc67fe94dEvan Cheng } else if (Opc == ARM::FCPYS || Opc == ARM::FCPYD) { 876334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; 877b74bb1a7a471a77e793d90de158aa4bbc67fe94dEvan Cheng } else if (Opc == ARM::VMOVD || Opc == ARM::VMOVQ) { 878334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; // FIXME 879334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 880334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 881334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 882334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 8835ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng 8848fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng/// getInstrPredicate - If instruction is predicated, returns its predicate 8858fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng/// condition, otherwise returns AL. It also returns the condition code 8868fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng/// register by reference. 8875adb66a646e2ec32265263739f5b01c3f50c176aEvan ChengARMCC::CondCodes 8885adb66a646e2ec32265263739f5b01c3f50c176aEvan Chengllvm::getInstrPredicate(const MachineInstr *MI, unsigned &PredReg) { 8898fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng int PIdx = MI->findFirstPredOperandIdx(); 8908fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng if (PIdx == -1) { 8918fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng PredReg = 0; 8928fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng return ARMCC::AL; 8938fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng } 8948fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng 8958fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng PredReg = MI->getOperand(PIdx+1).getReg(); 8968fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng return (ARMCC::CondCodes)MI->getOperand(PIdx).getImm(); 8978fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng} 8988fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng 8998fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng 9006495f63945e8dbde81f03a1dc2ab421993b9a495Evan Chengint llvm::getMatchingCondBranchOpcode(int Opc) { 9015ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng if (Opc == ARM::B) 9025ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng return ARM::Bcc; 9035ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng else if (Opc == ARM::tB) 9045ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng return ARM::tBcc; 9055ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng else if (Opc == ARM::t2B) 9065ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng return ARM::t2Bcc; 9075ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng 9085ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng llvm_unreachable("Unknown unconditional branch opcode!"); 9095ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng return 0; 9105ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng} 9115ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng 9126495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 9136495f63945e8dbde81f03a1dc2ab421993b9a495Evan Chengvoid llvm::emitARMRegPlusImmediate(MachineBasicBlock &MBB, 9146495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MachineBasicBlock::iterator &MBBI, DebugLoc dl, 9156495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned DestReg, unsigned BaseReg, int NumBytes, 9166495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ARMCC::CondCodes Pred, unsigned PredReg, 9176495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng const ARMBaseInstrInfo &TII) { 9186495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng bool isSub = NumBytes < 0; 9196495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (isSub) NumBytes = -NumBytes; 9206495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 9216495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng while (NumBytes) { 9226495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned RotAmt = ARM_AM::getSOImmValRotate(NumBytes); 9236495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned ThisVal = NumBytes & ARM_AM::rotr32(0xFF, RotAmt); 9246495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng assert(ThisVal && "Didn't extract field correctly"); 9256495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 9266495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // We will handle these bits from offset, clear them. 9276495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng NumBytes &= ~ThisVal; 9286495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 9296495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng assert(ARM_AM::getSOImmVal(ThisVal) != -1 && "Bit extraction didn't work?"); 9306495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 9316495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Build the new ADD / SUB. 9326495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned Opc = isSub ? ARM::SUBri : ARM::ADDri; 9336495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg) 9346495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng .addReg(BaseReg, RegState::Kill).addImm(ThisVal) 9356495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng .addImm((unsigned)Pred).addReg(PredReg).addReg(0); 9366495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng BaseReg = DestReg; 9376495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 9386495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng} 9396495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 940cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Chengbool llvm::rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx, 941cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng unsigned FrameReg, int &Offset, 942cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng const ARMBaseInstrInfo &TII) { 9436495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned Opcode = MI.getOpcode(); 9446495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng const TargetInstrDesc &Desc = MI.getDesc(); 9456495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask); 9466495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng bool isSub = false; 947764ab52dd80310a205c9888bf166d09dab858f90Jim Grosbach 9486495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Memory operands in inline assembly always use AddrMode2. 9496495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (Opcode == ARM::INLINEASM) 9506495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng AddrMode = ARMII::AddrMode2; 951764ab52dd80310a205c9888bf166d09dab858f90Jim Grosbach 9526495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (Opcode == ARM::ADDri) { 9536495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng Offset += MI.getOperand(FrameRegIdx+1).getImm(); 9546495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (Offset == 0) { 9556495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Turn it into a move. 9566495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MI.setDesc(TII.get(ARM::MOVr)); 9576495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false); 9586495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MI.RemoveOperand(FrameRegIdx+1); 959cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng Offset = 0; 960cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng return true; 9616495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } else if (Offset < 0) { 9626495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng Offset = -Offset; 9636495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng isSub = true; 9646495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MI.setDesc(TII.get(ARM::SUBri)); 9656495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 9666495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 9676495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Common case: small offset, fits into instruction. 9686495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (ARM_AM::getSOImmVal(Offset) != -1) { 9696495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Replace the FrameIndex with sp / fp 9706495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false); 9716495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset); 972cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng Offset = 0; 973cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng return true; 9746495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 9756495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 9766495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Otherwise, pull as much of the immedidate into this ADDri/SUBri 9776495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // as possible. 9786495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned RotAmt = ARM_AM::getSOImmValRotate(Offset); 9796495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xFF, RotAmt); 9806495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 9816495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // We will handle these bits from offset, clear them. 9826495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng Offset &= ~ThisImmVal; 9836495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 9846495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Get the properly encoded SOImmVal field. 9856495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng assert(ARM_AM::getSOImmVal(ThisImmVal) != -1 && 9866495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng "Bit extraction didn't work?"); 9876495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MI.getOperand(FrameRegIdx+1).ChangeToImmediate(ThisImmVal); 9886495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } else { 9896495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned ImmIdx = 0; 9906495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng int InstrOffs = 0; 9916495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned NumBits = 0; 9926495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned Scale = 1; 9936495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng switch (AddrMode) { 9946495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng case ARMII::AddrMode2: { 9956495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ImmIdx = FrameRegIdx+2; 9966495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng InstrOffs = ARM_AM::getAM2Offset(MI.getOperand(ImmIdx).getImm()); 9976495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (ARM_AM::getAM2Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub) 9986495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng InstrOffs *= -1; 9996495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng NumBits = 12; 10006495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng break; 10016495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 10026495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng case ARMII::AddrMode3: { 10036495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ImmIdx = FrameRegIdx+2; 10046495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng InstrOffs = ARM_AM::getAM3Offset(MI.getOperand(ImmIdx).getImm()); 10056495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (ARM_AM::getAM3Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub) 10066495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng InstrOffs *= -1; 10076495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng NumBits = 8; 10086495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng break; 10096495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 1010baf31088f1472f48ea5ae81f0b93636cc44ca444Anton Korobeynikov case ARMII::AddrMode4: 1011cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng // Can't fold any offset even if it's zero. 1012cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng return false; 10136495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng case ARMII::AddrMode5: { 10146495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ImmIdx = FrameRegIdx+1; 10156495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng InstrOffs = ARM_AM::getAM5Offset(MI.getOperand(ImmIdx).getImm()); 10166495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (ARM_AM::getAM5Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub) 10176495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng InstrOffs *= -1; 10186495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng NumBits = 8; 10196495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng Scale = 4; 10206495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng break; 10216495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 10226495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng default: 10236495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng llvm_unreachable("Unsupported addressing mode!"); 10246495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng break; 10256495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 10266495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 10276495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng Offset += InstrOffs * Scale; 10286495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!"); 10296495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (Offset < 0) { 10306495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng Offset = -Offset; 10316495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng isSub = true; 10326495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 10336495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 10346495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Attempt to fold address comp. if opcode has offset bits 10356495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (NumBits > 0) { 10366495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Common case: small offset, fits into instruction. 10376495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MachineOperand &ImmOp = MI.getOperand(ImmIdx); 10386495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng int ImmedOffset = Offset / Scale; 10396495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned Mask = (1 << NumBits) - 1; 10406495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if ((unsigned)Offset <= Mask * Scale) { 10416495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Replace the FrameIndex with sp 10426495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false); 10436495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (isSub) 10446495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ImmedOffset |= 1 << NumBits; 10456495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ImmOp.ChangeToImmediate(ImmedOffset); 1046cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng Offset = 0; 1047cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng return true; 10486495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 1049764ab52dd80310a205c9888bf166d09dab858f90Jim Grosbach 10506495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Otherwise, it didn't fit. Pull in what we can to simplify the immed. 10516495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ImmedOffset = ImmedOffset & Mask; 10526495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (isSub) 10536495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ImmedOffset |= 1 << NumBits; 10546495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ImmOp.ChangeToImmediate(ImmedOffset); 10556495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng Offset &= ~(Mask*Scale); 10566495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 10576495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 10586495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 1059cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng Offset = (isSub) ? -Offset : Offset; 1060cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng return Offset == 0; 10616495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng} 1062