ARMBaseInstrInfo.cpp revision 5b2f9136644c58ae32e00d8317540692a697d1c9
131d157ae1ac2cd9c787dc3c1d28e64c682803844Jia Liu//===-- ARMBaseInstrInfo.cpp - ARM Instruction Information ----------------===// 2334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// 3334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// The LLVM Compiler Infrastructure 4334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// 5334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// This file is distributed under the University of Illinois Open Source 6334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// License. See LICENSE.TXT for details. 7334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// 8334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin//===----------------------------------------------------------------------===// 9334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// 10334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// This file contains the Base ARM implementation of the TargetInstrInfo class. 11334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// 12334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin//===----------------------------------------------------------------------===// 13334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 14334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "ARMBaseInstrInfo.h" 15334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "ARM.h" 160e5233a9e5ee9385c6a940e3985194d77bee0bbbCraig Topper#include "ARMBaseRegisterInfo.h" 17d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng#include "ARMConstantPoolValue.h" 1848575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng#include "ARMHazardRecognizer.h" 19334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "ARMMachineFunctionInfo.h" 20ee04a6d3a40c3017124e3fd89a0db473a2824498Evan Cheng#include "MCTargetDesc/ARMAddressingModes.h" 21fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng#include "llvm/Constants.h" 22fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng#include "llvm/Function.h" 23fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng#include "llvm/GlobalValue.h" 24334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "llvm/CodeGen/LiveVariables.h" 25d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng#include "llvm/CodeGen/MachineConstantPool.h" 26334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "llvm/CodeGen/MachineFrameInfo.h" 27334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "llvm/CodeGen/MachineInstrBuilder.h" 28334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "llvm/CodeGen/MachineJumpTableInfo.h" 29249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov#include "llvm/CodeGen/MachineMemOperand.h" 302457f2c66184e978d4ed8fa9e2128effff26cb0bEvan Cheng#include "llvm/CodeGen/MachineRegisterInfo.h" 31ee04a6d3a40c3017124e3fd89a0db473a2824498Evan Cheng#include "llvm/CodeGen/SelectionDAGNodes.h" 32af76e592c7f9deff0e55c13dbb4a34f07f1c7f64Chris Lattner#include "llvm/MC/MCAsmInfo.h" 33f81b7f6069b27c0a515070dcb392f6828437412fJakub Staszak#include "llvm/Support/BranchProbability.h" 34334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "llvm/Support/CommandLine.h" 35f95215f551949d5e5adfbf4753aa833b9009b77aAnton Korobeynikov#include "llvm/Support/Debug.h" 36c25e7581b9b8088910da31702d4ca21c4734c6d7Torok Edwin#include "llvm/Support/ErrorHandling.h" 3740a5eb18b031fa1a5e9697e21e251e613d441cc5Bill Wendling#include "llvm/ADT/STLExtras.h" 3822fee2dff4c43b551aefa44a96ca74fcade6bfacEvan Cheng 394db3cffe94a5285239cc0056f939c6b74a5ca0b6Evan Cheng#define GET_INSTRINFO_CTOR 4022fee2dff4c43b551aefa44a96ca74fcade6bfacEvan Cheng#include "ARMGenInstrInfo.inc" 4122fee2dff4c43b551aefa44a96ca74fcade6bfacEvan Cheng 42334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinusing namespace llvm; 43334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 44334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinstatic cl::opt<bool> 45334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinEnableARM3Addr("enable-arm-3-addr-conv", cl::Hidden, 46334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin cl::desc("Enable ARM 2-addr to 3-addr conv")); 47334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 4861545829832ba0375249c42c84843d0b62c8f55fJakob Stoklund Olesenstatic cl::opt<bool> 493805d85e38c29d9106c758b63851eb847201f315Jakob Stoklund OlesenWidenVMOVS("widen-vmovs", cl::Hidden, cl::init(true), 5061545829832ba0375249c42c84843d0b62c8f55fJakob Stoklund Olesen cl::desc("Widen ARM vmovs to vmovd when possible")); 5161545829832ba0375249c42c84843d0b62c8f55fJakob Stoklund Olesen 5248575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng/// ARM_MLxEntry - Record information about MLA / MLS instructions. 5348575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Chengstruct ARM_MLxEntry { 5448575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng unsigned MLxOpc; // MLA / MLS opcode 5548575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng unsigned MulOpc; // Expanded multiplication opcode 5648575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng unsigned AddSubOpc; // Expanded add / sub opcode 5748575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng bool NegAcc; // True if the acc is negated before the add / sub. 5848575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng bool HasLane; // True if instruction has an extra "lane" operand. 5948575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng}; 6048575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng 6148575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Chengstatic const ARM_MLxEntry ARM_MLxTable[] = { 6248575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng // MLxOpc, MulOpc, AddSubOpc, NegAcc, HasLane 6348575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng // fp scalar ops 6448575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng { ARM::VMLAS, ARM::VMULS, ARM::VADDS, false, false }, 6548575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng { ARM::VMLSS, ARM::VMULS, ARM::VSUBS, false, false }, 6648575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng { ARM::VMLAD, ARM::VMULD, ARM::VADDD, false, false }, 6748575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng { ARM::VMLSD, ARM::VMULD, ARM::VSUBD, false, false }, 6848575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng { ARM::VNMLAS, ARM::VNMULS, ARM::VSUBS, true, false }, 6948575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng { ARM::VNMLSS, ARM::VMULS, ARM::VSUBS, true, false }, 7048575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng { ARM::VNMLAD, ARM::VNMULD, ARM::VSUBD, true, false }, 7148575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng { ARM::VNMLSD, ARM::VMULD, ARM::VSUBD, true, false }, 7248575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng 7348575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng // fp SIMD ops 7448575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng { ARM::VMLAfd, ARM::VMULfd, ARM::VADDfd, false, false }, 7548575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng { ARM::VMLSfd, ARM::VMULfd, ARM::VSUBfd, false, false }, 7648575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng { ARM::VMLAfq, ARM::VMULfq, ARM::VADDfq, false, false }, 7748575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng { ARM::VMLSfq, ARM::VMULfq, ARM::VSUBfq, false, false }, 7848575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng { ARM::VMLAslfd, ARM::VMULslfd, ARM::VADDfd, false, true }, 7948575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng { ARM::VMLSslfd, ARM::VMULslfd, ARM::VSUBfd, false, true }, 8048575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng { ARM::VMLAslfq, ARM::VMULslfq, ARM::VADDfq, false, true }, 8148575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng { ARM::VMLSslfq, ARM::VMULslfq, ARM::VSUBfq, false, true }, 8248575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng}; 8348575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng 84f95215f551949d5e5adfbf4753aa833b9009b77aAnton KorobeynikovARMBaseInstrInfo::ARMBaseInstrInfo(const ARMSubtarget& STI) 854db3cffe94a5285239cc0056f939c6b74a5ca0b6Evan Cheng : ARMGenInstrInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP), 86f95215f551949d5e5adfbf4753aa833b9009b77aAnton Korobeynikov Subtarget(STI) { 8748575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng for (unsigned i = 0, e = array_lengthof(ARM_MLxTable); i != e; ++i) { 8848575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng if (!MLxEntryMap.insert(std::make_pair(ARM_MLxTable[i].MLxOpc, i)).second) 8948575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng assert(false && "Duplicated entries?"); 9048575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng MLxHazardOpcodes.insert(ARM_MLxTable[i].AddSubOpc); 9148575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng MLxHazardOpcodes.insert(ARM_MLxTable[i].MulOpc); 9248575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng } 9348575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng} 9448575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng 952da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick// Use a ScoreboardHazardRecognizer for prepass ARM scheduling. TargetInstrImpl 962da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick// currently defaults to no prepass hazard recognizer. 9748575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan ChengScheduleHazardRecognizer *ARMBaseInstrInfo:: 982da8bc8a5f7705ac131184cd247f48500da0d74eAndrew TrickCreateTargetHazardRecognizer(const TargetMachine *TM, 992da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick const ScheduleDAG *DAG) const { 100c8bfd1d78ff9a307d1d4cb57cce4549b538e60f4Andrew Trick if (usePreRAHazardRecognizer()) { 1012da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick const InstrItineraryData *II = TM->getInstrItineraryData(); 1022da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick return new ScoreboardHazardRecognizer(II, DAG, "pre-RA-sched"); 1032da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick } 1042da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick return TargetInstrInfoImpl::CreateTargetHazardRecognizer(TM, DAG); 1052da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick} 1062da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick 1072da8bc8a5f7705ac131184cd247f48500da0d74eAndrew TrickScheduleHazardRecognizer *ARMBaseInstrInfo:: 1082da8bc8a5f7705ac131184cd247f48500da0d74eAndrew TrickCreateTargetPostRAHazardRecognizer(const InstrItineraryData *II, 1092da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick const ScheduleDAG *DAG) const { 11048575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng if (Subtarget.isThumb2() || Subtarget.hasVFP2()) 11148575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng return (ScheduleHazardRecognizer *) 1122da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick new ARMHazardRecognizer(II, *this, getRegisterInfo(), Subtarget, DAG); 1132da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick return TargetInstrInfoImpl::CreateTargetPostRAHazardRecognizer(II, DAG); 114334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 115334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 116334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinMachineInstr * 117334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinARMBaseInstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI, 118334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineBasicBlock::iterator &MBBI, 119334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin LiveVariables *LV) const { 12078703ddafe3d037f75d8ca188e4829d238289ac3Evan Cheng // FIXME: Thumb2 support. 12178703ddafe3d037f75d8ca188e4829d238289ac3Evan Cheng 122334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (!EnableARM3Addr) 123334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return NULL; 124334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 125334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineInstr *MI = MBBI; 126334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineFunction &MF = *MI->getParent()->getParent(); 12799405df044f2c584242e711cc9023ec90356da82Bruno Cardoso Lopes uint64_t TSFlags = MI->getDesc().TSFlags; 128334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool isPre = false; 129334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin switch ((TSFlags & ARMII::IndexModeMask) >> ARMII::IndexModeShift) { 130334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin default: return NULL; 131334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMII::IndexModePre: 132334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin isPre = true; 133334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin break; 134334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMII::IndexModePost: 135334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin break; 136334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 137334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 138334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Try splitting an indexed load/store to an un-indexed one plus an add/sub 139334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // operation. 140334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned MemOpc = getUnindexedOpcode(MI->getOpcode()); 141334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (MemOpc == 0) 142334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return NULL; 143334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 144334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineInstr *UpdateMI = NULL; 145334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineInstr *MemMI = NULL; 146334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned AddrMode = (TSFlags & ARMII::AddrModeMask); 147e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng const MCInstrDesc &MCID = MI->getDesc(); 148e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng unsigned NumOps = MCID.getNumOperands(); 1495a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng bool isLoad = !MI->mayStore(); 150334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const MachineOperand &WB = isLoad ? MI->getOperand(1) : MI->getOperand(0); 151334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const MachineOperand &Base = MI->getOperand(2); 152334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const MachineOperand &Offset = MI->getOperand(NumOps-3); 153334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned WBReg = WB.getReg(); 154334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned BaseReg = Base.getReg(); 155334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned OffReg = Offset.getReg(); 156334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned OffImm = MI->getOperand(NumOps-2).getImm(); 157334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin ARMCC::CondCodes Pred = (ARMCC::CondCodes)MI->getOperand(NumOps-1).getImm(); 158334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin switch (AddrMode) { 159bc2198133a1836598b54b943420748e75d5dea94Craig Topper default: llvm_unreachable("Unknown indexed op!"); 160334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMII::AddrMode2: { 161334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool isSub = ARM_AM::getAM2Op(OffImm) == ARM_AM::sub; 162334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned Amt = ARM_AM::getAM2Offset(OffImm); 163334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (OffReg == 0) { 164e7cbe4118b7ddf05032ff8772a98c51e1637bb5cEvan Cheng if (ARM_AM::getSOImmVal(Amt) == -1) 165334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Can't encode it in a so_imm operand. This transformation will 166334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // add more than 1 instruction. Abandon! 167334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return NULL; 168334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin UpdateMI = BuildMI(MF, MI->getDebugLoc(), 16978703ddafe3d037f75d8ca188e4829d238289ac3Evan Cheng get(isSub ? ARM::SUBri : ARM::ADDri), WBReg) 170e7cbe4118b7ddf05032ff8772a98c51e1637bb5cEvan Cheng .addReg(BaseReg).addImm(Amt) 171334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addImm(Pred).addReg(0).addReg(0); 172334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } else if (Amt != 0) { 173334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin ARM_AM::ShiftOpc ShOpc = ARM_AM::getAM2ShiftOpc(OffImm); 174334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned SOOpc = ARM_AM::getSORegOpc(ShOpc, Amt); 175334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin UpdateMI = BuildMI(MF, MI->getDebugLoc(), 17692a202213bb4c20301abf6ab64e46df3695e60bfOwen Anderson get(isSub ? ARM::SUBrsi : ARM::ADDrsi), WBReg) 177334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(BaseReg).addReg(OffReg).addReg(0).addImm(SOOpc) 178334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addImm(Pred).addReg(0).addReg(0); 179334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } else 180334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin UpdateMI = BuildMI(MF, MI->getDebugLoc(), 18178703ddafe3d037f75d8ca188e4829d238289ac3Evan Cheng get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg) 182334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(BaseReg).addReg(OffReg) 183334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addImm(Pred).addReg(0).addReg(0); 184334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin break; 185334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 186334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMII::AddrMode3 : { 187334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool isSub = ARM_AM::getAM3Op(OffImm) == ARM_AM::sub; 188334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned Amt = ARM_AM::getAM3Offset(OffImm); 189334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (OffReg == 0) 190334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Immediate is 8-bits. It's guaranteed to fit in a so_imm operand. 191334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin UpdateMI = BuildMI(MF, MI->getDebugLoc(), 19278703ddafe3d037f75d8ca188e4829d238289ac3Evan Cheng get(isSub ? ARM::SUBri : ARM::ADDri), WBReg) 193334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(BaseReg).addImm(Amt) 194334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addImm(Pred).addReg(0).addReg(0); 195334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin else 196334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin UpdateMI = BuildMI(MF, MI->getDebugLoc(), 19778703ddafe3d037f75d8ca188e4829d238289ac3Evan Cheng get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg) 198334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(BaseReg).addReg(OffReg) 199334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addImm(Pred).addReg(0).addReg(0); 200334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin break; 201334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 202334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 203334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 204334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin std::vector<MachineInstr*> NewMIs; 205334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (isPre) { 206334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (isLoad) 207334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MemMI = BuildMI(MF, MI->getDebugLoc(), 208334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin get(MemOpc), MI->getOperand(0).getReg()) 2093e5561247202bae994dd259a2d8dc4eff8f799f3Jim Grosbach .addReg(WBReg).addImm(0).addImm(Pred); 210334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin else 211334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MemMI = BuildMI(MF, MI->getDebugLoc(), 212334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin get(MemOpc)).addReg(MI->getOperand(1).getReg()) 213334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(WBReg).addReg(0).addImm(0).addImm(Pred); 214334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin NewMIs.push_back(MemMI); 215334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin NewMIs.push_back(UpdateMI); 216334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } else { 217334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (isLoad) 218334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MemMI = BuildMI(MF, MI->getDebugLoc(), 219334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin get(MemOpc), MI->getOperand(0).getReg()) 2203e5561247202bae994dd259a2d8dc4eff8f799f3Jim Grosbach .addReg(BaseReg).addImm(0).addImm(Pred); 221334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin else 222334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MemMI = BuildMI(MF, MI->getDebugLoc(), 223334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin get(MemOpc)).addReg(MI->getOperand(1).getReg()) 224334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred); 225334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (WB.isDead()) 226334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin UpdateMI->getOperand(0).setIsDead(); 227334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin NewMIs.push_back(UpdateMI); 228334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin NewMIs.push_back(MemMI); 229334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 230334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 231334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Transfer LiveVariables states, kill / dead info. 232334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (LV) { 233334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 234334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineOperand &MO = MI->getOperand(i); 235c9df025e33ac435adb3b3318d237c36ca7cec659Jakob Stoklund Olesen if (MO.isReg() && TargetRegisterInfo::isVirtualRegister(MO.getReg())) { 236334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned Reg = MO.getReg(); 237334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 238334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin LiveVariables::VarInfo &VI = LV->getVarInfo(Reg); 239334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (MO.isDef()) { 240334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineInstr *NewMI = (Reg == WBReg) ? UpdateMI : MemMI; 241334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (MO.isDead()) 242334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin LV->addVirtualRegisterDead(Reg, NewMI); 243334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 244334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (MO.isUse() && MO.isKill()) { 245334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin for (unsigned j = 0; j < 2; ++j) { 246334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Look at the two new MI's in reverse order. 247334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineInstr *NewMI = NewMIs[j]; 248334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (!NewMI->readsRegister(Reg)) 249334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin continue; 250334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin LV->addVirtualRegisterKilled(Reg, NewMI); 251334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (VI.removeKill(MI)) 252334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin VI.Kills.push_back(NewMI); 253334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin break; 254334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 255334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 256334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 257334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 258334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 259334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 260334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MFI->insert(MBBI, NewMIs[1]); 261334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MFI->insert(MBBI, NewMIs[0]); 262334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return NewMIs[0]; 263334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 264334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 265334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// Branch analysis. 266334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinbool 267334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinARMBaseInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB, 268334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineBasicBlock *&FBB, 269334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin SmallVectorImpl<MachineOperand> &Cond, 270334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool AllowModify) const { 271334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // If the block has no terminators, it just falls into the block after it. 272334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineBasicBlock::iterator I = MBB.end(); 27393d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen if (I == MBB.begin()) 27493d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen return false; 27593d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen --I; 27693d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen while (I->isDebugValue()) { 27793d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen if (I == MBB.begin()) 27893d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen return false; 27993d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen --I; 28093d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen } 28193d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen if (!isUnpredicatedTerminator(I)) 282334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 283334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 284334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Get the last instruction in the block. 285334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineInstr *LastInst = I; 286334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 287334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // If there is only one terminator instruction, process it. 288334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned LastOpc = LastInst->getOpcode(); 289334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) { 2905ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng if (isUncondBranchOpcode(LastOpc)) { 291334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin TBB = LastInst->getOperand(0).getMBB(); 292334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 293334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 2945ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng if (isCondBranchOpcode(LastOpc)) { 295334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Block ends with fall-through condbranch. 296334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin TBB = LastInst->getOperand(0).getMBB(); 297334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin Cond.push_back(LastInst->getOperand(1)); 298334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin Cond.push_back(LastInst->getOperand(2)); 299334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 300334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 301334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; // Can't handle indirect branch. 302334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 303334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 304334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Get the instruction before it if it is a terminator. 305334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineInstr *SecondLastInst = I; 306108c8724663354050dc09bb1262c3e4511adf82fEvan Cheng unsigned SecondLastOpc = SecondLastInst->getOpcode(); 307108c8724663354050dc09bb1262c3e4511adf82fEvan Cheng 308108c8724663354050dc09bb1262c3e4511adf82fEvan Cheng // If AllowModify is true and the block ends with two or more unconditional 309108c8724663354050dc09bb1262c3e4511adf82fEvan Cheng // branches, delete all but the first unconditional branch. 310108c8724663354050dc09bb1262c3e4511adf82fEvan Cheng if (AllowModify && isUncondBranchOpcode(LastOpc)) { 311108c8724663354050dc09bb1262c3e4511adf82fEvan Cheng while (isUncondBranchOpcode(SecondLastOpc)) { 312108c8724663354050dc09bb1262c3e4511adf82fEvan Cheng LastInst->eraseFromParent(); 313108c8724663354050dc09bb1262c3e4511adf82fEvan Cheng LastInst = SecondLastInst; 314108c8724663354050dc09bb1262c3e4511adf82fEvan Cheng LastOpc = LastInst->getOpcode(); 315676e258366dd17a0b4ee6ac66914237ce181202eEvan Cheng if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) { 316676e258366dd17a0b4ee6ac66914237ce181202eEvan Cheng // Return now the only terminator is an unconditional branch. 317676e258366dd17a0b4ee6ac66914237ce181202eEvan Cheng TBB = LastInst->getOperand(0).getMBB(); 318676e258366dd17a0b4ee6ac66914237ce181202eEvan Cheng return false; 319676e258366dd17a0b4ee6ac66914237ce181202eEvan Cheng } else { 320108c8724663354050dc09bb1262c3e4511adf82fEvan Cheng SecondLastInst = I; 321108c8724663354050dc09bb1262c3e4511adf82fEvan Cheng SecondLastOpc = SecondLastInst->getOpcode(); 322108c8724663354050dc09bb1262c3e4511adf82fEvan Cheng } 323108c8724663354050dc09bb1262c3e4511adf82fEvan Cheng } 324108c8724663354050dc09bb1262c3e4511adf82fEvan Cheng } 325334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 326334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // If there are three terminators, we don't know what sort of block this is. 327334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(--I)) 328334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; 329334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 3305ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng // If the block ends with a B and a Bcc, handle it. 3315ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng if (isCondBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) { 332334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin TBB = SecondLastInst->getOperand(0).getMBB(); 333334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin Cond.push_back(SecondLastInst->getOperand(1)); 334334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin Cond.push_back(SecondLastInst->getOperand(2)); 335334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin FBB = LastInst->getOperand(0).getMBB(); 336334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 337334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 338334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 339334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // If the block ends with two unconditional branches, handle it. The second 340334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // one is not executed, so remove it. 3415ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng if (isUncondBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) { 342334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin TBB = SecondLastInst->getOperand(0).getMBB(); 343334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin I = LastInst; 344334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (AllowModify) 345334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin I->eraseFromParent(); 346334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 347334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 348334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 349334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // ...likewise if it ends with a branch table followed by an unconditional 350334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // branch. The branch folder can create these, and we must get rid of them for 351334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // correctness of Thumb constant islands. 3528d4de5abfa1bcd974554ea14904ebf7af289e84dBob Wilson if ((isJumpTableBranchOpcode(SecondLastOpc) || 3538d4de5abfa1bcd974554ea14904ebf7af289e84dBob Wilson isIndirectBranchOpcode(SecondLastOpc)) && 3545ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng isUncondBranchOpcode(LastOpc)) { 355334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin I = LastInst; 356334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (AllowModify) 357334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin I->eraseFromParent(); 358334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; 359334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 360334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 361334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Otherwise, can't handle this. 362334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; 363334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 364334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 365334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 366334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinunsigned ARMBaseInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const { 367334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineBasicBlock::iterator I = MBB.end(); 368334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (I == MBB.begin()) return 0; 369334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin --I; 37093d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen while (I->isDebugValue()) { 37193d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen if (I == MBB.begin()) 37293d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen return 0; 37393d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen --I; 37493d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen } 3755ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng if (!isUncondBranchOpcode(I->getOpcode()) && 3765ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng !isCondBranchOpcode(I->getOpcode())) 377334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 0; 378334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 379334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Remove the branch. 380334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin I->eraseFromParent(); 381334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 382334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin I = MBB.end(); 383334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 384334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (I == MBB.begin()) return 1; 385334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin --I; 3865ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng if (!isCondBranchOpcode(I->getOpcode())) 387334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 1; 388334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 389334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Remove the branch. 390334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin I->eraseFromParent(); 391334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 2; 392334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 393334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 394334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinunsigned 395334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinARMBaseInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 3963bf912593301152b65accb9d9c37a95172f1df5aStuart Hastings MachineBasicBlock *FBB, 3973bf912593301152b65accb9d9c37a95172f1df5aStuart Hastings const SmallVectorImpl<MachineOperand> &Cond, 3983bf912593301152b65accb9d9c37a95172f1df5aStuart Hastings DebugLoc DL) const { 3996495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ARMFunctionInfo *AFI = MBB.getParent()->getInfo<ARMFunctionInfo>(); 4006495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng int BOpc = !AFI->isThumbFunction() 4016495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ? ARM::B : (AFI->isThumb2Function() ? ARM::t2B : ARM::tB); 4026495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng int BccOpc = !AFI->isThumbFunction() 4036495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ? ARM::Bcc : (AFI->isThumb2Function() ? ARM::t2Bcc : ARM::tBcc); 40451f6a7abf27fc92c3d8904c2334feab8b498e8e9Owen Anderson bool isThumb = AFI->isThumbFunction() || AFI->isThumb2Function(); 405e23dc9c0ef50b0a1934c04c1786f3a0478d62f41Andrew Trick 406334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Shouldn't be a fall through. 407334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin assert(TBB && "InsertBranch must not be told to insert a fallthrough"); 408334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin assert((Cond.size() == 2 || Cond.size() == 0) && 409334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin "ARM branch conditions have two components!"); 410334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 411334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (FBB == 0) { 412112fb73502d54dd7dd61ae2de24c92d4df181294Owen Anderson if (Cond.empty()) { // Unconditional branch? 41351f6a7abf27fc92c3d8904c2334feab8b498e8e9Owen Anderson if (isThumb) 41451f6a7abf27fc92c3d8904c2334feab8b498e8e9Owen Anderson BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB).addImm(ARMCC::AL).addReg(0); 41551f6a7abf27fc92c3d8904c2334feab8b498e8e9Owen Anderson else 41651f6a7abf27fc92c3d8904c2334feab8b498e8e9Owen Anderson BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB); 417112fb73502d54dd7dd61ae2de24c92d4df181294Owen Anderson } else 4183bf912593301152b65accb9d9c37a95172f1df5aStuart Hastings BuildMI(&MBB, DL, get(BccOpc)).addMBB(TBB) 419334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()); 420334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 1; 421334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 422334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 423334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Two-way conditional branch. 4243bf912593301152b65accb9d9c37a95172f1df5aStuart Hastings BuildMI(&MBB, DL, get(BccOpc)).addMBB(TBB) 425334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()); 42651f6a7abf27fc92c3d8904c2334feab8b498e8e9Owen Anderson if (isThumb) 42751f6a7abf27fc92c3d8904c2334feab8b498e8e9Owen Anderson BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB).addImm(ARMCC::AL).addReg(0); 42851f6a7abf27fc92c3d8904c2334feab8b498e8e9Owen Anderson else 42951f6a7abf27fc92c3d8904c2334feab8b498e8e9Owen Anderson BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB); 430334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 2; 431334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 432334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 433334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinbool ARMBaseInstrInfo:: 434334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const { 435334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin ARMCC::CondCodes CC = (ARMCC::CondCodes)(int)Cond[0].getImm(); 436334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin Cond[0].setImm(ARMCC::getOppositeCondition(CC)); 437334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 438334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 439334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 440ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Chengbool ARMBaseInstrInfo::isPredicated(const MachineInstr *MI) const { 441ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng if (MI->isBundle()) { 442ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng MachineBasicBlock::const_instr_iterator I = MI; 443ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end(); 444ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng while (++I != E && I->isInsideBundle()) { 445ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng int PIdx = I->findFirstPredOperandIdx(); 446ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng if (PIdx != -1 && I->getOperand(PIdx).getImm() != ARMCC::AL) 447ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng return true; 448ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng } 449ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng return false; 450ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng } 451ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng 452ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng int PIdx = MI->findFirstPredOperandIdx(); 453ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng return PIdx != -1 && MI->getOperand(PIdx).getImm() != ARMCC::AL; 454ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng} 455ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng 456334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinbool ARMBaseInstrInfo:: 457334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinPredicateInstruction(MachineInstr *MI, 458334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const SmallVectorImpl<MachineOperand> &Pred) const { 459334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned Opc = MI->getOpcode(); 4605ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng if (isUncondBranchOpcode(Opc)) { 4615ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng MI->setDesc(get(getMatchingCondBranchOpcode(Opc))); 462334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI->addOperand(MachineOperand::CreateImm(Pred[0].getImm())); 463334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI->addOperand(MachineOperand::CreateReg(Pred[1].getReg(), false)); 464334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; 465334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 466334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 467334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin int PIdx = MI->findFirstPredOperandIdx(); 468334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (PIdx != -1) { 469334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineOperand &PMO = MI->getOperand(PIdx); 470334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin PMO.setImm(Pred[0].getImm()); 471334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI->getOperand(PIdx+1).setReg(Pred[1].getReg()); 472334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; 473334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 474334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 475334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 476334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 477334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinbool ARMBaseInstrInfo:: 478334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinSubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1, 479334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const SmallVectorImpl<MachineOperand> &Pred2) const { 480334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (Pred1.size() > 2 || Pred2.size() > 2) 481334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 482334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 483334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin ARMCC::CondCodes CC1 = (ARMCC::CondCodes)Pred1[0].getImm(); 484334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin ARMCC::CondCodes CC2 = (ARMCC::CondCodes)Pred2[0].getImm(); 485334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (CC1 == CC2) 486334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; 487334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 488334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin switch (CC1) { 489334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin default: 490334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 491334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMCC::AL: 492334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; 493334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMCC::HS: 494334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return CC2 == ARMCC::HI; 495334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMCC::LS: 496334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return CC2 == ARMCC::LO || CC2 == ARMCC::EQ; 497334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMCC::GE: 498334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return CC2 == ARMCC::GT; 499334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMCC::LE: 500334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return CC2 == ARMCC::LT; 501334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 502334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 503334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 504334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinbool ARMBaseInstrInfo::DefinesPredicate(MachineInstr *MI, 505334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin std::vector<MachineOperand> &Pred) const { 506334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool Found = false; 507334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 508334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const MachineOperand &MO = MI->getOperand(i); 5092420b558de5d291d8503c1339004e5b5bf99a48aJakob Stoklund Olesen if ((MO.isRegMask() && MO.clobbersPhysReg(ARM::CPSR)) || 5102420b558de5d291d8503c1339004e5b5bf99a48aJakob Stoklund Olesen (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR)) { 511334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin Pred.push_back(MO); 512334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin Found = true; 513334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 514334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 515334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 516334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return Found; 517334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 518334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 519ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng/// isPredicable - Return true if the specified instruction can be predicated. 520ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng/// By default, this returns true for every instruction with a 521ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng/// PredicateOperand. 522ac0869dc8a7986855c5557cc67d4709600158ef5Evan Chengbool ARMBaseInstrInfo::isPredicable(MachineInstr *MI) const { 5235a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng if (!MI->isPredicable()) 524ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng return false; 525ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng 5265a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng if ((MI->getDesc().TSFlags & ARMII::DomainMask) == ARMII::DomainNEON) { 527ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng ARMFunctionInfo *AFI = 528ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng MI->getParent()->getParent()->getInfo<ARMFunctionInfo>(); 529d7f0810c934a7d13acb28c42d737ce58ec990ea8Evan Cheng return AFI->isThumb2Function(); 530ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng } 531ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng return true; 532ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng} 533334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 53456856b1f46ec1f073ceef4e826c544b8b1691608Chris Lattner/// FIXME: Works around a gcc miscompilation with -fstrict-aliasing. 53519e57025d458d3cb50804fd821fd89b868a819bdChandler CarruthLLVM_ATTRIBUTE_NOINLINE 536334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinstatic unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT, 53756856b1f46ec1f073ceef4e826c544b8b1691608Chris Lattner unsigned JTI); 538334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinstatic unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT, 539334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned JTI) { 54056856b1f46ec1f073ceef4e826c544b8b1691608Chris Lattner assert(JTI < JT.size()); 541334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return JT[JTI].MBBs.size(); 542334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 543334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 544334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin/// GetInstSize - Return the size of the specified MachineInstr. 545334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin/// 546334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinunsigned ARMBaseInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const { 547334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const MachineBasicBlock &MBB = *MI->getParent(); 548334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const MachineFunction *MF = MBB.getParent(); 54933adcfb4d217f5f23d9bde8ba02b8e48f9605fc5Chris Lattner const MCAsmInfo *MAI = MF->getTarget().getMCAsmInfo(); 550334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 551e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng const MCInstrDesc &MCID = MI->getDesc(); 55216884415db751c75f2133bd04921393c792b1158Owen Anderson if (MCID.getSize()) 55316884415db751c75f2133bd04921393c792b1158Owen Anderson return MCID.getSize(); 554334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 5554d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie // If this machine instr is an inline asm, measure it. 5564d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie if (MI->getOpcode() == ARM::INLINEASM) 5574d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie return getInlineAsmLength(MI->getOperand(0).getSymbolName(), *MAI); 5584d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie if (MI->isLabel()) 5594d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie return 0; 5604d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie unsigned Opc = MI->getOpcode(); 5614d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie switch (Opc) { 5624d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie case TargetOpcode::IMPLICIT_DEF: 5634d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie case TargetOpcode::KILL: 5644d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie case TargetOpcode::PROLOG_LABEL: 5654d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie case TargetOpcode::EH_LABEL: 5664d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie case TargetOpcode::DBG_VALUE: 5674d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie return 0; 5684d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie case TargetOpcode::BUNDLE: 5694d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie return getInstBundleLength(MI); 5704d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie case ARM::MOVi16_ga_pcrel: 5714d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie case ARM::MOVTi16_ga_pcrel: 5724d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie case ARM::t2MOVi16_ga_pcrel: 5734d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie case ARM::t2MOVTi16_ga_pcrel: 5744d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie return 4; 5754d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie case ARM::MOVi32imm: 5764d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie case ARM::t2MOVi32imm: 5774d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie return 8; 5784d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie case ARM::CONSTPOOL_ENTRY: 5794d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie // If this machine instr is a constant pool entry, its size is recorded as 5804d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie // operand #2. 5814d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie return MI->getOperand(2).getImm(); 5824d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie case ARM::Int_eh_sjlj_longjmp: 5834d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie return 16; 5844d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie case ARM::tInt_eh_sjlj_longjmp: 5854d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie return 10; 5864d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie case ARM::Int_eh_sjlj_setjmp: 5874d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie case ARM::Int_eh_sjlj_setjmp_nofp: 5884d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie return 20; 5894d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie case ARM::tInt_eh_sjlj_setjmp: 5904d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie case ARM::t2Int_eh_sjlj_setjmp: 5914d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie case ARM::t2Int_eh_sjlj_setjmp_nofp: 5924d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie return 12; 5934d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie case ARM::BR_JTr: 5944d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie case ARM::BR_JTm: 5954d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie case ARM::BR_JTadd: 5964d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie case ARM::tBR_JTr: 5974d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie case ARM::t2BR_JT: 5984d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie case ARM::t2TBB_JT: 5994d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie case ARM::t2TBH_JT: { 6004d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie // These are jumptable branches, i.e. a branch followed by an inlined 6014d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie // jumptable. The size is 4 + 4 * number of entries. For TBB, each 6024d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie // entry is one byte; TBH two byte each. 6034d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie unsigned EntrySize = (Opc == ARM::t2TBB_JT) 6044d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie ? 1 : ((Opc == ARM::t2TBH_JT) ? 2 : 4); 6054d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie unsigned NumOps = MCID.getNumOperands(); 6064d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie MachineOperand JTOP = 6074d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie MI->getOperand(NumOps - (MI->isPredicable() ? 3 : 2)); 6084d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie unsigned JTI = JTOP.getIndex(); 6094d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo(); 6104d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie assert(MJTI != 0); 6114d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables(); 6124d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie assert(JTI < JT.size()); 6134d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie // Thumb instructions are 2 byte aligned, but JT entries are 4 byte 6144d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie // 4 aligned. The assembler / linker may add 2 byte padding just before 6154d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie // the JT entries. The size does not include this padding; the 6164d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie // constant islands pass does separate bookkeeping for it. 6174d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie // FIXME: If we know the size of the function is less than (1 << 16) *2 6184d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie // bytes, we can use 16-bit entries instead. Then there won't be an 6194d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie // alignment issue. 6204d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie unsigned InstSize = (Opc == ARM::tBR_JTr || Opc == ARM::t2BR_JT) ? 2 : 4; 6214d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie unsigned NumEntries = getNumJTEntries(JT, JTI); 6224d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie if (Opc == ARM::t2TBB_JT && (NumEntries & 1)) 6234d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie // Make sure the instruction that follows TBB is 2-byte aligned. 6244d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie // FIXME: Constant island pass should insert an "ALIGN" instruction 6254d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie // instead. 6264d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie ++NumEntries; 6274d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie return NumEntries * EntrySize + InstSize; 6284d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie } 6294d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie default: 6304d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie // Otherwise, pseudo-instruction sizes are zero. 6314d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie return 0; 6324d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie } 633334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 634334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 635ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Chengunsigned ARMBaseInstrInfo::getInstBundleLength(const MachineInstr *MI) const { 636ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng unsigned Size = 0; 637ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng MachineBasicBlock::const_instr_iterator I = MI; 638ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end(); 639ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng while (++I != E && I->isInsideBundle()) { 640ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng assert(!I->isBundle() && "No nested bundle!"); 641ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng Size += GetInstSizeInBytes(&*I); 642ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng } 643ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng return Size; 644ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng} 645ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng 646ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesenvoid ARMBaseInstrInfo::copyPhysReg(MachineBasicBlock &MBB, 647ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen MachineBasicBlock::iterator I, DebugLoc DL, 648ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen unsigned DestReg, unsigned SrcReg, 649ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen bool KillSrc) const { 650ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen bool GPRDest = ARM::GPRRegClass.contains(DestReg); 651ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen bool GPRSrc = ARM::GPRRegClass.contains(SrcReg); 652ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen 653ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen if (GPRDest && GPRSrc) { 654ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen AddDefaultCC(AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::MOVr), DestReg) 655ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen .addReg(SrcReg, getKillRegState(KillSrc)))); 656ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen return; 6577bfdca0206f51132b26094c6f83a5ac97ee0f943David Goodwin } 658334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 659ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen bool SPRDest = ARM::SPRRegClass.contains(DestReg); 660ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen bool SPRSrc = ARM::SPRRegClass.contains(SrcReg); 661ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen 662e5038e191db82d4d92fdeec1b5bce5cae21f6d8fChad Rosier unsigned Opc = 0; 663142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen if (SPRDest && SPRSrc) 664ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen Opc = ARM::VMOVS; 665142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen else if (GPRDest && SPRSrc) 666ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen Opc = ARM::VMOVRS; 667ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen else if (SPRDest && GPRSrc) 668ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen Opc = ARM::VMOVSR; 669ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen else if (ARM::DPRRegClass.contains(DestReg, SrcReg)) 670ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen Opc = ARM::VMOVD; 671ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen else if (ARM::QPRRegClass.contains(DestReg, SrcReg)) 67243967a97cf9a296623e1cf5ed643e2f40b7e5766Owen Anderson Opc = ARM::VORRq; 673e5038e191db82d4d92fdeec1b5bce5cae21f6d8fChad Rosier 674e5038e191db82d4d92fdeec1b5bce5cae21f6d8fChad Rosier if (Opc) { 675e5038e191db82d4d92fdeec1b5bce5cae21f6d8fChad Rosier MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc), DestReg); 67643967a97cf9a296623e1cf5ed643e2f40b7e5766Owen Anderson MIB.addReg(SrcReg, getKillRegState(KillSrc)); 677e5038e191db82d4d92fdeec1b5bce5cae21f6d8fChad Rosier if (Opc == ARM::VORRq) 678e5038e191db82d4d92fdeec1b5bce5cae21f6d8fChad Rosier MIB.addReg(SrcReg, getKillRegState(KillSrc)); 679fea95c6bade86fcfa5bd07efdda9bd902f53be8cChad Rosier AddDefaultPred(MIB); 680e5038e191db82d4d92fdeec1b5bce5cae21f6d8fChad Rosier return; 681e5038e191db82d4d92fdeec1b5bce5cae21f6d8fChad Rosier } 682e5038e191db82d4d92fdeec1b5bce5cae21f6d8fChad Rosier 683fea95c6bade86fcfa5bd07efdda9bd902f53be8cChad Rosier // Generate instructions for VMOVQQ and VMOVQQQQ pseudos in place. 684fea95c6bade86fcfa5bd07efdda9bd902f53be8cChad Rosier if (ARM::QQPRRegClass.contains(DestReg, SrcReg) || 685fea95c6bade86fcfa5bd07efdda9bd902f53be8cChad Rosier ARM::QQQQPRRegClass.contains(DestReg, SrcReg)) { 686e5038e191db82d4d92fdeec1b5bce5cae21f6d8fChad Rosier const TargetRegisterInfo *TRI = &getRegisterInfo(); 687e5038e191db82d4d92fdeec1b5bce5cae21f6d8fChad Rosier assert(ARM::qsub_0 + 3 == ARM::qsub_3 && "Expected contiguous enum."); 688e23dc9c0ef50b0a1934c04c1786f3a0478d62f41Andrew Trick unsigned EndSubReg = ARM::QQPRRegClass.contains(DestReg, SrcReg) ? 689fea95c6bade86fcfa5bd07efdda9bd902f53be8cChad Rosier ARM::qsub_1 : ARM::qsub_3; 690e23dc9c0ef50b0a1934c04c1786f3a0478d62f41Andrew Trick for (unsigned i = ARM::qsub_0, e = EndSubReg + 1; i != e; ++i) { 691e5038e191db82d4d92fdeec1b5bce5cae21f6d8fChad Rosier unsigned Dst = TRI->getSubReg(DestReg, i); 692e5038e191db82d4d92fdeec1b5bce5cae21f6d8fChad Rosier unsigned Src = TRI->getSubReg(SrcReg, i); 693e5038e191db82d4d92fdeec1b5bce5cae21f6d8fChad Rosier MachineInstrBuilder Mov = 694e5038e191db82d4d92fdeec1b5bce5cae21f6d8fChad Rosier AddDefaultPred(BuildMI(MBB, I, I->getDebugLoc(), get(ARM::VORRq)) 695e5038e191db82d4d92fdeec1b5bce5cae21f6d8fChad Rosier .addReg(Dst, RegState::Define) 696e5038e191db82d4d92fdeec1b5bce5cae21f6d8fChad Rosier .addReg(Src, getKillRegState(KillSrc)) 697e5038e191db82d4d92fdeec1b5bce5cae21f6d8fChad Rosier .addReg(Src, getKillRegState(KillSrc))); 698fea95c6bade86fcfa5bd07efdda9bd902f53be8cChad Rosier if (i == EndSubReg) { 699e5038e191db82d4d92fdeec1b5bce5cae21f6d8fChad Rosier Mov->addRegisterDefined(DestReg, TRI); 700e5038e191db82d4d92fdeec1b5bce5cae21f6d8fChad Rosier if (KillSrc) 701e5038e191db82d4d92fdeec1b5bce5cae21f6d8fChad Rosier Mov->addRegisterKilled(SrcReg, TRI); 702e5038e191db82d4d92fdeec1b5bce5cae21f6d8fChad Rosier } 703e5038e191db82d4d92fdeec1b5bce5cae21f6d8fChad Rosier } 704e5038e191db82d4d92fdeec1b5bce5cae21f6d8fChad Rosier return; 705e5038e191db82d4d92fdeec1b5bce5cae21f6d8fChad Rosier } 706e5038e191db82d4d92fdeec1b5bce5cae21f6d8fChad Rosier llvm_unreachable("Impossible reg-to-reg copy"); 707334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 708334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 709c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Chengstatic const 710c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan ChengMachineInstrBuilder &AddDReg(MachineInstrBuilder &MIB, 711c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Cheng unsigned Reg, unsigned SubIdx, unsigned State, 712c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Cheng const TargetRegisterInfo *TRI) { 713c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Cheng if (!SubIdx) 714c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Cheng return MIB.addReg(Reg, State); 715c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Cheng 716c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Cheng if (TargetRegisterInfo::isPhysicalRegister(Reg)) 717c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Cheng return MIB.addReg(TRI->getSubReg(Reg, SubIdx), State); 718c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Cheng return MIB.addReg(Reg, State, SubIdx); 719c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Cheng} 720c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Cheng 721334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinvoid ARMBaseInstrInfo:: 722334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinstoreRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 723334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned SrcReg, bool isKill, int FI, 724746ad69e088176819981b4b2c5ac8dcd49f5e60eEvan Cheng const TargetRegisterClass *RC, 725746ad69e088176819981b4b2c5ac8dcd49f5e60eEvan Cheng const TargetRegisterInfo *TRI) const { 726c7f3ace20c325521c68335a1689645b43b06ddf0Chris Lattner DebugLoc DL; 727334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (I != MBB.end()) DL = I->getDebugLoc(); 728249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MachineFunction &MF = *MBB.getParent(); 729249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MachineFrameInfo &MFI = *MF.getFrameInfo(); 73031bc849123011b8eae6bb3c79876d9a3c26a6a1dJim Grosbach unsigned Align = MFI.getObjectAlignment(FI); 731249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov 732249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MachineMemOperand *MMO = 733978e0dfe46e481bfb1281e683aa308329e879e95Jay Foad MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FI), 73459db5496f4fc2ef6111569e542f8b65480ef14c1Chris Lattner MachineMemOperand::MOStore, 735249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MFI.getObjectSize(FI), 73631bc849123011b8eae6bb3c79876d9a3c26a6a1dJim Grosbach Align); 737334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 738e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson switch (RC->getSize()) { 739e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson case 4: 740e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson if (ARM::GPRRegClass.hasSubClassEq(RC)) { 741e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::STRi12)) 742334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(SrcReg, getKillRegState(isKill)) 7437e3383c007f53b3a00675af225e428cb66ddf404Jim Grosbach .addFrameIndex(FI).addImm(0).addMemOperand(MMO)); 744e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson } else if (ARM::SPRRegClass.hasSubClassEq(RC)) { 745e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTRS)) 746d31c5496d7e1580058b5c6fbc8fd537a641ea590Evan Cheng .addReg(SrcReg, getKillRegState(isKill)) 747d31c5496d7e1580058b5c6fbc8fd537a641ea590Evan Cheng .addFrameIndex(FI).addImm(0).addMemOperand(MMO)); 748e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson } else 749e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson llvm_unreachable("Unknown reg class!"); 750e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson break; 751e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson case 8: 752e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson if (ARM::DPRRegClass.hasSubClassEq(RC)) { 753e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTRD)) 754334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(SrcReg, getKillRegState(isKill)) 755249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov .addFrameIndex(FI).addImm(0).addMemOperand(MMO)); 756e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson } else 757e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson llvm_unreachable("Unknown reg class!"); 758e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson break; 759e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson case 16: 7605b2f9136644c58ae32e00d8317540692a697d1c9Jakob Stoklund Olesen if (ARM::DPairRegClass.hasSubClassEq(RC)) { 7617255a4e1332ccb69918ebe041dff05f9e4e5815dJakob Stoklund Olesen // Use aligned spills if the stack can be realigned. 7627255a4e1332ccb69918ebe041dff05f9e4e5815dJakob Stoklund Olesen if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) { 76328f08c93e75d291695ea89b9004145103292e85bJim Grosbach AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1q64)) 764f967ca0eaf30325cabe3c1971bf0dba16cf1b027Bob Wilson .addFrameIndex(FI).addImm(16) 76569b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng .addReg(SrcReg, getKillRegState(isKill)) 76669b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng .addMemOperand(MMO)); 767e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson } else { 768e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMQIA)) 76969b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng .addReg(SrcReg, getKillRegState(isKill)) 77069b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng .addFrameIndex(FI) 77169b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng .addMemOperand(MMO)); 772e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson } 773e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson } else 774e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson llvm_unreachable("Unknown reg class!"); 775e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson break; 776e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson case 32: 777e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson if (ARM::QQPRRegClass.hasSubClassEq(RC)) { 778e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) { 779e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson // FIXME: It's possible to only store part of the QQ register if the 780e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson // spilled def has a sub-register index. 781e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1d64QPseudo)) 782168f382dc67e5940cabdb28dc933c4f91cdd3137Bob Wilson .addFrameIndex(FI).addImm(16) 783168f382dc67e5940cabdb28dc933c4f91cdd3137Bob Wilson .addReg(SrcReg, getKillRegState(isKill)) 784168f382dc67e5940cabdb28dc933c4f91cdd3137Bob Wilson .addMemOperand(MMO)); 785e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson } else { 786e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson MachineInstrBuilder MIB = 787e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMDIA)) 78873fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling .addFrameIndex(FI)) 789e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson .addMemOperand(MMO); 790e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI); 791e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI); 792e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI); 793e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI); 794e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson } 795e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson } else 796e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson llvm_unreachable("Unknown reg class!"); 797e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson break; 798e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson case 64: 799e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson if (ARM::QQQQPRRegClass.hasSubClassEq(RC)) { 800e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson MachineInstrBuilder MIB = 801e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMDIA)) 802e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson .addFrameIndex(FI)) 803e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson .addMemOperand(MMO); 804e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI); 805e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI); 806e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI); 807e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson MIB = AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI); 808e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson MIB = AddDReg(MIB, SrcReg, ARM::dsub_4, 0, TRI); 809e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson MIB = AddDReg(MIB, SrcReg, ARM::dsub_5, 0, TRI); 810e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson MIB = AddDReg(MIB, SrcReg, ARM::dsub_6, 0, TRI); 811e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson AddDReg(MIB, SrcReg, ARM::dsub_7, 0, TRI); 812e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson } else 813e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson llvm_unreachable("Unknown reg class!"); 814e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson break; 815e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson default: 816e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson llvm_unreachable("Unknown reg class!"); 817334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 818334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 819334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 82034327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesenunsigned 82134327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund OlesenARMBaseInstrInfo::isStoreToStackSlot(const MachineInstr *MI, 82234327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen int &FrameIndex) const { 82334327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen switch (MI->getOpcode()) { 82434327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen default: break; 8257e3383c007f53b3a00675af225e428cb66ddf404Jim Grosbach case ARM::STRrs: 82634327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen case ARM::t2STRs: // FIXME: don't use t2STRs to access frame. 82734327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen if (MI->getOperand(1).isFI() && 82834327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen MI->getOperand(2).isReg() && 82934327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen MI->getOperand(3).isImm() && 83034327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen MI->getOperand(2).getReg() == 0 && 83134327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen MI->getOperand(3).getImm() == 0) { 83234327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen FrameIndex = MI->getOperand(1).getIndex(); 83334327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen return MI->getOperand(0).getReg(); 83434327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen } 83534327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen break; 8367e3383c007f53b3a00675af225e428cb66ddf404Jim Grosbach case ARM::STRi12: 83734327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen case ARM::t2STRi12: 83874472b4bf963c424da04f42dffdb94c85ef964bcJim Grosbach case ARM::tSTRspi: 83934327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen case ARM::VSTRD: 84034327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen case ARM::VSTRS: 84134327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen if (MI->getOperand(1).isFI() && 84234327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen MI->getOperand(2).isImm() && 84334327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen MI->getOperand(2).getImm() == 0) { 84434327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen FrameIndex = MI->getOperand(1).getIndex(); 84534327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen return MI->getOperand(0).getReg(); 84634327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen } 84734327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen break; 84828f08c93e75d291695ea89b9004145103292e85bJim Grosbach case ARM::VST1q64: 849d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen if (MI->getOperand(0).isFI() && 850d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen MI->getOperand(2).getSubReg() == 0) { 851d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen FrameIndex = MI->getOperand(0).getIndex(); 852d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen return MI->getOperand(2).getReg(); 853d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen } 85431bbc51ac9245bc82c933c9db8358ca9bb558ac5Jakob Stoklund Olesen break; 85573fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMQIA: 856d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen if (MI->getOperand(1).isFI() && 857d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen MI->getOperand(0).getSubReg() == 0) { 858d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen FrameIndex = MI->getOperand(1).getIndex(); 859d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen return MI->getOperand(0).getReg(); 860d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen } 861d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen break; 86234327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen } 86334327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen 86434327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen return 0; 86534327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen} 86634327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen 86736ee0e640554b8cc6ad1658fc3049e05d9967160Jakob Stoklund Olesenunsigned ARMBaseInstrInfo::isStoreToStackSlotPostFE(const MachineInstr *MI, 86836ee0e640554b8cc6ad1658fc3049e05d9967160Jakob Stoklund Olesen int &FrameIndex) const { 86936ee0e640554b8cc6ad1658fc3049e05d9967160Jakob Stoklund Olesen const MachineMemOperand *Dummy; 8705a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng return MI->mayStore() && hasStoreToStackSlot(MI, Dummy, FrameIndex); 87136ee0e640554b8cc6ad1658fc3049e05d9967160Jakob Stoklund Olesen} 87236ee0e640554b8cc6ad1658fc3049e05d9967160Jakob Stoklund Olesen 873334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinvoid ARMBaseInstrInfo:: 874334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinloadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 875334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned DestReg, int FI, 876746ad69e088176819981b4b2c5ac8dcd49f5e60eEvan Cheng const TargetRegisterClass *RC, 877746ad69e088176819981b4b2c5ac8dcd49f5e60eEvan Cheng const TargetRegisterInfo *TRI) const { 878c7f3ace20c325521c68335a1689645b43b06ddf0Chris Lattner DebugLoc DL; 879334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (I != MBB.end()) DL = I->getDebugLoc(); 880249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MachineFunction &MF = *MBB.getParent(); 881249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MachineFrameInfo &MFI = *MF.getFrameInfo(); 88231bc849123011b8eae6bb3c79876d9a3c26a6a1dJim Grosbach unsigned Align = MFI.getObjectAlignment(FI); 883249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MachineMemOperand *MMO = 88459db5496f4fc2ef6111569e542f8b65480ef14c1Chris Lattner MF.getMachineMemOperand( 885978e0dfe46e481bfb1281e683aa308329e879e95Jay Foad MachinePointerInfo::getFixedStack(FI), 88659db5496f4fc2ef6111569e542f8b65480ef14c1Chris Lattner MachineMemOperand::MOLoad, 887249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MFI.getObjectSize(FI), 88831bc849123011b8eae6bb3c79876d9a3c26a6a1dJim Grosbach Align); 889334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 890e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson switch (RC->getSize()) { 891e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson case 4: 892e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson if (ARM::GPRRegClass.hasSubClassEq(RC)) { 893e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::LDRi12), DestReg) 8943e5561247202bae994dd259a2d8dc4eff8f799f3Jim Grosbach .addFrameIndex(FI).addImm(0).addMemOperand(MMO)); 895e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson 896e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson } else if (ARM::SPRRegClass.hasSubClassEq(RC)) { 897e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRS), DestReg) 898d31c5496d7e1580058b5c6fbc8fd537a641ea590Evan Cheng .addFrameIndex(FI).addImm(0).addMemOperand(MMO)); 899e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson } else 900e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson llvm_unreachable("Unknown reg class!"); 901ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson break; 902e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson case 8: 903e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson if (ARM::DPRRegClass.hasSubClassEq(RC)) { 904e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRD), DestReg) 905249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov .addFrameIndex(FI).addImm(0).addMemOperand(MMO)); 906e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson } else 907e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson llvm_unreachable("Unknown reg class!"); 908ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson break; 909e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson case 16: 9105b2f9136644c58ae32e00d8317540692a697d1c9Jakob Stoklund Olesen if (ARM::DPairRegClass.hasSubClassEq(RC)) { 9117255a4e1332ccb69918ebe041dff05f9e4e5815dJakob Stoklund Olesen if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) { 91228f08c93e75d291695ea89b9004145103292e85bJim Grosbach AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1q64), DestReg) 913f967ca0eaf30325cabe3c1971bf0dba16cf1b027Bob Wilson .addFrameIndex(FI).addImm(16) 91469b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng .addMemOperand(MMO)); 915e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson } else { 916e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMQIA), DestReg) 917e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson .addFrameIndex(FI) 918e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson .addMemOperand(MMO)); 919e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson } 920e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson } else 921e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson llvm_unreachable("Unknown reg class!"); 922ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson break; 923e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson case 32: 924e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson if (ARM::QQPRRegClass.hasSubClassEq(RC)) { 925e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) { 926e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1d64QPseudo), DestReg) 927168f382dc67e5940cabdb28dc933c4f91cdd3137Bob Wilson .addFrameIndex(FI).addImm(16) 928168f382dc67e5940cabdb28dc933c4f91cdd3137Bob Wilson .addMemOperand(MMO)); 929e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson } else { 930e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson MachineInstrBuilder MIB = 93173fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMDIA)) 93273fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling .addFrameIndex(FI)) 933e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson .addMemOperand(MMO); 934fce711cb65716f86b4e150f42cbb597bbecf7dbeJakob Stoklund Olesen MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI); 935fce711cb65716f86b4e150f42cbb597bbecf7dbeJakob Stoklund Olesen MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI); 936fce711cb65716f86b4e150f42cbb597bbecf7dbeJakob Stoklund Olesen MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI); 937fce711cb65716f86b4e150f42cbb597bbecf7dbeJakob Stoklund Olesen MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::DefineNoRead, TRI); 9383247af294996ff8588077c06505b64966ad41542Jakob Stoklund Olesen if (TargetRegisterInfo::isPhysicalRegister(DestReg)) 9393247af294996ff8588077c06505b64966ad41542Jakob Stoklund Olesen MIB.addReg(DestReg, RegState::ImplicitDefine); 940e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson } 941e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson } else 942e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson llvm_unreachable("Unknown reg class!"); 943ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson break; 944e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson case 64: 945e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson if (ARM::QQQQPRRegClass.hasSubClassEq(RC)) { 946e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson MachineInstrBuilder MIB = 94773fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMDIA)) 94873fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling .addFrameIndex(FI)) 949e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson .addMemOperand(MMO); 950fce711cb65716f86b4e150f42cbb597bbecf7dbeJakob Stoklund Olesen MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI); 951fce711cb65716f86b4e150f42cbb597bbecf7dbeJakob Stoklund Olesen MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI); 952fce711cb65716f86b4e150f42cbb597bbecf7dbeJakob Stoklund Olesen MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI); 953fce711cb65716f86b4e150f42cbb597bbecf7dbeJakob Stoklund Olesen MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::DefineNoRead, TRI); 954fce711cb65716f86b4e150f42cbb597bbecf7dbeJakob Stoklund Olesen MIB = AddDReg(MIB, DestReg, ARM::dsub_4, RegState::DefineNoRead, TRI); 955fce711cb65716f86b4e150f42cbb597bbecf7dbeJakob Stoklund Olesen MIB = AddDReg(MIB, DestReg, ARM::dsub_5, RegState::DefineNoRead, TRI); 956fce711cb65716f86b4e150f42cbb597bbecf7dbeJakob Stoklund Olesen MIB = AddDReg(MIB, DestReg, ARM::dsub_6, RegState::DefineNoRead, TRI); 957fce711cb65716f86b4e150f42cbb597bbecf7dbeJakob Stoklund Olesen MIB = AddDReg(MIB, DestReg, ARM::dsub_7, RegState::DefineNoRead, TRI); 9583247af294996ff8588077c06505b64966ad41542Jakob Stoklund Olesen if (TargetRegisterInfo::isPhysicalRegister(DestReg)) 9593247af294996ff8588077c06505b64966ad41542Jakob Stoklund Olesen MIB.addReg(DestReg, RegState::ImplicitDefine); 960e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson } else 961e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson llvm_unreachable("Unknown reg class!"); 962ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson break; 963ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson default: 964ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson llvm_unreachable("Unknown regclass!"); 965334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 966334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 967334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 96834327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesenunsigned 96934327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund OlesenARMBaseInstrInfo::isLoadFromStackSlot(const MachineInstr *MI, 97034327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen int &FrameIndex) const { 97134327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen switch (MI->getOpcode()) { 97234327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen default: break; 9733e5561247202bae994dd259a2d8dc4eff8f799f3Jim Grosbach case ARM::LDRrs: 97434327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen case ARM::t2LDRs: // FIXME: don't use t2LDRs to access frame. 97534327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen if (MI->getOperand(1).isFI() && 97634327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen MI->getOperand(2).isReg() && 97734327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen MI->getOperand(3).isImm() && 97834327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen MI->getOperand(2).getReg() == 0 && 97934327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen MI->getOperand(3).getImm() == 0) { 98034327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen FrameIndex = MI->getOperand(1).getIndex(); 98134327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen return MI->getOperand(0).getReg(); 98234327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen } 98334327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen break; 9843e5561247202bae994dd259a2d8dc4eff8f799f3Jim Grosbach case ARM::LDRi12: 98534327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen case ARM::t2LDRi12: 98674472b4bf963c424da04f42dffdb94c85ef964bcJim Grosbach case ARM::tLDRspi: 98734327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen case ARM::VLDRD: 98834327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen case ARM::VLDRS: 98934327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen if (MI->getOperand(1).isFI() && 99034327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen MI->getOperand(2).isImm() && 99134327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen MI->getOperand(2).getImm() == 0) { 99234327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen FrameIndex = MI->getOperand(1).getIndex(); 993d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen return MI->getOperand(0).getReg(); 994d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen } 995d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen break; 99628f08c93e75d291695ea89b9004145103292e85bJim Grosbach case ARM::VLD1q64: 997d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen if (MI->getOperand(1).isFI() && 998d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen MI->getOperand(0).getSubReg() == 0) { 999d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen FrameIndex = MI->getOperand(1).getIndex(); 100006f264e504d75f0426eea55b9f9e36c780d8a4fcJakob Stoklund Olesen return MI->getOperand(0).getReg(); 100106f264e504d75f0426eea55b9f9e36c780d8a4fcJakob Stoklund Olesen } 100206f264e504d75f0426eea55b9f9e36c780d8a4fcJakob Stoklund Olesen break; 100373fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMQIA: 100406f264e504d75f0426eea55b9f9e36c780d8a4fcJakob Stoklund Olesen if (MI->getOperand(1).isFI() && 100506f264e504d75f0426eea55b9f9e36c780d8a4fcJakob Stoklund Olesen MI->getOperand(0).getSubReg() == 0) { 100606f264e504d75f0426eea55b9f9e36c780d8a4fcJakob Stoklund Olesen FrameIndex = MI->getOperand(1).getIndex(); 100734327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen return MI->getOperand(0).getReg(); 100834327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen } 100934327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen break; 101034327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen } 101134327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen 101234327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen return 0; 101334327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen} 101434327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen 101536ee0e640554b8cc6ad1658fc3049e05d9967160Jakob Stoklund Olesenunsigned ARMBaseInstrInfo::isLoadFromStackSlotPostFE(const MachineInstr *MI, 101636ee0e640554b8cc6ad1658fc3049e05d9967160Jakob Stoklund Olesen int &FrameIndex) const { 101736ee0e640554b8cc6ad1658fc3049e05d9967160Jakob Stoklund Olesen const MachineMemOperand *Dummy; 10185a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng return MI->mayLoad() && hasLoadFromStackSlot(MI, Dummy, FrameIndex); 101936ee0e640554b8cc6ad1658fc3049e05d9967160Jakob Stoklund Olesen} 102036ee0e640554b8cc6ad1658fc3049e05d9967160Jakob Stoklund Olesen 1021142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesenbool ARMBaseInstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const{ 1022142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen // This hook gets to expand COPY instructions before they become 1023142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen // copyPhysReg() calls. Look for VMOVS instructions that can legally be 1024142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen // widened to VMOVD. We prefer the VMOVD when possible because it may be 1025142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen // changed into a VORR that can go down the NEON pipeline. 1026142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen if (!WidenVMOVS || !MI->isCopy()) 1027142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen return false; 1028142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen 1029142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen // Look for a copy between even S-registers. That is where we keep floats 1030142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen // when using NEON v2f32 instructions for f32 arithmetic. 1031142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen unsigned DstRegS = MI->getOperand(0).getReg(); 1032142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen unsigned SrcRegS = MI->getOperand(1).getReg(); 1033142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen if (!ARM::SPRRegClass.contains(DstRegS, SrcRegS)) 1034142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen return false; 1035142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen 1036142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen const TargetRegisterInfo *TRI = &getRegisterInfo(); 1037142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen unsigned DstRegD = TRI->getMatchingSuperReg(DstRegS, ARM::ssub_0, 1038142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen &ARM::DPRRegClass); 1039142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen unsigned SrcRegD = TRI->getMatchingSuperReg(SrcRegS, ARM::ssub_0, 1040142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen &ARM::DPRRegClass); 1041142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen if (!DstRegD || !SrcRegD) 1042142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen return false; 1043142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen 1044142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen // We want to widen this into a DstRegD = VMOVD SrcRegD copy. This is only 1045142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen // legal if the COPY already defines the full DstRegD, and it isn't a 1046142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen // sub-register insertion. 1047142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen if (!MI->definesRegister(DstRegD, TRI) || MI->readsRegister(DstRegD, TRI)) 1048142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen return false; 1049142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen 10501c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen // A dead copy shouldn't show up here, but reject it just in case. 10511c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen if (MI->getOperand(0).isDead()) 10521c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen return false; 10531c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen 10541c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen // All clear, widen the COPY. 1055142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen DEBUG(dbgs() << "widening: " << *MI); 10561c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen 10571c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen // Get rid of the old <imp-def> of DstRegD. Leave it if it defines a Q-reg 10581c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen // or some other super-register. 10591c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen int ImpDefIdx = MI->findRegisterDefOperandIdx(DstRegD); 10601c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen if (ImpDefIdx != -1) 10611c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen MI->RemoveOperand(ImpDefIdx); 10621c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen 10631c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen // Change the opcode and operands. 1064142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen MI->setDesc(get(ARM::VMOVD)); 1065142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen MI->getOperand(0).setReg(DstRegD); 1066142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen MI->getOperand(1).setReg(SrcRegD); 1067142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen AddDefaultPred(MachineInstrBuilder(MI)); 10681c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen 10691c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen // We are now reading SrcRegD instead of SrcRegS. This may upset the 10701c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen // register scavenger and machine verifier, so we need to indicate that we 10711c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen // are reading an undefined value from SrcRegD, but a proper value from 10721c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen // SrcRegS. 10731c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen MI->getOperand(1).setIsUndef(); 10741c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen MachineInstrBuilder(MI).addReg(SrcRegS, RegState::Implicit); 10751c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen 10761c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen // SrcRegD may actually contain an unrelated value in the ssub_1 10771c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen // sub-register. Don't kill it. Only kill the ssub_0 sub-register. 10781c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen if (MI->getOperand(1).isKill()) { 10791c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen MI->getOperand(1).setIsKill(false); 10801c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen MI->addRegisterKilled(SrcRegS, TRI, true); 10811c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen } 10821c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen 1083142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen DEBUG(dbgs() << "replaced by: " << *MI); 1084142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen return true; 1085142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen} 1086142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen 108762b50656ceb854eb0be265d63b2a1d46e7400d8aEvan ChengMachineInstr* 108862b50656ceb854eb0be265d63b2a1d46e7400d8aEvan ChengARMBaseInstrInfo::emitFrameIndexDebugValue(MachineFunction &MF, 10898601a3d4decff0a380e059b037dabf71075497d3Evan Cheng int FrameIx, uint64_t Offset, 109062b50656ceb854eb0be265d63b2a1d46e7400d8aEvan Cheng const MDNode *MDPtr, 109162b50656ceb854eb0be265d63b2a1d46e7400d8aEvan Cheng DebugLoc DL) const { 109262b50656ceb854eb0be265d63b2a1d46e7400d8aEvan Cheng MachineInstrBuilder MIB = BuildMI(MF, DL, get(ARM::DBG_VALUE)) 109362b50656ceb854eb0be265d63b2a1d46e7400d8aEvan Cheng .addFrameIndex(FrameIx).addImm(0).addImm(Offset).addMetadata(MDPtr); 109462b50656ceb854eb0be265d63b2a1d46e7400d8aEvan Cheng return &*MIB; 109562b50656ceb854eb0be265d63b2a1d46e7400d8aEvan Cheng} 109662b50656ceb854eb0be265d63b2a1d46e7400d8aEvan Cheng 109730ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen/// Create a copy of a const pool value. Update CPI to the new index and return 109830ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen/// the label UID. 109930ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesenstatic unsigned duplicateCPV(MachineFunction &MF, unsigned &CPI) { 110030ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen MachineConstantPool *MCP = MF.getConstantPool(); 110130ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 110230ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen 110330ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPI]; 110430ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen assert(MCPE.isMachineConstantPoolEntry() && 110530ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen "Expecting a machine constantpool entry!"); 110630ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen ARMConstantPoolValue *ACPV = 110730ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal); 110830ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen 11095de5d4b6d0eb3fd379fa571d82f6fa764460b3b8Evan Cheng unsigned PCLabelId = AFI->createPICLabelUId(); 111030ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen ARMConstantPoolValue *NewCPV = 0; 111151f5b67395780b8421f4aa6ee998ed51b23dae9dJim Grosbach // FIXME: The below assumes PIC relocation model and that the function 111251f5b67395780b8421f4aa6ee998ed51b23dae9dJim Grosbach // is Thumb mode (t1 or t2). PCAdjustment would be 8 for ARM mode PIC, and 111351f5b67395780b8421f4aa6ee998ed51b23dae9dJim Grosbach // zero for non-PIC in ARM or Thumb. The callers are all of thumb LDR 111451f5b67395780b8421f4aa6ee998ed51b23dae9dJim Grosbach // instructions, so that's probably OK, but is PIC always correct when 111551f5b67395780b8421f4aa6ee998ed51b23dae9dJim Grosbach // we get here? 111630ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen if (ACPV->isGlobalValue()) 11175bb779976a7d8e48408051ec2289fe69206dc072Bill Wendling NewCPV = ARMConstantPoolConstant:: 11185bb779976a7d8e48408051ec2289fe69206dc072Bill Wendling Create(cast<ARMConstantPoolConstant>(ACPV)->getGV(), PCLabelId, 11195bb779976a7d8e48408051ec2289fe69206dc072Bill Wendling ARMCP::CPValue, 4); 112030ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen else if (ACPV->isExtSymbol()) 1121fe31e673506ef9a1080eaa684b43b34178c6f447Bill Wendling NewCPV = ARMConstantPoolSymbol:: 1122fe31e673506ef9a1080eaa684b43b34178c6f447Bill Wendling Create(MF.getFunction()->getContext(), 1123fe31e673506ef9a1080eaa684b43b34178c6f447Bill Wendling cast<ARMConstantPoolSymbol>(ACPV)->getSymbol(), PCLabelId, 4); 112430ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen else if (ACPV->isBlockAddress()) 11255bb779976a7d8e48408051ec2289fe69206dc072Bill Wendling NewCPV = ARMConstantPoolConstant:: 11265bb779976a7d8e48408051ec2289fe69206dc072Bill Wendling Create(cast<ARMConstantPoolConstant>(ACPV)->getBlockAddress(), PCLabelId, 11275bb779976a7d8e48408051ec2289fe69206dc072Bill Wendling ARMCP::CPBlockAddress, 4); 112851f5b67395780b8421f4aa6ee998ed51b23dae9dJim Grosbach else if (ACPV->isLSDA()) 11295bb779976a7d8e48408051ec2289fe69206dc072Bill Wendling NewCPV = ARMConstantPoolConstant::Create(MF.getFunction(), PCLabelId, 11305bb779976a7d8e48408051ec2289fe69206dc072Bill Wendling ARMCP::CPLSDA, 4); 1131e00897c5a91febe90ba21082fc636be892bf9bf1Bill Wendling else if (ACPV->isMachineBasicBlock()) 11323320f2a3bfd4daec23ba7ceb50525140cc6316daBill Wendling NewCPV = ARMConstantPoolMBB:: 11333320f2a3bfd4daec23ba7ceb50525140cc6316daBill Wendling Create(MF.getFunction()->getContext(), 11343320f2a3bfd4daec23ba7ceb50525140cc6316daBill Wendling cast<ARMConstantPoolMBB>(ACPV)->getMBB(), PCLabelId, 4); 113530ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen else 113630ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen llvm_unreachable("Unexpected ARM constantpool value type!!"); 113730ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen CPI = MCP->getConstantPoolIndex(NewCPV, MCPE.getAlignment()); 113830ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen return PCLabelId; 113930ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen} 114030ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen 1141fdc834046efd427d474e3b899ec69354c05071e0Evan Chengvoid ARMBaseInstrInfo:: 1142fdc834046efd427d474e3b899ec69354c05071e0Evan ChengreMaterialize(MachineBasicBlock &MBB, 1143fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng MachineBasicBlock::iterator I, 1144fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng unsigned DestReg, unsigned SubIdx, 1145d57cdd5683ea926e489067364fb7ffe5fd5d35eeEvan Cheng const MachineInstr *Orig, 11469edf7deb37f0f97664f279040fa15d89f32e23d9Jakob Stoklund Olesen const TargetRegisterInfo &TRI) const { 1147fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng unsigned Opcode = Orig->getOpcode(); 1148fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng switch (Opcode) { 1149fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng default: { 1150fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig); 11519edf7deb37f0f97664f279040fa15d89f32e23d9Jakob Stoklund Olesen MI->substituteRegister(Orig->getOperand(0).getReg(), DestReg, SubIdx, TRI); 1152fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng MBB.insert(I, MI); 1153fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng break; 1154fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng } 1155fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng case ARM::tLDRpci_pic: 1156fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng case ARM::t2LDRpci_pic: { 1157fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng MachineFunction &MF = *MBB.getParent(); 1158fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng unsigned CPI = Orig->getOperand(1).getIndex(); 115930ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen unsigned PCLabelId = duplicateCPV(MF, CPI); 1160fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng MachineInstrBuilder MIB = BuildMI(MBB, I, Orig->getDebugLoc(), get(Opcode), 1161fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng DestReg) 1162fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng .addConstantPoolIndex(CPI).addImm(PCLabelId); 1163d7d030a44796adc73a6eaa939cd17e52047734c1Chris Lattner MIB->setMemRefs(Orig->memoperands_begin(), Orig->memoperands_end()); 1164fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng break; 1165fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng } 1166fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng } 1167fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng} 1168fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng 116930ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund OlesenMachineInstr * 117030ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund OlesenARMBaseInstrInfo::duplicate(MachineInstr *Orig, MachineFunction &MF) const { 117130ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen MachineInstr *MI = TargetInstrInfoImpl::duplicate(Orig, MF); 117230ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen switch(Orig->getOpcode()) { 117330ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen case ARM::tLDRpci_pic: 117430ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen case ARM::t2LDRpci_pic: { 117530ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen unsigned CPI = Orig->getOperand(1).getIndex(); 117630ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen unsigned PCLabelId = duplicateCPV(MF, CPI); 117730ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen Orig->getOperand(1).setIndex(CPI); 117830ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen Orig->getOperand(2).setImm(PCLabelId); 117930ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen break; 118030ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen } 118130ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen } 118230ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen return MI; 118330ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen} 118430ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen 1185506049f29f4f202a8e45feb916cc0264440a7f6dEvan Chengbool ARMBaseInstrInfo::produceSameValue(const MachineInstr *MI0, 11869fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng const MachineInstr *MI1, 11879fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng const MachineRegisterInfo *MRI) const { 1188d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng int Opcode = MI0->getOpcode(); 1189d7e3cc840b81b0438e47f05d9664137a198876dfEvan Cheng if (Opcode == ARM::t2LDRpci || 11909b82425cb0105fd5704f6b9bcd5e7693b05b1759Evan Cheng Opcode == ARM::t2LDRpci_pic || 11919b82425cb0105fd5704f6b9bcd5e7693b05b1759Evan Cheng Opcode == ARM::tLDRpci || 11929fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng Opcode == ARM::tLDRpci_pic || 119353519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng Opcode == ARM::MOV_ga_dyn || 119453519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng Opcode == ARM::MOV_ga_pcrel || 119553519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng Opcode == ARM::MOV_ga_pcrel_ldr || 119653519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng Opcode == ARM::t2MOV_ga_dyn || 119753519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng Opcode == ARM::t2MOV_ga_pcrel) { 1198d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng if (MI1->getOpcode() != Opcode) 1199d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng return false; 1200d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng if (MI0->getNumOperands() != MI1->getNumOperands()) 1201d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng return false; 1202d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng 1203d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng const MachineOperand &MO0 = MI0->getOperand(1); 1204d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng const MachineOperand &MO1 = MI1->getOperand(1); 1205d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng if (MO0.getOffset() != MO1.getOffset()) 1206d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng return false; 1207d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng 120853519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng if (Opcode == ARM::MOV_ga_dyn || 120953519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng Opcode == ARM::MOV_ga_pcrel || 121053519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng Opcode == ARM::MOV_ga_pcrel_ldr || 121153519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng Opcode == ARM::t2MOV_ga_dyn || 121253519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng Opcode == ARM::t2MOV_ga_pcrel) 12139fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng // Ignore the PC labels. 12149fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng return MO0.getGlobal() == MO1.getGlobal(); 12159fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng 1216d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng const MachineFunction *MF = MI0->getParent()->getParent(); 1217d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng const MachineConstantPool *MCP = MF->getConstantPool(); 1218d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng int CPI0 = MO0.getIndex(); 1219d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng int CPI1 = MO1.getIndex(); 1220d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng const MachineConstantPoolEntry &MCPE0 = MCP->getConstants()[CPI0]; 1221d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng const MachineConstantPoolEntry &MCPE1 = MCP->getConstants()[CPI1]; 1222d700617193f3d11deb83cd56c4ababbc8e0ea19fEvan Cheng bool isARMCP0 = MCPE0.isMachineConstantPoolEntry(); 1223d700617193f3d11deb83cd56c4ababbc8e0ea19fEvan Cheng bool isARMCP1 = MCPE1.isMachineConstantPoolEntry(); 1224d700617193f3d11deb83cd56c4ababbc8e0ea19fEvan Cheng if (isARMCP0 && isARMCP1) { 1225d700617193f3d11deb83cd56c4ababbc8e0ea19fEvan Cheng ARMConstantPoolValue *ACPV0 = 1226d700617193f3d11deb83cd56c4ababbc8e0ea19fEvan Cheng static_cast<ARMConstantPoolValue*>(MCPE0.Val.MachineCPVal); 1227d700617193f3d11deb83cd56c4ababbc8e0ea19fEvan Cheng ARMConstantPoolValue *ACPV1 = 1228d700617193f3d11deb83cd56c4ababbc8e0ea19fEvan Cheng static_cast<ARMConstantPoolValue*>(MCPE1.Val.MachineCPVal); 1229d700617193f3d11deb83cd56c4ababbc8e0ea19fEvan Cheng return ACPV0->hasSameValue(ACPV1); 1230d700617193f3d11deb83cd56c4ababbc8e0ea19fEvan Cheng } else if (!isARMCP0 && !isARMCP1) { 1231d700617193f3d11deb83cd56c4ababbc8e0ea19fEvan Cheng return MCPE0.Val.ConstVal == MCPE1.Val.ConstVal; 1232d700617193f3d11deb83cd56c4ababbc8e0ea19fEvan Cheng } 1233d700617193f3d11deb83cd56c4ababbc8e0ea19fEvan Cheng return false; 12349fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng } else if (Opcode == ARM::PICLDR) { 12359fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng if (MI1->getOpcode() != Opcode) 12369fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng return false; 12379fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng if (MI0->getNumOperands() != MI1->getNumOperands()) 12389fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng return false; 12399fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng 12409fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng unsigned Addr0 = MI0->getOperand(1).getReg(); 12419fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng unsigned Addr1 = MI1->getOperand(1).getReg(); 12429fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng if (Addr0 != Addr1) { 12439fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng if (!MRI || 12449fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng !TargetRegisterInfo::isVirtualRegister(Addr0) || 12459fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng !TargetRegisterInfo::isVirtualRegister(Addr1)) 12469fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng return false; 12479fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng 12489fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng // This assumes SSA form. 12499fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng MachineInstr *Def0 = MRI->getVRegDef(Addr0); 12509fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng MachineInstr *Def1 = MRI->getVRegDef(Addr1); 12519fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng // Check if the loaded value, e.g. a constantpool of a global address, are 12529fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng // the same. 12539fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng if (!produceSameValue(Def0, Def1, MRI)) 12549fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng return false; 12559fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng } 12569fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng 12579fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng for (unsigned i = 3, e = MI0->getNumOperands(); i != e; ++i) { 12589fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng // %vreg12<def> = PICLDR %vreg11, 0, pred:14, pred:%noreg 12599fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng const MachineOperand &MO0 = MI0->getOperand(i); 12609fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng const MachineOperand &MO1 = MI1->getOperand(i); 12619fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng if (!MO0.isIdenticalTo(MO1)) 12629fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng return false; 12639fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng } 12649fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng return true; 1265d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng } 1266d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng 1267506049f29f4f202a8e45feb916cc0264440a7f6dEvan Cheng return MI0->isIdenticalTo(MI1, MachineInstr::IgnoreVRegDefs); 1268d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng} 1269d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng 12704b722108e2cf8e77157e0879a23789cd44829933Bill Wendling/// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to 12714b722108e2cf8e77157e0879a23789cd44829933Bill Wendling/// determine if two loads are loading from the same base address. It should 12724b722108e2cf8e77157e0879a23789cd44829933Bill Wendling/// only return true if the base pointers are the same and the only differences 12734b722108e2cf8e77157e0879a23789cd44829933Bill Wendling/// between the two addresses is the offset. It also returns the offsets by 12744b722108e2cf8e77157e0879a23789cd44829933Bill Wendling/// reference. 12754b722108e2cf8e77157e0879a23789cd44829933Bill Wendlingbool ARMBaseInstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, 12764b722108e2cf8e77157e0879a23789cd44829933Bill Wendling int64_t &Offset1, 12774b722108e2cf8e77157e0879a23789cd44829933Bill Wendling int64_t &Offset2) const { 12784b722108e2cf8e77157e0879a23789cd44829933Bill Wendling // Don't worry about Thumb: just ARM and Thumb2. 12794b722108e2cf8e77157e0879a23789cd44829933Bill Wendling if (Subtarget.isThumb1Only()) return false; 12804b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 12814b722108e2cf8e77157e0879a23789cd44829933Bill Wendling if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode()) 12824b722108e2cf8e77157e0879a23789cd44829933Bill Wendling return false; 12834b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 12844b722108e2cf8e77157e0879a23789cd44829933Bill Wendling switch (Load1->getMachineOpcode()) { 12854b722108e2cf8e77157e0879a23789cd44829933Bill Wendling default: 12864b722108e2cf8e77157e0879a23789cd44829933Bill Wendling return false; 12873e5561247202bae994dd259a2d8dc4eff8f799f3Jim Grosbach case ARM::LDRi12: 1288c1d30212e911d1e55ff6b25bffefb503708883c3Jim Grosbach case ARM::LDRBi12: 12894b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::LDRD: 12904b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::LDRH: 12914b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::LDRSB: 12924b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::LDRSH: 12934b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::VLDRD: 12944b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::VLDRS: 12954b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::t2LDRi8: 12964b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::t2LDRDi8: 12974b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::t2LDRSHi8: 12984b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::t2LDRi12: 12994b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::t2LDRSHi12: 13004b722108e2cf8e77157e0879a23789cd44829933Bill Wendling break; 13014b722108e2cf8e77157e0879a23789cd44829933Bill Wendling } 13024b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 13034b722108e2cf8e77157e0879a23789cd44829933Bill Wendling switch (Load2->getMachineOpcode()) { 13044b722108e2cf8e77157e0879a23789cd44829933Bill Wendling default: 13054b722108e2cf8e77157e0879a23789cd44829933Bill Wendling return false; 13063e5561247202bae994dd259a2d8dc4eff8f799f3Jim Grosbach case ARM::LDRi12: 1307c1d30212e911d1e55ff6b25bffefb503708883c3Jim Grosbach case ARM::LDRBi12: 13084b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::LDRD: 13094b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::LDRH: 13104b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::LDRSB: 13114b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::LDRSH: 13124b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::VLDRD: 13134b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::VLDRS: 13144b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::t2LDRi8: 13154b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::t2LDRDi8: 13164b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::t2LDRSHi8: 13174b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::t2LDRi12: 13184b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::t2LDRSHi12: 13194b722108e2cf8e77157e0879a23789cd44829933Bill Wendling break; 13204b722108e2cf8e77157e0879a23789cd44829933Bill Wendling } 13214b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 13224b722108e2cf8e77157e0879a23789cd44829933Bill Wendling // Check if base addresses and chain operands match. 13234b722108e2cf8e77157e0879a23789cd44829933Bill Wendling if (Load1->getOperand(0) != Load2->getOperand(0) || 13244b722108e2cf8e77157e0879a23789cd44829933Bill Wendling Load1->getOperand(4) != Load2->getOperand(4)) 13254b722108e2cf8e77157e0879a23789cd44829933Bill Wendling return false; 13264b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 13274b722108e2cf8e77157e0879a23789cd44829933Bill Wendling // Index should be Reg0. 13284b722108e2cf8e77157e0879a23789cd44829933Bill Wendling if (Load1->getOperand(3) != Load2->getOperand(3)) 13294b722108e2cf8e77157e0879a23789cd44829933Bill Wendling return false; 13304b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 13314b722108e2cf8e77157e0879a23789cd44829933Bill Wendling // Determine the offsets. 13324b722108e2cf8e77157e0879a23789cd44829933Bill Wendling if (isa<ConstantSDNode>(Load1->getOperand(1)) && 13334b722108e2cf8e77157e0879a23789cd44829933Bill Wendling isa<ConstantSDNode>(Load2->getOperand(1))) { 13344b722108e2cf8e77157e0879a23789cd44829933Bill Wendling Offset1 = cast<ConstantSDNode>(Load1->getOperand(1))->getSExtValue(); 13354b722108e2cf8e77157e0879a23789cd44829933Bill Wendling Offset2 = cast<ConstantSDNode>(Load2->getOperand(1))->getSExtValue(); 13364b722108e2cf8e77157e0879a23789cd44829933Bill Wendling return true; 13374b722108e2cf8e77157e0879a23789cd44829933Bill Wendling } 13384b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 13394b722108e2cf8e77157e0879a23789cd44829933Bill Wendling return false; 13404b722108e2cf8e77157e0879a23789cd44829933Bill Wendling} 13414b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 13424b722108e2cf8e77157e0879a23789cd44829933Bill Wendling/// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to 13437a2bdde0a0eebcd2125055e0eacaca040f0b766cChris Lattner/// determine (in conjunction with areLoadsFromSameBasePtr) if two loads should 13444b722108e2cf8e77157e0879a23789cd44829933Bill Wendling/// be scheduled togther. On some targets if two loads are loading from 13454b722108e2cf8e77157e0879a23789cd44829933Bill Wendling/// addresses in the same cache line, it's better if they are scheduled 13464b722108e2cf8e77157e0879a23789cd44829933Bill Wendling/// together. This function takes two integers that represent the load offsets 13474b722108e2cf8e77157e0879a23789cd44829933Bill Wendling/// from the common base address. It returns true if it decides it's desirable 13484b722108e2cf8e77157e0879a23789cd44829933Bill Wendling/// to schedule the two loads together. "NumLoads" is the number of loads that 13494b722108e2cf8e77157e0879a23789cd44829933Bill Wendling/// have already been scheduled after Load1. 13504b722108e2cf8e77157e0879a23789cd44829933Bill Wendlingbool ARMBaseInstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, 13514b722108e2cf8e77157e0879a23789cd44829933Bill Wendling int64_t Offset1, int64_t Offset2, 13524b722108e2cf8e77157e0879a23789cd44829933Bill Wendling unsigned NumLoads) const { 13534b722108e2cf8e77157e0879a23789cd44829933Bill Wendling // Don't worry about Thumb: just ARM and Thumb2. 13544b722108e2cf8e77157e0879a23789cd44829933Bill Wendling if (Subtarget.isThumb1Only()) return false; 13554b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 13564b722108e2cf8e77157e0879a23789cd44829933Bill Wendling assert(Offset2 > Offset1); 13574b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 13584b722108e2cf8e77157e0879a23789cd44829933Bill Wendling if ((Offset2 - Offset1) / 8 > 64) 13594b722108e2cf8e77157e0879a23789cd44829933Bill Wendling return false; 13604b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 13614b722108e2cf8e77157e0879a23789cd44829933Bill Wendling if (Load1->getMachineOpcode() != Load2->getMachineOpcode()) 13624b722108e2cf8e77157e0879a23789cd44829933Bill Wendling return false; // FIXME: overly conservative? 13634b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 13644b722108e2cf8e77157e0879a23789cd44829933Bill Wendling // Four loads in a row should be sufficient. 13654b722108e2cf8e77157e0879a23789cd44829933Bill Wendling if (NumLoads >= 3) 13664b722108e2cf8e77157e0879a23789cd44829933Bill Wendling return false; 13674b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 13684b722108e2cf8e77157e0879a23789cd44829933Bill Wendling return true; 13694b722108e2cf8e77157e0879a23789cd44829933Bill Wendling} 13704b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 137186050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Chengbool ARMBaseInstrInfo::isSchedulingBoundary(const MachineInstr *MI, 137286050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng const MachineBasicBlock *MBB, 137386050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng const MachineFunction &MF) const { 137457bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach // Debug info is never a scheduling boundary. It's necessary to be explicit 137557bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach // due to the special treatment of IT instructions below, otherwise a 137657bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach // dbg_value followed by an IT will result in the IT instruction being 137757bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach // considered a scheduling hazard, which is wrong. It should be the actual 137857bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach // instruction preceding the dbg_value instruction(s), just like it is 137957bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach // when debug info is not present. 138057bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach if (MI->isDebugValue()) 138157bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach return false; 138257bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach 138386050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // Terminators and labels can't be scheduled around. 13845a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng if (MI->isTerminator() || MI->isLabel()) 138586050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng return true; 138686050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng 138786050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // Treat the start of the IT block as a scheduling boundary, but schedule 138886050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // t2IT along with all instructions following it. 138986050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // FIXME: This is a big hammer. But the alternative is to add all potential 139086050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // true and anti dependencies to IT block instructions as implicit operands 139186050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // to the t2IT instruction. The added compile time and complexity does not 139286050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // seem worth it. 139386050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng MachineBasicBlock::const_iterator I = MI; 139457bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach // Make sure to skip any dbg_value instructions 139557bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach while (++I != MBB->end() && I->isDebugValue()) 139657bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach ; 139757bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach if (I != MBB->end() && I->getOpcode() == ARM::t2IT) 139886050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng return true; 139986050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng 140086050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // Don't attempt to schedule around any instruction that defines 140186050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // a stack-oriented pointer, as it's unlikely to be profitable. This 140286050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // saves compile time, because it doesn't require every single 140386050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // stack slot reference to depend on the instruction that does the 140486050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // modification. 1405a1aa8db51715bdd21770fbe4f7d7abf2c5d28829Jakob Stoklund Olesen // Calls don't actually change the stack pointer, even if they have imp-defs. 1406209600bb8830036f981238494ab0188c25364837Jakob Stoklund Olesen // No ARM calling conventions change the stack pointer. (X86 calling 1407209600bb8830036f981238494ab0188c25364837Jakob Stoklund Olesen // conventions sometimes do). 1408a1aa8db51715bdd21770fbe4f7d7abf2c5d28829Jakob Stoklund Olesen if (!MI->isCall() && MI->definesRegister(ARM::SP)) 140986050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng return true; 141086050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng 141186050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng return false; 141286050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng} 141386050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng 1414f81b7f6069b27c0a515070dcb392f6828437412fJakub Staszakbool ARMBaseInstrInfo:: 1415f81b7f6069b27c0a515070dcb392f6828437412fJakub StaszakisProfitableToIfCvt(MachineBasicBlock &MBB, 1416f81b7f6069b27c0a515070dcb392f6828437412fJakub Staszak unsigned NumCycles, unsigned ExtraPredCycles, 1417f81b7f6069b27c0a515070dcb392f6828437412fJakub Staszak const BranchProbability &Probability) const { 14185876db7a66fcc4ec4444a9f3e387c1cdc8baf9e5Cameron Zwarich if (!NumCycles) 141913151432edace19ee867a93b5c14573df4f75d24Evan Cheng return false; 14202bbb76909126db5bed6bde84b16d94ab5de4d372Michael J. Spencer 1421b20b85168c0e9819e6545f08281e9b83c82108f0Owen Anderson // Attempt to estimate the relative costs of predication versus branching. 1422f81b7f6069b27c0a515070dcb392f6828437412fJakub Staszak unsigned UnpredCost = Probability.getNumerator() * NumCycles; 1423f81b7f6069b27c0a515070dcb392f6828437412fJakub Staszak UnpredCost /= Probability.getDenominator(); 1424f81b7f6069b27c0a515070dcb392f6828437412fJakub Staszak UnpredCost += 1; // The branch itself 1425f81b7f6069b27c0a515070dcb392f6828437412fJakub Staszak UnpredCost += Subtarget.getMispredictionPenalty() / 10; 14262bbb76909126db5bed6bde84b16d94ab5de4d372Michael J. Spencer 1427f81b7f6069b27c0a515070dcb392f6828437412fJakub Staszak return (NumCycles + ExtraPredCycles) <= UnpredCost; 142813151432edace19ee867a93b5c14573df4f75d24Evan Cheng} 14292bbb76909126db5bed6bde84b16d94ab5de4d372Michael J. Spencer 143013151432edace19ee867a93b5c14573df4f75d24Evan Chengbool ARMBaseInstrInfo:: 14318239daf7c83a65a189c352cce3191cdc3bbfe151Evan ChengisProfitableToIfCvt(MachineBasicBlock &TMBB, 14328239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng unsigned TCycles, unsigned TExtra, 14338239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng MachineBasicBlock &FMBB, 14348239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng unsigned FCycles, unsigned FExtra, 1435f81b7f6069b27c0a515070dcb392f6828437412fJakub Staszak const BranchProbability &Probability) const { 14368239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng if (!TCycles || !FCycles) 1437b20b85168c0e9819e6545f08281e9b83c82108f0Owen Anderson return false; 14382bbb76909126db5bed6bde84b16d94ab5de4d372Michael J. Spencer 1439b20b85168c0e9819e6545f08281e9b83c82108f0Owen Anderson // Attempt to estimate the relative costs of predication versus branching. 1440f81b7f6069b27c0a515070dcb392f6828437412fJakub Staszak unsigned TUnpredCost = Probability.getNumerator() * TCycles; 1441f81b7f6069b27c0a515070dcb392f6828437412fJakub Staszak TUnpredCost /= Probability.getDenominator(); 1442e23dc9c0ef50b0a1934c04c1786f3a0478d62f41Andrew Trick 1443f81b7f6069b27c0a515070dcb392f6828437412fJakub Staszak uint32_t Comp = Probability.getDenominator() - Probability.getNumerator(); 1444f81b7f6069b27c0a515070dcb392f6828437412fJakub Staszak unsigned FUnpredCost = Comp * FCycles; 1445f81b7f6069b27c0a515070dcb392f6828437412fJakub Staszak FUnpredCost /= Probability.getDenominator(); 1446f81b7f6069b27c0a515070dcb392f6828437412fJakub Staszak 1447f81b7f6069b27c0a515070dcb392f6828437412fJakub Staszak unsigned UnpredCost = TUnpredCost + FUnpredCost; 1448f81b7f6069b27c0a515070dcb392f6828437412fJakub Staszak UnpredCost += 1; // The branch itself 1449f81b7f6069b27c0a515070dcb392f6828437412fJakub Staszak UnpredCost += Subtarget.getMispredictionPenalty() / 10; 1450f81b7f6069b27c0a515070dcb392f6828437412fJakub Staszak 1451f81b7f6069b27c0a515070dcb392f6828437412fJakub Staszak return (TCycles + FCycles + TExtra + FExtra) <= UnpredCost; 145213151432edace19ee867a93b5c14573df4f75d24Evan Cheng} 145313151432edace19ee867a93b5c14573df4f75d24Evan Cheng 14548fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng/// getInstrPredicate - If instruction is predicated, returns its predicate 14558fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng/// condition, otherwise returns AL. It also returns the condition code 14568fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng/// register by reference. 14575adb66a646e2ec32265263739f5b01c3f50c176aEvan ChengARMCC::CondCodes 14585adb66a646e2ec32265263739f5b01c3f50c176aEvan Chengllvm::getInstrPredicate(const MachineInstr *MI, unsigned &PredReg) { 14598fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng int PIdx = MI->findFirstPredOperandIdx(); 14608fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng if (PIdx == -1) { 14618fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng PredReg = 0; 14628fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng return ARMCC::AL; 14638fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng } 14648fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng 14658fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng PredReg = MI->getOperand(PIdx+1).getReg(); 14668fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng return (ARMCC::CondCodes)MI->getOperand(PIdx).getImm(); 14678fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng} 14688fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng 14698fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng 14706495f63945e8dbde81f03a1dc2ab421993b9a495Evan Chengint llvm::getMatchingCondBranchOpcode(int Opc) { 14715ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng if (Opc == ARM::B) 14725ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng return ARM::Bcc; 14734d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie if (Opc == ARM::tB) 14745ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng return ARM::tBcc; 14754d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie if (Opc == ARM::t2B) 14764d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie return ARM::t2Bcc; 14775ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng 14785ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng llvm_unreachable("Unknown unconditional branch opcode!"); 14795ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng} 14805ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng 14816495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 14823be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick/// Map pseudo instructions that imply an 'S' bit onto real opcodes. Whether the 14833be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick/// instruction is encoded with an 'S' bit is determined by the optional CPSR 14843be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick/// def operand. 14853be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick/// 14863be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick/// This will go away once we can teach tblgen how to set the optional CPSR def 14873be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick/// operand itself. 14883be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trickstruct AddSubFlagsOpcodePair { 14893be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick unsigned PseudoOpc; 14903be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick unsigned MachineOpc; 14913be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick}; 14923be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick 14933be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trickstatic AddSubFlagsOpcodePair AddSubFlagsOpcodeMap[] = { 14943be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick {ARM::ADDSri, ARM::ADDri}, 14953be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick {ARM::ADDSrr, ARM::ADDrr}, 14963be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick {ARM::ADDSrsi, ARM::ADDrsi}, 14973be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick {ARM::ADDSrsr, ARM::ADDrsr}, 14983be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick 14993be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick {ARM::SUBSri, ARM::SUBri}, 15003be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick {ARM::SUBSrr, ARM::SUBrr}, 15013be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick {ARM::SUBSrsi, ARM::SUBrsi}, 15023be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick {ARM::SUBSrsr, ARM::SUBrsr}, 15033be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick 15043be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick {ARM::RSBSri, ARM::RSBri}, 15053be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick {ARM::RSBSrsi, ARM::RSBrsi}, 15063be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick {ARM::RSBSrsr, ARM::RSBrsr}, 15073be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick 15083be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick {ARM::t2ADDSri, ARM::t2ADDri}, 15093be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick {ARM::t2ADDSrr, ARM::t2ADDrr}, 15103be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick {ARM::t2ADDSrs, ARM::t2ADDrs}, 15113be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick 15123be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick {ARM::t2SUBSri, ARM::t2SUBri}, 15133be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick {ARM::t2SUBSrr, ARM::t2SUBrr}, 15143be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick {ARM::t2SUBSrs, ARM::t2SUBrs}, 15153be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick 15163be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick {ARM::t2RSBSri, ARM::t2RSBri}, 15173be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick {ARM::t2RSBSrs, ARM::t2RSBrs}, 15183be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick}; 15193be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick 15203be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trickunsigned llvm::convertAddSubFlagsOpcode(unsigned OldOpc) { 15213be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick static const int NPairs = 15223be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick sizeof(AddSubFlagsOpcodeMap) / sizeof(AddSubFlagsOpcodePair); 15233be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick for (AddSubFlagsOpcodePair *OpcPair = &AddSubFlagsOpcodeMap[0], 15243be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick *End = &AddSubFlagsOpcodeMap[NPairs]; OpcPair != End; ++OpcPair) { 15253be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick if (OldOpc == OpcPair->PseudoOpc) { 15263be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick return OpcPair->MachineOpc; 15273be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick } 15283be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick } 15293be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick return 0; 15303be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick} 15313be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick 15326495f63945e8dbde81f03a1dc2ab421993b9a495Evan Chengvoid llvm::emitARMRegPlusImmediate(MachineBasicBlock &MBB, 15336495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MachineBasicBlock::iterator &MBBI, DebugLoc dl, 15346495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned DestReg, unsigned BaseReg, int NumBytes, 15356495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ARMCC::CondCodes Pred, unsigned PredReg, 153657caad7a33ff145b71545f10dcfbbf2fd0f595d3Anton Korobeynikov const ARMBaseInstrInfo &TII, unsigned MIFlags) { 15376495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng bool isSub = NumBytes < 0; 15386495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (isSub) NumBytes = -NumBytes; 15396495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 15406495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng while (NumBytes) { 15416495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned RotAmt = ARM_AM::getSOImmValRotate(NumBytes); 15426495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned ThisVal = NumBytes & ARM_AM::rotr32(0xFF, RotAmt); 15436495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng assert(ThisVal && "Didn't extract field correctly"); 15446495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 15456495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // We will handle these bits from offset, clear them. 15466495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng NumBytes &= ~ThisVal; 15476495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 15486495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng assert(ARM_AM::getSOImmVal(ThisVal) != -1 && "Bit extraction didn't work?"); 15496495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 15506495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Build the new ADD / SUB. 15516495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned Opc = isSub ? ARM::SUBri : ARM::ADDri; 15526495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg) 15536495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng .addReg(BaseReg, RegState::Kill).addImm(ThisVal) 155457caad7a33ff145b71545f10dcfbbf2fd0f595d3Anton Korobeynikov .addImm((unsigned)Pred).addReg(PredReg).addReg(0) 155557caad7a33ff145b71545f10dcfbbf2fd0f595d3Anton Korobeynikov .setMIFlags(MIFlags); 15566495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng BaseReg = DestReg; 15576495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 15586495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng} 15596495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 1560cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Chengbool llvm::rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx, 1561cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng unsigned FrameReg, int &Offset, 1562cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng const ARMBaseInstrInfo &TII) { 15636495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned Opcode = MI.getOpcode(); 1564e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng const MCInstrDesc &Desc = MI.getDesc(); 15656495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask); 15666495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng bool isSub = false; 1567764ab52dd80310a205c9888bf166d09dab858f90Jim Grosbach 15686495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Memory operands in inline assembly always use AddrMode2. 15696495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (Opcode == ARM::INLINEASM) 15706495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng AddrMode = ARMII::AddrMode2; 1571764ab52dd80310a205c9888bf166d09dab858f90Jim Grosbach 15726495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (Opcode == ARM::ADDri) { 15736495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng Offset += MI.getOperand(FrameRegIdx+1).getImm(); 15746495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (Offset == 0) { 15756495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Turn it into a move. 15766495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MI.setDesc(TII.get(ARM::MOVr)); 15776495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false); 15786495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MI.RemoveOperand(FrameRegIdx+1); 1579cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng Offset = 0; 1580cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng return true; 15816495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } else if (Offset < 0) { 15826495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng Offset = -Offset; 15836495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng isSub = true; 15846495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MI.setDesc(TII.get(ARM::SUBri)); 15856495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 15866495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 15876495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Common case: small offset, fits into instruction. 15886495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (ARM_AM::getSOImmVal(Offset) != -1) { 15896495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Replace the FrameIndex with sp / fp 15906495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false); 15916495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset); 1592cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng Offset = 0; 1593cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng return true; 15946495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 15956495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 15966495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Otherwise, pull as much of the immedidate into this ADDri/SUBri 15976495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // as possible. 15986495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned RotAmt = ARM_AM::getSOImmValRotate(Offset); 15996495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xFF, RotAmt); 16006495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 16016495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // We will handle these bits from offset, clear them. 16026495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng Offset &= ~ThisImmVal; 16036495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 16046495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Get the properly encoded SOImmVal field. 16056495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng assert(ARM_AM::getSOImmVal(ThisImmVal) != -1 && 16066495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng "Bit extraction didn't work?"); 16076495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MI.getOperand(FrameRegIdx+1).ChangeToImmediate(ThisImmVal); 16086495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } else { 16096495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned ImmIdx = 0; 16106495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng int InstrOffs = 0; 16116495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned NumBits = 0; 16126495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned Scale = 1; 16136495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng switch (AddrMode) { 16143e5561247202bae994dd259a2d8dc4eff8f799f3Jim Grosbach case ARMII::AddrMode_i12: { 16153e5561247202bae994dd259a2d8dc4eff8f799f3Jim Grosbach ImmIdx = FrameRegIdx + 1; 16163e5561247202bae994dd259a2d8dc4eff8f799f3Jim Grosbach InstrOffs = MI.getOperand(ImmIdx).getImm(); 16173e5561247202bae994dd259a2d8dc4eff8f799f3Jim Grosbach NumBits = 12; 16183e5561247202bae994dd259a2d8dc4eff8f799f3Jim Grosbach break; 16193e5561247202bae994dd259a2d8dc4eff8f799f3Jim Grosbach } 16206495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng case ARMII::AddrMode2: { 16216495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ImmIdx = FrameRegIdx+2; 16226495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng InstrOffs = ARM_AM::getAM2Offset(MI.getOperand(ImmIdx).getImm()); 16236495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (ARM_AM::getAM2Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub) 16246495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng InstrOffs *= -1; 16256495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng NumBits = 12; 16266495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng break; 16276495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 16286495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng case ARMII::AddrMode3: { 16296495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ImmIdx = FrameRegIdx+2; 16306495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng InstrOffs = ARM_AM::getAM3Offset(MI.getOperand(ImmIdx).getImm()); 16316495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (ARM_AM::getAM3Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub) 16326495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng InstrOffs *= -1; 16336495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng NumBits = 8; 16346495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng break; 16356495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 1636baf31088f1472f48ea5ae81f0b93636cc44ca444Anton Korobeynikov case ARMII::AddrMode4: 1637a44321776ecd96fa0344335d3027758be3386e45Jim Grosbach case ARMII::AddrMode6: 1638cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng // Can't fold any offset even if it's zero. 1639cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng return false; 16406495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng case ARMII::AddrMode5: { 16416495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ImmIdx = FrameRegIdx+1; 16426495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng InstrOffs = ARM_AM::getAM5Offset(MI.getOperand(ImmIdx).getImm()); 16436495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (ARM_AM::getAM5Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub) 16446495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng InstrOffs *= -1; 16456495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng NumBits = 8; 16466495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng Scale = 4; 16476495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng break; 16486495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 16496495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng default: 16506495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng llvm_unreachable("Unsupported addressing mode!"); 16516495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 16526495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 16536495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng Offset += InstrOffs * Scale; 16546495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!"); 16556495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (Offset < 0) { 16566495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng Offset = -Offset; 16576495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng isSub = true; 16586495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 16596495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 16606495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Attempt to fold address comp. if opcode has offset bits 16616495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (NumBits > 0) { 16626495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Common case: small offset, fits into instruction. 16636495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MachineOperand &ImmOp = MI.getOperand(ImmIdx); 16646495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng int ImmedOffset = Offset / Scale; 16656495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned Mask = (1 << NumBits) - 1; 16666495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if ((unsigned)Offset <= Mask * Scale) { 16676495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Replace the FrameIndex with sp 16686495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false); 166977aee8e22c36257716c2df2f275724765704f20cJim Grosbach // FIXME: When addrmode2 goes away, this will simplify (like the 167077aee8e22c36257716c2df2f275724765704f20cJim Grosbach // T2 version), as the LDR.i12 versions don't need the encoding 167177aee8e22c36257716c2df2f275724765704f20cJim Grosbach // tricks for the offset value. 167277aee8e22c36257716c2df2f275724765704f20cJim Grosbach if (isSub) { 167377aee8e22c36257716c2df2f275724765704f20cJim Grosbach if (AddrMode == ARMII::AddrMode_i12) 167477aee8e22c36257716c2df2f275724765704f20cJim Grosbach ImmedOffset = -ImmedOffset; 167577aee8e22c36257716c2df2f275724765704f20cJim Grosbach else 167677aee8e22c36257716c2df2f275724765704f20cJim Grosbach ImmedOffset |= 1 << NumBits; 167777aee8e22c36257716c2df2f275724765704f20cJim Grosbach } 16786495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ImmOp.ChangeToImmediate(ImmedOffset); 1679cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng Offset = 0; 1680cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng return true; 16816495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 1682764ab52dd80310a205c9888bf166d09dab858f90Jim Grosbach 16836495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Otherwise, it didn't fit. Pull in what we can to simplify the immed. 16846495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ImmedOffset = ImmedOffset & Mask; 1685063efbf569e46776093ddf50099c98fdbb362167Jim Grosbach if (isSub) { 1686063efbf569e46776093ddf50099c98fdbb362167Jim Grosbach if (AddrMode == ARMII::AddrMode_i12) 1687063efbf569e46776093ddf50099c98fdbb362167Jim Grosbach ImmedOffset = -ImmedOffset; 1688063efbf569e46776093ddf50099c98fdbb362167Jim Grosbach else 1689063efbf569e46776093ddf50099c98fdbb362167Jim Grosbach ImmedOffset |= 1 << NumBits; 1690063efbf569e46776093ddf50099c98fdbb362167Jim Grosbach } 16916495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ImmOp.ChangeToImmediate(ImmedOffset); 16926495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng Offset &= ~(Mask*Scale); 16936495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 16946495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 16956495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 1696cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng Offset = (isSub) ? -Offset : Offset; 1697cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng return Offset == 0; 16986495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng} 1699e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling 1700e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendlingbool ARMBaseInstrInfo:: 1701a99c3e9acd95f5fbfb611e3f807240cd74001142Eric ChristopherAnalyzeCompare(const MachineInstr *MI, unsigned &SrcReg, int &CmpMask, 1702a99c3e9acd95f5fbfb611e3f807240cd74001142Eric Christopher int &CmpValue) const { 1703e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling switch (MI->getOpcode()) { 1704e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling default: break; 170538ae997e63e3e1bb2c8679e01ea74cf8fd0be893Bill Wendling case ARM::CMPri: 1706e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling case ARM::t2CMPri: 1707e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling SrcReg = MI->getOperand(0).getReg(); 170804ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif CmpMask = ~0; 1709e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling CmpValue = MI->getOperand(1).getImm(); 1710e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling return true; 171104ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif case ARM::TSTri: 171204ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif case ARM::t2TSTri: 171304ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif SrcReg = MI->getOperand(0).getReg(); 171404ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif CmpMask = MI->getOperand(1).getImm(); 171504ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif CmpValue = 0; 171604ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif return true; 171704ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif } 171804ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif 171904ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif return false; 172004ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif} 172104ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif 172205642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif/// isSuitableForMask - Identify a suitable 'and' instruction that 172305642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif/// operates on the given source register and applies the same mask 172405642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif/// as a 'tst' instruction. Provide a limited look-through for copies. 172505642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif/// When successful, MI will hold the found instruction. 172605642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greifstatic bool isSuitableForMask(MachineInstr *&MI, unsigned SrcReg, 17278ff9bb189ce188452e6cae6ed65cb2745814126cGabor Greif int CmpMask, bool CommonUse) { 172805642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif switch (MI->getOpcode()) { 172904ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif case ARM::ANDri: 173004ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif case ARM::t2ANDri: 173105642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif if (CmpMask != MI->getOperand(2).getImm()) 17328ff9bb189ce188452e6cae6ed65cb2745814126cGabor Greif return false; 173305642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif if (SrcReg == MI->getOperand(CommonUse ? 1 : 0).getReg()) 173404ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif return true; 173504ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif break; 173605642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif case ARM::COPY: { 173705642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif // Walk down one instruction which is potentially an 'and'. 173805642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif const MachineInstr &Copy = *MI; 1739f000a7a212590bfd45e23c05bff5e1b683d25dd6Michael J. Spencer MachineBasicBlock::iterator AND( 1740f000a7a212590bfd45e23c05bff5e1b683d25dd6Michael J. Spencer llvm::next(MachineBasicBlock::iterator(MI))); 174105642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif if (AND == MI->getParent()->end()) return false; 174205642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif MI = AND; 174305642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif return isSuitableForMask(MI, Copy.getOperand(0).getReg(), 174405642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif CmpMask, true); 174505642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif } 1746e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling } 1747e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling 1748e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling return false; 1749e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling} 1750e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling 1751a65568676d0d9d53dd4aae8f1c58271bb4cfff10Bill Wendling/// OptimizeCompareInstr - Convert the instruction supplying the argument to the 1752eb96a2f6c03c0ec97c56a3493ac38024afacc774Evan Cheng/// comparison into one that sets the zero bit in the flags register. 1753e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendlingbool ARMBaseInstrInfo:: 175404ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor GreifOptimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, int CmpMask, 1755eb96a2f6c03c0ec97c56a3493ac38024afacc774Evan Cheng int CmpValue, const MachineRegisterInfo *MRI) const { 17563665661a5708c8adc2727be38b56d1d87ddeb661Bill Wendling if (CmpValue != 0) 175792ad57f066e9f256e4e3d72febf152e68caa80c7Bill Wendling return false; 175892ad57f066e9f256e4e3d72febf152e68caa80c7Bill Wendling 1759b41ee96d76ccf1eec2fd898def4cfd7c16868708Bill Wendling MachineRegisterInfo::def_iterator DI = MRI->def_begin(SrcReg); 1760b41ee96d76ccf1eec2fd898def4cfd7c16868708Bill Wendling if (llvm::next(DI) != MRI->def_end()) 176192ad57f066e9f256e4e3d72febf152e68caa80c7Bill Wendling // Only support one definition. 176292ad57f066e9f256e4e3d72febf152e68caa80c7Bill Wendling return false; 176392ad57f066e9f256e4e3d72febf152e68caa80c7Bill Wendling 176492ad57f066e9f256e4e3d72febf152e68caa80c7Bill Wendling MachineInstr *MI = &*DI; 176592ad57f066e9f256e4e3d72febf152e68caa80c7Bill Wendling 176604ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif // Masked compares sometimes use the same register as the corresponding 'and'. 176704ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif if (CmpMask != ~0) { 176805642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif if (!isSuitableForMask(MI, SrcReg, CmpMask, false)) { 176904ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif MI = 0; 1770b41ee96d76ccf1eec2fd898def4cfd7c16868708Bill Wendling for (MachineRegisterInfo::use_iterator UI = MRI->use_begin(SrcReg), 1771b41ee96d76ccf1eec2fd898def4cfd7c16868708Bill Wendling UE = MRI->use_end(); UI != UE; ++UI) { 177204ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif if (UI->getParent() != CmpInstr->getParent()) continue; 177305642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif MachineInstr *PotentialAND = &*UI; 17748ff9bb189ce188452e6cae6ed65cb2745814126cGabor Greif if (!isSuitableForMask(PotentialAND, SrcReg, CmpMask, true)) 177504ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif continue; 177605642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif MI = PotentialAND; 177704ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif break; 177804ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif } 177904ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif if (!MI) return false; 178004ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif } 178104ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif } 178204ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif 1783e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling // Conservatively refuse to convert an instruction which isn't in the same BB 1784e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling // as the comparison. 1785e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling if (MI->getParent() != CmpInstr->getParent()) 1786e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling return false; 1787e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling 1788e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling // Check that CPSR isn't set between the comparison instruction and the one we 1789e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling // want to change. 17907c2a4a30e0e16762c75adacebd05ec9fcbccf16bEvan Cheng MachineBasicBlock::iterator I = CmpInstr,E = MI, B = MI->getParent()->begin(); 17910aa38b9381a5be42abd4f5ca5baa8c2930d148d3Bill Wendling 17920aa38b9381a5be42abd4f5ca5baa8c2930d148d3Bill Wendling // Early exit if CmpInstr is at the beginning of the BB. 17930aa38b9381a5be42abd4f5ca5baa8c2930d148d3Bill Wendling if (I == B) return false; 17940aa38b9381a5be42abd4f5ca5baa8c2930d148d3Bill Wendling 1795e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling --I; 1796e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling for (; I != E; --I) { 1797e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling const MachineInstr &Instr = *I; 1798e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling 1799e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling for (unsigned IO = 0, EO = Instr.getNumOperands(); IO != EO; ++IO) { 1800e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling const MachineOperand &MO = Instr.getOperand(IO); 18012420b558de5d291d8503c1339004e5b5bf99a48aJakob Stoklund Olesen if (MO.isRegMask() && MO.clobbersPhysReg(ARM::CPSR)) 18022420b558de5d291d8503c1339004e5b5bf99a48aJakob Stoklund Olesen return false; 180340a5eb18b031fa1a5e9697e21e251e613d441cc5Bill Wendling if (!MO.isReg()) continue; 1804e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling 180540a5eb18b031fa1a5e9697e21e251e613d441cc5Bill Wendling // This instruction modifies or uses CPSR after the one we want to 180640a5eb18b031fa1a5e9697e21e251e613d441cc5Bill Wendling // change. We can't do this transformation. 1807e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling if (MO.getReg() == ARM::CPSR) 1808e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling return false; 1809e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling } 1810691e64a54ce899409abe7c131d15ed75e3c1fef5Evan Cheng 1811691e64a54ce899409abe7c131d15ed75e3c1fef5Evan Cheng if (I == B) 1812691e64a54ce899409abe7c131d15ed75e3c1fef5Evan Cheng // The 'and' is below the comparison instruction. 1813691e64a54ce899409abe7c131d15ed75e3c1fef5Evan Cheng return false; 1814e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling } 1815e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling 1816e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling // Set the "zero" bit in CPSR. 1817e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling switch (MI->getOpcode()) { 1818e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling default: break; 1819ca3f6a3925e9a6e91022aa211bdc1b6e3f2ff41fCameron Zwarich case ARM::RSBrr: 1820df298c9ea64eb335f63fc075d8ef6306682ffe75Owen Anderson case ARM::RSBri: 1821ca3f6a3925e9a6e91022aa211bdc1b6e3f2ff41fCameron Zwarich case ARM::RSCrr: 1822df298c9ea64eb335f63fc075d8ef6306682ffe75Owen Anderson case ARM::RSCri: 1823ca3f6a3925e9a6e91022aa211bdc1b6e3f2ff41fCameron Zwarich case ARM::ADDrr: 182438ae997e63e3e1bb2c8679e01ea74cf8fd0be893Bill Wendling case ARM::ADDri: 1825ca3f6a3925e9a6e91022aa211bdc1b6e3f2ff41fCameron Zwarich case ARM::ADCrr: 1826df298c9ea64eb335f63fc075d8ef6306682ffe75Owen Anderson case ARM::ADCri: 1827ca3f6a3925e9a6e91022aa211bdc1b6e3f2ff41fCameron Zwarich case ARM::SUBrr: 182838ae997e63e3e1bb2c8679e01ea74cf8fd0be893Bill Wendling case ARM::SUBri: 1829ca3f6a3925e9a6e91022aa211bdc1b6e3f2ff41fCameron Zwarich case ARM::SBCrr: 1830df298c9ea64eb335f63fc075d8ef6306682ffe75Owen Anderson case ARM::SBCri: 1831df298c9ea64eb335f63fc075d8ef6306682ffe75Owen Anderson case ARM::t2RSBri: 1832ca3f6a3925e9a6e91022aa211bdc1b6e3f2ff41fCameron Zwarich case ARM::t2ADDrr: 183338ae997e63e3e1bb2c8679e01ea74cf8fd0be893Bill Wendling case ARM::t2ADDri: 1834ca3f6a3925e9a6e91022aa211bdc1b6e3f2ff41fCameron Zwarich case ARM::t2ADCrr: 1835df298c9ea64eb335f63fc075d8ef6306682ffe75Owen Anderson case ARM::t2ADCri: 1836ca3f6a3925e9a6e91022aa211bdc1b6e3f2ff41fCameron Zwarich case ARM::t2SUBrr: 1837df298c9ea64eb335f63fc075d8ef6306682ffe75Owen Anderson case ARM::t2SUBri: 1838ca3f6a3925e9a6e91022aa211bdc1b6e3f2ff41fCameron Zwarich case ARM::t2SBCrr: 1839b485de5d8c3fe0c62c0b07f63f64bd10f6803c17Cameron Zwarich case ARM::t2SBCri: 1840b485de5d8c3fe0c62c0b07f63f64bd10f6803c17Cameron Zwarich case ARM::ANDrr: 1841b485de5d8c3fe0c62c0b07f63f64bd10f6803c17Cameron Zwarich case ARM::ANDri: 1842b485de5d8c3fe0c62c0b07f63f64bd10f6803c17Cameron Zwarich case ARM::t2ANDrr: 18430cb11ac32fc09c5db42fb801db242ac9fb51f6b1Cameron Zwarich case ARM::t2ANDri: 18440cb11ac32fc09c5db42fb801db242ac9fb51f6b1Cameron Zwarich case ARM::ORRrr: 18450cb11ac32fc09c5db42fb801db242ac9fb51f6b1Cameron Zwarich case ARM::ORRri: 18460cb11ac32fc09c5db42fb801db242ac9fb51f6b1Cameron Zwarich case ARM::t2ORRrr: 18470cb11ac32fc09c5db42fb801db242ac9fb51f6b1Cameron Zwarich case ARM::t2ORRri: 18480cb11ac32fc09c5db42fb801db242ac9fb51f6b1Cameron Zwarich case ARM::EORrr: 18490cb11ac32fc09c5db42fb801db242ac9fb51f6b1Cameron Zwarich case ARM::EORri: 18500cb11ac32fc09c5db42fb801db242ac9fb51f6b1Cameron Zwarich case ARM::t2EORrr: 18510cb11ac32fc09c5db42fb801db242ac9fb51f6b1Cameron Zwarich case ARM::t2EORri: { 18522c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng // Scan forward for the use of CPSR, if it's a conditional code requires 18532c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng // checking of V bit, then this is not safe to do. If we can't find the 18542c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng // CPSR use (i.e. used in another block), then it's not safe to perform 18552c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng // the optimization. 18562c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng bool isSafe = false; 18572c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng I = CmpInstr; 18582c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng E = MI->getParent()->end(); 18592c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng while (!isSafe && ++I != E) { 18602c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng const MachineInstr &Instr = *I; 18612c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng for (unsigned IO = 0, EO = Instr.getNumOperands(); 18622c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng !isSafe && IO != EO; ++IO) { 18632c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng const MachineOperand &MO = Instr.getOperand(IO); 18642420b558de5d291d8503c1339004e5b5bf99a48aJakob Stoklund Olesen if (MO.isRegMask() && MO.clobbersPhysReg(ARM::CPSR)) { 18652420b558de5d291d8503c1339004e5b5bf99a48aJakob Stoklund Olesen isSafe = true; 18662420b558de5d291d8503c1339004e5b5bf99a48aJakob Stoklund Olesen break; 18672420b558de5d291d8503c1339004e5b5bf99a48aJakob Stoklund Olesen } 18682c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng if (!MO.isReg() || MO.getReg() != ARM::CPSR) 18692c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng continue; 18702c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng if (MO.isDef()) { 18712c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng isSafe = true; 18722c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng break; 18732c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng } 18742c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng // Condition code is after the operand before CPSR. 18752c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng ARMCC::CondCodes CC = (ARMCC::CondCodes)Instr.getOperand(IO-1).getImm(); 18762c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng switch (CC) { 18772c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng default: 18782c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng isSafe = true; 18792c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng break; 18802c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng case ARMCC::VS: 18812c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng case ARMCC::VC: 18822c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng case ARMCC::GE: 18832c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng case ARMCC::LT: 18842c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng case ARMCC::GT: 18852c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng case ARMCC::LE: 18862c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng return false; 18872c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng } 18882c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng } 18892c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng } 18902c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng 18912c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng if (!isSafe) 18922c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng return false; 18932c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng 18943642e64c114e636548888c72c21ae023ee0121a7Evan Cheng // Toggle the optional operand to CPSR. 18953642e64c114e636548888c72c21ae023ee0121a7Evan Cheng MI->getOperand(5).setReg(ARM::CPSR); 18963642e64c114e636548888c72c21ae023ee0121a7Evan Cheng MI->getOperand(5).setIsDef(true); 1897e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling CmpInstr->eraseFromParent(); 1898e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling return true; 1899e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling } 1900b485de5d8c3fe0c62c0b07f63f64bd10f6803c17Cameron Zwarich } 1901e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling 1902e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling return false; 1903e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling} 19045f54ce347368105260be2cec497b6a4199dc5789Evan Cheng 1905c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Chengbool ARMBaseInstrInfo::FoldImmediate(MachineInstr *UseMI, 1906c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng MachineInstr *DefMI, unsigned Reg, 1907c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng MachineRegisterInfo *MRI) const { 1908c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng // Fold large immediates into add, sub, or, xor. 1909c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng unsigned DefOpc = DefMI->getOpcode(); 1910c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng if (DefOpc != ARM::t2MOVi32imm && DefOpc != ARM::MOVi32imm) 1911c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng return false; 1912c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng if (!DefMI->getOperand(1).isImm()) 1913c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng // Could be t2MOVi32imm <ga:xx> 1914c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng return false; 1915c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng 1916c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng if (!MRI->hasOneNonDBGUse(Reg)) 1917c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng return false; 1918c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng 1919e279f5953e9c3d934248cd4d2f24b6179ad9d2e6Evan Cheng const MCInstrDesc &DefMCID = DefMI->getDesc(); 1920e279f5953e9c3d934248cd4d2f24b6179ad9d2e6Evan Cheng if (DefMCID.hasOptionalDef()) { 1921e279f5953e9c3d934248cd4d2f24b6179ad9d2e6Evan Cheng unsigned NumOps = DefMCID.getNumOperands(); 1922e279f5953e9c3d934248cd4d2f24b6179ad9d2e6Evan Cheng const MachineOperand &MO = DefMI->getOperand(NumOps-1); 1923e279f5953e9c3d934248cd4d2f24b6179ad9d2e6Evan Cheng if (MO.getReg() == ARM::CPSR && !MO.isDead()) 1924e279f5953e9c3d934248cd4d2f24b6179ad9d2e6Evan Cheng // If DefMI defines CPSR and it is not dead, it's obviously not safe 1925e279f5953e9c3d934248cd4d2f24b6179ad9d2e6Evan Cheng // to delete DefMI. 1926e279f5953e9c3d934248cd4d2f24b6179ad9d2e6Evan Cheng return false; 1927e279f5953e9c3d934248cd4d2f24b6179ad9d2e6Evan Cheng } 1928e279f5953e9c3d934248cd4d2f24b6179ad9d2e6Evan Cheng 1929e279f5953e9c3d934248cd4d2f24b6179ad9d2e6Evan Cheng const MCInstrDesc &UseMCID = UseMI->getDesc(); 1930e279f5953e9c3d934248cd4d2f24b6179ad9d2e6Evan Cheng if (UseMCID.hasOptionalDef()) { 1931e279f5953e9c3d934248cd4d2f24b6179ad9d2e6Evan Cheng unsigned NumOps = UseMCID.getNumOperands(); 1932e279f5953e9c3d934248cd4d2f24b6179ad9d2e6Evan Cheng if (UseMI->getOperand(NumOps-1).getReg() == ARM::CPSR) 1933e279f5953e9c3d934248cd4d2f24b6179ad9d2e6Evan Cheng // If the instruction sets the flag, do not attempt this optimization 1934e279f5953e9c3d934248cd4d2f24b6179ad9d2e6Evan Cheng // since it may change the semantics of the code. 1935e279f5953e9c3d934248cd4d2f24b6179ad9d2e6Evan Cheng return false; 1936e279f5953e9c3d934248cd4d2f24b6179ad9d2e6Evan Cheng } 1937e279f5953e9c3d934248cd4d2f24b6179ad9d2e6Evan Cheng 1938c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng unsigned UseOpc = UseMI->getOpcode(); 19395c71c7a13715ed6f5bfdd5497172ddec316b68b0Evan Cheng unsigned NewUseOpc = 0; 1940c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng uint32_t ImmVal = (uint32_t)DefMI->getOperand(1).getImm(); 19415c71c7a13715ed6f5bfdd5497172ddec316b68b0Evan Cheng uint32_t SOImmValV1 = 0, SOImmValV2 = 0; 1942c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng bool Commute = false; 1943c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng switch (UseOpc) { 1944c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng default: return false; 1945c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::SUBrr: 1946c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::ADDrr: 1947c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::ORRrr: 1948c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::EORrr: 1949c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::t2SUBrr: 1950c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::t2ADDrr: 1951c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::t2ORRrr: 1952c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::t2EORrr: { 1953c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng Commute = UseMI->getOperand(2).getReg() != Reg; 1954c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng switch (UseOpc) { 1955c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng default: break; 1956c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::SUBrr: { 1957c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng if (Commute) 1958c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng return false; 1959c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng ImmVal = -ImmVal; 1960c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng NewUseOpc = ARM::SUBri; 1961c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng // Fallthrough 1962c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng } 1963c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::ADDrr: 1964c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::ORRrr: 1965c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::EORrr: { 1966c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng if (!ARM_AM::isSOImmTwoPartVal(ImmVal)) 1967c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng return false; 1968c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng SOImmValV1 = (uint32_t)ARM_AM::getSOImmTwoPartFirst(ImmVal); 1969c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng SOImmValV2 = (uint32_t)ARM_AM::getSOImmTwoPartSecond(ImmVal); 1970c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng switch (UseOpc) { 1971c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng default: break; 1972c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::ADDrr: NewUseOpc = ARM::ADDri; break; 1973c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::ORRrr: NewUseOpc = ARM::ORRri; break; 1974c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::EORrr: NewUseOpc = ARM::EORri; break; 1975c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng } 1976c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng break; 1977c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng } 1978c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::t2SUBrr: { 1979c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng if (Commute) 1980c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng return false; 1981c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng ImmVal = -ImmVal; 1982c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng NewUseOpc = ARM::t2SUBri; 1983c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng // Fallthrough 1984c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng } 1985c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::t2ADDrr: 1986c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::t2ORRrr: 1987c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::t2EORrr: { 1988c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng if (!ARM_AM::isT2SOImmTwoPartVal(ImmVal)) 1989c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng return false; 1990c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng SOImmValV1 = (uint32_t)ARM_AM::getT2SOImmTwoPartFirst(ImmVal); 1991c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng SOImmValV2 = (uint32_t)ARM_AM::getT2SOImmTwoPartSecond(ImmVal); 1992c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng switch (UseOpc) { 1993c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng default: break; 1994c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::t2ADDrr: NewUseOpc = ARM::t2ADDri; break; 1995c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::t2ORRrr: NewUseOpc = ARM::t2ORRri; break; 1996c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::t2EORrr: NewUseOpc = ARM::t2EORri; break; 1997c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng } 1998c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng break; 1999c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng } 2000c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng } 2001c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng } 2002c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng } 2003c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng 2004c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng unsigned OpIdx = Commute ? 2 : 1; 2005c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng unsigned Reg1 = UseMI->getOperand(OpIdx).getReg(); 2006c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng bool isKill = UseMI->getOperand(OpIdx).isKill(); 2007c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng unsigned NewReg = MRI->createVirtualRegister(MRI->getRegClass(Reg)); 2008c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng AddDefaultCC(AddDefaultPred(BuildMI(*UseMI->getParent(), 2009ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng UseMI, UseMI->getDebugLoc(), 2010c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng get(NewUseOpc), NewReg) 2011c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng .addReg(Reg1, getKillRegState(isKill)) 2012c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng .addImm(SOImmValV1))); 2013c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng UseMI->setDesc(get(NewUseOpc)); 2014c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng UseMI->getOperand(1).setReg(NewReg); 2015c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng UseMI->getOperand(1).setIsKill(); 2016c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng UseMI->getOperand(2).ChangeToImmediate(SOImmValV2); 2017c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng DefMI->eraseFromParent(); 2018c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng return true; 2019c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng} 2020c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng 20215f54ce347368105260be2cec497b6a4199dc5789Evan Chengunsigned 20228239daf7c83a65a189c352cce3191cdc3bbfe151Evan ChengARMBaseInstrInfo::getNumMicroOps(const InstrItineraryData *ItinData, 20238239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng const MachineInstr *MI) const { 20243ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng if (!ItinData || ItinData->isEmpty()) 20255f54ce347368105260be2cec497b6a4199dc5789Evan Cheng return 1; 20265f54ce347368105260be2cec497b6a4199dc5789Evan Cheng 2027e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng const MCInstrDesc &Desc = MI->getDesc(); 20285f54ce347368105260be2cec497b6a4199dc5789Evan Cheng unsigned Class = Desc.getSchedClass(); 2029064312de8641043b084603aa9a6b409bc794eed2Bob Wilson unsigned UOps = ItinData->Itineraries[Class].NumMicroOps; 20305f54ce347368105260be2cec497b6a4199dc5789Evan Cheng if (UOps) 20315f54ce347368105260be2cec497b6a4199dc5789Evan Cheng return UOps; 20325f54ce347368105260be2cec497b6a4199dc5789Evan Cheng 20335f54ce347368105260be2cec497b6a4199dc5789Evan Cheng unsigned Opc = MI->getOpcode(); 20345f54ce347368105260be2cec497b6a4199dc5789Evan Cheng switch (Opc) { 20355f54ce347368105260be2cec497b6a4199dc5789Evan Cheng default: 20365f54ce347368105260be2cec497b6a4199dc5789Evan Cheng llvm_unreachable("Unexpected multi-uops instruction!"); 203773fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMQIA: 203873fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMQIA: 20395f54ce347368105260be2cec497b6a4199dc5789Evan Cheng return 2; 20405f54ce347368105260be2cec497b6a4199dc5789Evan Cheng 20415f54ce347368105260be2cec497b6a4199dc5789Evan Cheng // The number of uOps for load / store multiple are determined by the number 20425f54ce347368105260be2cec497b6a4199dc5789Evan Cheng // registers. 20436e8f4c404825b79f9b9176483653f1aa927dfbdeAndrew Trick // 20443ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng // On Cortex-A8, each pair of register loads / stores can be scheduled on the 20453ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng // same cycle. The scheduling for the first load / store must be done 20463ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng // separately by assuming the the address is not 64-bit aligned. 204773fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling // 20483ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng // On Cortex-A9, the formula is simply (#reg / 2) + (#reg % 2). If the address 204973fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling // is not 64-bit aligned, then AGU would take an extra cycle. For VFP / NEON 205073fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling // load / store multiple, the formula is (#reg / 2) + (#reg % 2) + 1. 205173fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMDIA: 205273fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMDIA_UPD: 205373fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMDDB_UPD: 205473fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMSIA: 205573fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMSIA_UPD: 205673fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMSDB_UPD: 205773fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMDIA: 205873fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMDIA_UPD: 205973fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMDDB_UPD: 206073fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMSIA: 206173fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMSIA_UPD: 206273fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMSDB_UPD: { 20635f54ce347368105260be2cec497b6a4199dc5789Evan Cheng unsigned NumRegs = MI->getNumOperands() - Desc.getNumOperands(); 20645f54ce347368105260be2cec497b6a4199dc5789Evan Cheng return (NumRegs / 2) + (NumRegs % 2) + 1; 20655f54ce347368105260be2cec497b6a4199dc5789Evan Cheng } 206673fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling 206773fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMIA_RET: 206873fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMIA: 206973fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMDA: 207073fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMDB: 207173fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMIB: 207273fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMIA_UPD: 207373fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMDA_UPD: 207473fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMDB_UPD: 207573fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMIB_UPD: 207673fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::STMIA: 207773fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::STMDA: 207873fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::STMDB: 207973fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::STMIB: 208073fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::STMIA_UPD: 208173fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::STMDA_UPD: 208273fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::STMDB_UPD: 208373fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::STMIB_UPD: 208473fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::tLDMIA: 208573fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::tLDMIA_UPD: 208673fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::tSTMIA_UPD: 20875f54ce347368105260be2cec497b6a4199dc5789Evan Cheng case ARM::tPOP_RET: 20885f54ce347368105260be2cec497b6a4199dc5789Evan Cheng case ARM::tPOP: 20895f54ce347368105260be2cec497b6a4199dc5789Evan Cheng case ARM::tPUSH: 209073fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2LDMIA_RET: 209173fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2LDMIA: 209273fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2LDMDB: 209373fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2LDMIA_UPD: 209473fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2LDMDB_UPD: 209573fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2STMIA: 209673fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2STMDB: 209773fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2STMIA_UPD: 209873fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2STMDB_UPD: { 20993ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng unsigned NumRegs = MI->getNumOperands() - Desc.getNumOperands() + 1; 21003ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng if (Subtarget.isCortexA8()) { 21018239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng if (NumRegs < 4) 21028239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng return 2; 21038239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng // 4 registers would be issued: 2, 2. 21048239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng // 5 registers would be issued: 2, 2, 1. 21058239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng UOps = (NumRegs / 2); 21068239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng if (NumRegs % 2) 21078239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng ++UOps; 21088239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng return UOps; 21093ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng } else if (Subtarget.isCortexA9()) { 21103ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng UOps = (NumRegs / 2); 21113ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng // If there are odd number of registers or if it's not 64-bit aligned, 21123ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng // then it takes an extra AGU (Address Generation Unit) cycle. 21133ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng if ((NumRegs % 2) || 21143ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng !MI->hasOneMemOperand() || 21153ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng (*MI->memoperands_begin())->getAlignment() < 8) 21163ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng ++UOps; 21173ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng return UOps; 21183ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng } else { 21193ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng // Assume the worst. 21203ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng return NumRegs; 21212bbb76909126db5bed6bde84b16d94ab5de4d372Michael J. Spencer } 21225f54ce347368105260be2cec497b6a4199dc5789Evan Cheng } 21235f54ce347368105260be2cec497b6a4199dc5789Evan Cheng } 21245f54ce347368105260be2cec497b6a4199dc5789Evan Cheng} 2125a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng 2126a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Chengint 2127344d9db97062736cd66da6c07baa9108b6cfa419Evan ChengARMBaseInstrInfo::getVLDMDefCycle(const InstrItineraryData *ItinData, 2128e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng const MCInstrDesc &DefMCID, 2129344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng unsigned DefClass, 2130344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng unsigned DefIdx, unsigned DefAlign) const { 2131e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng int RegNo = (int)(DefIdx+1) - DefMCID.getNumOperands() + 1; 2132344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng if (RegNo <= 0) 2133344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // Def is the address writeback. 2134344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng return ItinData->getOperandCycle(DefClass, DefIdx); 2135344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng 2136344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng int DefCycle; 2137344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng if (Subtarget.isCortexA8()) { 2138344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // (regno / 2) + (regno % 2) + 1 2139344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng DefCycle = RegNo / 2 + 1; 2140344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng if (RegNo % 2) 2141344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng ++DefCycle; 2142344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng } else if (Subtarget.isCortexA9()) { 2143344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng DefCycle = RegNo; 2144344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng bool isSLoad = false; 214573fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling 2146e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng switch (DefMCID.getOpcode()) { 2147344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng default: break; 214873fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMSIA: 214973fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMSIA_UPD: 215073fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMSDB_UPD: 2151344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng isSLoad = true; 2152344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng break; 2153344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng } 215473fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling 2155344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // If there are odd number of 'S' registers or if it's not 64-bit aligned, 2156344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // then it takes an extra cycle. 2157344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng if ((isSLoad && (RegNo % 2)) || DefAlign < 8) 2158344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng ++DefCycle; 2159344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng } else { 2160344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // Assume the worst. 2161344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng DefCycle = RegNo + 2; 2162344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng } 2163344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng 2164344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng return DefCycle; 2165344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng} 2166344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng 2167344d9db97062736cd66da6c07baa9108b6cfa419Evan Chengint 2168344d9db97062736cd66da6c07baa9108b6cfa419Evan ChengARMBaseInstrInfo::getLDMDefCycle(const InstrItineraryData *ItinData, 2169e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng const MCInstrDesc &DefMCID, 2170344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng unsigned DefClass, 2171344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng unsigned DefIdx, unsigned DefAlign) const { 2172e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng int RegNo = (int)(DefIdx+1) - DefMCID.getNumOperands() + 1; 2173344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng if (RegNo <= 0) 2174344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // Def is the address writeback. 2175344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng return ItinData->getOperandCycle(DefClass, DefIdx); 2176344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng 2177344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng int DefCycle; 2178344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng if (Subtarget.isCortexA8()) { 2179344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // 4 registers would be issued: 1, 2, 1. 2180344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // 5 registers would be issued: 1, 2, 2. 2181344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng DefCycle = RegNo / 2; 2182344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng if (DefCycle < 1) 2183344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng DefCycle = 1; 2184344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // Result latency is issue cycle + 2: E2. 2185344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng DefCycle += 2; 2186344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng } else if (Subtarget.isCortexA9()) { 2187344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng DefCycle = (RegNo / 2); 2188344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // If there are odd number of registers or if it's not 64-bit aligned, 2189344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // then it takes an extra AGU (Address Generation Unit) cycle. 2190344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng if ((RegNo % 2) || DefAlign < 8) 2191344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng ++DefCycle; 2192344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // Result latency is AGU cycles + 2. 2193344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng DefCycle += 2; 2194344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng } else { 2195344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // Assume the worst. 2196344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng DefCycle = RegNo + 2; 2197344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng } 2198344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng 2199344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng return DefCycle; 2200344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng} 2201344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng 2202344d9db97062736cd66da6c07baa9108b6cfa419Evan Chengint 2203344d9db97062736cd66da6c07baa9108b6cfa419Evan ChengARMBaseInstrInfo::getVSTMUseCycle(const InstrItineraryData *ItinData, 2204e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng const MCInstrDesc &UseMCID, 2205344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng unsigned UseClass, 2206344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng unsigned UseIdx, unsigned UseAlign) const { 2207e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng int RegNo = (int)(UseIdx+1) - UseMCID.getNumOperands() + 1; 2208344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng if (RegNo <= 0) 2209344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng return ItinData->getOperandCycle(UseClass, UseIdx); 2210344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng 2211344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng int UseCycle; 2212344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng if (Subtarget.isCortexA8()) { 2213344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // (regno / 2) + (regno % 2) + 1 2214344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng UseCycle = RegNo / 2 + 1; 2215344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng if (RegNo % 2) 2216344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng ++UseCycle; 2217344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng } else if (Subtarget.isCortexA9()) { 2218344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng UseCycle = RegNo; 2219344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng bool isSStore = false; 222073fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling 2221e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng switch (UseMCID.getOpcode()) { 2222344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng default: break; 222373fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMSIA: 222473fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMSIA_UPD: 222573fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMSDB_UPD: 2226344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng isSStore = true; 2227344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng break; 2228344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng } 222973fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling 2230344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // If there are odd number of 'S' registers or if it's not 64-bit aligned, 2231344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // then it takes an extra cycle. 2232344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng if ((isSStore && (RegNo % 2)) || UseAlign < 8) 2233344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng ++UseCycle; 2234344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng } else { 2235344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // Assume the worst. 2236344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng UseCycle = RegNo + 2; 2237344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng } 2238344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng 2239344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng return UseCycle; 2240344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng} 2241344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng 2242344d9db97062736cd66da6c07baa9108b6cfa419Evan Chengint 2243344d9db97062736cd66da6c07baa9108b6cfa419Evan ChengARMBaseInstrInfo::getSTMUseCycle(const InstrItineraryData *ItinData, 2244e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng const MCInstrDesc &UseMCID, 2245344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng unsigned UseClass, 2246344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng unsigned UseIdx, unsigned UseAlign) const { 2247e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng int RegNo = (int)(UseIdx+1) - UseMCID.getNumOperands() + 1; 2248344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng if (RegNo <= 0) 2249344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng return ItinData->getOperandCycle(UseClass, UseIdx); 2250344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng 2251344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng int UseCycle; 2252344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng if (Subtarget.isCortexA8()) { 2253344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng UseCycle = RegNo / 2; 2254344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng if (UseCycle < 2) 2255344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng UseCycle = 2; 2256344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // Read in E3. 2257344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng UseCycle += 2; 2258344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng } else if (Subtarget.isCortexA9()) { 2259344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng UseCycle = (RegNo / 2); 2260344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // If there are odd number of registers or if it's not 64-bit aligned, 2261344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // then it takes an extra AGU (Address Generation Unit) cycle. 2262344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng if ((RegNo % 2) || UseAlign < 8) 2263344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng ++UseCycle; 2264344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng } else { 2265344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // Assume the worst. 2266344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng UseCycle = 1; 2267344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng } 2268344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng return UseCycle; 2269344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng} 2270344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng 2271344d9db97062736cd66da6c07baa9108b6cfa419Evan Chengint 2272a0792de66c8364d47b0a688c7f408efb7b10f31bEvan ChengARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData, 2273e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng const MCInstrDesc &DefMCID, 2274a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng unsigned DefIdx, unsigned DefAlign, 2275e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng const MCInstrDesc &UseMCID, 2276a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng unsigned UseIdx, unsigned UseAlign) const { 2277e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng unsigned DefClass = DefMCID.getSchedClass(); 2278e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng unsigned UseClass = UseMCID.getSchedClass(); 2279a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng 2280e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng if (DefIdx < DefMCID.getNumDefs() && UseIdx < UseMCID.getNumOperands()) 2281a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx); 2282a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng 2283a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng // This may be a def / use of a variable_ops instruction, the operand 2284a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng // latency might be determinable dynamically. Let the target try to 2285a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng // figure it out. 22869e08ee5d16b596078e20787f0b5f36121f099333Evan Cheng int DefCycle = -1; 22877e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng bool LdmBypass = false; 2288e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng switch (DefMCID.getOpcode()) { 2289a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng default: 2290a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng DefCycle = ItinData->getOperandCycle(DefClass, DefIdx); 2291a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng break; 229273fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling 229373fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMDIA: 229473fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMDIA_UPD: 229573fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMDDB_UPD: 229673fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMSIA: 229773fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMSIA_UPD: 229873fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMSDB_UPD: 2299e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng DefCycle = getVLDMDefCycle(ItinData, DefMCID, DefClass, DefIdx, DefAlign); 23005a50ceeaea980962c1982ad535226c7ab06c971cEvan Cheng break; 230173fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling 230273fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMIA_RET: 230373fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMIA: 230473fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMDA: 230573fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMDB: 230673fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMIB: 230773fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMIA_UPD: 230873fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMDA_UPD: 230973fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMDB_UPD: 231073fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMIB_UPD: 231173fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::tLDMIA: 231273fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::tLDMIA_UPD: 2313a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng case ARM::tPUSH: 231473fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2LDMIA_RET: 231573fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2LDMIA: 231673fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2LDMDB: 231773fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2LDMIA_UPD: 231873fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2LDMDB_UPD: 2319a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng LdmBypass = 1; 2320e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng DefCycle = getLDMDefCycle(ItinData, DefMCID, DefClass, DefIdx, DefAlign); 2321344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng break; 2322a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng } 2323a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng 2324a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng if (DefCycle == -1) 2325a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng // We can't seem to determine the result latency of the def, assume it's 2. 2326a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng DefCycle = 2; 2327a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng 2328a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng int UseCycle = -1; 2329e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng switch (UseMCID.getOpcode()) { 2330a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng default: 2331a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng UseCycle = ItinData->getOperandCycle(UseClass, UseIdx); 2332a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng break; 233373fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling 233473fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMDIA: 233573fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMDIA_UPD: 233673fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMDDB_UPD: 233773fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMSIA: 233873fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMSIA_UPD: 233973fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMSDB_UPD: 2340e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng UseCycle = getVSTMUseCycle(ItinData, UseMCID, UseClass, UseIdx, UseAlign); 23415a50ceeaea980962c1982ad535226c7ab06c971cEvan Cheng break; 234273fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling 234373fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::STMIA: 234473fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::STMDA: 234573fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::STMDB: 234673fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::STMIB: 234773fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::STMIA_UPD: 234873fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::STMDA_UPD: 234973fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::STMDB_UPD: 235073fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::STMIB_UPD: 235173fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::tSTMIA_UPD: 2352a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng case ARM::tPOP_RET: 2353a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng case ARM::tPOP: 235473fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2STMIA: 235573fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2STMDB: 235673fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2STMIA_UPD: 235773fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2STMDB_UPD: 2358e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng UseCycle = getSTMUseCycle(ItinData, UseMCID, UseClass, UseIdx, UseAlign); 23595a50ceeaea980962c1982ad535226c7ab06c971cEvan Cheng break; 2360a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng } 2361a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng 2362a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng if (UseCycle == -1) 2363a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng // Assume it's read in the first stage. 2364a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng UseCycle = 1; 2365a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng 2366a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng UseCycle = DefCycle - UseCycle + 1; 2367a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng if (UseCycle > 0) { 2368a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng if (LdmBypass) { 2369a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng // It's a variable_ops instruction so we can't use DefIdx here. Just use 2370a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng // first def operand. 2371e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng if (ItinData->hasPipelineForwarding(DefClass, DefMCID.getNumOperands()-1, 2372a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng UseClass, UseIdx)) 2373a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng --UseCycle; 2374a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng } else if (ItinData->hasPipelineForwarding(DefClass, DefIdx, 237573fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling UseClass, UseIdx)) { 2376a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng --UseCycle; 237773fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling } 2378a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng } 2379a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng 2380a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng return UseCycle; 2381a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng} 2382a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng 2383ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Chengstatic const MachineInstr *getBundledDefMI(const TargetRegisterInfo *TRI, 2384020f4106f820648fd7e91956859844a80de13974Evan Cheng const MachineInstr *MI, unsigned Reg, 2385ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng unsigned &DefIdx, unsigned &Dist) { 2386ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng Dist = 0; 2387ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng 2388ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng MachineBasicBlock::const_iterator I = MI; ++I; 2389ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng MachineBasicBlock::const_instr_iterator II = 2390ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng llvm::prior(I.getInstrIterator()); 2391ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng assert(II->isInsideBundle() && "Empty bundle?"); 2392ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng 2393ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng int Idx = -1; 2394ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng while (II->isInsideBundle()) { 2395ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng Idx = II->findRegisterDefOperandIdx(Reg, false, true, TRI); 2396ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng if (Idx != -1) 2397ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng break; 2398ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng --II; 2399ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng ++Dist; 2400ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng } 2401ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng 2402ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng assert(Idx != -1 && "Cannot find bundled definition!"); 2403ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng DefIdx = Idx; 2404ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng return II; 2405ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng} 2406ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng 2407ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Chengstatic const MachineInstr *getBundledUseMI(const TargetRegisterInfo *TRI, 2408020f4106f820648fd7e91956859844a80de13974Evan Cheng const MachineInstr *MI, unsigned Reg, 2409ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng unsigned &UseIdx, unsigned &Dist) { 2410ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng Dist = 0; 2411ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng 2412ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng MachineBasicBlock::const_instr_iterator II = MI; ++II; 2413ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng assert(II->isInsideBundle() && "Empty bundle?"); 2414ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end(); 2415ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng 2416ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng // FIXME: This doesn't properly handle multiple uses. 2417ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng int Idx = -1; 2418ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng while (II != E && II->isInsideBundle()) { 2419ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng Idx = II->findRegisterUseOperandIdx(Reg, false, TRI); 2420ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng if (Idx != -1) 2421ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng break; 2422ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng if (II->getOpcode() != ARM::t2IT) 2423ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng ++Dist; 2424ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng ++II; 2425ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng } 2426ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng 2427020f4106f820648fd7e91956859844a80de13974Evan Cheng if (Idx == -1) { 2428020f4106f820648fd7e91956859844a80de13974Evan Cheng Dist = 0; 2429020f4106f820648fd7e91956859844a80de13974Evan Cheng return 0; 2430020f4106f820648fd7e91956859844a80de13974Evan Cheng } 2431020f4106f820648fd7e91956859844a80de13974Evan Cheng 2432ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng UseIdx = Idx; 2433ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng return II; 2434ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng} 2435ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng 2436a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Chengint 2437a0792de66c8364d47b0a688c7f408efb7b10f31bEvan ChengARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData, 2438a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng const MachineInstr *DefMI, unsigned DefIdx, 2439a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng const MachineInstr *UseMI, unsigned UseIdx) const { 2440a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng if (DefMI->isCopyLike() || DefMI->isInsertSubreg() || 2441a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng DefMI->isRegSequence() || DefMI->isImplicitDef()) 2442a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng return 1; 2443a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng 2444a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng if (!ItinData || ItinData->isEmpty()) 24455a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng return DefMI->mayLoad() ? 3 : 1; 2446a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng 2447ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng const MCInstrDesc *DefMCID = &DefMI->getDesc(); 2448ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng const MCInstrDesc *UseMCID = &UseMI->getDesc(); 2449dd9dd6f857604abdeb5213648ffe50c10ccc59b9Evan Cheng const MachineOperand &DefMO = DefMI->getOperand(DefIdx); 2450020f4106f820648fd7e91956859844a80de13974Evan Cheng unsigned Reg = DefMO.getReg(); 2451020f4106f820648fd7e91956859844a80de13974Evan Cheng if (Reg == ARM::CPSR) { 2452e09206d4d7683e2a421104c5cb83f7808ba4b06eEvan Cheng if (DefMI->getOpcode() == ARM::FMSTAT) { 2453e09206d4d7683e2a421104c5cb83f7808ba4b06eEvan Cheng // fpscr -> cpsr stalls over 20 cycles on A8 (and earlier?) 2454e09206d4d7683e2a421104c5cb83f7808ba4b06eEvan Cheng return Subtarget.isCortexA9() ? 1 : 20; 2455e09206d4d7683e2a421104c5cb83f7808ba4b06eEvan Cheng } 2456e09206d4d7683e2a421104c5cb83f7808ba4b06eEvan Cheng 2457dd9dd6f857604abdeb5213648ffe50c10ccc59b9Evan Cheng // CPSR set and branch can be paired in the same cycle. 24585a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng if (UseMI->isBranch()) 2459e09206d4d7683e2a421104c5cb83f7808ba4b06eEvan Cheng return 0; 2460ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng 2461ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng // Otherwise it takes the instruction latency (generally one). 2462ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng int Latency = getInstrLatency(ItinData, DefMI); 2463020f4106f820648fd7e91956859844a80de13974Evan Cheng 2464020f4106f820648fd7e91956859844a80de13974Evan Cheng // For Thumb2 and -Os, prefer scheduling CPSR setting instruction close to 2465020f4106f820648fd7e91956859844a80de13974Evan Cheng // its uses. Instructions which are otherwise scheduled between them may 2466020f4106f820648fd7e91956859844a80de13974Evan Cheng // incur a code size penalty (not able to use the CPSR setting 16-bit 2467020f4106f820648fd7e91956859844a80de13974Evan Cheng // instructions). 2468020f4106f820648fd7e91956859844a80de13974Evan Cheng if (Latency > 0 && Subtarget.isThumb2()) { 2469020f4106f820648fd7e91956859844a80de13974Evan Cheng const MachineFunction *MF = DefMI->getParent()->getParent(); 2470020f4106f820648fd7e91956859844a80de13974Evan Cheng if (MF->getFunction()->hasFnAttr(Attribute::OptimizeForSize)) 2471020f4106f820648fd7e91956859844a80de13974Evan Cheng --Latency; 2472020f4106f820648fd7e91956859844a80de13974Evan Cheng } 2473ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng return Latency; 2474e09206d4d7683e2a421104c5cb83f7808ba4b06eEvan Cheng } 2475dd9dd6f857604abdeb5213648ffe50c10ccc59b9Evan Cheng 2476a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng unsigned DefAlign = DefMI->hasOneMemOperand() 2477a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng ? (*DefMI->memoperands_begin())->getAlignment() : 0; 2478a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng unsigned UseAlign = UseMI->hasOneMemOperand() 2479a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng ? (*UseMI->memoperands_begin())->getAlignment() : 0; 2480ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng 2481ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng unsigned DefAdj = 0; 2482ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng if (DefMI->isBundle()) { 2483020f4106f820648fd7e91956859844a80de13974Evan Cheng DefMI = getBundledDefMI(&getRegisterInfo(), DefMI, Reg, DefIdx, DefAdj); 2484ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng if (DefMI->isCopyLike() || DefMI->isInsertSubreg() || 2485ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng DefMI->isRegSequence() || DefMI->isImplicitDef()) 2486ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng return 1; 2487ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng DefMCID = &DefMI->getDesc(); 2488ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng } 2489ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng unsigned UseAdj = 0; 2490ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng if (UseMI->isBundle()) { 2491020f4106f820648fd7e91956859844a80de13974Evan Cheng unsigned NewUseIdx; 2492020f4106f820648fd7e91956859844a80de13974Evan Cheng const MachineInstr *NewUseMI = getBundledUseMI(&getRegisterInfo(), UseMI, 2493020f4106f820648fd7e91956859844a80de13974Evan Cheng Reg, NewUseIdx, UseAdj); 2494020f4106f820648fd7e91956859844a80de13974Evan Cheng if (NewUseMI) { 2495020f4106f820648fd7e91956859844a80de13974Evan Cheng UseMI = NewUseMI; 2496020f4106f820648fd7e91956859844a80de13974Evan Cheng UseIdx = NewUseIdx; 2497020f4106f820648fd7e91956859844a80de13974Evan Cheng UseMCID = &UseMI->getDesc(); 2498020f4106f820648fd7e91956859844a80de13974Evan Cheng } 2499ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng } 2500ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng 2501ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng int Latency = getOperandLatency(ItinData, *DefMCID, DefIdx, DefAlign, 2502ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng *UseMCID, UseIdx, UseAlign); 2503ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng int Adj = DefAdj + UseAdj; 2504ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng if (Adj) { 2505ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng Latency -= (int)(DefAdj + UseAdj); 2506ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng if (Latency < 1) 2507ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng return 1; 2508ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng } 25097e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng 25107e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng if (Latency > 1 && 25117e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng (Subtarget.isCortexA8() || Subtarget.isCortexA9())) { 25127e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng // FIXME: Shifter op hack: no shift (i.e. [r +/- r]) or [r + r << 2] 25137e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng // variants are one cycle cheaper. 2514ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng switch (DefMCID->getOpcode()) { 25157e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng default: break; 25167e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng case ARM::LDRrs: 25177e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng case ARM::LDRBrs: { 25187e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng unsigned ShOpVal = DefMI->getOperand(3).getImm(); 25197e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal); 25207e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng if (ShImm == 0 || 25217e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng (ShImm == 2 && ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl)) 25227e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng --Latency; 25237e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng break; 25247e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng } 25257e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng case ARM::t2LDRs: 25267e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng case ARM::t2LDRBs: 25277e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng case ARM::t2LDRHs: 25287e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng case ARM::t2LDRSHs: { 25297e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng // Thumb2 mode: lsl only. 25307e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng unsigned ShAmt = DefMI->getOperand(3).getImm(); 25317e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng if (ShAmt == 0 || ShAmt == 2) 25327e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng --Latency; 25337e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng break; 25347e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng } 25357e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng } 25367e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng } 25377e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng 253875b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng if (DefAlign < 8 && Subtarget.isCortexA9()) 2539ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng switch (DefMCID->getOpcode()) { 254075b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng default: break; 254175b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1q8: 254275b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1q16: 254375b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1q32: 254475b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1q64: 254510b90a9bbf7dcae1568c03a03f9606f5395f2144Jim Grosbach case ARM::VLD1q8wb_fixed: 254610b90a9bbf7dcae1568c03a03f9606f5395f2144Jim Grosbach case ARM::VLD1q16wb_fixed: 254710b90a9bbf7dcae1568c03a03f9606f5395f2144Jim Grosbach case ARM::VLD1q32wb_fixed: 254810b90a9bbf7dcae1568c03a03f9606f5395f2144Jim Grosbach case ARM::VLD1q64wb_fixed: 254910b90a9bbf7dcae1568c03a03f9606f5395f2144Jim Grosbach case ARM::VLD1q8wb_register: 255010b90a9bbf7dcae1568c03a03f9606f5395f2144Jim Grosbach case ARM::VLD1q16wb_register: 255110b90a9bbf7dcae1568c03a03f9606f5395f2144Jim Grosbach case ARM::VLD1q32wb_register: 255210b90a9bbf7dcae1568c03a03f9606f5395f2144Jim Grosbach case ARM::VLD1q64wb_register: 255375b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2d8: 255475b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2d16: 255575b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2d32: 255675b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2q8: 255775b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2q16: 255875b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2q32: 2559a4e3c7fc4ba2d55695b0484480685698132eba20Jim Grosbach case ARM::VLD2d8wb_fixed: 2560a4e3c7fc4ba2d55695b0484480685698132eba20Jim Grosbach case ARM::VLD2d16wb_fixed: 2561a4e3c7fc4ba2d55695b0484480685698132eba20Jim Grosbach case ARM::VLD2d32wb_fixed: 2562a4e3c7fc4ba2d55695b0484480685698132eba20Jim Grosbach case ARM::VLD2q8wb_fixed: 2563a4e3c7fc4ba2d55695b0484480685698132eba20Jim Grosbach case ARM::VLD2q16wb_fixed: 2564a4e3c7fc4ba2d55695b0484480685698132eba20Jim Grosbach case ARM::VLD2q32wb_fixed: 2565a4e3c7fc4ba2d55695b0484480685698132eba20Jim Grosbach case ARM::VLD2d8wb_register: 2566a4e3c7fc4ba2d55695b0484480685698132eba20Jim Grosbach case ARM::VLD2d16wb_register: 2567a4e3c7fc4ba2d55695b0484480685698132eba20Jim Grosbach case ARM::VLD2d32wb_register: 2568a4e3c7fc4ba2d55695b0484480685698132eba20Jim Grosbach case ARM::VLD2q8wb_register: 2569a4e3c7fc4ba2d55695b0484480685698132eba20Jim Grosbach case ARM::VLD2q16wb_register: 2570a4e3c7fc4ba2d55695b0484480685698132eba20Jim Grosbach case ARM::VLD2q32wb_register: 257175b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3d8: 257275b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3d16: 257375b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3d32: 257475b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1d64T: 257575b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3d8_UPD: 257675b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3d16_UPD: 257775b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3d32_UPD: 25785921675ff5ea632ab1e6d7aa5d1f263b858bbafaJim Grosbach case ARM::VLD1d64Twb_fixed: 25795921675ff5ea632ab1e6d7aa5d1f263b858bbafaJim Grosbach case ARM::VLD1d64Twb_register: 258075b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3q8_UPD: 258175b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3q16_UPD: 258275b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3q32_UPD: 258375b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4d8: 258475b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4d16: 258575b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4d32: 258675b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1d64Q: 258775b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4d8_UPD: 258875b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4d16_UPD: 258975b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4d32_UPD: 2590399cdca4d201f7232126c3a0643669971ede780aJim Grosbach case ARM::VLD1d64Qwb_fixed: 2591399cdca4d201f7232126c3a0643669971ede780aJim Grosbach case ARM::VLD1d64Qwb_register: 259275b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4q8_UPD: 259375b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4q16_UPD: 259475b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4q32_UPD: 259575b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1DUPq8: 259675b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1DUPq16: 259775b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1DUPq32: 2598096334e25ea68ac970942ecb680a82fbb8ad206cJim Grosbach case ARM::VLD1DUPq8wb_fixed: 2599096334e25ea68ac970942ecb680a82fbb8ad206cJim Grosbach case ARM::VLD1DUPq16wb_fixed: 2600096334e25ea68ac970942ecb680a82fbb8ad206cJim Grosbach case ARM::VLD1DUPq32wb_fixed: 2601096334e25ea68ac970942ecb680a82fbb8ad206cJim Grosbach case ARM::VLD1DUPq8wb_register: 2602096334e25ea68ac970942ecb680a82fbb8ad206cJim Grosbach case ARM::VLD1DUPq16wb_register: 2603096334e25ea68ac970942ecb680a82fbb8ad206cJim Grosbach case ARM::VLD1DUPq32wb_register: 260475b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2DUPd8: 260575b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2DUPd16: 260675b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2DUPd32: 2607e6949b13997e6d31aa4719a0e80c4b6b405e42a9Jim Grosbach case ARM::VLD2DUPd8wb_fixed: 2608e6949b13997e6d31aa4719a0e80c4b6b405e42a9Jim Grosbach case ARM::VLD2DUPd16wb_fixed: 2609e6949b13997e6d31aa4719a0e80c4b6b405e42a9Jim Grosbach case ARM::VLD2DUPd32wb_fixed: 2610e6949b13997e6d31aa4719a0e80c4b6b405e42a9Jim Grosbach case ARM::VLD2DUPd8wb_register: 2611e6949b13997e6d31aa4719a0e80c4b6b405e42a9Jim Grosbach case ARM::VLD2DUPd16wb_register: 2612e6949b13997e6d31aa4719a0e80c4b6b405e42a9Jim Grosbach case ARM::VLD2DUPd32wb_register: 261375b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4DUPd8: 261475b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4DUPd16: 261575b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4DUPd32: 261675b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4DUPd8_UPD: 261775b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4DUPd16_UPD: 261875b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4DUPd32_UPD: 261975b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1LNd8: 262075b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1LNd16: 262175b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1LNd32: 262275b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1LNd8_UPD: 262375b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1LNd16_UPD: 262475b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1LNd32_UPD: 262575b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2LNd8: 262675b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2LNd16: 262775b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2LNd32: 262875b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2LNq16: 262975b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2LNq32: 263075b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2LNd8_UPD: 263175b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2LNd16_UPD: 263275b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2LNd32_UPD: 263375b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2LNq16_UPD: 263475b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2LNq32_UPD: 263575b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4LNd8: 263675b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4LNd16: 263775b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4LNd32: 263875b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4LNq16: 263975b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4LNq32: 264075b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4LNd8_UPD: 264175b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4LNd16_UPD: 264275b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4LNd32_UPD: 264375b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4LNq16_UPD: 264475b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4LNq32_UPD: 264575b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng // If the address is not 64-bit aligned, the latencies of these 264675b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng // instructions increases by one. 264775b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng ++Latency; 264875b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng break; 264975b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng } 265075b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng 26517e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng return Latency; 2652a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng} 2653a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng 2654a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Chengint 2655a0792de66c8364d47b0a688c7f408efb7b10f31bEvan ChengARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData, 2656a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng SDNode *DefNode, unsigned DefIdx, 2657a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng SDNode *UseNode, unsigned UseIdx) const { 2658a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng if (!DefNode->isMachineOpcode()) 2659a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng return 1; 2660a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng 2661e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng const MCInstrDesc &DefMCID = get(DefNode->getMachineOpcode()); 2662c8bfd1d78ff9a307d1d4cb57cce4549b538e60f4Andrew Trick 2663e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng if (isZeroCost(DefMCID.Opcode)) 2664c8bfd1d78ff9a307d1d4cb57cce4549b538e60f4Andrew Trick return 0; 2665c8bfd1d78ff9a307d1d4cb57cce4549b538e60f4Andrew Trick 2666a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng if (!ItinData || ItinData->isEmpty()) 2667e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng return DefMCID.mayLoad() ? 3 : 1; 2668a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng 2669089751535d6e9adf65842e2ca5867bf9a70e1e95Evan Cheng if (!UseNode->isMachineOpcode()) { 2670e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng int Latency = ItinData->getOperandCycle(DefMCID.getSchedClass(), DefIdx); 2671089751535d6e9adf65842e2ca5867bf9a70e1e95Evan Cheng if (Subtarget.isCortexA9()) 2672089751535d6e9adf65842e2ca5867bf9a70e1e95Evan Cheng return Latency <= 2 ? 1 : Latency - 1; 2673089751535d6e9adf65842e2ca5867bf9a70e1e95Evan Cheng else 2674089751535d6e9adf65842e2ca5867bf9a70e1e95Evan Cheng return Latency <= 3 ? 1 : Latency - 2; 2675089751535d6e9adf65842e2ca5867bf9a70e1e95Evan Cheng } 2676a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng 2677e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng const MCInstrDesc &UseMCID = get(UseNode->getMachineOpcode()); 2678a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng const MachineSDNode *DefMN = dyn_cast<MachineSDNode>(DefNode); 2679a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng unsigned DefAlign = !DefMN->memoperands_empty() 2680a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng ? (*DefMN->memoperands_begin())->getAlignment() : 0; 2681a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng const MachineSDNode *UseMN = dyn_cast<MachineSDNode>(UseNode); 2682a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng unsigned UseAlign = !UseMN->memoperands_empty() 2683a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng ? (*UseMN->memoperands_begin())->getAlignment() : 0; 2684e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng int Latency = getOperandLatency(ItinData, DefMCID, DefIdx, DefAlign, 2685e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng UseMCID, UseIdx, UseAlign); 26867e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng 26877e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng if (Latency > 1 && 26887e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng (Subtarget.isCortexA8() || Subtarget.isCortexA9())) { 26897e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng // FIXME: Shifter op hack: no shift (i.e. [r +/- r]) or [r + r << 2] 26907e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng // variants are one cycle cheaper. 2691e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng switch (DefMCID.getOpcode()) { 26927e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng default: break; 26937e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng case ARM::LDRrs: 26947e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng case ARM::LDRBrs: { 26957e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng unsigned ShOpVal = 26967e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng cast<ConstantSDNode>(DefNode->getOperand(2))->getZExtValue(); 26977e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal); 26987e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng if (ShImm == 0 || 26997e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng (ShImm == 2 && ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl)) 27007e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng --Latency; 27017e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng break; 27027e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng } 27037e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng case ARM::t2LDRs: 27047e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng case ARM::t2LDRBs: 27057e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng case ARM::t2LDRHs: 27067e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng case ARM::t2LDRSHs: { 27077e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng // Thumb2 mode: lsl only. 27087e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng unsigned ShAmt = 27097e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng cast<ConstantSDNode>(DefNode->getOperand(2))->getZExtValue(); 27107e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng if (ShAmt == 0 || ShAmt == 2) 27117e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng --Latency; 27127e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng break; 27137e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng } 27147e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng } 27157e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng } 27167e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng 271775b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng if (DefAlign < 8 && Subtarget.isCortexA9()) 2718e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng switch (DefMCID.getOpcode()) { 271975b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng default: break; 272028f08c93e75d291695ea89b9004145103292e85bJim Grosbach case ARM::VLD1q8: 272128f08c93e75d291695ea89b9004145103292e85bJim Grosbach case ARM::VLD1q16: 272228f08c93e75d291695ea89b9004145103292e85bJim Grosbach case ARM::VLD1q32: 272328f08c93e75d291695ea89b9004145103292e85bJim Grosbach case ARM::VLD1q64: 272428f08c93e75d291695ea89b9004145103292e85bJim Grosbach case ARM::VLD1q8wb_register: 272528f08c93e75d291695ea89b9004145103292e85bJim Grosbach case ARM::VLD1q16wb_register: 272628f08c93e75d291695ea89b9004145103292e85bJim Grosbach case ARM::VLD1q32wb_register: 272728f08c93e75d291695ea89b9004145103292e85bJim Grosbach case ARM::VLD1q64wb_register: 272828f08c93e75d291695ea89b9004145103292e85bJim Grosbach case ARM::VLD1q8wb_fixed: 272928f08c93e75d291695ea89b9004145103292e85bJim Grosbach case ARM::VLD1q16wb_fixed: 273028f08c93e75d291695ea89b9004145103292e85bJim Grosbach case ARM::VLD1q32wb_fixed: 273128f08c93e75d291695ea89b9004145103292e85bJim Grosbach case ARM::VLD1q64wb_fixed: 273228f08c93e75d291695ea89b9004145103292e85bJim Grosbach case ARM::VLD2d8: 273328f08c93e75d291695ea89b9004145103292e85bJim Grosbach case ARM::VLD2d16: 273428f08c93e75d291695ea89b9004145103292e85bJim Grosbach case ARM::VLD2d32: 273575b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2q8Pseudo: 273675b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2q16Pseudo: 273775b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2q32Pseudo: 273828f08c93e75d291695ea89b9004145103292e85bJim Grosbach case ARM::VLD2d8wb_fixed: 273928f08c93e75d291695ea89b9004145103292e85bJim Grosbach case ARM::VLD2d16wb_fixed: 274028f08c93e75d291695ea89b9004145103292e85bJim Grosbach case ARM::VLD2d32wb_fixed: 2741a4e3c7fc4ba2d55695b0484480685698132eba20Jim Grosbach case ARM::VLD2q8PseudoWB_fixed: 2742a4e3c7fc4ba2d55695b0484480685698132eba20Jim Grosbach case ARM::VLD2q16PseudoWB_fixed: 2743a4e3c7fc4ba2d55695b0484480685698132eba20Jim Grosbach case ARM::VLD2q32PseudoWB_fixed: 274428f08c93e75d291695ea89b9004145103292e85bJim Grosbach case ARM::VLD2d8wb_register: 274528f08c93e75d291695ea89b9004145103292e85bJim Grosbach case ARM::VLD2d16wb_register: 274628f08c93e75d291695ea89b9004145103292e85bJim Grosbach case ARM::VLD2d32wb_register: 2747a4e3c7fc4ba2d55695b0484480685698132eba20Jim Grosbach case ARM::VLD2q8PseudoWB_register: 2748a4e3c7fc4ba2d55695b0484480685698132eba20Jim Grosbach case ARM::VLD2q16PseudoWB_register: 2749a4e3c7fc4ba2d55695b0484480685698132eba20Jim Grosbach case ARM::VLD2q32PseudoWB_register: 275075b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3d8Pseudo: 275175b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3d16Pseudo: 275275b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3d32Pseudo: 275375b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1d64TPseudo: 275475b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3d8Pseudo_UPD: 275575b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3d16Pseudo_UPD: 275675b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3d32Pseudo_UPD: 275775b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3q8Pseudo_UPD: 275875b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3q16Pseudo_UPD: 275975b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3q32Pseudo_UPD: 276075b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3q8oddPseudo: 276175b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3q16oddPseudo: 276275b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3q32oddPseudo: 276375b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3q8oddPseudo_UPD: 276475b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3q16oddPseudo_UPD: 276575b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3q32oddPseudo_UPD: 276675b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4d8Pseudo: 276775b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4d16Pseudo: 276875b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4d32Pseudo: 276975b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1d64QPseudo: 277075b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4d8Pseudo_UPD: 277175b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4d16Pseudo_UPD: 277275b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4d32Pseudo_UPD: 277375b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4q8Pseudo_UPD: 277475b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4q16Pseudo_UPD: 277575b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4q32Pseudo_UPD: 277675b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4q8oddPseudo: 277775b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4q16oddPseudo: 277875b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4q32oddPseudo: 277975b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4q8oddPseudo_UPD: 278075b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4q16oddPseudo_UPD: 278175b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4q32oddPseudo_UPD: 2782c0fc450f0754508871bc70f21e528bf2f1520da1Jim Grosbach case ARM::VLD1DUPq8: 2783c0fc450f0754508871bc70f21e528bf2f1520da1Jim Grosbach case ARM::VLD1DUPq16: 2784c0fc450f0754508871bc70f21e528bf2f1520da1Jim Grosbach case ARM::VLD1DUPq32: 2785c0fc450f0754508871bc70f21e528bf2f1520da1Jim Grosbach case ARM::VLD1DUPq8wb_fixed: 2786c0fc450f0754508871bc70f21e528bf2f1520da1Jim Grosbach case ARM::VLD1DUPq16wb_fixed: 2787c0fc450f0754508871bc70f21e528bf2f1520da1Jim Grosbach case ARM::VLD1DUPq32wb_fixed: 2788c0fc450f0754508871bc70f21e528bf2f1520da1Jim Grosbach case ARM::VLD1DUPq8wb_register: 2789c0fc450f0754508871bc70f21e528bf2f1520da1Jim Grosbach case ARM::VLD1DUPq16wb_register: 2790c0fc450f0754508871bc70f21e528bf2f1520da1Jim Grosbach case ARM::VLD1DUPq32wb_register: 2791c0fc450f0754508871bc70f21e528bf2f1520da1Jim Grosbach case ARM::VLD2DUPd8: 2792c0fc450f0754508871bc70f21e528bf2f1520da1Jim Grosbach case ARM::VLD2DUPd16: 2793c0fc450f0754508871bc70f21e528bf2f1520da1Jim Grosbach case ARM::VLD2DUPd32: 2794c0fc450f0754508871bc70f21e528bf2f1520da1Jim Grosbach case ARM::VLD2DUPd8wb_fixed: 2795c0fc450f0754508871bc70f21e528bf2f1520da1Jim Grosbach case ARM::VLD2DUPd16wb_fixed: 2796c0fc450f0754508871bc70f21e528bf2f1520da1Jim Grosbach case ARM::VLD2DUPd32wb_fixed: 2797c0fc450f0754508871bc70f21e528bf2f1520da1Jim Grosbach case ARM::VLD2DUPd8wb_register: 2798c0fc450f0754508871bc70f21e528bf2f1520da1Jim Grosbach case ARM::VLD2DUPd16wb_register: 2799c0fc450f0754508871bc70f21e528bf2f1520da1Jim Grosbach case ARM::VLD2DUPd32wb_register: 280075b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4DUPd8Pseudo: 280175b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4DUPd16Pseudo: 280275b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4DUPd32Pseudo: 280375b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4DUPd8Pseudo_UPD: 280475b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4DUPd16Pseudo_UPD: 280575b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4DUPd32Pseudo_UPD: 280675b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1LNq8Pseudo: 280775b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1LNq16Pseudo: 280875b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1LNq32Pseudo: 280975b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1LNq8Pseudo_UPD: 281075b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1LNq16Pseudo_UPD: 281175b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1LNq32Pseudo_UPD: 281275b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2LNd8Pseudo: 281375b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2LNd16Pseudo: 281475b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2LNd32Pseudo: 281575b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2LNq16Pseudo: 281675b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2LNq32Pseudo: 281775b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2LNd8Pseudo_UPD: 281875b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2LNd16Pseudo_UPD: 281975b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2LNd32Pseudo_UPD: 282075b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2LNq16Pseudo_UPD: 282175b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2LNq32Pseudo_UPD: 282275b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4LNd8Pseudo: 282375b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4LNd16Pseudo: 282475b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4LNd32Pseudo: 282575b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4LNq16Pseudo: 282675b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4LNq32Pseudo: 282775b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4LNd8Pseudo_UPD: 282875b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4LNd16Pseudo_UPD: 282975b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4LNd32Pseudo_UPD: 283075b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4LNq16Pseudo_UPD: 283175b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4LNq32Pseudo_UPD: 283275b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng // If the address is not 64-bit aligned, the latencies of these 283375b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng // instructions increases by one. 283475b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng ++Latency; 283575b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng break; 283675b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng } 283775b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng 28387e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng return Latency; 2839a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng} 28402312842de0c641107dd04d7e056d02491cc781caEvan Cheng 2841020f4106f820648fd7e91956859844a80de13974Evan Chengunsigned 2842020f4106f820648fd7e91956859844a80de13974Evan ChengARMBaseInstrInfo::getOutputLatency(const InstrItineraryData *ItinData, 2843020f4106f820648fd7e91956859844a80de13974Evan Cheng const MachineInstr *DefMI, unsigned DefIdx, 2844020f4106f820648fd7e91956859844a80de13974Evan Cheng const MachineInstr *DepMI) const { 2845020f4106f820648fd7e91956859844a80de13974Evan Cheng unsigned Reg = DefMI->getOperand(DefIdx).getReg(); 2846020f4106f820648fd7e91956859844a80de13974Evan Cheng if (DepMI->readsRegister(Reg, &getRegisterInfo()) || !isPredicated(DepMI)) 2847020f4106f820648fd7e91956859844a80de13974Evan Cheng return 1; 2848020f4106f820648fd7e91956859844a80de13974Evan Cheng 2849020f4106f820648fd7e91956859844a80de13974Evan Cheng // If the second MI is predicated, then there is an implicit use dependency. 2850020f4106f820648fd7e91956859844a80de13974Evan Cheng return getOperandLatency(ItinData, DefMI, DefIdx, DepMI, 2851020f4106f820648fd7e91956859844a80de13974Evan Cheng DepMI->getNumOperands()); 2852020f4106f820648fd7e91956859844a80de13974Evan Cheng} 2853020f4106f820648fd7e91956859844a80de13974Evan Cheng 28548239daf7c83a65a189c352cce3191cdc3bbfe151Evan Chengint ARMBaseInstrInfo::getInstrLatency(const InstrItineraryData *ItinData, 28558239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng const MachineInstr *MI, 28568239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng unsigned *PredCost) const { 28578239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng if (MI->isCopyLike() || MI->isInsertSubreg() || 28588239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng MI->isRegSequence() || MI->isImplicitDef()) 28598239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng return 1; 28608239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng 28618239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng if (!ItinData || ItinData->isEmpty()) 28628239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng return 1; 28638239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng 2864ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng if (MI->isBundle()) { 2865ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng int Latency = 0; 2866ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng MachineBasicBlock::const_instr_iterator I = MI; 2867ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end(); 2868ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng while (++I != E && I->isInsideBundle()) { 2869ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng if (I->getOpcode() != ARM::t2IT) 2870ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng Latency += getInstrLatency(ItinData, I, PredCost); 2871ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng } 2872ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng return Latency; 2873ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng } 2874ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng 2875e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng const MCInstrDesc &MCID = MI->getDesc(); 2876e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng unsigned Class = MCID.getSchedClass(); 28778239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng unsigned UOps = ItinData->Itineraries[Class].NumMicroOps; 28788c3b87cf19df5631125254784d57446b80e12397Jakob Stoklund Olesen if (PredCost && (MCID.isCall() || MCID.hasImplicitDefOfPhysReg(ARM::CPSR))) 28798239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng // When predicated, CPSR is an additional source operand for CPSR updating 28808239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng // instructions, this apparently increases their latencies. 28818239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng *PredCost = 1; 28828239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng if (UOps) 28838239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng return ItinData->getStageLatency(Class); 28848239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng return getNumMicroOps(ItinData, MI); 28858239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng} 28868239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng 28878239daf7c83a65a189c352cce3191cdc3bbfe151Evan Chengint ARMBaseInstrInfo::getInstrLatency(const InstrItineraryData *ItinData, 28888239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng SDNode *Node) const { 28898239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng if (!Node->isMachineOpcode()) 28908239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng return 1; 28918239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng 28928239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng if (!ItinData || ItinData->isEmpty()) 28938239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng return 1; 28948239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng 28958239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng unsigned Opcode = Node->getMachineOpcode(); 28968239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng switch (Opcode) { 28978239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng default: 28988239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng return ItinData->getStageLatency(get(Opcode).getSchedClass()); 289973fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMQIA: 290073fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMQIA: 29018239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng return 2; 29028b3ca6216d62bf3f729c2e122dcfeb7c4d7500dcEric Christopher } 29038239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng} 29048239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng 29052312842de0c641107dd04d7e056d02491cc781caEvan Chengbool ARMBaseInstrInfo:: 29062312842de0c641107dd04d7e056d02491cc781caEvan ChenghasHighOperandLatency(const InstrItineraryData *ItinData, 29072312842de0c641107dd04d7e056d02491cc781caEvan Cheng const MachineRegisterInfo *MRI, 29082312842de0c641107dd04d7e056d02491cc781caEvan Cheng const MachineInstr *DefMI, unsigned DefIdx, 29092312842de0c641107dd04d7e056d02491cc781caEvan Cheng const MachineInstr *UseMI, unsigned UseIdx) const { 29102312842de0c641107dd04d7e056d02491cc781caEvan Cheng unsigned DDomain = DefMI->getDesc().TSFlags & ARMII::DomainMask; 29112312842de0c641107dd04d7e056d02491cc781caEvan Cheng unsigned UDomain = UseMI->getDesc().TSFlags & ARMII::DomainMask; 29122312842de0c641107dd04d7e056d02491cc781caEvan Cheng if (Subtarget.isCortexA8() && 29132312842de0c641107dd04d7e056d02491cc781caEvan Cheng (DDomain == ARMII::DomainVFP || UDomain == ARMII::DomainVFP)) 29142312842de0c641107dd04d7e056d02491cc781caEvan Cheng // CortexA8 VFP instructions are not pipelined. 29152312842de0c641107dd04d7e056d02491cc781caEvan Cheng return true; 29162312842de0c641107dd04d7e056d02491cc781caEvan Cheng 29172312842de0c641107dd04d7e056d02491cc781caEvan Cheng // Hoist VFP / NEON instructions with 4 or higher latency. 29182312842de0c641107dd04d7e056d02491cc781caEvan Cheng int Latency = getOperandLatency(ItinData, DefMI, DefIdx, UseMI, UseIdx); 29192312842de0c641107dd04d7e056d02491cc781caEvan Cheng if (Latency <= 3) 29202312842de0c641107dd04d7e056d02491cc781caEvan Cheng return false; 29212312842de0c641107dd04d7e056d02491cc781caEvan Cheng return DDomain == ARMII::DomainVFP || DDomain == ARMII::DomainNEON || 29222312842de0c641107dd04d7e056d02491cc781caEvan Cheng UDomain == ARMII::DomainVFP || UDomain == ARMII::DomainNEON; 29232312842de0c641107dd04d7e056d02491cc781caEvan Cheng} 2924c8141dfc7f983cb04e65d8acd6bcbdc8e4b8a0aeEvan Cheng 2925c8141dfc7f983cb04e65d8acd6bcbdc8e4b8a0aeEvan Chengbool ARMBaseInstrInfo:: 2926c8141dfc7f983cb04e65d8acd6bcbdc8e4b8a0aeEvan ChenghasLowDefLatency(const InstrItineraryData *ItinData, 2927c8141dfc7f983cb04e65d8acd6bcbdc8e4b8a0aeEvan Cheng const MachineInstr *DefMI, unsigned DefIdx) const { 2928c8141dfc7f983cb04e65d8acd6bcbdc8e4b8a0aeEvan Cheng if (!ItinData || ItinData->isEmpty()) 2929c8141dfc7f983cb04e65d8acd6bcbdc8e4b8a0aeEvan Cheng return false; 2930c8141dfc7f983cb04e65d8acd6bcbdc8e4b8a0aeEvan Cheng 2931c8141dfc7f983cb04e65d8acd6bcbdc8e4b8a0aeEvan Cheng unsigned DDomain = DefMI->getDesc().TSFlags & ARMII::DomainMask; 2932c8141dfc7f983cb04e65d8acd6bcbdc8e4b8a0aeEvan Cheng if (DDomain == ARMII::DomainGeneral) { 2933c8141dfc7f983cb04e65d8acd6bcbdc8e4b8a0aeEvan Cheng unsigned DefClass = DefMI->getDesc().getSchedClass(); 2934c8141dfc7f983cb04e65d8acd6bcbdc8e4b8a0aeEvan Cheng int DefCycle = ItinData->getOperandCycle(DefClass, DefIdx); 2935c8141dfc7f983cb04e65d8acd6bcbdc8e4b8a0aeEvan Cheng return (DefCycle != -1 && DefCycle <= 2); 2936c8141dfc7f983cb04e65d8acd6bcbdc8e4b8a0aeEvan Cheng } 2937c8141dfc7f983cb04e65d8acd6bcbdc8e4b8a0aeEvan Cheng return false; 2938c8141dfc7f983cb04e65d8acd6bcbdc8e4b8a0aeEvan Cheng} 293948575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng 29403be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trickbool ARMBaseInstrInfo::verifyInstruction(const MachineInstr *MI, 29413be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick StringRef &ErrInfo) const { 29423be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick if (convertAddSubFlagsOpcode(MI->getOpcode())) { 29433be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick ErrInfo = "Pseudo flag setting opcodes only exist in Selection DAG"; 29443be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick return false; 29453be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick } 29463be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick return true; 29473be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick} 29483be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick 294948575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Chengbool 295048575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan ChengARMBaseInstrInfo::isFpMLxInstruction(unsigned Opcode, unsigned &MulOpc, 295148575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng unsigned &AddSubOpc, 295248575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng bool &NegAcc, bool &HasLane) const { 295348575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng DenseMap<unsigned, unsigned>::const_iterator I = MLxEntryMap.find(Opcode); 295448575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng if (I == MLxEntryMap.end()) 295548575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng return false; 295648575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng 295748575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng const ARM_MLxEntry &Entry = ARM_MLxTable[I->second]; 295848575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng MulOpc = Entry.MulOpc; 295948575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng AddSubOpc = Entry.AddSubOpc; 296048575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng NegAcc = Entry.NegAcc; 296148575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng HasLane = Entry.HasLane; 296248575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng return true; 296348575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng} 296413fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen 296513fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen//===----------------------------------------------------------------------===// 296613fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen// Execution domains. 296713fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen//===----------------------------------------------------------------------===// 296813fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen// 296913fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen// Some instructions go down the NEON pipeline, some go down the VFP pipeline, 297013fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen// and some can go down both. The vmov instructions go down the VFP pipeline, 297113fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen// but they can be changed to vorr equivalents that are executed by the NEON 297213fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen// pipeline. 297313fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen// 297413fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen// We use the following execution domain numbering: 297513fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen// 29768bb3d3cb30df06bdcb3ef5a208e3e59f4eeb4868Jakob Stoklund Olesenenum ARMExeDomain { 29778bb3d3cb30df06bdcb3ef5a208e3e59f4eeb4868Jakob Stoklund Olesen ExeGeneric = 0, 29788bb3d3cb30df06bdcb3ef5a208e3e59f4eeb4868Jakob Stoklund Olesen ExeVFP = 1, 29798bb3d3cb30df06bdcb3ef5a208e3e59f4eeb4868Jakob Stoklund Olesen ExeNEON = 2 29808bb3d3cb30df06bdcb3ef5a208e3e59f4eeb4868Jakob Stoklund Olesen}; 298113fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen// 298213fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen// Also see ARMInstrFormats.td and Domain* enums in ARMBaseInfo.h 298313fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen// 298413fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesenstd::pair<uint16_t, uint16_t> 298513fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund OlesenARMBaseInstrInfo::getExecutionDomain(const MachineInstr *MI) const { 298613fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen // VMOVD is a VFP instruction, but can be changed to NEON if it isn't 298713fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen // predicated. 298813fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen if (MI->getOpcode() == ARM::VMOVD && !isPredicated(MI)) 29898bb3d3cb30df06bdcb3ef5a208e3e59f4eeb4868Jakob Stoklund Olesen return std::make_pair(ExeVFP, (1<<ExeVFP) | (1<<ExeNEON)); 299013fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen 299113fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen // No other instructions can be swizzled, so just determine their domain. 299213fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen unsigned Domain = MI->getDesc().TSFlags & ARMII::DomainMask; 299313fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen 299413fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen if (Domain & ARMII::DomainNEON) 29958bb3d3cb30df06bdcb3ef5a208e3e59f4eeb4868Jakob Stoklund Olesen return std::make_pair(ExeNEON, 0); 299613fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen 299713fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen // Certain instructions can go either way on Cortex-A8. 299813fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen // Treat them as NEON instructions. 299913fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen if ((Domain & ARMII::DomainNEONA8) && Subtarget.isCortexA8()) 30008bb3d3cb30df06bdcb3ef5a208e3e59f4eeb4868Jakob Stoklund Olesen return std::make_pair(ExeNEON, 0); 300113fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen 300213fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen if (Domain & ARMII::DomainVFP) 30038bb3d3cb30df06bdcb3ef5a208e3e59f4eeb4868Jakob Stoklund Olesen return std::make_pair(ExeVFP, 0); 300413fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen 30058bb3d3cb30df06bdcb3ef5a208e3e59f4eeb4868Jakob Stoklund Olesen return std::make_pair(ExeGeneric, 0); 300613fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen} 300713fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen 300813fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesenvoid 300913fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund OlesenARMBaseInstrInfo::setExecutionDomain(MachineInstr *MI, unsigned Domain) const { 301013fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen // We only know how to change VMOVD into VORR. 301113fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen assert(MI->getOpcode() == ARM::VMOVD && "Can only swizzle VMOVD"); 30128bb3d3cb30df06bdcb3ef5a208e3e59f4eeb4868Jakob Stoklund Olesen if (Domain != ExeNEON) 301313fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen return; 301413fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen 30158bb3d3cb30df06bdcb3ef5a208e3e59f4eeb4868Jakob Stoklund Olesen // Zap the predicate operands. 30168bb3d3cb30df06bdcb3ef5a208e3e59f4eeb4868Jakob Stoklund Olesen assert(!isPredicated(MI) && "Cannot predicate a VORRd"); 30178bb3d3cb30df06bdcb3ef5a208e3e59f4eeb4868Jakob Stoklund Olesen MI->RemoveOperand(3); 30188bb3d3cb30df06bdcb3ef5a208e3e59f4eeb4868Jakob Stoklund Olesen MI->RemoveOperand(2); 30198bb3d3cb30df06bdcb3ef5a208e3e59f4eeb4868Jakob Stoklund Olesen 302013fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen // Change to a VORRd which requires two identical use operands. 302113fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen MI->setDesc(get(ARM::VORRd)); 30228bb3d3cb30df06bdcb3ef5a208e3e59f4eeb4868Jakob Stoklund Olesen 30238bb3d3cb30df06bdcb3ef5a208e3e59f4eeb4868Jakob Stoklund Olesen // Add the extra source operand and new predicates. 30248bb3d3cb30df06bdcb3ef5a208e3e59f4eeb4868Jakob Stoklund Olesen // This will go before any implicit ops. 30251c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen AddDefaultPred(MachineInstrBuilder(MI).addOperand(MI->getOperand(1))); 302613fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen} 3027c01810eeb7227010f73cb39e3c4fa0197a3c4ef0Jim Grosbach 3028c01810eeb7227010f73cb39e3c4fa0197a3c4ef0Jim Grosbachbool ARMBaseInstrInfo::hasNOP() const { 3029c01810eeb7227010f73cb39e3c4fa0197a3c4ef0Jim Grosbach return (Subtarget.getFeatureBits() & ARM::HasV6T2Ops) != 0; 3030c01810eeb7227010f73cb39e3c4fa0197a3c4ef0Jim Grosbach} 3031