ARMBaseInstrInfo.cpp revision 8190173350f4e4d916d2307278955b133fba8a00
131c24bf5b39cc8391d4cfdbf8cf5163975fdb81eJim Grosbach//===- ARMBaseInstrInfo.cpp - ARM Instruction Information -------*- C++ -*-===// 2334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// 3334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// The LLVM Compiler Infrastructure 4334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// 5334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// This file is distributed under the University of Illinois Open Source 6334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// License. See LICENSE.TXT for details. 7334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// 8334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin//===----------------------------------------------------------------------===// 9334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// 10334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// This file contains the Base ARM implementation of the TargetInstrInfo class. 11334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// 12334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin//===----------------------------------------------------------------------===// 13334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 14334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "ARMBaseInstrInfo.h" 15334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "ARM.h" 16334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "ARMAddressingModes.h" 17d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng#include "ARMConstantPoolValue.h" 18334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "ARMGenInstrInfo.inc" 19334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "ARMMachineFunctionInfo.h" 20f95215f551949d5e5adfbf4753aa833b9009b77aAnton Korobeynikov#include "ARMRegisterInfo.h" 21fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng#include "llvm/Constants.h" 22fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng#include "llvm/Function.h" 23fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng#include "llvm/GlobalValue.h" 24334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "llvm/ADT/STLExtras.h" 25334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "llvm/CodeGen/LiveVariables.h" 26d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng#include "llvm/CodeGen/MachineConstantPool.h" 27334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "llvm/CodeGen/MachineFrameInfo.h" 28334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "llvm/CodeGen/MachineInstrBuilder.h" 29334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "llvm/CodeGen/MachineJumpTableInfo.h" 30249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov#include "llvm/CodeGen/MachineMemOperand.h" 312457f2c66184e978d4ed8fa9e2128effff26cb0bEvan Cheng#include "llvm/CodeGen/MachineRegisterInfo.h" 32249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov#include "llvm/CodeGen/PseudoSourceValue.h" 33af76e592c7f9deff0e55c13dbb4a34f07f1c7f64Chris Lattner#include "llvm/MC/MCAsmInfo.h" 34334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "llvm/Support/CommandLine.h" 35f95215f551949d5e5adfbf4753aa833b9009b77aAnton Korobeynikov#include "llvm/Support/Debug.h" 36c25e7581b9b8088910da31702d4ca21c4734c6d7Torok Edwin#include "llvm/Support/ErrorHandling.h" 37334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinusing namespace llvm; 38334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 39334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinstatic cl::opt<bool> 40334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinEnableARM3Addr("enable-arm-3-addr-conv", cl::Hidden, 41334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin cl::desc("Enable ARM 2-addr to 3-addr conv")); 42334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 43f95215f551949d5e5adfbf4753aa833b9009b77aAnton KorobeynikovARMBaseInstrInfo::ARMBaseInstrInfo(const ARMSubtarget& STI) 44f95215f551949d5e5adfbf4753aa833b9009b77aAnton Korobeynikov : TargetInstrInfoImpl(ARMInsts, array_lengthof(ARMInsts)), 45f95215f551949d5e5adfbf4753aa833b9009b77aAnton Korobeynikov Subtarget(STI) { 46334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 47334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 48334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinMachineInstr * 49334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinARMBaseInstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI, 50334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineBasicBlock::iterator &MBBI, 51334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin LiveVariables *LV) const { 5278703ddafe3d037f75d8ca188e4829d238289ac3Evan Cheng // FIXME: Thumb2 support. 5378703ddafe3d037f75d8ca188e4829d238289ac3Evan Cheng 54334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (!EnableARM3Addr) 55334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return NULL; 56334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 57334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineInstr *MI = MBBI; 58334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineFunction &MF = *MI->getParent()->getParent(); 5999405df044f2c584242e711cc9023ec90356da82Bruno Cardoso Lopes uint64_t TSFlags = MI->getDesc().TSFlags; 60334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool isPre = false; 61334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin switch ((TSFlags & ARMII::IndexModeMask) >> ARMII::IndexModeShift) { 62334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin default: return NULL; 63334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMII::IndexModePre: 64334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin isPre = true; 65334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin break; 66334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMII::IndexModePost: 67334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin break; 68334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 69334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 70334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Try splitting an indexed load/store to an un-indexed one plus an add/sub 71334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // operation. 72334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned MemOpc = getUnindexedOpcode(MI->getOpcode()); 73334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (MemOpc == 0) 74334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return NULL; 75334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 76334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineInstr *UpdateMI = NULL; 77334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineInstr *MemMI = NULL; 78334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned AddrMode = (TSFlags & ARMII::AddrModeMask); 79334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const TargetInstrDesc &TID = MI->getDesc(); 80334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned NumOps = TID.getNumOperands(); 81334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool isLoad = !TID.mayStore(); 82334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const MachineOperand &WB = isLoad ? MI->getOperand(1) : MI->getOperand(0); 83334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const MachineOperand &Base = MI->getOperand(2); 84334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const MachineOperand &Offset = MI->getOperand(NumOps-3); 85334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned WBReg = WB.getReg(); 86334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned BaseReg = Base.getReg(); 87334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned OffReg = Offset.getReg(); 88334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned OffImm = MI->getOperand(NumOps-2).getImm(); 89334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin ARMCC::CondCodes Pred = (ARMCC::CondCodes)MI->getOperand(NumOps-1).getImm(); 90334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin switch (AddrMode) { 91334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin default: 92334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin assert(false && "Unknown indexed op!"); 93334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return NULL; 94334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMII::AddrMode2: { 95334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool isSub = ARM_AM::getAM2Op(OffImm) == ARM_AM::sub; 96334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned Amt = ARM_AM::getAM2Offset(OffImm); 97334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (OffReg == 0) { 98e7cbe4118b7ddf05032ff8772a98c51e1637bb5cEvan Cheng if (ARM_AM::getSOImmVal(Amt) == -1) 99334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Can't encode it in a so_imm operand. This transformation will 100334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // add more than 1 instruction. Abandon! 101334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return NULL; 102334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin UpdateMI = BuildMI(MF, MI->getDebugLoc(), 10378703ddafe3d037f75d8ca188e4829d238289ac3Evan Cheng get(isSub ? ARM::SUBri : ARM::ADDri), WBReg) 104e7cbe4118b7ddf05032ff8772a98c51e1637bb5cEvan Cheng .addReg(BaseReg).addImm(Amt) 105334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addImm(Pred).addReg(0).addReg(0); 106334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } else if (Amt != 0) { 107334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin ARM_AM::ShiftOpc ShOpc = ARM_AM::getAM2ShiftOpc(OffImm); 108334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned SOOpc = ARM_AM::getSORegOpc(ShOpc, Amt); 109334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin UpdateMI = BuildMI(MF, MI->getDebugLoc(), 11078703ddafe3d037f75d8ca188e4829d238289ac3Evan Cheng get(isSub ? ARM::SUBrs : ARM::ADDrs), WBReg) 111334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(BaseReg).addReg(OffReg).addReg(0).addImm(SOOpc) 112334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addImm(Pred).addReg(0).addReg(0); 113334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } else 114334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin UpdateMI = BuildMI(MF, MI->getDebugLoc(), 11578703ddafe3d037f75d8ca188e4829d238289ac3Evan Cheng get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg) 116334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(BaseReg).addReg(OffReg) 117334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addImm(Pred).addReg(0).addReg(0); 118334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin break; 119334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 120334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMII::AddrMode3 : { 121334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool isSub = ARM_AM::getAM3Op(OffImm) == ARM_AM::sub; 122334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned Amt = ARM_AM::getAM3Offset(OffImm); 123334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (OffReg == 0) 124334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Immediate is 8-bits. It's guaranteed to fit in a so_imm operand. 125334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin UpdateMI = BuildMI(MF, MI->getDebugLoc(), 12678703ddafe3d037f75d8ca188e4829d238289ac3Evan Cheng get(isSub ? ARM::SUBri : ARM::ADDri), WBReg) 127334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(BaseReg).addImm(Amt) 128334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addImm(Pred).addReg(0).addReg(0); 129334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin else 130334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin UpdateMI = BuildMI(MF, MI->getDebugLoc(), 13178703ddafe3d037f75d8ca188e4829d238289ac3Evan Cheng get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg) 132334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(BaseReg).addReg(OffReg) 133334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addImm(Pred).addReg(0).addReg(0); 134334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin break; 135334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 136334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 137334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 138334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin std::vector<MachineInstr*> NewMIs; 139334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (isPre) { 140334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (isLoad) 141334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MemMI = BuildMI(MF, MI->getDebugLoc(), 142334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin get(MemOpc), MI->getOperand(0).getReg()) 143334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(WBReg).addReg(0).addImm(0).addImm(Pred); 144334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin else 145334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MemMI = BuildMI(MF, MI->getDebugLoc(), 146334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin get(MemOpc)).addReg(MI->getOperand(1).getReg()) 147334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(WBReg).addReg(0).addImm(0).addImm(Pred); 148334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin NewMIs.push_back(MemMI); 149334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin NewMIs.push_back(UpdateMI); 150334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } else { 151334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (isLoad) 152334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MemMI = BuildMI(MF, MI->getDebugLoc(), 153334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin get(MemOpc), MI->getOperand(0).getReg()) 154334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred); 155334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin else 156334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MemMI = BuildMI(MF, MI->getDebugLoc(), 157334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin get(MemOpc)).addReg(MI->getOperand(1).getReg()) 158334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred); 159334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (WB.isDead()) 160334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin UpdateMI->getOperand(0).setIsDead(); 161334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin NewMIs.push_back(UpdateMI); 162334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin NewMIs.push_back(MemMI); 163334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 164334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 165334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Transfer LiveVariables states, kill / dead info. 166334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (LV) { 167334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 168334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineOperand &MO = MI->getOperand(i); 169334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (MO.isReg() && MO.getReg() && 170334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin TargetRegisterInfo::isVirtualRegister(MO.getReg())) { 171334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned Reg = MO.getReg(); 172334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 173334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin LiveVariables::VarInfo &VI = LV->getVarInfo(Reg); 174334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (MO.isDef()) { 175334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineInstr *NewMI = (Reg == WBReg) ? UpdateMI : MemMI; 176334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (MO.isDead()) 177334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin LV->addVirtualRegisterDead(Reg, NewMI); 178334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 179334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (MO.isUse() && MO.isKill()) { 180334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin for (unsigned j = 0; j < 2; ++j) { 181334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Look at the two new MI's in reverse order. 182334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineInstr *NewMI = NewMIs[j]; 183334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (!NewMI->readsRegister(Reg)) 184334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin continue; 185334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin LV->addVirtualRegisterKilled(Reg, NewMI); 186334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (VI.removeKill(MI)) 187334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin VI.Kills.push_back(NewMI); 188334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin break; 189334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 190334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 191334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 192334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 193334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 194334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 195334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MFI->insert(MBBI, NewMIs[1]); 196334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MFI->insert(MBBI, NewMIs[0]); 197334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return NewMIs[0]; 198334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 199334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 2002457f2c66184e978d4ed8fa9e2128effff26cb0bEvan Chengbool 2012457f2c66184e978d4ed8fa9e2128effff26cb0bEvan ChengARMBaseInstrInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB, 20218f30e6f5e80787808fe1455742452a5210afe07Jim Grosbach MachineBasicBlock::iterator MI, 20318f30e6f5e80787808fe1455742452a5210afe07Jim Grosbach const std::vector<CalleeSavedInfo> &CSI, 20418f30e6f5e80787808fe1455742452a5210afe07Jim Grosbach const TargetRegisterInfo *TRI) const { 2052457f2c66184e978d4ed8fa9e2128effff26cb0bEvan Cheng if (CSI.empty()) 2062457f2c66184e978d4ed8fa9e2128effff26cb0bEvan Cheng return false; 2072457f2c66184e978d4ed8fa9e2128effff26cb0bEvan Cheng 2082457f2c66184e978d4ed8fa9e2128effff26cb0bEvan Cheng DebugLoc DL; 2092457f2c66184e978d4ed8fa9e2128effff26cb0bEvan Cheng if (MI != MBB.end()) DL = MI->getDebugLoc(); 2102457f2c66184e978d4ed8fa9e2128effff26cb0bEvan Cheng 2112457f2c66184e978d4ed8fa9e2128effff26cb0bEvan Cheng for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 2122457f2c66184e978d4ed8fa9e2128effff26cb0bEvan Cheng unsigned Reg = CSI[i].getReg(); 2132457f2c66184e978d4ed8fa9e2128effff26cb0bEvan Cheng bool isKill = true; 2142457f2c66184e978d4ed8fa9e2128effff26cb0bEvan Cheng 2152457f2c66184e978d4ed8fa9e2128effff26cb0bEvan Cheng // Add the callee-saved register as live-in unless it's LR and 2162457f2c66184e978d4ed8fa9e2128effff26cb0bEvan Cheng // @llvm.returnaddress is called. If LR is returned for @llvm.returnaddress 2172457f2c66184e978d4ed8fa9e2128effff26cb0bEvan Cheng // then it's already added to the function and entry block live-in sets. 2182457f2c66184e978d4ed8fa9e2128effff26cb0bEvan Cheng if (Reg == ARM::LR) { 2192457f2c66184e978d4ed8fa9e2128effff26cb0bEvan Cheng MachineFunction &MF = *MBB.getParent(); 2202457f2c66184e978d4ed8fa9e2128effff26cb0bEvan Cheng if (MF.getFrameInfo()->isReturnAddressTaken() && 2212457f2c66184e978d4ed8fa9e2128effff26cb0bEvan Cheng MF.getRegInfo().isLiveIn(Reg)) 2222457f2c66184e978d4ed8fa9e2128effff26cb0bEvan Cheng isKill = false; 2232457f2c66184e978d4ed8fa9e2128effff26cb0bEvan Cheng } 2242457f2c66184e978d4ed8fa9e2128effff26cb0bEvan Cheng 2252457f2c66184e978d4ed8fa9e2128effff26cb0bEvan Cheng if (isKill) 2262457f2c66184e978d4ed8fa9e2128effff26cb0bEvan Cheng MBB.addLiveIn(Reg); 2272457f2c66184e978d4ed8fa9e2128effff26cb0bEvan Cheng 2282457f2c66184e978d4ed8fa9e2128effff26cb0bEvan Cheng // Insert the spill to the stack frame. The register is killed at the spill 2292457f2c66184e978d4ed8fa9e2128effff26cb0bEvan Cheng // 23042d075c4fb21995265961501cec9ff6e3fb497ceRafael Espindola const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); 2312457f2c66184e978d4ed8fa9e2128effff26cb0bEvan Cheng storeRegToStackSlot(MBB, MI, Reg, isKill, 23242d075c4fb21995265961501cec9ff6e3fb497ceRafael Espindola CSI[i].getFrameIdx(), RC, TRI); 2332457f2c66184e978d4ed8fa9e2128effff26cb0bEvan Cheng } 2342457f2c66184e978d4ed8fa9e2128effff26cb0bEvan Cheng return true; 2352457f2c66184e978d4ed8fa9e2128effff26cb0bEvan Cheng} 2362457f2c66184e978d4ed8fa9e2128effff26cb0bEvan Cheng 237334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// Branch analysis. 238334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinbool 239334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinARMBaseInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB, 240334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineBasicBlock *&FBB, 241334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin SmallVectorImpl<MachineOperand> &Cond, 242334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool AllowModify) const { 243334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // If the block has no terminators, it just falls into the block after it. 244334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineBasicBlock::iterator I = MBB.end(); 24593d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen if (I == MBB.begin()) 24693d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen return false; 24793d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen --I; 24893d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen while (I->isDebugValue()) { 24993d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen if (I == MBB.begin()) 25093d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen return false; 25193d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen --I; 25293d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen } 25393d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen if (!isUnpredicatedTerminator(I)) 254334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 255334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 256334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Get the last instruction in the block. 257334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineInstr *LastInst = I; 258334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 259334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // If there is only one terminator instruction, process it. 260334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned LastOpc = LastInst->getOpcode(); 261334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) { 2625ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng if (isUncondBranchOpcode(LastOpc)) { 263334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin TBB = LastInst->getOperand(0).getMBB(); 264334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 265334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 2665ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng if (isCondBranchOpcode(LastOpc)) { 267334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Block ends with fall-through condbranch. 268334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin TBB = LastInst->getOperand(0).getMBB(); 269334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin Cond.push_back(LastInst->getOperand(1)); 270334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin Cond.push_back(LastInst->getOperand(2)); 271334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 272334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 273334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; // Can't handle indirect branch. 274334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 275334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 276334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Get the instruction before it if it is a terminator. 277334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineInstr *SecondLastInst = I; 278334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 279334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // If there are three terminators, we don't know what sort of block this is. 280334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(--I)) 281334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; 282334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 2835ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng // If the block ends with a B and a Bcc, handle it. 284334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned SecondLastOpc = SecondLastInst->getOpcode(); 2855ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng if (isCondBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) { 286334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin TBB = SecondLastInst->getOperand(0).getMBB(); 287334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin Cond.push_back(SecondLastInst->getOperand(1)); 288334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin Cond.push_back(SecondLastInst->getOperand(2)); 289334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin FBB = LastInst->getOperand(0).getMBB(); 290334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 291334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 292334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 293334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // If the block ends with two unconditional branches, handle it. The second 294334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // one is not executed, so remove it. 2955ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng if (isUncondBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) { 296334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin TBB = SecondLastInst->getOperand(0).getMBB(); 297334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin I = LastInst; 298334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (AllowModify) 299334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin I->eraseFromParent(); 300334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 301334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 302334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 303334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // ...likewise if it ends with a branch table followed by an unconditional 304334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // branch. The branch folder can create these, and we must get rid of them for 305334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // correctness of Thumb constant islands. 3068d4de5abfa1bcd974554ea14904ebf7af289e84dBob Wilson if ((isJumpTableBranchOpcode(SecondLastOpc) || 3078d4de5abfa1bcd974554ea14904ebf7af289e84dBob Wilson isIndirectBranchOpcode(SecondLastOpc)) && 3085ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng isUncondBranchOpcode(LastOpc)) { 309334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin I = LastInst; 310334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (AllowModify) 311334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin I->eraseFromParent(); 312334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; 313334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 314334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 315334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Otherwise, can't handle this. 316334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; 317334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 318334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 319334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 320334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinunsigned ARMBaseInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const { 321334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineBasicBlock::iterator I = MBB.end(); 322334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (I == MBB.begin()) return 0; 323334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin --I; 32493d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen while (I->isDebugValue()) { 32593d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen if (I == MBB.begin()) 32693d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen return 0; 32793d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen --I; 32893d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen } 3295ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng if (!isUncondBranchOpcode(I->getOpcode()) && 3305ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng !isCondBranchOpcode(I->getOpcode())) 331334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 0; 332334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 333334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Remove the branch. 334334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin I->eraseFromParent(); 335334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 336334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin I = MBB.end(); 337334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 338334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (I == MBB.begin()) return 1; 339334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin --I; 3405ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng if (!isCondBranchOpcode(I->getOpcode())) 341334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 1; 342334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 343334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Remove the branch. 344334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin I->eraseFromParent(); 345334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 2; 346334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 347334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 348334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinunsigned 349334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinARMBaseInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 3503bf912593301152b65accb9d9c37a95172f1df5aStuart Hastings MachineBasicBlock *FBB, 3513bf912593301152b65accb9d9c37a95172f1df5aStuart Hastings const SmallVectorImpl<MachineOperand> &Cond, 3523bf912593301152b65accb9d9c37a95172f1df5aStuart Hastings DebugLoc DL) const { 3536495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ARMFunctionInfo *AFI = MBB.getParent()->getInfo<ARMFunctionInfo>(); 3546495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng int BOpc = !AFI->isThumbFunction() 3556495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ? ARM::B : (AFI->isThumb2Function() ? ARM::t2B : ARM::tB); 3566495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng int BccOpc = !AFI->isThumbFunction() 3576495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ? ARM::Bcc : (AFI->isThumb2Function() ? ARM::t2Bcc : ARM::tBcc); 358334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 359334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Shouldn't be a fall through. 360334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin assert(TBB && "InsertBranch must not be told to insert a fallthrough"); 361334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin assert((Cond.size() == 2 || Cond.size() == 0) && 362334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin "ARM branch conditions have two components!"); 363334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 364334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (FBB == 0) { 365334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (Cond.empty()) // Unconditional branch? 3663bf912593301152b65accb9d9c37a95172f1df5aStuart Hastings BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB); 367334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin else 3683bf912593301152b65accb9d9c37a95172f1df5aStuart Hastings BuildMI(&MBB, DL, get(BccOpc)).addMBB(TBB) 369334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()); 370334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 1; 371334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 372334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 373334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Two-way conditional branch. 3743bf912593301152b65accb9d9c37a95172f1df5aStuart Hastings BuildMI(&MBB, DL, get(BccOpc)).addMBB(TBB) 375334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()); 3763bf912593301152b65accb9d9c37a95172f1df5aStuart Hastings BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB); 377334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 2; 378334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 379334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 380334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinbool ARMBaseInstrInfo:: 381334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const { 382334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin ARMCC::CondCodes CC = (ARMCC::CondCodes)(int)Cond[0].getImm(); 383334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin Cond[0].setImm(ARMCC::getOppositeCondition(CC)); 384334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 385334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 386334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 387334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinbool ARMBaseInstrInfo:: 388334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinPredicateInstruction(MachineInstr *MI, 389334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const SmallVectorImpl<MachineOperand> &Pred) const { 390334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned Opc = MI->getOpcode(); 3915ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng if (isUncondBranchOpcode(Opc)) { 3925ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng MI->setDesc(get(getMatchingCondBranchOpcode(Opc))); 393334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI->addOperand(MachineOperand::CreateImm(Pred[0].getImm())); 394334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI->addOperand(MachineOperand::CreateReg(Pred[1].getReg(), false)); 395334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; 396334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 397334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 398334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin int PIdx = MI->findFirstPredOperandIdx(); 399334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (PIdx != -1) { 400334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineOperand &PMO = MI->getOperand(PIdx); 401334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin PMO.setImm(Pred[0].getImm()); 402334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI->getOperand(PIdx+1).setReg(Pred[1].getReg()); 403334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; 404334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 405334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 406334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 407334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 408334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinbool ARMBaseInstrInfo:: 409334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinSubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1, 410334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const SmallVectorImpl<MachineOperand> &Pred2) const { 411334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (Pred1.size() > 2 || Pred2.size() > 2) 412334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 413334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 414334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin ARMCC::CondCodes CC1 = (ARMCC::CondCodes)Pred1[0].getImm(); 415334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin ARMCC::CondCodes CC2 = (ARMCC::CondCodes)Pred2[0].getImm(); 416334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (CC1 == CC2) 417334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; 418334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 419334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin switch (CC1) { 420334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin default: 421334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 422334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMCC::AL: 423334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; 424334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMCC::HS: 425334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return CC2 == ARMCC::HI; 426334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMCC::LS: 427334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return CC2 == ARMCC::LO || CC2 == ARMCC::EQ; 428334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMCC::GE: 429334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return CC2 == ARMCC::GT; 430334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMCC::LE: 431334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return CC2 == ARMCC::LT; 432334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 433334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 434334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 435334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinbool ARMBaseInstrInfo::DefinesPredicate(MachineInstr *MI, 436334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin std::vector<MachineOperand> &Pred) const { 4378fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng // FIXME: This confuses implicit_def with optional CPSR def. 438334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const TargetInstrDesc &TID = MI->getDesc(); 439334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (!TID.getImplicitDefs() && !TID.hasOptionalDef()) 440334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 441334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 442334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool Found = false; 443334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 444334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const MachineOperand &MO = MI->getOperand(i); 445334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (MO.isReg() && MO.getReg() == ARM::CPSR) { 446334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin Pred.push_back(MO); 447334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin Found = true; 448334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 449334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 450334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 451334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return Found; 452334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 453334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 454ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng/// isPredicable - Return true if the specified instruction can be predicated. 455ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng/// By default, this returns true for every instruction with a 456ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng/// PredicateOperand. 457ac0869dc8a7986855c5557cc67d4709600158ef5Evan Chengbool ARMBaseInstrInfo::isPredicable(MachineInstr *MI) const { 458ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng const TargetInstrDesc &TID = MI->getDesc(); 459ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng if (!TID.isPredicable()) 460ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng return false; 461ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng 462ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng if ((TID.TSFlags & ARMII::DomainMask) == ARMII::DomainNEON) { 463ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng ARMFunctionInfo *AFI = 464ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng MI->getParent()->getParent()->getInfo<ARMFunctionInfo>(); 465d7f0810c934a7d13acb28c42d737ce58ec990ea8Evan Cheng return AFI->isThumb2Function(); 466ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng } 467ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng return true; 468ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng} 469334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 47056856b1f46ec1f073ceef4e826c544b8b1691608Chris Lattner/// FIXME: Works around a gcc miscompilation with -fstrict-aliasing. 47156856b1f46ec1f073ceef4e826c544b8b1691608Chris LattnerDISABLE_INLINE 472334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinstatic unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT, 47356856b1f46ec1f073ceef4e826c544b8b1691608Chris Lattner unsigned JTI); 474334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinstatic unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT, 475334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned JTI) { 47656856b1f46ec1f073ceef4e826c544b8b1691608Chris Lattner assert(JTI < JT.size()); 477334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return JT[JTI].MBBs.size(); 478334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 479334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 480334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin/// GetInstSize - Return the size of the specified MachineInstr. 481334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin/// 482334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinunsigned ARMBaseInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const { 483334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const MachineBasicBlock &MBB = *MI->getParent(); 484334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const MachineFunction *MF = MBB.getParent(); 48533adcfb4d217f5f23d9bde8ba02b8e48f9605fc5Chris Lattner const MCAsmInfo *MAI = MF->getTarget().getMCAsmInfo(); 486334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 487334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Basic size info comes from the TSFlags field. 488334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const TargetInstrDesc &TID = MI->getDesc(); 48999405df044f2c584242e711cc9023ec90356da82Bruno Cardoso Lopes uint64_t TSFlags = TID.TSFlags; 490334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 491a0ee862f2e3a0d202244e02459ddcf0dca0e8607Evan Cheng unsigned Opc = MI->getOpcode(); 492334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin switch ((TSFlags & ARMII::SizeMask) >> ARMII::SizeShift) { 493334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin default: { 494334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // If this machine instr is an inline asm, measure it. 495334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (MI->getOpcode() == ARM::INLINEASM) 49633adcfb4d217f5f23d9bde8ba02b8e48f9605fc5Chris Lattner return getInlineAsmLength(MI->getOperand(0).getSymbolName(), *MAI); 497334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (MI->isLabel()) 498334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 0; 499a0ee862f2e3a0d202244e02459ddcf0dca0e8607Evan Cheng switch (Opc) { 500334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin default: 501c23197a26f34f559ea9797de51e187087c039c42Torok Edwin llvm_unreachable("Unknown or unset size field for instr!"); 502518bb53485df640d7b7e3f6b0544099020c42aa7Chris Lattner case TargetOpcode::IMPLICIT_DEF: 503518bb53485df640d7b7e3f6b0544099020c42aa7Chris Lattner case TargetOpcode::KILL: 504518bb53485df640d7b7e3f6b0544099020c42aa7Chris Lattner case TargetOpcode::DBG_LABEL: 505518bb53485df640d7b7e3f6b0544099020c42aa7Chris Lattner case TargetOpcode::EH_LABEL: 506375be7730a6f3dee7a6dc319ee6c355a11ac99adDale Johannesen case TargetOpcode::DBG_VALUE: 507334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 0; 508334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 509334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin break; 510334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 511789476240d6b6f8ad9366cadf790a82bd41bb0b3Evan Cheng case ARMII::Size8Bytes: return 8; // ARM instruction x 2. 512789476240d6b6f8ad9366cadf790a82bd41bb0b3Evan Cheng case ARMII::Size4Bytes: return 4; // ARM / Thumb2 instruction. 513789476240d6b6f8ad9366cadf790a82bd41bb0b3Evan Cheng case ARMII::Size2Bytes: return 2; // Thumb1 instruction. 514334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMII::SizeSpecial: { 515a0ee862f2e3a0d202244e02459ddcf0dca0e8607Evan Cheng switch (Opc) { 516334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARM::CONSTPOOL_ENTRY: 517334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // If this machine instr is a constant pool entry, its size is recorded as 518334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // operand #2. 519334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return MI->getOperand(2).getImm(); 5205eb195153950bc7ebfc30649494a78b2096b5ef8Jim Grosbach case ARM::Int_eh_sjlj_longjmp: 5215eb195153950bc7ebfc30649494a78b2096b5ef8Jim Grosbach return 16; 5225eb195153950bc7ebfc30649494a78b2096b5ef8Jim Grosbach case ARM::tInt_eh_sjlj_longjmp: 5235eb195153950bc7ebfc30649494a78b2096b5ef8Jim Grosbach return 10; 524789476240d6b6f8ad9366cadf790a82bd41bb0b3Evan Cheng case ARM::Int_eh_sjlj_setjmp: 525d100755bab38784703f677b8b8eb174b624b346bJim Grosbach case ARM::Int_eh_sjlj_setjmp_nofp: 5260798eddd07b8dc827a4e6e9028c4c3a8d9444286Jim Grosbach return 20; 527d122874996a6faa8832569b632fd73a32ace7ae7Jim Grosbach case ARM::tInt_eh_sjlj_setjmp: 5285aa1684e5da9a85286bf7d29da419d261a70c2f2Jim Grosbach case ARM::t2Int_eh_sjlj_setjmp: 529d100755bab38784703f677b8b8eb174b624b346bJim Grosbach case ARM::t2Int_eh_sjlj_setjmp_nofp: 5300798eddd07b8dc827a4e6e9028c4c3a8d9444286Jim Grosbach return 12; 531334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARM::BR_JTr: 532334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARM::BR_JTm: 533334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARM::BR_JTadd: 534a0ee862f2e3a0d202244e02459ddcf0dca0e8607Evan Cheng case ARM::tBR_JTr: 535d26b14c34cbcee1448b86b524578fc51cc979023Evan Cheng case ARM::t2BR_JT: 536d26b14c34cbcee1448b86b524578fc51cc979023Evan Cheng case ARM::t2TBB: 537d26b14c34cbcee1448b86b524578fc51cc979023Evan Cheng case ARM::t2TBH: { 538334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // These are jumptable branches, i.e. a branch followed by an inlined 539d26b14c34cbcee1448b86b524578fc51cc979023Evan Cheng // jumptable. The size is 4 + 4 * number of entries. For TBB, each 540d26b14c34cbcee1448b86b524578fc51cc979023Evan Cheng // entry is one byte; TBH two byte each. 541a0ee862f2e3a0d202244e02459ddcf0dca0e8607Evan Cheng unsigned EntrySize = (Opc == ARM::t2TBB) 542a0ee862f2e3a0d202244e02459ddcf0dca0e8607Evan Cheng ? 1 : ((Opc == ARM::t2TBH) ? 2 : 4); 543334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned NumOps = TID.getNumOperands(); 544334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineOperand JTOP = 545334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI->getOperand(NumOps - (TID.isPredicable() ? 3 : 2)); 546334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned JTI = JTOP.getIndex(); 547334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo(); 548b1e803985d3378538ae9cff7eed4102c002d1e22Chris Lattner assert(MJTI != 0); 549334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables(); 550334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin assert(JTI < JT.size()); 551334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Thumb instructions are 2 byte aligned, but JT entries are 4 byte 552334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // 4 aligned. The assembler / linker may add 2 byte padding just before 553334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // the JT entries. The size does not include this padding; the 554334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // constant islands pass does separate bookkeeping for it. 555334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // FIXME: If we know the size of the function is less than (1 << 16) *2 556334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // bytes, we can use 16-bit entries instead. Then there won't be an 557334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // alignment issue. 55825f7cfc3cccba6f569f29f79ea533bae960b93c0Evan Cheng unsigned InstSize = (Opc == ARM::tBR_JTr || Opc == ARM::t2BR_JT) ? 2 : 4; 55925f7cfc3cccba6f569f29f79ea533bae960b93c0Evan Cheng unsigned NumEntries = getNumJTEntries(JT, JTI); 56025f7cfc3cccba6f569f29f79ea533bae960b93c0Evan Cheng if (Opc == ARM::t2TBB && (NumEntries & 1)) 56125f7cfc3cccba6f569f29f79ea533bae960b93c0Evan Cheng // Make sure the instruction that follows TBB is 2-byte aligned. 56225f7cfc3cccba6f569f29f79ea533bae960b93c0Evan Cheng // FIXME: Constant island pass should insert an "ALIGN" instruction 56325f7cfc3cccba6f569f29f79ea533bae960b93c0Evan Cheng // instead. 56425f7cfc3cccba6f569f29f79ea533bae960b93c0Evan Cheng ++NumEntries; 56525f7cfc3cccba6f569f29f79ea533bae960b93c0Evan Cheng return NumEntries * EntrySize + InstSize; 566334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 567334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin default: 568334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Otherwise, pseudo-instruction sizes are zero. 569334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 0; 570334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 571334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 572334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 573334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 0; // Not reached 574334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 575334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 576334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin/// Return true if the instruction is a register to register move and 577334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin/// leave the source and dest operands in the passed parameters. 578334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin/// 579334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinbool 580334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinARMBaseInstrInfo::isMoveInstr(const MachineInstr &MI, 581334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned &SrcReg, unsigned &DstReg, 582334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned& SrcSubIdx, unsigned& DstSubIdx) const { 58368e3c6ae49ff67cba98403e43b5bd0c2499caa41Evan Cheng switch (MI.getOpcode()) { 584dced03fc846fa7cd9558ecb8e33ca98ec29bdcf0Evan Cheng default: break; 585e5165490b7ba24bb2f3043399e0d60e7f3bcf8a5Jim Grosbach case ARM::VMOVS: 58668e3c6ae49ff67cba98403e43b5bd0c2499caa41Evan Cheng case ARM::VMOVD: 587e5165490b7ba24bb2f3043399e0d60e7f3bcf8a5Jim Grosbach case ARM::VMOVDneon: 588b63387afc6b10e88631d1ef232c41ab6c18c8581Evan Cheng case ARM::VMOVQ: 589b63387afc6b10e88631d1ef232c41ab6c18c8581Evan Cheng case ARM::VMOVQQ : { 590334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin SrcReg = MI.getOperand(1).getReg(); 591334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin DstReg = MI.getOperand(0).getReg(); 592b63387afc6b10e88631d1ef232c41ab6c18c8581Evan Cheng SrcSubIdx = MI.getOperand(1).getSubReg(); 593b63387afc6b10e88631d1ef232c41ab6c18c8581Evan Cheng DstSubIdx = MI.getOperand(0).getSubReg(); 594334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; 595334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 59668e3c6ae49ff67cba98403e43b5bd0c2499caa41Evan Cheng case ARM::MOVr: 5976470a116f17b70aba0c2e7ee751551a5ac9797f6Dale Johannesen case ARM::MOVr_TC: 59868e3c6ae49ff67cba98403e43b5bd0c2499caa41Evan Cheng case ARM::tMOVr: 59968e3c6ae49ff67cba98403e43b5bd0c2499caa41Evan Cheng case ARM::tMOVgpr2tgpr: 60068e3c6ae49ff67cba98403e43b5bd0c2499caa41Evan Cheng case ARM::tMOVtgpr2gpr: 60168e3c6ae49ff67cba98403e43b5bd0c2499caa41Evan Cheng case ARM::tMOVgpr2gpr: 60268e3c6ae49ff67cba98403e43b5bd0c2499caa41Evan Cheng case ARM::t2MOVr: { 603334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin assert(MI.getDesc().getNumOperands() >= 2 && 604334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI.getOperand(0).isReg() && 605334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI.getOperand(1).isReg() && 606334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin "Invalid ARM MOV instruction"); 607334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin SrcReg = MI.getOperand(1).getReg(); 608334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin DstReg = MI.getOperand(0).getReg(); 609b63387afc6b10e88631d1ef232c41ab6c18c8581Evan Cheng SrcSubIdx = MI.getOperand(1).getSubReg(); 610b63387afc6b10e88631d1ef232c41ab6c18c8581Evan Cheng DstSubIdx = MI.getOperand(0).getSubReg(); 611334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; 612334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 61368e3c6ae49ff67cba98403e43b5bd0c2499caa41Evan Cheng } 614334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 615334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 616334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 617334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 618764ab52dd80310a205c9888bf166d09dab858f90Jim Grosbachunsigned 619334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinARMBaseInstrInfo::isLoadFromStackSlot(const MachineInstr *MI, 620334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin int &FrameIndex) const { 621dced03fc846fa7cd9558ecb8e33ca98ec29bdcf0Evan Cheng switch (MI->getOpcode()) { 622dced03fc846fa7cd9558ecb8e33ca98ec29bdcf0Evan Cheng default: break; 623dced03fc846fa7cd9558ecb8e33ca98ec29bdcf0Evan Cheng case ARM::LDR: 624dced03fc846fa7cd9558ecb8e33ca98ec29bdcf0Evan Cheng case ARM::t2LDRs: // FIXME: don't use t2LDRs to access frame. 625334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (MI->getOperand(1).isFI() && 626334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI->getOperand(2).isReg() && 627334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI->getOperand(3).isImm() && 628334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI->getOperand(2).getReg() == 0 && 629334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI->getOperand(3).getImm() == 0) { 630334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin FrameIndex = MI->getOperand(1).getIndex(); 631334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return MI->getOperand(0).getReg(); 632334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 633dced03fc846fa7cd9558ecb8e33ca98ec29bdcf0Evan Cheng break; 634dced03fc846fa7cd9558ecb8e33ca98ec29bdcf0Evan Cheng case ARM::t2LDRi12: 635dced03fc846fa7cd9558ecb8e33ca98ec29bdcf0Evan Cheng case ARM::tRestore: 6365ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin if (MI->getOperand(1).isFI() && 6375ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin MI->getOperand(2).isImm() && 6385ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin MI->getOperand(2).getImm() == 0) { 6395ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin FrameIndex = MI->getOperand(1).getIndex(); 6405ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin return MI->getOperand(0).getReg(); 6415ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin } 642dced03fc846fa7cd9558ecb8e33ca98ec29bdcf0Evan Cheng break; 643e5165490b7ba24bb2f3043399e0d60e7f3bcf8a5Jim Grosbach case ARM::VLDRD: 644e5165490b7ba24bb2f3043399e0d60e7f3bcf8a5Jim Grosbach case ARM::VLDRS: 645334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (MI->getOperand(1).isFI() && 646334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI->getOperand(2).isImm() && 647334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI->getOperand(2).getImm() == 0) { 648334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin FrameIndex = MI->getOperand(1).getIndex(); 649334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return MI->getOperand(0).getReg(); 650334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 651dced03fc846fa7cd9558ecb8e33ca98ec29bdcf0Evan Cheng break; 652334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 653334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 654334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 0; 655334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 656334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 657334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinunsigned 658334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinARMBaseInstrInfo::isStoreToStackSlot(const MachineInstr *MI, 659334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin int &FrameIndex) const { 660dced03fc846fa7cd9558ecb8e33ca98ec29bdcf0Evan Cheng switch (MI->getOpcode()) { 661dced03fc846fa7cd9558ecb8e33ca98ec29bdcf0Evan Cheng default: break; 662dced03fc846fa7cd9558ecb8e33ca98ec29bdcf0Evan Cheng case ARM::STR: 663dced03fc846fa7cd9558ecb8e33ca98ec29bdcf0Evan Cheng case ARM::t2STRs: // FIXME: don't use t2STRs to access frame. 664334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (MI->getOperand(1).isFI() && 665334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI->getOperand(2).isReg() && 666334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI->getOperand(3).isImm() && 667334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI->getOperand(2).getReg() == 0 && 668334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI->getOperand(3).getImm() == 0) { 669334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin FrameIndex = MI->getOperand(1).getIndex(); 670334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return MI->getOperand(0).getReg(); 671334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 672dced03fc846fa7cd9558ecb8e33ca98ec29bdcf0Evan Cheng break; 673dced03fc846fa7cd9558ecb8e33ca98ec29bdcf0Evan Cheng case ARM::t2STRi12: 674dced03fc846fa7cd9558ecb8e33ca98ec29bdcf0Evan Cheng case ARM::tSpill: 6755ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin if (MI->getOperand(1).isFI() && 6765ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin MI->getOperand(2).isImm() && 6775ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin MI->getOperand(2).getImm() == 0) { 6785ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin FrameIndex = MI->getOperand(1).getIndex(); 6795ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin return MI->getOperand(0).getReg(); 6805ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin } 681dced03fc846fa7cd9558ecb8e33ca98ec29bdcf0Evan Cheng break; 682e5165490b7ba24bb2f3043399e0d60e7f3bcf8a5Jim Grosbach case ARM::VSTRD: 683e5165490b7ba24bb2f3043399e0d60e7f3bcf8a5Jim Grosbach case ARM::VSTRS: 684334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (MI->getOperand(1).isFI() && 685334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI->getOperand(2).isImm() && 686334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI->getOperand(2).getImm() == 0) { 687334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin FrameIndex = MI->getOperand(1).getIndex(); 688334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return MI->getOperand(0).getReg(); 689334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 690dced03fc846fa7cd9558ecb8e33ca98ec29bdcf0Evan Cheng break; 691334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 692334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 693334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 0; 694334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 695334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 696334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinbool 697334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinARMBaseInstrInfo::copyRegToReg(MachineBasicBlock &MBB, 698334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineBasicBlock::iterator I, 699334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned DestReg, unsigned SrcReg, 700334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const TargetRegisterClass *DestRC, 70134dcc6fadca0a1117cdbd0e9b35c991a55b6e556Dan Gohman const TargetRegisterClass *SrcRC, 70234dcc6fadca0a1117cdbd0e9b35c991a55b6e556Dan Gohman DebugLoc DL) const { 7036470a116f17b70aba0c2e7ee751551a5ac9797f6Dale Johannesen // tGPR or tcGPR is used sometimes in ARM instructions that need to avoid 7046470a116f17b70aba0c2e7ee751551a5ac9797f6Dale Johannesen // using certain registers. Just treat them as GPR here. 7056470a116f17b70aba0c2e7ee751551a5ac9797f6Dale Johannesen if (DestRC == ARM::tGPRRegisterClass || DestRC == ARM::tcGPRRegisterClass) 7061665b0a2246c83a2c123be105a1a167cf2b423feBob Wilson DestRC = ARM::GPRRegisterClass; 7076470a116f17b70aba0c2e7ee751551a5ac9797f6Dale Johannesen if (SrcRC == ARM::tGPRRegisterClass || SrcRC == ARM::tcGPRRegisterClass) 7081665b0a2246c83a2c123be105a1a167cf2b423feBob Wilson SrcRC = ARM::GPRRegisterClass; 7091665b0a2246c83a2c123be105a1a167cf2b423feBob Wilson 710d31f972bd33de85071c716f69bf5c6d735f730f2Rafael Espindola if (DestRC == ARM::SPR_8RegisterClass) 711d31f972bd33de85071c716f69bf5c6d735f730f2Rafael Espindola DestRC = ARM::SPRRegisterClass; 712d31f972bd33de85071c716f69bf5c6d735f730f2Rafael Espindola if (SrcRC == ARM::SPR_8RegisterClass) 713d31f972bd33de85071c716f69bf5c6d735f730f2Rafael Espindola SrcRC = ARM::SPRRegisterClass; 714d31f972bd33de85071c716f69bf5c6d735f730f2Rafael Espindola 7156755d97a62fd6796f4146833efb1051fc96a61c0Anton Korobeynikov // Allow DPR / DPR_VFP2 / DPR_8 cross-class copies. 7166755d97a62fd6796f4146833efb1051fc96a61c0Anton Korobeynikov if (DestRC == ARM::DPR_8RegisterClass) 7176755d97a62fd6796f4146833efb1051fc96a61c0Anton Korobeynikov DestRC = ARM::DPR_VFP2RegisterClass; 7186755d97a62fd6796f4146833efb1051fc96a61c0Anton Korobeynikov if (SrcRC == ARM::DPR_8RegisterClass) 7196755d97a62fd6796f4146833efb1051fc96a61c0Anton Korobeynikov SrcRC = ARM::DPR_VFP2RegisterClass; 7206755d97a62fd6796f4146833efb1051fc96a61c0Anton Korobeynikov 721a5e82a5748763eba327176def083eec688eb4d6bRafael Espindola // NEONMoveFixPass will convert VFP moves to NEON moves when profitable. 722a5e82a5748763eba327176def083eec688eb4d6bRafael Espindola if (DestRC == ARM::DPR_VFP2RegisterClass) 723a5e82a5748763eba327176def083eec688eb4d6bRafael Espindola DestRC = ARM::DPRRegisterClass; 724a5e82a5748763eba327176def083eec688eb4d6bRafael Espindola if (SrcRC == ARM::DPR_VFP2RegisterClass) 725a5e82a5748763eba327176def083eec688eb4d6bRafael Espindola SrcRC = ARM::DPRRegisterClass; 726a5e82a5748763eba327176def083eec688eb4d6bRafael Espindola 7276755d97a62fd6796f4146833efb1051fc96a61c0Anton Korobeynikov // Allow QPR / QPR_VFP2 / QPR_8 cross-class copies. 7286755d97a62fd6796f4146833efb1051fc96a61c0Anton Korobeynikov if (DestRC == ARM::QPR_VFP2RegisterClass || 7296755d97a62fd6796f4146833efb1051fc96a61c0Anton Korobeynikov DestRC == ARM::QPR_8RegisterClass) 7306755d97a62fd6796f4146833efb1051fc96a61c0Anton Korobeynikov DestRC = ARM::QPRRegisterClass; 7316755d97a62fd6796f4146833efb1051fc96a61c0Anton Korobeynikov if (SrcRC == ARM::QPR_VFP2RegisterClass || 7326755d97a62fd6796f4146833efb1051fc96a61c0Anton Korobeynikov SrcRC == ARM::QPR_8RegisterClass) 7336755d97a62fd6796f4146833efb1051fc96a61c0Anton Korobeynikov SrcRC = ARM::QPRRegisterClass; 7346755d97a62fd6796f4146833efb1051fc96a61c0Anton Korobeynikov 73522c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng // Allow QQPR / QQPR_VFP2 cross-class copies. 73622c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng if (DestRC == ARM::QQPR_VFP2RegisterClass) 737b63387afc6b10e88631d1ef232c41ab6c18c8581Evan Cheng DestRC = ARM::QQPRRegisterClass; 73822c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng if (SrcRC == ARM::QQPR_VFP2RegisterClass) 739b63387afc6b10e88631d1ef232c41ab6c18c8581Evan Cheng SrcRC = ARM::QQPRRegisterClass; 740b63387afc6b10e88631d1ef232c41ab6c18c8581Evan Cheng 7416755d97a62fd6796f4146833efb1051fc96a61c0Anton Korobeynikov // Disallow copies of unequal sizes. 7426755d97a62fd6796f4146833efb1051fc96a61c0Anton Korobeynikov if (DestRC != SrcRC && DestRC->getSize() != SrcRC->getSize()) 7436755d97a62fd6796f4146833efb1051fc96a61c0Anton Korobeynikov return false; 744b4db6a46e0de3283fa70ea0a7d3623f2e4e2d2a3Evan Cheng 7456755d97a62fd6796f4146833efb1051fc96a61c0Anton Korobeynikov if (DestRC == ARM::GPRRegisterClass) { 7466755d97a62fd6796f4146833efb1051fc96a61c0Anton Korobeynikov if (SrcRC == ARM::SPRRegisterClass) 7476755d97a62fd6796f4146833efb1051fc96a61c0Anton Korobeynikov AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VMOVRS), DestReg) 7486755d97a62fd6796f4146833efb1051fc96a61c0Anton Korobeynikov .addReg(SrcReg)); 7496755d97a62fd6796f4146833efb1051fc96a61c0Anton Korobeynikov else 7506755d97a62fd6796f4146833efb1051fc96a61c0Anton Korobeynikov AddDefaultCC(AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::MOVr), 7516755d97a62fd6796f4146833efb1051fc96a61c0Anton Korobeynikov DestReg).addReg(SrcReg))); 7526755d97a62fd6796f4146833efb1051fc96a61c0Anton Korobeynikov } else { 7536755d97a62fd6796f4146833efb1051fc96a61c0Anton Korobeynikov unsigned Opc; 7546755d97a62fd6796f4146833efb1051fc96a61c0Anton Korobeynikov 7556755d97a62fd6796f4146833efb1051fc96a61c0Anton Korobeynikov if (DestRC == ARM::SPRRegisterClass) 7566755d97a62fd6796f4146833efb1051fc96a61c0Anton Korobeynikov Opc = (SrcRC == ARM::GPRRegisterClass ? ARM::VMOVSR : ARM::VMOVS); 7576755d97a62fd6796f4146833efb1051fc96a61c0Anton Korobeynikov else if (DestRC == ARM::DPRRegisterClass) 7586755d97a62fd6796f4146833efb1051fc96a61c0Anton Korobeynikov Opc = ARM::VMOVD; 7596755d97a62fd6796f4146833efb1051fc96a61c0Anton Korobeynikov else if (DestRC == ARM::QPRRegisterClass) 7606755d97a62fd6796f4146833efb1051fc96a61c0Anton Korobeynikov Opc = ARM::VMOVQ; 761b63387afc6b10e88631d1ef232c41ab6c18c8581Evan Cheng else if (DestRC == ARM::QQPRRegisterClass) 762b63387afc6b10e88631d1ef232c41ab6c18c8581Evan Cheng Opc = ARM::VMOVQQ; 76322c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng else if (DestRC == ARM::QQQQPRRegisterClass) 76422c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng Opc = ARM::VMOVQQQQ; 7656755d97a62fd6796f4146833efb1051fc96a61c0Anton Korobeynikov else 7667bfdca0206f51132b26094c6f83a5ac97ee0f943David Goodwin return false; 767334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 76814f1d4e74bd52b044a2c2bb6dd8df20b0480e633Bob Wilson MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc), DestReg); 76914f1d4e74bd52b044a2c2bb6dd8df20b0480e633Bob Wilson MIB.addReg(SrcReg); 77014f1d4e74bd52b044a2c2bb6dd8df20b0480e633Bob Wilson if (Opc != ARM::VMOVQQ && Opc != ARM::VMOVQQQQ) 77114f1d4e74bd52b044a2c2bb6dd8df20b0480e633Bob Wilson AddDefaultPred(MIB); 7727bfdca0206f51132b26094c6f83a5ac97ee0f943David Goodwin } 773334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 774334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; 775334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 776334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 777c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Chengstatic const 778c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan ChengMachineInstrBuilder &AddDReg(MachineInstrBuilder &MIB, 779c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Cheng unsigned Reg, unsigned SubIdx, unsigned State, 780c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Cheng const TargetRegisterInfo *TRI) { 781c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Cheng if (!SubIdx) 782c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Cheng return MIB.addReg(Reg, State); 783c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Cheng 784c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Cheng if (TargetRegisterInfo::isPhysicalRegister(Reg)) 785c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Cheng return MIB.addReg(TRI->getSubReg(Reg, SubIdx), State); 786c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Cheng return MIB.addReg(Reg, State, SubIdx); 787c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Cheng} 788c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Cheng 789334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinvoid ARMBaseInstrInfo:: 790334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinstoreRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 791334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned SrcReg, bool isKill, int FI, 792746ad69e088176819981b4b2c5ac8dcd49f5e60eEvan Cheng const TargetRegisterClass *RC, 793746ad69e088176819981b4b2c5ac8dcd49f5e60eEvan Cheng const TargetRegisterInfo *TRI) const { 794c7f3ace20c325521c68335a1689645b43b06ddf0Chris Lattner DebugLoc DL; 795334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (I != MBB.end()) DL = I->getDebugLoc(); 796249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MachineFunction &MF = *MBB.getParent(); 797249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MachineFrameInfo &MFI = *MF.getFrameInfo(); 79831bc849123011b8eae6bb3c79876d9a3c26a6a1dJim Grosbach unsigned Align = MFI.getObjectAlignment(FI); 799249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov 800249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MachineMemOperand *MMO = 801ff89dcb06fbd103373436e2d0ae85f252fae2254Evan Cheng MF.getMachineMemOperand(PseudoSourceValue::getFixedStack(FI), 802249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MachineMemOperand::MOStore, 0, 803249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MFI.getObjectSize(FI), 80431bc849123011b8eae6bb3c79876d9a3c26a6a1dJim Grosbach Align); 805334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 8060eb0c7401c34c0b4604f732ce54db995eead14e6Bob Wilson // tGPR is used sometimes in ARM instructions that need to avoid using 8070eb0c7401c34c0b4604f732ce54db995eead14e6Bob Wilson // certain registers. Just treat it as GPR here. 8086470a116f17b70aba0c2e7ee751551a5ac9797f6Dale Johannesen if (RC == ARM::tGPRRegisterClass || RC == ARM::tcGPRRegisterClass) 8090eb0c7401c34c0b4604f732ce54db995eead14e6Bob Wilson RC = ARM::GPRRegisterClass; 8100eb0c7401c34c0b4604f732ce54db995eead14e6Bob Wilson 811ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson switch (RC->getID()) { 812ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson case ARM::GPRRegClassID: 8135732ca084aaa0cd26149e50dd4b487efff37fe41Evan Cheng AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::STR)) 814334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(SrcReg, getKillRegState(isKill)) 815249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov .addFrameIndex(FI).addReg(0).addImm(0).addMemOperand(MMO)); 816ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson break; 817ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson case ARM::SPRRegClassID: 818d31c5496d7e1580058b5c6fbc8fd537a641ea590Evan Cheng AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTRS)) 819d31c5496d7e1580058b5c6fbc8fd537a641ea590Evan Cheng .addReg(SrcReg, getKillRegState(isKill)) 820d31c5496d7e1580058b5c6fbc8fd537a641ea590Evan Cheng .addFrameIndex(FI).addImm(0).addMemOperand(MMO)); 821ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson break; 822ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson case ARM::DPRRegClassID: 823ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson case ARM::DPR_VFP2RegClassID: 824ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson case ARM::DPR_8RegClassID: 825e5165490b7ba24bb2f3043399e0d60e7f3bcf8a5Jim Grosbach AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTRD)) 826334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(SrcReg, getKillRegState(isKill)) 827249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov .addFrameIndex(FI).addImm(0).addMemOperand(MMO)); 828ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson break; 829ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson case ARM::QPRRegClassID: 830ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson case ARM::QPR_VFP2RegClassID: 831ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson case ARM::QPR_8RegClassID: 832baf31088f1472f48ea5ae81f0b93636cc44ca444Anton Korobeynikov // FIXME: Neon instructions should support predicates 833b63387afc6b10e88631d1ef232c41ab6c18c8581Evan Cheng if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) { 83469b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1q)) 835f967ca0eaf30325cabe3c1971bf0dba16cf1b027Bob Wilson .addFrameIndex(FI).addImm(16) 83669b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng .addReg(SrcReg, getKillRegState(isKill)) 83769b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng .addMemOperand(MMO)); 83831bc849123011b8eae6bb3c79876d9a3c26a6a1dJim Grosbach } else { 83969b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMQ)) 84069b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng .addReg(SrcReg, getKillRegState(isKill)) 84169b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng .addFrameIndex(FI) 84269b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng .addImm(ARM_AM::getAM5Opc(ARM_AM::ia, 4)) 84369b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng .addMemOperand(MMO)); 84431bc849123011b8eae6bb3c79876d9a3c26a6a1dJim Grosbach } 845ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson break; 846ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson case ARM::QQPRRegClassID: 847ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson case ARM::QQPR_VFP2RegClassID: 848435d4991779d6a47cadff4ea670b490d8507d6c4Evan Cheng if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) { 84922c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng // FIXME: It's possible to only store part of the QQ register if the 85022c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng // spilled def has a sub-register index. 8518190173350f4e4d916d2307278955b133fba8a00Bob Wilson MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::VST1d64Q)) 852f967ca0eaf30325cabe3c1971bf0dba16cf1b027Bob Wilson .addFrameIndex(FI).addImm(16); 853558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI); 854558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI); 855558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI); 856558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen MIB = AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI); 857435d4991779d6a47cadff4ea670b490d8507d6c4Evan Cheng AddDefaultPred(MIB.addMemOperand(MMO)); 858435d4991779d6a47cadff4ea670b490d8507d6c4Evan Cheng } else { 859435d4991779d6a47cadff4ea670b490d8507d6c4Evan Cheng MachineInstrBuilder MIB = 860435d4991779d6a47cadff4ea670b490d8507d6c4Evan Cheng AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMD)) 861435d4991779d6a47cadff4ea670b490d8507d6c4Evan Cheng .addFrameIndex(FI) 862435d4991779d6a47cadff4ea670b490d8507d6c4Evan Cheng .addImm(ARM_AM::getAM5Opc(ARM_AM::ia, 4))) 863435d4991779d6a47cadff4ea670b490d8507d6c4Evan Cheng .addMemOperand(MMO); 864558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI); 865558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI); 866558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI); 867558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI); 868435d4991779d6a47cadff4ea670b490d8507d6c4Evan Cheng } 869ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson break; 870ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson case ARM::QQQQPRRegClassID: { 87122c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng MachineInstrBuilder MIB = 87222c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMD)) 87322c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng .addFrameIndex(FI) 87422c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng .addImm(ARM_AM::getAM5Opc(ARM_AM::ia, 4))) 87522c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng .addMemOperand(MMO); 876558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI); 877558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI); 878558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI); 879558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen MIB = AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI); 880558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen MIB = AddDReg(MIB, SrcReg, ARM::dsub_4, 0, TRI); 881558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen MIB = AddDReg(MIB, SrcReg, ARM::dsub_5, 0, TRI); 882558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen MIB = AddDReg(MIB, SrcReg, ARM::dsub_6, 0, TRI); 883558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen AddDReg(MIB, SrcReg, ARM::dsub_7, 0, TRI); 884ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson break; 885ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson } 886ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson default: 887ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson llvm_unreachable("Unknown regclass!"); 888334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 889334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 890334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 891334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinvoid ARMBaseInstrInfo:: 892334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinloadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 893334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned DestReg, int FI, 894746ad69e088176819981b4b2c5ac8dcd49f5e60eEvan Cheng const TargetRegisterClass *RC, 895746ad69e088176819981b4b2c5ac8dcd49f5e60eEvan Cheng const TargetRegisterInfo *TRI) const { 896c7f3ace20c325521c68335a1689645b43b06ddf0Chris Lattner DebugLoc DL; 897334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (I != MBB.end()) DL = I->getDebugLoc(); 898249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MachineFunction &MF = *MBB.getParent(); 899249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MachineFrameInfo &MFI = *MF.getFrameInfo(); 90031bc849123011b8eae6bb3c79876d9a3c26a6a1dJim Grosbach unsigned Align = MFI.getObjectAlignment(FI); 901249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MachineMemOperand *MMO = 902ff89dcb06fbd103373436e2d0ae85f252fae2254Evan Cheng MF.getMachineMemOperand(PseudoSourceValue::getFixedStack(FI), 903249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MachineMemOperand::MOLoad, 0, 904249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MFI.getObjectSize(FI), 90531bc849123011b8eae6bb3c79876d9a3c26a6a1dJim Grosbach Align); 906334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 9070eb0c7401c34c0b4604f732ce54db995eead14e6Bob Wilson // tGPR is used sometimes in ARM instructions that need to avoid using 9080eb0c7401c34c0b4604f732ce54db995eead14e6Bob Wilson // certain registers. Just treat it as GPR here. 9096470a116f17b70aba0c2e7ee751551a5ac9797f6Dale Johannesen if (RC == ARM::tGPRRegisterClass || RC == ARM::tcGPRRegisterClass) 9100eb0c7401c34c0b4604f732ce54db995eead14e6Bob Wilson RC = ARM::GPRRegisterClass; 9110eb0c7401c34c0b4604f732ce54db995eead14e6Bob Wilson 912ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson switch (RC->getID()) { 913ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson case ARM::GPRRegClassID: 9145732ca084aaa0cd26149e50dd4b487efff37fe41Evan Cheng AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::LDR), DestReg) 915249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov .addFrameIndex(FI).addReg(0).addImm(0).addMemOperand(MMO)); 916ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson break; 917ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson case ARM::SPRRegClassID: 918d31c5496d7e1580058b5c6fbc8fd537a641ea590Evan Cheng AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRS), DestReg) 919d31c5496d7e1580058b5c6fbc8fd537a641ea590Evan Cheng .addFrameIndex(FI).addImm(0).addMemOperand(MMO)); 920ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson break; 921ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson case ARM::DPRRegClassID: 922ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson case ARM::DPR_VFP2RegClassID: 923ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson case ARM::DPR_8RegClassID: 924e5165490b7ba24bb2f3043399e0d60e7f3bcf8a5Jim Grosbach AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRD), DestReg) 925249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov .addFrameIndex(FI).addImm(0).addMemOperand(MMO)); 926ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson break; 927ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson case ARM::QPRRegClassID: 928ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson case ARM::QPR_VFP2RegClassID: 929ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson case ARM::QPR_8RegClassID: 930b63387afc6b10e88631d1ef232c41ab6c18c8581Evan Cheng if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) { 93169b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1q), DestReg) 932f967ca0eaf30325cabe3c1971bf0dba16cf1b027Bob Wilson .addFrameIndex(FI).addImm(16) 93369b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng .addMemOperand(MMO)); 93431bc849123011b8eae6bb3c79876d9a3c26a6a1dJim Grosbach } else { 93569b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMQ), DestReg) 93669b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng .addFrameIndex(FI) 93769b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng .addImm(ARM_AM::getAM5Opc(ARM_AM::ia, 4)) 93869b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng .addMemOperand(MMO)); 93931bc849123011b8eae6bb3c79876d9a3c26a6a1dJim Grosbach } 940ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson break; 941ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson case ARM::QQPRRegClassID: 942ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson case ARM::QQPR_VFP2RegClassID: 943435d4991779d6a47cadff4ea670b490d8507d6c4Evan Cheng if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) { 9448190173350f4e4d916d2307278955b133fba8a00Bob Wilson MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::VLD1d64Q)); 945558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::Define, TRI); 946558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::Define, TRI); 947558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::Define, TRI); 948558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::Define, TRI); 949f967ca0eaf30325cabe3c1971bf0dba16cf1b027Bob Wilson AddDefaultPred(MIB.addFrameIndex(FI).addImm(16).addMemOperand(MMO)); 950435d4991779d6a47cadff4ea670b490d8507d6c4Evan Cheng } else { 951435d4991779d6a47cadff4ea670b490d8507d6c4Evan Cheng MachineInstrBuilder MIB = 952435d4991779d6a47cadff4ea670b490d8507d6c4Evan Cheng AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMD)) 953435d4991779d6a47cadff4ea670b490d8507d6c4Evan Cheng .addFrameIndex(FI) 954435d4991779d6a47cadff4ea670b490d8507d6c4Evan Cheng .addImm(ARM_AM::getAM5Opc(ARM_AM::ia, 4))) 955435d4991779d6a47cadff4ea670b490d8507d6c4Evan Cheng .addMemOperand(MMO); 956558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::Define, TRI); 957558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::Define, TRI); 958558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::Define, TRI); 959558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen AddDReg(MIB, DestReg, ARM::dsub_3, RegState::Define, TRI); 960435d4991779d6a47cadff4ea670b490d8507d6c4Evan Cheng } 961ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson break; 962ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson case ARM::QQQQPRRegClassID: { 963ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson MachineInstrBuilder MIB = 964ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMD)) 965ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson .addFrameIndex(FI) 966ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson .addImm(ARM_AM::getAM5Opc(ARM_AM::ia, 4))) 967ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson .addMemOperand(MMO); 968ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::Define, TRI); 969ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::Define, TRI); 970ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::Define, TRI); 971ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::Define, TRI); 972ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson MIB = AddDReg(MIB, DestReg, ARM::dsub_4, RegState::Define, TRI); 973ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson MIB = AddDReg(MIB, DestReg, ARM::dsub_5, RegState::Define, TRI); 974ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson MIB = AddDReg(MIB, DestReg, ARM::dsub_6, RegState::Define, TRI); 975ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson AddDReg(MIB, DestReg, ARM::dsub_7, RegState::Define, TRI); 976ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson break; 977ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson } 978ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson default: 979ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson llvm_unreachable("Unknown regclass!"); 980334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 981334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 982334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 98362b50656ceb854eb0be265d63b2a1d46e7400d8aEvan ChengMachineInstr* 98462b50656ceb854eb0be265d63b2a1d46e7400d8aEvan ChengARMBaseInstrInfo::emitFrameIndexDebugValue(MachineFunction &MF, 9858601a3d4decff0a380e059b037dabf71075497d3Evan Cheng int FrameIx, uint64_t Offset, 98662b50656ceb854eb0be265d63b2a1d46e7400d8aEvan Cheng const MDNode *MDPtr, 98762b50656ceb854eb0be265d63b2a1d46e7400d8aEvan Cheng DebugLoc DL) const { 98862b50656ceb854eb0be265d63b2a1d46e7400d8aEvan Cheng MachineInstrBuilder MIB = BuildMI(MF, DL, get(ARM::DBG_VALUE)) 98962b50656ceb854eb0be265d63b2a1d46e7400d8aEvan Cheng .addFrameIndex(FrameIx).addImm(0).addImm(Offset).addMetadata(MDPtr); 99062b50656ceb854eb0be265d63b2a1d46e7400d8aEvan Cheng return &*MIB; 99162b50656ceb854eb0be265d63b2a1d46e7400d8aEvan Cheng} 99262b50656ceb854eb0be265d63b2a1d46e7400d8aEvan Cheng 993334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinMachineInstr *ARMBaseInstrInfo:: 994334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinfoldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI, 995334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const SmallVectorImpl<unsigned> &Ops, int FI) const { 996334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (Ops.size() != 1) return NULL; 997334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 998334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned OpNum = Ops[0]; 999334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned Opc = MI->getOpcode(); 1000334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineInstr *NewMI = NULL; 100119068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng if (Opc == ARM::MOVr || Opc == ARM::t2MOVr) { 1002334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // If it is updating CPSR, then it cannot be folded. 100319068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng if (MI->getOperand(4).getReg() == ARM::CPSR && !MI->getOperand(4).isDead()) 100419068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng return NULL; 100519068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng unsigned Pred = MI->getOperand(2).getImm(); 100619068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng unsigned PredReg = MI->getOperand(3).getReg(); 100719068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng if (OpNum == 0) { // move -> store 100819068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng unsigned SrcReg = MI->getOperand(1).getReg(); 1009ed3ad212ec34fa2866fb70f9e52ddda31032ea3bEvan Cheng unsigned SrcSubReg = MI->getOperand(1).getSubReg(); 101019068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng bool isKill = MI->getOperand(1).isKill(); 101119068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng bool isUndef = MI->getOperand(1).isUndef(); 101219068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng if (Opc == ARM::MOVr) 101319068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::STR)) 1014ed3ad212ec34fa2866fb70f9e52ddda31032ea3bEvan Cheng .addReg(SrcReg, 1015ed3ad212ec34fa2866fb70f9e52ddda31032ea3bEvan Cheng getKillRegState(isKill) | getUndefRegState(isUndef), 1016ed3ad212ec34fa2866fb70f9e52ddda31032ea3bEvan Cheng SrcSubReg) 101719068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng .addFrameIndex(FI).addReg(0).addImm(0).addImm(Pred).addReg(PredReg); 101819068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng else // ARM::t2MOVr 101919068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::t2STRi12)) 1020ed3ad212ec34fa2866fb70f9e52ddda31032ea3bEvan Cheng .addReg(SrcReg, 1021ed3ad212ec34fa2866fb70f9e52ddda31032ea3bEvan Cheng getKillRegState(isKill) | getUndefRegState(isUndef), 1022ed3ad212ec34fa2866fb70f9e52ddda31032ea3bEvan Cheng SrcSubReg) 102319068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg); 102419068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng } else { // move -> load 102519068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng unsigned DstReg = MI->getOperand(0).getReg(); 1026ed3ad212ec34fa2866fb70f9e52ddda31032ea3bEvan Cheng unsigned DstSubReg = MI->getOperand(0).getSubReg(); 102719068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng bool isDead = MI->getOperand(0).isDead(); 102819068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng bool isUndef = MI->getOperand(0).isUndef(); 102919068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng if (Opc == ARM::MOVr) 103019068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::LDR)) 103119068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng .addReg(DstReg, 103219068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng RegState::Define | 103319068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng getDeadRegState(isDead) | 1034ed3ad212ec34fa2866fb70f9e52ddda31032ea3bEvan Cheng getUndefRegState(isUndef), DstSubReg) 103519068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng .addFrameIndex(FI).addReg(0).addImm(0).addImm(Pred).addReg(PredReg); 103619068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng else // ARM::t2MOVr 103719068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::t2LDRi12)) 103819068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng .addReg(DstReg, 103919068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng RegState::Define | 104019068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng getDeadRegState(isDead) | 1041ed3ad212ec34fa2866fb70f9e52ddda31032ea3bEvan Cheng getUndefRegState(isUndef), DstSubReg) 104219068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg); 1043334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 104419068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng } else if (Opc == ARM::tMOVgpr2gpr || 104519068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng Opc == ARM::tMOVtgpr2gpr || 104619068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng Opc == ARM::tMOVgpr2tgpr) { 104719068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng if (OpNum == 0) { // move -> store 104819068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng unsigned SrcReg = MI->getOperand(1).getReg(); 1049ed3ad212ec34fa2866fb70f9e52ddda31032ea3bEvan Cheng unsigned SrcSubReg = MI->getOperand(1).getSubReg(); 105019068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng bool isKill = MI->getOperand(1).isKill(); 105119068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng bool isUndef = MI->getOperand(1).isUndef(); 105219068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::t2STRi12)) 1053ed3ad212ec34fa2866fb70f9e52ddda31032ea3bEvan Cheng .addReg(SrcReg, 1054ed3ad212ec34fa2866fb70f9e52ddda31032ea3bEvan Cheng getKillRegState(isKill) | getUndefRegState(isUndef), 1055ed3ad212ec34fa2866fb70f9e52ddda31032ea3bEvan Cheng SrcSubReg) 105619068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng .addFrameIndex(FI).addImm(0).addImm(ARMCC::AL).addReg(0); 105719068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng } else { // move -> load 105819068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng unsigned DstReg = MI->getOperand(0).getReg(); 1059ed3ad212ec34fa2866fb70f9e52ddda31032ea3bEvan Cheng unsigned DstSubReg = MI->getOperand(0).getSubReg(); 106019068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng bool isDead = MI->getOperand(0).isDead(); 106119068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng bool isUndef = MI->getOperand(0).isUndef(); 106219068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::t2LDRi12)) 106319068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng .addReg(DstReg, 106419068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng RegState::Define | 106519068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng getDeadRegState(isDead) | 1066ed3ad212ec34fa2866fb70f9e52ddda31032ea3bEvan Cheng getUndefRegState(isUndef), 1067ed3ad212ec34fa2866fb70f9e52ddda31032ea3bEvan Cheng DstSubReg) 106819068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng .addFrameIndex(FI).addImm(0).addImm(ARMCC::AL).addReg(0); 106919068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng } 1070e5165490b7ba24bb2f3043399e0d60e7f3bcf8a5Jim Grosbach } else if (Opc == ARM::VMOVS) { 1071334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned Pred = MI->getOperand(2).getImm(); 1072334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned PredReg = MI->getOperand(3).getReg(); 1073334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (OpNum == 0) { // move -> store 1074334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned SrcReg = MI->getOperand(1).getReg(); 1075ed3ad212ec34fa2866fb70f9e52ddda31032ea3bEvan Cheng unsigned SrcSubReg = MI->getOperand(1).getSubReg(); 1076334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool isKill = MI->getOperand(1).isKill(); 1077334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool isUndef = MI->getOperand(1).isUndef(); 1078e5165490b7ba24bb2f3043399e0d60e7f3bcf8a5Jim Grosbach NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::VSTRS)) 1079ed3ad212ec34fa2866fb70f9e52ddda31032ea3bEvan Cheng .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef), 1080ed3ad212ec34fa2866fb70f9e52ddda31032ea3bEvan Cheng SrcSubReg) 1081334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addFrameIndex(FI) 1082334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addImm(0).addImm(Pred).addReg(PredReg); 1083334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } else { // move -> load 1084334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned DstReg = MI->getOperand(0).getReg(); 1085ed3ad212ec34fa2866fb70f9e52ddda31032ea3bEvan Cheng unsigned DstSubReg = MI->getOperand(0).getSubReg(); 1086334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool isDead = MI->getOperand(0).isDead(); 1087334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool isUndef = MI->getOperand(0).isUndef(); 1088e5165490b7ba24bb2f3043399e0d60e7f3bcf8a5Jim Grosbach NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::VLDRS)) 1089334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(DstReg, 1090334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin RegState::Define | 1091334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin getDeadRegState(isDead) | 1092ed3ad212ec34fa2866fb70f9e52ddda31032ea3bEvan Cheng getUndefRegState(isUndef), 1093ed3ad212ec34fa2866fb70f9e52ddda31032ea3bEvan Cheng DstSubReg) 1094334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg); 1095334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 109669b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng } else if (Opc == ARM::VMOVD || Opc == ARM::VMOVDneon) { 1097334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned Pred = MI->getOperand(2).getImm(); 1098334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned PredReg = MI->getOperand(3).getReg(); 1099334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (OpNum == 0) { // move -> store 1100334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned SrcReg = MI->getOperand(1).getReg(); 1101ed3ad212ec34fa2866fb70f9e52ddda31032ea3bEvan Cheng unsigned SrcSubReg = MI->getOperand(1).getSubReg(); 1102334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool isKill = MI->getOperand(1).isKill(); 1103334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool isUndef = MI->getOperand(1).isUndef(); 1104e5165490b7ba24bb2f3043399e0d60e7f3bcf8a5Jim Grosbach NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::VSTRD)) 1105ed3ad212ec34fa2866fb70f9e52ddda31032ea3bEvan Cheng .addReg(SrcReg, 1106ed3ad212ec34fa2866fb70f9e52ddda31032ea3bEvan Cheng getKillRegState(isKill) | getUndefRegState(isUndef), 1107ed3ad212ec34fa2866fb70f9e52ddda31032ea3bEvan Cheng SrcSubReg) 1108334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg); 1109334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } else { // move -> load 1110334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned DstReg = MI->getOperand(0).getReg(); 1111ed3ad212ec34fa2866fb70f9e52ddda31032ea3bEvan Cheng unsigned DstSubReg = MI->getOperand(0).getSubReg(); 1112334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool isDead = MI->getOperand(0).isDead(); 1113334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool isUndef = MI->getOperand(0).isUndef(); 1114e5165490b7ba24bb2f3043399e0d60e7f3bcf8a5Jim Grosbach NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::VLDRD)) 1115334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(DstReg, 1116334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin RegState::Define | 1117334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin getDeadRegState(isDead) | 1118ed3ad212ec34fa2866fb70f9e52ddda31032ea3bEvan Cheng getUndefRegState(isUndef), 1119ed3ad212ec34fa2866fb70f9e52ddda31032ea3bEvan Cheng DstSubReg) 1120334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg); 1121334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 112269b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng } else if (Opc == ARM::VMOVQ) { 112369b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng MachineFrameInfo &MFI = *MF.getFrameInfo(); 112469b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng unsigned Pred = MI->getOperand(2).getImm(); 112569b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng unsigned PredReg = MI->getOperand(3).getReg(); 112669b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng if (OpNum == 0) { // move -> store 112769b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng unsigned SrcReg = MI->getOperand(1).getReg(); 112869b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng unsigned SrcSubReg = MI->getOperand(1).getSubReg(); 112969b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng bool isKill = MI->getOperand(1).isKill(); 113069b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng bool isUndef = MI->getOperand(1).isUndef(); 113169b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng if (MFI.getObjectAlignment(FI) >= 16 && 113269b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng getRegisterInfo().canRealignStack(MF)) { 113369b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::VST1q)) 1134f967ca0eaf30325cabe3c1971bf0dba16cf1b027Bob Wilson .addFrameIndex(FI).addImm(16) 113569b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng .addReg(SrcReg, 113669b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng getKillRegState(isKill) | getUndefRegState(isUndef), 113769b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng SrcSubReg) 113869b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng .addImm(Pred).addReg(PredReg); 113969b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng } else { 114069b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::VSTMQ)) 114169b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng .addReg(SrcReg, 114269b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng getKillRegState(isKill) | getUndefRegState(isUndef), 114369b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng SrcSubReg) 114469b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng .addFrameIndex(FI).addImm(ARM_AM::getAM5Opc(ARM_AM::ia, 4)) 114569b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng .addImm(Pred).addReg(PredReg); 114669b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng } 114769b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng } else { // move -> load 114869b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng unsigned DstReg = MI->getOperand(0).getReg(); 114969b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng unsigned DstSubReg = MI->getOperand(0).getSubReg(); 115069b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng bool isDead = MI->getOperand(0).isDead(); 115169b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng bool isUndef = MI->getOperand(0).isUndef(); 115269b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng if (MFI.getObjectAlignment(FI) >= 16 && 115369b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng getRegisterInfo().canRealignStack(MF)) { 115469b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::VLD1q)) 115569b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng .addReg(DstReg, 115669b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng RegState::Define | 115769b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng getDeadRegState(isDead) | 115869b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng getUndefRegState(isUndef), 115969b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng DstSubReg) 1160f967ca0eaf30325cabe3c1971bf0dba16cf1b027Bob Wilson .addFrameIndex(FI).addImm(16).addImm(Pred).addReg(PredReg); 116169b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng } else { 116269b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::VLDMQ)) 116369b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng .addReg(DstReg, 116469b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng RegState::Define | 116569b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng getDeadRegState(isDead) | 116669b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng getUndefRegState(isUndef), 116769b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng DstSubReg) 116869b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng .addFrameIndex(FI).addImm(ARM_AM::getAM5Opc(ARM_AM::ia, 4)) 116969b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng .addImm(Pred).addReg(PredReg); 117069b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng } 117169b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng } 1172334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 1173334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 1174334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return NewMI; 1175334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 1176334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 1177764ab52dd80310a205c9888bf166d09dab858f90Jim GrosbachMachineInstr* 1178334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinARMBaseInstrInfo::foldMemoryOperandImpl(MachineFunction &MF, 1179334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineInstr* MI, 1180334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const SmallVectorImpl<unsigned> &Ops, 1181334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineInstr* LoadMI) const { 11821f5c9887544ac2cb39d48e35cc6fa7a7b73ed3b0Evan Cheng // FIXME 1183334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 0; 1184334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 1185334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 1186334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinbool 1187334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinARMBaseInstrInfo::canFoldMemoryOperand(const MachineInstr *MI, 1188229464564243b24fb12cece515d727673e726994Evan Cheng const SmallVectorImpl<unsigned> &Ops) const { 1189334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (Ops.size() != 1) return false; 1190334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 1191334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned Opc = MI->getOpcode(); 11925732ca084aaa0cd26149e50dd4b487efff37fe41Evan Cheng if (Opc == ARM::MOVr || Opc == ARM::t2MOVr) { 1193334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // If it is updating CPSR, then it cannot be folded. 1194229464564243b24fb12cece515d727673e726994Evan Cheng return MI->getOperand(4).getReg() != ARM::CPSR || 1195229464564243b24fb12cece515d727673e726994Evan Cheng MI->getOperand(4).isDead(); 119619068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng } else if (Opc == ARM::tMOVgpr2gpr || 119719068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng Opc == ARM::tMOVtgpr2gpr || 119819068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng Opc == ARM::tMOVgpr2tgpr) { 119919068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng return true; 120069b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng } else if (Opc == ARM::VMOVS || Opc == ARM::VMOVD || 120169b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng Opc == ARM::VMOVDneon || Opc == ARM::VMOVQ) { 1202334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; 1203334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 1204334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 120522c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng // FIXME: VMOVQQ and VMOVQQQQ? 120622c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng 1207334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 1208334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 12095ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng 121030ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen/// Create a copy of a const pool value. Update CPI to the new index and return 121130ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen/// the label UID. 121230ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesenstatic unsigned duplicateCPV(MachineFunction &MF, unsigned &CPI) { 121330ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen MachineConstantPool *MCP = MF.getConstantPool(); 121430ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 121530ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen 121630ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPI]; 121730ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen assert(MCPE.isMachineConstantPoolEntry() && 121830ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen "Expecting a machine constantpool entry!"); 121930ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen ARMConstantPoolValue *ACPV = 122030ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal); 122130ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen 122230ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen unsigned PCLabelId = AFI->createConstPoolEntryUId(); 122330ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen ARMConstantPoolValue *NewCPV = 0; 122430ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen if (ACPV->isGlobalValue()) 122530ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen NewCPV = new ARMConstantPoolValue(ACPV->getGV(), PCLabelId, 122630ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen ARMCP::CPValue, 4); 122730ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen else if (ACPV->isExtSymbol()) 122830ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen NewCPV = new ARMConstantPoolValue(MF.getFunction()->getContext(), 122930ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen ACPV->getSymbol(), PCLabelId, 4); 123030ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen else if (ACPV->isBlockAddress()) 123130ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen NewCPV = new ARMConstantPoolValue(ACPV->getBlockAddress(), PCLabelId, 123230ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen ARMCP::CPBlockAddress, 4); 123330ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen else 123430ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen llvm_unreachable("Unexpected ARM constantpool value type!!"); 123530ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen CPI = MCP->getConstantPoolIndex(NewCPV, MCPE.getAlignment()); 123630ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen return PCLabelId; 123730ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen} 123830ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen 1239fdc834046efd427d474e3b899ec69354c05071e0Evan Chengvoid ARMBaseInstrInfo:: 1240fdc834046efd427d474e3b899ec69354c05071e0Evan ChengreMaterialize(MachineBasicBlock &MBB, 1241fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng MachineBasicBlock::iterator I, 1242fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng unsigned DestReg, unsigned SubIdx, 1243d57cdd5683ea926e489067364fb7ffe5fd5d35eeEvan Cheng const MachineInstr *Orig, 12449edf7deb37f0f97664f279040fa15d89f32e23d9Jakob Stoklund Olesen const TargetRegisterInfo &TRI) const { 1245fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng unsigned Opcode = Orig->getOpcode(); 1246fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng switch (Opcode) { 1247fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng default: { 1248fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig); 12499edf7deb37f0f97664f279040fa15d89f32e23d9Jakob Stoklund Olesen MI->substituteRegister(Orig->getOperand(0).getReg(), DestReg, SubIdx, TRI); 1250fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng MBB.insert(I, MI); 1251fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng break; 1252fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng } 1253fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng case ARM::tLDRpci_pic: 1254fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng case ARM::t2LDRpci_pic: { 1255fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng MachineFunction &MF = *MBB.getParent(); 1256fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng unsigned CPI = Orig->getOperand(1).getIndex(); 125730ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen unsigned PCLabelId = duplicateCPV(MF, CPI); 1258fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng MachineInstrBuilder MIB = BuildMI(MBB, I, Orig->getDebugLoc(), get(Opcode), 1259fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng DestReg) 1260fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng .addConstantPoolIndex(CPI).addImm(PCLabelId); 1261fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng (*MIB).setMemRefs(Orig->memoperands_begin(), Orig->memoperands_end()); 1262fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng break; 1263fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng } 1264fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng } 1265fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng} 1266fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng 126730ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund OlesenMachineInstr * 126830ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund OlesenARMBaseInstrInfo::duplicate(MachineInstr *Orig, MachineFunction &MF) const { 126930ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen MachineInstr *MI = TargetInstrInfoImpl::duplicate(Orig, MF); 127030ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen switch(Orig->getOpcode()) { 127130ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen case ARM::tLDRpci_pic: 127230ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen case ARM::t2LDRpci_pic: { 127330ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen unsigned CPI = Orig->getOperand(1).getIndex(); 127430ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen unsigned PCLabelId = duplicateCPV(MF, CPI); 127530ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen Orig->getOperand(1).setIndex(CPI); 127630ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen Orig->getOperand(2).setImm(PCLabelId); 127730ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen break; 127830ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen } 127930ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen } 128030ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen return MI; 128130ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen} 128230ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen 1283506049f29f4f202a8e45feb916cc0264440a7f6dEvan Chengbool ARMBaseInstrInfo::produceSameValue(const MachineInstr *MI0, 1284506049f29f4f202a8e45feb916cc0264440a7f6dEvan Cheng const MachineInstr *MI1) const { 1285d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng int Opcode = MI0->getOpcode(); 12869b82425cb0105fd5704f6b9bcd5e7693b05b1759Evan Cheng if (Opcode == ARM::t2LDRpci || 12879b82425cb0105fd5704f6b9bcd5e7693b05b1759Evan Cheng Opcode == ARM::t2LDRpci_pic || 12889b82425cb0105fd5704f6b9bcd5e7693b05b1759Evan Cheng Opcode == ARM::tLDRpci || 12899b82425cb0105fd5704f6b9bcd5e7693b05b1759Evan Cheng Opcode == ARM::tLDRpci_pic) { 1290d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng if (MI1->getOpcode() != Opcode) 1291d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng return false; 1292d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng if (MI0->getNumOperands() != MI1->getNumOperands()) 1293d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng return false; 1294d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng 1295d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng const MachineOperand &MO0 = MI0->getOperand(1); 1296d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng const MachineOperand &MO1 = MI1->getOperand(1); 1297d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng if (MO0.getOffset() != MO1.getOffset()) 1298d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng return false; 1299d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng 1300d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng const MachineFunction *MF = MI0->getParent()->getParent(); 1301d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng const MachineConstantPool *MCP = MF->getConstantPool(); 1302d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng int CPI0 = MO0.getIndex(); 1303d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng int CPI1 = MO1.getIndex(); 1304d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng const MachineConstantPoolEntry &MCPE0 = MCP->getConstants()[CPI0]; 1305d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng const MachineConstantPoolEntry &MCPE1 = MCP->getConstants()[CPI1]; 1306d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng ARMConstantPoolValue *ACPV0 = 1307d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng static_cast<ARMConstantPoolValue*>(MCPE0.Val.MachineCPVal); 1308d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng ARMConstantPoolValue *ACPV1 = 1309d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng static_cast<ARMConstantPoolValue*>(MCPE1.Val.MachineCPVal); 1310d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng return ACPV0->hasSameValue(ACPV1); 1311d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng } 1312d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng 1313506049f29f4f202a8e45feb916cc0264440a7f6dEvan Cheng return MI0->isIdenticalTo(MI1, MachineInstr::IgnoreVRegDefs); 1314d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng} 1315d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng 13164b722108e2cf8e77157e0879a23789cd44829933Bill Wendling/// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to 13174b722108e2cf8e77157e0879a23789cd44829933Bill Wendling/// determine if two loads are loading from the same base address. It should 13184b722108e2cf8e77157e0879a23789cd44829933Bill Wendling/// only return true if the base pointers are the same and the only differences 13194b722108e2cf8e77157e0879a23789cd44829933Bill Wendling/// between the two addresses is the offset. It also returns the offsets by 13204b722108e2cf8e77157e0879a23789cd44829933Bill Wendling/// reference. 13214b722108e2cf8e77157e0879a23789cd44829933Bill Wendlingbool ARMBaseInstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, 13224b722108e2cf8e77157e0879a23789cd44829933Bill Wendling int64_t &Offset1, 13234b722108e2cf8e77157e0879a23789cd44829933Bill Wendling int64_t &Offset2) const { 13244b722108e2cf8e77157e0879a23789cd44829933Bill Wendling // Don't worry about Thumb: just ARM and Thumb2. 13254b722108e2cf8e77157e0879a23789cd44829933Bill Wendling if (Subtarget.isThumb1Only()) return false; 13264b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 13274b722108e2cf8e77157e0879a23789cd44829933Bill Wendling if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode()) 13284b722108e2cf8e77157e0879a23789cd44829933Bill Wendling return false; 13294b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 13304b722108e2cf8e77157e0879a23789cd44829933Bill Wendling switch (Load1->getMachineOpcode()) { 13314b722108e2cf8e77157e0879a23789cd44829933Bill Wendling default: 13324b722108e2cf8e77157e0879a23789cd44829933Bill Wendling return false; 13334b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::LDR: 13344b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::LDRB: 13354b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::LDRD: 13364b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::LDRH: 13374b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::LDRSB: 13384b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::LDRSH: 13394b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::VLDRD: 13404b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::VLDRS: 13414b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::t2LDRi8: 13424b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::t2LDRDi8: 13434b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::t2LDRSHi8: 13444b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::t2LDRi12: 13454b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::t2LDRSHi12: 13464b722108e2cf8e77157e0879a23789cd44829933Bill Wendling break; 13474b722108e2cf8e77157e0879a23789cd44829933Bill Wendling } 13484b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 13494b722108e2cf8e77157e0879a23789cd44829933Bill Wendling switch (Load2->getMachineOpcode()) { 13504b722108e2cf8e77157e0879a23789cd44829933Bill Wendling default: 13514b722108e2cf8e77157e0879a23789cd44829933Bill Wendling return false; 13524b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::LDR: 13534b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::LDRB: 13544b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::LDRD: 13554b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::LDRH: 13564b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::LDRSB: 13574b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::LDRSH: 13584b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::VLDRD: 13594b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::VLDRS: 13604b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::t2LDRi8: 13614b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::t2LDRDi8: 13624b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::t2LDRSHi8: 13634b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::t2LDRi12: 13644b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::t2LDRSHi12: 13654b722108e2cf8e77157e0879a23789cd44829933Bill Wendling break; 13664b722108e2cf8e77157e0879a23789cd44829933Bill Wendling } 13674b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 13684b722108e2cf8e77157e0879a23789cd44829933Bill Wendling // Check if base addresses and chain operands match. 13694b722108e2cf8e77157e0879a23789cd44829933Bill Wendling if (Load1->getOperand(0) != Load2->getOperand(0) || 13704b722108e2cf8e77157e0879a23789cd44829933Bill Wendling Load1->getOperand(4) != Load2->getOperand(4)) 13714b722108e2cf8e77157e0879a23789cd44829933Bill Wendling return false; 13724b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 13734b722108e2cf8e77157e0879a23789cd44829933Bill Wendling // Index should be Reg0. 13744b722108e2cf8e77157e0879a23789cd44829933Bill Wendling if (Load1->getOperand(3) != Load2->getOperand(3)) 13754b722108e2cf8e77157e0879a23789cd44829933Bill Wendling return false; 13764b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 13774b722108e2cf8e77157e0879a23789cd44829933Bill Wendling // Determine the offsets. 13784b722108e2cf8e77157e0879a23789cd44829933Bill Wendling if (isa<ConstantSDNode>(Load1->getOperand(1)) && 13794b722108e2cf8e77157e0879a23789cd44829933Bill Wendling isa<ConstantSDNode>(Load2->getOperand(1))) { 13804b722108e2cf8e77157e0879a23789cd44829933Bill Wendling Offset1 = cast<ConstantSDNode>(Load1->getOperand(1))->getSExtValue(); 13814b722108e2cf8e77157e0879a23789cd44829933Bill Wendling Offset2 = cast<ConstantSDNode>(Load2->getOperand(1))->getSExtValue(); 13824b722108e2cf8e77157e0879a23789cd44829933Bill Wendling return true; 13834b722108e2cf8e77157e0879a23789cd44829933Bill Wendling } 13844b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 13854b722108e2cf8e77157e0879a23789cd44829933Bill Wendling return false; 13864b722108e2cf8e77157e0879a23789cd44829933Bill Wendling} 13874b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 13884b722108e2cf8e77157e0879a23789cd44829933Bill Wendling/// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to 13894b722108e2cf8e77157e0879a23789cd44829933Bill Wendling/// determine (in conjuction with areLoadsFromSameBasePtr) if two loads should 13904b722108e2cf8e77157e0879a23789cd44829933Bill Wendling/// be scheduled togther. On some targets if two loads are loading from 13914b722108e2cf8e77157e0879a23789cd44829933Bill Wendling/// addresses in the same cache line, it's better if they are scheduled 13924b722108e2cf8e77157e0879a23789cd44829933Bill Wendling/// together. This function takes two integers that represent the load offsets 13934b722108e2cf8e77157e0879a23789cd44829933Bill Wendling/// from the common base address. It returns true if it decides it's desirable 13944b722108e2cf8e77157e0879a23789cd44829933Bill Wendling/// to schedule the two loads together. "NumLoads" is the number of loads that 13954b722108e2cf8e77157e0879a23789cd44829933Bill Wendling/// have already been scheduled after Load1. 13964b722108e2cf8e77157e0879a23789cd44829933Bill Wendlingbool ARMBaseInstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, 13974b722108e2cf8e77157e0879a23789cd44829933Bill Wendling int64_t Offset1, int64_t Offset2, 13984b722108e2cf8e77157e0879a23789cd44829933Bill Wendling unsigned NumLoads) const { 13994b722108e2cf8e77157e0879a23789cd44829933Bill Wendling // Don't worry about Thumb: just ARM and Thumb2. 14004b722108e2cf8e77157e0879a23789cd44829933Bill Wendling if (Subtarget.isThumb1Only()) return false; 14014b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 14024b722108e2cf8e77157e0879a23789cd44829933Bill Wendling assert(Offset2 > Offset1); 14034b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 14044b722108e2cf8e77157e0879a23789cd44829933Bill Wendling if ((Offset2 - Offset1) / 8 > 64) 14054b722108e2cf8e77157e0879a23789cd44829933Bill Wendling return false; 14064b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 14074b722108e2cf8e77157e0879a23789cd44829933Bill Wendling if (Load1->getMachineOpcode() != Load2->getMachineOpcode()) 14084b722108e2cf8e77157e0879a23789cd44829933Bill Wendling return false; // FIXME: overly conservative? 14094b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 14104b722108e2cf8e77157e0879a23789cd44829933Bill Wendling // Four loads in a row should be sufficient. 14114b722108e2cf8e77157e0879a23789cd44829933Bill Wendling if (NumLoads >= 3) 14124b722108e2cf8e77157e0879a23789cd44829933Bill Wendling return false; 14134b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 14144b722108e2cf8e77157e0879a23789cd44829933Bill Wendling return true; 14154b722108e2cf8e77157e0879a23789cd44829933Bill Wendling} 14164b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 141786050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Chengbool ARMBaseInstrInfo::isSchedulingBoundary(const MachineInstr *MI, 141886050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng const MachineBasicBlock *MBB, 141986050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng const MachineFunction &MF) const { 142057bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach // Debug info is never a scheduling boundary. It's necessary to be explicit 142157bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach // due to the special treatment of IT instructions below, otherwise a 142257bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach // dbg_value followed by an IT will result in the IT instruction being 142357bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach // considered a scheduling hazard, which is wrong. It should be the actual 142457bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach // instruction preceding the dbg_value instruction(s), just like it is 142557bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach // when debug info is not present. 142657bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach if (MI->isDebugValue()) 142757bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach return false; 142857bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach 142986050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // Terminators and labels can't be scheduled around. 143086050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng if (MI->getDesc().isTerminator() || MI->isLabel()) 143186050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng return true; 143286050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng 143386050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // Treat the start of the IT block as a scheduling boundary, but schedule 143486050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // t2IT along with all instructions following it. 143586050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // FIXME: This is a big hammer. But the alternative is to add all potential 143686050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // true and anti dependencies to IT block instructions as implicit operands 143786050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // to the t2IT instruction. The added compile time and complexity does not 143886050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // seem worth it. 143986050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng MachineBasicBlock::const_iterator I = MI; 144057bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach // Make sure to skip any dbg_value instructions 144157bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach while (++I != MBB->end() && I->isDebugValue()) 144257bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach ; 144357bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach if (I != MBB->end() && I->getOpcode() == ARM::t2IT) 144486050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng return true; 144586050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng 144686050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // Don't attempt to schedule around any instruction that defines 144786050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // a stack-oriented pointer, as it's unlikely to be profitable. This 144886050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // saves compile time, because it doesn't require every single 144986050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // stack slot reference to depend on the instruction that does the 145086050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // modification. 145186050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng if (MI->definesRegister(ARM::SP)) 145286050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng return true; 145386050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng 145486050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng return false; 145586050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng} 145686050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng 145713151432edace19ee867a93b5c14573df4f75d24Evan Chengbool ARMBaseInstrInfo:: 145813151432edace19ee867a93b5c14573df4f75d24Evan ChengisProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumInstrs) const { 145913151432edace19ee867a93b5c14573df4f75d24Evan Cheng if (!NumInstrs) 146013151432edace19ee867a93b5c14573df4f75d24Evan Cheng return false; 146113151432edace19ee867a93b5c14573df4f75d24Evan Cheng if (Subtarget.getCPUString() == "generic") 146213151432edace19ee867a93b5c14573df4f75d24Evan Cheng // Generic (and overly aggressive) if-conversion limits for testing. 146313151432edace19ee867a93b5c14573df4f75d24Evan Cheng return NumInstrs <= 10; 146413151432edace19ee867a93b5c14573df4f75d24Evan Cheng else if (Subtarget.hasV7Ops()) 146513151432edace19ee867a93b5c14573df4f75d24Evan Cheng return NumInstrs <= 3; 146613151432edace19ee867a93b5c14573df4f75d24Evan Cheng return NumInstrs <= 2; 146713151432edace19ee867a93b5c14573df4f75d24Evan Cheng} 146813151432edace19ee867a93b5c14573df4f75d24Evan Cheng 146913151432edace19ee867a93b5c14573df4f75d24Evan Chengbool ARMBaseInstrInfo:: 147013151432edace19ee867a93b5c14573df4f75d24Evan ChengisProfitableToIfCvt(MachineBasicBlock &TMBB, unsigned NumT, 147113151432edace19ee867a93b5c14573df4f75d24Evan Cheng MachineBasicBlock &FMBB, unsigned NumF) const { 147213151432edace19ee867a93b5c14573df4f75d24Evan Cheng return NumT && NumF && NumT <= 2 && NumF <= 2; 147313151432edace19ee867a93b5c14573df4f75d24Evan Cheng} 147413151432edace19ee867a93b5c14573df4f75d24Evan Cheng 14758fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng/// getInstrPredicate - If instruction is predicated, returns its predicate 14768fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng/// condition, otherwise returns AL. It also returns the condition code 14778fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng/// register by reference. 14785adb66a646e2ec32265263739f5b01c3f50c176aEvan ChengARMCC::CondCodes 14795adb66a646e2ec32265263739f5b01c3f50c176aEvan Chengllvm::getInstrPredicate(const MachineInstr *MI, unsigned &PredReg) { 14808fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng int PIdx = MI->findFirstPredOperandIdx(); 14818fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng if (PIdx == -1) { 14828fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng PredReg = 0; 14838fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng return ARMCC::AL; 14848fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng } 14858fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng 14868fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng PredReg = MI->getOperand(PIdx+1).getReg(); 14878fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng return (ARMCC::CondCodes)MI->getOperand(PIdx).getImm(); 14888fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng} 14898fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng 14908fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng 14916495f63945e8dbde81f03a1dc2ab421993b9a495Evan Chengint llvm::getMatchingCondBranchOpcode(int Opc) { 14925ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng if (Opc == ARM::B) 14935ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng return ARM::Bcc; 14945ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng else if (Opc == ARM::tB) 14955ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng return ARM::tBcc; 14965ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng else if (Opc == ARM::t2B) 14975ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng return ARM::t2Bcc; 14985ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng 14995ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng llvm_unreachable("Unknown unconditional branch opcode!"); 15005ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng return 0; 15015ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng} 15025ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng 15036495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 15046495f63945e8dbde81f03a1dc2ab421993b9a495Evan Chengvoid llvm::emitARMRegPlusImmediate(MachineBasicBlock &MBB, 15056495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MachineBasicBlock::iterator &MBBI, DebugLoc dl, 15066495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned DestReg, unsigned BaseReg, int NumBytes, 15076495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ARMCC::CondCodes Pred, unsigned PredReg, 15086495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng const ARMBaseInstrInfo &TII) { 15096495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng bool isSub = NumBytes < 0; 15106495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (isSub) NumBytes = -NumBytes; 15116495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 15126495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng while (NumBytes) { 15136495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned RotAmt = ARM_AM::getSOImmValRotate(NumBytes); 15146495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned ThisVal = NumBytes & ARM_AM::rotr32(0xFF, RotAmt); 15156495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng assert(ThisVal && "Didn't extract field correctly"); 15166495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 15176495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // We will handle these bits from offset, clear them. 15186495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng NumBytes &= ~ThisVal; 15196495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 15206495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng assert(ARM_AM::getSOImmVal(ThisVal) != -1 && "Bit extraction didn't work?"); 15216495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 15226495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Build the new ADD / SUB. 15236495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned Opc = isSub ? ARM::SUBri : ARM::ADDri; 15246495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg) 15256495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng .addReg(BaseReg, RegState::Kill).addImm(ThisVal) 15266495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng .addImm((unsigned)Pred).addReg(PredReg).addReg(0); 15276495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng BaseReg = DestReg; 15286495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 15296495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng} 15306495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 1531cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Chengbool llvm::rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx, 1532cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng unsigned FrameReg, int &Offset, 1533cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng const ARMBaseInstrInfo &TII) { 15346495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned Opcode = MI.getOpcode(); 15356495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng const TargetInstrDesc &Desc = MI.getDesc(); 15366495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask); 15376495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng bool isSub = false; 1538764ab52dd80310a205c9888bf166d09dab858f90Jim Grosbach 15396495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Memory operands in inline assembly always use AddrMode2. 15406495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (Opcode == ARM::INLINEASM) 15416495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng AddrMode = ARMII::AddrMode2; 1542764ab52dd80310a205c9888bf166d09dab858f90Jim Grosbach 15436495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (Opcode == ARM::ADDri) { 15446495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng Offset += MI.getOperand(FrameRegIdx+1).getImm(); 15456495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (Offset == 0) { 15466495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Turn it into a move. 15476495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MI.setDesc(TII.get(ARM::MOVr)); 15486495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false); 15496495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MI.RemoveOperand(FrameRegIdx+1); 1550cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng Offset = 0; 1551cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng return true; 15526495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } else if (Offset < 0) { 15536495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng Offset = -Offset; 15546495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng isSub = true; 15556495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MI.setDesc(TII.get(ARM::SUBri)); 15566495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 15576495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 15586495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Common case: small offset, fits into instruction. 15596495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (ARM_AM::getSOImmVal(Offset) != -1) { 15606495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Replace the FrameIndex with sp / fp 15616495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false); 15626495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset); 1563cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng Offset = 0; 1564cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng return true; 15656495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 15666495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 15676495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Otherwise, pull as much of the immedidate into this ADDri/SUBri 15686495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // as possible. 15696495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned RotAmt = ARM_AM::getSOImmValRotate(Offset); 15706495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xFF, RotAmt); 15716495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 15726495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // We will handle these bits from offset, clear them. 15736495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng Offset &= ~ThisImmVal; 15746495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 15756495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Get the properly encoded SOImmVal field. 15766495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng assert(ARM_AM::getSOImmVal(ThisImmVal) != -1 && 15776495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng "Bit extraction didn't work?"); 15786495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MI.getOperand(FrameRegIdx+1).ChangeToImmediate(ThisImmVal); 15796495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } else { 15806495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned ImmIdx = 0; 15816495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng int InstrOffs = 0; 15826495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned NumBits = 0; 15836495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned Scale = 1; 15846495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng switch (AddrMode) { 15856495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng case ARMII::AddrMode2: { 15866495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ImmIdx = FrameRegIdx+2; 15876495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng InstrOffs = ARM_AM::getAM2Offset(MI.getOperand(ImmIdx).getImm()); 15886495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (ARM_AM::getAM2Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub) 15896495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng InstrOffs *= -1; 15906495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng NumBits = 12; 15916495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng break; 15926495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 15936495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng case ARMII::AddrMode3: { 15946495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ImmIdx = FrameRegIdx+2; 15956495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng InstrOffs = ARM_AM::getAM3Offset(MI.getOperand(ImmIdx).getImm()); 15966495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (ARM_AM::getAM3Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub) 15976495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng InstrOffs *= -1; 15986495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng NumBits = 8; 15996495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng break; 16006495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 1601baf31088f1472f48ea5ae81f0b93636cc44ca444Anton Korobeynikov case ARMII::AddrMode4: 1602a44321776ecd96fa0344335d3027758be3386e45Jim Grosbach case ARMII::AddrMode6: 1603cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng // Can't fold any offset even if it's zero. 1604cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng return false; 16056495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng case ARMII::AddrMode5: { 16066495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ImmIdx = FrameRegIdx+1; 16076495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng InstrOffs = ARM_AM::getAM5Offset(MI.getOperand(ImmIdx).getImm()); 16086495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (ARM_AM::getAM5Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub) 16096495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng InstrOffs *= -1; 16106495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng NumBits = 8; 16116495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng Scale = 4; 16126495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng break; 16136495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 16146495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng default: 16156495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng llvm_unreachable("Unsupported addressing mode!"); 16166495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng break; 16176495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 16186495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 16196495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng Offset += InstrOffs * Scale; 16206495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!"); 16216495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (Offset < 0) { 16226495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng Offset = -Offset; 16236495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng isSub = true; 16246495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 16256495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 16266495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Attempt to fold address comp. if opcode has offset bits 16276495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (NumBits > 0) { 16286495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Common case: small offset, fits into instruction. 16296495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MachineOperand &ImmOp = MI.getOperand(ImmIdx); 16306495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng int ImmedOffset = Offset / Scale; 16316495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned Mask = (1 << NumBits) - 1; 16326495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if ((unsigned)Offset <= Mask * Scale) { 16336495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Replace the FrameIndex with sp 16346495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false); 16356495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (isSub) 16366495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ImmedOffset |= 1 << NumBits; 16376495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ImmOp.ChangeToImmediate(ImmedOffset); 1638cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng Offset = 0; 1639cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng return true; 16406495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 1641764ab52dd80310a205c9888bf166d09dab858f90Jim Grosbach 16426495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Otherwise, it didn't fit. Pull in what we can to simplify the immed. 16436495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ImmedOffset = ImmedOffset & Mask; 16446495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (isSub) 16456495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ImmedOffset |= 1 << NumBits; 16466495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ImmOp.ChangeToImmediate(ImmedOffset); 16476495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng Offset &= ~(Mask*Scale); 16486495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 16496495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 16506495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 1651cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng Offset = (isSub) ? -Offset : Offset; 1652cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng return Offset == 0; 16536495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng} 1654