ARMBaseInstrInfo.cpp revision 97ecb83dffb5ff78ff84e9da21189268f52c63b2
131d157ae1ac2cd9c787dc3c1d28e64c682803844Jia Liu//===-- ARMBaseInstrInfo.cpp - ARM Instruction Information ----------------===// 2334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// 3334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// The LLVM Compiler Infrastructure 4334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// 5334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// This file is distributed under the University of Illinois Open Source 6334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// License. See LICENSE.TXT for details. 7334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// 8334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin//===----------------------------------------------------------------------===// 9334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// 10334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// This file contains the Base ARM implementation of the TargetInstrInfo class. 11334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// 12334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin//===----------------------------------------------------------------------===// 13334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 14334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "ARMBaseInstrInfo.h" 15334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "ARM.h" 160e5233a9e5ee9385c6a940e3985194d77bee0bbbCraig Topper#include "ARMBaseRegisterInfo.h" 17d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng#include "ARMConstantPoolValue.h" 1848575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng#include "ARMHazardRecognizer.h" 19334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "ARMMachineFunctionInfo.h" 20ee04a6d3a40c3017124e3fd89a0db473a2824498Evan Cheng#include "MCTargetDesc/ARMAddressingModes.h" 21fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng#include "llvm/Constants.h" 22fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng#include "llvm/Function.h" 23fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng#include "llvm/GlobalValue.h" 24334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "llvm/CodeGen/LiveVariables.h" 25d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng#include "llvm/CodeGen/MachineConstantPool.h" 26334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "llvm/CodeGen/MachineFrameInfo.h" 27334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "llvm/CodeGen/MachineInstrBuilder.h" 28334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "llvm/CodeGen/MachineJumpTableInfo.h" 29249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov#include "llvm/CodeGen/MachineMemOperand.h" 302457f2c66184e978d4ed8fa9e2128effff26cb0bEvan Cheng#include "llvm/CodeGen/MachineRegisterInfo.h" 31ee04a6d3a40c3017124e3fd89a0db473a2824498Evan Cheng#include "llvm/CodeGen/SelectionDAGNodes.h" 32af76e592c7f9deff0e55c13dbb4a34f07f1c7f64Chris Lattner#include "llvm/MC/MCAsmInfo.h" 33f81b7f6069b27c0a515070dcb392f6828437412fJakub Staszak#include "llvm/Support/BranchProbability.h" 34334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "llvm/Support/CommandLine.h" 35f95215f551949d5e5adfbf4753aa833b9009b77aAnton Korobeynikov#include "llvm/Support/Debug.h" 36c25e7581b9b8088910da31702d4ca21c4734c6d7Torok Edwin#include "llvm/Support/ErrorHandling.h" 3740a5eb18b031fa1a5e9697e21e251e613d441cc5Bill Wendling#include "llvm/ADT/STLExtras.h" 3822fee2dff4c43b551aefa44a96ca74fcade6bfacEvan Cheng 394db3cffe94a5285239cc0056f939c6b74a5ca0b6Evan Cheng#define GET_INSTRINFO_CTOR 4022fee2dff4c43b551aefa44a96ca74fcade6bfacEvan Cheng#include "ARMGenInstrInfo.inc" 4122fee2dff4c43b551aefa44a96ca74fcade6bfacEvan Cheng 42334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinusing namespace llvm; 43334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 44334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinstatic cl::opt<bool> 45334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinEnableARM3Addr("enable-arm-3-addr-conv", cl::Hidden, 46334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin cl::desc("Enable ARM 2-addr to 3-addr conv")); 47334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 4861545829832ba0375249c42c84843d0b62c8f55fJakob Stoklund Olesenstatic cl::opt<bool> 493805d85e38c29d9106c758b63851eb847201f315Jakob Stoklund OlesenWidenVMOVS("widen-vmovs", cl::Hidden, cl::init(true), 5061545829832ba0375249c42c84843d0b62c8f55fJakob Stoklund Olesen cl::desc("Widen ARM vmovs to vmovd when possible")); 5161545829832ba0375249c42c84843d0b62c8f55fJakob Stoklund Olesen 5248575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng/// ARM_MLxEntry - Record information about MLA / MLS instructions. 5348575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Chengstruct ARM_MLxEntry { 54cd2859eef83708c00330c94f6842499b48d5ed02Craig Topper uint16_t MLxOpc; // MLA / MLS opcode 55cd2859eef83708c00330c94f6842499b48d5ed02Craig Topper uint16_t MulOpc; // Expanded multiplication opcode 56cd2859eef83708c00330c94f6842499b48d5ed02Craig Topper uint16_t AddSubOpc; // Expanded add / sub opcode 5748575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng bool NegAcc; // True if the acc is negated before the add / sub. 5848575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng bool HasLane; // True if instruction has an extra "lane" operand. 5948575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng}; 6048575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng 6148575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Chengstatic const ARM_MLxEntry ARM_MLxTable[] = { 6248575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng // MLxOpc, MulOpc, AddSubOpc, NegAcc, HasLane 6348575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng // fp scalar ops 6448575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng { ARM::VMLAS, ARM::VMULS, ARM::VADDS, false, false }, 6548575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng { ARM::VMLSS, ARM::VMULS, ARM::VSUBS, false, false }, 6648575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng { ARM::VMLAD, ARM::VMULD, ARM::VADDD, false, false }, 6748575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng { ARM::VMLSD, ARM::VMULD, ARM::VSUBD, false, false }, 6848575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng { ARM::VNMLAS, ARM::VNMULS, ARM::VSUBS, true, false }, 6948575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng { ARM::VNMLSS, ARM::VMULS, ARM::VSUBS, true, false }, 7048575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng { ARM::VNMLAD, ARM::VNMULD, ARM::VSUBD, true, false }, 7148575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng { ARM::VNMLSD, ARM::VMULD, ARM::VSUBD, true, false }, 7248575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng 7348575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng // fp SIMD ops 7448575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng { ARM::VMLAfd, ARM::VMULfd, ARM::VADDfd, false, false }, 7548575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng { ARM::VMLSfd, ARM::VMULfd, ARM::VSUBfd, false, false }, 7648575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng { ARM::VMLAfq, ARM::VMULfq, ARM::VADDfq, false, false }, 7748575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng { ARM::VMLSfq, ARM::VMULfq, ARM::VSUBfq, false, false }, 7848575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng { ARM::VMLAslfd, ARM::VMULslfd, ARM::VADDfd, false, true }, 7948575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng { ARM::VMLSslfd, ARM::VMULslfd, ARM::VSUBfd, false, true }, 8048575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng { ARM::VMLAslfq, ARM::VMULslfq, ARM::VADDfq, false, true }, 8148575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng { ARM::VMLSslfq, ARM::VMULslfq, ARM::VSUBfq, false, true }, 8248575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng}; 8348575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng 84f95215f551949d5e5adfbf4753aa833b9009b77aAnton KorobeynikovARMBaseInstrInfo::ARMBaseInstrInfo(const ARMSubtarget& STI) 854db3cffe94a5285239cc0056f939c6b74a5ca0b6Evan Cheng : ARMGenInstrInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP), 86f95215f551949d5e5adfbf4753aa833b9009b77aAnton Korobeynikov Subtarget(STI) { 8748575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng for (unsigned i = 0, e = array_lengthof(ARM_MLxTable); i != e; ++i) { 8848575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng if (!MLxEntryMap.insert(std::make_pair(ARM_MLxTable[i].MLxOpc, i)).second) 8948575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng assert(false && "Duplicated entries?"); 9048575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng MLxHazardOpcodes.insert(ARM_MLxTable[i].AddSubOpc); 9148575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng MLxHazardOpcodes.insert(ARM_MLxTable[i].MulOpc); 9248575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng } 9348575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng} 9448575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng 952da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick// Use a ScoreboardHazardRecognizer for prepass ARM scheduling. TargetInstrImpl 962da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick// currently defaults to no prepass hazard recognizer. 9748575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan ChengScheduleHazardRecognizer *ARMBaseInstrInfo:: 982da8bc8a5f7705ac131184cd247f48500da0d74eAndrew TrickCreateTargetHazardRecognizer(const TargetMachine *TM, 992da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick const ScheduleDAG *DAG) const { 100c8bfd1d78ff9a307d1d4cb57cce4549b538e60f4Andrew Trick if (usePreRAHazardRecognizer()) { 1012da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick const InstrItineraryData *II = TM->getInstrItineraryData(); 1022da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick return new ScoreboardHazardRecognizer(II, DAG, "pre-RA-sched"); 1032da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick } 1042da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick return TargetInstrInfoImpl::CreateTargetHazardRecognizer(TM, DAG); 1052da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick} 1062da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick 1072da8bc8a5f7705ac131184cd247f48500da0d74eAndrew TrickScheduleHazardRecognizer *ARMBaseInstrInfo:: 1082da8bc8a5f7705ac131184cd247f48500da0d74eAndrew TrickCreateTargetPostRAHazardRecognizer(const InstrItineraryData *II, 1092da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick const ScheduleDAG *DAG) const { 11048575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng if (Subtarget.isThumb2() || Subtarget.hasVFP2()) 11148575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng return (ScheduleHazardRecognizer *) 1122da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick new ARMHazardRecognizer(II, *this, getRegisterInfo(), Subtarget, DAG); 1132da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick return TargetInstrInfoImpl::CreateTargetPostRAHazardRecognizer(II, DAG); 114334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 115334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 116334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinMachineInstr * 117334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinARMBaseInstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI, 118334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineBasicBlock::iterator &MBBI, 119334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin LiveVariables *LV) const { 12078703ddafe3d037f75d8ca188e4829d238289ac3Evan Cheng // FIXME: Thumb2 support. 12178703ddafe3d037f75d8ca188e4829d238289ac3Evan Cheng 122334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (!EnableARM3Addr) 123334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return NULL; 124334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 125334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineInstr *MI = MBBI; 126334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineFunction &MF = *MI->getParent()->getParent(); 12799405df044f2c584242e711cc9023ec90356da82Bruno Cardoso Lopes uint64_t TSFlags = MI->getDesc().TSFlags; 128334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool isPre = false; 129334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin switch ((TSFlags & ARMII::IndexModeMask) >> ARMII::IndexModeShift) { 130334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin default: return NULL; 131334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMII::IndexModePre: 132334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin isPre = true; 133334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin break; 134334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMII::IndexModePost: 135334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin break; 136334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 137334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 138334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Try splitting an indexed load/store to an un-indexed one plus an add/sub 139334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // operation. 140334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned MemOpc = getUnindexedOpcode(MI->getOpcode()); 141334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (MemOpc == 0) 142334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return NULL; 143334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 144334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineInstr *UpdateMI = NULL; 145334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineInstr *MemMI = NULL; 146334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned AddrMode = (TSFlags & ARMII::AddrModeMask); 147e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng const MCInstrDesc &MCID = MI->getDesc(); 148e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng unsigned NumOps = MCID.getNumOperands(); 1495a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng bool isLoad = !MI->mayStore(); 150334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const MachineOperand &WB = isLoad ? MI->getOperand(1) : MI->getOperand(0); 151334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const MachineOperand &Base = MI->getOperand(2); 152334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const MachineOperand &Offset = MI->getOperand(NumOps-3); 153334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned WBReg = WB.getReg(); 154334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned BaseReg = Base.getReg(); 155334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned OffReg = Offset.getReg(); 156334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned OffImm = MI->getOperand(NumOps-2).getImm(); 157334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin ARMCC::CondCodes Pred = (ARMCC::CondCodes)MI->getOperand(NumOps-1).getImm(); 158334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin switch (AddrMode) { 159bc2198133a1836598b54b943420748e75d5dea94Craig Topper default: llvm_unreachable("Unknown indexed op!"); 160334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMII::AddrMode2: { 161334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool isSub = ARM_AM::getAM2Op(OffImm) == ARM_AM::sub; 162334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned Amt = ARM_AM::getAM2Offset(OffImm); 163334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (OffReg == 0) { 164e7cbe4118b7ddf05032ff8772a98c51e1637bb5cEvan Cheng if (ARM_AM::getSOImmVal(Amt) == -1) 165334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Can't encode it in a so_imm operand. This transformation will 166334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // add more than 1 instruction. Abandon! 167334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return NULL; 168334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin UpdateMI = BuildMI(MF, MI->getDebugLoc(), 16978703ddafe3d037f75d8ca188e4829d238289ac3Evan Cheng get(isSub ? ARM::SUBri : ARM::ADDri), WBReg) 170e7cbe4118b7ddf05032ff8772a98c51e1637bb5cEvan Cheng .addReg(BaseReg).addImm(Amt) 171334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addImm(Pred).addReg(0).addReg(0); 172334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } else if (Amt != 0) { 173334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin ARM_AM::ShiftOpc ShOpc = ARM_AM::getAM2ShiftOpc(OffImm); 174334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned SOOpc = ARM_AM::getSORegOpc(ShOpc, Amt); 175334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin UpdateMI = BuildMI(MF, MI->getDebugLoc(), 17692a202213bb4c20301abf6ab64e46df3695e60bfOwen Anderson get(isSub ? ARM::SUBrsi : ARM::ADDrsi), WBReg) 177334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(BaseReg).addReg(OffReg).addReg(0).addImm(SOOpc) 178334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addImm(Pred).addReg(0).addReg(0); 179334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } else 180334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin UpdateMI = BuildMI(MF, MI->getDebugLoc(), 18178703ddafe3d037f75d8ca188e4829d238289ac3Evan Cheng get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg) 182334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(BaseReg).addReg(OffReg) 183334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addImm(Pred).addReg(0).addReg(0); 184334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin break; 185334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 186334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMII::AddrMode3 : { 187334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool isSub = ARM_AM::getAM3Op(OffImm) == ARM_AM::sub; 188334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned Amt = ARM_AM::getAM3Offset(OffImm); 189334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (OffReg == 0) 190334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Immediate is 8-bits. It's guaranteed to fit in a so_imm operand. 191334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin UpdateMI = BuildMI(MF, MI->getDebugLoc(), 19278703ddafe3d037f75d8ca188e4829d238289ac3Evan Cheng get(isSub ? ARM::SUBri : ARM::ADDri), WBReg) 193334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(BaseReg).addImm(Amt) 194334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addImm(Pred).addReg(0).addReg(0); 195334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin else 196334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin UpdateMI = BuildMI(MF, MI->getDebugLoc(), 19778703ddafe3d037f75d8ca188e4829d238289ac3Evan Cheng get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg) 198334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(BaseReg).addReg(OffReg) 199334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addImm(Pred).addReg(0).addReg(0); 200334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin break; 201334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 202334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 203334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 204334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin std::vector<MachineInstr*> NewMIs; 205334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (isPre) { 206334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (isLoad) 207334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MemMI = BuildMI(MF, MI->getDebugLoc(), 208334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin get(MemOpc), MI->getOperand(0).getReg()) 2093e5561247202bae994dd259a2d8dc4eff8f799f3Jim Grosbach .addReg(WBReg).addImm(0).addImm(Pred); 210334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin else 211334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MemMI = BuildMI(MF, MI->getDebugLoc(), 212334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin get(MemOpc)).addReg(MI->getOperand(1).getReg()) 213334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(WBReg).addReg(0).addImm(0).addImm(Pred); 214334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin NewMIs.push_back(MemMI); 215334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin NewMIs.push_back(UpdateMI); 216334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } else { 217334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (isLoad) 218334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MemMI = BuildMI(MF, MI->getDebugLoc(), 219334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin get(MemOpc), MI->getOperand(0).getReg()) 2203e5561247202bae994dd259a2d8dc4eff8f799f3Jim Grosbach .addReg(BaseReg).addImm(0).addImm(Pred); 221334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin else 222334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MemMI = BuildMI(MF, MI->getDebugLoc(), 223334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin get(MemOpc)).addReg(MI->getOperand(1).getReg()) 224334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred); 225334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (WB.isDead()) 226334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin UpdateMI->getOperand(0).setIsDead(); 227334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin NewMIs.push_back(UpdateMI); 228334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin NewMIs.push_back(MemMI); 229334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 230334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 231334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Transfer LiveVariables states, kill / dead info. 232334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (LV) { 233334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 234334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineOperand &MO = MI->getOperand(i); 235c9df025e33ac435adb3b3318d237c36ca7cec659Jakob Stoklund Olesen if (MO.isReg() && TargetRegisterInfo::isVirtualRegister(MO.getReg())) { 236334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned Reg = MO.getReg(); 237334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 238334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin LiveVariables::VarInfo &VI = LV->getVarInfo(Reg); 239334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (MO.isDef()) { 240334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineInstr *NewMI = (Reg == WBReg) ? UpdateMI : MemMI; 241334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (MO.isDead()) 242334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin LV->addVirtualRegisterDead(Reg, NewMI); 243334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 244334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (MO.isUse() && MO.isKill()) { 245334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin for (unsigned j = 0; j < 2; ++j) { 246334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Look at the two new MI's in reverse order. 247334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineInstr *NewMI = NewMIs[j]; 248334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (!NewMI->readsRegister(Reg)) 249334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin continue; 250334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin LV->addVirtualRegisterKilled(Reg, NewMI); 251334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (VI.removeKill(MI)) 252334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin VI.Kills.push_back(NewMI); 253334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin break; 254334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 255334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 256334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 257334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 258334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 259334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 260334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MFI->insert(MBBI, NewMIs[1]); 261334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MFI->insert(MBBI, NewMIs[0]); 262334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return NewMIs[0]; 263334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 264334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 265334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// Branch analysis. 266334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinbool 267334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinARMBaseInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB, 268334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineBasicBlock *&FBB, 269334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin SmallVectorImpl<MachineOperand> &Cond, 270334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool AllowModify) const { 271334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // If the block has no terminators, it just falls into the block after it. 272334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineBasicBlock::iterator I = MBB.end(); 27393d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen if (I == MBB.begin()) 27493d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen return false; 27593d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen --I; 27693d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen while (I->isDebugValue()) { 27793d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen if (I == MBB.begin()) 27893d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen return false; 27993d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen --I; 28093d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen } 28193d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen if (!isUnpredicatedTerminator(I)) 282334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 283334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 284334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Get the last instruction in the block. 285334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineInstr *LastInst = I; 286334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 287334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // If there is only one terminator instruction, process it. 288334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned LastOpc = LastInst->getOpcode(); 289334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) { 2905ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng if (isUncondBranchOpcode(LastOpc)) { 291334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin TBB = LastInst->getOperand(0).getMBB(); 292334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 293334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 2945ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng if (isCondBranchOpcode(LastOpc)) { 295334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Block ends with fall-through condbranch. 296334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin TBB = LastInst->getOperand(0).getMBB(); 297334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin Cond.push_back(LastInst->getOperand(1)); 298334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin Cond.push_back(LastInst->getOperand(2)); 299334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 300334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 301334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; // Can't handle indirect branch. 302334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 303334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 304334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Get the instruction before it if it is a terminator. 305334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineInstr *SecondLastInst = I; 306108c8724663354050dc09bb1262c3e4511adf82fEvan Cheng unsigned SecondLastOpc = SecondLastInst->getOpcode(); 307108c8724663354050dc09bb1262c3e4511adf82fEvan Cheng 308108c8724663354050dc09bb1262c3e4511adf82fEvan Cheng // If AllowModify is true and the block ends with two or more unconditional 309108c8724663354050dc09bb1262c3e4511adf82fEvan Cheng // branches, delete all but the first unconditional branch. 310108c8724663354050dc09bb1262c3e4511adf82fEvan Cheng if (AllowModify && isUncondBranchOpcode(LastOpc)) { 311108c8724663354050dc09bb1262c3e4511adf82fEvan Cheng while (isUncondBranchOpcode(SecondLastOpc)) { 312108c8724663354050dc09bb1262c3e4511adf82fEvan Cheng LastInst->eraseFromParent(); 313108c8724663354050dc09bb1262c3e4511adf82fEvan Cheng LastInst = SecondLastInst; 314108c8724663354050dc09bb1262c3e4511adf82fEvan Cheng LastOpc = LastInst->getOpcode(); 315676e258366dd17a0b4ee6ac66914237ce181202eEvan Cheng if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) { 316676e258366dd17a0b4ee6ac66914237ce181202eEvan Cheng // Return now the only terminator is an unconditional branch. 317676e258366dd17a0b4ee6ac66914237ce181202eEvan Cheng TBB = LastInst->getOperand(0).getMBB(); 318676e258366dd17a0b4ee6ac66914237ce181202eEvan Cheng return false; 319676e258366dd17a0b4ee6ac66914237ce181202eEvan Cheng } else { 320108c8724663354050dc09bb1262c3e4511adf82fEvan Cheng SecondLastInst = I; 321108c8724663354050dc09bb1262c3e4511adf82fEvan Cheng SecondLastOpc = SecondLastInst->getOpcode(); 322108c8724663354050dc09bb1262c3e4511adf82fEvan Cheng } 323108c8724663354050dc09bb1262c3e4511adf82fEvan Cheng } 324108c8724663354050dc09bb1262c3e4511adf82fEvan Cheng } 325334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 326334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // If there are three terminators, we don't know what sort of block this is. 327334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(--I)) 328334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; 329334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 3305ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng // If the block ends with a B and a Bcc, handle it. 3315ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng if (isCondBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) { 332334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin TBB = SecondLastInst->getOperand(0).getMBB(); 333334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin Cond.push_back(SecondLastInst->getOperand(1)); 334334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin Cond.push_back(SecondLastInst->getOperand(2)); 335334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin FBB = LastInst->getOperand(0).getMBB(); 336334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 337334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 338334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 339334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // If the block ends with two unconditional branches, handle it. The second 340334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // one is not executed, so remove it. 3415ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng if (isUncondBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) { 342334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin TBB = SecondLastInst->getOperand(0).getMBB(); 343334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin I = LastInst; 344334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (AllowModify) 345334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin I->eraseFromParent(); 346334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 347334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 348334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 349334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // ...likewise if it ends with a branch table followed by an unconditional 350334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // branch. The branch folder can create these, and we must get rid of them for 351334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // correctness of Thumb constant islands. 3528d4de5abfa1bcd974554ea14904ebf7af289e84dBob Wilson if ((isJumpTableBranchOpcode(SecondLastOpc) || 3538d4de5abfa1bcd974554ea14904ebf7af289e84dBob Wilson isIndirectBranchOpcode(SecondLastOpc)) && 3545ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng isUncondBranchOpcode(LastOpc)) { 355334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin I = LastInst; 356334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (AllowModify) 357334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin I->eraseFromParent(); 358334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; 359334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 360334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 361334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Otherwise, can't handle this. 362334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; 363334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 364334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 365334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 366334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinunsigned ARMBaseInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const { 367334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineBasicBlock::iterator I = MBB.end(); 368334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (I == MBB.begin()) return 0; 369334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin --I; 37093d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen while (I->isDebugValue()) { 37193d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen if (I == MBB.begin()) 37293d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen return 0; 37393d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen --I; 37493d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen } 3755ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng if (!isUncondBranchOpcode(I->getOpcode()) && 3765ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng !isCondBranchOpcode(I->getOpcode())) 377334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 0; 378334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 379334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Remove the branch. 380334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin I->eraseFromParent(); 381334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 382334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin I = MBB.end(); 383334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 384334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (I == MBB.begin()) return 1; 385334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin --I; 3865ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng if (!isCondBranchOpcode(I->getOpcode())) 387334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 1; 388334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 389334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Remove the branch. 390334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin I->eraseFromParent(); 391334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 2; 392334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 393334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 394334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinunsigned 395334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinARMBaseInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 3963bf912593301152b65accb9d9c37a95172f1df5aStuart Hastings MachineBasicBlock *FBB, 3973bf912593301152b65accb9d9c37a95172f1df5aStuart Hastings const SmallVectorImpl<MachineOperand> &Cond, 3983bf912593301152b65accb9d9c37a95172f1df5aStuart Hastings DebugLoc DL) const { 3996495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ARMFunctionInfo *AFI = MBB.getParent()->getInfo<ARMFunctionInfo>(); 4006495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng int BOpc = !AFI->isThumbFunction() 4016495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ? ARM::B : (AFI->isThumb2Function() ? ARM::t2B : ARM::tB); 4026495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng int BccOpc = !AFI->isThumbFunction() 4036495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ? ARM::Bcc : (AFI->isThumb2Function() ? ARM::t2Bcc : ARM::tBcc); 40451f6a7abf27fc92c3d8904c2334feab8b498e8e9Owen Anderson bool isThumb = AFI->isThumbFunction() || AFI->isThumb2Function(); 405e23dc9c0ef50b0a1934c04c1786f3a0478d62f41Andrew Trick 406334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Shouldn't be a fall through. 407334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin assert(TBB && "InsertBranch must not be told to insert a fallthrough"); 408334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin assert((Cond.size() == 2 || Cond.size() == 0) && 409334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin "ARM branch conditions have two components!"); 410334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 411334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (FBB == 0) { 412112fb73502d54dd7dd61ae2de24c92d4df181294Owen Anderson if (Cond.empty()) { // Unconditional branch? 41351f6a7abf27fc92c3d8904c2334feab8b498e8e9Owen Anderson if (isThumb) 41451f6a7abf27fc92c3d8904c2334feab8b498e8e9Owen Anderson BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB).addImm(ARMCC::AL).addReg(0); 41551f6a7abf27fc92c3d8904c2334feab8b498e8e9Owen Anderson else 41651f6a7abf27fc92c3d8904c2334feab8b498e8e9Owen Anderson BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB); 417112fb73502d54dd7dd61ae2de24c92d4df181294Owen Anderson } else 4183bf912593301152b65accb9d9c37a95172f1df5aStuart Hastings BuildMI(&MBB, DL, get(BccOpc)).addMBB(TBB) 419334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()); 420334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 1; 421334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 422334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 423334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Two-way conditional branch. 4243bf912593301152b65accb9d9c37a95172f1df5aStuart Hastings BuildMI(&MBB, DL, get(BccOpc)).addMBB(TBB) 425334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()); 42651f6a7abf27fc92c3d8904c2334feab8b498e8e9Owen Anderson if (isThumb) 42751f6a7abf27fc92c3d8904c2334feab8b498e8e9Owen Anderson BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB).addImm(ARMCC::AL).addReg(0); 42851f6a7abf27fc92c3d8904c2334feab8b498e8e9Owen Anderson else 42951f6a7abf27fc92c3d8904c2334feab8b498e8e9Owen Anderson BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB); 430334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 2; 431334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 432334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 433334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinbool ARMBaseInstrInfo:: 434334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const { 435334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin ARMCC::CondCodes CC = (ARMCC::CondCodes)(int)Cond[0].getImm(); 436334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin Cond[0].setImm(ARMCC::getOppositeCondition(CC)); 437334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 438334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 439334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 440ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Chengbool ARMBaseInstrInfo::isPredicated(const MachineInstr *MI) const { 441ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng if (MI->isBundle()) { 442ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng MachineBasicBlock::const_instr_iterator I = MI; 443ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end(); 444ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng while (++I != E && I->isInsideBundle()) { 445ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng int PIdx = I->findFirstPredOperandIdx(); 446ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng if (PIdx != -1 && I->getOperand(PIdx).getImm() != ARMCC::AL) 447ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng return true; 448ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng } 449ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng return false; 450ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng } 451ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng 452ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng int PIdx = MI->findFirstPredOperandIdx(); 453ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng return PIdx != -1 && MI->getOperand(PIdx).getImm() != ARMCC::AL; 454ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng} 455ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng 456334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinbool ARMBaseInstrInfo:: 457334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinPredicateInstruction(MachineInstr *MI, 458334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const SmallVectorImpl<MachineOperand> &Pred) const { 459334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned Opc = MI->getOpcode(); 4605ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng if (isUncondBranchOpcode(Opc)) { 4615ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng MI->setDesc(get(getMatchingCondBranchOpcode(Opc))); 462334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI->addOperand(MachineOperand::CreateImm(Pred[0].getImm())); 463334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI->addOperand(MachineOperand::CreateReg(Pred[1].getReg(), false)); 464334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; 465334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 466334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 467334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin int PIdx = MI->findFirstPredOperandIdx(); 468334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (PIdx != -1) { 469334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineOperand &PMO = MI->getOperand(PIdx); 470334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin PMO.setImm(Pred[0].getImm()); 471334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI->getOperand(PIdx+1).setReg(Pred[1].getReg()); 472334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; 473334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 474334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 475334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 476334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 477334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinbool ARMBaseInstrInfo:: 478334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinSubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1, 479334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const SmallVectorImpl<MachineOperand> &Pred2) const { 480334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (Pred1.size() > 2 || Pred2.size() > 2) 481334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 482334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 483334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin ARMCC::CondCodes CC1 = (ARMCC::CondCodes)Pred1[0].getImm(); 484334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin ARMCC::CondCodes CC2 = (ARMCC::CondCodes)Pred2[0].getImm(); 485334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (CC1 == CC2) 486334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; 487334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 488334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin switch (CC1) { 489334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin default: 490334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 491334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMCC::AL: 492334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; 493334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMCC::HS: 494334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return CC2 == ARMCC::HI; 495334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMCC::LS: 496334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return CC2 == ARMCC::LO || CC2 == ARMCC::EQ; 497334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMCC::GE: 498334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return CC2 == ARMCC::GT; 499334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMCC::LE: 500334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return CC2 == ARMCC::LT; 501334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 502334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 503334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 504334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinbool ARMBaseInstrInfo::DefinesPredicate(MachineInstr *MI, 505334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin std::vector<MachineOperand> &Pred) const { 506334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool Found = false; 507334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 508334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const MachineOperand &MO = MI->getOperand(i); 5092420b558de5d291d8503c1339004e5b5bf99a48aJakob Stoklund Olesen if ((MO.isRegMask() && MO.clobbersPhysReg(ARM::CPSR)) || 5102420b558de5d291d8503c1339004e5b5bf99a48aJakob Stoklund Olesen (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR)) { 511334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin Pred.push_back(MO); 512334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin Found = true; 513334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 514334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 515334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 516334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return Found; 517334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 518334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 519ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng/// isPredicable - Return true if the specified instruction can be predicated. 520ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng/// By default, this returns true for every instruction with a 521ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng/// PredicateOperand. 522ac0869dc8a7986855c5557cc67d4709600158ef5Evan Chengbool ARMBaseInstrInfo::isPredicable(MachineInstr *MI) const { 5235a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng if (!MI->isPredicable()) 524ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng return false; 525ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng 5265a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng if ((MI->getDesc().TSFlags & ARMII::DomainMask) == ARMII::DomainNEON) { 527ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng ARMFunctionInfo *AFI = 528ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng MI->getParent()->getParent()->getInfo<ARMFunctionInfo>(); 529d7f0810c934a7d13acb28c42d737ce58ec990ea8Evan Cheng return AFI->isThumb2Function(); 530ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng } 531ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng return true; 532ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng} 533334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 53456856b1f46ec1f073ceef4e826c544b8b1691608Chris Lattner/// FIXME: Works around a gcc miscompilation with -fstrict-aliasing. 53519e57025d458d3cb50804fd821fd89b868a819bdChandler CarruthLLVM_ATTRIBUTE_NOINLINE 536334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinstatic unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT, 53756856b1f46ec1f073ceef4e826c544b8b1691608Chris Lattner unsigned JTI); 538334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinstatic unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT, 539334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned JTI) { 54056856b1f46ec1f073ceef4e826c544b8b1691608Chris Lattner assert(JTI < JT.size()); 541334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return JT[JTI].MBBs.size(); 542334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 543334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 544334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin/// GetInstSize - Return the size of the specified MachineInstr. 545334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin/// 546334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinunsigned ARMBaseInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const { 547334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const MachineBasicBlock &MBB = *MI->getParent(); 548334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const MachineFunction *MF = MBB.getParent(); 54933adcfb4d217f5f23d9bde8ba02b8e48f9605fc5Chris Lattner const MCAsmInfo *MAI = MF->getTarget().getMCAsmInfo(); 550334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 551e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng const MCInstrDesc &MCID = MI->getDesc(); 55216884415db751c75f2133bd04921393c792b1158Owen Anderson if (MCID.getSize()) 55316884415db751c75f2133bd04921393c792b1158Owen Anderson return MCID.getSize(); 554334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 5554d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie // If this machine instr is an inline asm, measure it. 5564d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie if (MI->getOpcode() == ARM::INLINEASM) 5574d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie return getInlineAsmLength(MI->getOperand(0).getSymbolName(), *MAI); 5584d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie if (MI->isLabel()) 5594d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie return 0; 5604d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie unsigned Opc = MI->getOpcode(); 5614d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie switch (Opc) { 5624d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie case TargetOpcode::IMPLICIT_DEF: 5634d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie case TargetOpcode::KILL: 5644d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie case TargetOpcode::PROLOG_LABEL: 5654d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie case TargetOpcode::EH_LABEL: 5664d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie case TargetOpcode::DBG_VALUE: 5674d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie return 0; 5684d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie case TargetOpcode::BUNDLE: 5694d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie return getInstBundleLength(MI); 5704d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie case ARM::MOVi16_ga_pcrel: 5714d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie case ARM::MOVTi16_ga_pcrel: 5724d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie case ARM::t2MOVi16_ga_pcrel: 5734d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie case ARM::t2MOVTi16_ga_pcrel: 5744d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie return 4; 5754d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie case ARM::MOVi32imm: 5764d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie case ARM::t2MOVi32imm: 5774d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie return 8; 5784d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie case ARM::CONSTPOOL_ENTRY: 5794d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie // If this machine instr is a constant pool entry, its size is recorded as 5804d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie // operand #2. 5814d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie return MI->getOperand(2).getImm(); 5824d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie case ARM::Int_eh_sjlj_longjmp: 5834d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie return 16; 5844d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie case ARM::tInt_eh_sjlj_longjmp: 5854d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie return 10; 5864d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie case ARM::Int_eh_sjlj_setjmp: 5874d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie case ARM::Int_eh_sjlj_setjmp_nofp: 5884d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie return 20; 5894d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie case ARM::tInt_eh_sjlj_setjmp: 5904d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie case ARM::t2Int_eh_sjlj_setjmp: 5914d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie case ARM::t2Int_eh_sjlj_setjmp_nofp: 5924d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie return 12; 5934d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie case ARM::BR_JTr: 5944d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie case ARM::BR_JTm: 5954d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie case ARM::BR_JTadd: 5964d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie case ARM::tBR_JTr: 5974d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie case ARM::t2BR_JT: 5984d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie case ARM::t2TBB_JT: 5994d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie case ARM::t2TBH_JT: { 6004d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie // These are jumptable branches, i.e. a branch followed by an inlined 6014d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie // jumptable. The size is 4 + 4 * number of entries. For TBB, each 6024d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie // entry is one byte; TBH two byte each. 6034d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie unsigned EntrySize = (Opc == ARM::t2TBB_JT) 6044d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie ? 1 : ((Opc == ARM::t2TBH_JT) ? 2 : 4); 6054d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie unsigned NumOps = MCID.getNumOperands(); 6064d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie MachineOperand JTOP = 6074d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie MI->getOperand(NumOps - (MI->isPredicable() ? 3 : 2)); 6084d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie unsigned JTI = JTOP.getIndex(); 6094d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo(); 6104d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie assert(MJTI != 0); 6114d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables(); 6124d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie assert(JTI < JT.size()); 6134d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie // Thumb instructions are 2 byte aligned, but JT entries are 4 byte 6144d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie // 4 aligned. The assembler / linker may add 2 byte padding just before 6154d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie // the JT entries. The size does not include this padding; the 6164d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie // constant islands pass does separate bookkeeping for it. 6174d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie // FIXME: If we know the size of the function is less than (1 << 16) *2 6184d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie // bytes, we can use 16-bit entries instead. Then there won't be an 6194d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie // alignment issue. 6204d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie unsigned InstSize = (Opc == ARM::tBR_JTr || Opc == ARM::t2BR_JT) ? 2 : 4; 6214d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie unsigned NumEntries = getNumJTEntries(JT, JTI); 6224d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie if (Opc == ARM::t2TBB_JT && (NumEntries & 1)) 6234d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie // Make sure the instruction that follows TBB is 2-byte aligned. 6244d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie // FIXME: Constant island pass should insert an "ALIGN" instruction 6254d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie // instead. 6264d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie ++NumEntries; 6274d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie return NumEntries * EntrySize + InstSize; 6284d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie } 6294d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie default: 6304d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie // Otherwise, pseudo-instruction sizes are zero. 6314d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie return 0; 6324d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie } 633334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 634334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 635ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Chengunsigned ARMBaseInstrInfo::getInstBundleLength(const MachineInstr *MI) const { 636ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng unsigned Size = 0; 637ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng MachineBasicBlock::const_instr_iterator I = MI; 638ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end(); 639ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng while (++I != E && I->isInsideBundle()) { 640ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng assert(!I->isBundle() && "No nested bundle!"); 641ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng Size += GetInstSizeInBytes(&*I); 642ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng } 643ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng return Size; 644ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng} 645ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng 646ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesenvoid ARMBaseInstrInfo::copyPhysReg(MachineBasicBlock &MBB, 647ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen MachineBasicBlock::iterator I, DebugLoc DL, 648ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen unsigned DestReg, unsigned SrcReg, 649ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen bool KillSrc) const { 650ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen bool GPRDest = ARM::GPRRegClass.contains(DestReg); 651ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen bool GPRSrc = ARM::GPRRegClass.contains(SrcReg); 652ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen 653ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen if (GPRDest && GPRSrc) { 654ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen AddDefaultCC(AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::MOVr), DestReg) 655ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen .addReg(SrcReg, getKillRegState(KillSrc)))); 656ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen return; 6577bfdca0206f51132b26094c6f83a5ac97ee0f943David Goodwin } 658334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 659ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen bool SPRDest = ARM::SPRRegClass.contains(DestReg); 660ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen bool SPRSrc = ARM::SPRRegClass.contains(SrcReg); 661ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen 662e5038e191db82d4d92fdeec1b5bce5cae21f6d8fChad Rosier unsigned Opc = 0; 663142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen if (SPRDest && SPRSrc) 664ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen Opc = ARM::VMOVS; 665142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen else if (GPRDest && SPRSrc) 666ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen Opc = ARM::VMOVRS; 667ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen else if (SPRDest && GPRSrc) 668ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen Opc = ARM::VMOVSR; 669ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen else if (ARM::DPRRegClass.contains(DestReg, SrcReg)) 670ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen Opc = ARM::VMOVD; 671ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen else if (ARM::QPRRegClass.contains(DestReg, SrcReg)) 67243967a97cf9a296623e1cf5ed643e2f40b7e5766Owen Anderson Opc = ARM::VORRq; 673e5038e191db82d4d92fdeec1b5bce5cae21f6d8fChad Rosier 674e5038e191db82d4d92fdeec1b5bce5cae21f6d8fChad Rosier if (Opc) { 675e5038e191db82d4d92fdeec1b5bce5cae21f6d8fChad Rosier MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc), DestReg); 67643967a97cf9a296623e1cf5ed643e2f40b7e5766Owen Anderson MIB.addReg(SrcReg, getKillRegState(KillSrc)); 677e5038e191db82d4d92fdeec1b5bce5cae21f6d8fChad Rosier if (Opc == ARM::VORRq) 678e5038e191db82d4d92fdeec1b5bce5cae21f6d8fChad Rosier MIB.addReg(SrcReg, getKillRegState(KillSrc)); 679fea95c6bade86fcfa5bd07efdda9bd902f53be8cChad Rosier AddDefaultPred(MIB); 680e5038e191db82d4d92fdeec1b5bce5cae21f6d8fChad Rosier return; 681e5038e191db82d4d92fdeec1b5bce5cae21f6d8fChad Rosier } 682e5038e191db82d4d92fdeec1b5bce5cae21f6d8fChad Rosier 68385bdf2e76a0351468f231f48069c64bc6938f140Jakob Stoklund Olesen // Handle register classes that require multiple instructions. 68485bdf2e76a0351468f231f48069c64bc6938f140Jakob Stoklund Olesen unsigned BeginIdx = 0; 68585bdf2e76a0351468f231f48069c64bc6938f140Jakob Stoklund Olesen unsigned SubRegs = 0; 6867611a88b58e0a6960cdb5c72dc18a6c93e44cdc2Andrew Trick int Spacing = 1; 68785bdf2e76a0351468f231f48069c64bc6938f140Jakob Stoklund Olesen 68885bdf2e76a0351468f231f48069c64bc6938f140Jakob Stoklund Olesen // Use VORRq when possible. 68985bdf2e76a0351468f231f48069c64bc6938f140Jakob Stoklund Olesen if (ARM::QQPRRegClass.contains(DestReg, SrcReg)) 69085bdf2e76a0351468f231f48069c64bc6938f140Jakob Stoklund Olesen Opc = ARM::VORRq, BeginIdx = ARM::qsub_0, SubRegs = 2; 69185bdf2e76a0351468f231f48069c64bc6938f140Jakob Stoklund Olesen else if (ARM::QQQQPRRegClass.contains(DestReg, SrcReg)) 69285bdf2e76a0351468f231f48069c64bc6938f140Jakob Stoklund Olesen Opc = ARM::VORRq, BeginIdx = ARM::qsub_0, SubRegs = 4; 69385bdf2e76a0351468f231f48069c64bc6938f140Jakob Stoklund Olesen // Fall back to VMOVD. 69485bdf2e76a0351468f231f48069c64bc6938f140Jakob Stoklund Olesen else if (ARM::DPairRegClass.contains(DestReg, SrcReg)) 69585bdf2e76a0351468f231f48069c64bc6938f140Jakob Stoklund Olesen Opc = ARM::VMOVD, BeginIdx = ARM::dsub_0, SubRegs = 2; 69685bdf2e76a0351468f231f48069c64bc6938f140Jakob Stoklund Olesen else if (ARM::DTripleRegClass.contains(DestReg, SrcReg)) 69785bdf2e76a0351468f231f48069c64bc6938f140Jakob Stoklund Olesen Opc = ARM::VMOVD, BeginIdx = ARM::dsub_0, SubRegs = 3; 69885bdf2e76a0351468f231f48069c64bc6938f140Jakob Stoklund Olesen else if (ARM::DQuadRegClass.contains(DestReg, SrcReg)) 69985bdf2e76a0351468f231f48069c64bc6938f140Jakob Stoklund Olesen Opc = ARM::VMOVD, BeginIdx = ARM::dsub_0, SubRegs = 4; 70085bdf2e76a0351468f231f48069c64bc6938f140Jakob Stoklund Olesen 70185bdf2e76a0351468f231f48069c64bc6938f140Jakob Stoklund Olesen else if (ARM::DPairSpcRegClass.contains(DestReg, SrcReg)) 70285bdf2e76a0351468f231f48069c64bc6938f140Jakob Stoklund Olesen Opc = ARM::VMOVD, BeginIdx = ARM::dsub_0, SubRegs = 2, Spacing = 2; 70385bdf2e76a0351468f231f48069c64bc6938f140Jakob Stoklund Olesen else if (ARM::DTripleSpcRegClass.contains(DestReg, SrcReg)) 70485bdf2e76a0351468f231f48069c64bc6938f140Jakob Stoklund Olesen Opc = ARM::VMOVD, BeginIdx = ARM::dsub_0, SubRegs = 3, Spacing = 2; 70585bdf2e76a0351468f231f48069c64bc6938f140Jakob Stoklund Olesen else if (ARM::DQuadSpcRegClass.contains(DestReg, SrcReg)) 70685bdf2e76a0351468f231f48069c64bc6938f140Jakob Stoklund Olesen Opc = ARM::VMOVD, BeginIdx = ARM::dsub_0, SubRegs = 4, Spacing = 2; 70785bdf2e76a0351468f231f48069c64bc6938f140Jakob Stoklund Olesen 7087611a88b58e0a6960cdb5c72dc18a6c93e44cdc2Andrew Trick assert(Opc && "Impossible reg-to-reg copy"); 709d79dedd458c1de07fbc568ea8c3b4194e94df48eAndrew Trick 710d79dedd458c1de07fbc568ea8c3b4194e94df48eAndrew Trick const TargetRegisterInfo *TRI = &getRegisterInfo(); 711d79dedd458c1de07fbc568ea8c3b4194e94df48eAndrew Trick MachineInstrBuilder Mov; 712f26e43df26bb7b0c7bf4853477e36611e2c90deaAndrew Trick 713f26e43df26bb7b0c7bf4853477e36611e2c90deaAndrew Trick // Copy register tuples backward when the first Dest reg overlaps with SrcReg. 714f26e43df26bb7b0c7bf4853477e36611e2c90deaAndrew Trick if (TRI->regsOverlap(SrcReg, TRI->getSubReg(DestReg, BeginIdx))) { 715f26e43df26bb7b0c7bf4853477e36611e2c90deaAndrew Trick BeginIdx = BeginIdx + ((SubRegs-1)*Spacing); 716f26e43df26bb7b0c7bf4853477e36611e2c90deaAndrew Trick Spacing = -Spacing; 717f26e43df26bb7b0c7bf4853477e36611e2c90deaAndrew Trick } 718f26e43df26bb7b0c7bf4853477e36611e2c90deaAndrew Trick#ifndef NDEBUG 719f26e43df26bb7b0c7bf4853477e36611e2c90deaAndrew Trick SmallSet<unsigned, 4> DstRegs; 720f26e43df26bb7b0c7bf4853477e36611e2c90deaAndrew Trick#endif 721d79dedd458c1de07fbc568ea8c3b4194e94df48eAndrew Trick for (unsigned i = 0; i != SubRegs; ++i) { 722d79dedd458c1de07fbc568ea8c3b4194e94df48eAndrew Trick unsigned Dst = TRI->getSubReg(DestReg, BeginIdx + i*Spacing); 723d79dedd458c1de07fbc568ea8c3b4194e94df48eAndrew Trick unsigned Src = TRI->getSubReg(SrcReg, BeginIdx + i*Spacing); 724d79dedd458c1de07fbc568ea8c3b4194e94df48eAndrew Trick assert(Dst && Src && "Bad sub-register"); 725f26e43df26bb7b0c7bf4853477e36611e2c90deaAndrew Trick#ifndef NDEBUG 726f26e43df26bb7b0c7bf4853477e36611e2c90deaAndrew Trick assert(!DstRegs.count(Src) && "destructive vector copy"); 7277611a88b58e0a6960cdb5c72dc18a6c93e44cdc2Andrew Trick DstRegs.insert(Dst); 728f26e43df26bb7b0c7bf4853477e36611e2c90deaAndrew Trick#endif 729d79dedd458c1de07fbc568ea8c3b4194e94df48eAndrew Trick Mov = BuildMI(MBB, I, I->getDebugLoc(), get(Opc), Dst) 730d79dedd458c1de07fbc568ea8c3b4194e94df48eAndrew Trick .addReg(Src); 731d79dedd458c1de07fbc568ea8c3b4194e94df48eAndrew Trick // VORR takes two source operands. 732d79dedd458c1de07fbc568ea8c3b4194e94df48eAndrew Trick if (Opc == ARM::VORRq) 733d79dedd458c1de07fbc568ea8c3b4194e94df48eAndrew Trick Mov.addReg(Src); 734d79dedd458c1de07fbc568ea8c3b4194e94df48eAndrew Trick Mov = AddDefaultPred(Mov); 735e5038e191db82d4d92fdeec1b5bce5cae21f6d8fChad Rosier } 736d79dedd458c1de07fbc568ea8c3b4194e94df48eAndrew Trick // Add implicit super-register defs and kills to the last instruction. 737d79dedd458c1de07fbc568ea8c3b4194e94df48eAndrew Trick Mov->addRegisterDefined(DestReg, TRI); 738d79dedd458c1de07fbc568ea8c3b4194e94df48eAndrew Trick if (KillSrc) 739d79dedd458c1de07fbc568ea8c3b4194e94df48eAndrew Trick Mov->addRegisterKilled(SrcReg, TRI); 740334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 741334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 742c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Chengstatic const 743c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan ChengMachineInstrBuilder &AddDReg(MachineInstrBuilder &MIB, 744c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Cheng unsigned Reg, unsigned SubIdx, unsigned State, 745c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Cheng const TargetRegisterInfo *TRI) { 746c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Cheng if (!SubIdx) 747c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Cheng return MIB.addReg(Reg, State); 748c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Cheng 749c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Cheng if (TargetRegisterInfo::isPhysicalRegister(Reg)) 750c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Cheng return MIB.addReg(TRI->getSubReg(Reg, SubIdx), State); 751c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Cheng return MIB.addReg(Reg, State, SubIdx); 752c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Cheng} 753c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Cheng 754334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinvoid ARMBaseInstrInfo:: 755334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinstoreRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 756334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned SrcReg, bool isKill, int FI, 757746ad69e088176819981b4b2c5ac8dcd49f5e60eEvan Cheng const TargetRegisterClass *RC, 758746ad69e088176819981b4b2c5ac8dcd49f5e60eEvan Cheng const TargetRegisterInfo *TRI) const { 759c7f3ace20c325521c68335a1689645b43b06ddf0Chris Lattner DebugLoc DL; 760334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (I != MBB.end()) DL = I->getDebugLoc(); 761249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MachineFunction &MF = *MBB.getParent(); 762249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MachineFrameInfo &MFI = *MF.getFrameInfo(); 76331bc849123011b8eae6bb3c79876d9a3c26a6a1dJim Grosbach unsigned Align = MFI.getObjectAlignment(FI); 764249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov 765249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MachineMemOperand *MMO = 766978e0dfe46e481bfb1281e683aa308329e879e95Jay Foad MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FI), 76759db5496f4fc2ef6111569e542f8b65480ef14c1Chris Lattner MachineMemOperand::MOStore, 768249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MFI.getObjectSize(FI), 76931bc849123011b8eae6bb3c79876d9a3c26a6a1dJim Grosbach Align); 770334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 771e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson switch (RC->getSize()) { 772e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson case 4: 773e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson if (ARM::GPRRegClass.hasSubClassEq(RC)) { 774e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::STRi12)) 775334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(SrcReg, getKillRegState(isKill)) 7767e3383c007f53b3a00675af225e428cb66ddf404Jim Grosbach .addFrameIndex(FI).addImm(0).addMemOperand(MMO)); 777e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson } else if (ARM::SPRRegClass.hasSubClassEq(RC)) { 778e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTRS)) 779d31c5496d7e1580058b5c6fbc8fd537a641ea590Evan Cheng .addReg(SrcReg, getKillRegState(isKill)) 780d31c5496d7e1580058b5c6fbc8fd537a641ea590Evan Cheng .addFrameIndex(FI).addImm(0).addMemOperand(MMO)); 781e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson } else 782e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson llvm_unreachable("Unknown reg class!"); 783e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson break; 784e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson case 8: 785e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson if (ARM::DPRRegClass.hasSubClassEq(RC)) { 786e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTRD)) 787334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(SrcReg, getKillRegState(isKill)) 788249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov .addFrameIndex(FI).addImm(0).addMemOperand(MMO)); 789e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson } else 790e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson llvm_unreachable("Unknown reg class!"); 791e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson break; 792e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson case 16: 7935b2f9136644c58ae32e00d8317540692a697d1c9Jakob Stoklund Olesen if (ARM::DPairRegClass.hasSubClassEq(RC)) { 7947255a4e1332ccb69918ebe041dff05f9e4e5815dJakob Stoklund Olesen // Use aligned spills if the stack can be realigned. 7957255a4e1332ccb69918ebe041dff05f9e4e5815dJakob Stoklund Olesen if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) { 79628f08c93e75d291695ea89b9004145103292e85bJim Grosbach AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1q64)) 797f967ca0eaf30325cabe3c1971bf0dba16cf1b027Bob Wilson .addFrameIndex(FI).addImm(16) 79869b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng .addReg(SrcReg, getKillRegState(isKill)) 79969b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng .addMemOperand(MMO)); 800e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson } else { 801e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMQIA)) 80269b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng .addReg(SrcReg, getKillRegState(isKill)) 80369b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng .addFrameIndex(FI) 80469b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng .addMemOperand(MMO)); 805e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson } 806e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson } else 807e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson llvm_unreachable("Unknown reg class!"); 808e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson break; 809b58d7d03125526c152ade0c75be302b3c9eab997Anton Korobeynikov case 24: 810b58d7d03125526c152ade0c75be302b3c9eab997Anton Korobeynikov if (ARM::DTripleRegClass.hasSubClassEq(RC)) { 811b58d7d03125526c152ade0c75be302b3c9eab997Anton Korobeynikov // Use aligned spills if the stack can be realigned. 812b58d7d03125526c152ade0c75be302b3c9eab997Anton Korobeynikov if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) { 813b58d7d03125526c152ade0c75be302b3c9eab997Anton Korobeynikov AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1d64TPseudo)) 814b58d7d03125526c152ade0c75be302b3c9eab997Anton Korobeynikov .addFrameIndex(FI).addImm(16) 815b58d7d03125526c152ade0c75be302b3c9eab997Anton Korobeynikov .addReg(SrcReg, getKillRegState(isKill)) 816b58d7d03125526c152ade0c75be302b3c9eab997Anton Korobeynikov .addMemOperand(MMO)); 817b58d7d03125526c152ade0c75be302b3c9eab997Anton Korobeynikov } else { 818b58d7d03125526c152ade0c75be302b3c9eab997Anton Korobeynikov MachineInstrBuilder MIB = 819b58d7d03125526c152ade0c75be302b3c9eab997Anton Korobeynikov AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMDIA)) 820b58d7d03125526c152ade0c75be302b3c9eab997Anton Korobeynikov .addFrameIndex(FI)) 821b58d7d03125526c152ade0c75be302b3c9eab997Anton Korobeynikov .addMemOperand(MMO); 822b58d7d03125526c152ade0c75be302b3c9eab997Anton Korobeynikov MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI); 823b58d7d03125526c152ade0c75be302b3c9eab997Anton Korobeynikov MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI); 824b58d7d03125526c152ade0c75be302b3c9eab997Anton Korobeynikov AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI); 825b58d7d03125526c152ade0c75be302b3c9eab997Anton Korobeynikov } 826b58d7d03125526c152ade0c75be302b3c9eab997Anton Korobeynikov } else 827b58d7d03125526c152ade0c75be302b3c9eab997Anton Korobeynikov llvm_unreachable("Unknown reg class!"); 828b58d7d03125526c152ade0c75be302b3c9eab997Anton Korobeynikov break; 829e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson case 32: 830b58d7d03125526c152ade0c75be302b3c9eab997Anton Korobeynikov if (ARM::QQPRRegClass.hasSubClassEq(RC) || ARM::DQuadRegClass.hasSubClassEq(RC)) { 831e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) { 832e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson // FIXME: It's possible to only store part of the QQ register if the 833e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson // spilled def has a sub-register index. 834e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1d64QPseudo)) 835168f382dc67e5940cabdb28dc933c4f91cdd3137Bob Wilson .addFrameIndex(FI).addImm(16) 836168f382dc67e5940cabdb28dc933c4f91cdd3137Bob Wilson .addReg(SrcReg, getKillRegState(isKill)) 837168f382dc67e5940cabdb28dc933c4f91cdd3137Bob Wilson .addMemOperand(MMO)); 838e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson } else { 839e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson MachineInstrBuilder MIB = 840e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMDIA)) 84173fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling .addFrameIndex(FI)) 842e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson .addMemOperand(MMO); 843e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI); 844e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI); 845e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI); 846e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI); 847e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson } 848e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson } else 849e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson llvm_unreachable("Unknown reg class!"); 850e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson break; 851e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson case 64: 852e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson if (ARM::QQQQPRRegClass.hasSubClassEq(RC)) { 853e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson MachineInstrBuilder MIB = 854e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMDIA)) 855e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson .addFrameIndex(FI)) 856e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson .addMemOperand(MMO); 857e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI); 858e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI); 859e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI); 860e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson MIB = AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI); 861e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson MIB = AddDReg(MIB, SrcReg, ARM::dsub_4, 0, TRI); 862e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson MIB = AddDReg(MIB, SrcReg, ARM::dsub_5, 0, TRI); 863e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson MIB = AddDReg(MIB, SrcReg, ARM::dsub_6, 0, TRI); 864e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson AddDReg(MIB, SrcReg, ARM::dsub_7, 0, TRI); 865e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson } else 866e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson llvm_unreachable("Unknown reg class!"); 867e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson break; 868e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson default: 869e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson llvm_unreachable("Unknown reg class!"); 870334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 871334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 872334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 87334327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesenunsigned 87434327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund OlesenARMBaseInstrInfo::isStoreToStackSlot(const MachineInstr *MI, 87534327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen int &FrameIndex) const { 87634327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen switch (MI->getOpcode()) { 87734327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen default: break; 8787e3383c007f53b3a00675af225e428cb66ddf404Jim Grosbach case ARM::STRrs: 87934327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen case ARM::t2STRs: // FIXME: don't use t2STRs to access frame. 88034327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen if (MI->getOperand(1).isFI() && 88134327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen MI->getOperand(2).isReg() && 88234327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen MI->getOperand(3).isImm() && 88334327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen MI->getOperand(2).getReg() == 0 && 88434327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen MI->getOperand(3).getImm() == 0) { 88534327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen FrameIndex = MI->getOperand(1).getIndex(); 88634327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen return MI->getOperand(0).getReg(); 88734327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen } 88834327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen break; 8897e3383c007f53b3a00675af225e428cb66ddf404Jim Grosbach case ARM::STRi12: 89034327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen case ARM::t2STRi12: 89174472b4bf963c424da04f42dffdb94c85ef964bcJim Grosbach case ARM::tSTRspi: 89234327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen case ARM::VSTRD: 89334327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen case ARM::VSTRS: 89434327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen if (MI->getOperand(1).isFI() && 89534327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen MI->getOperand(2).isImm() && 89634327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen MI->getOperand(2).getImm() == 0) { 89734327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen FrameIndex = MI->getOperand(1).getIndex(); 89834327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen return MI->getOperand(0).getReg(); 89934327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen } 90034327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen break; 90128f08c93e75d291695ea89b9004145103292e85bJim Grosbach case ARM::VST1q64: 902161474d198d44ab505861c1ec55f022b27314b35Anton Korobeynikov case ARM::VST1d64TPseudo: 903161474d198d44ab505861c1ec55f022b27314b35Anton Korobeynikov case ARM::VST1d64QPseudo: 904d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen if (MI->getOperand(0).isFI() && 905d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen MI->getOperand(2).getSubReg() == 0) { 906d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen FrameIndex = MI->getOperand(0).getIndex(); 907d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen return MI->getOperand(2).getReg(); 908d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen } 90931bbc51ac9245bc82c933c9db8358ca9bb558ac5Jakob Stoklund Olesen break; 91073fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMQIA: 911d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen if (MI->getOperand(1).isFI() && 912d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen MI->getOperand(0).getSubReg() == 0) { 913d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen FrameIndex = MI->getOperand(1).getIndex(); 914d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen return MI->getOperand(0).getReg(); 915d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen } 916d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen break; 91734327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen } 91834327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen 91934327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen return 0; 92034327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen} 92134327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen 92236ee0e640554b8cc6ad1658fc3049e05d9967160Jakob Stoklund Olesenunsigned ARMBaseInstrInfo::isStoreToStackSlotPostFE(const MachineInstr *MI, 92336ee0e640554b8cc6ad1658fc3049e05d9967160Jakob Stoklund Olesen int &FrameIndex) const { 92436ee0e640554b8cc6ad1658fc3049e05d9967160Jakob Stoklund Olesen const MachineMemOperand *Dummy; 9255a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng return MI->mayStore() && hasStoreToStackSlot(MI, Dummy, FrameIndex); 92636ee0e640554b8cc6ad1658fc3049e05d9967160Jakob Stoklund Olesen} 92736ee0e640554b8cc6ad1658fc3049e05d9967160Jakob Stoklund Olesen 928334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinvoid ARMBaseInstrInfo:: 929334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinloadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 930334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned DestReg, int FI, 931746ad69e088176819981b4b2c5ac8dcd49f5e60eEvan Cheng const TargetRegisterClass *RC, 932746ad69e088176819981b4b2c5ac8dcd49f5e60eEvan Cheng const TargetRegisterInfo *TRI) const { 933c7f3ace20c325521c68335a1689645b43b06ddf0Chris Lattner DebugLoc DL; 934334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (I != MBB.end()) DL = I->getDebugLoc(); 935249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MachineFunction &MF = *MBB.getParent(); 936249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MachineFrameInfo &MFI = *MF.getFrameInfo(); 93731bc849123011b8eae6bb3c79876d9a3c26a6a1dJim Grosbach unsigned Align = MFI.getObjectAlignment(FI); 938249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MachineMemOperand *MMO = 93959db5496f4fc2ef6111569e542f8b65480ef14c1Chris Lattner MF.getMachineMemOperand( 940978e0dfe46e481bfb1281e683aa308329e879e95Jay Foad MachinePointerInfo::getFixedStack(FI), 94159db5496f4fc2ef6111569e542f8b65480ef14c1Chris Lattner MachineMemOperand::MOLoad, 942249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MFI.getObjectSize(FI), 94331bc849123011b8eae6bb3c79876d9a3c26a6a1dJim Grosbach Align); 944334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 945e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson switch (RC->getSize()) { 946e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson case 4: 947e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson if (ARM::GPRRegClass.hasSubClassEq(RC)) { 948e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::LDRi12), DestReg) 9493e5561247202bae994dd259a2d8dc4eff8f799f3Jim Grosbach .addFrameIndex(FI).addImm(0).addMemOperand(MMO)); 950e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson 951e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson } else if (ARM::SPRRegClass.hasSubClassEq(RC)) { 952e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRS), DestReg) 953d31c5496d7e1580058b5c6fbc8fd537a641ea590Evan Cheng .addFrameIndex(FI).addImm(0).addMemOperand(MMO)); 954e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson } else 955e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson llvm_unreachable("Unknown reg class!"); 956ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson break; 957e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson case 8: 958e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson if (ARM::DPRRegClass.hasSubClassEq(RC)) { 959e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRD), DestReg) 960249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov .addFrameIndex(FI).addImm(0).addMemOperand(MMO)); 961e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson } else 962e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson llvm_unreachable("Unknown reg class!"); 963ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson break; 964e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson case 16: 9655b2f9136644c58ae32e00d8317540692a697d1c9Jakob Stoklund Olesen if (ARM::DPairRegClass.hasSubClassEq(RC)) { 9667255a4e1332ccb69918ebe041dff05f9e4e5815dJakob Stoklund Olesen if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) { 96728f08c93e75d291695ea89b9004145103292e85bJim Grosbach AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1q64), DestReg) 968f967ca0eaf30325cabe3c1971bf0dba16cf1b027Bob Wilson .addFrameIndex(FI).addImm(16) 96969b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng .addMemOperand(MMO)); 970e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson } else { 971e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMQIA), DestReg) 972e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson .addFrameIndex(FI) 973e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson .addMemOperand(MMO)); 974e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson } 975e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson } else 976e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson llvm_unreachable("Unknown reg class!"); 977ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson break; 978b58d7d03125526c152ade0c75be302b3c9eab997Anton Korobeynikov case 24: 979b58d7d03125526c152ade0c75be302b3c9eab997Anton Korobeynikov if (ARM::DTripleRegClass.hasSubClassEq(RC)) { 980b58d7d03125526c152ade0c75be302b3c9eab997Anton Korobeynikov if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) { 981b58d7d03125526c152ade0c75be302b3c9eab997Anton Korobeynikov AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1d64TPseudo), DestReg) 982b58d7d03125526c152ade0c75be302b3c9eab997Anton Korobeynikov .addFrameIndex(FI).addImm(16) 983b58d7d03125526c152ade0c75be302b3c9eab997Anton Korobeynikov .addMemOperand(MMO)); 984b58d7d03125526c152ade0c75be302b3c9eab997Anton Korobeynikov } else { 985b58d7d03125526c152ade0c75be302b3c9eab997Anton Korobeynikov MachineInstrBuilder MIB = 986b58d7d03125526c152ade0c75be302b3c9eab997Anton Korobeynikov AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMDIA)) 987b58d7d03125526c152ade0c75be302b3c9eab997Anton Korobeynikov .addFrameIndex(FI) 988b58d7d03125526c152ade0c75be302b3c9eab997Anton Korobeynikov .addMemOperand(MMO)); 989b58d7d03125526c152ade0c75be302b3c9eab997Anton Korobeynikov MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI); 990b58d7d03125526c152ade0c75be302b3c9eab997Anton Korobeynikov MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI); 991b58d7d03125526c152ade0c75be302b3c9eab997Anton Korobeynikov MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI); 992b58d7d03125526c152ade0c75be302b3c9eab997Anton Korobeynikov if (TargetRegisterInfo::isPhysicalRegister(DestReg)) 993b58d7d03125526c152ade0c75be302b3c9eab997Anton Korobeynikov MIB.addReg(DestReg, RegState::ImplicitDefine); 994b58d7d03125526c152ade0c75be302b3c9eab997Anton Korobeynikov } 995b58d7d03125526c152ade0c75be302b3c9eab997Anton Korobeynikov } else 996b58d7d03125526c152ade0c75be302b3c9eab997Anton Korobeynikov llvm_unreachable("Unknown reg class!"); 997b58d7d03125526c152ade0c75be302b3c9eab997Anton Korobeynikov break; 998b58d7d03125526c152ade0c75be302b3c9eab997Anton Korobeynikov case 32: 999b58d7d03125526c152ade0c75be302b3c9eab997Anton Korobeynikov if (ARM::QQPRRegClass.hasSubClassEq(RC) || ARM::DQuadRegClass.hasSubClassEq(RC)) { 1000e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) { 1001e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1d64QPseudo), DestReg) 1002168f382dc67e5940cabdb28dc933c4f91cdd3137Bob Wilson .addFrameIndex(FI).addImm(16) 1003168f382dc67e5940cabdb28dc933c4f91cdd3137Bob Wilson .addMemOperand(MMO)); 1004e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson } else { 1005e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson MachineInstrBuilder MIB = 100673fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMDIA)) 100773fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling .addFrameIndex(FI)) 1008e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson .addMemOperand(MMO); 1009fce711cb65716f86b4e150f42cbb597bbecf7dbeJakob Stoklund Olesen MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI); 1010fce711cb65716f86b4e150f42cbb597bbecf7dbeJakob Stoklund Olesen MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI); 1011fce711cb65716f86b4e150f42cbb597bbecf7dbeJakob Stoklund Olesen MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI); 1012fce711cb65716f86b4e150f42cbb597bbecf7dbeJakob Stoklund Olesen MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::DefineNoRead, TRI); 10133247af294996ff8588077c06505b64966ad41542Jakob Stoklund Olesen if (TargetRegisterInfo::isPhysicalRegister(DestReg)) 10143247af294996ff8588077c06505b64966ad41542Jakob Stoklund Olesen MIB.addReg(DestReg, RegState::ImplicitDefine); 1015e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson } 1016e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson } else 1017e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson llvm_unreachable("Unknown reg class!"); 1018ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson break; 1019e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson case 64: 1020e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson if (ARM::QQQQPRRegClass.hasSubClassEq(RC)) { 1021e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson MachineInstrBuilder MIB = 102273fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMDIA)) 102373fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling .addFrameIndex(FI)) 1024e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson .addMemOperand(MMO); 1025fce711cb65716f86b4e150f42cbb597bbecf7dbeJakob Stoklund Olesen MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI); 1026fce711cb65716f86b4e150f42cbb597bbecf7dbeJakob Stoklund Olesen MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI); 1027fce711cb65716f86b4e150f42cbb597bbecf7dbeJakob Stoklund Olesen MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI); 1028fce711cb65716f86b4e150f42cbb597bbecf7dbeJakob Stoklund Olesen MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::DefineNoRead, TRI); 1029fce711cb65716f86b4e150f42cbb597bbecf7dbeJakob Stoklund Olesen MIB = AddDReg(MIB, DestReg, ARM::dsub_4, RegState::DefineNoRead, TRI); 1030fce711cb65716f86b4e150f42cbb597bbecf7dbeJakob Stoklund Olesen MIB = AddDReg(MIB, DestReg, ARM::dsub_5, RegState::DefineNoRead, TRI); 1031fce711cb65716f86b4e150f42cbb597bbecf7dbeJakob Stoklund Olesen MIB = AddDReg(MIB, DestReg, ARM::dsub_6, RegState::DefineNoRead, TRI); 1032fce711cb65716f86b4e150f42cbb597bbecf7dbeJakob Stoklund Olesen MIB = AddDReg(MIB, DestReg, ARM::dsub_7, RegState::DefineNoRead, TRI); 10333247af294996ff8588077c06505b64966ad41542Jakob Stoklund Olesen if (TargetRegisterInfo::isPhysicalRegister(DestReg)) 10343247af294996ff8588077c06505b64966ad41542Jakob Stoklund Olesen MIB.addReg(DestReg, RegState::ImplicitDefine); 1035e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson } else 1036e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson llvm_unreachable("Unknown reg class!"); 1037ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson break; 1038ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson default: 1039ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson llvm_unreachable("Unknown regclass!"); 1040334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 1041334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 1042334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 104334327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesenunsigned 104434327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund OlesenARMBaseInstrInfo::isLoadFromStackSlot(const MachineInstr *MI, 104534327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen int &FrameIndex) const { 104634327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen switch (MI->getOpcode()) { 104734327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen default: break; 10483e5561247202bae994dd259a2d8dc4eff8f799f3Jim Grosbach case ARM::LDRrs: 104934327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen case ARM::t2LDRs: // FIXME: don't use t2LDRs to access frame. 105034327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen if (MI->getOperand(1).isFI() && 105134327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen MI->getOperand(2).isReg() && 105234327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen MI->getOperand(3).isImm() && 105334327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen MI->getOperand(2).getReg() == 0 && 105434327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen MI->getOperand(3).getImm() == 0) { 105534327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen FrameIndex = MI->getOperand(1).getIndex(); 105634327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen return MI->getOperand(0).getReg(); 105734327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen } 105834327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen break; 10593e5561247202bae994dd259a2d8dc4eff8f799f3Jim Grosbach case ARM::LDRi12: 106034327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen case ARM::t2LDRi12: 106174472b4bf963c424da04f42dffdb94c85ef964bcJim Grosbach case ARM::tLDRspi: 106234327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen case ARM::VLDRD: 106334327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen case ARM::VLDRS: 106434327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen if (MI->getOperand(1).isFI() && 106534327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen MI->getOperand(2).isImm() && 106634327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen MI->getOperand(2).getImm() == 0) { 106734327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen FrameIndex = MI->getOperand(1).getIndex(); 1068d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen return MI->getOperand(0).getReg(); 1069d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen } 1070d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen break; 107128f08c93e75d291695ea89b9004145103292e85bJim Grosbach case ARM::VLD1q64: 1072161474d198d44ab505861c1ec55f022b27314b35Anton Korobeynikov case ARM::VLD1d64TPseudo: 1073161474d198d44ab505861c1ec55f022b27314b35Anton Korobeynikov case ARM::VLD1d64QPseudo: 1074d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen if (MI->getOperand(1).isFI() && 1075d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen MI->getOperand(0).getSubReg() == 0) { 1076d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen FrameIndex = MI->getOperand(1).getIndex(); 107706f264e504d75f0426eea55b9f9e36c780d8a4fcJakob Stoklund Olesen return MI->getOperand(0).getReg(); 107806f264e504d75f0426eea55b9f9e36c780d8a4fcJakob Stoklund Olesen } 107906f264e504d75f0426eea55b9f9e36c780d8a4fcJakob Stoklund Olesen break; 108073fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMQIA: 108106f264e504d75f0426eea55b9f9e36c780d8a4fcJakob Stoklund Olesen if (MI->getOperand(1).isFI() && 108206f264e504d75f0426eea55b9f9e36c780d8a4fcJakob Stoklund Olesen MI->getOperand(0).getSubReg() == 0) { 108306f264e504d75f0426eea55b9f9e36c780d8a4fcJakob Stoklund Olesen FrameIndex = MI->getOperand(1).getIndex(); 108434327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen return MI->getOperand(0).getReg(); 108534327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen } 108634327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen break; 108734327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen } 108834327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen 108934327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen return 0; 109034327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen} 109134327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen 109236ee0e640554b8cc6ad1658fc3049e05d9967160Jakob Stoklund Olesenunsigned ARMBaseInstrInfo::isLoadFromStackSlotPostFE(const MachineInstr *MI, 109336ee0e640554b8cc6ad1658fc3049e05d9967160Jakob Stoklund Olesen int &FrameIndex) const { 109436ee0e640554b8cc6ad1658fc3049e05d9967160Jakob Stoklund Olesen const MachineMemOperand *Dummy; 10955a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng return MI->mayLoad() && hasLoadFromStackSlot(MI, Dummy, FrameIndex); 109636ee0e640554b8cc6ad1658fc3049e05d9967160Jakob Stoklund Olesen} 109736ee0e640554b8cc6ad1658fc3049e05d9967160Jakob Stoklund Olesen 1098142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesenbool ARMBaseInstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const{ 1099142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen // This hook gets to expand COPY instructions before they become 1100142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen // copyPhysReg() calls. Look for VMOVS instructions that can legally be 1101142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen // widened to VMOVD. We prefer the VMOVD when possible because it may be 1102142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen // changed into a VORR that can go down the NEON pipeline. 1103142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen if (!WidenVMOVS || !MI->isCopy()) 1104142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen return false; 1105142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen 1106142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen // Look for a copy between even S-registers. That is where we keep floats 1107142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen // when using NEON v2f32 instructions for f32 arithmetic. 1108142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen unsigned DstRegS = MI->getOperand(0).getReg(); 1109142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen unsigned SrcRegS = MI->getOperand(1).getReg(); 1110142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen if (!ARM::SPRRegClass.contains(DstRegS, SrcRegS)) 1111142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen return false; 1112142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen 1113142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen const TargetRegisterInfo *TRI = &getRegisterInfo(); 1114142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen unsigned DstRegD = TRI->getMatchingSuperReg(DstRegS, ARM::ssub_0, 1115142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen &ARM::DPRRegClass); 1116142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen unsigned SrcRegD = TRI->getMatchingSuperReg(SrcRegS, ARM::ssub_0, 1117142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen &ARM::DPRRegClass); 1118142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen if (!DstRegD || !SrcRegD) 1119142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen return false; 1120142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen 1121142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen // We want to widen this into a DstRegD = VMOVD SrcRegD copy. This is only 1122142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen // legal if the COPY already defines the full DstRegD, and it isn't a 1123142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen // sub-register insertion. 1124142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen if (!MI->definesRegister(DstRegD, TRI) || MI->readsRegister(DstRegD, TRI)) 1125142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen return false; 1126142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen 11271c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen // A dead copy shouldn't show up here, but reject it just in case. 11281c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen if (MI->getOperand(0).isDead()) 11291c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen return false; 11301c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen 11311c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen // All clear, widen the COPY. 1132142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen DEBUG(dbgs() << "widening: " << *MI); 11331c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen 11341c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen // Get rid of the old <imp-def> of DstRegD. Leave it if it defines a Q-reg 11351c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen // or some other super-register. 11361c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen int ImpDefIdx = MI->findRegisterDefOperandIdx(DstRegD); 11371c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen if (ImpDefIdx != -1) 11381c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen MI->RemoveOperand(ImpDefIdx); 11391c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen 11401c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen // Change the opcode and operands. 1141142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen MI->setDesc(get(ARM::VMOVD)); 1142142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen MI->getOperand(0).setReg(DstRegD); 1143142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen MI->getOperand(1).setReg(SrcRegD); 1144142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen AddDefaultPred(MachineInstrBuilder(MI)); 11451c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen 11461c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen // We are now reading SrcRegD instead of SrcRegS. This may upset the 11471c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen // register scavenger and machine verifier, so we need to indicate that we 11481c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen // are reading an undefined value from SrcRegD, but a proper value from 11491c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen // SrcRegS. 11501c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen MI->getOperand(1).setIsUndef(); 11511c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen MachineInstrBuilder(MI).addReg(SrcRegS, RegState::Implicit); 11521c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen 11531c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen // SrcRegD may actually contain an unrelated value in the ssub_1 11541c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen // sub-register. Don't kill it. Only kill the ssub_0 sub-register. 11551c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen if (MI->getOperand(1).isKill()) { 11561c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen MI->getOperand(1).setIsKill(false); 11571c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen MI->addRegisterKilled(SrcRegS, TRI, true); 11581c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen } 11591c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen 1160142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen DEBUG(dbgs() << "replaced by: " << *MI); 1161142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen return true; 1162142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen} 1163142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen 116462b50656ceb854eb0be265d63b2a1d46e7400d8aEvan ChengMachineInstr* 116562b50656ceb854eb0be265d63b2a1d46e7400d8aEvan ChengARMBaseInstrInfo::emitFrameIndexDebugValue(MachineFunction &MF, 11668601a3d4decff0a380e059b037dabf71075497d3Evan Cheng int FrameIx, uint64_t Offset, 116762b50656ceb854eb0be265d63b2a1d46e7400d8aEvan Cheng const MDNode *MDPtr, 116862b50656ceb854eb0be265d63b2a1d46e7400d8aEvan Cheng DebugLoc DL) const { 116962b50656ceb854eb0be265d63b2a1d46e7400d8aEvan Cheng MachineInstrBuilder MIB = BuildMI(MF, DL, get(ARM::DBG_VALUE)) 117062b50656ceb854eb0be265d63b2a1d46e7400d8aEvan Cheng .addFrameIndex(FrameIx).addImm(0).addImm(Offset).addMetadata(MDPtr); 117162b50656ceb854eb0be265d63b2a1d46e7400d8aEvan Cheng return &*MIB; 117262b50656ceb854eb0be265d63b2a1d46e7400d8aEvan Cheng} 117362b50656ceb854eb0be265d63b2a1d46e7400d8aEvan Cheng 117430ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen/// Create a copy of a const pool value. Update CPI to the new index and return 117530ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen/// the label UID. 117630ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesenstatic unsigned duplicateCPV(MachineFunction &MF, unsigned &CPI) { 117730ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen MachineConstantPool *MCP = MF.getConstantPool(); 117830ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 117930ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen 118030ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPI]; 118130ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen assert(MCPE.isMachineConstantPoolEntry() && 118230ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen "Expecting a machine constantpool entry!"); 118330ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen ARMConstantPoolValue *ACPV = 118430ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal); 118530ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen 11865de5d4b6d0eb3fd379fa571d82f6fa764460b3b8Evan Cheng unsigned PCLabelId = AFI->createPICLabelUId(); 118730ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen ARMConstantPoolValue *NewCPV = 0; 118851f5b67395780b8421f4aa6ee998ed51b23dae9dJim Grosbach // FIXME: The below assumes PIC relocation model and that the function 118951f5b67395780b8421f4aa6ee998ed51b23dae9dJim Grosbach // is Thumb mode (t1 or t2). PCAdjustment would be 8 for ARM mode PIC, and 119051f5b67395780b8421f4aa6ee998ed51b23dae9dJim Grosbach // zero for non-PIC in ARM or Thumb. The callers are all of thumb LDR 119151f5b67395780b8421f4aa6ee998ed51b23dae9dJim Grosbach // instructions, so that's probably OK, but is PIC always correct when 119251f5b67395780b8421f4aa6ee998ed51b23dae9dJim Grosbach // we get here? 119330ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen if (ACPV->isGlobalValue()) 11945bb779976a7d8e48408051ec2289fe69206dc072Bill Wendling NewCPV = ARMConstantPoolConstant:: 11955bb779976a7d8e48408051ec2289fe69206dc072Bill Wendling Create(cast<ARMConstantPoolConstant>(ACPV)->getGV(), PCLabelId, 11965bb779976a7d8e48408051ec2289fe69206dc072Bill Wendling ARMCP::CPValue, 4); 119730ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen else if (ACPV->isExtSymbol()) 1198fe31e673506ef9a1080eaa684b43b34178c6f447Bill Wendling NewCPV = ARMConstantPoolSymbol:: 1199fe31e673506ef9a1080eaa684b43b34178c6f447Bill Wendling Create(MF.getFunction()->getContext(), 1200fe31e673506ef9a1080eaa684b43b34178c6f447Bill Wendling cast<ARMConstantPoolSymbol>(ACPV)->getSymbol(), PCLabelId, 4); 120130ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen else if (ACPV->isBlockAddress()) 12025bb779976a7d8e48408051ec2289fe69206dc072Bill Wendling NewCPV = ARMConstantPoolConstant:: 12035bb779976a7d8e48408051ec2289fe69206dc072Bill Wendling Create(cast<ARMConstantPoolConstant>(ACPV)->getBlockAddress(), PCLabelId, 12045bb779976a7d8e48408051ec2289fe69206dc072Bill Wendling ARMCP::CPBlockAddress, 4); 120551f5b67395780b8421f4aa6ee998ed51b23dae9dJim Grosbach else if (ACPV->isLSDA()) 12065bb779976a7d8e48408051ec2289fe69206dc072Bill Wendling NewCPV = ARMConstantPoolConstant::Create(MF.getFunction(), PCLabelId, 12075bb779976a7d8e48408051ec2289fe69206dc072Bill Wendling ARMCP::CPLSDA, 4); 1208e00897c5a91febe90ba21082fc636be892bf9bf1Bill Wendling else if (ACPV->isMachineBasicBlock()) 12093320f2a3bfd4daec23ba7ceb50525140cc6316daBill Wendling NewCPV = ARMConstantPoolMBB:: 12103320f2a3bfd4daec23ba7ceb50525140cc6316daBill Wendling Create(MF.getFunction()->getContext(), 12113320f2a3bfd4daec23ba7ceb50525140cc6316daBill Wendling cast<ARMConstantPoolMBB>(ACPV)->getMBB(), PCLabelId, 4); 121230ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen else 121330ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen llvm_unreachable("Unexpected ARM constantpool value type!!"); 121430ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen CPI = MCP->getConstantPoolIndex(NewCPV, MCPE.getAlignment()); 121530ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen return PCLabelId; 121630ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen} 121730ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen 1218fdc834046efd427d474e3b899ec69354c05071e0Evan Chengvoid ARMBaseInstrInfo:: 1219fdc834046efd427d474e3b899ec69354c05071e0Evan ChengreMaterialize(MachineBasicBlock &MBB, 1220fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng MachineBasicBlock::iterator I, 1221fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng unsigned DestReg, unsigned SubIdx, 1222d57cdd5683ea926e489067364fb7ffe5fd5d35eeEvan Cheng const MachineInstr *Orig, 12239edf7deb37f0f97664f279040fa15d89f32e23d9Jakob Stoklund Olesen const TargetRegisterInfo &TRI) const { 1224fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng unsigned Opcode = Orig->getOpcode(); 1225fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng switch (Opcode) { 1226fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng default: { 1227fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig); 12289edf7deb37f0f97664f279040fa15d89f32e23d9Jakob Stoklund Olesen MI->substituteRegister(Orig->getOperand(0).getReg(), DestReg, SubIdx, TRI); 1229fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng MBB.insert(I, MI); 1230fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng break; 1231fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng } 1232fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng case ARM::tLDRpci_pic: 1233fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng case ARM::t2LDRpci_pic: { 1234fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng MachineFunction &MF = *MBB.getParent(); 1235fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng unsigned CPI = Orig->getOperand(1).getIndex(); 123630ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen unsigned PCLabelId = duplicateCPV(MF, CPI); 1237fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng MachineInstrBuilder MIB = BuildMI(MBB, I, Orig->getDebugLoc(), get(Opcode), 1238fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng DestReg) 1239fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng .addConstantPoolIndex(CPI).addImm(PCLabelId); 1240d7d030a44796adc73a6eaa939cd17e52047734c1Chris Lattner MIB->setMemRefs(Orig->memoperands_begin(), Orig->memoperands_end()); 1241fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng break; 1242fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng } 1243fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng } 1244fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng} 1245fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng 124630ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund OlesenMachineInstr * 124730ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund OlesenARMBaseInstrInfo::duplicate(MachineInstr *Orig, MachineFunction &MF) const { 124830ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen MachineInstr *MI = TargetInstrInfoImpl::duplicate(Orig, MF); 124930ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen switch(Orig->getOpcode()) { 125030ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen case ARM::tLDRpci_pic: 125130ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen case ARM::t2LDRpci_pic: { 125230ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen unsigned CPI = Orig->getOperand(1).getIndex(); 125330ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen unsigned PCLabelId = duplicateCPV(MF, CPI); 125430ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen Orig->getOperand(1).setIndex(CPI); 125530ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen Orig->getOperand(2).setImm(PCLabelId); 125630ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen break; 125730ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen } 125830ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen } 125930ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen return MI; 126030ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen} 126130ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen 1262506049f29f4f202a8e45feb916cc0264440a7f6dEvan Chengbool ARMBaseInstrInfo::produceSameValue(const MachineInstr *MI0, 12639fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng const MachineInstr *MI1, 12649fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng const MachineRegisterInfo *MRI) const { 1265d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng int Opcode = MI0->getOpcode(); 1266d7e3cc840b81b0438e47f05d9664137a198876dfEvan Cheng if (Opcode == ARM::t2LDRpci || 12679b82425cb0105fd5704f6b9bcd5e7693b05b1759Evan Cheng Opcode == ARM::t2LDRpci_pic || 12689b82425cb0105fd5704f6b9bcd5e7693b05b1759Evan Cheng Opcode == ARM::tLDRpci || 12699fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng Opcode == ARM::tLDRpci_pic || 127053519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng Opcode == ARM::MOV_ga_dyn || 127153519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng Opcode == ARM::MOV_ga_pcrel || 127253519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng Opcode == ARM::MOV_ga_pcrel_ldr || 127353519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng Opcode == ARM::t2MOV_ga_dyn || 127453519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng Opcode == ARM::t2MOV_ga_pcrel) { 1275d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng if (MI1->getOpcode() != Opcode) 1276d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng return false; 1277d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng if (MI0->getNumOperands() != MI1->getNumOperands()) 1278d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng return false; 1279d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng 1280d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng const MachineOperand &MO0 = MI0->getOperand(1); 1281d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng const MachineOperand &MO1 = MI1->getOperand(1); 1282d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng if (MO0.getOffset() != MO1.getOffset()) 1283d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng return false; 1284d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng 128553519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng if (Opcode == ARM::MOV_ga_dyn || 128653519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng Opcode == ARM::MOV_ga_pcrel || 128753519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng Opcode == ARM::MOV_ga_pcrel_ldr || 128853519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng Opcode == ARM::t2MOV_ga_dyn || 128953519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng Opcode == ARM::t2MOV_ga_pcrel) 12909fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng // Ignore the PC labels. 12919fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng return MO0.getGlobal() == MO1.getGlobal(); 12929fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng 1293d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng const MachineFunction *MF = MI0->getParent()->getParent(); 1294d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng const MachineConstantPool *MCP = MF->getConstantPool(); 1295d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng int CPI0 = MO0.getIndex(); 1296d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng int CPI1 = MO1.getIndex(); 1297d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng const MachineConstantPoolEntry &MCPE0 = MCP->getConstants()[CPI0]; 1298d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng const MachineConstantPoolEntry &MCPE1 = MCP->getConstants()[CPI1]; 1299d700617193f3d11deb83cd56c4ababbc8e0ea19fEvan Cheng bool isARMCP0 = MCPE0.isMachineConstantPoolEntry(); 1300d700617193f3d11deb83cd56c4ababbc8e0ea19fEvan Cheng bool isARMCP1 = MCPE1.isMachineConstantPoolEntry(); 1301d700617193f3d11deb83cd56c4ababbc8e0ea19fEvan Cheng if (isARMCP0 && isARMCP1) { 1302d700617193f3d11deb83cd56c4ababbc8e0ea19fEvan Cheng ARMConstantPoolValue *ACPV0 = 1303d700617193f3d11deb83cd56c4ababbc8e0ea19fEvan Cheng static_cast<ARMConstantPoolValue*>(MCPE0.Val.MachineCPVal); 1304d700617193f3d11deb83cd56c4ababbc8e0ea19fEvan Cheng ARMConstantPoolValue *ACPV1 = 1305d700617193f3d11deb83cd56c4ababbc8e0ea19fEvan Cheng static_cast<ARMConstantPoolValue*>(MCPE1.Val.MachineCPVal); 1306d700617193f3d11deb83cd56c4ababbc8e0ea19fEvan Cheng return ACPV0->hasSameValue(ACPV1); 1307d700617193f3d11deb83cd56c4ababbc8e0ea19fEvan Cheng } else if (!isARMCP0 && !isARMCP1) { 1308d700617193f3d11deb83cd56c4ababbc8e0ea19fEvan Cheng return MCPE0.Val.ConstVal == MCPE1.Val.ConstVal; 1309d700617193f3d11deb83cd56c4ababbc8e0ea19fEvan Cheng } 1310d700617193f3d11deb83cd56c4ababbc8e0ea19fEvan Cheng return false; 13119fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng } else if (Opcode == ARM::PICLDR) { 13129fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng if (MI1->getOpcode() != Opcode) 13139fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng return false; 13149fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng if (MI0->getNumOperands() != MI1->getNumOperands()) 13159fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng return false; 13169fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng 13179fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng unsigned Addr0 = MI0->getOperand(1).getReg(); 13189fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng unsigned Addr1 = MI1->getOperand(1).getReg(); 13199fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng if (Addr0 != Addr1) { 13209fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng if (!MRI || 13219fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng !TargetRegisterInfo::isVirtualRegister(Addr0) || 13229fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng !TargetRegisterInfo::isVirtualRegister(Addr1)) 13239fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng return false; 13249fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng 13259fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng // This assumes SSA form. 13269fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng MachineInstr *Def0 = MRI->getVRegDef(Addr0); 13279fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng MachineInstr *Def1 = MRI->getVRegDef(Addr1); 13289fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng // Check if the loaded value, e.g. a constantpool of a global address, are 13299fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng // the same. 13309fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng if (!produceSameValue(Def0, Def1, MRI)) 13319fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng return false; 13329fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng } 13339fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng 13349fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng for (unsigned i = 3, e = MI0->getNumOperands(); i != e; ++i) { 13359fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng // %vreg12<def> = PICLDR %vreg11, 0, pred:14, pred:%noreg 13369fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng const MachineOperand &MO0 = MI0->getOperand(i); 13379fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng const MachineOperand &MO1 = MI1->getOperand(i); 13389fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng if (!MO0.isIdenticalTo(MO1)) 13399fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng return false; 13409fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng } 13419fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng return true; 1342d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng } 1343d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng 1344506049f29f4f202a8e45feb916cc0264440a7f6dEvan Cheng return MI0->isIdenticalTo(MI1, MachineInstr::IgnoreVRegDefs); 1345d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng} 1346d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng 13474b722108e2cf8e77157e0879a23789cd44829933Bill Wendling/// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to 13484b722108e2cf8e77157e0879a23789cd44829933Bill Wendling/// determine if two loads are loading from the same base address. It should 13494b722108e2cf8e77157e0879a23789cd44829933Bill Wendling/// only return true if the base pointers are the same and the only differences 13504b722108e2cf8e77157e0879a23789cd44829933Bill Wendling/// between the two addresses is the offset. It also returns the offsets by 13514b722108e2cf8e77157e0879a23789cd44829933Bill Wendling/// reference. 13524b722108e2cf8e77157e0879a23789cd44829933Bill Wendlingbool ARMBaseInstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, 13534b722108e2cf8e77157e0879a23789cd44829933Bill Wendling int64_t &Offset1, 13544b722108e2cf8e77157e0879a23789cd44829933Bill Wendling int64_t &Offset2) const { 13554b722108e2cf8e77157e0879a23789cd44829933Bill Wendling // Don't worry about Thumb: just ARM and Thumb2. 13564b722108e2cf8e77157e0879a23789cd44829933Bill Wendling if (Subtarget.isThumb1Only()) return false; 13574b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 13584b722108e2cf8e77157e0879a23789cd44829933Bill Wendling if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode()) 13594b722108e2cf8e77157e0879a23789cd44829933Bill Wendling return false; 13604b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 13614b722108e2cf8e77157e0879a23789cd44829933Bill Wendling switch (Load1->getMachineOpcode()) { 13624b722108e2cf8e77157e0879a23789cd44829933Bill Wendling default: 13634b722108e2cf8e77157e0879a23789cd44829933Bill Wendling return false; 13643e5561247202bae994dd259a2d8dc4eff8f799f3Jim Grosbach case ARM::LDRi12: 1365c1d30212e911d1e55ff6b25bffefb503708883c3Jim Grosbach case ARM::LDRBi12: 13664b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::LDRD: 13674b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::LDRH: 13684b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::LDRSB: 13694b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::LDRSH: 13704b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::VLDRD: 13714b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::VLDRS: 13724b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::t2LDRi8: 13734b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::t2LDRDi8: 13744b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::t2LDRSHi8: 13754b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::t2LDRi12: 13764b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::t2LDRSHi12: 13774b722108e2cf8e77157e0879a23789cd44829933Bill Wendling break; 13784b722108e2cf8e77157e0879a23789cd44829933Bill Wendling } 13794b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 13804b722108e2cf8e77157e0879a23789cd44829933Bill Wendling switch (Load2->getMachineOpcode()) { 13814b722108e2cf8e77157e0879a23789cd44829933Bill Wendling default: 13824b722108e2cf8e77157e0879a23789cd44829933Bill Wendling return false; 13833e5561247202bae994dd259a2d8dc4eff8f799f3Jim Grosbach case ARM::LDRi12: 1384c1d30212e911d1e55ff6b25bffefb503708883c3Jim Grosbach case ARM::LDRBi12: 13854b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::LDRD: 13864b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::LDRH: 13874b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::LDRSB: 13884b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::LDRSH: 13894b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::VLDRD: 13904b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::VLDRS: 13914b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::t2LDRi8: 13924b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::t2LDRDi8: 13934b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::t2LDRSHi8: 13944b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::t2LDRi12: 13954b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::t2LDRSHi12: 13964b722108e2cf8e77157e0879a23789cd44829933Bill Wendling break; 13974b722108e2cf8e77157e0879a23789cd44829933Bill Wendling } 13984b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 13994b722108e2cf8e77157e0879a23789cd44829933Bill Wendling // Check if base addresses and chain operands match. 14004b722108e2cf8e77157e0879a23789cd44829933Bill Wendling if (Load1->getOperand(0) != Load2->getOperand(0) || 14014b722108e2cf8e77157e0879a23789cd44829933Bill Wendling Load1->getOperand(4) != Load2->getOperand(4)) 14024b722108e2cf8e77157e0879a23789cd44829933Bill Wendling return false; 14034b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 14044b722108e2cf8e77157e0879a23789cd44829933Bill Wendling // Index should be Reg0. 14054b722108e2cf8e77157e0879a23789cd44829933Bill Wendling if (Load1->getOperand(3) != Load2->getOperand(3)) 14064b722108e2cf8e77157e0879a23789cd44829933Bill Wendling return false; 14074b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 14084b722108e2cf8e77157e0879a23789cd44829933Bill Wendling // Determine the offsets. 14094b722108e2cf8e77157e0879a23789cd44829933Bill Wendling if (isa<ConstantSDNode>(Load1->getOperand(1)) && 14104b722108e2cf8e77157e0879a23789cd44829933Bill Wendling isa<ConstantSDNode>(Load2->getOperand(1))) { 14114b722108e2cf8e77157e0879a23789cd44829933Bill Wendling Offset1 = cast<ConstantSDNode>(Load1->getOperand(1))->getSExtValue(); 14124b722108e2cf8e77157e0879a23789cd44829933Bill Wendling Offset2 = cast<ConstantSDNode>(Load2->getOperand(1))->getSExtValue(); 14134b722108e2cf8e77157e0879a23789cd44829933Bill Wendling return true; 14144b722108e2cf8e77157e0879a23789cd44829933Bill Wendling } 14154b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 14164b722108e2cf8e77157e0879a23789cd44829933Bill Wendling return false; 14174b722108e2cf8e77157e0879a23789cd44829933Bill Wendling} 14184b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 14194b722108e2cf8e77157e0879a23789cd44829933Bill Wendling/// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to 14207a2bdde0a0eebcd2125055e0eacaca040f0b766cChris Lattner/// determine (in conjunction with areLoadsFromSameBasePtr) if two loads should 14214b722108e2cf8e77157e0879a23789cd44829933Bill Wendling/// be scheduled togther. On some targets if two loads are loading from 14224b722108e2cf8e77157e0879a23789cd44829933Bill Wendling/// addresses in the same cache line, it's better if they are scheduled 14234b722108e2cf8e77157e0879a23789cd44829933Bill Wendling/// together. This function takes two integers that represent the load offsets 14244b722108e2cf8e77157e0879a23789cd44829933Bill Wendling/// from the common base address. It returns true if it decides it's desirable 14254b722108e2cf8e77157e0879a23789cd44829933Bill Wendling/// to schedule the two loads together. "NumLoads" is the number of loads that 14264b722108e2cf8e77157e0879a23789cd44829933Bill Wendling/// have already been scheduled after Load1. 14274b722108e2cf8e77157e0879a23789cd44829933Bill Wendlingbool ARMBaseInstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, 14284b722108e2cf8e77157e0879a23789cd44829933Bill Wendling int64_t Offset1, int64_t Offset2, 14294b722108e2cf8e77157e0879a23789cd44829933Bill Wendling unsigned NumLoads) const { 14304b722108e2cf8e77157e0879a23789cd44829933Bill Wendling // Don't worry about Thumb: just ARM and Thumb2. 14314b722108e2cf8e77157e0879a23789cd44829933Bill Wendling if (Subtarget.isThumb1Only()) return false; 14324b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 14334b722108e2cf8e77157e0879a23789cd44829933Bill Wendling assert(Offset2 > Offset1); 14344b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 14354b722108e2cf8e77157e0879a23789cd44829933Bill Wendling if ((Offset2 - Offset1) / 8 > 64) 14364b722108e2cf8e77157e0879a23789cd44829933Bill Wendling return false; 14374b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 14384b722108e2cf8e77157e0879a23789cd44829933Bill Wendling if (Load1->getMachineOpcode() != Load2->getMachineOpcode()) 14394b722108e2cf8e77157e0879a23789cd44829933Bill Wendling return false; // FIXME: overly conservative? 14404b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 14414b722108e2cf8e77157e0879a23789cd44829933Bill Wendling // Four loads in a row should be sufficient. 14424b722108e2cf8e77157e0879a23789cd44829933Bill Wendling if (NumLoads >= 3) 14434b722108e2cf8e77157e0879a23789cd44829933Bill Wendling return false; 14444b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 14454b722108e2cf8e77157e0879a23789cd44829933Bill Wendling return true; 14464b722108e2cf8e77157e0879a23789cd44829933Bill Wendling} 14474b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 144886050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Chengbool ARMBaseInstrInfo::isSchedulingBoundary(const MachineInstr *MI, 144986050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng const MachineBasicBlock *MBB, 145086050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng const MachineFunction &MF) const { 145157bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach // Debug info is never a scheduling boundary. It's necessary to be explicit 145257bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach // due to the special treatment of IT instructions below, otherwise a 145357bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach // dbg_value followed by an IT will result in the IT instruction being 145457bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach // considered a scheduling hazard, which is wrong. It should be the actual 145557bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach // instruction preceding the dbg_value instruction(s), just like it is 145657bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach // when debug info is not present. 145757bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach if (MI->isDebugValue()) 145857bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach return false; 145957bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach 146086050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // Terminators and labels can't be scheduled around. 14615a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng if (MI->isTerminator() || MI->isLabel()) 146286050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng return true; 146386050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng 146486050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // Treat the start of the IT block as a scheduling boundary, but schedule 146586050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // t2IT along with all instructions following it. 146686050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // FIXME: This is a big hammer. But the alternative is to add all potential 146786050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // true and anti dependencies to IT block instructions as implicit operands 146886050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // to the t2IT instruction. The added compile time and complexity does not 146986050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // seem worth it. 147086050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng MachineBasicBlock::const_iterator I = MI; 147157bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach // Make sure to skip any dbg_value instructions 147257bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach while (++I != MBB->end() && I->isDebugValue()) 147357bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach ; 147457bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach if (I != MBB->end() && I->getOpcode() == ARM::t2IT) 147586050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng return true; 147686050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng 147786050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // Don't attempt to schedule around any instruction that defines 147886050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // a stack-oriented pointer, as it's unlikely to be profitable. This 147986050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // saves compile time, because it doesn't require every single 148086050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // stack slot reference to depend on the instruction that does the 148186050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // modification. 1482a1aa8db51715bdd21770fbe4f7d7abf2c5d28829Jakob Stoklund Olesen // Calls don't actually change the stack pointer, even if they have imp-defs. 1483209600bb8830036f981238494ab0188c25364837Jakob Stoklund Olesen // No ARM calling conventions change the stack pointer. (X86 calling 1484209600bb8830036f981238494ab0188c25364837Jakob Stoklund Olesen // conventions sometimes do). 1485a1aa8db51715bdd21770fbe4f7d7abf2c5d28829Jakob Stoklund Olesen if (!MI->isCall() && MI->definesRegister(ARM::SP)) 148686050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng return true; 148786050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng 148886050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng return false; 148986050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng} 149086050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng 1491f81b7f6069b27c0a515070dcb392f6828437412fJakub Staszakbool ARMBaseInstrInfo:: 1492f81b7f6069b27c0a515070dcb392f6828437412fJakub StaszakisProfitableToIfCvt(MachineBasicBlock &MBB, 1493f81b7f6069b27c0a515070dcb392f6828437412fJakub Staszak unsigned NumCycles, unsigned ExtraPredCycles, 1494f81b7f6069b27c0a515070dcb392f6828437412fJakub Staszak const BranchProbability &Probability) const { 14955876db7a66fcc4ec4444a9f3e387c1cdc8baf9e5Cameron Zwarich if (!NumCycles) 149613151432edace19ee867a93b5c14573df4f75d24Evan Cheng return false; 14972bbb76909126db5bed6bde84b16d94ab5de4d372Michael J. Spencer 1498b20b85168c0e9819e6545f08281e9b83c82108f0Owen Anderson // Attempt to estimate the relative costs of predication versus branching. 1499f81b7f6069b27c0a515070dcb392f6828437412fJakub Staszak unsigned UnpredCost = Probability.getNumerator() * NumCycles; 1500f81b7f6069b27c0a515070dcb392f6828437412fJakub Staszak UnpredCost /= Probability.getDenominator(); 1501f81b7f6069b27c0a515070dcb392f6828437412fJakub Staszak UnpredCost += 1; // The branch itself 1502f81b7f6069b27c0a515070dcb392f6828437412fJakub Staszak UnpredCost += Subtarget.getMispredictionPenalty() / 10; 15032bbb76909126db5bed6bde84b16d94ab5de4d372Michael J. Spencer 1504f81b7f6069b27c0a515070dcb392f6828437412fJakub Staszak return (NumCycles + ExtraPredCycles) <= UnpredCost; 150513151432edace19ee867a93b5c14573df4f75d24Evan Cheng} 15062bbb76909126db5bed6bde84b16d94ab5de4d372Michael J. Spencer 150713151432edace19ee867a93b5c14573df4f75d24Evan Chengbool ARMBaseInstrInfo:: 15088239daf7c83a65a189c352cce3191cdc3bbfe151Evan ChengisProfitableToIfCvt(MachineBasicBlock &TMBB, 15098239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng unsigned TCycles, unsigned TExtra, 15108239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng MachineBasicBlock &FMBB, 15118239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng unsigned FCycles, unsigned FExtra, 1512f81b7f6069b27c0a515070dcb392f6828437412fJakub Staszak const BranchProbability &Probability) const { 15138239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng if (!TCycles || !FCycles) 1514b20b85168c0e9819e6545f08281e9b83c82108f0Owen Anderson return false; 15152bbb76909126db5bed6bde84b16d94ab5de4d372Michael J. Spencer 1516b20b85168c0e9819e6545f08281e9b83c82108f0Owen Anderson // Attempt to estimate the relative costs of predication versus branching. 1517f81b7f6069b27c0a515070dcb392f6828437412fJakub Staszak unsigned TUnpredCost = Probability.getNumerator() * TCycles; 1518f81b7f6069b27c0a515070dcb392f6828437412fJakub Staszak TUnpredCost /= Probability.getDenominator(); 1519e23dc9c0ef50b0a1934c04c1786f3a0478d62f41Andrew Trick 1520f81b7f6069b27c0a515070dcb392f6828437412fJakub Staszak uint32_t Comp = Probability.getDenominator() - Probability.getNumerator(); 1521f81b7f6069b27c0a515070dcb392f6828437412fJakub Staszak unsigned FUnpredCost = Comp * FCycles; 1522f81b7f6069b27c0a515070dcb392f6828437412fJakub Staszak FUnpredCost /= Probability.getDenominator(); 1523f81b7f6069b27c0a515070dcb392f6828437412fJakub Staszak 1524f81b7f6069b27c0a515070dcb392f6828437412fJakub Staszak unsigned UnpredCost = TUnpredCost + FUnpredCost; 1525f81b7f6069b27c0a515070dcb392f6828437412fJakub Staszak UnpredCost += 1; // The branch itself 1526f81b7f6069b27c0a515070dcb392f6828437412fJakub Staszak UnpredCost += Subtarget.getMispredictionPenalty() / 10; 1527f81b7f6069b27c0a515070dcb392f6828437412fJakub Staszak 1528f81b7f6069b27c0a515070dcb392f6828437412fJakub Staszak return (TCycles + FCycles + TExtra + FExtra) <= UnpredCost; 152913151432edace19ee867a93b5c14573df4f75d24Evan Cheng} 153013151432edace19ee867a93b5c14573df4f75d24Evan Cheng 15318fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng/// getInstrPredicate - If instruction is predicated, returns its predicate 15328fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng/// condition, otherwise returns AL. It also returns the condition code 15338fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng/// register by reference. 15345adb66a646e2ec32265263739f5b01c3f50c176aEvan ChengARMCC::CondCodes 15355adb66a646e2ec32265263739f5b01c3f50c176aEvan Chengllvm::getInstrPredicate(const MachineInstr *MI, unsigned &PredReg) { 15368fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng int PIdx = MI->findFirstPredOperandIdx(); 15378fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng if (PIdx == -1) { 15388fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng PredReg = 0; 15398fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng return ARMCC::AL; 15408fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng } 15418fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng 15428fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng PredReg = MI->getOperand(PIdx+1).getReg(); 15438fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng return (ARMCC::CondCodes)MI->getOperand(PIdx).getImm(); 15448fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng} 15458fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng 15468fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng 15476495f63945e8dbde81f03a1dc2ab421993b9a495Evan Chengint llvm::getMatchingCondBranchOpcode(int Opc) { 15485ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng if (Opc == ARM::B) 15495ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng return ARM::Bcc; 15504d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie if (Opc == ARM::tB) 15515ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng return ARM::tBcc; 15524d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie if (Opc == ARM::t2B) 15534d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie return ARM::t2Bcc; 15545ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng 15555ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng llvm_unreachable("Unknown unconditional branch opcode!"); 15565ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng} 15575ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng 1558c5041cac7d3aeaa7350abadf2a7ada92e8da27dcJakob Stoklund Olesen/// commuteInstruction - Handle commutable instructions. 1559c5041cac7d3aeaa7350abadf2a7ada92e8da27dcJakob Stoklund OlesenMachineInstr * 1560c5041cac7d3aeaa7350abadf2a7ada92e8da27dcJakob Stoklund OlesenARMBaseInstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const { 1561c5041cac7d3aeaa7350abadf2a7ada92e8da27dcJakob Stoklund Olesen switch (MI->getOpcode()) { 1562c5041cac7d3aeaa7350abadf2a7ada92e8da27dcJakob Stoklund Olesen case ARM::MOVCCr: 1563c5041cac7d3aeaa7350abadf2a7ada92e8da27dcJakob Stoklund Olesen case ARM::t2MOVCCr: { 1564c5041cac7d3aeaa7350abadf2a7ada92e8da27dcJakob Stoklund Olesen // MOVCC can be commuted by inverting the condition. 1565c5041cac7d3aeaa7350abadf2a7ada92e8da27dcJakob Stoklund Olesen unsigned PredReg = 0; 1566c5041cac7d3aeaa7350abadf2a7ada92e8da27dcJakob Stoklund Olesen ARMCC::CondCodes CC = getInstrPredicate(MI, PredReg); 1567c5041cac7d3aeaa7350abadf2a7ada92e8da27dcJakob Stoklund Olesen // MOVCC AL can't be inverted. Shouldn't happen. 1568c5041cac7d3aeaa7350abadf2a7ada92e8da27dcJakob Stoklund Olesen if (CC == ARMCC::AL || PredReg != ARM::CPSR) 1569c5041cac7d3aeaa7350abadf2a7ada92e8da27dcJakob Stoklund Olesen return NULL; 1570c5041cac7d3aeaa7350abadf2a7ada92e8da27dcJakob Stoklund Olesen MI = TargetInstrInfoImpl::commuteInstruction(MI, NewMI); 1571c5041cac7d3aeaa7350abadf2a7ada92e8da27dcJakob Stoklund Olesen if (!MI) 1572c5041cac7d3aeaa7350abadf2a7ada92e8da27dcJakob Stoklund Olesen return NULL; 1573c5041cac7d3aeaa7350abadf2a7ada92e8da27dcJakob Stoklund Olesen // After swapping the MOVCC operands, also invert the condition. 1574c5041cac7d3aeaa7350abadf2a7ada92e8da27dcJakob Stoklund Olesen MI->getOperand(MI->findFirstPredOperandIdx()) 1575c5041cac7d3aeaa7350abadf2a7ada92e8da27dcJakob Stoklund Olesen .setImm(ARMCC::getOppositeCondition(CC)); 1576c5041cac7d3aeaa7350abadf2a7ada92e8da27dcJakob Stoklund Olesen return MI; 1577c5041cac7d3aeaa7350abadf2a7ada92e8da27dcJakob Stoklund Olesen } 1578c5041cac7d3aeaa7350abadf2a7ada92e8da27dcJakob Stoklund Olesen } 1579c5041cac7d3aeaa7350abadf2a7ada92e8da27dcJakob Stoklund Olesen return TargetInstrInfoImpl::commuteInstruction(MI, NewMI); 1580c5041cac7d3aeaa7350abadf2a7ada92e8da27dcJakob Stoklund Olesen} 15816495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 15822860b7ea3a1d60213ee7228bd274bc4f8b170772Jakob Stoklund Olesen/// Identify instructions that can be folded into a MOVCC instruction, and 1583098c6a547fe540b3bbace4c3d4713f400c67b8a9Jakob Stoklund Olesen/// return the defining instruction. 1584098c6a547fe540b3bbace4c3d4713f400c67b8a9Jakob Stoklund Olesenstatic MachineInstr *canFoldIntoMOVCC(unsigned Reg, 1585098c6a547fe540b3bbace4c3d4713f400c67b8a9Jakob Stoklund Olesen const MachineRegisterInfo &MRI, 1586098c6a547fe540b3bbace4c3d4713f400c67b8a9Jakob Stoklund Olesen const TargetInstrInfo *TII) { 15872860b7ea3a1d60213ee7228bd274bc4f8b170772Jakob Stoklund Olesen if (!TargetRegisterInfo::isVirtualRegister(Reg)) 15882860b7ea3a1d60213ee7228bd274bc4f8b170772Jakob Stoklund Olesen return 0; 15892860b7ea3a1d60213ee7228bd274bc4f8b170772Jakob Stoklund Olesen if (!MRI.hasOneNonDBGUse(Reg)) 15902860b7ea3a1d60213ee7228bd274bc4f8b170772Jakob Stoklund Olesen return 0; 1591098c6a547fe540b3bbace4c3d4713f400c67b8a9Jakob Stoklund Olesen MachineInstr *MI = MRI.getVRegDef(Reg); 15922860b7ea3a1d60213ee7228bd274bc4f8b170772Jakob Stoklund Olesen if (!MI) 15932860b7ea3a1d60213ee7228bd274bc4f8b170772Jakob Stoklund Olesen return 0; 1594098c6a547fe540b3bbace4c3d4713f400c67b8a9Jakob Stoklund Olesen // MI is folded into the MOVCC by predicating it. 1595098c6a547fe540b3bbace4c3d4713f400c67b8a9Jakob Stoklund Olesen if (!MI->isPredicable()) 1596098c6a547fe540b3bbace4c3d4713f400c67b8a9Jakob Stoklund Olesen return 0; 15972860b7ea3a1d60213ee7228bd274bc4f8b170772Jakob Stoklund Olesen // Check if MI has any non-dead defs or physreg uses. This also detects 15982860b7ea3a1d60213ee7228bd274bc4f8b170772Jakob Stoklund Olesen // predicated instructions which will be reading CPSR. 15992860b7ea3a1d60213ee7228bd274bc4f8b170772Jakob Stoklund Olesen for (unsigned i = 1, e = MI->getNumOperands(); i != e; ++i) { 16002860b7ea3a1d60213ee7228bd274bc4f8b170772Jakob Stoklund Olesen const MachineOperand &MO = MI->getOperand(i); 1601a7fb3f68047556a7355e1f1080fb3d1ca9eb7078Jakob Stoklund Olesen // Reject frame index operands, PEI can't handle the predicated pseudos. 1602a7fb3f68047556a7355e1f1080fb3d1ca9eb7078Jakob Stoklund Olesen if (MO.isFI() || MO.isCPI() || MO.isJTI()) 1603a7fb3f68047556a7355e1f1080fb3d1ca9eb7078Jakob Stoklund Olesen return 0; 16042860b7ea3a1d60213ee7228bd274bc4f8b170772Jakob Stoklund Olesen if (!MO.isReg()) 16052860b7ea3a1d60213ee7228bd274bc4f8b170772Jakob Stoklund Olesen continue; 1606098c6a547fe540b3bbace4c3d4713f400c67b8a9Jakob Stoklund Olesen // MI can't have any tied operands, that would conflict with predication. 1607098c6a547fe540b3bbace4c3d4713f400c67b8a9Jakob Stoklund Olesen if (MO.isTied()) 1608098c6a547fe540b3bbace4c3d4713f400c67b8a9Jakob Stoklund Olesen return 0; 16092860b7ea3a1d60213ee7228bd274bc4f8b170772Jakob Stoklund Olesen if (TargetRegisterInfo::isPhysicalRegister(MO.getReg())) 16102860b7ea3a1d60213ee7228bd274bc4f8b170772Jakob Stoklund Olesen return 0; 16112860b7ea3a1d60213ee7228bd274bc4f8b170772Jakob Stoklund Olesen if (MO.isDef() && !MO.isDead()) 16122860b7ea3a1d60213ee7228bd274bc4f8b170772Jakob Stoklund Olesen return 0; 16132860b7ea3a1d60213ee7228bd274bc4f8b170772Jakob Stoklund Olesen } 1614098c6a547fe540b3bbace4c3d4713f400c67b8a9Jakob Stoklund Olesen bool DontMoveAcrossStores = true; 1615098c6a547fe540b3bbace4c3d4713f400c67b8a9Jakob Stoklund Olesen if (!MI->isSafeToMove(TII, /* AliasAnalysis = */ 0, DontMoveAcrossStores)) 1616098c6a547fe540b3bbace4c3d4713f400c67b8a9Jakob Stoklund Olesen return 0; 1617098c6a547fe540b3bbace4c3d4713f400c67b8a9Jakob Stoklund Olesen return MI; 16182860b7ea3a1d60213ee7228bd274bc4f8b170772Jakob Stoklund Olesen} 16192860b7ea3a1d60213ee7228bd274bc4f8b170772Jakob Stoklund Olesen 1620053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesenbool ARMBaseInstrInfo::analyzeSelect(const MachineInstr *MI, 1621053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen SmallVectorImpl<MachineOperand> &Cond, 1622053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen unsigned &TrueOp, unsigned &FalseOp, 1623053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen bool &Optimizable) const { 1624053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen assert((MI->getOpcode() == ARM::MOVCCr || MI->getOpcode() == ARM::t2MOVCCr) && 1625053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen "Unknown select instruction"); 1626053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen // MOVCC operands: 1627053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen // 0: Def. 1628053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen // 1: True use. 1629053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen // 2: False use. 1630053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen // 3: Condition code. 1631053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen // 4: CPSR use. 1632053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen TrueOp = 1; 1633053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen FalseOp = 2; 1634053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen Cond.push_back(MI->getOperand(3)); 1635053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen Cond.push_back(MI->getOperand(4)); 1636053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen // We can always fold a def. 1637053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen Optimizable = true; 1638053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen return false; 1639053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen} 1640053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen 1641053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund OlesenMachineInstr *ARMBaseInstrInfo::optimizeSelect(MachineInstr *MI, 1642053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen bool PreferFalse) const { 1643053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen assert((MI->getOpcode() == ARM::MOVCCr || MI->getOpcode() == ARM::t2MOVCCr) && 1644053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen "Unknown select instruction"); 1645053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen const MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo(); 1646098c6a547fe540b3bbace4c3d4713f400c67b8a9Jakob Stoklund Olesen MachineInstr *DefMI = canFoldIntoMOVCC(MI->getOperand(2).getReg(), MRI, this); 1647098c6a547fe540b3bbace4c3d4713f400c67b8a9Jakob Stoklund Olesen bool Invert = !DefMI; 1648098c6a547fe540b3bbace4c3d4713f400c67b8a9Jakob Stoklund Olesen if (!DefMI) 1649098c6a547fe540b3bbace4c3d4713f400c67b8a9Jakob Stoklund Olesen DefMI = canFoldIntoMOVCC(MI->getOperand(1).getReg(), MRI, this); 1650098c6a547fe540b3bbace4c3d4713f400c67b8a9Jakob Stoklund Olesen if (!DefMI) 1651053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen return 0; 1652053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen 1653053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen // Create a new predicated version of DefMI. 1654053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen // Rfalse is the first use. 1655053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen MachineInstrBuilder NewMI = BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), 1656098c6a547fe540b3bbace4c3d4713f400c67b8a9Jakob Stoklund Olesen DefMI->getDesc(), 1657098c6a547fe540b3bbace4c3d4713f400c67b8a9Jakob Stoklund Olesen MI->getOperand(0).getReg()); 1658053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen 1659053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen // Copy all the DefMI operands, excluding its (null) predicate. 1660053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen const MCInstrDesc &DefDesc = DefMI->getDesc(); 1661053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen for (unsigned i = 1, e = DefDesc.getNumOperands(); 1662053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen i != e && !DefDesc.OpInfo[i].isPredicate(); ++i) 1663053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen NewMI.addOperand(DefMI->getOperand(i)); 1664053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen 1665053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen unsigned CondCode = MI->getOperand(3).getImm(); 1666053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen if (Invert) 1667053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen NewMI.addImm(ARMCC::getOppositeCondition(ARMCC::CondCodes(CondCode))); 1668053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen else 1669053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen NewMI.addImm(CondCode); 1670053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen NewMI.addOperand(MI->getOperand(4)); 1671053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen 1672053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen // DefMI is not the -S version that sets CPSR, so add an optional %noreg. 1673053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen if (NewMI->hasOptionalDef()) 1674053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen AddDefaultCC(NewMI); 1675053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen 1676098c6a547fe540b3bbace4c3d4713f400c67b8a9Jakob Stoklund Olesen // The output register value when the predicate is false is an implicit 1677098c6a547fe540b3bbace4c3d4713f400c67b8a9Jakob Stoklund Olesen // register operand tied to the first def. 1678098c6a547fe540b3bbace4c3d4713f400c67b8a9Jakob Stoklund Olesen // The tie makes the register allocator ensure the FalseReg is allocated the 1679098c6a547fe540b3bbace4c3d4713f400c67b8a9Jakob Stoklund Olesen // same register as operand 0. 1680098c6a547fe540b3bbace4c3d4713f400c67b8a9Jakob Stoklund Olesen MachineOperand FalseReg = MI->getOperand(Invert ? 2 : 1); 1681098c6a547fe540b3bbace4c3d4713f400c67b8a9Jakob Stoklund Olesen FalseReg.setImplicit(); 1682098c6a547fe540b3bbace4c3d4713f400c67b8a9Jakob Stoklund Olesen NewMI->addOperand(FalseReg); 1683098c6a547fe540b3bbace4c3d4713f400c67b8a9Jakob Stoklund Olesen NewMI->tieOperands(0, NewMI->getNumOperands() - 1); 1684098c6a547fe540b3bbace4c3d4713f400c67b8a9Jakob Stoklund Olesen 1685053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen // The caller will erase MI, but not DefMI. 1686053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen DefMI->eraseFromParent(); 1687053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen return NewMI; 1688053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen} 1689053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen 16903be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick/// Map pseudo instructions that imply an 'S' bit onto real opcodes. Whether the 16913be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick/// instruction is encoded with an 'S' bit is determined by the optional CPSR 16923be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick/// def operand. 16933be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick/// 16943be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick/// This will go away once we can teach tblgen how to set the optional CPSR def 16953be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick/// operand itself. 16963be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trickstruct AddSubFlagsOpcodePair { 1697cd2859eef83708c00330c94f6842499b48d5ed02Craig Topper uint16_t PseudoOpc; 1698cd2859eef83708c00330c94f6842499b48d5ed02Craig Topper uint16_t MachineOpc; 16993be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick}; 17003be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick 1701cd2859eef83708c00330c94f6842499b48d5ed02Craig Topperstatic const AddSubFlagsOpcodePair AddSubFlagsOpcodeMap[] = { 17023be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick {ARM::ADDSri, ARM::ADDri}, 17033be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick {ARM::ADDSrr, ARM::ADDrr}, 17043be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick {ARM::ADDSrsi, ARM::ADDrsi}, 17053be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick {ARM::ADDSrsr, ARM::ADDrsr}, 17063be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick 17073be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick {ARM::SUBSri, ARM::SUBri}, 17083be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick {ARM::SUBSrr, ARM::SUBrr}, 17093be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick {ARM::SUBSrsi, ARM::SUBrsi}, 17103be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick {ARM::SUBSrsr, ARM::SUBrsr}, 17113be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick 17123be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick {ARM::RSBSri, ARM::RSBri}, 17133be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick {ARM::RSBSrsi, ARM::RSBrsi}, 17143be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick {ARM::RSBSrsr, ARM::RSBrsr}, 17153be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick 17163be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick {ARM::t2ADDSri, ARM::t2ADDri}, 17173be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick {ARM::t2ADDSrr, ARM::t2ADDrr}, 17183be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick {ARM::t2ADDSrs, ARM::t2ADDrs}, 17193be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick 17203be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick {ARM::t2SUBSri, ARM::t2SUBri}, 17213be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick {ARM::t2SUBSrr, ARM::t2SUBrr}, 17223be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick {ARM::t2SUBSrs, ARM::t2SUBrs}, 17233be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick 17243be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick {ARM::t2RSBSri, ARM::t2RSBri}, 17253be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick {ARM::t2RSBSrs, ARM::t2RSBrs}, 17263be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick}; 17273be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick 17283be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trickunsigned llvm::convertAddSubFlagsOpcode(unsigned OldOpc) { 1729cd2859eef83708c00330c94f6842499b48d5ed02Craig Topper for (unsigned i = 0, e = array_lengthof(AddSubFlagsOpcodeMap); i != e; ++i) 1730cd2859eef83708c00330c94f6842499b48d5ed02Craig Topper if (OldOpc == AddSubFlagsOpcodeMap[i].PseudoOpc) 1731cd2859eef83708c00330c94f6842499b48d5ed02Craig Topper return AddSubFlagsOpcodeMap[i].MachineOpc; 17323be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick return 0; 17333be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick} 17343be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick 17356495f63945e8dbde81f03a1dc2ab421993b9a495Evan Chengvoid llvm::emitARMRegPlusImmediate(MachineBasicBlock &MBB, 17366495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MachineBasicBlock::iterator &MBBI, DebugLoc dl, 17376495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned DestReg, unsigned BaseReg, int NumBytes, 17386495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ARMCC::CondCodes Pred, unsigned PredReg, 173957caad7a33ff145b71545f10dcfbbf2fd0f595d3Anton Korobeynikov const ARMBaseInstrInfo &TII, unsigned MIFlags) { 17406495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng bool isSub = NumBytes < 0; 17416495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (isSub) NumBytes = -NumBytes; 17426495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 17436495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng while (NumBytes) { 17446495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned RotAmt = ARM_AM::getSOImmValRotate(NumBytes); 17456495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned ThisVal = NumBytes & ARM_AM::rotr32(0xFF, RotAmt); 17466495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng assert(ThisVal && "Didn't extract field correctly"); 17476495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 17486495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // We will handle these bits from offset, clear them. 17496495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng NumBytes &= ~ThisVal; 17506495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 17516495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng assert(ARM_AM::getSOImmVal(ThisVal) != -1 && "Bit extraction didn't work?"); 17526495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 17536495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Build the new ADD / SUB. 17546495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned Opc = isSub ? ARM::SUBri : ARM::ADDri; 17556495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg) 17566495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng .addReg(BaseReg, RegState::Kill).addImm(ThisVal) 175757caad7a33ff145b71545f10dcfbbf2fd0f595d3Anton Korobeynikov .addImm((unsigned)Pred).addReg(PredReg).addReg(0) 175857caad7a33ff145b71545f10dcfbbf2fd0f595d3Anton Korobeynikov .setMIFlags(MIFlags); 17596495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng BaseReg = DestReg; 17606495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 17616495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng} 17626495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 1763cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Chengbool llvm::rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx, 1764cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng unsigned FrameReg, int &Offset, 1765cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng const ARMBaseInstrInfo &TII) { 17666495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned Opcode = MI.getOpcode(); 1767e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng const MCInstrDesc &Desc = MI.getDesc(); 17686495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask); 17696495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng bool isSub = false; 1770764ab52dd80310a205c9888bf166d09dab858f90Jim Grosbach 17716495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Memory operands in inline assembly always use AddrMode2. 17726495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (Opcode == ARM::INLINEASM) 17736495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng AddrMode = ARMII::AddrMode2; 1774764ab52dd80310a205c9888bf166d09dab858f90Jim Grosbach 17756495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (Opcode == ARM::ADDri) { 17766495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng Offset += MI.getOperand(FrameRegIdx+1).getImm(); 17776495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (Offset == 0) { 17786495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Turn it into a move. 17796495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MI.setDesc(TII.get(ARM::MOVr)); 17806495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false); 17816495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MI.RemoveOperand(FrameRegIdx+1); 1782cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng Offset = 0; 1783cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng return true; 17846495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } else if (Offset < 0) { 17856495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng Offset = -Offset; 17866495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng isSub = true; 17876495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MI.setDesc(TII.get(ARM::SUBri)); 17886495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 17896495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 17906495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Common case: small offset, fits into instruction. 17916495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (ARM_AM::getSOImmVal(Offset) != -1) { 17926495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Replace the FrameIndex with sp / fp 17936495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false); 17946495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset); 1795cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng Offset = 0; 1796cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng return true; 17976495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 17986495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 17996495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Otherwise, pull as much of the immedidate into this ADDri/SUBri 18006495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // as possible. 18016495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned RotAmt = ARM_AM::getSOImmValRotate(Offset); 18026495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xFF, RotAmt); 18036495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 18046495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // We will handle these bits from offset, clear them. 18056495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng Offset &= ~ThisImmVal; 18066495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 18076495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Get the properly encoded SOImmVal field. 18086495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng assert(ARM_AM::getSOImmVal(ThisImmVal) != -1 && 18096495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng "Bit extraction didn't work?"); 18106495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MI.getOperand(FrameRegIdx+1).ChangeToImmediate(ThisImmVal); 18116495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } else { 18126495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned ImmIdx = 0; 18136495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng int InstrOffs = 0; 18146495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned NumBits = 0; 18156495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned Scale = 1; 18166495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng switch (AddrMode) { 18173e5561247202bae994dd259a2d8dc4eff8f799f3Jim Grosbach case ARMII::AddrMode_i12: { 18183e5561247202bae994dd259a2d8dc4eff8f799f3Jim Grosbach ImmIdx = FrameRegIdx + 1; 18193e5561247202bae994dd259a2d8dc4eff8f799f3Jim Grosbach InstrOffs = MI.getOperand(ImmIdx).getImm(); 18203e5561247202bae994dd259a2d8dc4eff8f799f3Jim Grosbach NumBits = 12; 18213e5561247202bae994dd259a2d8dc4eff8f799f3Jim Grosbach break; 18223e5561247202bae994dd259a2d8dc4eff8f799f3Jim Grosbach } 18236495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng case ARMII::AddrMode2: { 18246495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ImmIdx = FrameRegIdx+2; 18256495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng InstrOffs = ARM_AM::getAM2Offset(MI.getOperand(ImmIdx).getImm()); 18266495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (ARM_AM::getAM2Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub) 18276495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng InstrOffs *= -1; 18286495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng NumBits = 12; 18296495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng break; 18306495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 18316495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng case ARMII::AddrMode3: { 18326495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ImmIdx = FrameRegIdx+2; 18336495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng InstrOffs = ARM_AM::getAM3Offset(MI.getOperand(ImmIdx).getImm()); 18346495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (ARM_AM::getAM3Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub) 18356495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng InstrOffs *= -1; 18366495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng NumBits = 8; 18376495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng break; 18386495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 1839baf31088f1472f48ea5ae81f0b93636cc44ca444Anton Korobeynikov case ARMII::AddrMode4: 1840a44321776ecd96fa0344335d3027758be3386e45Jim Grosbach case ARMII::AddrMode6: 1841cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng // Can't fold any offset even if it's zero. 1842cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng return false; 18436495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng case ARMII::AddrMode5: { 18446495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ImmIdx = FrameRegIdx+1; 18456495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng InstrOffs = ARM_AM::getAM5Offset(MI.getOperand(ImmIdx).getImm()); 18466495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (ARM_AM::getAM5Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub) 18476495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng InstrOffs *= -1; 18486495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng NumBits = 8; 18496495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng Scale = 4; 18506495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng break; 18516495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 18526495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng default: 18536495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng llvm_unreachable("Unsupported addressing mode!"); 18546495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 18556495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 18566495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng Offset += InstrOffs * Scale; 18576495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!"); 18586495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (Offset < 0) { 18596495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng Offset = -Offset; 18606495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng isSub = true; 18616495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 18626495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 18636495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Attempt to fold address comp. if opcode has offset bits 18646495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (NumBits > 0) { 18656495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Common case: small offset, fits into instruction. 18666495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MachineOperand &ImmOp = MI.getOperand(ImmIdx); 18676495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng int ImmedOffset = Offset / Scale; 18686495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned Mask = (1 << NumBits) - 1; 18696495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if ((unsigned)Offset <= Mask * Scale) { 18706495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Replace the FrameIndex with sp 18716495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false); 187277aee8e22c36257716c2df2f275724765704f20cJim Grosbach // FIXME: When addrmode2 goes away, this will simplify (like the 187377aee8e22c36257716c2df2f275724765704f20cJim Grosbach // T2 version), as the LDR.i12 versions don't need the encoding 187477aee8e22c36257716c2df2f275724765704f20cJim Grosbach // tricks for the offset value. 187577aee8e22c36257716c2df2f275724765704f20cJim Grosbach if (isSub) { 187677aee8e22c36257716c2df2f275724765704f20cJim Grosbach if (AddrMode == ARMII::AddrMode_i12) 187777aee8e22c36257716c2df2f275724765704f20cJim Grosbach ImmedOffset = -ImmedOffset; 187877aee8e22c36257716c2df2f275724765704f20cJim Grosbach else 187977aee8e22c36257716c2df2f275724765704f20cJim Grosbach ImmedOffset |= 1 << NumBits; 188077aee8e22c36257716c2df2f275724765704f20cJim Grosbach } 18816495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ImmOp.ChangeToImmediate(ImmedOffset); 1882cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng Offset = 0; 1883cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng return true; 18846495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 1885764ab52dd80310a205c9888bf166d09dab858f90Jim Grosbach 18866495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Otherwise, it didn't fit. Pull in what we can to simplify the immed. 18876495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ImmedOffset = ImmedOffset & Mask; 1888063efbf569e46776093ddf50099c98fdbb362167Jim Grosbach if (isSub) { 1889063efbf569e46776093ddf50099c98fdbb362167Jim Grosbach if (AddrMode == ARMII::AddrMode_i12) 1890063efbf569e46776093ddf50099c98fdbb362167Jim Grosbach ImmedOffset = -ImmedOffset; 1891063efbf569e46776093ddf50099c98fdbb362167Jim Grosbach else 1892063efbf569e46776093ddf50099c98fdbb362167Jim Grosbach ImmedOffset |= 1 << NumBits; 1893063efbf569e46776093ddf50099c98fdbb362167Jim Grosbach } 18946495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ImmOp.ChangeToImmediate(ImmedOffset); 18956495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng Offset &= ~(Mask*Scale); 18966495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 18976495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 18986495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 1899cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng Offset = (isSub) ? -Offset : Offset; 1900cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng return Offset == 0; 19016495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng} 1902e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling 1903de7266c611b37ec050efb53b73166081a98cea13Manman Ren/// analyzeCompare - For a comparison instruction, return the source registers 1904de7266c611b37ec050efb53b73166081a98cea13Manman Ren/// in SrcReg and SrcReg2 if having two register operands, and the value it 1905de7266c611b37ec050efb53b73166081a98cea13Manman Ren/// compares against in CmpValue. Return true if the comparison instruction 1906de7266c611b37ec050efb53b73166081a98cea13Manman Ren/// can be analyzed. 1907e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendlingbool ARMBaseInstrInfo:: 1908de7266c611b37ec050efb53b73166081a98cea13Manman RenanalyzeCompare(const MachineInstr *MI, unsigned &SrcReg, unsigned &SrcReg2, 1909de7266c611b37ec050efb53b73166081a98cea13Manman Ren int &CmpMask, int &CmpValue) const { 1910e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling switch (MI->getOpcode()) { 1911e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling default: break; 191238ae997e63e3e1bb2c8679e01ea74cf8fd0be893Bill Wendling case ARM::CMPri: 1913e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling case ARM::t2CMPri: 1914e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling SrcReg = MI->getOperand(0).getReg(); 1915de7266c611b37ec050efb53b73166081a98cea13Manman Ren SrcReg2 = 0; 191604ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif CmpMask = ~0; 1917e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling CmpValue = MI->getOperand(1).getImm(); 1918e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling return true; 1919247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren case ARM::CMPrr: 1920247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren case ARM::t2CMPrr: 1921247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren SrcReg = MI->getOperand(0).getReg(); 1922de7266c611b37ec050efb53b73166081a98cea13Manman Ren SrcReg2 = MI->getOperand(1).getReg(); 1923247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren CmpMask = ~0; 1924247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren CmpValue = 0; 1925247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren return true; 192604ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif case ARM::TSTri: 192704ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif case ARM::t2TSTri: 192804ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif SrcReg = MI->getOperand(0).getReg(); 1929de7266c611b37ec050efb53b73166081a98cea13Manman Ren SrcReg2 = 0; 193004ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif CmpMask = MI->getOperand(1).getImm(); 193104ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif CmpValue = 0; 193204ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif return true; 193304ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif } 193404ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif 193504ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif return false; 193604ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif} 193704ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif 193805642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif/// isSuitableForMask - Identify a suitable 'and' instruction that 193905642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif/// operates on the given source register and applies the same mask 194005642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif/// as a 'tst' instruction. Provide a limited look-through for copies. 194105642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif/// When successful, MI will hold the found instruction. 194205642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greifstatic bool isSuitableForMask(MachineInstr *&MI, unsigned SrcReg, 19438ff9bb189ce188452e6cae6ed65cb2745814126cGabor Greif int CmpMask, bool CommonUse) { 194405642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif switch (MI->getOpcode()) { 194504ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif case ARM::ANDri: 194604ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif case ARM::t2ANDri: 194705642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif if (CmpMask != MI->getOperand(2).getImm()) 19488ff9bb189ce188452e6cae6ed65cb2745814126cGabor Greif return false; 194905642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif if (SrcReg == MI->getOperand(CommonUse ? 1 : 0).getReg()) 195004ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif return true; 195104ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif break; 195205642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif case ARM::COPY: { 195305642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif // Walk down one instruction which is potentially an 'and'. 195405642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif const MachineInstr &Copy = *MI; 1955f000a7a212590bfd45e23c05bff5e1b683d25dd6Michael J. Spencer MachineBasicBlock::iterator AND( 1956f000a7a212590bfd45e23c05bff5e1b683d25dd6Michael J. Spencer llvm::next(MachineBasicBlock::iterator(MI))); 195705642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif if (AND == MI->getParent()->end()) return false; 195805642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif MI = AND; 195905642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif return isSuitableForMask(MI, Copy.getOperand(0).getReg(), 196005642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif CmpMask, true); 196105642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif } 1962e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling } 1963e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling 1964e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling return false; 1965e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling} 1966e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling 196776c6ccbd4cee0637c961e32435177ab89e931fedManman Ren/// getSwappedCondition - assume the flags are set by MI(a,b), return 196876c6ccbd4cee0637c961e32435177ab89e931fedManman Ren/// the condition code if we modify the instructions such that flags are 196976c6ccbd4cee0637c961e32435177ab89e931fedManman Ren/// set by MI(b,a). 197076c6ccbd4cee0637c961e32435177ab89e931fedManman Reninline static ARMCC::CondCodes getSwappedCondition(ARMCC::CondCodes CC) { 197176c6ccbd4cee0637c961e32435177ab89e931fedManman Ren switch (CC) { 197276c6ccbd4cee0637c961e32435177ab89e931fedManman Ren default: return ARMCC::AL; 197376c6ccbd4cee0637c961e32435177ab89e931fedManman Ren case ARMCC::EQ: return ARMCC::EQ; 197476c6ccbd4cee0637c961e32435177ab89e931fedManman Ren case ARMCC::NE: return ARMCC::NE; 197576c6ccbd4cee0637c961e32435177ab89e931fedManman Ren case ARMCC::HS: return ARMCC::LS; 197676c6ccbd4cee0637c961e32435177ab89e931fedManman Ren case ARMCC::LO: return ARMCC::HI; 197776c6ccbd4cee0637c961e32435177ab89e931fedManman Ren case ARMCC::HI: return ARMCC::LO; 197876c6ccbd4cee0637c961e32435177ab89e931fedManman Ren case ARMCC::LS: return ARMCC::HS; 197976c6ccbd4cee0637c961e32435177ab89e931fedManman Ren case ARMCC::GE: return ARMCC::LE; 198076c6ccbd4cee0637c961e32435177ab89e931fedManman Ren case ARMCC::LT: return ARMCC::GT; 198176c6ccbd4cee0637c961e32435177ab89e931fedManman Ren case ARMCC::GT: return ARMCC::LT; 198276c6ccbd4cee0637c961e32435177ab89e931fedManman Ren case ARMCC::LE: return ARMCC::GE; 198376c6ccbd4cee0637c961e32435177ab89e931fedManman Ren } 198476c6ccbd4cee0637c961e32435177ab89e931fedManman Ren} 198576c6ccbd4cee0637c961e32435177ab89e931fedManman Ren 198676c6ccbd4cee0637c961e32435177ab89e931fedManman Ren/// isRedundantFlagInstr - check whether the first instruction, whose only 198776c6ccbd4cee0637c961e32435177ab89e931fedManman Ren/// purpose is to update flags, can be made redundant. 198876c6ccbd4cee0637c961e32435177ab89e931fedManman Ren/// CMPrr can be made redundant by SUBrr if the operands are the same. 198976c6ccbd4cee0637c961e32435177ab89e931fedManman Ren/// CMPri can be made redundant by SUBri if the operands are the same. 199076c6ccbd4cee0637c961e32435177ab89e931fedManman Ren/// This function can be extended later on. 199176c6ccbd4cee0637c961e32435177ab89e931fedManman Reninline static bool isRedundantFlagInstr(MachineInstr *CmpI, unsigned SrcReg, 199276c6ccbd4cee0637c961e32435177ab89e931fedManman Ren unsigned SrcReg2, int ImmValue, 199376c6ccbd4cee0637c961e32435177ab89e931fedManman Ren MachineInstr *OI) { 199476c6ccbd4cee0637c961e32435177ab89e931fedManman Ren if ((CmpI->getOpcode() == ARM::CMPrr || 199576c6ccbd4cee0637c961e32435177ab89e931fedManman Ren CmpI->getOpcode() == ARM::t2CMPrr) && 199676c6ccbd4cee0637c961e32435177ab89e931fedManman Ren (OI->getOpcode() == ARM::SUBrr || 199776c6ccbd4cee0637c961e32435177ab89e931fedManman Ren OI->getOpcode() == ARM::t2SUBrr) && 199876c6ccbd4cee0637c961e32435177ab89e931fedManman Ren ((OI->getOperand(1).getReg() == SrcReg && 199976c6ccbd4cee0637c961e32435177ab89e931fedManman Ren OI->getOperand(2).getReg() == SrcReg2) || 200076c6ccbd4cee0637c961e32435177ab89e931fedManman Ren (OI->getOperand(1).getReg() == SrcReg2 && 200176c6ccbd4cee0637c961e32435177ab89e931fedManman Ren OI->getOperand(2).getReg() == SrcReg))) 200276c6ccbd4cee0637c961e32435177ab89e931fedManman Ren return true; 200376c6ccbd4cee0637c961e32435177ab89e931fedManman Ren 200476c6ccbd4cee0637c961e32435177ab89e931fedManman Ren if ((CmpI->getOpcode() == ARM::CMPri || 200576c6ccbd4cee0637c961e32435177ab89e931fedManman Ren CmpI->getOpcode() == ARM::t2CMPri) && 200676c6ccbd4cee0637c961e32435177ab89e931fedManman Ren (OI->getOpcode() == ARM::SUBri || 200776c6ccbd4cee0637c961e32435177ab89e931fedManman Ren OI->getOpcode() == ARM::t2SUBri) && 200876c6ccbd4cee0637c961e32435177ab89e931fedManman Ren OI->getOperand(1).getReg() == SrcReg && 200976c6ccbd4cee0637c961e32435177ab89e931fedManman Ren OI->getOperand(2).getImm() == ImmValue) 201076c6ccbd4cee0637c961e32435177ab89e931fedManman Ren return true; 201176c6ccbd4cee0637c961e32435177ab89e931fedManman Ren return false; 201276c6ccbd4cee0637c961e32435177ab89e931fedManman Ren} 201376c6ccbd4cee0637c961e32435177ab89e931fedManman Ren 2014de7266c611b37ec050efb53b73166081a98cea13Manman Ren/// optimizeCompareInstr - Convert the instruction supplying the argument to the 2015de7266c611b37ec050efb53b73166081a98cea13Manman Ren/// comparison into one that sets the zero bit in the flags register; 2016de7266c611b37ec050efb53b73166081a98cea13Manman Ren/// Remove a redundant Compare instruction if an earlier instruction can set the 2017de7266c611b37ec050efb53b73166081a98cea13Manman Ren/// flags in the same way as Compare. 2018de7266c611b37ec050efb53b73166081a98cea13Manman Ren/// E.g. SUBrr(r1,r2) and CMPrr(r1,r2). We also handle the case where two 2019de7266c611b37ec050efb53b73166081a98cea13Manman Ren/// operands are swapped: SUBrr(r1,r2) and CMPrr(r2,r1), by updating the 2020de7266c611b37ec050efb53b73166081a98cea13Manman Ren/// condition code of instructions which use the flags. 2021e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendlingbool ARMBaseInstrInfo:: 2022de7266c611b37ec050efb53b73166081a98cea13Manman RenoptimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, unsigned SrcReg2, 2023de7266c611b37ec050efb53b73166081a98cea13Manman Ren int CmpMask, int CmpValue, 2024de7266c611b37ec050efb53b73166081a98cea13Manman Ren const MachineRegisterInfo *MRI) const { 202576c6ccbd4cee0637c961e32435177ab89e931fedManman Ren // Get the unique definition of SrcReg. 202676c6ccbd4cee0637c961e32435177ab89e931fedManman Ren MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg); 202776c6ccbd4cee0637c961e32435177ab89e931fedManman Ren if (!MI) return false; 202892ad57f066e9f256e4e3d72febf152e68caa80c7Bill Wendling 202904ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif // Masked compares sometimes use the same register as the corresponding 'and'. 203004ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif if (CmpMask != ~0) { 2031519daf5d2dd80614ac4e529b199e6f3e595bfc80Jakob Stoklund Olesen if (!isSuitableForMask(MI, SrcReg, CmpMask, false) || isPredicated(MI)) { 203204ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif MI = 0; 2033b41ee96d76ccf1eec2fd898def4cfd7c16868708Bill Wendling for (MachineRegisterInfo::use_iterator UI = MRI->use_begin(SrcReg), 2034b41ee96d76ccf1eec2fd898def4cfd7c16868708Bill Wendling UE = MRI->use_end(); UI != UE; ++UI) { 203504ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif if (UI->getParent() != CmpInstr->getParent()) continue; 203605642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif MachineInstr *PotentialAND = &*UI; 2037519daf5d2dd80614ac4e529b199e6f3e595bfc80Jakob Stoklund Olesen if (!isSuitableForMask(PotentialAND, SrcReg, CmpMask, true) || 2038519daf5d2dd80614ac4e529b199e6f3e595bfc80Jakob Stoklund Olesen isPredicated(PotentialAND)) 203904ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif continue; 204005642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif MI = PotentialAND; 204104ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif break; 204204ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif } 204304ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif if (!MI) return false; 204404ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif } 204504ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif } 204604ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif 2047247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren // Get ready to iterate backward from CmpInstr. 2048247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren MachineBasicBlock::iterator I = CmpInstr, E = MI, 2049247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren B = CmpInstr->getParent()->begin(); 20500aa38b9381a5be42abd4f5ca5baa8c2930d148d3Bill Wendling 20510aa38b9381a5be42abd4f5ca5baa8c2930d148d3Bill Wendling // Early exit if CmpInstr is at the beginning of the BB. 20520aa38b9381a5be42abd4f5ca5baa8c2930d148d3Bill Wendling if (I == B) return false; 20530aa38b9381a5be42abd4f5ca5baa8c2930d148d3Bill Wendling 2054247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren // There are two possible candidates which can be changed to set CPSR: 2055247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren // One is MI, the other is a SUB instruction. 2056247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren // For CMPrr(r1,r2), we are looking for SUB(r1,r2) or SUB(r2,r1). 2057247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren // For CMPri(r1, CmpValue), we are looking for SUBri(r1, CmpValue). 2058247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren MachineInstr *Sub = NULL; 2059de7266c611b37ec050efb53b73166081a98cea13Manman Ren if (SrcReg2 != 0) 2060247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren // MI is not a candidate for CMPrr. 2061247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren MI = NULL; 2062de7266c611b37ec050efb53b73166081a98cea13Manman Ren else if (MI->getParent() != CmpInstr->getParent() || CmpValue != 0) { 2063247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren // Conservatively refuse to convert an instruction which isn't in the same 2064247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren // BB as the comparison. 2065247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren // For CMPri, we need to check Sub, thus we can't return here. 20664949e98cccb98abb0ba3f67c22be757d446ab108Manman Ren if (CmpInstr->getOpcode() == ARM::CMPri || 2067247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren CmpInstr->getOpcode() == ARM::t2CMPri) 2068247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren MI = NULL; 2069247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren else 2070247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren return false; 2071247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren } 2072247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren 2073247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren // Check that CPSR isn't set between the comparison instruction and the one we 2074247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren // want to change. At the same time, search for Sub. 207576c6ccbd4cee0637c961e32435177ab89e931fedManman Ren const TargetRegisterInfo *TRI = &getRegisterInfo(); 2076e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling --I; 2077e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling for (; I != E; --I) { 2078e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling const MachineInstr &Instr = *I; 2079e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling 208076c6ccbd4cee0637c961e32435177ab89e931fedManman Ren if (Instr.modifiesRegister(ARM::CPSR, TRI) || 208176c6ccbd4cee0637c961e32435177ab89e931fedManman Ren Instr.readsRegister(ARM::CPSR, TRI)) 208240a5eb18b031fa1a5e9697e21e251e613d441cc5Bill Wendling // This instruction modifies or uses CPSR after the one we want to 208340a5eb18b031fa1a5e9697e21e251e613d441cc5Bill Wendling // change. We can't do this transformation. 208476c6ccbd4cee0637c961e32435177ab89e931fedManman Ren return false; 2085247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren 208676c6ccbd4cee0637c961e32435177ab89e931fedManman Ren // Check whether CmpInstr can be made redundant by the current instruction. 208776c6ccbd4cee0637c961e32435177ab89e931fedManman Ren if (isRedundantFlagInstr(CmpInstr, SrcReg, SrcReg2, CmpValue, &*I)) { 2088247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren Sub = &*I; 2089247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren break; 2090247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren } 2091247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren 2092691e64a54ce899409abe7c131d15ed75e3c1fef5Evan Cheng if (I == B) 2093691e64a54ce899409abe7c131d15ed75e3c1fef5Evan Cheng // The 'and' is below the comparison instruction. 2094691e64a54ce899409abe7c131d15ed75e3c1fef5Evan Cheng return false; 2095e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling } 2096e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling 2097247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren // Return false if no candidates exist. 2098247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren if (!MI && !Sub) 2099247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren return false; 2100247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren 2101247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren // The single candidate is called MI. 2102247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren if (!MI) MI = Sub; 2103247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren 2104519daf5d2dd80614ac4e529b199e6f3e595bfc80Jakob Stoklund Olesen // We can't use a predicated instruction - it doesn't always write the flags. 2105519daf5d2dd80614ac4e529b199e6f3e595bfc80Jakob Stoklund Olesen if (isPredicated(MI)) 2106519daf5d2dd80614ac4e529b199e6f3e595bfc80Jakob Stoklund Olesen return false; 2107519daf5d2dd80614ac4e529b199e6f3e595bfc80Jakob Stoklund Olesen 2108e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling switch (MI->getOpcode()) { 2109e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling default: break; 2110ca3f6a3925e9a6e91022aa211bdc1b6e3f2ff41fCameron Zwarich case ARM::RSBrr: 2111df298c9ea64eb335f63fc075d8ef6306682ffe75Owen Anderson case ARM::RSBri: 2112ca3f6a3925e9a6e91022aa211bdc1b6e3f2ff41fCameron Zwarich case ARM::RSCrr: 2113df298c9ea64eb335f63fc075d8ef6306682ffe75Owen Anderson case ARM::RSCri: 2114ca3f6a3925e9a6e91022aa211bdc1b6e3f2ff41fCameron Zwarich case ARM::ADDrr: 211538ae997e63e3e1bb2c8679e01ea74cf8fd0be893Bill Wendling case ARM::ADDri: 2116ca3f6a3925e9a6e91022aa211bdc1b6e3f2ff41fCameron Zwarich case ARM::ADCrr: 2117df298c9ea64eb335f63fc075d8ef6306682ffe75Owen Anderson case ARM::ADCri: 2118ca3f6a3925e9a6e91022aa211bdc1b6e3f2ff41fCameron Zwarich case ARM::SUBrr: 211938ae997e63e3e1bb2c8679e01ea74cf8fd0be893Bill Wendling case ARM::SUBri: 2120ca3f6a3925e9a6e91022aa211bdc1b6e3f2ff41fCameron Zwarich case ARM::SBCrr: 2121df298c9ea64eb335f63fc075d8ef6306682ffe75Owen Anderson case ARM::SBCri: 2122df298c9ea64eb335f63fc075d8ef6306682ffe75Owen Anderson case ARM::t2RSBri: 2123ca3f6a3925e9a6e91022aa211bdc1b6e3f2ff41fCameron Zwarich case ARM::t2ADDrr: 212438ae997e63e3e1bb2c8679e01ea74cf8fd0be893Bill Wendling case ARM::t2ADDri: 2125ca3f6a3925e9a6e91022aa211bdc1b6e3f2ff41fCameron Zwarich case ARM::t2ADCrr: 2126df298c9ea64eb335f63fc075d8ef6306682ffe75Owen Anderson case ARM::t2ADCri: 2127ca3f6a3925e9a6e91022aa211bdc1b6e3f2ff41fCameron Zwarich case ARM::t2SUBrr: 2128df298c9ea64eb335f63fc075d8ef6306682ffe75Owen Anderson case ARM::t2SUBri: 2129ca3f6a3925e9a6e91022aa211bdc1b6e3f2ff41fCameron Zwarich case ARM::t2SBCrr: 2130b485de5d8c3fe0c62c0b07f63f64bd10f6803c17Cameron Zwarich case ARM::t2SBCri: 2131b485de5d8c3fe0c62c0b07f63f64bd10f6803c17Cameron Zwarich case ARM::ANDrr: 2132b485de5d8c3fe0c62c0b07f63f64bd10f6803c17Cameron Zwarich case ARM::ANDri: 2133b485de5d8c3fe0c62c0b07f63f64bd10f6803c17Cameron Zwarich case ARM::t2ANDrr: 21340cb11ac32fc09c5db42fb801db242ac9fb51f6b1Cameron Zwarich case ARM::t2ANDri: 21350cb11ac32fc09c5db42fb801db242ac9fb51f6b1Cameron Zwarich case ARM::ORRrr: 21360cb11ac32fc09c5db42fb801db242ac9fb51f6b1Cameron Zwarich case ARM::ORRri: 21370cb11ac32fc09c5db42fb801db242ac9fb51f6b1Cameron Zwarich case ARM::t2ORRrr: 21380cb11ac32fc09c5db42fb801db242ac9fb51f6b1Cameron Zwarich case ARM::t2ORRri: 21390cb11ac32fc09c5db42fb801db242ac9fb51f6b1Cameron Zwarich case ARM::EORrr: 21400cb11ac32fc09c5db42fb801db242ac9fb51f6b1Cameron Zwarich case ARM::EORri: 21410cb11ac32fc09c5db42fb801db242ac9fb51f6b1Cameron Zwarich case ARM::t2EORrr: 21420cb11ac32fc09c5db42fb801db242ac9fb51f6b1Cameron Zwarich case ARM::t2EORri: { 2143247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren // Scan forward for the use of CPSR 2144247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren // When checking against MI: if it's a conditional code requires 214545ed19499b8f7025d9acf91cc37fbf6ea63abc4fManman Ren // checking of V bit, then this is not safe to do. 214645ed19499b8f7025d9acf91cc37fbf6ea63abc4fManman Ren // It is safe to remove CmpInstr if CPSR is redefined or killed. 214745ed19499b8f7025d9acf91cc37fbf6ea63abc4fManman Ren // If we are done with the basic block, we need to check whether CPSR is 214845ed19499b8f7025d9acf91cc37fbf6ea63abc4fManman Ren // live-out. 214976c6ccbd4cee0637c961e32435177ab89e931fedManman Ren SmallVector<std::pair<MachineOperand*, ARMCC::CondCodes>, 4> 215076c6ccbd4cee0637c961e32435177ab89e931fedManman Ren OperandsToUpdate; 21512c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng bool isSafe = false; 21522c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng I = CmpInstr; 2153247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren E = CmpInstr->getParent()->end(); 21542c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng while (!isSafe && ++I != E) { 21552c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng const MachineInstr &Instr = *I; 21562c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng for (unsigned IO = 0, EO = Instr.getNumOperands(); 21572c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng !isSafe && IO != EO; ++IO) { 21582c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng const MachineOperand &MO = Instr.getOperand(IO); 21592420b558de5d291d8503c1339004e5b5bf99a48aJakob Stoklund Olesen if (MO.isRegMask() && MO.clobbersPhysReg(ARM::CPSR)) { 21602420b558de5d291d8503c1339004e5b5bf99a48aJakob Stoklund Olesen isSafe = true; 21612420b558de5d291d8503c1339004e5b5bf99a48aJakob Stoklund Olesen break; 21622420b558de5d291d8503c1339004e5b5bf99a48aJakob Stoklund Olesen } 21632c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng if (!MO.isReg() || MO.getReg() != ARM::CPSR) 21642c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng continue; 21652c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng if (MO.isDef()) { 21662c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng isSafe = true; 21672c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng break; 21682c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng } 21692c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng // Condition code is after the operand before CPSR. 21702c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng ARMCC::CondCodes CC = (ARMCC::CondCodes)Instr.getOperand(IO-1).getImm(); 217176c6ccbd4cee0637c961e32435177ab89e931fedManman Ren if (Sub) { 217276c6ccbd4cee0637c961e32435177ab89e931fedManman Ren ARMCC::CondCodes NewCC = getSwappedCondition(CC); 217376c6ccbd4cee0637c961e32435177ab89e931fedManman Ren if (NewCC == ARMCC::AL) 2174247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren return false; 217576c6ccbd4cee0637c961e32435177ab89e931fedManman Ren // If we have SUB(r1, r2) and CMP(r2, r1), the condition code based 217676c6ccbd4cee0637c961e32435177ab89e931fedManman Ren // on CMP needs to be updated to be based on SUB. 217776c6ccbd4cee0637c961e32435177ab89e931fedManman Ren // Push the condition code operands to OperandsToUpdate. 217876c6ccbd4cee0637c961e32435177ab89e931fedManman Ren // If it is safe to remove CmpInstr, the condition code of these 217976c6ccbd4cee0637c961e32435177ab89e931fedManman Ren // operands will be modified. 218076c6ccbd4cee0637c961e32435177ab89e931fedManman Ren if (SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 && 218176c6ccbd4cee0637c961e32435177ab89e931fedManman Ren Sub->getOperand(2).getReg() == SrcReg) 218276c6ccbd4cee0637c961e32435177ab89e931fedManman Ren OperandsToUpdate.push_back(std::make_pair(&((*I).getOperand(IO-1)), 218376c6ccbd4cee0637c961e32435177ab89e931fedManman Ren NewCC)); 218476c6ccbd4cee0637c961e32435177ab89e931fedManman Ren } 2185247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren else 2186247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren switch (CC) { 2187247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren default: 21889af64303fa887a3d9b75e715787ba587c3f18139Manman Ren // CPSR can be used multiple times, we should continue. 2189247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren break; 2190247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren case ARMCC::VS: 2191247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren case ARMCC::VC: 2192247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren case ARMCC::GE: 2193247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren case ARMCC::LT: 2194247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren case ARMCC::GT: 2195247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren case ARMCC::LE: 2196247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren return false; 2197247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren } 21982c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng } 21992c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng } 22002c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng 220145ed19499b8f7025d9acf91cc37fbf6ea63abc4fManman Ren // If CPSR is not killed nor re-defined, we should check whether it is 220245ed19499b8f7025d9acf91cc37fbf6ea63abc4fManman Ren // live-out. If it is live-out, do not optimize. 220345ed19499b8f7025d9acf91cc37fbf6ea63abc4fManman Ren if (!isSafe) { 220445ed19499b8f7025d9acf91cc37fbf6ea63abc4fManman Ren MachineBasicBlock *MBB = CmpInstr->getParent(); 220545ed19499b8f7025d9acf91cc37fbf6ea63abc4fManman Ren for (MachineBasicBlock::succ_iterator SI = MBB->succ_begin(), 220645ed19499b8f7025d9acf91cc37fbf6ea63abc4fManman Ren SE = MBB->succ_end(); SI != SE; ++SI) 220745ed19499b8f7025d9acf91cc37fbf6ea63abc4fManman Ren if ((*SI)->isLiveIn(ARM::CPSR)) 220845ed19499b8f7025d9acf91cc37fbf6ea63abc4fManman Ren return false; 220945ed19499b8f7025d9acf91cc37fbf6ea63abc4fManman Ren } 22102c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng 22113642e64c114e636548888c72c21ae023ee0121a7Evan Cheng // Toggle the optional operand to CPSR. 22123642e64c114e636548888c72c21ae023ee0121a7Evan Cheng MI->getOperand(5).setReg(ARM::CPSR); 22133642e64c114e636548888c72c21ae023ee0121a7Evan Cheng MI->getOperand(5).setIsDef(true); 2214519daf5d2dd80614ac4e529b199e6f3e595bfc80Jakob Stoklund Olesen assert(!isPredicated(MI) && "Can't use flags from predicated instruction"); 2215e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling CmpInstr->eraseFromParent(); 2216247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren 2217247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren // Modify the condition code of operands in OperandsToUpdate. 2218247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren // Since we have SUB(r1, r2) and CMP(r2, r1), the condition code needs to 2219247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren // be changed from r2 > r1 to r1 < r2, from r2 < r1 to r1 > r2, etc. 222076c6ccbd4cee0637c961e32435177ab89e931fedManman Ren for (unsigned i = 0, e = OperandsToUpdate.size(); i < e; i++) 222176c6ccbd4cee0637c961e32435177ab89e931fedManman Ren OperandsToUpdate[i].first->setImm(OperandsToUpdate[i].second); 2222e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling return true; 2223e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling } 2224b485de5d8c3fe0c62c0b07f63f64bd10f6803c17Cameron Zwarich } 2225e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling 2226e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling return false; 2227e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling} 22285f54ce347368105260be2cec497b6a4199dc5789Evan Cheng 2229c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Chengbool ARMBaseInstrInfo::FoldImmediate(MachineInstr *UseMI, 2230c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng MachineInstr *DefMI, unsigned Reg, 2231c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng MachineRegisterInfo *MRI) const { 2232c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng // Fold large immediates into add, sub, or, xor. 2233c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng unsigned DefOpc = DefMI->getOpcode(); 2234c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng if (DefOpc != ARM::t2MOVi32imm && DefOpc != ARM::MOVi32imm) 2235c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng return false; 2236c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng if (!DefMI->getOperand(1).isImm()) 2237c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng // Could be t2MOVi32imm <ga:xx> 2238c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng return false; 2239c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng 2240c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng if (!MRI->hasOneNonDBGUse(Reg)) 2241c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng return false; 2242c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng 2243e279f5953e9c3d934248cd4d2f24b6179ad9d2e6Evan Cheng const MCInstrDesc &DefMCID = DefMI->getDesc(); 2244e279f5953e9c3d934248cd4d2f24b6179ad9d2e6Evan Cheng if (DefMCID.hasOptionalDef()) { 2245e279f5953e9c3d934248cd4d2f24b6179ad9d2e6Evan Cheng unsigned NumOps = DefMCID.getNumOperands(); 2246e279f5953e9c3d934248cd4d2f24b6179ad9d2e6Evan Cheng const MachineOperand &MO = DefMI->getOperand(NumOps-1); 2247e279f5953e9c3d934248cd4d2f24b6179ad9d2e6Evan Cheng if (MO.getReg() == ARM::CPSR && !MO.isDead()) 2248e279f5953e9c3d934248cd4d2f24b6179ad9d2e6Evan Cheng // If DefMI defines CPSR and it is not dead, it's obviously not safe 2249e279f5953e9c3d934248cd4d2f24b6179ad9d2e6Evan Cheng // to delete DefMI. 2250e279f5953e9c3d934248cd4d2f24b6179ad9d2e6Evan Cheng return false; 2251e279f5953e9c3d934248cd4d2f24b6179ad9d2e6Evan Cheng } 2252e279f5953e9c3d934248cd4d2f24b6179ad9d2e6Evan Cheng 2253e279f5953e9c3d934248cd4d2f24b6179ad9d2e6Evan Cheng const MCInstrDesc &UseMCID = UseMI->getDesc(); 2254e279f5953e9c3d934248cd4d2f24b6179ad9d2e6Evan Cheng if (UseMCID.hasOptionalDef()) { 2255e279f5953e9c3d934248cd4d2f24b6179ad9d2e6Evan Cheng unsigned NumOps = UseMCID.getNumOperands(); 2256e279f5953e9c3d934248cd4d2f24b6179ad9d2e6Evan Cheng if (UseMI->getOperand(NumOps-1).getReg() == ARM::CPSR) 2257e279f5953e9c3d934248cd4d2f24b6179ad9d2e6Evan Cheng // If the instruction sets the flag, do not attempt this optimization 2258e279f5953e9c3d934248cd4d2f24b6179ad9d2e6Evan Cheng // since it may change the semantics of the code. 2259e279f5953e9c3d934248cd4d2f24b6179ad9d2e6Evan Cheng return false; 2260e279f5953e9c3d934248cd4d2f24b6179ad9d2e6Evan Cheng } 2261e279f5953e9c3d934248cd4d2f24b6179ad9d2e6Evan Cheng 2262c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng unsigned UseOpc = UseMI->getOpcode(); 22635c71c7a13715ed6f5bfdd5497172ddec316b68b0Evan Cheng unsigned NewUseOpc = 0; 2264c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng uint32_t ImmVal = (uint32_t)DefMI->getOperand(1).getImm(); 22655c71c7a13715ed6f5bfdd5497172ddec316b68b0Evan Cheng uint32_t SOImmValV1 = 0, SOImmValV2 = 0; 2266c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng bool Commute = false; 2267c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng switch (UseOpc) { 2268c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng default: return false; 2269c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::SUBrr: 2270c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::ADDrr: 2271c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::ORRrr: 2272c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::EORrr: 2273c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::t2SUBrr: 2274c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::t2ADDrr: 2275c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::t2ORRrr: 2276c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::t2EORrr: { 2277c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng Commute = UseMI->getOperand(2).getReg() != Reg; 2278c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng switch (UseOpc) { 2279c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng default: break; 2280c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::SUBrr: { 2281c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng if (Commute) 2282c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng return false; 2283c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng ImmVal = -ImmVal; 2284c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng NewUseOpc = ARM::SUBri; 2285c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng // Fallthrough 2286c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng } 2287c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::ADDrr: 2288c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::ORRrr: 2289c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::EORrr: { 2290c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng if (!ARM_AM::isSOImmTwoPartVal(ImmVal)) 2291c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng return false; 2292c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng SOImmValV1 = (uint32_t)ARM_AM::getSOImmTwoPartFirst(ImmVal); 2293c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng SOImmValV2 = (uint32_t)ARM_AM::getSOImmTwoPartSecond(ImmVal); 2294c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng switch (UseOpc) { 2295c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng default: break; 2296c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::ADDrr: NewUseOpc = ARM::ADDri; break; 2297c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::ORRrr: NewUseOpc = ARM::ORRri; break; 2298c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::EORrr: NewUseOpc = ARM::EORri; break; 2299c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng } 2300c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng break; 2301c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng } 2302c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::t2SUBrr: { 2303c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng if (Commute) 2304c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng return false; 2305c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng ImmVal = -ImmVal; 2306c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng NewUseOpc = ARM::t2SUBri; 2307c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng // Fallthrough 2308c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng } 2309c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::t2ADDrr: 2310c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::t2ORRrr: 2311c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::t2EORrr: { 2312c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng if (!ARM_AM::isT2SOImmTwoPartVal(ImmVal)) 2313c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng return false; 2314c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng SOImmValV1 = (uint32_t)ARM_AM::getT2SOImmTwoPartFirst(ImmVal); 2315c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng SOImmValV2 = (uint32_t)ARM_AM::getT2SOImmTwoPartSecond(ImmVal); 2316c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng switch (UseOpc) { 2317c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng default: break; 2318c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::t2ADDrr: NewUseOpc = ARM::t2ADDri; break; 2319c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::t2ORRrr: NewUseOpc = ARM::t2ORRri; break; 2320c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::t2EORrr: NewUseOpc = ARM::t2EORri; break; 2321c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng } 2322c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng break; 2323c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng } 2324c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng } 2325c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng } 2326c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng } 2327c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng 2328c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng unsigned OpIdx = Commute ? 2 : 1; 2329c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng unsigned Reg1 = UseMI->getOperand(OpIdx).getReg(); 2330c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng bool isKill = UseMI->getOperand(OpIdx).isKill(); 2331c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng unsigned NewReg = MRI->createVirtualRegister(MRI->getRegClass(Reg)); 2332c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng AddDefaultCC(AddDefaultPred(BuildMI(*UseMI->getParent(), 2333ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng UseMI, UseMI->getDebugLoc(), 2334c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng get(NewUseOpc), NewReg) 2335c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng .addReg(Reg1, getKillRegState(isKill)) 2336c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng .addImm(SOImmValV1))); 2337c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng UseMI->setDesc(get(NewUseOpc)); 2338c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng UseMI->getOperand(1).setReg(NewReg); 2339c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng UseMI->getOperand(1).setIsKill(); 2340c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng UseMI->getOperand(2).ChangeToImmediate(SOImmValV2); 2341c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng DefMI->eraseFromParent(); 2342c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng return true; 2343c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng} 2344c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng 23459eed53379f19f836769a0c4a14042eeb1b587769Andrew Trick// Return the number of 32-bit words loaded by LDM or stored by STM. If this 23469eed53379f19f836769a0c4a14042eeb1b587769Andrew Trick// can't be easily determined return 0 (missing MachineMemOperand). 23479eed53379f19f836769a0c4a14042eeb1b587769Andrew Trick// 23489eed53379f19f836769a0c4a14042eeb1b587769Andrew Trick// FIXME: The current MachineInstr design does not support relying on machine 23499eed53379f19f836769a0c4a14042eeb1b587769Andrew Trick// mem operands to determine the width of a memory access. Instead, we expect 23509eed53379f19f836769a0c4a14042eeb1b587769Andrew Trick// the target to provide this information based on the instruction opcode and 23519eed53379f19f836769a0c4a14042eeb1b587769Andrew Trick// operands. However, using MachineMemOperand is a the best solution now for 23529eed53379f19f836769a0c4a14042eeb1b587769Andrew Trick// two reasons: 23539eed53379f19f836769a0c4a14042eeb1b587769Andrew Trick// 23549eed53379f19f836769a0c4a14042eeb1b587769Andrew Trick// 1) getNumMicroOps tries to infer LDM memory width from the total number of MI 23559eed53379f19f836769a0c4a14042eeb1b587769Andrew Trick// operands. This is much more dangerous than using the MachineMemOperand 23569eed53379f19f836769a0c4a14042eeb1b587769Andrew Trick// sizes because CodeGen passes can insert/remove optional machine operands. In 23579eed53379f19f836769a0c4a14042eeb1b587769Andrew Trick// fact, it's totally incorrect for preRA passes and appears to be wrong for 23589eed53379f19f836769a0c4a14042eeb1b587769Andrew Trick// postRA passes as well. 23599eed53379f19f836769a0c4a14042eeb1b587769Andrew Trick// 23609eed53379f19f836769a0c4a14042eeb1b587769Andrew Trick// 2) getNumLDMAddresses is only used by the scheduling machine model and any 23619eed53379f19f836769a0c4a14042eeb1b587769Andrew Trick// machine model that calls this should handle the unknown (zero size) case. 23629eed53379f19f836769a0c4a14042eeb1b587769Andrew Trick// 23639eed53379f19f836769a0c4a14042eeb1b587769Andrew Trick// Long term, we should require a target hook that verifies MachineMemOperand 23649eed53379f19f836769a0c4a14042eeb1b587769Andrew Trick// sizes during MC lowering. That target hook should be local to MC lowering 23659eed53379f19f836769a0c4a14042eeb1b587769Andrew Trick// because we can't ensure that it is aware of other MI forms. Doing this will 23669eed53379f19f836769a0c4a14042eeb1b587769Andrew Trick// ensure that MachineMemOperands are correctly propagated through all passes. 23679eed53379f19f836769a0c4a14042eeb1b587769Andrew Trickunsigned ARMBaseInstrInfo::getNumLDMAddresses(const MachineInstr *MI) const { 23689eed53379f19f836769a0c4a14042eeb1b587769Andrew Trick unsigned Size = 0; 23699eed53379f19f836769a0c4a14042eeb1b587769Andrew Trick for (MachineInstr::mmo_iterator I = MI->memoperands_begin(), 23709eed53379f19f836769a0c4a14042eeb1b587769Andrew Trick E = MI->memoperands_end(); I != E; ++I) { 23719eed53379f19f836769a0c4a14042eeb1b587769Andrew Trick Size += (*I)->getSize(); 23729eed53379f19f836769a0c4a14042eeb1b587769Andrew Trick } 23739eed53379f19f836769a0c4a14042eeb1b587769Andrew Trick return Size / 4; 23749eed53379f19f836769a0c4a14042eeb1b587769Andrew Trick} 23759eed53379f19f836769a0c4a14042eeb1b587769Andrew Trick 23765f54ce347368105260be2cec497b6a4199dc5789Evan Chengunsigned 23778239daf7c83a65a189c352cce3191cdc3bbfe151Evan ChengARMBaseInstrInfo::getNumMicroOps(const InstrItineraryData *ItinData, 23788239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng const MachineInstr *MI) const { 23793ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng if (!ItinData || ItinData->isEmpty()) 23805f54ce347368105260be2cec497b6a4199dc5789Evan Cheng return 1; 23815f54ce347368105260be2cec497b6a4199dc5789Evan Cheng 2382e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng const MCInstrDesc &Desc = MI->getDesc(); 23835f54ce347368105260be2cec497b6a4199dc5789Evan Cheng unsigned Class = Desc.getSchedClass(); 2384218ee74a011c0d350099c452810da0bd57a15047Andrew Trick int ItinUOps = ItinData->getNumMicroOps(Class); 2385218ee74a011c0d350099c452810da0bd57a15047Andrew Trick if (ItinUOps >= 0) 2386218ee74a011c0d350099c452810da0bd57a15047Andrew Trick return ItinUOps; 23875f54ce347368105260be2cec497b6a4199dc5789Evan Cheng 23885f54ce347368105260be2cec497b6a4199dc5789Evan Cheng unsigned Opc = MI->getOpcode(); 23895f54ce347368105260be2cec497b6a4199dc5789Evan Cheng switch (Opc) { 23905f54ce347368105260be2cec497b6a4199dc5789Evan Cheng default: 23915f54ce347368105260be2cec497b6a4199dc5789Evan Cheng llvm_unreachable("Unexpected multi-uops instruction!"); 239273fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMQIA: 239373fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMQIA: 23945f54ce347368105260be2cec497b6a4199dc5789Evan Cheng return 2; 23955f54ce347368105260be2cec497b6a4199dc5789Evan Cheng 23965f54ce347368105260be2cec497b6a4199dc5789Evan Cheng // The number of uOps for load / store multiple are determined by the number 23975f54ce347368105260be2cec497b6a4199dc5789Evan Cheng // registers. 23986e8f4c404825b79f9b9176483653f1aa927dfbdeAndrew Trick // 23993ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng // On Cortex-A8, each pair of register loads / stores can be scheduled on the 24003ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng // same cycle. The scheduling for the first load / store must be done 2401c8e41c591741b3da1077f7000274ad040bef8002Sylvestre Ledru // separately by assuming the address is not 64-bit aligned. 240273fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling // 24033ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng // On Cortex-A9, the formula is simply (#reg / 2) + (#reg % 2). If the address 240473fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling // is not 64-bit aligned, then AGU would take an extra cycle. For VFP / NEON 240573fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling // load / store multiple, the formula is (#reg / 2) + (#reg % 2) + 1. 240673fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMDIA: 240773fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMDIA_UPD: 240873fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMDDB_UPD: 240973fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMSIA: 241073fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMSIA_UPD: 241173fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMSDB_UPD: 241273fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMDIA: 241373fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMDIA_UPD: 241473fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMDDB_UPD: 241573fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMSIA: 241673fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMSIA_UPD: 241773fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMSDB_UPD: { 24185f54ce347368105260be2cec497b6a4199dc5789Evan Cheng unsigned NumRegs = MI->getNumOperands() - Desc.getNumOperands(); 24195f54ce347368105260be2cec497b6a4199dc5789Evan Cheng return (NumRegs / 2) + (NumRegs % 2) + 1; 24205f54ce347368105260be2cec497b6a4199dc5789Evan Cheng } 242173fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling 242273fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMIA_RET: 242373fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMIA: 242473fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMDA: 242573fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMDB: 242673fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMIB: 242773fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMIA_UPD: 242873fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMDA_UPD: 242973fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMDB_UPD: 243073fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMIB_UPD: 243173fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::STMIA: 243273fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::STMDA: 243373fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::STMDB: 243473fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::STMIB: 243573fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::STMIA_UPD: 243673fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::STMDA_UPD: 243773fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::STMDB_UPD: 243873fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::STMIB_UPD: 243973fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::tLDMIA: 244073fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::tLDMIA_UPD: 244173fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::tSTMIA_UPD: 24425f54ce347368105260be2cec497b6a4199dc5789Evan Cheng case ARM::tPOP_RET: 24435f54ce347368105260be2cec497b6a4199dc5789Evan Cheng case ARM::tPOP: 24445f54ce347368105260be2cec497b6a4199dc5789Evan Cheng case ARM::tPUSH: 244573fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2LDMIA_RET: 244673fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2LDMIA: 244773fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2LDMDB: 244873fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2LDMIA_UPD: 244973fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2LDMDB_UPD: 245073fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2STMIA: 245173fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2STMDB: 245273fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2STMIA_UPD: 245373fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2STMDB_UPD: { 24543ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng unsigned NumRegs = MI->getNumOperands() - Desc.getNumOperands() + 1; 24553ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng if (Subtarget.isCortexA8()) { 24568239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng if (NumRegs < 4) 24578239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng return 2; 24588239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng // 4 registers would be issued: 2, 2. 24598239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng // 5 registers would be issued: 2, 2, 1. 2460218ee74a011c0d350099c452810da0bd57a15047Andrew Trick int A8UOps = (NumRegs / 2); 24618239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng if (NumRegs % 2) 2462218ee74a011c0d350099c452810da0bd57a15047Andrew Trick ++A8UOps; 2463218ee74a011c0d350099c452810da0bd57a15047Andrew Trick return A8UOps; 2464616471d4bfe4717fa86259ff4534703357b3b723Silviu Baranga } else if (Subtarget.isLikeA9()) { 2465218ee74a011c0d350099c452810da0bd57a15047Andrew Trick int A9UOps = (NumRegs / 2); 24663ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng // If there are odd number of registers or if it's not 64-bit aligned, 24673ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng // then it takes an extra AGU (Address Generation Unit) cycle. 24683ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng if ((NumRegs % 2) || 24693ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng !MI->hasOneMemOperand() || 24703ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng (*MI->memoperands_begin())->getAlignment() < 8) 2471218ee74a011c0d350099c452810da0bd57a15047Andrew Trick ++A9UOps; 2472218ee74a011c0d350099c452810da0bd57a15047Andrew Trick return A9UOps; 24733ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng } else { 24743ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng // Assume the worst. 24753ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng return NumRegs; 24762bbb76909126db5bed6bde84b16d94ab5de4d372Michael J. Spencer } 24775f54ce347368105260be2cec497b6a4199dc5789Evan Cheng } 24785f54ce347368105260be2cec497b6a4199dc5789Evan Cheng } 24795f54ce347368105260be2cec497b6a4199dc5789Evan Cheng} 2480a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng 2481a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Chengint 2482344d9db97062736cd66da6c07baa9108b6cfa419Evan ChengARMBaseInstrInfo::getVLDMDefCycle(const InstrItineraryData *ItinData, 2483e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng const MCInstrDesc &DefMCID, 2484344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng unsigned DefClass, 2485344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng unsigned DefIdx, unsigned DefAlign) const { 2486e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng int RegNo = (int)(DefIdx+1) - DefMCID.getNumOperands() + 1; 2487344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng if (RegNo <= 0) 2488344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // Def is the address writeback. 2489344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng return ItinData->getOperandCycle(DefClass, DefIdx); 2490344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng 2491344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng int DefCycle; 2492344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng if (Subtarget.isCortexA8()) { 2493344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // (regno / 2) + (regno % 2) + 1 2494344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng DefCycle = RegNo / 2 + 1; 2495344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng if (RegNo % 2) 2496344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng ++DefCycle; 2497616471d4bfe4717fa86259ff4534703357b3b723Silviu Baranga } else if (Subtarget.isLikeA9()) { 2498344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng DefCycle = RegNo; 2499344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng bool isSLoad = false; 250073fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling 2501e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng switch (DefMCID.getOpcode()) { 2502344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng default: break; 250373fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMSIA: 250473fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMSIA_UPD: 250573fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMSDB_UPD: 2506344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng isSLoad = true; 2507344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng break; 2508344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng } 250973fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling 2510344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // If there are odd number of 'S' registers or if it's not 64-bit aligned, 2511344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // then it takes an extra cycle. 2512344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng if ((isSLoad && (RegNo % 2)) || DefAlign < 8) 2513344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng ++DefCycle; 2514344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng } else { 2515344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // Assume the worst. 2516344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng DefCycle = RegNo + 2; 2517344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng } 2518344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng 2519344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng return DefCycle; 2520344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng} 2521344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng 2522344d9db97062736cd66da6c07baa9108b6cfa419Evan Chengint 2523344d9db97062736cd66da6c07baa9108b6cfa419Evan ChengARMBaseInstrInfo::getLDMDefCycle(const InstrItineraryData *ItinData, 2524e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng const MCInstrDesc &DefMCID, 2525344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng unsigned DefClass, 2526344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng unsigned DefIdx, unsigned DefAlign) const { 2527e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng int RegNo = (int)(DefIdx+1) - DefMCID.getNumOperands() + 1; 2528344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng if (RegNo <= 0) 2529344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // Def is the address writeback. 2530344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng return ItinData->getOperandCycle(DefClass, DefIdx); 2531344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng 2532344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng int DefCycle; 2533344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng if (Subtarget.isCortexA8()) { 2534344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // 4 registers would be issued: 1, 2, 1. 2535344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // 5 registers would be issued: 1, 2, 2. 2536344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng DefCycle = RegNo / 2; 2537344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng if (DefCycle < 1) 2538344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng DefCycle = 1; 2539344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // Result latency is issue cycle + 2: E2. 2540344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng DefCycle += 2; 2541616471d4bfe4717fa86259ff4534703357b3b723Silviu Baranga } else if (Subtarget.isLikeA9()) { 2542344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng DefCycle = (RegNo / 2); 2543344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // If there are odd number of registers or if it's not 64-bit aligned, 2544344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // then it takes an extra AGU (Address Generation Unit) cycle. 2545344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng if ((RegNo % 2) || DefAlign < 8) 2546344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng ++DefCycle; 2547344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // Result latency is AGU cycles + 2. 2548344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng DefCycle += 2; 2549344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng } else { 2550344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // Assume the worst. 2551344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng DefCycle = RegNo + 2; 2552344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng } 2553344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng 2554344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng return DefCycle; 2555344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng} 2556344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng 2557344d9db97062736cd66da6c07baa9108b6cfa419Evan Chengint 2558344d9db97062736cd66da6c07baa9108b6cfa419Evan ChengARMBaseInstrInfo::getVSTMUseCycle(const InstrItineraryData *ItinData, 2559e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng const MCInstrDesc &UseMCID, 2560344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng unsigned UseClass, 2561344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng unsigned UseIdx, unsigned UseAlign) const { 2562e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng int RegNo = (int)(UseIdx+1) - UseMCID.getNumOperands() + 1; 2563344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng if (RegNo <= 0) 2564344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng return ItinData->getOperandCycle(UseClass, UseIdx); 2565344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng 2566344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng int UseCycle; 2567344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng if (Subtarget.isCortexA8()) { 2568344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // (regno / 2) + (regno % 2) + 1 2569344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng UseCycle = RegNo / 2 + 1; 2570344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng if (RegNo % 2) 2571344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng ++UseCycle; 2572616471d4bfe4717fa86259ff4534703357b3b723Silviu Baranga } else if (Subtarget.isLikeA9()) { 2573344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng UseCycle = RegNo; 2574344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng bool isSStore = false; 257573fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling 2576e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng switch (UseMCID.getOpcode()) { 2577344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng default: break; 257873fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMSIA: 257973fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMSIA_UPD: 258073fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMSDB_UPD: 2581344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng isSStore = true; 2582344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng break; 2583344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng } 258473fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling 2585344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // If there are odd number of 'S' registers or if it's not 64-bit aligned, 2586344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // then it takes an extra cycle. 2587344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng if ((isSStore && (RegNo % 2)) || UseAlign < 8) 2588344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng ++UseCycle; 2589344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng } else { 2590344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // Assume the worst. 2591344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng UseCycle = RegNo + 2; 2592344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng } 2593344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng 2594344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng return UseCycle; 2595344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng} 2596344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng 2597344d9db97062736cd66da6c07baa9108b6cfa419Evan Chengint 2598344d9db97062736cd66da6c07baa9108b6cfa419Evan ChengARMBaseInstrInfo::getSTMUseCycle(const InstrItineraryData *ItinData, 2599e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng const MCInstrDesc &UseMCID, 2600344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng unsigned UseClass, 2601344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng unsigned UseIdx, unsigned UseAlign) const { 2602e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng int RegNo = (int)(UseIdx+1) - UseMCID.getNumOperands() + 1; 2603344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng if (RegNo <= 0) 2604344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng return ItinData->getOperandCycle(UseClass, UseIdx); 2605344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng 2606344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng int UseCycle; 2607344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng if (Subtarget.isCortexA8()) { 2608344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng UseCycle = RegNo / 2; 2609344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng if (UseCycle < 2) 2610344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng UseCycle = 2; 2611344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // Read in E3. 2612344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng UseCycle += 2; 2613616471d4bfe4717fa86259ff4534703357b3b723Silviu Baranga } else if (Subtarget.isLikeA9()) { 2614344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng UseCycle = (RegNo / 2); 2615344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // If there are odd number of registers or if it's not 64-bit aligned, 2616344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // then it takes an extra AGU (Address Generation Unit) cycle. 2617344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng if ((RegNo % 2) || UseAlign < 8) 2618344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng ++UseCycle; 2619344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng } else { 2620344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // Assume the worst. 2621344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng UseCycle = 1; 2622344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng } 2623344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng return UseCycle; 2624344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng} 2625344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng 2626344d9db97062736cd66da6c07baa9108b6cfa419Evan Chengint 2627a0792de66c8364d47b0a688c7f408efb7b10f31bEvan ChengARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData, 2628e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng const MCInstrDesc &DefMCID, 2629a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng unsigned DefIdx, unsigned DefAlign, 2630e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng const MCInstrDesc &UseMCID, 2631a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng unsigned UseIdx, unsigned UseAlign) const { 2632e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng unsigned DefClass = DefMCID.getSchedClass(); 2633e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng unsigned UseClass = UseMCID.getSchedClass(); 2634a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng 2635e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng if (DefIdx < DefMCID.getNumDefs() && UseIdx < UseMCID.getNumOperands()) 2636a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx); 2637a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng 2638a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng // This may be a def / use of a variable_ops instruction, the operand 2639a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng // latency might be determinable dynamically. Let the target try to 2640a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng // figure it out. 26419e08ee5d16b596078e20787f0b5f36121f099333Evan Cheng int DefCycle = -1; 26427e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng bool LdmBypass = false; 2643e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng switch (DefMCID.getOpcode()) { 2644a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng default: 2645a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng DefCycle = ItinData->getOperandCycle(DefClass, DefIdx); 2646a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng break; 264773fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling 264873fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMDIA: 264973fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMDIA_UPD: 265073fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMDDB_UPD: 265173fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMSIA: 265273fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMSIA_UPD: 265373fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMSDB_UPD: 2654e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng DefCycle = getVLDMDefCycle(ItinData, DefMCID, DefClass, DefIdx, DefAlign); 26555a50ceeaea980962c1982ad535226c7ab06c971cEvan Cheng break; 265673fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling 265773fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMIA_RET: 265873fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMIA: 265973fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMDA: 266073fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMDB: 266173fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMIB: 266273fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMIA_UPD: 266373fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMDA_UPD: 266473fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMDB_UPD: 266573fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMIB_UPD: 266673fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::tLDMIA: 266773fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::tLDMIA_UPD: 2668a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng case ARM::tPUSH: 266973fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2LDMIA_RET: 267073fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2LDMIA: 267173fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2LDMDB: 267273fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2LDMIA_UPD: 267373fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2LDMDB_UPD: 2674a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng LdmBypass = 1; 2675e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng DefCycle = getLDMDefCycle(ItinData, DefMCID, DefClass, DefIdx, DefAlign); 2676344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng break; 2677a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng } 2678a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng 2679a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng if (DefCycle == -1) 2680a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng // We can't seem to determine the result latency of the def, assume it's 2. 2681a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng DefCycle = 2; 2682a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng 2683a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng int UseCycle = -1; 2684e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng switch (UseMCID.getOpcode()) { 2685a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng default: 2686a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng UseCycle = ItinData->getOperandCycle(UseClass, UseIdx); 2687a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng break; 268873fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling 268973fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMDIA: 269073fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMDIA_UPD: 269173fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMDDB_UPD: 269273fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMSIA: 269373fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMSIA_UPD: 269473fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMSDB_UPD: 2695e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng UseCycle = getVSTMUseCycle(ItinData, UseMCID, UseClass, UseIdx, UseAlign); 26965a50ceeaea980962c1982ad535226c7ab06c971cEvan Cheng break; 269773fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling 269873fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::STMIA: 269973fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::STMDA: 270073fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::STMDB: 270173fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::STMIB: 270273fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::STMIA_UPD: 270373fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::STMDA_UPD: 270473fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::STMDB_UPD: 270573fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::STMIB_UPD: 270673fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::tSTMIA_UPD: 2707a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng case ARM::tPOP_RET: 2708a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng case ARM::tPOP: 270973fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2STMIA: 271073fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2STMDB: 271173fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2STMIA_UPD: 271273fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2STMDB_UPD: 2713e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng UseCycle = getSTMUseCycle(ItinData, UseMCID, UseClass, UseIdx, UseAlign); 27145a50ceeaea980962c1982ad535226c7ab06c971cEvan Cheng break; 2715a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng } 2716a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng 2717a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng if (UseCycle == -1) 2718a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng // Assume it's read in the first stage. 2719a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng UseCycle = 1; 2720a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng 2721a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng UseCycle = DefCycle - UseCycle + 1; 2722a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng if (UseCycle > 0) { 2723a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng if (LdmBypass) { 2724a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng // It's a variable_ops instruction so we can't use DefIdx here. Just use 2725a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng // first def operand. 2726e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng if (ItinData->hasPipelineForwarding(DefClass, DefMCID.getNumOperands()-1, 2727a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng UseClass, UseIdx)) 2728a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng --UseCycle; 2729a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng } else if (ItinData->hasPipelineForwarding(DefClass, DefIdx, 273073fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling UseClass, UseIdx)) { 2731a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng --UseCycle; 273273fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling } 2733a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng } 2734a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng 2735a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng return UseCycle; 2736a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng} 2737a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng 2738ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Chengstatic const MachineInstr *getBundledDefMI(const TargetRegisterInfo *TRI, 2739020f4106f820648fd7e91956859844a80de13974Evan Cheng const MachineInstr *MI, unsigned Reg, 2740ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng unsigned &DefIdx, unsigned &Dist) { 2741ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng Dist = 0; 2742ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng 2743ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng MachineBasicBlock::const_iterator I = MI; ++I; 2744ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng MachineBasicBlock::const_instr_iterator II = 2745ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng llvm::prior(I.getInstrIterator()); 2746ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng assert(II->isInsideBundle() && "Empty bundle?"); 2747ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng 2748ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng int Idx = -1; 2749ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng while (II->isInsideBundle()) { 2750ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng Idx = II->findRegisterDefOperandIdx(Reg, false, true, TRI); 2751ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng if (Idx != -1) 2752ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng break; 2753ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng --II; 2754ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng ++Dist; 2755ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng } 2756ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng 2757ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng assert(Idx != -1 && "Cannot find bundled definition!"); 2758ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng DefIdx = Idx; 2759ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng return II; 2760ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng} 2761ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng 2762ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Chengstatic const MachineInstr *getBundledUseMI(const TargetRegisterInfo *TRI, 2763020f4106f820648fd7e91956859844a80de13974Evan Cheng const MachineInstr *MI, unsigned Reg, 2764ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng unsigned &UseIdx, unsigned &Dist) { 2765ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng Dist = 0; 2766ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng 2767ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng MachineBasicBlock::const_instr_iterator II = MI; ++II; 2768ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng assert(II->isInsideBundle() && "Empty bundle?"); 2769ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end(); 2770ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng 2771ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng // FIXME: This doesn't properly handle multiple uses. 2772ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng int Idx = -1; 2773ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng while (II != E && II->isInsideBundle()) { 2774ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng Idx = II->findRegisterUseOperandIdx(Reg, false, TRI); 2775ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng if (Idx != -1) 2776ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng break; 2777ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng if (II->getOpcode() != ARM::t2IT) 2778ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng ++Dist; 2779ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng ++II; 2780ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng } 2781ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng 2782020f4106f820648fd7e91956859844a80de13974Evan Cheng if (Idx == -1) { 2783020f4106f820648fd7e91956859844a80de13974Evan Cheng Dist = 0; 2784020f4106f820648fd7e91956859844a80de13974Evan Cheng return 0; 2785020f4106f820648fd7e91956859844a80de13974Evan Cheng } 2786020f4106f820648fd7e91956859844a80de13974Evan Cheng 2787ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng UseIdx = Idx; 2788ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng return II; 2789ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng} 2790ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng 279168b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick/// Return the number of cycles to add to (or subtract from) the static 279268b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick/// itinerary based on the def opcode and alignment. The caller will ensure that 279368b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick/// adjusted latency is at least one cycle. 279468b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trickstatic int adjustDefLatency(const ARMSubtarget &Subtarget, 279568b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick const MachineInstr *DefMI, 279668b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick const MCInstrDesc *DefMCID, unsigned DefAlign) { 279768b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick int Adjust = 0; 2798616471d4bfe4717fa86259ff4534703357b3b723Silviu Baranga if (Subtarget.isCortexA8() || Subtarget.isLikeA9()) { 27997e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng // FIXME: Shifter op hack: no shift (i.e. [r +/- r]) or [r + r << 2] 28007e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng // variants are one cycle cheaper. 2801ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng switch (DefMCID->getOpcode()) { 28027e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng default: break; 2803cff9baa95273bc279bf5fadb9e27afbd25cca20bJakob Stoklund Olesen case ARM::LDRrs: 2804cff9baa95273bc279bf5fadb9e27afbd25cca20bJakob Stoklund Olesen case ARM::LDRBrs: { 28057e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng unsigned ShOpVal = DefMI->getOperand(3).getImm(); 28067e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal); 28077e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng if (ShImm == 0 || 28087e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng (ShImm == 2 && ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl)) 280968b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick --Adjust; 28107e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng break; 28117e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng } 2812cff9baa95273bc279bf5fadb9e27afbd25cca20bJakob Stoklund Olesen case ARM::t2LDRs: 2813cff9baa95273bc279bf5fadb9e27afbd25cca20bJakob Stoklund Olesen case ARM::t2LDRBs: 2814cff9baa95273bc279bf5fadb9e27afbd25cca20bJakob Stoklund Olesen case ARM::t2LDRHs: 28157e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng case ARM::t2LDRSHs: { 28167e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng // Thumb2 mode: lsl only. 28177e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng unsigned ShAmt = DefMI->getOperand(3).getImm(); 28187e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng if (ShAmt == 0 || ShAmt == 2) 281968b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick --Adjust; 28207e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng break; 28217e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng } 28227e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng } 28237e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng } 28247e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng 2825616471d4bfe4717fa86259ff4534703357b3b723Silviu Baranga if (DefAlign < 8 && Subtarget.isLikeA9()) { 2826ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng switch (DefMCID->getOpcode()) { 282775b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng default: break; 282875b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1q8: 282975b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1q16: 283075b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1q32: 283175b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1q64: 283210b90a9bbf7dcae1568c03a03f9606f5395f2144Jim Grosbach case ARM::VLD1q8wb_fixed: 283310b90a9bbf7dcae1568c03a03f9606f5395f2144Jim Grosbach case ARM::VLD1q16wb_fixed: 283410b90a9bbf7dcae1568c03a03f9606f5395f2144Jim Grosbach case ARM::VLD1q32wb_fixed: 283510b90a9bbf7dcae1568c03a03f9606f5395f2144Jim Grosbach case ARM::VLD1q64wb_fixed: 283610b90a9bbf7dcae1568c03a03f9606f5395f2144Jim Grosbach case ARM::VLD1q8wb_register: 283710b90a9bbf7dcae1568c03a03f9606f5395f2144Jim Grosbach case ARM::VLD1q16wb_register: 283810b90a9bbf7dcae1568c03a03f9606f5395f2144Jim Grosbach case ARM::VLD1q32wb_register: 283910b90a9bbf7dcae1568c03a03f9606f5395f2144Jim Grosbach case ARM::VLD1q64wb_register: 284075b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2d8: 284175b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2d16: 284275b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2d32: 284375b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2q8: 284475b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2q16: 284575b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2q32: 2846a4e3c7fc4ba2d55695b0484480685698132eba20Jim Grosbach case ARM::VLD2d8wb_fixed: 2847a4e3c7fc4ba2d55695b0484480685698132eba20Jim Grosbach case ARM::VLD2d16wb_fixed: 2848a4e3c7fc4ba2d55695b0484480685698132eba20Jim Grosbach case ARM::VLD2d32wb_fixed: 2849a4e3c7fc4ba2d55695b0484480685698132eba20Jim Grosbach case ARM::VLD2q8wb_fixed: 2850a4e3c7fc4ba2d55695b0484480685698132eba20Jim Grosbach case ARM::VLD2q16wb_fixed: 2851a4e3c7fc4ba2d55695b0484480685698132eba20Jim Grosbach case ARM::VLD2q32wb_fixed: 2852a4e3c7fc4ba2d55695b0484480685698132eba20Jim Grosbach case ARM::VLD2d8wb_register: 2853a4e3c7fc4ba2d55695b0484480685698132eba20Jim Grosbach case ARM::VLD2d16wb_register: 2854a4e3c7fc4ba2d55695b0484480685698132eba20Jim Grosbach case ARM::VLD2d32wb_register: 2855a4e3c7fc4ba2d55695b0484480685698132eba20Jim Grosbach case ARM::VLD2q8wb_register: 2856a4e3c7fc4ba2d55695b0484480685698132eba20Jim Grosbach case ARM::VLD2q16wb_register: 2857a4e3c7fc4ba2d55695b0484480685698132eba20Jim Grosbach case ARM::VLD2q32wb_register: 285875b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3d8: 285975b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3d16: 286075b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3d32: 286175b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1d64T: 286275b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3d8_UPD: 286375b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3d16_UPD: 286475b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3d32_UPD: 28655921675ff5ea632ab1e6d7aa5d1f263b858bbafaJim Grosbach case ARM::VLD1d64Twb_fixed: 28665921675ff5ea632ab1e6d7aa5d1f263b858bbafaJim Grosbach case ARM::VLD1d64Twb_register: 286775b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3q8_UPD: 286875b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3q16_UPD: 286975b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3q32_UPD: 287075b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4d8: 287175b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4d16: 287275b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4d32: 287375b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1d64Q: 287475b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4d8_UPD: 287575b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4d16_UPD: 287675b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4d32_UPD: 2877399cdca4d201f7232126c3a0643669971ede780aJim Grosbach case ARM::VLD1d64Qwb_fixed: 2878399cdca4d201f7232126c3a0643669971ede780aJim Grosbach case ARM::VLD1d64Qwb_register: 287975b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4q8_UPD: 288075b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4q16_UPD: 288175b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4q32_UPD: 288275b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1DUPq8: 288375b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1DUPq16: 288475b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1DUPq32: 2885096334e25ea68ac970942ecb680a82fbb8ad206cJim Grosbach case ARM::VLD1DUPq8wb_fixed: 2886096334e25ea68ac970942ecb680a82fbb8ad206cJim Grosbach case ARM::VLD1DUPq16wb_fixed: 2887096334e25ea68ac970942ecb680a82fbb8ad206cJim Grosbach case ARM::VLD1DUPq32wb_fixed: 2888096334e25ea68ac970942ecb680a82fbb8ad206cJim Grosbach case ARM::VLD1DUPq8wb_register: 2889096334e25ea68ac970942ecb680a82fbb8ad206cJim Grosbach case ARM::VLD1DUPq16wb_register: 2890096334e25ea68ac970942ecb680a82fbb8ad206cJim Grosbach case ARM::VLD1DUPq32wb_register: 289175b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2DUPd8: 289275b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2DUPd16: 289375b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2DUPd32: 2894e6949b13997e6d31aa4719a0e80c4b6b405e42a9Jim Grosbach case ARM::VLD2DUPd8wb_fixed: 2895e6949b13997e6d31aa4719a0e80c4b6b405e42a9Jim Grosbach case ARM::VLD2DUPd16wb_fixed: 2896e6949b13997e6d31aa4719a0e80c4b6b405e42a9Jim Grosbach case ARM::VLD2DUPd32wb_fixed: 2897e6949b13997e6d31aa4719a0e80c4b6b405e42a9Jim Grosbach case ARM::VLD2DUPd8wb_register: 2898e6949b13997e6d31aa4719a0e80c4b6b405e42a9Jim Grosbach case ARM::VLD2DUPd16wb_register: 2899e6949b13997e6d31aa4719a0e80c4b6b405e42a9Jim Grosbach case ARM::VLD2DUPd32wb_register: 290075b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4DUPd8: 290175b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4DUPd16: 290275b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4DUPd32: 290375b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4DUPd8_UPD: 290475b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4DUPd16_UPD: 290575b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4DUPd32_UPD: 290675b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1LNd8: 290775b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1LNd16: 290875b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1LNd32: 290975b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1LNd8_UPD: 291075b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1LNd16_UPD: 291175b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1LNd32_UPD: 291275b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2LNd8: 291375b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2LNd16: 291475b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2LNd32: 291575b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2LNq16: 291675b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2LNq32: 291775b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2LNd8_UPD: 291875b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2LNd16_UPD: 291975b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2LNd32_UPD: 292075b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2LNq16_UPD: 292175b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2LNq32_UPD: 292275b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4LNd8: 292375b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4LNd16: 292475b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4LNd32: 292575b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4LNq16: 292675b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4LNq32: 292775b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4LNd8_UPD: 292875b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4LNd16_UPD: 292975b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4LNd32_UPD: 293075b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4LNq16_UPD: 293175b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4LNq32_UPD: 293275b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng // If the address is not 64-bit aligned, the latencies of these 293375b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng // instructions increases by one. 293468b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick ++Adjust; 293575b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng break; 293675b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng } 293768b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick } 293868b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick return Adjust; 293968b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick} 294068b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick 294175b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng 294268b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick 294368b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trickint 294468b16541cc58411c7b0607ca4c0fb497222b668dAndrew TrickARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData, 294568b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick const MachineInstr *DefMI, unsigned DefIdx, 294668b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick const MachineInstr *UseMI, 294768b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick unsigned UseIdx) const { 294868b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick // No operand latency. The caller may fall back to getInstrLatency. 294968b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick if (!ItinData || ItinData->isEmpty()) 295068b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick return -1; 295168b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick 295268b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick const MachineOperand &DefMO = DefMI->getOperand(DefIdx); 295368b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick unsigned Reg = DefMO.getReg(); 295468b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick const MCInstrDesc *DefMCID = &DefMI->getDesc(); 295568b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick const MCInstrDesc *UseMCID = &UseMI->getDesc(); 295668b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick 295768b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick unsigned DefAdj = 0; 295868b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick if (DefMI->isBundle()) { 295968b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick DefMI = getBundledDefMI(&getRegisterInfo(), DefMI, Reg, DefIdx, DefAdj); 296068b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick DefMCID = &DefMI->getDesc(); 296168b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick } 296268b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick if (DefMI->isCopyLike() || DefMI->isInsertSubreg() || 296368b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick DefMI->isRegSequence() || DefMI->isImplicitDef()) { 296468b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick return 1; 296568b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick } 296668b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick 296768b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick unsigned UseAdj = 0; 296868b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick if (UseMI->isBundle()) { 296968b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick unsigned NewUseIdx; 297068b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick const MachineInstr *NewUseMI = getBundledUseMI(&getRegisterInfo(), UseMI, 297168b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick Reg, NewUseIdx, UseAdj); 2972e2b32bb20ee76f24708b3c9e19b6fbc651c25637Andrew Trick if (!NewUseMI) 2973e2b32bb20ee76f24708b3c9e19b6fbc651c25637Andrew Trick return -1; 2974e2b32bb20ee76f24708b3c9e19b6fbc651c25637Andrew Trick 2975e2b32bb20ee76f24708b3c9e19b6fbc651c25637Andrew Trick UseMI = NewUseMI; 2976e2b32bb20ee76f24708b3c9e19b6fbc651c25637Andrew Trick UseIdx = NewUseIdx; 2977e2b32bb20ee76f24708b3c9e19b6fbc651c25637Andrew Trick UseMCID = &UseMI->getDesc(); 297868b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick } 297968b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick 298068b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick if (Reg == ARM::CPSR) { 298168b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick if (DefMI->getOpcode() == ARM::FMSTAT) { 298268b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick // fpscr -> cpsr stalls over 20 cycles on A8 (and earlier?) 2983616471d4bfe4717fa86259ff4534703357b3b723Silviu Baranga return Subtarget.isLikeA9() ? 1 : 20; 298468b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick } 298568b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick 298668b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick // CPSR set and branch can be paired in the same cycle. 298768b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick if (UseMI->isBranch()) 298868b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick return 0; 298968b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick 299068b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick // Otherwise it takes the instruction latency (generally one). 299168b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick unsigned Latency = getInstrLatency(ItinData, DefMI); 299268b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick 299368b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick // For Thumb2 and -Os, prefer scheduling CPSR setting instruction close to 299468b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick // its uses. Instructions which are otherwise scheduled between them may 299568b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick // incur a code size penalty (not able to use the CPSR setting 16-bit 299668b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick // instructions). 299768b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick if (Latency > 0 && Subtarget.isThumb2()) { 299868b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick const MachineFunction *MF = DefMI->getParent()->getParent(); 299968b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick if (MF->getFunction()->hasFnAttr(Attribute::OptimizeForSize)) 300068b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick --Latency; 300168b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick } 300268b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick return Latency; 300368b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick } 300468b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick 3005e2b32bb20ee76f24708b3c9e19b6fbc651c25637Andrew Trick if (DefMO.isImplicit() || UseMI->getOperand(UseIdx).isImplicit()) 3006e2b32bb20ee76f24708b3c9e19b6fbc651c25637Andrew Trick return -1; 3007e2b32bb20ee76f24708b3c9e19b6fbc651c25637Andrew Trick 300868b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick unsigned DefAlign = DefMI->hasOneMemOperand() 300968b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick ? (*DefMI->memoperands_begin())->getAlignment() : 0; 301068b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick unsigned UseAlign = UseMI->hasOneMemOperand() 301168b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick ? (*UseMI->memoperands_begin())->getAlignment() : 0; 301268b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick 301368b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick // Get the itinerary's latency if possible, and handle variable_ops. 301468b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick int Latency = getOperandLatency(ItinData, *DefMCID, DefIdx, DefAlign, 301568b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick *UseMCID, UseIdx, UseAlign); 301668b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick // Unable to find operand latency. The caller may resort to getInstrLatency. 301768b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick if (Latency < 0) 301868b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick return Latency; 301968b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick 302068b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick // Adjust for IT block position. 302168b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick int Adj = DefAdj + UseAdj; 302268b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick 302368b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick // Adjust for dynamic def-side opcode variants not captured by the itinerary. 302468b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick Adj += adjustDefLatency(Subtarget, DefMI, DefMCID, DefAlign); 302568b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick if (Adj >= 0 || (int)Latency > -Adj) { 302668b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick return Latency + Adj; 302768b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick } 302868b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick // Return the itinerary latency, which may be zero but not less than zero. 30297e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng return Latency; 3030a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng} 3031a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng 3032a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Chengint 3033a0792de66c8364d47b0a688c7f408efb7b10f31bEvan ChengARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData, 3034a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng SDNode *DefNode, unsigned DefIdx, 3035a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng SDNode *UseNode, unsigned UseIdx) const { 3036a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng if (!DefNode->isMachineOpcode()) 3037a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng return 1; 3038a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng 3039e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng const MCInstrDesc &DefMCID = get(DefNode->getMachineOpcode()); 3040c8bfd1d78ff9a307d1d4cb57cce4549b538e60f4Andrew Trick 3041e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng if (isZeroCost(DefMCID.Opcode)) 3042c8bfd1d78ff9a307d1d4cb57cce4549b538e60f4Andrew Trick return 0; 3043c8bfd1d78ff9a307d1d4cb57cce4549b538e60f4Andrew Trick 3044a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng if (!ItinData || ItinData->isEmpty()) 3045e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng return DefMCID.mayLoad() ? 3 : 1; 3046a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng 3047089751535d6e9adf65842e2ca5867bf9a70e1e95Evan Cheng if (!UseNode->isMachineOpcode()) { 3048e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng int Latency = ItinData->getOperandCycle(DefMCID.getSchedClass(), DefIdx); 3049616471d4bfe4717fa86259ff4534703357b3b723Silviu Baranga if (Subtarget.isLikeA9()) 3050089751535d6e9adf65842e2ca5867bf9a70e1e95Evan Cheng return Latency <= 2 ? 1 : Latency - 1; 3051089751535d6e9adf65842e2ca5867bf9a70e1e95Evan Cheng else 3052089751535d6e9adf65842e2ca5867bf9a70e1e95Evan Cheng return Latency <= 3 ? 1 : Latency - 2; 3053089751535d6e9adf65842e2ca5867bf9a70e1e95Evan Cheng } 3054a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng 3055e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng const MCInstrDesc &UseMCID = get(UseNode->getMachineOpcode()); 3056a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng const MachineSDNode *DefMN = dyn_cast<MachineSDNode>(DefNode); 3057a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng unsigned DefAlign = !DefMN->memoperands_empty() 3058a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng ? (*DefMN->memoperands_begin())->getAlignment() : 0; 3059a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng const MachineSDNode *UseMN = dyn_cast<MachineSDNode>(UseNode); 3060a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng unsigned UseAlign = !UseMN->memoperands_empty() 3061a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng ? (*UseMN->memoperands_begin())->getAlignment() : 0; 3062e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng int Latency = getOperandLatency(ItinData, DefMCID, DefIdx, DefAlign, 3063e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng UseMCID, UseIdx, UseAlign); 30647e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng 30657e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng if (Latency > 1 && 3066616471d4bfe4717fa86259ff4534703357b3b723Silviu Baranga (Subtarget.isCortexA8() || Subtarget.isLikeA9())) { 30677e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng // FIXME: Shifter op hack: no shift (i.e. [r +/- r]) or [r + r << 2] 30687e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng // variants are one cycle cheaper. 3069e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng switch (DefMCID.getOpcode()) { 30707e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng default: break; 3071cff9baa95273bc279bf5fadb9e27afbd25cca20bJakob Stoklund Olesen case ARM::LDRrs: 3072cff9baa95273bc279bf5fadb9e27afbd25cca20bJakob Stoklund Olesen case ARM::LDRBrs: { 30737e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng unsigned ShOpVal = 30747e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng cast<ConstantSDNode>(DefNode->getOperand(2))->getZExtValue(); 30757e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal); 30767e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng if (ShImm == 0 || 30777e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng (ShImm == 2 && ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl)) 30787e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng --Latency; 30797e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng break; 30807e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng } 3081cff9baa95273bc279bf5fadb9e27afbd25cca20bJakob Stoklund Olesen case ARM::t2LDRs: 3082cff9baa95273bc279bf5fadb9e27afbd25cca20bJakob Stoklund Olesen case ARM::t2LDRBs: 3083cff9baa95273bc279bf5fadb9e27afbd25cca20bJakob Stoklund Olesen case ARM::t2LDRHs: 30847e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng case ARM::t2LDRSHs: { 30857e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng // Thumb2 mode: lsl only. 30867e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng unsigned ShAmt = 30877e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng cast<ConstantSDNode>(DefNode->getOperand(2))->getZExtValue(); 30887e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng if (ShAmt == 0 || ShAmt == 2) 30897e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng --Latency; 30907e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng break; 30917e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng } 30927e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng } 30937e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng } 30947e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng 3095616471d4bfe4717fa86259ff4534703357b3b723Silviu Baranga if (DefAlign < 8 && Subtarget.isLikeA9()) 3096e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng switch (DefMCID.getOpcode()) { 309775b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng default: break; 309828f08c93e75d291695ea89b9004145103292e85bJim Grosbach case ARM::VLD1q8: 309928f08c93e75d291695ea89b9004145103292e85bJim Grosbach case ARM::VLD1q16: 310028f08c93e75d291695ea89b9004145103292e85bJim Grosbach case ARM::VLD1q32: 310128f08c93e75d291695ea89b9004145103292e85bJim Grosbach case ARM::VLD1q64: 310228f08c93e75d291695ea89b9004145103292e85bJim Grosbach case ARM::VLD1q8wb_register: 310328f08c93e75d291695ea89b9004145103292e85bJim Grosbach case ARM::VLD1q16wb_register: 310428f08c93e75d291695ea89b9004145103292e85bJim Grosbach case ARM::VLD1q32wb_register: 310528f08c93e75d291695ea89b9004145103292e85bJim Grosbach case ARM::VLD1q64wb_register: 310628f08c93e75d291695ea89b9004145103292e85bJim Grosbach case ARM::VLD1q8wb_fixed: 310728f08c93e75d291695ea89b9004145103292e85bJim Grosbach case ARM::VLD1q16wb_fixed: 310828f08c93e75d291695ea89b9004145103292e85bJim Grosbach case ARM::VLD1q32wb_fixed: 310928f08c93e75d291695ea89b9004145103292e85bJim Grosbach case ARM::VLD1q64wb_fixed: 311028f08c93e75d291695ea89b9004145103292e85bJim Grosbach case ARM::VLD2d8: 311128f08c93e75d291695ea89b9004145103292e85bJim Grosbach case ARM::VLD2d16: 311228f08c93e75d291695ea89b9004145103292e85bJim Grosbach case ARM::VLD2d32: 311375b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2q8Pseudo: 311475b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2q16Pseudo: 311575b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2q32Pseudo: 311628f08c93e75d291695ea89b9004145103292e85bJim Grosbach case ARM::VLD2d8wb_fixed: 311728f08c93e75d291695ea89b9004145103292e85bJim Grosbach case ARM::VLD2d16wb_fixed: 311828f08c93e75d291695ea89b9004145103292e85bJim Grosbach case ARM::VLD2d32wb_fixed: 3119a4e3c7fc4ba2d55695b0484480685698132eba20Jim Grosbach case ARM::VLD2q8PseudoWB_fixed: 3120a4e3c7fc4ba2d55695b0484480685698132eba20Jim Grosbach case ARM::VLD2q16PseudoWB_fixed: 3121a4e3c7fc4ba2d55695b0484480685698132eba20Jim Grosbach case ARM::VLD2q32PseudoWB_fixed: 312228f08c93e75d291695ea89b9004145103292e85bJim Grosbach case ARM::VLD2d8wb_register: 312328f08c93e75d291695ea89b9004145103292e85bJim Grosbach case ARM::VLD2d16wb_register: 312428f08c93e75d291695ea89b9004145103292e85bJim Grosbach case ARM::VLD2d32wb_register: 3125a4e3c7fc4ba2d55695b0484480685698132eba20Jim Grosbach case ARM::VLD2q8PseudoWB_register: 3126a4e3c7fc4ba2d55695b0484480685698132eba20Jim Grosbach case ARM::VLD2q16PseudoWB_register: 3127a4e3c7fc4ba2d55695b0484480685698132eba20Jim Grosbach case ARM::VLD2q32PseudoWB_register: 312875b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3d8Pseudo: 312975b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3d16Pseudo: 313075b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3d32Pseudo: 313175b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1d64TPseudo: 313275b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3d8Pseudo_UPD: 313375b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3d16Pseudo_UPD: 313475b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3d32Pseudo_UPD: 313575b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3q8Pseudo_UPD: 313675b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3q16Pseudo_UPD: 313775b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3q32Pseudo_UPD: 313875b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3q8oddPseudo: 313975b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3q16oddPseudo: 314075b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3q32oddPseudo: 314175b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3q8oddPseudo_UPD: 314275b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3q16oddPseudo_UPD: 314375b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3q32oddPseudo_UPD: 314475b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4d8Pseudo: 314575b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4d16Pseudo: 314675b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4d32Pseudo: 314775b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1d64QPseudo: 314875b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4d8Pseudo_UPD: 314975b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4d16Pseudo_UPD: 315075b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4d32Pseudo_UPD: 315175b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4q8Pseudo_UPD: 315275b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4q16Pseudo_UPD: 315375b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4q32Pseudo_UPD: 315475b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4q8oddPseudo: 315575b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4q16oddPseudo: 315675b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4q32oddPseudo: 315775b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4q8oddPseudo_UPD: 315875b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4q16oddPseudo_UPD: 315975b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4q32oddPseudo_UPD: 3160c0fc450f0754508871bc70f21e528bf2f1520da1Jim Grosbach case ARM::VLD1DUPq8: 3161c0fc450f0754508871bc70f21e528bf2f1520da1Jim Grosbach case ARM::VLD1DUPq16: 3162c0fc450f0754508871bc70f21e528bf2f1520da1Jim Grosbach case ARM::VLD1DUPq32: 3163c0fc450f0754508871bc70f21e528bf2f1520da1Jim Grosbach case ARM::VLD1DUPq8wb_fixed: 3164c0fc450f0754508871bc70f21e528bf2f1520da1Jim Grosbach case ARM::VLD1DUPq16wb_fixed: 3165c0fc450f0754508871bc70f21e528bf2f1520da1Jim Grosbach case ARM::VLD1DUPq32wb_fixed: 3166c0fc450f0754508871bc70f21e528bf2f1520da1Jim Grosbach case ARM::VLD1DUPq8wb_register: 3167c0fc450f0754508871bc70f21e528bf2f1520da1Jim Grosbach case ARM::VLD1DUPq16wb_register: 3168c0fc450f0754508871bc70f21e528bf2f1520da1Jim Grosbach case ARM::VLD1DUPq32wb_register: 3169c0fc450f0754508871bc70f21e528bf2f1520da1Jim Grosbach case ARM::VLD2DUPd8: 3170c0fc450f0754508871bc70f21e528bf2f1520da1Jim Grosbach case ARM::VLD2DUPd16: 3171c0fc450f0754508871bc70f21e528bf2f1520da1Jim Grosbach case ARM::VLD2DUPd32: 3172c0fc450f0754508871bc70f21e528bf2f1520da1Jim Grosbach case ARM::VLD2DUPd8wb_fixed: 3173c0fc450f0754508871bc70f21e528bf2f1520da1Jim Grosbach case ARM::VLD2DUPd16wb_fixed: 3174c0fc450f0754508871bc70f21e528bf2f1520da1Jim Grosbach case ARM::VLD2DUPd32wb_fixed: 3175c0fc450f0754508871bc70f21e528bf2f1520da1Jim Grosbach case ARM::VLD2DUPd8wb_register: 3176c0fc450f0754508871bc70f21e528bf2f1520da1Jim Grosbach case ARM::VLD2DUPd16wb_register: 3177c0fc450f0754508871bc70f21e528bf2f1520da1Jim Grosbach case ARM::VLD2DUPd32wb_register: 317875b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4DUPd8Pseudo: 317975b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4DUPd16Pseudo: 318075b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4DUPd32Pseudo: 318175b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4DUPd8Pseudo_UPD: 318275b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4DUPd16Pseudo_UPD: 318375b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4DUPd32Pseudo_UPD: 318475b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1LNq8Pseudo: 318575b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1LNq16Pseudo: 318675b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1LNq32Pseudo: 318775b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1LNq8Pseudo_UPD: 318875b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1LNq16Pseudo_UPD: 318975b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1LNq32Pseudo_UPD: 319075b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2LNd8Pseudo: 319175b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2LNd16Pseudo: 319275b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2LNd32Pseudo: 319375b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2LNq16Pseudo: 319475b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2LNq32Pseudo: 319575b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2LNd8Pseudo_UPD: 319675b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2LNd16Pseudo_UPD: 319775b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2LNd32Pseudo_UPD: 319875b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2LNq16Pseudo_UPD: 319975b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2LNq32Pseudo_UPD: 320075b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4LNd8Pseudo: 320175b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4LNd16Pseudo: 320275b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4LNd32Pseudo: 320375b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4LNq16Pseudo: 320475b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4LNq32Pseudo: 320575b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4LNd8Pseudo_UPD: 320675b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4LNd16Pseudo_UPD: 320775b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4LNd32Pseudo_UPD: 320875b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4LNq16Pseudo_UPD: 320975b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4LNq32Pseudo_UPD: 321075b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng // If the address is not 64-bit aligned, the latencies of these 321175b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng // instructions increases by one. 321275b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng ++Latency; 321375b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng break; 321475b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng } 321575b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng 32167e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng return Latency; 3217a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng} 32182312842de0c641107dd04d7e056d02491cc781caEvan Cheng 3219020f4106f820648fd7e91956859844a80de13974Evan Chengunsigned 3220020f4106f820648fd7e91956859844a80de13974Evan ChengARMBaseInstrInfo::getOutputLatency(const InstrItineraryData *ItinData, 3221020f4106f820648fd7e91956859844a80de13974Evan Cheng const MachineInstr *DefMI, unsigned DefIdx, 3222020f4106f820648fd7e91956859844a80de13974Evan Cheng const MachineInstr *DepMI) const { 3223020f4106f820648fd7e91956859844a80de13974Evan Cheng unsigned Reg = DefMI->getOperand(DefIdx).getReg(); 3224020f4106f820648fd7e91956859844a80de13974Evan Cheng if (DepMI->readsRegister(Reg, &getRegisterInfo()) || !isPredicated(DepMI)) 3225020f4106f820648fd7e91956859844a80de13974Evan Cheng return 1; 3226020f4106f820648fd7e91956859844a80de13974Evan Cheng 3227020f4106f820648fd7e91956859844a80de13974Evan Cheng // If the second MI is predicated, then there is an implicit use dependency. 3228ef2d9e59aba381c42e018df9c26f9025c1995a64Andrew Trick return getInstrLatency(ItinData, DefMI); 3229020f4106f820648fd7e91956859844a80de13974Evan Cheng} 3230020f4106f820648fd7e91956859844a80de13974Evan Cheng 3231b7e0289fb320c8440ba5eed121a8b932dbd806a2Andrew Trickunsigned ARMBaseInstrInfo::getInstrLatency(const InstrItineraryData *ItinData, 3232b7e0289fb320c8440ba5eed121a8b932dbd806a2Andrew Trick const MachineInstr *MI, 3233b7e0289fb320c8440ba5eed121a8b932dbd806a2Andrew Trick unsigned *PredCost) const { 32348239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng if (MI->isCopyLike() || MI->isInsertSubreg() || 32358239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng MI->isRegSequence() || MI->isImplicitDef()) 32368239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng return 1; 32378239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng 3238ed7a51e69209af87f3749d5f95740f69a1dc7711Andrew Trick // An instruction scheduler typically runs on unbundled instructions, however 3239ed7a51e69209af87f3749d5f95740f69a1dc7711Andrew Trick // other passes may query the latency of a bundled instruction. 3240ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng if (MI->isBundle()) { 3241ed7a51e69209af87f3749d5f95740f69a1dc7711Andrew Trick unsigned Latency = 0; 3242ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng MachineBasicBlock::const_instr_iterator I = MI; 3243ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end(); 3244ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng while (++I != E && I->isInsideBundle()) { 3245ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng if (I->getOpcode() != ARM::t2IT) 3246ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng Latency += getInstrLatency(ItinData, I, PredCost); 3247ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng } 3248ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng return Latency; 3249ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng } 3250ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng 3251e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng const MCInstrDesc &MCID = MI->getDesc(); 3252ed7a51e69209af87f3749d5f95740f69a1dc7711Andrew Trick if (PredCost && (MCID.isCall() || MCID.hasImplicitDefOfPhysReg(ARM::CPSR))) { 32538239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng // When predicated, CPSR is an additional source operand for CPSR updating 32548239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng // instructions, this apparently increases their latencies. 32558239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng *PredCost = 1; 3256ed7a51e69209af87f3749d5f95740f69a1dc7711Andrew Trick } 3257ed7a51e69209af87f3749d5f95740f69a1dc7711Andrew Trick // Be sure to call getStageLatency for an empty itinerary in case it has a 3258ed7a51e69209af87f3749d5f95740f69a1dc7711Andrew Trick // valid MinLatency property. 3259ed7a51e69209af87f3749d5f95740f69a1dc7711Andrew Trick if (!ItinData) 3260ed7a51e69209af87f3749d5f95740f69a1dc7711Andrew Trick return MI->mayLoad() ? 3 : 1; 3261ed7a51e69209af87f3749d5f95740f69a1dc7711Andrew Trick 3262ed7a51e69209af87f3749d5f95740f69a1dc7711Andrew Trick unsigned Class = MCID.getSchedClass(); 3263ed7a51e69209af87f3749d5f95740f69a1dc7711Andrew Trick 3264ed7a51e69209af87f3749d5f95740f69a1dc7711Andrew Trick // For instructions with variable uops, use uops as latency. 326514ccc7b963861a856b593cc4fff62decd8ce248aAndrew Trick if (!ItinData->isEmpty() && ItinData->getNumMicroOps(Class) < 0) 3266ed7a51e69209af87f3749d5f95740f69a1dc7711Andrew Trick return getNumMicroOps(ItinData, MI); 326714ccc7b963861a856b593cc4fff62decd8ce248aAndrew Trick 3268ed7a51e69209af87f3749d5f95740f69a1dc7711Andrew Trick // For the common case, fall back on the itinerary's latency. 326968b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick unsigned Latency = ItinData->getStageLatency(Class); 327068b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick 327168b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick // Adjust for dynamic def-side opcode variants not captured by the itinerary. 327268b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick unsigned DefAlign = MI->hasOneMemOperand() 327368b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick ? (*MI->memoperands_begin())->getAlignment() : 0; 327468b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick int Adj = adjustDefLatency(Subtarget, MI, &MCID, DefAlign); 327568b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick if (Adj >= 0 || (int)Latency > -Adj) { 327668b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick return Latency + Adj; 327768b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick } 327868b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick return Latency; 32798239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng} 32808239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng 32818239daf7c83a65a189c352cce3191cdc3bbfe151Evan Chengint ARMBaseInstrInfo::getInstrLatency(const InstrItineraryData *ItinData, 32828239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng SDNode *Node) const { 32838239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng if (!Node->isMachineOpcode()) 32848239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng return 1; 32858239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng 32868239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng if (!ItinData || ItinData->isEmpty()) 32878239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng return 1; 32888239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng 32898239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng unsigned Opcode = Node->getMachineOpcode(); 32908239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng switch (Opcode) { 32918239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng default: 32928239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng return ItinData->getStageLatency(get(Opcode).getSchedClass()); 329373fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMQIA: 329473fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMQIA: 32958239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng return 2; 32968b3ca6216d62bf3f729c2e122dcfeb7c4d7500dcEric Christopher } 32978239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng} 32988239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng 32992312842de0c641107dd04d7e056d02491cc781caEvan Chengbool ARMBaseInstrInfo:: 33002312842de0c641107dd04d7e056d02491cc781caEvan ChenghasHighOperandLatency(const InstrItineraryData *ItinData, 33012312842de0c641107dd04d7e056d02491cc781caEvan Cheng const MachineRegisterInfo *MRI, 33022312842de0c641107dd04d7e056d02491cc781caEvan Cheng const MachineInstr *DefMI, unsigned DefIdx, 33032312842de0c641107dd04d7e056d02491cc781caEvan Cheng const MachineInstr *UseMI, unsigned UseIdx) const { 33042312842de0c641107dd04d7e056d02491cc781caEvan Cheng unsigned DDomain = DefMI->getDesc().TSFlags & ARMII::DomainMask; 33052312842de0c641107dd04d7e056d02491cc781caEvan Cheng unsigned UDomain = UseMI->getDesc().TSFlags & ARMII::DomainMask; 33062312842de0c641107dd04d7e056d02491cc781caEvan Cheng if (Subtarget.isCortexA8() && 33072312842de0c641107dd04d7e056d02491cc781caEvan Cheng (DDomain == ARMII::DomainVFP || UDomain == ARMII::DomainVFP)) 33082312842de0c641107dd04d7e056d02491cc781caEvan Cheng // CortexA8 VFP instructions are not pipelined. 33092312842de0c641107dd04d7e056d02491cc781caEvan Cheng return true; 33102312842de0c641107dd04d7e056d02491cc781caEvan Cheng 33112312842de0c641107dd04d7e056d02491cc781caEvan Cheng // Hoist VFP / NEON instructions with 4 or higher latency. 3312397f4e3583b36b23047fec06b1648f0771cd6fe3Andrew Trick int Latency = computeOperandLatency(ItinData, DefMI, DefIdx, UseMI, UseIdx, 3313397f4e3583b36b23047fec06b1648f0771cd6fe3Andrew Trick /*FindMin=*/false); 3314f377071bf8393d35797107c753da3e84aea94ebeAndrew Trick if (Latency < 0) 3315f377071bf8393d35797107c753da3e84aea94ebeAndrew Trick Latency = getInstrLatency(ItinData, DefMI); 33162312842de0c641107dd04d7e056d02491cc781caEvan Cheng if (Latency <= 3) 33172312842de0c641107dd04d7e056d02491cc781caEvan Cheng return false; 33182312842de0c641107dd04d7e056d02491cc781caEvan Cheng return DDomain == ARMII::DomainVFP || DDomain == ARMII::DomainNEON || 33192312842de0c641107dd04d7e056d02491cc781caEvan Cheng UDomain == ARMII::DomainVFP || UDomain == ARMII::DomainNEON; 33202312842de0c641107dd04d7e056d02491cc781caEvan Cheng} 3321c8141dfc7f983cb04e65d8acd6bcbdc8e4b8a0aeEvan Cheng 3322c8141dfc7f983cb04e65d8acd6bcbdc8e4b8a0aeEvan Chengbool ARMBaseInstrInfo:: 3323c8141dfc7f983cb04e65d8acd6bcbdc8e4b8a0aeEvan ChenghasLowDefLatency(const InstrItineraryData *ItinData, 3324c8141dfc7f983cb04e65d8acd6bcbdc8e4b8a0aeEvan Cheng const MachineInstr *DefMI, unsigned DefIdx) const { 3325c8141dfc7f983cb04e65d8acd6bcbdc8e4b8a0aeEvan Cheng if (!ItinData || ItinData->isEmpty()) 3326c8141dfc7f983cb04e65d8acd6bcbdc8e4b8a0aeEvan Cheng return false; 3327c8141dfc7f983cb04e65d8acd6bcbdc8e4b8a0aeEvan Cheng 3328c8141dfc7f983cb04e65d8acd6bcbdc8e4b8a0aeEvan Cheng unsigned DDomain = DefMI->getDesc().TSFlags & ARMII::DomainMask; 3329c8141dfc7f983cb04e65d8acd6bcbdc8e4b8a0aeEvan Cheng if (DDomain == ARMII::DomainGeneral) { 3330c8141dfc7f983cb04e65d8acd6bcbdc8e4b8a0aeEvan Cheng unsigned DefClass = DefMI->getDesc().getSchedClass(); 3331c8141dfc7f983cb04e65d8acd6bcbdc8e4b8a0aeEvan Cheng int DefCycle = ItinData->getOperandCycle(DefClass, DefIdx); 3332c8141dfc7f983cb04e65d8acd6bcbdc8e4b8a0aeEvan Cheng return (DefCycle != -1 && DefCycle <= 2); 3333c8141dfc7f983cb04e65d8acd6bcbdc8e4b8a0aeEvan Cheng } 3334c8141dfc7f983cb04e65d8acd6bcbdc8e4b8a0aeEvan Cheng return false; 3335c8141dfc7f983cb04e65d8acd6bcbdc8e4b8a0aeEvan Cheng} 333648575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng 33373be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trickbool ARMBaseInstrInfo::verifyInstruction(const MachineInstr *MI, 33383be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick StringRef &ErrInfo) const { 33393be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick if (convertAddSubFlagsOpcode(MI->getOpcode())) { 33403be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick ErrInfo = "Pseudo flag setting opcodes only exist in Selection DAG"; 33413be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick return false; 33423be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick } 33433be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick return true; 33443be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick} 33453be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick 334648575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Chengbool 334748575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan ChengARMBaseInstrInfo::isFpMLxInstruction(unsigned Opcode, unsigned &MulOpc, 334848575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng unsigned &AddSubOpc, 334948575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng bool &NegAcc, bool &HasLane) const { 335048575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng DenseMap<unsigned, unsigned>::const_iterator I = MLxEntryMap.find(Opcode); 335148575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng if (I == MLxEntryMap.end()) 335248575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng return false; 335348575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng 335448575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng const ARM_MLxEntry &Entry = ARM_MLxTable[I->second]; 335548575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng MulOpc = Entry.MulOpc; 335648575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng AddSubOpc = Entry.AddSubOpc; 335748575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng NegAcc = Entry.NegAcc; 335848575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng HasLane = Entry.HasLane; 335948575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng return true; 336048575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng} 336113fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen 336213fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen//===----------------------------------------------------------------------===// 336313fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen// Execution domains. 336413fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen//===----------------------------------------------------------------------===// 336513fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen// 336613fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen// Some instructions go down the NEON pipeline, some go down the VFP pipeline, 336713fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen// and some can go down both. The vmov instructions go down the VFP pipeline, 336813fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen// but they can be changed to vorr equivalents that are executed by the NEON 336913fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen// pipeline. 337013fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen// 337113fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen// We use the following execution domain numbering: 337213fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen// 33738bb3d3cb30df06bdcb3ef5a208e3e59f4eeb4868Jakob Stoklund Olesenenum ARMExeDomain { 33748bb3d3cb30df06bdcb3ef5a208e3e59f4eeb4868Jakob Stoklund Olesen ExeGeneric = 0, 33758bb3d3cb30df06bdcb3ef5a208e3e59f4eeb4868Jakob Stoklund Olesen ExeVFP = 1, 33768bb3d3cb30df06bdcb3ef5a208e3e59f4eeb4868Jakob Stoklund Olesen ExeNEON = 2 33778bb3d3cb30df06bdcb3ef5a208e3e59f4eeb4868Jakob Stoklund Olesen}; 337813fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen// 337913fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen// Also see ARMInstrFormats.td and Domain* enums in ARMBaseInfo.h 338013fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen// 338113fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesenstd::pair<uint16_t, uint16_t> 338213fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund OlesenARMBaseInstrInfo::getExecutionDomain(const MachineInstr *MI) const { 33833c8ad92455ff06c8e69085702ef1f13944eab4ddTim Northover // VMOVD, VMOVRS and VMOVSR are VFP instructions, but can be changed to NEON 33843c8ad92455ff06c8e69085702ef1f13944eab4ddTim Northover // if they are not predicated. 338513fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen if (MI->getOpcode() == ARM::VMOVD && !isPredicated(MI)) 33868bb3d3cb30df06bdcb3ef5a208e3e59f4eeb4868Jakob Stoklund Olesen return std::make_pair(ExeVFP, (1<<ExeVFP) | (1<<ExeNEON)); 338713fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen 3388616471d4bfe4717fa86259ff4534703357b3b723Silviu Baranga // A9-like cores are particularly picky about mixing the two and want these 33893c8ad92455ff06c8e69085702ef1f13944eab4ddTim Northover // converted. 3390616471d4bfe4717fa86259ff4534703357b3b723Silviu Baranga if (Subtarget.isLikeA9() && !isPredicated(MI) && 33913c8ad92455ff06c8e69085702ef1f13944eab4ddTim Northover (MI->getOpcode() == ARM::VMOVRS || 3392c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover MI->getOpcode() == ARM::VMOVSR || 3393c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover MI->getOpcode() == ARM::VMOVS)) 33943c8ad92455ff06c8e69085702ef1f13944eab4ddTim Northover return std::make_pair(ExeVFP, (1<<ExeVFP) | (1<<ExeNEON)); 33953c8ad92455ff06c8e69085702ef1f13944eab4ddTim Northover 339613fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen // No other instructions can be swizzled, so just determine their domain. 339713fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen unsigned Domain = MI->getDesc().TSFlags & ARMII::DomainMask; 339813fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen 339913fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen if (Domain & ARMII::DomainNEON) 34008bb3d3cb30df06bdcb3ef5a208e3e59f4eeb4868Jakob Stoklund Olesen return std::make_pair(ExeNEON, 0); 340113fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen 340213fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen // Certain instructions can go either way on Cortex-A8. 340313fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen // Treat them as NEON instructions. 340413fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen if ((Domain & ARMII::DomainNEONA8) && Subtarget.isCortexA8()) 34058bb3d3cb30df06bdcb3ef5a208e3e59f4eeb4868Jakob Stoklund Olesen return std::make_pair(ExeNEON, 0); 340613fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen 340713fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen if (Domain & ARMII::DomainVFP) 34088bb3d3cb30df06bdcb3ef5a208e3e59f4eeb4868Jakob Stoklund Olesen return std::make_pair(ExeVFP, 0); 340913fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen 34108bb3d3cb30df06bdcb3ef5a208e3e59f4eeb4868Jakob Stoklund Olesen return std::make_pair(ExeGeneric, 0); 341113fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen} 341213fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen 341320599ea4bced03634a54b52e98d261018366f279Tim Northoverstatic unsigned getCorrespondingDRegAndLane(const TargetRegisterInfo *TRI, 341420599ea4bced03634a54b52e98d261018366f279Tim Northover unsigned SReg, unsigned &Lane) { 341520599ea4bced03634a54b52e98d261018366f279Tim Northover unsigned DReg = TRI->getMatchingSuperReg(SReg, ARM::ssub_0, &ARM::DPRRegClass); 341620599ea4bced03634a54b52e98d261018366f279Tim Northover Lane = 0; 341720599ea4bced03634a54b52e98d261018366f279Tim Northover 341820599ea4bced03634a54b52e98d261018366f279Tim Northover if (DReg != ARM::NoRegister) 341920599ea4bced03634a54b52e98d261018366f279Tim Northover return DReg; 342020599ea4bced03634a54b52e98d261018366f279Tim Northover 342120599ea4bced03634a54b52e98d261018366f279Tim Northover Lane = 1; 342220599ea4bced03634a54b52e98d261018366f279Tim Northover DReg = TRI->getMatchingSuperReg(SReg, ARM::ssub_1, &ARM::DPRRegClass); 342320599ea4bced03634a54b52e98d261018366f279Tim Northover 342420599ea4bced03634a54b52e98d261018366f279Tim Northover assert(DReg && "S-register with no D super-register?"); 342520599ea4bced03634a54b52e98d261018366f279Tim Northover return DReg; 342620599ea4bced03634a54b52e98d261018366f279Tim Northover} 342720599ea4bced03634a54b52e98d261018366f279Tim Northover 342897ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy/// getImplicitSPRUseForDPRUse - Given a use of a DPR register and lane, 342997ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy/// set ImplicitSReg to a register number that must be marked as implicit-use or 343097ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy/// zero if no register needs to be defined as implicit-use. 343197ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy/// 343297ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy/// If the function cannot determine if an SPR should be marked implicit use or 343397ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy/// not, it returns false. 343497ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy/// 343597ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy/// This function handles cases where an instruction is being modified from taking 343697ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy/// an SPR to a DPR[Lane]. A use of the DPR is being added, which may conflict 343797ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy/// with an earlier def of an SPR corresponding to DPR[Lane^1] (i.e. the other 343897ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy/// lane of the DPR). 343997ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy/// 344097ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy/// If the other SPR is defined, an implicit-use of it should be added. Else, 344197ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy/// (including the case where the DPR itself is defined), it should not. 344297ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy/// 344397ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloystatic bool getImplicitSPRUseForDPRUse(const TargetRegisterInfo *TRI, 344497ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy MachineInstr *MI, 344597ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy unsigned DReg, unsigned Lane, 344697ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy unsigned &ImplicitSReg) { 344797ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy // If the DPR is defined or used already, the other SPR lane will be chained 344897ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy // correctly, so there is nothing to be done. 344997ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy if (MI->definesRegister(DReg, TRI) || MI->readsRegister(DReg, TRI)) { 345097ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy ImplicitSReg = 0; 345197ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy return true; 345297ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy } 345397ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy 345497ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy // Otherwise we need to go searching to see if the SPR is set explicitly. 345597ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy ImplicitSReg = TRI->getSubReg(DReg, 345697ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy (Lane & 1) ? ARM::ssub_0 : ARM::ssub_1); 345797ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy MachineBasicBlock::LivenessQueryResult LQR = 345897ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy MI->getParent()->computeRegisterLiveness(TRI, ImplicitSReg, MI); 345997ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy 346097ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy if (LQR == MachineBasicBlock::LQR_Live) 346197ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy return true; 346297ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy else if (LQR == MachineBasicBlock::LQR_Unknown) 346397ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy return false; 346497ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy 346597ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy // If the register is known not to be live, there is no need to add an 346697ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy // implicit-use. 346797ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy ImplicitSReg = 0; 346897ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy return true; 346997ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy} 347020599ea4bced03634a54b52e98d261018366f279Tim Northover 347113fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesenvoid 347213fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund OlesenARMBaseInstrInfo::setExecutionDomain(MachineInstr *MI, unsigned Domain) const { 34733c8ad92455ff06c8e69085702ef1f13944eab4ddTim Northover unsigned DstReg, SrcReg, DReg; 34743c8ad92455ff06c8e69085702ef1f13944eab4ddTim Northover unsigned Lane; 34753c8ad92455ff06c8e69085702ef1f13944eab4ddTim Northover MachineInstrBuilder MIB(MI); 34763c8ad92455ff06c8e69085702ef1f13944eab4ddTim Northover const TargetRegisterInfo *TRI = &getRegisterInfo(); 34773c8ad92455ff06c8e69085702ef1f13944eab4ddTim Northover switch (MI->getOpcode()) { 34783c8ad92455ff06c8e69085702ef1f13944eab4ddTim Northover default: 34793c8ad92455ff06c8e69085702ef1f13944eab4ddTim Northover llvm_unreachable("cannot handle opcode!"); 34803c8ad92455ff06c8e69085702ef1f13944eab4ddTim Northover break; 34813c8ad92455ff06c8e69085702ef1f13944eab4ddTim Northover case ARM::VMOVD: 34823c8ad92455ff06c8e69085702ef1f13944eab4ddTim Northover if (Domain != ExeNEON) 34833c8ad92455ff06c8e69085702ef1f13944eab4ddTim Northover break; 34843c8ad92455ff06c8e69085702ef1f13944eab4ddTim Northover 34853c8ad92455ff06c8e69085702ef1f13944eab4ddTim Northover // Zap the predicate operands. 34863c8ad92455ff06c8e69085702ef1f13944eab4ddTim Northover assert(!isPredicated(MI) && "Cannot predicate a VORRd"); 34873c8ad92455ff06c8e69085702ef1f13944eab4ddTim Northover 348820599ea4bced03634a54b52e98d261018366f279Tim Northover // Source instruction is %DDst = VMOVD %DSrc, 14, %noreg (; implicits) 348920599ea4bced03634a54b52e98d261018366f279Tim Northover DstReg = MI->getOperand(0).getReg(); 349020599ea4bced03634a54b52e98d261018366f279Tim Northover SrcReg = MI->getOperand(1).getReg(); 34913c8ad92455ff06c8e69085702ef1f13944eab4ddTim Northover 349220599ea4bced03634a54b52e98d261018366f279Tim Northover for (unsigned i = MI->getDesc().getNumOperands(); i; --i) 349320599ea4bced03634a54b52e98d261018366f279Tim Northover MI->RemoveOperand(i-1); 349420599ea4bced03634a54b52e98d261018366f279Tim Northover 349520599ea4bced03634a54b52e98d261018366f279Tim Northover // Change to a %DDst = VORRd %DSrc, %DSrc, 14, %noreg (; implicits) 349620599ea4bced03634a54b52e98d261018366f279Tim Northover MI->setDesc(get(ARM::VORRd)); 349720599ea4bced03634a54b52e98d261018366f279Tim Northover AddDefaultPred(MIB.addReg(DstReg, RegState::Define) 349820599ea4bced03634a54b52e98d261018366f279Tim Northover .addReg(SrcReg) 349920599ea4bced03634a54b52e98d261018366f279Tim Northover .addReg(SrcReg)); 35003c8ad92455ff06c8e69085702ef1f13944eab4ddTim Northover break; 35013c8ad92455ff06c8e69085702ef1f13944eab4ddTim Northover case ARM::VMOVRS: 35023c8ad92455ff06c8e69085702ef1f13944eab4ddTim Northover if (Domain != ExeNEON) 35033c8ad92455ff06c8e69085702ef1f13944eab4ddTim Northover break; 35043c8ad92455ff06c8e69085702ef1f13944eab4ddTim Northover assert(!isPredicated(MI) && "Cannot predicate a VGETLN"); 35053c8ad92455ff06c8e69085702ef1f13944eab4ddTim Northover 350620599ea4bced03634a54b52e98d261018366f279Tim Northover // Source instruction is %RDst = VMOVRS %SSrc, 14, %noreg (; implicits) 35073c8ad92455ff06c8e69085702ef1f13944eab4ddTim Northover DstReg = MI->getOperand(0).getReg(); 35083c8ad92455ff06c8e69085702ef1f13944eab4ddTim Northover SrcReg = MI->getOperand(1).getReg(); 350913fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen 351020599ea4bced03634a54b52e98d261018366f279Tim Northover for (unsigned i = MI->getDesc().getNumOperands(); i; --i) 351120599ea4bced03634a54b52e98d261018366f279Tim Northover MI->RemoveOperand(i-1); 35123c8ad92455ff06c8e69085702ef1f13944eab4ddTim Northover 351320599ea4bced03634a54b52e98d261018366f279Tim Northover DReg = getCorrespondingDRegAndLane(TRI, SrcReg, Lane); 35143c8ad92455ff06c8e69085702ef1f13944eab4ddTim Northover 351520599ea4bced03634a54b52e98d261018366f279Tim Northover // Convert to %RDst = VGETLNi32 %DSrc, Lane, 14, %noreg (; imps) 351620599ea4bced03634a54b52e98d261018366f279Tim Northover // Note that DSrc has been widened and the other lane may be undef, which 351720599ea4bced03634a54b52e98d261018366f279Tim Northover // contaminates the entire register. 35183c8ad92455ff06c8e69085702ef1f13944eab4ddTim Northover MI->setDesc(get(ARM::VGETLNi32)); 351920599ea4bced03634a54b52e98d261018366f279Tim Northover AddDefaultPred(MIB.addReg(DstReg, RegState::Define) 352020599ea4bced03634a54b52e98d261018366f279Tim Northover .addReg(DReg, RegState::Undef) 352120599ea4bced03634a54b52e98d261018366f279Tim Northover .addImm(Lane)); 35223c8ad92455ff06c8e69085702ef1f13944eab4ddTim Northover 352320599ea4bced03634a54b52e98d261018366f279Tim Northover // The old source should be an implicit use, otherwise we might think it 352420599ea4bced03634a54b52e98d261018366f279Tim Northover // was dead before here. 35253c8ad92455ff06c8e69085702ef1f13944eab4ddTim Northover MIB.addReg(SrcReg, RegState::Implicit); 35263c8ad92455ff06c8e69085702ef1f13944eab4ddTim Northover break; 352797ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy case ARM::VMOVSR: { 35283c8ad92455ff06c8e69085702ef1f13944eab4ddTim Northover if (Domain != ExeNEON) 35293c8ad92455ff06c8e69085702ef1f13944eab4ddTim Northover break; 35303c8ad92455ff06c8e69085702ef1f13944eab4ddTim Northover assert(!isPredicated(MI) && "Cannot predicate a VSETLN"); 35313c8ad92455ff06c8e69085702ef1f13944eab4ddTim Northover 353220599ea4bced03634a54b52e98d261018366f279Tim Northover // Source instruction is %SDst = VMOVSR %RSrc, 14, %noreg (; implicits) 35333c8ad92455ff06c8e69085702ef1f13944eab4ddTim Northover DstReg = MI->getOperand(0).getReg(); 35343c8ad92455ff06c8e69085702ef1f13944eab4ddTim Northover SrcReg = MI->getOperand(1).getReg(); 35353c8ad92455ff06c8e69085702ef1f13944eab4ddTim Northover 353620599ea4bced03634a54b52e98d261018366f279Tim Northover DReg = getCorrespondingDRegAndLane(TRI, DstReg, Lane); 35373c8ad92455ff06c8e69085702ef1f13944eab4ddTim Northover 353897ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy unsigned ImplicitSReg; 353997ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy if (!getImplicitSPRUseForDPRUse(TRI, MI, DReg, Lane, ImplicitSReg)) 354097ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy break; 354189f49808ee79eebbc3267b6c595514d4ca1f3247Tim Northover 35427bebddf55ece46995f310d79195afb4e5b239886Tim Northover for (unsigned i = MI->getDesc().getNumOperands(); i; --i) 35437bebddf55ece46995f310d79195afb4e5b239886Tim Northover MI->RemoveOperand(i-1); 35447bebddf55ece46995f310d79195afb4e5b239886Tim Northover 354520599ea4bced03634a54b52e98d261018366f279Tim Northover // Convert to %DDst = VSETLNi32 %DDst, %RSrc, Lane, 14, %noreg (; imps) 354620599ea4bced03634a54b52e98d261018366f279Tim Northover // Again DDst may be undefined at the beginning of this instruction. 354720599ea4bced03634a54b52e98d261018366f279Tim Northover MI->setDesc(get(ARM::VSETLNi32)); 354889f49808ee79eebbc3267b6c595514d4ca1f3247Tim Northover MIB.addReg(DReg, RegState::Define) 354989f49808ee79eebbc3267b6c595514d4ca1f3247Tim Northover .addReg(DReg, getUndefRegState(!MI->readsRegister(DReg, TRI))) 355089f49808ee79eebbc3267b6c595514d4ca1f3247Tim Northover .addReg(SrcReg) 355189f49808ee79eebbc3267b6c595514d4ca1f3247Tim Northover .addImm(Lane); 355289f49808ee79eebbc3267b6c595514d4ca1f3247Tim Northover AddDefaultPred(MIB); 3553c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover 355489f49808ee79eebbc3267b6c595514d4ca1f3247Tim Northover // The narrower destination must be marked as set to keep previous chains 355589f49808ee79eebbc3267b6c595514d4ca1f3247Tim Northover // in place. 355620599ea4bced03634a54b52e98d261018366f279Tim Northover MIB.addReg(DstReg, RegState::Define | RegState::Implicit); 355797ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy if (ImplicitSReg != 0) 355897ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy MIB.addReg(ImplicitSReg, RegState::Implicit); 35593c8ad92455ff06c8e69085702ef1f13944eab4ddTim Northover break; 356097ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy } 3561c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover case ARM::VMOVS: { 3562c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover if (Domain != ExeNEON) 3563c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover break; 3564c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover 3565c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover // Source instruction is %SDst = VMOVS %SSrc, 14, %noreg (; implicits) 3566c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover DstReg = MI->getOperand(0).getReg(); 3567c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover SrcReg = MI->getOperand(1).getReg(); 3568c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover 3569c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover unsigned DstLane = 0, SrcLane = 0, DDst, DSrc; 3570c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover DDst = getCorrespondingDRegAndLane(TRI, DstReg, DstLane); 3571c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover DSrc = getCorrespondingDRegAndLane(TRI, SrcReg, SrcLane); 3572c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover 357397ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy unsigned ImplicitSReg; 357497ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy if (!getImplicitSPRUseForDPRUse(TRI, MI, DSrc, SrcLane, ImplicitSReg)) 357597ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy break; 357689f49808ee79eebbc3267b6c595514d4ca1f3247Tim Northover 35777bebddf55ece46995f310d79195afb4e5b239886Tim Northover for (unsigned i = MI->getDesc().getNumOperands(); i; --i) 35787bebddf55ece46995f310d79195afb4e5b239886Tim Northover MI->RemoveOperand(i-1); 35797bebddf55ece46995f310d79195afb4e5b239886Tim Northover 3580c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover if (DSrc == DDst) { 3581c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover // Destination can be: 3582c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover // %DDst = VDUPLN32d %DDst, Lane, 14, %noreg (; implicits) 3583c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover MI->setDesc(get(ARM::VDUPLN32d)); 358489f49808ee79eebbc3267b6c595514d4ca1f3247Tim Northover MIB.addReg(DDst, RegState::Define) 358589f49808ee79eebbc3267b6c595514d4ca1f3247Tim Northover .addReg(DDst, getUndefRegState(!MI->readsRegister(DDst, TRI))) 358689f49808ee79eebbc3267b6c595514d4ca1f3247Tim Northover .addImm(SrcLane); 358789f49808ee79eebbc3267b6c595514d4ca1f3247Tim Northover AddDefaultPred(MIB); 3588c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover 3589c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover // Neither the source or the destination are naturally represented any 3590c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover // more, so add them in manually. 3591c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover MIB.addReg(DstReg, RegState::Implicit | RegState::Define); 3592c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover MIB.addReg(SrcReg, RegState::Implicit); 359397ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy if (ImplicitSReg != 0) 359497ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy MIB.addReg(ImplicitSReg, RegState::Implicit); 3595c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover break; 3596c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover } 3597c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover 3598c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover // In general there's no single instruction that can perform an S <-> S 3599c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover // move in NEON space, but a pair of VEXT instructions *can* do the 3600c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover // job. It turns out that the VEXTs needed will only use DSrc once, with 3601c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover // the position based purely on the combination of lane-0 and lane-1 3602c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover // involved. For example 3603c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover // vmov s0, s2 -> vext.32 d0, d0, d1, #1 vext.32 d0, d0, d0, #1 3604c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover // vmov s1, s3 -> vext.32 d0, d1, d0, #1 vext.32 d0, d0, d0, #1 3605c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover // vmov s0, s3 -> vext.32 d0, d0, d0, #1 vext.32 d0, d1, d0, #1 3606c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover // vmov s1, s2 -> vext.32 d0, d0, d0, #1 vext.32 d0, d0, d1, #1 3607c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover // 3608c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover // Pattern of the MachineInstrs is: 3609c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover // %DDst = VEXTd32 %DSrc1, %DSrc2, Lane, 14, %noreg (;implicits) 3610c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover MachineInstrBuilder NewMIB; 3611c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover NewMIB = BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), 3612c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover get(ARM::VEXTd32), DDst); 361389f49808ee79eebbc3267b6c595514d4ca1f3247Tim Northover 361489f49808ee79eebbc3267b6c595514d4ca1f3247Tim Northover // On the first instruction, both DSrc and DDst may be <undef> if present. 361589f49808ee79eebbc3267b6c595514d4ca1f3247Tim Northover // Specifically when the original instruction didn't have them as an 361689f49808ee79eebbc3267b6c595514d4ca1f3247Tim Northover // <imp-use>. 361789f49808ee79eebbc3267b6c595514d4ca1f3247Tim Northover unsigned CurReg = SrcLane == 1 && DstLane == 1 ? DSrc : DDst; 361889f49808ee79eebbc3267b6c595514d4ca1f3247Tim Northover bool CurUndef = !MI->readsRegister(CurReg, TRI); 361989f49808ee79eebbc3267b6c595514d4ca1f3247Tim Northover NewMIB.addReg(CurReg, getUndefRegState(CurUndef)); 362089f49808ee79eebbc3267b6c595514d4ca1f3247Tim Northover 362189f49808ee79eebbc3267b6c595514d4ca1f3247Tim Northover CurReg = SrcLane == 0 && DstLane == 0 ? DSrc : DDst; 362289f49808ee79eebbc3267b6c595514d4ca1f3247Tim Northover CurUndef = !MI->readsRegister(CurReg, TRI); 362389f49808ee79eebbc3267b6c595514d4ca1f3247Tim Northover NewMIB.addReg(CurReg, getUndefRegState(CurUndef)); 362489f49808ee79eebbc3267b6c595514d4ca1f3247Tim Northover 3625c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover NewMIB.addImm(1); 3626c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover AddDefaultPred(NewMIB); 3627c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover 3628c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover if (SrcLane == DstLane) 3629c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover NewMIB.addReg(SrcReg, RegState::Implicit); 3630c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover 3631c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover MI->setDesc(get(ARM::VEXTd32)); 3632c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover MIB.addReg(DDst, RegState::Define); 363389f49808ee79eebbc3267b6c595514d4ca1f3247Tim Northover 363489f49808ee79eebbc3267b6c595514d4ca1f3247Tim Northover // On the second instruction, DDst has definitely been defined above, so 363589f49808ee79eebbc3267b6c595514d4ca1f3247Tim Northover // it is not <undef>. DSrc, if present, can be <undef> as above. 363689f49808ee79eebbc3267b6c595514d4ca1f3247Tim Northover CurReg = SrcLane == 1 && DstLane == 0 ? DSrc : DDst; 363789f49808ee79eebbc3267b6c595514d4ca1f3247Tim Northover CurUndef = CurReg == DSrc && !MI->readsRegister(CurReg, TRI); 363889f49808ee79eebbc3267b6c595514d4ca1f3247Tim Northover MIB.addReg(CurReg, getUndefRegState(CurUndef)); 363989f49808ee79eebbc3267b6c595514d4ca1f3247Tim Northover 364089f49808ee79eebbc3267b6c595514d4ca1f3247Tim Northover CurReg = SrcLane == 0 && DstLane == 1 ? DSrc : DDst; 364189f49808ee79eebbc3267b6c595514d4ca1f3247Tim Northover CurUndef = CurReg == DSrc && !MI->readsRegister(CurReg, TRI); 364289f49808ee79eebbc3267b6c595514d4ca1f3247Tim Northover MIB.addReg(CurReg, getUndefRegState(CurUndef)); 364389f49808ee79eebbc3267b6c595514d4ca1f3247Tim Northover 3644c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover MIB.addImm(1); 3645c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover AddDefaultPred(MIB); 3646c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover 3647c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover if (SrcLane != DstLane) 3648c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover MIB.addReg(SrcReg, RegState::Implicit); 3649c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover 3650c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover // As before, the original destination is no longer represented, add it 3651c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover // implicitly. 3652c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover MIB.addReg(DstReg, RegState::Define | RegState::Implicit); 365397ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy if (ImplicitSReg != 0) 365497ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy MIB.addReg(ImplicitSReg, RegState::Implicit); 3655c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover break; 3656c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover } 36573c8ad92455ff06c8e69085702ef1f13944eab4ddTim Northover } 36588bb3d3cb30df06bdcb3ef5a208e3e59f4eeb4868Jakob Stoklund Olesen 365913fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen} 3660c01810eeb7227010f73cb39e3c4fa0197a3c4ef0Jim Grosbach 3661c01810eeb7227010f73cb39e3c4fa0197a3c4ef0Jim Grosbachbool ARMBaseInstrInfo::hasNOP() const { 3662c01810eeb7227010f73cb39e3c4fa0197a3c4ef0Jim Grosbach return (Subtarget.getFeatureBits() & ARM::HasV6T2Ops) != 0; 3663c01810eeb7227010f73cb39e3c4fa0197a3c4ef0Jim Grosbach} 3664