ARMBaseInstrInfo.cpp revision 99405df044f2c584242e711cc9023ec90356da82
131c24bf5b39cc8391d4cfdbf8cf5163975fdb81eJim Grosbach//===- ARMBaseInstrInfo.cpp - ARM Instruction Information -------*- C++ -*-===// 2334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// 3334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// The LLVM Compiler Infrastructure 4334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// 5334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// This file is distributed under the University of Illinois Open Source 6334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// License. See LICENSE.TXT for details. 7334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// 8334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin//===----------------------------------------------------------------------===// 9334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// 10334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// This file contains the Base ARM implementation of the TargetInstrInfo class. 11334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// 12334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin//===----------------------------------------------------------------------===// 13334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 14334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "ARMBaseInstrInfo.h" 15334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "ARM.h" 16334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "ARMAddressingModes.h" 17d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng#include "ARMConstantPoolValue.h" 18334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "ARMGenInstrInfo.inc" 19334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "ARMMachineFunctionInfo.h" 20f95215f551949d5e5adfbf4753aa833b9009b77aAnton Korobeynikov#include "ARMRegisterInfo.h" 21fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng#include "llvm/Constants.h" 22fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng#include "llvm/Function.h" 23fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng#include "llvm/GlobalValue.h" 24334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "llvm/ADT/STLExtras.h" 25334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "llvm/CodeGen/LiveVariables.h" 26d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng#include "llvm/CodeGen/MachineConstantPool.h" 27334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "llvm/CodeGen/MachineFrameInfo.h" 28334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "llvm/CodeGen/MachineInstrBuilder.h" 29334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "llvm/CodeGen/MachineJumpTableInfo.h" 30249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov#include "llvm/CodeGen/MachineMemOperand.h" 312457f2c66184e978d4ed8fa9e2128effff26cb0bEvan Cheng#include "llvm/CodeGen/MachineRegisterInfo.h" 32249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov#include "llvm/CodeGen/PseudoSourceValue.h" 33af76e592c7f9deff0e55c13dbb4a34f07f1c7f64Chris Lattner#include "llvm/MC/MCAsmInfo.h" 34334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "llvm/Support/CommandLine.h" 35f95215f551949d5e5adfbf4753aa833b9009b77aAnton Korobeynikov#include "llvm/Support/Debug.h" 36c25e7581b9b8088910da31702d4ca21c4734c6d7Torok Edwin#include "llvm/Support/ErrorHandling.h" 37334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinusing namespace llvm; 38334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 39334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinstatic cl::opt<bool> 40334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinEnableARM3Addr("enable-arm-3-addr-conv", cl::Hidden, 41334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin cl::desc("Enable ARM 2-addr to 3-addr conv")); 42334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 43f95215f551949d5e5adfbf4753aa833b9009b77aAnton KorobeynikovARMBaseInstrInfo::ARMBaseInstrInfo(const ARMSubtarget& STI) 44f95215f551949d5e5adfbf4753aa833b9009b77aAnton Korobeynikov : TargetInstrInfoImpl(ARMInsts, array_lengthof(ARMInsts)), 45f95215f551949d5e5adfbf4753aa833b9009b77aAnton Korobeynikov Subtarget(STI) { 46334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 47334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 48334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinMachineInstr * 49334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinARMBaseInstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI, 50334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineBasicBlock::iterator &MBBI, 51334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin LiveVariables *LV) const { 5278703ddafe3d037f75d8ca188e4829d238289ac3Evan Cheng // FIXME: Thumb2 support. 5378703ddafe3d037f75d8ca188e4829d238289ac3Evan Cheng 54334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (!EnableARM3Addr) 55334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return NULL; 56334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 57334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineInstr *MI = MBBI; 58334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineFunction &MF = *MI->getParent()->getParent(); 5999405df044f2c584242e711cc9023ec90356da82Bruno Cardoso Lopes uint64_t TSFlags = MI->getDesc().TSFlags; 60334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool isPre = false; 61334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin switch ((TSFlags & ARMII::IndexModeMask) >> ARMII::IndexModeShift) { 62334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin default: return NULL; 63334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMII::IndexModePre: 64334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin isPre = true; 65334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin break; 66334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMII::IndexModePost: 67334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin break; 68334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 69334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 70334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Try splitting an indexed load/store to an un-indexed one plus an add/sub 71334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // operation. 72334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned MemOpc = getUnindexedOpcode(MI->getOpcode()); 73334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (MemOpc == 0) 74334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return NULL; 75334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 76334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineInstr *UpdateMI = NULL; 77334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineInstr *MemMI = NULL; 78334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned AddrMode = (TSFlags & ARMII::AddrModeMask); 79334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const TargetInstrDesc &TID = MI->getDesc(); 80334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned NumOps = TID.getNumOperands(); 81334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool isLoad = !TID.mayStore(); 82334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const MachineOperand &WB = isLoad ? MI->getOperand(1) : MI->getOperand(0); 83334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const MachineOperand &Base = MI->getOperand(2); 84334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const MachineOperand &Offset = MI->getOperand(NumOps-3); 85334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned WBReg = WB.getReg(); 86334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned BaseReg = Base.getReg(); 87334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned OffReg = Offset.getReg(); 88334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned OffImm = MI->getOperand(NumOps-2).getImm(); 89334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin ARMCC::CondCodes Pred = (ARMCC::CondCodes)MI->getOperand(NumOps-1).getImm(); 90334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin switch (AddrMode) { 91334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin default: 92334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin assert(false && "Unknown indexed op!"); 93334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return NULL; 94334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMII::AddrMode2: { 95334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool isSub = ARM_AM::getAM2Op(OffImm) == ARM_AM::sub; 96334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned Amt = ARM_AM::getAM2Offset(OffImm); 97334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (OffReg == 0) { 98e7cbe4118b7ddf05032ff8772a98c51e1637bb5cEvan Cheng if (ARM_AM::getSOImmVal(Amt) == -1) 99334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Can't encode it in a so_imm operand. This transformation will 100334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // add more than 1 instruction. Abandon! 101334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return NULL; 102334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin UpdateMI = BuildMI(MF, MI->getDebugLoc(), 10378703ddafe3d037f75d8ca188e4829d238289ac3Evan Cheng get(isSub ? ARM::SUBri : ARM::ADDri), WBReg) 104e7cbe4118b7ddf05032ff8772a98c51e1637bb5cEvan Cheng .addReg(BaseReg).addImm(Amt) 105334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addImm(Pred).addReg(0).addReg(0); 106334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } else if (Amt != 0) { 107334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin ARM_AM::ShiftOpc ShOpc = ARM_AM::getAM2ShiftOpc(OffImm); 108334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned SOOpc = ARM_AM::getSORegOpc(ShOpc, Amt); 109334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin UpdateMI = BuildMI(MF, MI->getDebugLoc(), 11078703ddafe3d037f75d8ca188e4829d238289ac3Evan Cheng get(isSub ? ARM::SUBrs : ARM::ADDrs), WBReg) 111334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(BaseReg).addReg(OffReg).addReg(0).addImm(SOOpc) 112334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addImm(Pred).addReg(0).addReg(0); 113334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } else 114334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin UpdateMI = BuildMI(MF, MI->getDebugLoc(), 11578703ddafe3d037f75d8ca188e4829d238289ac3Evan Cheng get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg) 116334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(BaseReg).addReg(OffReg) 117334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addImm(Pred).addReg(0).addReg(0); 118334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin break; 119334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 120334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMII::AddrMode3 : { 121334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool isSub = ARM_AM::getAM3Op(OffImm) == ARM_AM::sub; 122334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned Amt = ARM_AM::getAM3Offset(OffImm); 123334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (OffReg == 0) 124334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Immediate is 8-bits. It's guaranteed to fit in a so_imm operand. 125334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin UpdateMI = BuildMI(MF, MI->getDebugLoc(), 12678703ddafe3d037f75d8ca188e4829d238289ac3Evan Cheng get(isSub ? ARM::SUBri : ARM::ADDri), WBReg) 127334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(BaseReg).addImm(Amt) 128334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addImm(Pred).addReg(0).addReg(0); 129334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin else 130334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin UpdateMI = BuildMI(MF, MI->getDebugLoc(), 13178703ddafe3d037f75d8ca188e4829d238289ac3Evan Cheng get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg) 132334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(BaseReg).addReg(OffReg) 133334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addImm(Pred).addReg(0).addReg(0); 134334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin break; 135334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 136334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 137334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 138334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin std::vector<MachineInstr*> NewMIs; 139334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (isPre) { 140334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (isLoad) 141334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MemMI = BuildMI(MF, MI->getDebugLoc(), 142334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin get(MemOpc), MI->getOperand(0).getReg()) 143334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(WBReg).addReg(0).addImm(0).addImm(Pred); 144334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin else 145334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MemMI = BuildMI(MF, MI->getDebugLoc(), 146334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin get(MemOpc)).addReg(MI->getOperand(1).getReg()) 147334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(WBReg).addReg(0).addImm(0).addImm(Pred); 148334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin NewMIs.push_back(MemMI); 149334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin NewMIs.push_back(UpdateMI); 150334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } else { 151334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (isLoad) 152334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MemMI = BuildMI(MF, MI->getDebugLoc(), 153334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin get(MemOpc), MI->getOperand(0).getReg()) 154334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred); 155334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin else 156334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MemMI = BuildMI(MF, MI->getDebugLoc(), 157334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin get(MemOpc)).addReg(MI->getOperand(1).getReg()) 158334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred); 159334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (WB.isDead()) 160334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin UpdateMI->getOperand(0).setIsDead(); 161334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin NewMIs.push_back(UpdateMI); 162334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin NewMIs.push_back(MemMI); 163334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 164334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 165334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Transfer LiveVariables states, kill / dead info. 166334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (LV) { 167334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 168334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineOperand &MO = MI->getOperand(i); 169334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (MO.isReg() && MO.getReg() && 170334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin TargetRegisterInfo::isVirtualRegister(MO.getReg())) { 171334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned Reg = MO.getReg(); 172334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 173334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin LiveVariables::VarInfo &VI = LV->getVarInfo(Reg); 174334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (MO.isDef()) { 175334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineInstr *NewMI = (Reg == WBReg) ? UpdateMI : MemMI; 176334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (MO.isDead()) 177334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin LV->addVirtualRegisterDead(Reg, NewMI); 178334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 179334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (MO.isUse() && MO.isKill()) { 180334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin for (unsigned j = 0; j < 2; ++j) { 181334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Look at the two new MI's in reverse order. 182334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineInstr *NewMI = NewMIs[j]; 183334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (!NewMI->readsRegister(Reg)) 184334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin continue; 185334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin LV->addVirtualRegisterKilled(Reg, NewMI); 186334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (VI.removeKill(MI)) 187334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin VI.Kills.push_back(NewMI); 188334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin break; 189334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 190334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 191334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 192334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 193334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 194334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 195334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MFI->insert(MBBI, NewMIs[1]); 196334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MFI->insert(MBBI, NewMIs[0]); 197334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return NewMIs[0]; 198334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 199334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 2002457f2c66184e978d4ed8fa9e2128effff26cb0bEvan Chengbool 2012457f2c66184e978d4ed8fa9e2128effff26cb0bEvan ChengARMBaseInstrInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB, 20218f30e6f5e80787808fe1455742452a5210afe07Jim Grosbach MachineBasicBlock::iterator MI, 20318f30e6f5e80787808fe1455742452a5210afe07Jim Grosbach const std::vector<CalleeSavedInfo> &CSI, 20418f30e6f5e80787808fe1455742452a5210afe07Jim Grosbach const TargetRegisterInfo *TRI) const { 2052457f2c66184e978d4ed8fa9e2128effff26cb0bEvan Cheng if (CSI.empty()) 2062457f2c66184e978d4ed8fa9e2128effff26cb0bEvan Cheng return false; 2072457f2c66184e978d4ed8fa9e2128effff26cb0bEvan Cheng 2082457f2c66184e978d4ed8fa9e2128effff26cb0bEvan Cheng DebugLoc DL; 2092457f2c66184e978d4ed8fa9e2128effff26cb0bEvan Cheng if (MI != MBB.end()) DL = MI->getDebugLoc(); 2102457f2c66184e978d4ed8fa9e2128effff26cb0bEvan Cheng 2112457f2c66184e978d4ed8fa9e2128effff26cb0bEvan Cheng for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 2122457f2c66184e978d4ed8fa9e2128effff26cb0bEvan Cheng unsigned Reg = CSI[i].getReg(); 2132457f2c66184e978d4ed8fa9e2128effff26cb0bEvan Cheng bool isKill = true; 2142457f2c66184e978d4ed8fa9e2128effff26cb0bEvan Cheng 2152457f2c66184e978d4ed8fa9e2128effff26cb0bEvan Cheng // Add the callee-saved register as live-in unless it's LR and 2162457f2c66184e978d4ed8fa9e2128effff26cb0bEvan Cheng // @llvm.returnaddress is called. If LR is returned for @llvm.returnaddress 2172457f2c66184e978d4ed8fa9e2128effff26cb0bEvan Cheng // then it's already added to the function and entry block live-in sets. 2182457f2c66184e978d4ed8fa9e2128effff26cb0bEvan Cheng if (Reg == ARM::LR) { 2192457f2c66184e978d4ed8fa9e2128effff26cb0bEvan Cheng MachineFunction &MF = *MBB.getParent(); 2202457f2c66184e978d4ed8fa9e2128effff26cb0bEvan Cheng if (MF.getFrameInfo()->isReturnAddressTaken() && 2212457f2c66184e978d4ed8fa9e2128effff26cb0bEvan Cheng MF.getRegInfo().isLiveIn(Reg)) 2222457f2c66184e978d4ed8fa9e2128effff26cb0bEvan Cheng isKill = false; 2232457f2c66184e978d4ed8fa9e2128effff26cb0bEvan Cheng } 2242457f2c66184e978d4ed8fa9e2128effff26cb0bEvan Cheng 2252457f2c66184e978d4ed8fa9e2128effff26cb0bEvan Cheng if (isKill) 2262457f2c66184e978d4ed8fa9e2128effff26cb0bEvan Cheng MBB.addLiveIn(Reg); 2272457f2c66184e978d4ed8fa9e2128effff26cb0bEvan Cheng 2282457f2c66184e978d4ed8fa9e2128effff26cb0bEvan Cheng // Insert the spill to the stack frame. The register is killed at the spill 2292457f2c66184e978d4ed8fa9e2128effff26cb0bEvan Cheng // 23042d075c4fb21995265961501cec9ff6e3fb497ceRafael Espindola const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); 2312457f2c66184e978d4ed8fa9e2128effff26cb0bEvan Cheng storeRegToStackSlot(MBB, MI, Reg, isKill, 23242d075c4fb21995265961501cec9ff6e3fb497ceRafael Espindola CSI[i].getFrameIdx(), RC, TRI); 2332457f2c66184e978d4ed8fa9e2128effff26cb0bEvan Cheng } 2342457f2c66184e978d4ed8fa9e2128effff26cb0bEvan Cheng return true; 2352457f2c66184e978d4ed8fa9e2128effff26cb0bEvan Cheng} 2362457f2c66184e978d4ed8fa9e2128effff26cb0bEvan Cheng 237334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// Branch analysis. 238334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinbool 239334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinARMBaseInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB, 240334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineBasicBlock *&FBB, 241334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin SmallVectorImpl<MachineOperand> &Cond, 242334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool AllowModify) const { 243334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // If the block has no terminators, it just falls into the block after it. 244334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineBasicBlock::iterator I = MBB.end(); 24593d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen if (I == MBB.begin()) 24693d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen return false; 24793d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen --I; 24893d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen while (I->isDebugValue()) { 24993d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen if (I == MBB.begin()) 25093d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen return false; 25193d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen --I; 25293d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen } 25393d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen if (!isUnpredicatedTerminator(I)) 254334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 255334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 256334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Get the last instruction in the block. 257334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineInstr *LastInst = I; 258334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 259334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // If there is only one terminator instruction, process it. 260334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned LastOpc = LastInst->getOpcode(); 261334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) { 2625ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng if (isUncondBranchOpcode(LastOpc)) { 263334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin TBB = LastInst->getOperand(0).getMBB(); 264334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 265334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 2665ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng if (isCondBranchOpcode(LastOpc)) { 267334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Block ends with fall-through condbranch. 268334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin TBB = LastInst->getOperand(0).getMBB(); 269334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin Cond.push_back(LastInst->getOperand(1)); 270334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin Cond.push_back(LastInst->getOperand(2)); 271334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 272334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 273334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; // Can't handle indirect branch. 274334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 275334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 276334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Get the instruction before it if it is a terminator. 277334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineInstr *SecondLastInst = I; 278334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 279334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // If there are three terminators, we don't know what sort of block this is. 280334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(--I)) 281334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; 282334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 2835ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng // If the block ends with a B and a Bcc, handle it. 284334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned SecondLastOpc = SecondLastInst->getOpcode(); 2855ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng if (isCondBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) { 286334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin TBB = SecondLastInst->getOperand(0).getMBB(); 287334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin Cond.push_back(SecondLastInst->getOperand(1)); 288334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin Cond.push_back(SecondLastInst->getOperand(2)); 289334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin FBB = LastInst->getOperand(0).getMBB(); 290334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 291334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 292334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 293334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // If the block ends with two unconditional branches, handle it. The second 294334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // one is not executed, so remove it. 2955ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng if (isUncondBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) { 296334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin TBB = SecondLastInst->getOperand(0).getMBB(); 297334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin I = LastInst; 298334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (AllowModify) 299334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin I->eraseFromParent(); 300334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 301334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 302334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 303334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // ...likewise if it ends with a branch table followed by an unconditional 304334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // branch. The branch folder can create these, and we must get rid of them for 305334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // correctness of Thumb constant islands. 3068d4de5abfa1bcd974554ea14904ebf7af289e84dBob Wilson if ((isJumpTableBranchOpcode(SecondLastOpc) || 3078d4de5abfa1bcd974554ea14904ebf7af289e84dBob Wilson isIndirectBranchOpcode(SecondLastOpc)) && 3085ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng isUncondBranchOpcode(LastOpc)) { 309334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin I = LastInst; 310334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (AllowModify) 311334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin I->eraseFromParent(); 312334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; 313334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 314334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 315334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Otherwise, can't handle this. 316334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; 317334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 318334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 319334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 320334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinunsigned ARMBaseInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const { 321334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineBasicBlock::iterator I = MBB.end(); 322334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (I == MBB.begin()) return 0; 323334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin --I; 32493d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen while (I->isDebugValue()) { 32593d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen if (I == MBB.begin()) 32693d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen return 0; 32793d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen --I; 32893d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen } 3295ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng if (!isUncondBranchOpcode(I->getOpcode()) && 3305ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng !isCondBranchOpcode(I->getOpcode())) 331334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 0; 332334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 333334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Remove the branch. 334334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin I->eraseFromParent(); 335334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 336334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin I = MBB.end(); 337334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 338334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (I == MBB.begin()) return 1; 339334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin --I; 3405ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng if (!isCondBranchOpcode(I->getOpcode())) 341334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 1; 342334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 343334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Remove the branch. 344334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin I->eraseFromParent(); 345334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 2; 346334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 347334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 348334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinunsigned 349334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinARMBaseInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 35018f30e6f5e80787808fe1455742452a5210afe07Jim Grosbach MachineBasicBlock *FBB, 35118f30e6f5e80787808fe1455742452a5210afe07Jim Grosbach const SmallVectorImpl<MachineOperand> &Cond) const { 352334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // FIXME this should probably have a DebugLoc argument 353c7f3ace20c325521c68335a1689645b43b06ddf0Chris Lattner DebugLoc dl; 3546495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 3556495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ARMFunctionInfo *AFI = MBB.getParent()->getInfo<ARMFunctionInfo>(); 3566495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng int BOpc = !AFI->isThumbFunction() 3576495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ? ARM::B : (AFI->isThumb2Function() ? ARM::t2B : ARM::tB); 3586495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng int BccOpc = !AFI->isThumbFunction() 3596495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ? ARM::Bcc : (AFI->isThumb2Function() ? ARM::t2Bcc : ARM::tBcc); 360334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 361334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Shouldn't be a fall through. 362334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin assert(TBB && "InsertBranch must not be told to insert a fallthrough"); 363334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin assert((Cond.size() == 2 || Cond.size() == 0) && 364334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin "ARM branch conditions have two components!"); 365334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 366334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (FBB == 0) { 367334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (Cond.empty()) // Unconditional branch? 368334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin BuildMI(&MBB, dl, get(BOpc)).addMBB(TBB); 369334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin else 370334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin BuildMI(&MBB, dl, get(BccOpc)).addMBB(TBB) 371334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()); 372334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 1; 373334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 374334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 375334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Two-way conditional branch. 376334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin BuildMI(&MBB, dl, get(BccOpc)).addMBB(TBB) 377334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()); 378334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin BuildMI(&MBB, dl, get(BOpc)).addMBB(FBB); 379334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 2; 380334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 381334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 382334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinbool ARMBaseInstrInfo:: 383334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const { 384334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin ARMCC::CondCodes CC = (ARMCC::CondCodes)(int)Cond[0].getImm(); 385334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin Cond[0].setImm(ARMCC::getOppositeCondition(CC)); 386334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 387334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 388334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 389334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinbool ARMBaseInstrInfo:: 390334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinPredicateInstruction(MachineInstr *MI, 391334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const SmallVectorImpl<MachineOperand> &Pred) const { 392334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned Opc = MI->getOpcode(); 3935ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng if (isUncondBranchOpcode(Opc)) { 3945ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng MI->setDesc(get(getMatchingCondBranchOpcode(Opc))); 395334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI->addOperand(MachineOperand::CreateImm(Pred[0].getImm())); 396334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI->addOperand(MachineOperand::CreateReg(Pred[1].getReg(), false)); 397334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; 398334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 399334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 400334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin int PIdx = MI->findFirstPredOperandIdx(); 401334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (PIdx != -1) { 402334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineOperand &PMO = MI->getOperand(PIdx); 403334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin PMO.setImm(Pred[0].getImm()); 404334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI->getOperand(PIdx+1).setReg(Pred[1].getReg()); 405334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; 406334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 407334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 408334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 409334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 410334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinbool ARMBaseInstrInfo:: 411334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinSubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1, 412334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const SmallVectorImpl<MachineOperand> &Pred2) const { 413334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (Pred1.size() > 2 || Pred2.size() > 2) 414334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 415334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 416334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin ARMCC::CondCodes CC1 = (ARMCC::CondCodes)Pred1[0].getImm(); 417334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin ARMCC::CondCodes CC2 = (ARMCC::CondCodes)Pred2[0].getImm(); 418334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (CC1 == CC2) 419334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; 420334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 421334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin switch (CC1) { 422334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin default: 423334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 424334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMCC::AL: 425334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; 426334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMCC::HS: 427334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return CC2 == ARMCC::HI; 428334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMCC::LS: 429334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return CC2 == ARMCC::LO || CC2 == ARMCC::EQ; 430334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMCC::GE: 431334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return CC2 == ARMCC::GT; 432334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMCC::LE: 433334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return CC2 == ARMCC::LT; 434334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 435334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 436334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 437334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinbool ARMBaseInstrInfo::DefinesPredicate(MachineInstr *MI, 438334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin std::vector<MachineOperand> &Pred) const { 4398fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng // FIXME: This confuses implicit_def with optional CPSR def. 440334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const TargetInstrDesc &TID = MI->getDesc(); 441334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (!TID.getImplicitDefs() && !TID.hasOptionalDef()) 442334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 443334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 444334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool Found = false; 445334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 446334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const MachineOperand &MO = MI->getOperand(i); 447334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (MO.isReg() && MO.getReg() == ARM::CPSR) { 448334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin Pred.push_back(MO); 449334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin Found = true; 450334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 451334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 452334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 453334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return Found; 454334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 455334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 456ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng/// isPredicable - Return true if the specified instruction can be predicated. 457ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng/// By default, this returns true for every instruction with a 458ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng/// PredicateOperand. 459ac0869dc8a7986855c5557cc67d4709600158ef5Evan Chengbool ARMBaseInstrInfo::isPredicable(MachineInstr *MI) const { 460ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng const TargetInstrDesc &TID = MI->getDesc(); 461ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng if (!TID.isPredicable()) 462ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng return false; 463ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng 464ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng if ((TID.TSFlags & ARMII::DomainMask) == ARMII::DomainNEON) { 465ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng ARMFunctionInfo *AFI = 466ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng MI->getParent()->getParent()->getInfo<ARMFunctionInfo>(); 467d7f0810c934a7d13acb28c42d737ce58ec990ea8Evan Cheng return AFI->isThumb2Function(); 468ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng } 469ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng return true; 470ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng} 471334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 47256856b1f46ec1f073ceef4e826c544b8b1691608Chris Lattner/// FIXME: Works around a gcc miscompilation with -fstrict-aliasing. 47356856b1f46ec1f073ceef4e826c544b8b1691608Chris LattnerDISABLE_INLINE 474334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinstatic unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT, 47556856b1f46ec1f073ceef4e826c544b8b1691608Chris Lattner unsigned JTI); 476334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinstatic unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT, 477334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned JTI) { 47856856b1f46ec1f073ceef4e826c544b8b1691608Chris Lattner assert(JTI < JT.size()); 479334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return JT[JTI].MBBs.size(); 480334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 481334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 482334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin/// GetInstSize - Return the size of the specified MachineInstr. 483334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin/// 484334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinunsigned ARMBaseInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const { 485334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const MachineBasicBlock &MBB = *MI->getParent(); 486334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const MachineFunction *MF = MBB.getParent(); 48733adcfb4d217f5f23d9bde8ba02b8e48f9605fc5Chris Lattner const MCAsmInfo *MAI = MF->getTarget().getMCAsmInfo(); 488334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 489334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Basic size info comes from the TSFlags field. 490334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const TargetInstrDesc &TID = MI->getDesc(); 49199405df044f2c584242e711cc9023ec90356da82Bruno Cardoso Lopes uint64_t TSFlags = TID.TSFlags; 492334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 493a0ee862f2e3a0d202244e02459ddcf0dca0e8607Evan Cheng unsigned Opc = MI->getOpcode(); 494334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin switch ((TSFlags & ARMII::SizeMask) >> ARMII::SizeShift) { 495334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin default: { 496334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // If this machine instr is an inline asm, measure it. 497334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (MI->getOpcode() == ARM::INLINEASM) 49833adcfb4d217f5f23d9bde8ba02b8e48f9605fc5Chris Lattner return getInlineAsmLength(MI->getOperand(0).getSymbolName(), *MAI); 499334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (MI->isLabel()) 500334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 0; 501a0ee862f2e3a0d202244e02459ddcf0dca0e8607Evan Cheng switch (Opc) { 502334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin default: 503c23197a26f34f559ea9797de51e187087c039c42Torok Edwin llvm_unreachable("Unknown or unset size field for instr!"); 504518bb53485df640d7b7e3f6b0544099020c42aa7Chris Lattner case TargetOpcode::IMPLICIT_DEF: 505518bb53485df640d7b7e3f6b0544099020c42aa7Chris Lattner case TargetOpcode::KILL: 506518bb53485df640d7b7e3f6b0544099020c42aa7Chris Lattner case TargetOpcode::DBG_LABEL: 507518bb53485df640d7b7e3f6b0544099020c42aa7Chris Lattner case TargetOpcode::EH_LABEL: 508375be7730a6f3dee7a6dc319ee6c355a11ac99adDale Johannesen case TargetOpcode::DBG_VALUE: 509334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 0; 510334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 511334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin break; 512334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 513789476240d6b6f8ad9366cadf790a82bd41bb0b3Evan Cheng case ARMII::Size8Bytes: return 8; // ARM instruction x 2. 514789476240d6b6f8ad9366cadf790a82bd41bb0b3Evan Cheng case ARMII::Size4Bytes: return 4; // ARM / Thumb2 instruction. 515789476240d6b6f8ad9366cadf790a82bd41bb0b3Evan Cheng case ARMII::Size2Bytes: return 2; // Thumb1 instruction. 516334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMII::SizeSpecial: { 517a0ee862f2e3a0d202244e02459ddcf0dca0e8607Evan Cheng switch (Opc) { 518334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARM::CONSTPOOL_ENTRY: 519334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // If this machine instr is a constant pool entry, its size is recorded as 520334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // operand #2. 521334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return MI->getOperand(2).getImm(); 5225eb195153950bc7ebfc30649494a78b2096b5ef8Jim Grosbach case ARM::Int_eh_sjlj_longjmp: 5235eb195153950bc7ebfc30649494a78b2096b5ef8Jim Grosbach return 16; 5245eb195153950bc7ebfc30649494a78b2096b5ef8Jim Grosbach case ARM::tInt_eh_sjlj_longjmp: 5255eb195153950bc7ebfc30649494a78b2096b5ef8Jim Grosbach return 10; 526789476240d6b6f8ad9366cadf790a82bd41bb0b3Evan Cheng case ARM::Int_eh_sjlj_setjmp: 527d100755bab38784703f677b8b8eb174b624b346bJim Grosbach case ARM::Int_eh_sjlj_setjmp_nofp: 5280798eddd07b8dc827a4e6e9028c4c3a8d9444286Jim Grosbach return 20; 529d122874996a6faa8832569b632fd73a32ace7ae7Jim Grosbach case ARM::tInt_eh_sjlj_setjmp: 5305aa1684e5da9a85286bf7d29da419d261a70c2f2Jim Grosbach case ARM::t2Int_eh_sjlj_setjmp: 531d100755bab38784703f677b8b8eb174b624b346bJim Grosbach case ARM::t2Int_eh_sjlj_setjmp_nofp: 5320798eddd07b8dc827a4e6e9028c4c3a8d9444286Jim Grosbach return 12; 533334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARM::BR_JTr: 534334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARM::BR_JTm: 535334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARM::BR_JTadd: 536a0ee862f2e3a0d202244e02459ddcf0dca0e8607Evan Cheng case ARM::tBR_JTr: 537d26b14c34cbcee1448b86b524578fc51cc979023Evan Cheng case ARM::t2BR_JT: 538d26b14c34cbcee1448b86b524578fc51cc979023Evan Cheng case ARM::t2TBB: 539d26b14c34cbcee1448b86b524578fc51cc979023Evan Cheng case ARM::t2TBH: { 540334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // These are jumptable branches, i.e. a branch followed by an inlined 541d26b14c34cbcee1448b86b524578fc51cc979023Evan Cheng // jumptable. The size is 4 + 4 * number of entries. For TBB, each 542d26b14c34cbcee1448b86b524578fc51cc979023Evan Cheng // entry is one byte; TBH two byte each. 543a0ee862f2e3a0d202244e02459ddcf0dca0e8607Evan Cheng unsigned EntrySize = (Opc == ARM::t2TBB) 544a0ee862f2e3a0d202244e02459ddcf0dca0e8607Evan Cheng ? 1 : ((Opc == ARM::t2TBH) ? 2 : 4); 545334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned NumOps = TID.getNumOperands(); 546334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineOperand JTOP = 547334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI->getOperand(NumOps - (TID.isPredicable() ? 3 : 2)); 548334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned JTI = JTOP.getIndex(); 549334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo(); 550b1e803985d3378538ae9cff7eed4102c002d1e22Chris Lattner assert(MJTI != 0); 551334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables(); 552334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin assert(JTI < JT.size()); 553334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Thumb instructions are 2 byte aligned, but JT entries are 4 byte 554334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // 4 aligned. The assembler / linker may add 2 byte padding just before 555334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // the JT entries. The size does not include this padding; the 556334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // constant islands pass does separate bookkeeping for it. 557334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // FIXME: If we know the size of the function is less than (1 << 16) *2 558334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // bytes, we can use 16-bit entries instead. Then there won't be an 559334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // alignment issue. 56025f7cfc3cccba6f569f29f79ea533bae960b93c0Evan Cheng unsigned InstSize = (Opc == ARM::tBR_JTr || Opc == ARM::t2BR_JT) ? 2 : 4; 56125f7cfc3cccba6f569f29f79ea533bae960b93c0Evan Cheng unsigned NumEntries = getNumJTEntries(JT, JTI); 56225f7cfc3cccba6f569f29f79ea533bae960b93c0Evan Cheng if (Opc == ARM::t2TBB && (NumEntries & 1)) 56325f7cfc3cccba6f569f29f79ea533bae960b93c0Evan Cheng // Make sure the instruction that follows TBB is 2-byte aligned. 56425f7cfc3cccba6f569f29f79ea533bae960b93c0Evan Cheng // FIXME: Constant island pass should insert an "ALIGN" instruction 56525f7cfc3cccba6f569f29f79ea533bae960b93c0Evan Cheng // instead. 56625f7cfc3cccba6f569f29f79ea533bae960b93c0Evan Cheng ++NumEntries; 56725f7cfc3cccba6f569f29f79ea533bae960b93c0Evan Cheng return NumEntries * EntrySize + InstSize; 568334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 569334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin default: 570334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Otherwise, pseudo-instruction sizes are zero. 571334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 0; 572334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 573334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 574334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 575334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 0; // Not reached 576334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 577334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 578334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin/// Return true if the instruction is a register to register move and 579334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin/// leave the source and dest operands in the passed parameters. 580334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin/// 581334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinbool 582334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinARMBaseInstrInfo::isMoveInstr(const MachineInstr &MI, 583334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned &SrcReg, unsigned &DstReg, 584334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned& SrcSubIdx, unsigned& DstSubIdx) const { 58568e3c6ae49ff67cba98403e43b5bd0c2499caa41Evan Cheng switch (MI.getOpcode()) { 586dced03fc846fa7cd9558ecb8e33ca98ec29bdcf0Evan Cheng default: break; 587e5165490b7ba24bb2f3043399e0d60e7f3bcf8a5Jim Grosbach case ARM::VMOVS: 58868e3c6ae49ff67cba98403e43b5bd0c2499caa41Evan Cheng case ARM::VMOVD: 589e5165490b7ba24bb2f3043399e0d60e7f3bcf8a5Jim Grosbach case ARM::VMOVDneon: 590b63387afc6b10e88631d1ef232c41ab6c18c8581Evan Cheng case ARM::VMOVQ: 591b63387afc6b10e88631d1ef232c41ab6c18c8581Evan Cheng case ARM::VMOVQQ : { 592334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin SrcReg = MI.getOperand(1).getReg(); 593334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin DstReg = MI.getOperand(0).getReg(); 594b63387afc6b10e88631d1ef232c41ab6c18c8581Evan Cheng SrcSubIdx = MI.getOperand(1).getSubReg(); 595b63387afc6b10e88631d1ef232c41ab6c18c8581Evan Cheng DstSubIdx = MI.getOperand(0).getSubReg(); 596334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; 597334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 59868e3c6ae49ff67cba98403e43b5bd0c2499caa41Evan Cheng case ARM::MOVr: 59968e3c6ae49ff67cba98403e43b5bd0c2499caa41Evan Cheng case ARM::tMOVr: 60068e3c6ae49ff67cba98403e43b5bd0c2499caa41Evan Cheng case ARM::tMOVgpr2tgpr: 60168e3c6ae49ff67cba98403e43b5bd0c2499caa41Evan Cheng case ARM::tMOVtgpr2gpr: 60268e3c6ae49ff67cba98403e43b5bd0c2499caa41Evan Cheng case ARM::tMOVgpr2gpr: 60368e3c6ae49ff67cba98403e43b5bd0c2499caa41Evan Cheng case ARM::t2MOVr: { 604334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin assert(MI.getDesc().getNumOperands() >= 2 && 605334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI.getOperand(0).isReg() && 606334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI.getOperand(1).isReg() && 607334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin "Invalid ARM MOV instruction"); 608334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin SrcReg = MI.getOperand(1).getReg(); 609334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin DstReg = MI.getOperand(0).getReg(); 610b63387afc6b10e88631d1ef232c41ab6c18c8581Evan Cheng SrcSubIdx = MI.getOperand(1).getSubReg(); 611b63387afc6b10e88631d1ef232c41ab6c18c8581Evan Cheng DstSubIdx = MI.getOperand(0).getSubReg(); 612334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; 613334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 61468e3c6ae49ff67cba98403e43b5bd0c2499caa41Evan Cheng } 615334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 616334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 617334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 618334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 619764ab52dd80310a205c9888bf166d09dab858f90Jim Grosbachunsigned 620334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinARMBaseInstrInfo::isLoadFromStackSlot(const MachineInstr *MI, 621334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin int &FrameIndex) const { 622dced03fc846fa7cd9558ecb8e33ca98ec29bdcf0Evan Cheng switch (MI->getOpcode()) { 623dced03fc846fa7cd9558ecb8e33ca98ec29bdcf0Evan Cheng default: break; 624dced03fc846fa7cd9558ecb8e33ca98ec29bdcf0Evan Cheng case ARM::LDR: 625dced03fc846fa7cd9558ecb8e33ca98ec29bdcf0Evan Cheng case ARM::t2LDRs: // FIXME: don't use t2LDRs to access frame. 626334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (MI->getOperand(1).isFI() && 627334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI->getOperand(2).isReg() && 628334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI->getOperand(3).isImm() && 629334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI->getOperand(2).getReg() == 0 && 630334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI->getOperand(3).getImm() == 0) { 631334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin FrameIndex = MI->getOperand(1).getIndex(); 632334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return MI->getOperand(0).getReg(); 633334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 634dced03fc846fa7cd9558ecb8e33ca98ec29bdcf0Evan Cheng break; 635dced03fc846fa7cd9558ecb8e33ca98ec29bdcf0Evan Cheng case ARM::t2LDRi12: 636dced03fc846fa7cd9558ecb8e33ca98ec29bdcf0Evan Cheng case ARM::tRestore: 6375ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin if (MI->getOperand(1).isFI() && 6385ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin MI->getOperand(2).isImm() && 6395ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin MI->getOperand(2).getImm() == 0) { 6405ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin FrameIndex = MI->getOperand(1).getIndex(); 6415ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin return MI->getOperand(0).getReg(); 6425ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin } 643dced03fc846fa7cd9558ecb8e33ca98ec29bdcf0Evan Cheng break; 644e5165490b7ba24bb2f3043399e0d60e7f3bcf8a5Jim Grosbach case ARM::VLDRD: 645e5165490b7ba24bb2f3043399e0d60e7f3bcf8a5Jim Grosbach case ARM::VLDRS: 646334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (MI->getOperand(1).isFI() && 647334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI->getOperand(2).isImm() && 648334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI->getOperand(2).getImm() == 0) { 649334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin FrameIndex = MI->getOperand(1).getIndex(); 650334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return MI->getOperand(0).getReg(); 651334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 652dced03fc846fa7cd9558ecb8e33ca98ec29bdcf0Evan Cheng break; 653334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 654334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 655334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 0; 656334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 657334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 658334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinunsigned 659334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinARMBaseInstrInfo::isStoreToStackSlot(const MachineInstr *MI, 660334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin int &FrameIndex) const { 661dced03fc846fa7cd9558ecb8e33ca98ec29bdcf0Evan Cheng switch (MI->getOpcode()) { 662dced03fc846fa7cd9558ecb8e33ca98ec29bdcf0Evan Cheng default: break; 663dced03fc846fa7cd9558ecb8e33ca98ec29bdcf0Evan Cheng case ARM::STR: 664dced03fc846fa7cd9558ecb8e33ca98ec29bdcf0Evan Cheng case ARM::t2STRs: // FIXME: don't use t2STRs to access frame. 665334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (MI->getOperand(1).isFI() && 666334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI->getOperand(2).isReg() && 667334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI->getOperand(3).isImm() && 668334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI->getOperand(2).getReg() == 0 && 669334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI->getOperand(3).getImm() == 0) { 670334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin FrameIndex = MI->getOperand(1).getIndex(); 671334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return MI->getOperand(0).getReg(); 672334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 673dced03fc846fa7cd9558ecb8e33ca98ec29bdcf0Evan Cheng break; 674dced03fc846fa7cd9558ecb8e33ca98ec29bdcf0Evan Cheng case ARM::t2STRi12: 675dced03fc846fa7cd9558ecb8e33ca98ec29bdcf0Evan Cheng case ARM::tSpill: 6765ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin if (MI->getOperand(1).isFI() && 6775ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin MI->getOperand(2).isImm() && 6785ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin MI->getOperand(2).getImm() == 0) { 6795ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin FrameIndex = MI->getOperand(1).getIndex(); 6805ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin return MI->getOperand(0).getReg(); 6815ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin } 682dced03fc846fa7cd9558ecb8e33ca98ec29bdcf0Evan Cheng break; 683e5165490b7ba24bb2f3043399e0d60e7f3bcf8a5Jim Grosbach case ARM::VSTRD: 684e5165490b7ba24bb2f3043399e0d60e7f3bcf8a5Jim Grosbach case ARM::VSTRS: 685334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (MI->getOperand(1).isFI() && 686334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI->getOperand(2).isImm() && 687334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI->getOperand(2).getImm() == 0) { 688334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin FrameIndex = MI->getOperand(1).getIndex(); 689334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return MI->getOperand(0).getReg(); 690334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 691dced03fc846fa7cd9558ecb8e33ca98ec29bdcf0Evan Cheng break; 692334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 693334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 694334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 0; 695334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 696334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 697334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinbool 698334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinARMBaseInstrInfo::copyRegToReg(MachineBasicBlock &MBB, 699334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineBasicBlock::iterator I, 700334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned DestReg, unsigned SrcReg, 701334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const TargetRegisterClass *DestRC, 70234dcc6fadca0a1117cdbd0e9b35c991a55b6e556Dan Gohman const TargetRegisterClass *SrcRC, 70334dcc6fadca0a1117cdbd0e9b35c991a55b6e556Dan Gohman DebugLoc DL) const { 7041665b0a2246c83a2c123be105a1a167cf2b423feBob Wilson // tGPR is used sometimes in ARM instructions that need to avoid using 7051665b0a2246c83a2c123be105a1a167cf2b423feBob Wilson // certain registers. Just treat it as GPR here. 7061665b0a2246c83a2c123be105a1a167cf2b423feBob Wilson if (DestRC == ARM::tGPRRegisterClass) 7071665b0a2246c83a2c123be105a1a167cf2b423feBob Wilson DestRC = ARM::GPRRegisterClass; 7081665b0a2246c83a2c123be105a1a167cf2b423feBob Wilson if (SrcRC == ARM::tGPRRegisterClass) 7091665b0a2246c83a2c123be105a1a167cf2b423feBob Wilson SrcRC = ARM::GPRRegisterClass; 7101665b0a2246c83a2c123be105a1a167cf2b423feBob Wilson 7116755d97a62fd6796f4146833efb1051fc96a61c0Anton Korobeynikov // Allow DPR / DPR_VFP2 / DPR_8 cross-class copies. 7126755d97a62fd6796f4146833efb1051fc96a61c0Anton Korobeynikov if (DestRC == ARM::DPR_8RegisterClass) 7136755d97a62fd6796f4146833efb1051fc96a61c0Anton Korobeynikov DestRC = ARM::DPR_VFP2RegisterClass; 7146755d97a62fd6796f4146833efb1051fc96a61c0Anton Korobeynikov if (SrcRC == ARM::DPR_8RegisterClass) 7156755d97a62fd6796f4146833efb1051fc96a61c0Anton Korobeynikov SrcRC = ARM::DPR_VFP2RegisterClass; 7166755d97a62fd6796f4146833efb1051fc96a61c0Anton Korobeynikov 7176755d97a62fd6796f4146833efb1051fc96a61c0Anton Korobeynikov // Allow QPR / QPR_VFP2 / QPR_8 cross-class copies. 7186755d97a62fd6796f4146833efb1051fc96a61c0Anton Korobeynikov if (DestRC == ARM::QPR_VFP2RegisterClass || 7196755d97a62fd6796f4146833efb1051fc96a61c0Anton Korobeynikov DestRC == ARM::QPR_8RegisterClass) 7206755d97a62fd6796f4146833efb1051fc96a61c0Anton Korobeynikov DestRC = ARM::QPRRegisterClass; 7216755d97a62fd6796f4146833efb1051fc96a61c0Anton Korobeynikov if (SrcRC == ARM::QPR_VFP2RegisterClass || 7226755d97a62fd6796f4146833efb1051fc96a61c0Anton Korobeynikov SrcRC == ARM::QPR_8RegisterClass) 7236755d97a62fd6796f4146833efb1051fc96a61c0Anton Korobeynikov SrcRC = ARM::QPRRegisterClass; 7246755d97a62fd6796f4146833efb1051fc96a61c0Anton Korobeynikov 72522c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng // Allow QQPR / QQPR_VFP2 cross-class copies. 72622c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng if (DestRC == ARM::QQPR_VFP2RegisterClass) 727b63387afc6b10e88631d1ef232c41ab6c18c8581Evan Cheng DestRC = ARM::QQPRRegisterClass; 72822c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng if (SrcRC == ARM::QQPR_VFP2RegisterClass) 729b63387afc6b10e88631d1ef232c41ab6c18c8581Evan Cheng SrcRC = ARM::QQPRRegisterClass; 730b63387afc6b10e88631d1ef232c41ab6c18c8581Evan Cheng 7316755d97a62fd6796f4146833efb1051fc96a61c0Anton Korobeynikov // Disallow copies of unequal sizes. 7326755d97a62fd6796f4146833efb1051fc96a61c0Anton Korobeynikov if (DestRC != SrcRC && DestRC->getSize() != SrcRC->getSize()) 7336755d97a62fd6796f4146833efb1051fc96a61c0Anton Korobeynikov return false; 734b4db6a46e0de3283fa70ea0a7d3623f2e4e2d2a3Evan Cheng 7356755d97a62fd6796f4146833efb1051fc96a61c0Anton Korobeynikov if (DestRC == ARM::GPRRegisterClass) { 7366755d97a62fd6796f4146833efb1051fc96a61c0Anton Korobeynikov if (SrcRC == ARM::SPRRegisterClass) 7376755d97a62fd6796f4146833efb1051fc96a61c0Anton Korobeynikov AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VMOVRS), DestReg) 7386755d97a62fd6796f4146833efb1051fc96a61c0Anton Korobeynikov .addReg(SrcReg)); 7396755d97a62fd6796f4146833efb1051fc96a61c0Anton Korobeynikov else 7406755d97a62fd6796f4146833efb1051fc96a61c0Anton Korobeynikov AddDefaultCC(AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::MOVr), 7416755d97a62fd6796f4146833efb1051fc96a61c0Anton Korobeynikov DestReg).addReg(SrcReg))); 7426755d97a62fd6796f4146833efb1051fc96a61c0Anton Korobeynikov } else { 7436755d97a62fd6796f4146833efb1051fc96a61c0Anton Korobeynikov unsigned Opc; 7446755d97a62fd6796f4146833efb1051fc96a61c0Anton Korobeynikov 7456755d97a62fd6796f4146833efb1051fc96a61c0Anton Korobeynikov if (DestRC == ARM::SPRRegisterClass) 7466755d97a62fd6796f4146833efb1051fc96a61c0Anton Korobeynikov Opc = (SrcRC == ARM::GPRRegisterClass ? ARM::VMOVSR : ARM::VMOVS); 7476755d97a62fd6796f4146833efb1051fc96a61c0Anton Korobeynikov else if (DestRC == ARM::DPRRegisterClass) 7486755d97a62fd6796f4146833efb1051fc96a61c0Anton Korobeynikov Opc = ARM::VMOVD; 7496755d97a62fd6796f4146833efb1051fc96a61c0Anton Korobeynikov else if (DestRC == ARM::DPR_VFP2RegisterClass || 7506755d97a62fd6796f4146833efb1051fc96a61c0Anton Korobeynikov SrcRC == ARM::DPR_VFP2RegisterClass) 7516755d97a62fd6796f4146833efb1051fc96a61c0Anton Korobeynikov // Always use neon reg-reg move if source or dest is NEON-only regclass. 7526755d97a62fd6796f4146833efb1051fc96a61c0Anton Korobeynikov Opc = ARM::VMOVDneon; 7536755d97a62fd6796f4146833efb1051fc96a61c0Anton Korobeynikov else if (DestRC == ARM::QPRRegisterClass) 7546755d97a62fd6796f4146833efb1051fc96a61c0Anton Korobeynikov Opc = ARM::VMOVQ; 755b63387afc6b10e88631d1ef232c41ab6c18c8581Evan Cheng else if (DestRC == ARM::QQPRRegisterClass) 756b63387afc6b10e88631d1ef232c41ab6c18c8581Evan Cheng Opc = ARM::VMOVQQ; 75722c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng else if (DestRC == ARM::QQQQPRRegisterClass) 75822c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng Opc = ARM::VMOVQQQQ; 7596755d97a62fd6796f4146833efb1051fc96a61c0Anton Korobeynikov else 7607bfdca0206f51132b26094c6f83a5ac97ee0f943David Goodwin return false; 761334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 762b63387afc6b10e88631d1ef232c41ab6c18c8581Evan Cheng AddDefaultPred(BuildMI(MBB, I, DL, get(Opc), DestReg).addReg(SrcReg)); 7637bfdca0206f51132b26094c6f83a5ac97ee0f943David Goodwin } 764334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 765334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; 766334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 767334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 768c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Chengstatic const 769c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan ChengMachineInstrBuilder &AddDReg(MachineInstrBuilder &MIB, 770c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Cheng unsigned Reg, unsigned SubIdx, unsigned State, 771c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Cheng const TargetRegisterInfo *TRI) { 772c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Cheng if (!SubIdx) 773c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Cheng return MIB.addReg(Reg, State); 774c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Cheng 775c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Cheng if (TargetRegisterInfo::isPhysicalRegister(Reg)) 776c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Cheng return MIB.addReg(TRI->getSubReg(Reg, SubIdx), State); 777c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Cheng return MIB.addReg(Reg, State, SubIdx); 778c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Cheng} 779c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Cheng 780334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinvoid ARMBaseInstrInfo:: 781334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinstoreRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 782334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned SrcReg, bool isKill, int FI, 783746ad69e088176819981b4b2c5ac8dcd49f5e60eEvan Cheng const TargetRegisterClass *RC, 784746ad69e088176819981b4b2c5ac8dcd49f5e60eEvan Cheng const TargetRegisterInfo *TRI) const { 785c7f3ace20c325521c68335a1689645b43b06ddf0Chris Lattner DebugLoc DL; 786334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (I != MBB.end()) DL = I->getDebugLoc(); 787249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MachineFunction &MF = *MBB.getParent(); 788249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MachineFrameInfo &MFI = *MF.getFrameInfo(); 78931bc849123011b8eae6bb3c79876d9a3c26a6a1dJim Grosbach unsigned Align = MFI.getObjectAlignment(FI); 790249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov 791249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MachineMemOperand *MMO = 792ff89dcb06fbd103373436e2d0ae85f252fae2254Evan Cheng MF.getMachineMemOperand(PseudoSourceValue::getFixedStack(FI), 793249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MachineMemOperand::MOStore, 0, 794249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MFI.getObjectSize(FI), 79531bc849123011b8eae6bb3c79876d9a3c26a6a1dJim Grosbach Align); 796334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 7970eb0c7401c34c0b4604f732ce54db995eead14e6Bob Wilson // tGPR is used sometimes in ARM instructions that need to avoid using 7980eb0c7401c34c0b4604f732ce54db995eead14e6Bob Wilson // certain registers. Just treat it as GPR here. 7990eb0c7401c34c0b4604f732ce54db995eead14e6Bob Wilson if (RC == ARM::tGPRRegisterClass) 8000eb0c7401c34c0b4604f732ce54db995eead14e6Bob Wilson RC = ARM::GPRRegisterClass; 8010eb0c7401c34c0b4604f732ce54db995eead14e6Bob Wilson 802334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (RC == ARM::GPRRegisterClass) { 8035732ca084aaa0cd26149e50dd4b487efff37fe41Evan Cheng AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::STR)) 804334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(SrcReg, getKillRegState(isKill)) 805249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov .addFrameIndex(FI).addReg(0).addImm(0).addMemOperand(MMO)); 806d31c5496d7e1580058b5c6fbc8fd537a641ea590Evan Cheng } else if (RC == ARM::SPRRegisterClass) { 807d31c5496d7e1580058b5c6fbc8fd537a641ea590Evan Cheng AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTRS)) 808d31c5496d7e1580058b5c6fbc8fd537a641ea590Evan Cheng .addReg(SrcReg, getKillRegState(isKill)) 809d31c5496d7e1580058b5c6fbc8fd537a641ea590Evan Cheng .addFrameIndex(FI).addImm(0).addMemOperand(MMO)); 8106ca0b9e7220911a6d1fccf34e532e69c7e37cd2fAnton Korobeynikov } else if (RC == ARM::DPRRegisterClass || 8116ca0b9e7220911a6d1fccf34e532e69c7e37cd2fAnton Korobeynikov RC == ARM::DPR_VFP2RegisterClass || 8126ca0b9e7220911a6d1fccf34e532e69c7e37cd2fAnton Korobeynikov RC == ARM::DPR_8RegisterClass) { 813e5165490b7ba24bb2f3043399e0d60e7f3bcf8a5Jim Grosbach AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTRD)) 814334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(SrcReg, getKillRegState(isKill)) 815249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov .addFrameIndex(FI).addImm(0).addMemOperand(MMO)); 816b63387afc6b10e88631d1ef232c41ab6c18c8581Evan Cheng } else if (RC == ARM::QPRRegisterClass || 817b63387afc6b10e88631d1ef232c41ab6c18c8581Evan Cheng RC == ARM::QPR_VFP2RegisterClass || 818b63387afc6b10e88631d1ef232c41ab6c18c8581Evan Cheng RC == ARM::QPR_8RegisterClass) { 819baf31088f1472f48ea5ae81f0b93636cc44ca444Anton Korobeynikov // FIXME: Neon instructions should support predicates 820b63387afc6b10e88631d1ef232c41ab6c18c8581Evan Cheng if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) { 82169b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1q)) 82269b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng .addFrameIndex(FI).addImm(128) 82369b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng .addReg(SrcReg, getKillRegState(isKill)) 82469b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng .addMemOperand(MMO)); 82531bc849123011b8eae6bb3c79876d9a3c26a6a1dJim Grosbach } else { 82669b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMQ)) 82769b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng .addReg(SrcReg, getKillRegState(isKill)) 82869b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng .addFrameIndex(FI) 82969b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng .addImm(ARM_AM::getAM5Opc(ARM_AM::ia, 4)) 83069b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng .addMemOperand(MMO)); 83131bc849123011b8eae6bb3c79876d9a3c26a6a1dJim Grosbach } 83222c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng } else if (RC == ARM::QQPRRegisterClass || RC == ARM::QQPR_VFP2RegisterClass){ 833435d4991779d6a47cadff4ea670b490d8507d6c4Evan Cheng if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) { 83422c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng // FIXME: It's possible to only store part of the QQ register if the 83522c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng // spilled def has a sub-register index. 836435d4991779d6a47cadff4ea670b490d8507d6c4Evan Cheng MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::VST2q32)) 837435d4991779d6a47cadff4ea670b490d8507d6c4Evan Cheng .addFrameIndex(FI).addImm(128); 838558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI); 839558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI); 840558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI); 841558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen MIB = AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI); 842435d4991779d6a47cadff4ea670b490d8507d6c4Evan Cheng AddDefaultPred(MIB.addMemOperand(MMO)); 843435d4991779d6a47cadff4ea670b490d8507d6c4Evan Cheng } else { 844435d4991779d6a47cadff4ea670b490d8507d6c4Evan Cheng MachineInstrBuilder MIB = 845435d4991779d6a47cadff4ea670b490d8507d6c4Evan Cheng AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMD)) 846435d4991779d6a47cadff4ea670b490d8507d6c4Evan Cheng .addFrameIndex(FI) 847435d4991779d6a47cadff4ea670b490d8507d6c4Evan Cheng .addImm(ARM_AM::getAM5Opc(ARM_AM::ia, 4))) 848435d4991779d6a47cadff4ea670b490d8507d6c4Evan Cheng .addMemOperand(MMO); 849558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI); 850558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI); 851558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI); 852558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI); 853435d4991779d6a47cadff4ea670b490d8507d6c4Evan Cheng } 85422c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng } else { 85522c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng assert(RC == ARM::QQQQPRRegisterClass && "Unknown regclass!"); 85622c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng MachineInstrBuilder MIB = 85722c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMD)) 85822c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng .addFrameIndex(FI) 85922c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng .addImm(ARM_AM::getAM5Opc(ARM_AM::ia, 4))) 86022c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng .addMemOperand(MMO); 861558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI); 862558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI); 863558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI); 864558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen MIB = AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI); 865558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen MIB = AddDReg(MIB, SrcReg, ARM::dsub_4, 0, TRI); 866558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen MIB = AddDReg(MIB, SrcReg, ARM::dsub_5, 0, TRI); 867558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen MIB = AddDReg(MIB, SrcReg, ARM::dsub_6, 0, TRI); 868558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen AddDReg(MIB, SrcReg, ARM::dsub_7, 0, TRI); 869334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 870334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 871334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 872334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinvoid ARMBaseInstrInfo:: 873334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinloadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 874334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned DestReg, int FI, 875746ad69e088176819981b4b2c5ac8dcd49f5e60eEvan Cheng const TargetRegisterClass *RC, 876746ad69e088176819981b4b2c5ac8dcd49f5e60eEvan Cheng const TargetRegisterInfo *TRI) const { 877c7f3ace20c325521c68335a1689645b43b06ddf0Chris Lattner DebugLoc DL; 878334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (I != MBB.end()) DL = I->getDebugLoc(); 879249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MachineFunction &MF = *MBB.getParent(); 880249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MachineFrameInfo &MFI = *MF.getFrameInfo(); 88131bc849123011b8eae6bb3c79876d9a3c26a6a1dJim Grosbach unsigned Align = MFI.getObjectAlignment(FI); 882249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MachineMemOperand *MMO = 883ff89dcb06fbd103373436e2d0ae85f252fae2254Evan Cheng MF.getMachineMemOperand(PseudoSourceValue::getFixedStack(FI), 884249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MachineMemOperand::MOLoad, 0, 885249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MFI.getObjectSize(FI), 88631bc849123011b8eae6bb3c79876d9a3c26a6a1dJim Grosbach Align); 887334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 8880eb0c7401c34c0b4604f732ce54db995eead14e6Bob Wilson // tGPR is used sometimes in ARM instructions that need to avoid using 8890eb0c7401c34c0b4604f732ce54db995eead14e6Bob Wilson // certain registers. Just treat it as GPR here. 8900eb0c7401c34c0b4604f732ce54db995eead14e6Bob Wilson if (RC == ARM::tGPRRegisterClass) 8910eb0c7401c34c0b4604f732ce54db995eead14e6Bob Wilson RC = ARM::GPRRegisterClass; 8920eb0c7401c34c0b4604f732ce54db995eead14e6Bob Wilson 893334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (RC == ARM::GPRRegisterClass) { 8945732ca084aaa0cd26149e50dd4b487efff37fe41Evan Cheng AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::LDR), DestReg) 895249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov .addFrameIndex(FI).addReg(0).addImm(0).addMemOperand(MMO)); 896d31c5496d7e1580058b5c6fbc8fd537a641ea590Evan Cheng } else if (RC == ARM::SPRRegisterClass) { 897d31c5496d7e1580058b5c6fbc8fd537a641ea590Evan Cheng AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRS), DestReg) 898d31c5496d7e1580058b5c6fbc8fd537a641ea590Evan Cheng .addFrameIndex(FI).addImm(0).addMemOperand(MMO)); 8996ca0b9e7220911a6d1fccf34e532e69c7e37cd2fAnton Korobeynikov } else if (RC == ARM::DPRRegisterClass || 9006ca0b9e7220911a6d1fccf34e532e69c7e37cd2fAnton Korobeynikov RC == ARM::DPR_VFP2RegisterClass || 9016ca0b9e7220911a6d1fccf34e532e69c7e37cd2fAnton Korobeynikov RC == ARM::DPR_8RegisterClass) { 902e5165490b7ba24bb2f3043399e0d60e7f3bcf8a5Jim Grosbach AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRD), DestReg) 903249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov .addFrameIndex(FI).addImm(0).addMemOperand(MMO)); 904b63387afc6b10e88631d1ef232c41ab6c18c8581Evan Cheng } else if (RC == ARM::QPRRegisterClass || 905b63387afc6b10e88631d1ef232c41ab6c18c8581Evan Cheng RC == ARM::QPR_VFP2RegisterClass || 906b63387afc6b10e88631d1ef232c41ab6c18c8581Evan Cheng RC == ARM::QPR_8RegisterClass) { 907b63387afc6b10e88631d1ef232c41ab6c18c8581Evan Cheng if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) { 90869b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1q), DestReg) 90969b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng .addFrameIndex(FI).addImm(128) 91069b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng .addMemOperand(MMO)); 91131bc849123011b8eae6bb3c79876d9a3c26a6a1dJim Grosbach } else { 91269b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMQ), DestReg) 91369b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng .addFrameIndex(FI) 91469b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng .addImm(ARM_AM::getAM5Opc(ARM_AM::ia, 4)) 91569b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng .addMemOperand(MMO)); 91631bc849123011b8eae6bb3c79876d9a3c26a6a1dJim Grosbach } 91722c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng } else if (RC == ARM::QQPRRegisterClass || RC == ARM::QQPR_VFP2RegisterClass){ 918435d4991779d6a47cadff4ea670b490d8507d6c4Evan Cheng if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) { 919435d4991779d6a47cadff4ea670b490d8507d6c4Evan Cheng MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::VLD2q32)); 920558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::Define, TRI); 921558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::Define, TRI); 922558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::Define, TRI); 923558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::Define, TRI); 924435d4991779d6a47cadff4ea670b490d8507d6c4Evan Cheng AddDefaultPred(MIB.addFrameIndex(FI).addImm(128).addMemOperand(MMO)); 925435d4991779d6a47cadff4ea670b490d8507d6c4Evan Cheng } else { 926435d4991779d6a47cadff4ea670b490d8507d6c4Evan Cheng MachineInstrBuilder MIB = 927435d4991779d6a47cadff4ea670b490d8507d6c4Evan Cheng AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMD)) 928435d4991779d6a47cadff4ea670b490d8507d6c4Evan Cheng .addFrameIndex(FI) 929435d4991779d6a47cadff4ea670b490d8507d6c4Evan Cheng .addImm(ARM_AM::getAM5Opc(ARM_AM::ia, 4))) 930435d4991779d6a47cadff4ea670b490d8507d6c4Evan Cheng .addMemOperand(MMO); 931558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::Define, TRI); 932558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::Define, TRI); 933558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::Define, TRI); 934558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen AddDReg(MIB, DestReg, ARM::dsub_3, RegState::Define, TRI); 935435d4991779d6a47cadff4ea670b490d8507d6c4Evan Cheng } 93622c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng } else { 93722c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng assert(RC == ARM::QQQQPRRegisterClass && "Unknown regclass!"); 93822c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng MachineInstrBuilder MIB = 93922c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMD)) 94022c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng .addFrameIndex(FI) 94122c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng .addImm(ARM_AM::getAM5Opc(ARM_AM::ia, 4))) 94222c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng .addMemOperand(MMO); 943558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::Define, TRI); 944558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::Define, TRI); 945558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::Define, TRI); 946558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::Define, TRI); 947558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen MIB = AddDReg(MIB, DestReg, ARM::dsub_4, RegState::Define, TRI); 948558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen MIB = AddDReg(MIB, DestReg, ARM::dsub_5, RegState::Define, TRI); 949558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen MIB = AddDReg(MIB, DestReg, ARM::dsub_6, RegState::Define, TRI); 950558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen AddDReg(MIB, DestReg, ARM::dsub_7, RegState::Define, TRI); 951334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 952334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 953334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 95462b50656ceb854eb0be265d63b2a1d46e7400d8aEvan ChengMachineInstr* 95562b50656ceb854eb0be265d63b2a1d46e7400d8aEvan ChengARMBaseInstrInfo::emitFrameIndexDebugValue(MachineFunction &MF, 9568601a3d4decff0a380e059b037dabf71075497d3Evan Cheng int FrameIx, uint64_t Offset, 95762b50656ceb854eb0be265d63b2a1d46e7400d8aEvan Cheng const MDNode *MDPtr, 95862b50656ceb854eb0be265d63b2a1d46e7400d8aEvan Cheng DebugLoc DL) const { 95962b50656ceb854eb0be265d63b2a1d46e7400d8aEvan Cheng MachineInstrBuilder MIB = BuildMI(MF, DL, get(ARM::DBG_VALUE)) 96062b50656ceb854eb0be265d63b2a1d46e7400d8aEvan Cheng .addFrameIndex(FrameIx).addImm(0).addImm(Offset).addMetadata(MDPtr); 96162b50656ceb854eb0be265d63b2a1d46e7400d8aEvan Cheng return &*MIB; 96262b50656ceb854eb0be265d63b2a1d46e7400d8aEvan Cheng} 96362b50656ceb854eb0be265d63b2a1d46e7400d8aEvan Cheng 964334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinMachineInstr *ARMBaseInstrInfo:: 965334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinfoldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI, 966334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const SmallVectorImpl<unsigned> &Ops, int FI) const { 967334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (Ops.size() != 1) return NULL; 968334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 969334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned OpNum = Ops[0]; 970334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned Opc = MI->getOpcode(); 971334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineInstr *NewMI = NULL; 97219068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng if (Opc == ARM::MOVr || Opc == ARM::t2MOVr) { 973334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // If it is updating CPSR, then it cannot be folded. 97419068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng if (MI->getOperand(4).getReg() == ARM::CPSR && !MI->getOperand(4).isDead()) 97519068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng return NULL; 97619068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng unsigned Pred = MI->getOperand(2).getImm(); 97719068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng unsigned PredReg = MI->getOperand(3).getReg(); 97819068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng if (OpNum == 0) { // move -> store 97919068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng unsigned SrcReg = MI->getOperand(1).getReg(); 980ed3ad212ec34fa2866fb70f9e52ddda31032ea3bEvan Cheng unsigned SrcSubReg = MI->getOperand(1).getSubReg(); 98119068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng bool isKill = MI->getOperand(1).isKill(); 98219068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng bool isUndef = MI->getOperand(1).isUndef(); 98319068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng if (Opc == ARM::MOVr) 98419068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::STR)) 985ed3ad212ec34fa2866fb70f9e52ddda31032ea3bEvan Cheng .addReg(SrcReg, 986ed3ad212ec34fa2866fb70f9e52ddda31032ea3bEvan Cheng getKillRegState(isKill) | getUndefRegState(isUndef), 987ed3ad212ec34fa2866fb70f9e52ddda31032ea3bEvan Cheng SrcSubReg) 98819068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng .addFrameIndex(FI).addReg(0).addImm(0).addImm(Pred).addReg(PredReg); 98919068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng else // ARM::t2MOVr 99019068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::t2STRi12)) 991ed3ad212ec34fa2866fb70f9e52ddda31032ea3bEvan Cheng .addReg(SrcReg, 992ed3ad212ec34fa2866fb70f9e52ddda31032ea3bEvan Cheng getKillRegState(isKill) | getUndefRegState(isUndef), 993ed3ad212ec34fa2866fb70f9e52ddda31032ea3bEvan Cheng SrcSubReg) 99419068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg); 99519068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng } else { // move -> load 99619068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng unsigned DstReg = MI->getOperand(0).getReg(); 997ed3ad212ec34fa2866fb70f9e52ddda31032ea3bEvan Cheng unsigned DstSubReg = MI->getOperand(0).getSubReg(); 99819068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng bool isDead = MI->getOperand(0).isDead(); 99919068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng bool isUndef = MI->getOperand(0).isUndef(); 100019068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng if (Opc == ARM::MOVr) 100119068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::LDR)) 100219068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng .addReg(DstReg, 100319068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng RegState::Define | 100419068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng getDeadRegState(isDead) | 1005ed3ad212ec34fa2866fb70f9e52ddda31032ea3bEvan Cheng getUndefRegState(isUndef), DstSubReg) 100619068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng .addFrameIndex(FI).addReg(0).addImm(0).addImm(Pred).addReg(PredReg); 100719068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng else // ARM::t2MOVr 100819068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::t2LDRi12)) 100919068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng .addReg(DstReg, 101019068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng RegState::Define | 101119068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng getDeadRegState(isDead) | 1012ed3ad212ec34fa2866fb70f9e52ddda31032ea3bEvan Cheng getUndefRegState(isUndef), DstSubReg) 101319068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg); 1014334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 101519068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng } else if (Opc == ARM::tMOVgpr2gpr || 101619068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng Opc == ARM::tMOVtgpr2gpr || 101719068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng Opc == ARM::tMOVgpr2tgpr) { 101819068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng if (OpNum == 0) { // move -> store 101919068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng unsigned SrcReg = MI->getOperand(1).getReg(); 1020ed3ad212ec34fa2866fb70f9e52ddda31032ea3bEvan Cheng unsigned SrcSubReg = MI->getOperand(1).getSubReg(); 102119068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng bool isKill = MI->getOperand(1).isKill(); 102219068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng bool isUndef = MI->getOperand(1).isUndef(); 102319068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::t2STRi12)) 1024ed3ad212ec34fa2866fb70f9e52ddda31032ea3bEvan Cheng .addReg(SrcReg, 1025ed3ad212ec34fa2866fb70f9e52ddda31032ea3bEvan Cheng getKillRegState(isKill) | getUndefRegState(isUndef), 1026ed3ad212ec34fa2866fb70f9e52ddda31032ea3bEvan Cheng SrcSubReg) 102719068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng .addFrameIndex(FI).addImm(0).addImm(ARMCC::AL).addReg(0); 102819068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng } else { // move -> load 102919068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng unsigned DstReg = MI->getOperand(0).getReg(); 1030ed3ad212ec34fa2866fb70f9e52ddda31032ea3bEvan Cheng unsigned DstSubReg = MI->getOperand(0).getSubReg(); 103119068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng bool isDead = MI->getOperand(0).isDead(); 103219068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng bool isUndef = MI->getOperand(0).isUndef(); 103319068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::t2LDRi12)) 103419068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng .addReg(DstReg, 103519068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng RegState::Define | 103619068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng getDeadRegState(isDead) | 1037ed3ad212ec34fa2866fb70f9e52ddda31032ea3bEvan Cheng getUndefRegState(isUndef), 1038ed3ad212ec34fa2866fb70f9e52ddda31032ea3bEvan Cheng DstSubReg) 103919068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng .addFrameIndex(FI).addImm(0).addImm(ARMCC::AL).addReg(0); 104019068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng } 1041e5165490b7ba24bb2f3043399e0d60e7f3bcf8a5Jim Grosbach } else if (Opc == ARM::VMOVS) { 1042334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned Pred = MI->getOperand(2).getImm(); 1043334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned PredReg = MI->getOperand(3).getReg(); 1044334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (OpNum == 0) { // move -> store 1045334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned SrcReg = MI->getOperand(1).getReg(); 1046ed3ad212ec34fa2866fb70f9e52ddda31032ea3bEvan Cheng unsigned SrcSubReg = MI->getOperand(1).getSubReg(); 1047334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool isKill = MI->getOperand(1).isKill(); 1048334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool isUndef = MI->getOperand(1).isUndef(); 1049e5165490b7ba24bb2f3043399e0d60e7f3bcf8a5Jim Grosbach NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::VSTRS)) 1050ed3ad212ec34fa2866fb70f9e52ddda31032ea3bEvan Cheng .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef), 1051ed3ad212ec34fa2866fb70f9e52ddda31032ea3bEvan Cheng SrcSubReg) 1052334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addFrameIndex(FI) 1053334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addImm(0).addImm(Pred).addReg(PredReg); 1054334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } else { // move -> load 1055334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned DstReg = MI->getOperand(0).getReg(); 1056ed3ad212ec34fa2866fb70f9e52ddda31032ea3bEvan Cheng unsigned DstSubReg = MI->getOperand(0).getSubReg(); 1057334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool isDead = MI->getOperand(0).isDead(); 1058334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool isUndef = MI->getOperand(0).isUndef(); 1059e5165490b7ba24bb2f3043399e0d60e7f3bcf8a5Jim Grosbach NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::VLDRS)) 1060334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(DstReg, 1061334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin RegState::Define | 1062334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin getDeadRegState(isDead) | 1063ed3ad212ec34fa2866fb70f9e52ddda31032ea3bEvan Cheng getUndefRegState(isUndef), 1064ed3ad212ec34fa2866fb70f9e52ddda31032ea3bEvan Cheng DstSubReg) 1065334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg); 1066334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 106769b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng } else if (Opc == ARM::VMOVD || Opc == ARM::VMOVDneon) { 1068334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned Pred = MI->getOperand(2).getImm(); 1069334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned PredReg = MI->getOperand(3).getReg(); 1070334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (OpNum == 0) { // move -> store 1071334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned SrcReg = MI->getOperand(1).getReg(); 1072ed3ad212ec34fa2866fb70f9e52ddda31032ea3bEvan Cheng unsigned SrcSubReg = MI->getOperand(1).getSubReg(); 1073334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool isKill = MI->getOperand(1).isKill(); 1074334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool isUndef = MI->getOperand(1).isUndef(); 1075e5165490b7ba24bb2f3043399e0d60e7f3bcf8a5Jim Grosbach NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::VSTRD)) 1076ed3ad212ec34fa2866fb70f9e52ddda31032ea3bEvan Cheng .addReg(SrcReg, 1077ed3ad212ec34fa2866fb70f9e52ddda31032ea3bEvan Cheng getKillRegState(isKill) | getUndefRegState(isUndef), 1078ed3ad212ec34fa2866fb70f9e52ddda31032ea3bEvan Cheng SrcSubReg) 1079334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg); 1080334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } else { // move -> load 1081334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned DstReg = MI->getOperand(0).getReg(); 1082ed3ad212ec34fa2866fb70f9e52ddda31032ea3bEvan Cheng unsigned DstSubReg = MI->getOperand(0).getSubReg(); 1083334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool isDead = MI->getOperand(0).isDead(); 1084334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool isUndef = MI->getOperand(0).isUndef(); 1085e5165490b7ba24bb2f3043399e0d60e7f3bcf8a5Jim Grosbach NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::VLDRD)) 1086334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(DstReg, 1087334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin RegState::Define | 1088334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin getDeadRegState(isDead) | 1089ed3ad212ec34fa2866fb70f9e52ddda31032ea3bEvan Cheng getUndefRegState(isUndef), 1090ed3ad212ec34fa2866fb70f9e52ddda31032ea3bEvan Cheng DstSubReg) 1091334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg); 1092334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 109369b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng } else if (Opc == ARM::VMOVQ) { 109469b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng MachineFrameInfo &MFI = *MF.getFrameInfo(); 109569b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng unsigned Pred = MI->getOperand(2).getImm(); 109669b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng unsigned PredReg = MI->getOperand(3).getReg(); 109769b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng if (OpNum == 0) { // move -> store 109869b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng unsigned SrcReg = MI->getOperand(1).getReg(); 109969b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng unsigned SrcSubReg = MI->getOperand(1).getSubReg(); 110069b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng bool isKill = MI->getOperand(1).isKill(); 110169b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng bool isUndef = MI->getOperand(1).isUndef(); 110269b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng if (MFI.getObjectAlignment(FI) >= 16 && 110369b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng getRegisterInfo().canRealignStack(MF)) { 110469b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::VST1q)) 110569b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng .addFrameIndex(FI).addImm(128) 110669b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng .addReg(SrcReg, 110769b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng getKillRegState(isKill) | getUndefRegState(isUndef), 110869b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng SrcSubReg) 110969b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng .addImm(Pred).addReg(PredReg); 111069b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng } else { 111169b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::VSTMQ)) 111269b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng .addReg(SrcReg, 111369b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng getKillRegState(isKill) | getUndefRegState(isUndef), 111469b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng SrcSubReg) 111569b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng .addFrameIndex(FI).addImm(ARM_AM::getAM5Opc(ARM_AM::ia, 4)) 111669b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng .addImm(Pred).addReg(PredReg); 111769b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng } 111869b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng } else { // move -> load 111969b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng unsigned DstReg = MI->getOperand(0).getReg(); 112069b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng unsigned DstSubReg = MI->getOperand(0).getSubReg(); 112169b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng bool isDead = MI->getOperand(0).isDead(); 112269b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng bool isUndef = MI->getOperand(0).isUndef(); 112369b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng if (MFI.getObjectAlignment(FI) >= 16 && 112469b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng getRegisterInfo().canRealignStack(MF)) { 112569b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::VLD1q)) 112669b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng .addReg(DstReg, 112769b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng RegState::Define | 112869b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng getDeadRegState(isDead) | 112969b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng getUndefRegState(isUndef), 113069b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng DstSubReg) 113169b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng .addFrameIndex(FI).addImm(128).addImm(Pred).addReg(PredReg); 113269b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng } else { 113369b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::VLDMQ)) 113469b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng .addReg(DstReg, 113569b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng RegState::Define | 113669b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng getDeadRegState(isDead) | 113769b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng getUndefRegState(isUndef), 113869b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng DstSubReg) 113969b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng .addFrameIndex(FI).addImm(ARM_AM::getAM5Opc(ARM_AM::ia, 4)) 114069b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng .addImm(Pred).addReg(PredReg); 114169b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng } 114269b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng } 1143334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 1144334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 1145334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return NewMI; 1146334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 1147334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 1148764ab52dd80310a205c9888bf166d09dab858f90Jim GrosbachMachineInstr* 1149334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinARMBaseInstrInfo::foldMemoryOperandImpl(MachineFunction &MF, 1150334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineInstr* MI, 1151334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const SmallVectorImpl<unsigned> &Ops, 1152334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineInstr* LoadMI) const { 11531f5c9887544ac2cb39d48e35cc6fa7a7b73ed3b0Evan Cheng // FIXME 1154334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 0; 1155334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 1156334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 1157334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinbool 1158334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinARMBaseInstrInfo::canFoldMemoryOperand(const MachineInstr *MI, 1159229464564243b24fb12cece515d727673e726994Evan Cheng const SmallVectorImpl<unsigned> &Ops) const { 1160334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (Ops.size() != 1) return false; 1161334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 1162334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned Opc = MI->getOpcode(); 11635732ca084aaa0cd26149e50dd4b487efff37fe41Evan Cheng if (Opc == ARM::MOVr || Opc == ARM::t2MOVr) { 1164334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // If it is updating CPSR, then it cannot be folded. 1165229464564243b24fb12cece515d727673e726994Evan Cheng return MI->getOperand(4).getReg() != ARM::CPSR || 1166229464564243b24fb12cece515d727673e726994Evan Cheng MI->getOperand(4).isDead(); 116719068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng } else if (Opc == ARM::tMOVgpr2gpr || 116819068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng Opc == ARM::tMOVtgpr2gpr || 116919068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng Opc == ARM::tMOVgpr2tgpr) { 117019068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng return true; 117169b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng } else if (Opc == ARM::VMOVS || Opc == ARM::VMOVD || 117269b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng Opc == ARM::VMOVDneon || Opc == ARM::VMOVQ) { 1173334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; 1174334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 1175334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 117622c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng // FIXME: VMOVQQ and VMOVQQQQ? 117722c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng 1178334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 1179334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 11805ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng 118130ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen/// Create a copy of a const pool value. Update CPI to the new index and return 118230ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen/// the label UID. 118330ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesenstatic unsigned duplicateCPV(MachineFunction &MF, unsigned &CPI) { 118430ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen MachineConstantPool *MCP = MF.getConstantPool(); 118530ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 118630ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen 118730ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPI]; 118830ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen assert(MCPE.isMachineConstantPoolEntry() && 118930ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen "Expecting a machine constantpool entry!"); 119030ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen ARMConstantPoolValue *ACPV = 119130ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal); 119230ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen 119330ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen unsigned PCLabelId = AFI->createConstPoolEntryUId(); 119430ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen ARMConstantPoolValue *NewCPV = 0; 119530ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen if (ACPV->isGlobalValue()) 119630ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen NewCPV = new ARMConstantPoolValue(ACPV->getGV(), PCLabelId, 119730ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen ARMCP::CPValue, 4); 119830ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen else if (ACPV->isExtSymbol()) 119930ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen NewCPV = new ARMConstantPoolValue(MF.getFunction()->getContext(), 120030ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen ACPV->getSymbol(), PCLabelId, 4); 120130ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen else if (ACPV->isBlockAddress()) 120230ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen NewCPV = new ARMConstantPoolValue(ACPV->getBlockAddress(), PCLabelId, 120330ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen ARMCP::CPBlockAddress, 4); 120430ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen else 120530ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen llvm_unreachable("Unexpected ARM constantpool value type!!"); 120630ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen CPI = MCP->getConstantPoolIndex(NewCPV, MCPE.getAlignment()); 120730ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen return PCLabelId; 120830ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen} 120930ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen 1210fdc834046efd427d474e3b899ec69354c05071e0Evan Chengvoid ARMBaseInstrInfo:: 1211fdc834046efd427d474e3b899ec69354c05071e0Evan ChengreMaterialize(MachineBasicBlock &MBB, 1212fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng MachineBasicBlock::iterator I, 1213fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng unsigned DestReg, unsigned SubIdx, 1214d57cdd5683ea926e489067364fb7ffe5fd5d35eeEvan Cheng const MachineInstr *Orig, 12159edf7deb37f0f97664f279040fa15d89f32e23d9Jakob Stoklund Olesen const TargetRegisterInfo &TRI) const { 1216fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng unsigned Opcode = Orig->getOpcode(); 1217fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng switch (Opcode) { 1218fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng default: { 1219fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig); 12209edf7deb37f0f97664f279040fa15d89f32e23d9Jakob Stoklund Olesen MI->substituteRegister(Orig->getOperand(0).getReg(), DestReg, SubIdx, TRI); 1221fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng MBB.insert(I, MI); 1222fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng break; 1223fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng } 1224fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng case ARM::tLDRpci_pic: 1225fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng case ARM::t2LDRpci_pic: { 1226fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng MachineFunction &MF = *MBB.getParent(); 1227fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng unsigned CPI = Orig->getOperand(1).getIndex(); 122830ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen unsigned PCLabelId = duplicateCPV(MF, CPI); 1229fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng MachineInstrBuilder MIB = BuildMI(MBB, I, Orig->getDebugLoc(), get(Opcode), 1230fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng DestReg) 1231fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng .addConstantPoolIndex(CPI).addImm(PCLabelId); 1232fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng (*MIB).setMemRefs(Orig->memoperands_begin(), Orig->memoperands_end()); 1233fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng break; 1234fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng } 1235fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng } 1236fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng} 1237fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng 123830ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund OlesenMachineInstr * 123930ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund OlesenARMBaseInstrInfo::duplicate(MachineInstr *Orig, MachineFunction &MF) const { 124030ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen MachineInstr *MI = TargetInstrInfoImpl::duplicate(Orig, MF); 124130ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen switch(Orig->getOpcode()) { 124230ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen case ARM::tLDRpci_pic: 124330ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen case ARM::t2LDRpci_pic: { 124430ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen unsigned CPI = Orig->getOperand(1).getIndex(); 124530ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen unsigned PCLabelId = duplicateCPV(MF, CPI); 124630ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen Orig->getOperand(1).setIndex(CPI); 124730ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen Orig->getOperand(2).setImm(PCLabelId); 124830ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen break; 124930ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen } 125030ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen } 125130ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen return MI; 125230ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen} 125330ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen 1254506049f29f4f202a8e45feb916cc0264440a7f6dEvan Chengbool ARMBaseInstrInfo::produceSameValue(const MachineInstr *MI0, 1255506049f29f4f202a8e45feb916cc0264440a7f6dEvan Cheng const MachineInstr *MI1) const { 1256d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng int Opcode = MI0->getOpcode(); 12579b82425cb0105fd5704f6b9bcd5e7693b05b1759Evan Cheng if (Opcode == ARM::t2LDRpci || 12589b82425cb0105fd5704f6b9bcd5e7693b05b1759Evan Cheng Opcode == ARM::t2LDRpci_pic || 12599b82425cb0105fd5704f6b9bcd5e7693b05b1759Evan Cheng Opcode == ARM::tLDRpci || 12609b82425cb0105fd5704f6b9bcd5e7693b05b1759Evan Cheng Opcode == ARM::tLDRpci_pic) { 1261d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng if (MI1->getOpcode() != Opcode) 1262d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng return false; 1263d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng if (MI0->getNumOperands() != MI1->getNumOperands()) 1264d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng return false; 1265d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng 1266d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng const MachineOperand &MO0 = MI0->getOperand(1); 1267d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng const MachineOperand &MO1 = MI1->getOperand(1); 1268d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng if (MO0.getOffset() != MO1.getOffset()) 1269d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng return false; 1270d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng 1271d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng const MachineFunction *MF = MI0->getParent()->getParent(); 1272d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng const MachineConstantPool *MCP = MF->getConstantPool(); 1273d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng int CPI0 = MO0.getIndex(); 1274d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng int CPI1 = MO1.getIndex(); 1275d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng const MachineConstantPoolEntry &MCPE0 = MCP->getConstants()[CPI0]; 1276d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng const MachineConstantPoolEntry &MCPE1 = MCP->getConstants()[CPI1]; 1277d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng ARMConstantPoolValue *ACPV0 = 1278d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng static_cast<ARMConstantPoolValue*>(MCPE0.Val.MachineCPVal); 1279d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng ARMConstantPoolValue *ACPV1 = 1280d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng static_cast<ARMConstantPoolValue*>(MCPE1.Val.MachineCPVal); 1281d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng return ACPV0->hasSameValue(ACPV1); 1282d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng } 1283d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng 1284506049f29f4f202a8e45feb916cc0264440a7f6dEvan Cheng return MI0->isIdenticalTo(MI1, MachineInstr::IgnoreVRegDefs); 1285d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng} 1286d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng 12878fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng/// getInstrPredicate - If instruction is predicated, returns its predicate 12888fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng/// condition, otherwise returns AL. It also returns the condition code 12898fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng/// register by reference. 12905adb66a646e2ec32265263739f5b01c3f50c176aEvan ChengARMCC::CondCodes 12915adb66a646e2ec32265263739f5b01c3f50c176aEvan Chengllvm::getInstrPredicate(const MachineInstr *MI, unsigned &PredReg) { 12928fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng int PIdx = MI->findFirstPredOperandIdx(); 12938fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng if (PIdx == -1) { 12948fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng PredReg = 0; 12958fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng return ARMCC::AL; 12968fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng } 12978fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng 12988fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng PredReg = MI->getOperand(PIdx+1).getReg(); 12998fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng return (ARMCC::CondCodes)MI->getOperand(PIdx).getImm(); 13008fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng} 13018fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng 13028fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng 13036495f63945e8dbde81f03a1dc2ab421993b9a495Evan Chengint llvm::getMatchingCondBranchOpcode(int Opc) { 13045ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng if (Opc == ARM::B) 13055ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng return ARM::Bcc; 13065ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng else if (Opc == ARM::tB) 13075ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng return ARM::tBcc; 13085ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng else if (Opc == ARM::t2B) 13095ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng return ARM::t2Bcc; 13105ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng 13115ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng llvm_unreachable("Unknown unconditional branch opcode!"); 13125ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng return 0; 13135ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng} 13145ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng 13156495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 13166495f63945e8dbde81f03a1dc2ab421993b9a495Evan Chengvoid llvm::emitARMRegPlusImmediate(MachineBasicBlock &MBB, 13176495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MachineBasicBlock::iterator &MBBI, DebugLoc dl, 13186495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned DestReg, unsigned BaseReg, int NumBytes, 13196495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ARMCC::CondCodes Pred, unsigned PredReg, 13206495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng const ARMBaseInstrInfo &TII) { 13216495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng bool isSub = NumBytes < 0; 13226495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (isSub) NumBytes = -NumBytes; 13236495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 13246495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng while (NumBytes) { 13256495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned RotAmt = ARM_AM::getSOImmValRotate(NumBytes); 13266495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned ThisVal = NumBytes & ARM_AM::rotr32(0xFF, RotAmt); 13276495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng assert(ThisVal && "Didn't extract field correctly"); 13286495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 13296495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // We will handle these bits from offset, clear them. 13306495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng NumBytes &= ~ThisVal; 13316495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 13326495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng assert(ARM_AM::getSOImmVal(ThisVal) != -1 && "Bit extraction didn't work?"); 13336495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 13346495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Build the new ADD / SUB. 13356495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned Opc = isSub ? ARM::SUBri : ARM::ADDri; 13366495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg) 13376495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng .addReg(BaseReg, RegState::Kill).addImm(ThisVal) 13386495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng .addImm((unsigned)Pred).addReg(PredReg).addReg(0); 13396495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng BaseReg = DestReg; 13406495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 13416495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng} 13426495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 1343cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Chengbool llvm::rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx, 1344cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng unsigned FrameReg, int &Offset, 1345cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng const ARMBaseInstrInfo &TII) { 13466495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned Opcode = MI.getOpcode(); 13476495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng const TargetInstrDesc &Desc = MI.getDesc(); 13486495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask); 13496495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng bool isSub = false; 1350764ab52dd80310a205c9888bf166d09dab858f90Jim Grosbach 13516495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Memory operands in inline assembly always use AddrMode2. 13526495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (Opcode == ARM::INLINEASM) 13536495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng AddrMode = ARMII::AddrMode2; 1354764ab52dd80310a205c9888bf166d09dab858f90Jim Grosbach 13556495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (Opcode == ARM::ADDri) { 13566495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng Offset += MI.getOperand(FrameRegIdx+1).getImm(); 13576495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (Offset == 0) { 13586495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Turn it into a move. 13596495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MI.setDesc(TII.get(ARM::MOVr)); 13606495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false); 13616495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MI.RemoveOperand(FrameRegIdx+1); 1362cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng Offset = 0; 1363cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng return true; 13646495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } else if (Offset < 0) { 13656495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng Offset = -Offset; 13666495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng isSub = true; 13676495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MI.setDesc(TII.get(ARM::SUBri)); 13686495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 13696495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 13706495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Common case: small offset, fits into instruction. 13716495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (ARM_AM::getSOImmVal(Offset) != -1) { 13726495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Replace the FrameIndex with sp / fp 13736495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false); 13746495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset); 1375cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng Offset = 0; 1376cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng return true; 13776495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 13786495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 13796495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Otherwise, pull as much of the immedidate into this ADDri/SUBri 13806495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // as possible. 13816495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned RotAmt = ARM_AM::getSOImmValRotate(Offset); 13826495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xFF, RotAmt); 13836495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 13846495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // We will handle these bits from offset, clear them. 13856495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng Offset &= ~ThisImmVal; 13866495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 13876495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Get the properly encoded SOImmVal field. 13886495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng assert(ARM_AM::getSOImmVal(ThisImmVal) != -1 && 13896495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng "Bit extraction didn't work?"); 13906495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MI.getOperand(FrameRegIdx+1).ChangeToImmediate(ThisImmVal); 13916495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } else { 13926495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned ImmIdx = 0; 13936495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng int InstrOffs = 0; 13946495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned NumBits = 0; 13956495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned Scale = 1; 13966495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng switch (AddrMode) { 13976495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng case ARMII::AddrMode2: { 13986495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ImmIdx = FrameRegIdx+2; 13996495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng InstrOffs = ARM_AM::getAM2Offset(MI.getOperand(ImmIdx).getImm()); 14006495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (ARM_AM::getAM2Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub) 14016495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng InstrOffs *= -1; 14026495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng NumBits = 12; 14036495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng break; 14046495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 14056495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng case ARMII::AddrMode3: { 14066495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ImmIdx = FrameRegIdx+2; 14076495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng InstrOffs = ARM_AM::getAM3Offset(MI.getOperand(ImmIdx).getImm()); 14086495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (ARM_AM::getAM3Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub) 14096495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng InstrOffs *= -1; 14106495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng NumBits = 8; 14116495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng break; 14126495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 1413baf31088f1472f48ea5ae81f0b93636cc44ca444Anton Korobeynikov case ARMII::AddrMode4: 1414a44321776ecd96fa0344335d3027758be3386e45Jim Grosbach case ARMII::AddrMode6: 1415cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng // Can't fold any offset even if it's zero. 1416cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng return false; 14176495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng case ARMII::AddrMode5: { 14186495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ImmIdx = FrameRegIdx+1; 14196495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng InstrOffs = ARM_AM::getAM5Offset(MI.getOperand(ImmIdx).getImm()); 14206495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (ARM_AM::getAM5Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub) 14216495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng InstrOffs *= -1; 14226495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng NumBits = 8; 14236495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng Scale = 4; 14246495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng break; 14256495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 14266495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng default: 14276495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng llvm_unreachable("Unsupported addressing mode!"); 14286495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng break; 14296495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 14306495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 14316495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng Offset += InstrOffs * Scale; 14326495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!"); 14336495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (Offset < 0) { 14346495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng Offset = -Offset; 14356495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng isSub = true; 14366495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 14376495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 14386495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Attempt to fold address comp. if opcode has offset bits 14396495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (NumBits > 0) { 14406495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Common case: small offset, fits into instruction. 14416495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MachineOperand &ImmOp = MI.getOperand(ImmIdx); 14426495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng int ImmedOffset = Offset / Scale; 14436495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned Mask = (1 << NumBits) - 1; 14446495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if ((unsigned)Offset <= Mask * Scale) { 14456495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Replace the FrameIndex with sp 14466495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false); 14476495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (isSub) 14486495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ImmedOffset |= 1 << NumBits; 14496495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ImmOp.ChangeToImmediate(ImmedOffset); 1450cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng Offset = 0; 1451cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng return true; 14526495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 1453764ab52dd80310a205c9888bf166d09dab858f90Jim Grosbach 14546495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Otherwise, it didn't fit. Pull in what we can to simplify the immed. 14556495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ImmedOffset = ImmedOffset & Mask; 14566495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (isSub) 14576495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ImmedOffset |= 1 << NumBits; 14586495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ImmOp.ChangeToImmediate(ImmedOffset); 14596495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng Offset &= ~(Mask*Scale); 14606495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 14616495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 14626495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 1463cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng Offset = (isSub) ? -Offset : Offset; 1464cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng return Offset == 0; 14656495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng} 1466