ARMBaseInstrInfo.cpp revision baf31088f1472f48ea5ae81f0b93636cc44ca444
1334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin//===- ARMBaseInstrInfo.cpp - ARM Instruction Information -----------*- C++ -*-===// 2334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// 3334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// The LLVM Compiler Infrastructure 4334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// 5334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// This file is distributed under the University of Illinois Open Source 6334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// License. See LICENSE.TXT for details. 7334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// 8334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin//===----------------------------------------------------------------------===// 9334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// 10334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// This file contains the Base ARM implementation of the TargetInstrInfo class. 11334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// 12334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin//===----------------------------------------------------------------------===// 13334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 14334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "ARMBaseInstrInfo.h" 15334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "ARM.h" 16334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "ARMAddressingModes.h" 17334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "ARMGenInstrInfo.inc" 18334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "ARMMachineFunctionInfo.h" 19334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "llvm/ADT/STLExtras.h" 20334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "llvm/CodeGen/LiveVariables.h" 21334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "llvm/CodeGen/MachineFrameInfo.h" 22334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "llvm/CodeGen/MachineInstrBuilder.h" 23334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "llvm/CodeGen/MachineJumpTableInfo.h" 24334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "llvm/Target/TargetAsmInfo.h" 25334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "llvm/Support/CommandLine.h" 26c25e7581b9b8088910da31702d4ca21c4734c6d7Torok Edwin#include "llvm/Support/ErrorHandling.h" 27334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinusing namespace llvm; 28334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 29334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinstatic cl::opt<bool> 30334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinEnableARM3Addr("enable-arm-3-addr-conv", cl::Hidden, 31334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin cl::desc("Enable ARM 2-addr to 3-addr conv")); 32334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 33d90183d25dcbc0eabde56319fed4e8d6ace2e6ebChris LattnerARMBaseInstrInfo::ARMBaseInstrInfo() 346495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng : TargetInstrInfoImpl(ARMInsts, array_lengthof(ARMInsts)) { 35334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 36334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 37334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinMachineInstr * 38334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinARMBaseInstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI, 39334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineBasicBlock::iterator &MBBI, 40334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin LiveVariables *LV) const { 4178703ddafe3d037f75d8ca188e4829d238289ac3Evan Cheng // FIXME: Thumb2 support. 4278703ddafe3d037f75d8ca188e4829d238289ac3Evan Cheng 43334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (!EnableARM3Addr) 44334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return NULL; 45334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 46334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineInstr *MI = MBBI; 47334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineFunction &MF = *MI->getParent()->getParent(); 48334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned TSFlags = MI->getDesc().TSFlags; 49334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool isPre = false; 50334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin switch ((TSFlags & ARMII::IndexModeMask) >> ARMII::IndexModeShift) { 51334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin default: return NULL; 52334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMII::IndexModePre: 53334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin isPre = true; 54334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin break; 55334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMII::IndexModePost: 56334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin break; 57334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 58334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 59334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Try splitting an indexed load/store to an un-indexed one plus an add/sub 60334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // operation. 61334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned MemOpc = getUnindexedOpcode(MI->getOpcode()); 62334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (MemOpc == 0) 63334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return NULL; 64334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 65334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineInstr *UpdateMI = NULL; 66334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineInstr *MemMI = NULL; 67334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned AddrMode = (TSFlags & ARMII::AddrModeMask); 68334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const TargetInstrDesc &TID = MI->getDesc(); 69334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned NumOps = TID.getNumOperands(); 70334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool isLoad = !TID.mayStore(); 71334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const MachineOperand &WB = isLoad ? MI->getOperand(1) : MI->getOperand(0); 72334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const MachineOperand &Base = MI->getOperand(2); 73334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const MachineOperand &Offset = MI->getOperand(NumOps-3); 74334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned WBReg = WB.getReg(); 75334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned BaseReg = Base.getReg(); 76334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned OffReg = Offset.getReg(); 77334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned OffImm = MI->getOperand(NumOps-2).getImm(); 78334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin ARMCC::CondCodes Pred = (ARMCC::CondCodes)MI->getOperand(NumOps-1).getImm(); 79334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin switch (AddrMode) { 80334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin default: 81334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin assert(false && "Unknown indexed op!"); 82334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return NULL; 83334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMII::AddrMode2: { 84334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool isSub = ARM_AM::getAM2Op(OffImm) == ARM_AM::sub; 85334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned Amt = ARM_AM::getAM2Offset(OffImm); 86334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (OffReg == 0) { 87e7cbe4118b7ddf05032ff8772a98c51e1637bb5cEvan Cheng if (ARM_AM::getSOImmVal(Amt) == -1) 88334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Can't encode it in a so_imm operand. This transformation will 89334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // add more than 1 instruction. Abandon! 90334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return NULL; 91334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin UpdateMI = BuildMI(MF, MI->getDebugLoc(), 9278703ddafe3d037f75d8ca188e4829d238289ac3Evan Cheng get(isSub ? ARM::SUBri : ARM::ADDri), WBReg) 93e7cbe4118b7ddf05032ff8772a98c51e1637bb5cEvan Cheng .addReg(BaseReg).addImm(Amt) 94334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addImm(Pred).addReg(0).addReg(0); 95334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } else if (Amt != 0) { 96334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin ARM_AM::ShiftOpc ShOpc = ARM_AM::getAM2ShiftOpc(OffImm); 97334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned SOOpc = ARM_AM::getSORegOpc(ShOpc, Amt); 98334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin UpdateMI = BuildMI(MF, MI->getDebugLoc(), 9978703ddafe3d037f75d8ca188e4829d238289ac3Evan Cheng get(isSub ? ARM::SUBrs : ARM::ADDrs), WBReg) 100334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(BaseReg).addReg(OffReg).addReg(0).addImm(SOOpc) 101334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addImm(Pred).addReg(0).addReg(0); 102334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } else 103334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin UpdateMI = BuildMI(MF, MI->getDebugLoc(), 10478703ddafe3d037f75d8ca188e4829d238289ac3Evan Cheng get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg) 105334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(BaseReg).addReg(OffReg) 106334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addImm(Pred).addReg(0).addReg(0); 107334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin break; 108334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 109334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMII::AddrMode3 : { 110334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool isSub = ARM_AM::getAM3Op(OffImm) == ARM_AM::sub; 111334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned Amt = ARM_AM::getAM3Offset(OffImm); 112334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (OffReg == 0) 113334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Immediate is 8-bits. It's guaranteed to fit in a so_imm operand. 114334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin UpdateMI = BuildMI(MF, MI->getDebugLoc(), 11578703ddafe3d037f75d8ca188e4829d238289ac3Evan Cheng get(isSub ? ARM::SUBri : ARM::ADDri), WBReg) 116334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(BaseReg).addImm(Amt) 117334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addImm(Pred).addReg(0).addReg(0); 118334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin else 119334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin UpdateMI = BuildMI(MF, MI->getDebugLoc(), 12078703ddafe3d037f75d8ca188e4829d238289ac3Evan Cheng get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg) 121334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(BaseReg).addReg(OffReg) 122334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addImm(Pred).addReg(0).addReg(0); 123334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin break; 124334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 125334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 126334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 127334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin std::vector<MachineInstr*> NewMIs; 128334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (isPre) { 129334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (isLoad) 130334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MemMI = BuildMI(MF, MI->getDebugLoc(), 131334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin get(MemOpc), MI->getOperand(0).getReg()) 132334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(WBReg).addReg(0).addImm(0).addImm(Pred); 133334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin else 134334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MemMI = BuildMI(MF, MI->getDebugLoc(), 135334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin get(MemOpc)).addReg(MI->getOperand(1).getReg()) 136334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(WBReg).addReg(0).addImm(0).addImm(Pred); 137334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin NewMIs.push_back(MemMI); 138334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin NewMIs.push_back(UpdateMI); 139334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } else { 140334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (isLoad) 141334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MemMI = BuildMI(MF, MI->getDebugLoc(), 142334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin get(MemOpc), MI->getOperand(0).getReg()) 143334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred); 144334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin else 145334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MemMI = BuildMI(MF, MI->getDebugLoc(), 146334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin get(MemOpc)).addReg(MI->getOperand(1).getReg()) 147334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred); 148334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (WB.isDead()) 149334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin UpdateMI->getOperand(0).setIsDead(); 150334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin NewMIs.push_back(UpdateMI); 151334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin NewMIs.push_back(MemMI); 152334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 153334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 154334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Transfer LiveVariables states, kill / dead info. 155334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (LV) { 156334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 157334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineOperand &MO = MI->getOperand(i); 158334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (MO.isReg() && MO.getReg() && 159334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin TargetRegisterInfo::isVirtualRegister(MO.getReg())) { 160334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned Reg = MO.getReg(); 161334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 162334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin LiveVariables::VarInfo &VI = LV->getVarInfo(Reg); 163334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (MO.isDef()) { 164334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineInstr *NewMI = (Reg == WBReg) ? UpdateMI : MemMI; 165334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (MO.isDead()) 166334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin LV->addVirtualRegisterDead(Reg, NewMI); 167334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 168334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (MO.isUse() && MO.isKill()) { 169334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin for (unsigned j = 0; j < 2; ++j) { 170334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Look at the two new MI's in reverse order. 171334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineInstr *NewMI = NewMIs[j]; 172334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (!NewMI->readsRegister(Reg)) 173334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin continue; 174334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin LV->addVirtualRegisterKilled(Reg, NewMI); 175334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (VI.removeKill(MI)) 176334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin VI.Kills.push_back(NewMI); 177334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin break; 178334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 179334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 180334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 181334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 182334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 183334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 184334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MFI->insert(MBBI, NewMIs[1]); 185334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MFI->insert(MBBI, NewMIs[0]); 186334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return NewMIs[0]; 187334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 188334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 189334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// Branch analysis. 190334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinbool 191334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinARMBaseInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB, 192334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineBasicBlock *&FBB, 193334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin SmallVectorImpl<MachineOperand> &Cond, 194334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool AllowModify) const { 195334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // If the block has no terminators, it just falls into the block after it. 196334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineBasicBlock::iterator I = MBB.end(); 197334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) 198334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 199334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 200334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Get the last instruction in the block. 201334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineInstr *LastInst = I; 202334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 203334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // If there is only one terminator instruction, process it. 204334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned LastOpc = LastInst->getOpcode(); 205334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) { 2065ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng if (isUncondBranchOpcode(LastOpc)) { 207334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin TBB = LastInst->getOperand(0).getMBB(); 208334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 209334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 2105ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng if (isCondBranchOpcode(LastOpc)) { 211334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Block ends with fall-through condbranch. 212334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin TBB = LastInst->getOperand(0).getMBB(); 213334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin Cond.push_back(LastInst->getOperand(1)); 214334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin Cond.push_back(LastInst->getOperand(2)); 215334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 216334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 217334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; // Can't handle indirect branch. 218334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 219334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 220334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Get the instruction before it if it is a terminator. 221334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineInstr *SecondLastInst = I; 222334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 223334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // If there are three terminators, we don't know what sort of block this is. 224334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(--I)) 225334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; 226334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 2275ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng // If the block ends with a B and a Bcc, handle it. 228334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned SecondLastOpc = SecondLastInst->getOpcode(); 2295ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng if (isCondBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) { 230334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin TBB = SecondLastInst->getOperand(0).getMBB(); 231334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin Cond.push_back(SecondLastInst->getOperand(1)); 232334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin Cond.push_back(SecondLastInst->getOperand(2)); 233334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin FBB = LastInst->getOperand(0).getMBB(); 234334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 235334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 236334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 237334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // If the block ends with two unconditional branches, handle it. The second 238334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // one is not executed, so remove it. 2395ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng if (isUncondBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) { 240334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin TBB = SecondLastInst->getOperand(0).getMBB(); 241334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin I = LastInst; 242334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (AllowModify) 243334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin I->eraseFromParent(); 244334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 245334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 246334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 247334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // ...likewise if it ends with a branch table followed by an unconditional 248334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // branch. The branch folder can create these, and we must get rid of them for 249334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // correctness of Thumb constant islands. 25083e0e36be8390fee1235783731f6c64aa604b7eeEvan Cheng if (isJumpTableBranchOpcode(SecondLastOpc) && 2515ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng isUncondBranchOpcode(LastOpc)) { 252334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin I = LastInst; 253334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (AllowModify) 254334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin I->eraseFromParent(); 255334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; 256334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 257334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 258334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Otherwise, can't handle this. 259334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; 260334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 261334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 262334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 263334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinunsigned ARMBaseInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const { 264334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineBasicBlock::iterator I = MBB.end(); 265334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (I == MBB.begin()) return 0; 266334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin --I; 2675ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng if (!isUncondBranchOpcode(I->getOpcode()) && 2685ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng !isCondBranchOpcode(I->getOpcode())) 269334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 0; 270334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 271334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Remove the branch. 272334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin I->eraseFromParent(); 273334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 274334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin I = MBB.end(); 275334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 276334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (I == MBB.begin()) return 1; 277334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin --I; 2785ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng if (!isCondBranchOpcode(I->getOpcode())) 279334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 1; 280334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 281334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Remove the branch. 282334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin I->eraseFromParent(); 283334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 2; 284334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 285334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 286334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinunsigned 287334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinARMBaseInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 288334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineBasicBlock *FBB, 289334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const SmallVectorImpl<MachineOperand> &Cond) const { 290334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // FIXME this should probably have a DebugLoc argument 291334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin DebugLoc dl = DebugLoc::getUnknownLoc(); 2926495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 2936495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ARMFunctionInfo *AFI = MBB.getParent()->getInfo<ARMFunctionInfo>(); 2946495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng int BOpc = !AFI->isThumbFunction() 2956495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ? ARM::B : (AFI->isThumb2Function() ? ARM::t2B : ARM::tB); 2966495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng int BccOpc = !AFI->isThumbFunction() 2976495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ? ARM::Bcc : (AFI->isThumb2Function() ? ARM::t2Bcc : ARM::tBcc); 298334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 299334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Shouldn't be a fall through. 300334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin assert(TBB && "InsertBranch must not be told to insert a fallthrough"); 301334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin assert((Cond.size() == 2 || Cond.size() == 0) && 302334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin "ARM branch conditions have two components!"); 303334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 304334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (FBB == 0) { 305334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (Cond.empty()) // Unconditional branch? 306334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin BuildMI(&MBB, dl, get(BOpc)).addMBB(TBB); 307334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin else 308334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin BuildMI(&MBB, dl, get(BccOpc)).addMBB(TBB) 309334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()); 310334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 1; 311334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 312334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 313334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Two-way conditional branch. 314334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin BuildMI(&MBB, dl, get(BccOpc)).addMBB(TBB) 315334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()); 316334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin BuildMI(&MBB, dl, get(BOpc)).addMBB(FBB); 317334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 2; 318334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 319334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 320334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinbool ARMBaseInstrInfo:: 321334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const { 322334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin ARMCC::CondCodes CC = (ARMCC::CondCodes)(int)Cond[0].getImm(); 323334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin Cond[0].setImm(ARMCC::getOppositeCondition(CC)); 324334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 325334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 326334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 327334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinbool ARMBaseInstrInfo:: 328334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinPredicateInstruction(MachineInstr *MI, 329334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const SmallVectorImpl<MachineOperand> &Pred) const { 330334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned Opc = MI->getOpcode(); 3315ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng if (isUncondBranchOpcode(Opc)) { 3325ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng MI->setDesc(get(getMatchingCondBranchOpcode(Opc))); 333334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI->addOperand(MachineOperand::CreateImm(Pred[0].getImm())); 334334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI->addOperand(MachineOperand::CreateReg(Pred[1].getReg(), false)); 335334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; 336334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 337334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 338334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin int PIdx = MI->findFirstPredOperandIdx(); 339334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (PIdx != -1) { 340334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineOperand &PMO = MI->getOperand(PIdx); 341334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin PMO.setImm(Pred[0].getImm()); 342334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI->getOperand(PIdx+1).setReg(Pred[1].getReg()); 343334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; 344334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 345334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 346334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 347334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 348334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinbool ARMBaseInstrInfo:: 349334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinSubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1, 350334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const SmallVectorImpl<MachineOperand> &Pred2) const { 351334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (Pred1.size() > 2 || Pred2.size() > 2) 352334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 353334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 354334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin ARMCC::CondCodes CC1 = (ARMCC::CondCodes)Pred1[0].getImm(); 355334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin ARMCC::CondCodes CC2 = (ARMCC::CondCodes)Pred2[0].getImm(); 356334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (CC1 == CC2) 357334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; 358334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 359334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin switch (CC1) { 360334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin default: 361334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 362334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMCC::AL: 363334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; 364334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMCC::HS: 365334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return CC2 == ARMCC::HI; 366334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMCC::LS: 367334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return CC2 == ARMCC::LO || CC2 == ARMCC::EQ; 368334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMCC::GE: 369334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return CC2 == ARMCC::GT; 370334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMCC::LE: 371334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return CC2 == ARMCC::LT; 372334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 373334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 374334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 375334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinbool ARMBaseInstrInfo::DefinesPredicate(MachineInstr *MI, 376334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin std::vector<MachineOperand> &Pred) const { 3778fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng // FIXME: This confuses implicit_def with optional CPSR def. 378334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const TargetInstrDesc &TID = MI->getDesc(); 379334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (!TID.getImplicitDefs() && !TID.hasOptionalDef()) 380334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 381334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 382334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool Found = false; 383334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 384334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const MachineOperand &MO = MI->getOperand(i); 385334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (MO.isReg() && MO.getReg() == ARM::CPSR) { 386334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin Pred.push_back(MO); 387334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin Found = true; 388334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 389334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 390334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 391334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return Found; 392334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 393334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 394334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 395334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin/// FIXME: Works around a gcc miscompilation with -fstrict-aliasing 396334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinstatic unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT, 397334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned JTI) DISABLE_INLINE; 398334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinstatic unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT, 399334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned JTI) { 400334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return JT[JTI].MBBs.size(); 401334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 402334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 403334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin/// GetInstSize - Return the size of the specified MachineInstr. 404334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin/// 405334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinunsigned ARMBaseInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const { 406334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const MachineBasicBlock &MBB = *MI->getParent(); 407334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const MachineFunction *MF = MBB.getParent(); 408334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const TargetAsmInfo *TAI = MF->getTarget().getTargetAsmInfo(); 409334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 410334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Basic size info comes from the TSFlags field. 411334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const TargetInstrDesc &TID = MI->getDesc(); 412334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned TSFlags = TID.TSFlags; 413334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 414a0ee862f2e3a0d202244e02459ddcf0dca0e8607Evan Cheng unsigned Opc = MI->getOpcode(); 415334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin switch ((TSFlags & ARMII::SizeMask) >> ARMII::SizeShift) { 416334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin default: { 417334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // If this machine instr is an inline asm, measure it. 418334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (MI->getOpcode() == ARM::INLINEASM) 419d90183d25dcbc0eabde56319fed4e8d6ace2e6ebChris Lattner return getInlineAsmLength(MI->getOperand(0).getSymbolName(), *TAI); 420334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (MI->isLabel()) 421334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 0; 422a0ee862f2e3a0d202244e02459ddcf0dca0e8607Evan Cheng switch (Opc) { 423334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin default: 424c23197a26f34f559ea9797de51e187087c039c42Torok Edwin llvm_unreachable("Unknown or unset size field for instr!"); 425334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case TargetInstrInfo::IMPLICIT_DEF: 426334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case TargetInstrInfo::DECLARE: 427334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case TargetInstrInfo::DBG_LABEL: 428334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case TargetInstrInfo::EH_LABEL: 429334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 0; 430334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 431334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin break; 432334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 433789476240d6b6f8ad9366cadf790a82bd41bb0b3Evan Cheng case ARMII::Size8Bytes: return 8; // ARM instruction x 2. 434789476240d6b6f8ad9366cadf790a82bd41bb0b3Evan Cheng case ARMII::Size4Bytes: return 4; // ARM / Thumb2 instruction. 435789476240d6b6f8ad9366cadf790a82bd41bb0b3Evan Cheng case ARMII::Size2Bytes: return 2; // Thumb1 instruction. 436334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMII::SizeSpecial: { 437a0ee862f2e3a0d202244e02459ddcf0dca0e8607Evan Cheng switch (Opc) { 438334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARM::CONSTPOOL_ENTRY: 439334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // If this machine instr is a constant pool entry, its size is recorded as 440334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // operand #2. 441334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return MI->getOperand(2).getImm(); 442789476240d6b6f8ad9366cadf790a82bd41bb0b3Evan Cheng case ARM::Int_eh_sjlj_setjmp: 443789476240d6b6f8ad9366cadf790a82bd41bb0b3Evan Cheng return 12; 444334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARM::BR_JTr: 445334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARM::BR_JTm: 446334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARM::BR_JTadd: 447a0ee862f2e3a0d202244e02459ddcf0dca0e8607Evan Cheng case ARM::tBR_JTr: 448d26b14c34cbcee1448b86b524578fc51cc979023Evan Cheng case ARM::t2BR_JT: 449d26b14c34cbcee1448b86b524578fc51cc979023Evan Cheng case ARM::t2TBB: 450d26b14c34cbcee1448b86b524578fc51cc979023Evan Cheng case ARM::t2TBH: { 451334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // These are jumptable branches, i.e. a branch followed by an inlined 452d26b14c34cbcee1448b86b524578fc51cc979023Evan Cheng // jumptable. The size is 4 + 4 * number of entries. For TBB, each 453d26b14c34cbcee1448b86b524578fc51cc979023Evan Cheng // entry is one byte; TBH two byte each. 454a0ee862f2e3a0d202244e02459ddcf0dca0e8607Evan Cheng unsigned EntrySize = (Opc == ARM::t2TBB) 455a0ee862f2e3a0d202244e02459ddcf0dca0e8607Evan Cheng ? 1 : ((Opc == ARM::t2TBH) ? 2 : 4); 456334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned NumOps = TID.getNumOperands(); 457334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineOperand JTOP = 458334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI->getOperand(NumOps - (TID.isPredicable() ? 3 : 2)); 459334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned JTI = JTOP.getIndex(); 460334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo(); 461334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables(); 462334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin assert(JTI < JT.size()); 463334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Thumb instructions are 2 byte aligned, but JT entries are 4 byte 464334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // 4 aligned. The assembler / linker may add 2 byte padding just before 465334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // the JT entries. The size does not include this padding; the 466334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // constant islands pass does separate bookkeeping for it. 467334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // FIXME: If we know the size of the function is less than (1 << 16) *2 468334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // bytes, we can use 16-bit entries instead. Then there won't be an 469334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // alignment issue. 47025f7cfc3cccba6f569f29f79ea533bae960b93c0Evan Cheng unsigned InstSize = (Opc == ARM::tBR_JTr || Opc == ARM::t2BR_JT) ? 2 : 4; 47125f7cfc3cccba6f569f29f79ea533bae960b93c0Evan Cheng unsigned NumEntries = getNumJTEntries(JT, JTI); 47225f7cfc3cccba6f569f29f79ea533bae960b93c0Evan Cheng if (Opc == ARM::t2TBB && (NumEntries & 1)) 47325f7cfc3cccba6f569f29f79ea533bae960b93c0Evan Cheng // Make sure the instruction that follows TBB is 2-byte aligned. 47425f7cfc3cccba6f569f29f79ea533bae960b93c0Evan Cheng // FIXME: Constant island pass should insert an "ALIGN" instruction 47525f7cfc3cccba6f569f29f79ea533bae960b93c0Evan Cheng // instead. 47625f7cfc3cccba6f569f29f79ea533bae960b93c0Evan Cheng ++NumEntries; 47725f7cfc3cccba6f569f29f79ea533bae960b93c0Evan Cheng return NumEntries * EntrySize + InstSize; 478334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 479334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin default: 480334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Otherwise, pseudo-instruction sizes are zero. 481334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 0; 482334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 483334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 484334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 485334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 0; // Not reached 486334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 487334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 488334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin/// Return true if the instruction is a register to register move and 489334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin/// leave the source and dest operands in the passed parameters. 490334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin/// 491334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinbool 492334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinARMBaseInstrInfo::isMoveInstr(const MachineInstr &MI, 493334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned &SrcReg, unsigned &DstReg, 494334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned& SrcSubIdx, unsigned& DstSubIdx) const { 495334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin SrcSubIdx = DstSubIdx = 0; // No sub-registers. 496334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 49768e3c6ae49ff67cba98403e43b5bd0c2499caa41Evan Cheng switch (MI.getOpcode()) { 498dced03fc846fa7cd9558ecb8e33ca98ec29bdcf0Evan Cheng default: break; 49968e3c6ae49ff67cba98403e43b5bd0c2499caa41Evan Cheng case ARM::FCPYS: 50068e3c6ae49ff67cba98403e43b5bd0c2499caa41Evan Cheng case ARM::FCPYD: 50168e3c6ae49ff67cba98403e43b5bd0c2499caa41Evan Cheng case ARM::VMOVD: 50268e3c6ae49ff67cba98403e43b5bd0c2499caa41Evan Cheng case ARM::VMOVQ: { 503334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin SrcReg = MI.getOperand(1).getReg(); 504334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin DstReg = MI.getOperand(0).getReg(); 505334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; 506334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 50768e3c6ae49ff67cba98403e43b5bd0c2499caa41Evan Cheng case ARM::MOVr: 50868e3c6ae49ff67cba98403e43b5bd0c2499caa41Evan Cheng case ARM::tMOVr: 50968e3c6ae49ff67cba98403e43b5bd0c2499caa41Evan Cheng case ARM::tMOVgpr2tgpr: 51068e3c6ae49ff67cba98403e43b5bd0c2499caa41Evan Cheng case ARM::tMOVtgpr2gpr: 51168e3c6ae49ff67cba98403e43b5bd0c2499caa41Evan Cheng case ARM::tMOVgpr2gpr: 51268e3c6ae49ff67cba98403e43b5bd0c2499caa41Evan Cheng case ARM::t2MOVr: { 513334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin assert(MI.getDesc().getNumOperands() >= 2 && 514334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI.getOperand(0).isReg() && 515334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI.getOperand(1).isReg() && 516334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin "Invalid ARM MOV instruction"); 517334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin SrcReg = MI.getOperand(1).getReg(); 518334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin DstReg = MI.getOperand(0).getReg(); 519334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; 520334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 52168e3c6ae49ff67cba98403e43b5bd0c2499caa41Evan Cheng } 522334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 523334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 524334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 525334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 526334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinunsigned 527334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinARMBaseInstrInfo::isLoadFromStackSlot(const MachineInstr *MI, 528334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin int &FrameIndex) const { 529dced03fc846fa7cd9558ecb8e33ca98ec29bdcf0Evan Cheng switch (MI->getOpcode()) { 530dced03fc846fa7cd9558ecb8e33ca98ec29bdcf0Evan Cheng default: break; 531dced03fc846fa7cd9558ecb8e33ca98ec29bdcf0Evan Cheng case ARM::LDR: 532dced03fc846fa7cd9558ecb8e33ca98ec29bdcf0Evan Cheng case ARM::t2LDRs: // FIXME: don't use t2LDRs to access frame. 533334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (MI->getOperand(1).isFI() && 534334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI->getOperand(2).isReg() && 535334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI->getOperand(3).isImm() && 536334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI->getOperand(2).getReg() == 0 && 537334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI->getOperand(3).getImm() == 0) { 538334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin FrameIndex = MI->getOperand(1).getIndex(); 539334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return MI->getOperand(0).getReg(); 540334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 541dced03fc846fa7cd9558ecb8e33ca98ec29bdcf0Evan Cheng break; 542dced03fc846fa7cd9558ecb8e33ca98ec29bdcf0Evan Cheng case ARM::t2LDRi12: 543dced03fc846fa7cd9558ecb8e33ca98ec29bdcf0Evan Cheng case ARM::tRestore: 5445ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin if (MI->getOperand(1).isFI() && 5455ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin MI->getOperand(2).isImm() && 5465ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin MI->getOperand(2).getImm() == 0) { 5475ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin FrameIndex = MI->getOperand(1).getIndex(); 5485ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin return MI->getOperand(0).getReg(); 5495ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin } 550dced03fc846fa7cd9558ecb8e33ca98ec29bdcf0Evan Cheng break; 551dced03fc846fa7cd9558ecb8e33ca98ec29bdcf0Evan Cheng case ARM::FLDD: 552dced03fc846fa7cd9558ecb8e33ca98ec29bdcf0Evan Cheng case ARM::FLDS: 553334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (MI->getOperand(1).isFI() && 554334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI->getOperand(2).isImm() && 555334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI->getOperand(2).getImm() == 0) { 556334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin FrameIndex = MI->getOperand(1).getIndex(); 557334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return MI->getOperand(0).getReg(); 558334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 559dced03fc846fa7cd9558ecb8e33ca98ec29bdcf0Evan Cheng break; 560334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 561334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 562334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 0; 563334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 564334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 565334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinunsigned 566334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinARMBaseInstrInfo::isStoreToStackSlot(const MachineInstr *MI, 567334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin int &FrameIndex) const { 568dced03fc846fa7cd9558ecb8e33ca98ec29bdcf0Evan Cheng switch (MI->getOpcode()) { 569dced03fc846fa7cd9558ecb8e33ca98ec29bdcf0Evan Cheng default: break; 570dced03fc846fa7cd9558ecb8e33ca98ec29bdcf0Evan Cheng case ARM::STR: 571dced03fc846fa7cd9558ecb8e33ca98ec29bdcf0Evan Cheng case ARM::t2STRs: // FIXME: don't use t2STRs to access frame. 572334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (MI->getOperand(1).isFI() && 573334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI->getOperand(2).isReg() && 574334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI->getOperand(3).isImm() && 575334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI->getOperand(2).getReg() == 0 && 576334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI->getOperand(3).getImm() == 0) { 577334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin FrameIndex = MI->getOperand(1).getIndex(); 578334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return MI->getOperand(0).getReg(); 579334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 580dced03fc846fa7cd9558ecb8e33ca98ec29bdcf0Evan Cheng break; 581dced03fc846fa7cd9558ecb8e33ca98ec29bdcf0Evan Cheng case ARM::t2STRi12: 582dced03fc846fa7cd9558ecb8e33ca98ec29bdcf0Evan Cheng case ARM::tSpill: 5835ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin if (MI->getOperand(1).isFI() && 5845ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin MI->getOperand(2).isImm() && 5855ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin MI->getOperand(2).getImm() == 0) { 5865ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin FrameIndex = MI->getOperand(1).getIndex(); 5875ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin return MI->getOperand(0).getReg(); 5885ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin } 589dced03fc846fa7cd9558ecb8e33ca98ec29bdcf0Evan Cheng break; 590dced03fc846fa7cd9558ecb8e33ca98ec29bdcf0Evan Cheng case ARM::FSTD: 5911d2426c4701650846922d312eb742cc55385c721Evan Cheng case ARM::FSTS: 592334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (MI->getOperand(1).isFI() && 593334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI->getOperand(2).isImm() && 594334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI->getOperand(2).getImm() == 0) { 595334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin FrameIndex = MI->getOperand(1).getIndex(); 596334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return MI->getOperand(0).getReg(); 597334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 598dced03fc846fa7cd9558ecb8e33ca98ec29bdcf0Evan Cheng break; 599334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 600334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 601334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 0; 602334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 603334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 604334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinbool 605334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinARMBaseInstrInfo::copyRegToReg(MachineBasicBlock &MBB, 606334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineBasicBlock::iterator I, 607334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned DestReg, unsigned SrcReg, 608334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const TargetRegisterClass *DestRC, 609334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const TargetRegisterClass *SrcRC) const { 610334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin DebugLoc DL = DebugLoc::getUnknownLoc(); 611334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (I != MBB.end()) DL = I->getDebugLoc(); 612334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 613334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (DestRC != SrcRC) { 6141d2426c4701650846922d312eb742cc55385c721Evan Cheng if (((DestRC == ARM::DPRRegisterClass) && 6151d2426c4701650846922d312eb742cc55385c721Evan Cheng (SrcRC == ARM::DPR_VFP2RegisterClass)) || 6161d2426c4701650846922d312eb742cc55385c721Evan Cheng ((SrcRC == ARM::DPRRegisterClass) && 6171d2426c4701650846922d312eb742cc55385c721Evan Cheng (DestRC == ARM::DPR_VFP2RegisterClass))) { 6187bfdca0206f51132b26094c6f83a5ac97ee0f943David Goodwin // Allow copy between DPR and DPR_VFP2. 6197bfdca0206f51132b26094c6f83a5ac97ee0f943David Goodwin } else { 6207bfdca0206f51132b26094c6f83a5ac97ee0f943David Goodwin return false; 6217bfdca0206f51132b26094c6f83a5ac97ee0f943David Goodwin } 622334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 623334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 6247bfdca0206f51132b26094c6f83a5ac97ee0f943David Goodwin if (DestRC == ARM::GPRRegisterClass) { 62508b93c6a70ae59af375f205cfcffeaa3517577abEvan Cheng AddDefaultCC(AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::MOVr), 626dd6f63209cba0003e67470938830de2cb6917336Evan Cheng DestReg).addReg(SrcReg))); 6277bfdca0206f51132b26094c6f83a5ac97ee0f943David Goodwin } else if (DestRC == ARM::SPRRegisterClass) { 628b74bb1a7a471a77e793d90de158aa4bbc67fe94dEvan Cheng AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FCPYS), DestReg) 629334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(SrcReg)); 6307bfdca0206f51132b26094c6f83a5ac97ee0f943David Goodwin } else if ((DestRC == ARM::DPRRegisterClass) || 6317bfdca0206f51132b26094c6f83a5ac97ee0f943David Goodwin (DestRC == ARM::DPR_VFP2RegisterClass)) { 632b74bb1a7a471a77e793d90de158aa4bbc67fe94dEvan Cheng AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FCPYD), DestReg) 633334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(SrcReg)); 6347bfdca0206f51132b26094c6f83a5ac97ee0f943David Goodwin } else if (DestRC == ARM::QPRRegisterClass) { 635b74bb1a7a471a77e793d90de158aa4bbc67fe94dEvan Cheng BuildMI(MBB, I, DL, get(ARM::VMOVQ), DestReg).addReg(SrcReg); 6367bfdca0206f51132b26094c6f83a5ac97ee0f943David Goodwin } else { 637334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 6387bfdca0206f51132b26094c6f83a5ac97ee0f943David Goodwin } 639334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 640334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; 641334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 642334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 643334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinvoid ARMBaseInstrInfo:: 644334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinstoreRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 645334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned SrcReg, bool isKill, int FI, 646334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const TargetRegisterClass *RC) const { 647334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin DebugLoc DL = DebugLoc::getUnknownLoc(); 648334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (I != MBB.end()) DL = I->getDebugLoc(); 649334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 650334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (RC == ARM::GPRRegisterClass) { 6515732ca084aaa0cd26149e50dd4b487efff37fe41Evan Cheng AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::STR)) 652334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(SrcReg, getKillRegState(isKill)) 653334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addFrameIndex(FI).addReg(0).addImm(0)); 6541d2426c4701650846922d312eb742cc55385c721Evan Cheng } else if (RC == ARM::DPRRegisterClass || RC == ARM::DPR_VFP2RegisterClass) { 655b74bb1a7a471a77e793d90de158aa4bbc67fe94dEvan Cheng AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FSTD)) 656334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(SrcReg, getKillRegState(isKill)) 657334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addFrameIndex(FI).addImm(0)); 658baf31088f1472f48ea5ae81f0b93636cc44ca444Anton Korobeynikov } else if (RC == ARM::SPRRegisterClass) { 659b74bb1a7a471a77e793d90de158aa4bbc67fe94dEvan Cheng AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FSTS)) 660334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(SrcReg, getKillRegState(isKill)) 661334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addFrameIndex(FI).addImm(0)); 662baf31088f1472f48ea5ae81f0b93636cc44ca444Anton Korobeynikov } else { 663baf31088f1472f48ea5ae81f0b93636cc44ca444Anton Korobeynikov assert(RC == ARM::QPRRegisterClass && "Unknown regclass!"); 664baf31088f1472f48ea5ae81f0b93636cc44ca444Anton Korobeynikov // FIXME: Neon instructions should support predicates 665baf31088f1472f48ea5ae81f0b93636cc44ca444Anton Korobeynikov BuildMI(MBB, I, DL, get(ARM::VSTRQ)).addReg(SrcReg, getKillRegState(isKill)) 666baf31088f1472f48ea5ae81f0b93636cc44ca444Anton Korobeynikov .addFrameIndex(FI).addImm(0); 667334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 668334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 669334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 670334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinvoid ARMBaseInstrInfo:: 671334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinloadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 672334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned DestReg, int FI, 673334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const TargetRegisterClass *RC) const { 674334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin DebugLoc DL = DebugLoc::getUnknownLoc(); 675334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (I != MBB.end()) DL = I->getDebugLoc(); 676334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 677334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (RC == ARM::GPRRegisterClass) { 6785732ca084aaa0cd26149e50dd4b487efff37fe41Evan Cheng AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::LDR), DestReg) 679334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addFrameIndex(FI).addReg(0).addImm(0)); 6801d2426c4701650846922d312eb742cc55385c721Evan Cheng } else if (RC == ARM::DPRRegisterClass || RC == ARM::DPR_VFP2RegisterClass) { 681b74bb1a7a471a77e793d90de158aa4bbc67fe94dEvan Cheng AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FLDD), DestReg) 682334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addFrameIndex(FI).addImm(0)); 683baf31088f1472f48ea5ae81f0b93636cc44ca444Anton Korobeynikov } else if (RC == ARM::SPRRegisterClass) { 684b74bb1a7a471a77e793d90de158aa4bbc67fe94dEvan Cheng AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FLDS), DestReg) 685334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addFrameIndex(FI).addImm(0)); 686baf31088f1472f48ea5ae81f0b93636cc44ca444Anton Korobeynikov } else { 687baf31088f1472f48ea5ae81f0b93636cc44ca444Anton Korobeynikov assert(RC == ARM::QPRRegisterClass && "Unknown regclass!"); 688baf31088f1472f48ea5ae81f0b93636cc44ca444Anton Korobeynikov // FIXME: Neon instructions should support predicates 689baf31088f1472f48ea5ae81f0b93636cc44ca444Anton Korobeynikov BuildMI(MBB, I, DL, get(ARM::VLDRQ), DestReg).addFrameIndex(FI).addImm(0); 690334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 691334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 692334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 693334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinMachineInstr *ARMBaseInstrInfo:: 694334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinfoldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI, 695334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const SmallVectorImpl<unsigned> &Ops, int FI) const { 696334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (Ops.size() != 1) return NULL; 697334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 698334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned OpNum = Ops[0]; 699334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned Opc = MI->getOpcode(); 700334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineInstr *NewMI = NULL; 701861986401e05e437cb33bfd8320d510b956fe41eEvan Cheng if (Opc == ARM::MOVr || Opc == ARM::t2MOVr) { // FIXME: tMOVgpr2gpr etc.? 702334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // If it is updating CPSR, then it cannot be folded. 7031f5c9887544ac2cb39d48e35cc6fa7a7b73ed3b0Evan Cheng if (MI->getOperand(4).getReg() != ARM::CPSR || MI->getOperand(4).isDead()) { 704334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned Pred = MI->getOperand(2).getImm(); 705334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned PredReg = MI->getOperand(3).getReg(); 706334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (OpNum == 0) { // move -> store 707334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned SrcReg = MI->getOperand(1).getReg(); 708334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool isKill = MI->getOperand(1).isKill(); 709334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool isUndef = MI->getOperand(1).isUndef(); 7105732ca084aaa0cd26149e50dd4b487efff37fe41Evan Cheng if (Opc == ARM::MOVr) 7115732ca084aaa0cd26149e50dd4b487efff37fe41Evan Cheng NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::STR)) 7125732ca084aaa0cd26149e50dd4b487efff37fe41Evan Cheng .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef)) 7135732ca084aaa0cd26149e50dd4b487efff37fe41Evan Cheng .addFrameIndex(FI).addReg(0).addImm(0).addImm(Pred).addReg(PredReg); 7145732ca084aaa0cd26149e50dd4b487efff37fe41Evan Cheng else // ARM::t2MOVr 7155732ca084aaa0cd26149e50dd4b487efff37fe41Evan Cheng NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::t2STRi12)) 7165732ca084aaa0cd26149e50dd4b487efff37fe41Evan Cheng .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef)) 7175732ca084aaa0cd26149e50dd4b487efff37fe41Evan Cheng .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg); 718334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } else { // move -> load 719334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned DstReg = MI->getOperand(0).getReg(); 720334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool isDead = MI->getOperand(0).isDead(); 721334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool isUndef = MI->getOperand(0).isUndef(); 7225732ca084aaa0cd26149e50dd4b487efff37fe41Evan Cheng if (Opc == ARM::MOVr) 7235732ca084aaa0cd26149e50dd4b487efff37fe41Evan Cheng NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::LDR)) 7245732ca084aaa0cd26149e50dd4b487efff37fe41Evan Cheng .addReg(DstReg, 7255732ca084aaa0cd26149e50dd4b487efff37fe41Evan Cheng RegState::Define | 7265732ca084aaa0cd26149e50dd4b487efff37fe41Evan Cheng getDeadRegState(isDead) | 7275732ca084aaa0cd26149e50dd4b487efff37fe41Evan Cheng getUndefRegState(isUndef)) 7285732ca084aaa0cd26149e50dd4b487efff37fe41Evan Cheng .addFrameIndex(FI).addReg(0).addImm(0).addImm(Pred).addReg(PredReg); 7295732ca084aaa0cd26149e50dd4b487efff37fe41Evan Cheng else // ARM::t2MOVr 7305732ca084aaa0cd26149e50dd4b487efff37fe41Evan Cheng NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::t2LDRi12)) 7315732ca084aaa0cd26149e50dd4b487efff37fe41Evan Cheng .addReg(DstReg, 7325732ca084aaa0cd26149e50dd4b487efff37fe41Evan Cheng RegState::Define | 7335732ca084aaa0cd26149e50dd4b487efff37fe41Evan Cheng getDeadRegState(isDead) | 7345732ca084aaa0cd26149e50dd4b487efff37fe41Evan Cheng getUndefRegState(isUndef)) 7355732ca084aaa0cd26149e50dd4b487efff37fe41Evan Cheng .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg); 736334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 737334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 738334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 739b74bb1a7a471a77e793d90de158aa4bbc67fe94dEvan Cheng else if (Opc == ARM::FCPYS) { 740334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned Pred = MI->getOperand(2).getImm(); 741334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned PredReg = MI->getOperand(3).getReg(); 742334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (OpNum == 0) { // move -> store 743334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned SrcReg = MI->getOperand(1).getReg(); 744334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool isKill = MI->getOperand(1).isKill(); 745334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool isUndef = MI->getOperand(1).isUndef(); 746b74bb1a7a471a77e793d90de158aa4bbc67fe94dEvan Cheng NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::FSTS)) 747334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef)) 748334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addFrameIndex(FI) 749334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addImm(0).addImm(Pred).addReg(PredReg); 750334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } else { // move -> load 751334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned DstReg = MI->getOperand(0).getReg(); 752334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool isDead = MI->getOperand(0).isDead(); 753334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool isUndef = MI->getOperand(0).isUndef(); 754b74bb1a7a471a77e793d90de158aa4bbc67fe94dEvan Cheng NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::FLDS)) 755334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(DstReg, 756334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin RegState::Define | 757334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin getDeadRegState(isDead) | 758334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin getUndefRegState(isUndef)) 759334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg); 760334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 761334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 762b74bb1a7a471a77e793d90de158aa4bbc67fe94dEvan Cheng else if (Opc == ARM::FCPYD) { 763334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned Pred = MI->getOperand(2).getImm(); 764334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned PredReg = MI->getOperand(3).getReg(); 765334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (OpNum == 0) { // move -> store 766334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned SrcReg = MI->getOperand(1).getReg(); 767334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool isKill = MI->getOperand(1).isKill(); 768334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool isUndef = MI->getOperand(1).isUndef(); 769b74bb1a7a471a77e793d90de158aa4bbc67fe94dEvan Cheng NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::FSTD)) 770334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef)) 771334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg); 772334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } else { // move -> load 773334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned DstReg = MI->getOperand(0).getReg(); 774334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool isDead = MI->getOperand(0).isDead(); 775334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool isUndef = MI->getOperand(0).isUndef(); 776b74bb1a7a471a77e793d90de158aa4bbc67fe94dEvan Cheng NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::FLDD)) 777334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(DstReg, 778334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin RegState::Define | 779334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin getDeadRegState(isDead) | 780334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin getUndefRegState(isUndef)) 781334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg); 782334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 783334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 784334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 785334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return NewMI; 786334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 787334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 788334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinMachineInstr* 789334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinARMBaseInstrInfo::foldMemoryOperandImpl(MachineFunction &MF, 790334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineInstr* MI, 791334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const SmallVectorImpl<unsigned> &Ops, 792334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineInstr* LoadMI) const { 7931f5c9887544ac2cb39d48e35cc6fa7a7b73ed3b0Evan Cheng // FIXME 794334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 0; 795334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 796334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 797334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinbool 798334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinARMBaseInstrInfo::canFoldMemoryOperand(const MachineInstr *MI, 799334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const SmallVectorImpl<unsigned> &Ops) const { 800334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (Ops.size() != 1) return false; 801334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 802334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned Opc = MI->getOpcode(); 8035732ca084aaa0cd26149e50dd4b487efff37fe41Evan Cheng if (Opc == ARM::MOVr || Opc == ARM::t2MOVr) { 804334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // If it is updating CPSR, then it cannot be folded. 8051f5c9887544ac2cb39d48e35cc6fa7a7b73ed3b0Evan Cheng return MI->getOperand(4).getReg() != ARM::CPSR ||MI->getOperand(4).isDead(); 806b74bb1a7a471a77e793d90de158aa4bbc67fe94dEvan Cheng } else if (Opc == ARM::FCPYS || Opc == ARM::FCPYD) { 807334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; 808b74bb1a7a471a77e793d90de158aa4bbc67fe94dEvan Cheng } else if (Opc == ARM::VMOVD || Opc == ARM::VMOVQ) { 809334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; // FIXME 810334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 811334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 812334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 813334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 8145ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng 8158fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng/// getInstrPredicate - If instruction is predicated, returns its predicate 8168fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng/// condition, otherwise returns AL. It also returns the condition code 8178fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng/// register by reference. 8188fb903604e83dfd63659c919042bf2bfed3c940fEvan ChengARMCC::CondCodes llvm::getInstrPredicate(MachineInstr *MI, unsigned &PredReg) { 8198fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng int PIdx = MI->findFirstPredOperandIdx(); 8208fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng if (PIdx == -1) { 8218fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng PredReg = 0; 8228fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng return ARMCC::AL; 8238fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng } 8248fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng 8258fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng PredReg = MI->getOperand(PIdx+1).getReg(); 8268fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng return (ARMCC::CondCodes)MI->getOperand(PIdx).getImm(); 8278fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng} 8288fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng 8298fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng 8306495f63945e8dbde81f03a1dc2ab421993b9a495Evan Chengint llvm::getMatchingCondBranchOpcode(int Opc) { 8315ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng if (Opc == ARM::B) 8325ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng return ARM::Bcc; 8335ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng else if (Opc == ARM::tB) 8345ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng return ARM::tBcc; 8355ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng else if (Opc == ARM::t2B) 8365ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng return ARM::t2Bcc; 8375ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng 8385ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng llvm_unreachable("Unknown unconditional branch opcode!"); 8395ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng return 0; 8405ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng} 8415ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng 8426495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 8436495f63945e8dbde81f03a1dc2ab421993b9a495Evan Chengvoid llvm::emitARMRegPlusImmediate(MachineBasicBlock &MBB, 8446495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MachineBasicBlock::iterator &MBBI, DebugLoc dl, 8456495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned DestReg, unsigned BaseReg, int NumBytes, 8466495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ARMCC::CondCodes Pred, unsigned PredReg, 8476495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng const ARMBaseInstrInfo &TII) { 8486495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng bool isSub = NumBytes < 0; 8496495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (isSub) NumBytes = -NumBytes; 8506495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 8516495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng while (NumBytes) { 8526495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned RotAmt = ARM_AM::getSOImmValRotate(NumBytes); 8536495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned ThisVal = NumBytes & ARM_AM::rotr32(0xFF, RotAmt); 8546495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng assert(ThisVal && "Didn't extract field correctly"); 8556495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 8566495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // We will handle these bits from offset, clear them. 8576495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng NumBytes &= ~ThisVal; 8586495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 8596495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng assert(ARM_AM::getSOImmVal(ThisVal) != -1 && "Bit extraction didn't work?"); 8606495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 8616495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Build the new ADD / SUB. 8626495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned Opc = isSub ? ARM::SUBri : ARM::ADDri; 8636495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg) 8646495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng .addReg(BaseReg, RegState::Kill).addImm(ThisVal) 8656495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng .addImm((unsigned)Pred).addReg(PredReg).addReg(0); 8666495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng BaseReg = DestReg; 8676495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 8686495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng} 8696495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 8706495f63945e8dbde81f03a1dc2ab421993b9a495Evan Chengint llvm::rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx, 8716495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned FrameReg, int Offset, 8726495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng const ARMBaseInstrInfo &TII) { 8736495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned Opcode = MI.getOpcode(); 8746495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng const TargetInstrDesc &Desc = MI.getDesc(); 8756495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask); 8766495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng bool isSub = false; 8776495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 8786495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Memory operands in inline assembly always use AddrMode2. 8796495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (Opcode == ARM::INLINEASM) 8806495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng AddrMode = ARMII::AddrMode2; 8816495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 8826495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (Opcode == ARM::ADDri) { 8836495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng Offset += MI.getOperand(FrameRegIdx+1).getImm(); 8846495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (Offset == 0) { 8856495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Turn it into a move. 8866495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MI.setDesc(TII.get(ARM::MOVr)); 8876495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false); 8886495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MI.RemoveOperand(FrameRegIdx+1); 8896495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng return 0; 8906495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } else if (Offset < 0) { 8916495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng Offset = -Offset; 8926495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng isSub = true; 8936495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MI.setDesc(TII.get(ARM::SUBri)); 8946495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 8956495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 8966495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Common case: small offset, fits into instruction. 8976495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (ARM_AM::getSOImmVal(Offset) != -1) { 8986495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Replace the FrameIndex with sp / fp 8996495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false); 9006495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset); 9016495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng return 0; 9026495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 9036495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 9046495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Otherwise, pull as much of the immedidate into this ADDri/SUBri 9056495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // as possible. 9066495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned RotAmt = ARM_AM::getSOImmValRotate(Offset); 9076495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xFF, RotAmt); 9086495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 9096495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // We will handle these bits from offset, clear them. 9106495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng Offset &= ~ThisImmVal; 9116495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 9126495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Get the properly encoded SOImmVal field. 9136495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng assert(ARM_AM::getSOImmVal(ThisImmVal) != -1 && 9146495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng "Bit extraction didn't work?"); 9156495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MI.getOperand(FrameRegIdx+1).ChangeToImmediate(ThisImmVal); 9166495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } else { 9176495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned ImmIdx = 0; 9186495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng int InstrOffs = 0; 9196495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned NumBits = 0; 9206495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned Scale = 1; 9216495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng switch (AddrMode) { 9226495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng case ARMII::AddrMode2: { 9236495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ImmIdx = FrameRegIdx+2; 9246495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng InstrOffs = ARM_AM::getAM2Offset(MI.getOperand(ImmIdx).getImm()); 9256495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (ARM_AM::getAM2Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub) 9266495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng InstrOffs *= -1; 9276495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng NumBits = 12; 9286495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng break; 9296495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 9306495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng case ARMII::AddrMode3: { 9316495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ImmIdx = FrameRegIdx+2; 9326495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng InstrOffs = ARM_AM::getAM3Offset(MI.getOperand(ImmIdx).getImm()); 9336495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (ARM_AM::getAM3Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub) 9346495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng InstrOffs *= -1; 9356495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng NumBits = 8; 9366495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng break; 9376495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 938baf31088f1472f48ea5ae81f0b93636cc44ca444Anton Korobeynikov case ARMII::AddrMode4: 939baf31088f1472f48ea5ae81f0b93636cc44ca444Anton Korobeynikov break; 9406495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng case ARMII::AddrMode5: { 9416495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ImmIdx = FrameRegIdx+1; 9426495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng InstrOffs = ARM_AM::getAM5Offset(MI.getOperand(ImmIdx).getImm()); 9436495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (ARM_AM::getAM5Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub) 9446495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng InstrOffs *= -1; 9456495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng NumBits = 8; 9466495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng Scale = 4; 9476495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng break; 9486495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 9496495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng default: 9506495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng llvm_unreachable("Unsupported addressing mode!"); 9516495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng break; 9526495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 9536495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 9546495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng Offset += InstrOffs * Scale; 9556495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!"); 9566495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (Offset < 0) { 9576495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng Offset = -Offset; 9586495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng isSub = true; 9596495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 9606495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 9616495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Attempt to fold address comp. if opcode has offset bits 9626495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (NumBits > 0) { 9636495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Common case: small offset, fits into instruction. 9646495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MachineOperand &ImmOp = MI.getOperand(ImmIdx); 9656495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng int ImmedOffset = Offset / Scale; 9666495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned Mask = (1 << NumBits) - 1; 9676495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if ((unsigned)Offset <= Mask * Scale) { 9686495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Replace the FrameIndex with sp 9696495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false); 9706495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (isSub) 9716495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ImmedOffset |= 1 << NumBits; 9726495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ImmOp.ChangeToImmediate(ImmedOffset); 9736495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng return 0; 9746495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 9756495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 9766495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Otherwise, it didn't fit. Pull in what we can to simplify the immed. 9776495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ImmedOffset = ImmedOffset & Mask; 9786495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (isSub) 9796495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ImmedOffset |= 1 << NumBits; 9806495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ImmOp.ChangeToImmediate(ImmedOffset); 9816495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng Offset &= ~(Mask*Scale); 9826495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 9836495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 9846495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 9856495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng return (isSub) ? -Offset : Offset; 9866495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng} 987