ARMBaseInstrInfo.cpp revision c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cb
131c24bf5b39cc8391d4cfdbf8cf5163975fdb81eJim Grosbach//===- ARMBaseInstrInfo.cpp - ARM Instruction Information -------*- C++ -*-===// 2334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// 3334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// The LLVM Compiler Infrastructure 4334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// 5334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// This file is distributed under the University of Illinois Open Source 6334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// License. See LICENSE.TXT for details. 7334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// 8334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin//===----------------------------------------------------------------------===// 9334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// 10334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// This file contains the Base ARM implementation of the TargetInstrInfo class. 11334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// 12334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin//===----------------------------------------------------------------------===// 13334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 14334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "ARMBaseInstrInfo.h" 15334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "ARM.h" 16334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "ARMAddressingModes.h" 17d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng#include "ARMConstantPoolValue.h" 18334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "ARMGenInstrInfo.inc" 19334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "ARMMachineFunctionInfo.h" 20f95215f551949d5e5adfbf4753aa833b9009b77aAnton Korobeynikov#include "ARMRegisterInfo.h" 21fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng#include "llvm/Constants.h" 22fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng#include "llvm/Function.h" 23fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng#include "llvm/GlobalValue.h" 24334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "llvm/ADT/STLExtras.h" 25334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "llvm/CodeGen/LiveVariables.h" 26d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng#include "llvm/CodeGen/MachineConstantPool.h" 27334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "llvm/CodeGen/MachineFrameInfo.h" 28334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "llvm/CodeGen/MachineInstrBuilder.h" 29334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "llvm/CodeGen/MachineJumpTableInfo.h" 30249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov#include "llvm/CodeGen/MachineMemOperand.h" 31249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov#include "llvm/CodeGen/PseudoSourceValue.h" 32af76e592c7f9deff0e55c13dbb4a34f07f1c7f64Chris Lattner#include "llvm/MC/MCAsmInfo.h" 33334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "llvm/Support/CommandLine.h" 34f95215f551949d5e5adfbf4753aa833b9009b77aAnton Korobeynikov#include "llvm/Support/Debug.h" 35c25e7581b9b8088910da31702d4ca21c4734c6d7Torok Edwin#include "llvm/Support/ErrorHandling.h" 36334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinusing namespace llvm; 37334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 38334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinstatic cl::opt<bool> 39334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinEnableARM3Addr("enable-arm-3-addr-conv", cl::Hidden, 40334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin cl::desc("Enable ARM 2-addr to 3-addr conv")); 41334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 42f95215f551949d5e5adfbf4753aa833b9009b77aAnton KorobeynikovARMBaseInstrInfo::ARMBaseInstrInfo(const ARMSubtarget& STI) 43f95215f551949d5e5adfbf4753aa833b9009b77aAnton Korobeynikov : TargetInstrInfoImpl(ARMInsts, array_lengthof(ARMInsts)), 44f95215f551949d5e5adfbf4753aa833b9009b77aAnton Korobeynikov Subtarget(STI) { 45334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 46334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 47334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinMachineInstr * 48334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinARMBaseInstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI, 49334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineBasicBlock::iterator &MBBI, 50334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin LiveVariables *LV) const { 5178703ddafe3d037f75d8ca188e4829d238289ac3Evan Cheng // FIXME: Thumb2 support. 5278703ddafe3d037f75d8ca188e4829d238289ac3Evan Cheng 53334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (!EnableARM3Addr) 54334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return NULL; 55334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 56334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineInstr *MI = MBBI; 57334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineFunction &MF = *MI->getParent()->getParent(); 58334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned TSFlags = MI->getDesc().TSFlags; 59334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool isPre = false; 60334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin switch ((TSFlags & ARMII::IndexModeMask) >> ARMII::IndexModeShift) { 61334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin default: return NULL; 62334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMII::IndexModePre: 63334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin isPre = true; 64334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin break; 65334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMII::IndexModePost: 66334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin break; 67334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 68334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 69334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Try splitting an indexed load/store to an un-indexed one plus an add/sub 70334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // operation. 71334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned MemOpc = getUnindexedOpcode(MI->getOpcode()); 72334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (MemOpc == 0) 73334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return NULL; 74334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 75334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineInstr *UpdateMI = NULL; 76334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineInstr *MemMI = NULL; 77334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned AddrMode = (TSFlags & ARMII::AddrModeMask); 78334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const TargetInstrDesc &TID = MI->getDesc(); 79334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned NumOps = TID.getNumOperands(); 80334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool isLoad = !TID.mayStore(); 81334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const MachineOperand &WB = isLoad ? MI->getOperand(1) : MI->getOperand(0); 82334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const MachineOperand &Base = MI->getOperand(2); 83334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const MachineOperand &Offset = MI->getOperand(NumOps-3); 84334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned WBReg = WB.getReg(); 85334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned BaseReg = Base.getReg(); 86334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned OffReg = Offset.getReg(); 87334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned OffImm = MI->getOperand(NumOps-2).getImm(); 88334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin ARMCC::CondCodes Pred = (ARMCC::CondCodes)MI->getOperand(NumOps-1).getImm(); 89334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin switch (AddrMode) { 90334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin default: 91334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin assert(false && "Unknown indexed op!"); 92334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return NULL; 93334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMII::AddrMode2: { 94334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool isSub = ARM_AM::getAM2Op(OffImm) == ARM_AM::sub; 95334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned Amt = ARM_AM::getAM2Offset(OffImm); 96334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (OffReg == 0) { 97e7cbe4118b7ddf05032ff8772a98c51e1637bb5cEvan Cheng if (ARM_AM::getSOImmVal(Amt) == -1) 98334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Can't encode it in a so_imm operand. This transformation will 99334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // add more than 1 instruction. Abandon! 100334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return NULL; 101334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin UpdateMI = BuildMI(MF, MI->getDebugLoc(), 10278703ddafe3d037f75d8ca188e4829d238289ac3Evan Cheng get(isSub ? ARM::SUBri : ARM::ADDri), WBReg) 103e7cbe4118b7ddf05032ff8772a98c51e1637bb5cEvan Cheng .addReg(BaseReg).addImm(Amt) 104334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addImm(Pred).addReg(0).addReg(0); 105334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } else if (Amt != 0) { 106334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin ARM_AM::ShiftOpc ShOpc = ARM_AM::getAM2ShiftOpc(OffImm); 107334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned SOOpc = ARM_AM::getSORegOpc(ShOpc, Amt); 108334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin UpdateMI = BuildMI(MF, MI->getDebugLoc(), 10978703ddafe3d037f75d8ca188e4829d238289ac3Evan Cheng get(isSub ? ARM::SUBrs : ARM::ADDrs), WBReg) 110334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(BaseReg).addReg(OffReg).addReg(0).addImm(SOOpc) 111334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addImm(Pred).addReg(0).addReg(0); 112334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } else 113334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin UpdateMI = BuildMI(MF, MI->getDebugLoc(), 11478703ddafe3d037f75d8ca188e4829d238289ac3Evan Cheng get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg) 115334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(BaseReg).addReg(OffReg) 116334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addImm(Pred).addReg(0).addReg(0); 117334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin break; 118334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 119334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMII::AddrMode3 : { 120334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool isSub = ARM_AM::getAM3Op(OffImm) == ARM_AM::sub; 121334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned Amt = ARM_AM::getAM3Offset(OffImm); 122334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (OffReg == 0) 123334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Immediate is 8-bits. It's guaranteed to fit in a so_imm operand. 124334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin UpdateMI = BuildMI(MF, MI->getDebugLoc(), 12578703ddafe3d037f75d8ca188e4829d238289ac3Evan Cheng get(isSub ? ARM::SUBri : ARM::ADDri), WBReg) 126334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(BaseReg).addImm(Amt) 127334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addImm(Pred).addReg(0).addReg(0); 128334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin else 129334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin UpdateMI = BuildMI(MF, MI->getDebugLoc(), 13078703ddafe3d037f75d8ca188e4829d238289ac3Evan Cheng get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg) 131334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(BaseReg).addReg(OffReg) 132334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addImm(Pred).addReg(0).addReg(0); 133334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin break; 134334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 135334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 136334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 137334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin std::vector<MachineInstr*> NewMIs; 138334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (isPre) { 139334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (isLoad) 140334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MemMI = BuildMI(MF, MI->getDebugLoc(), 141334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin get(MemOpc), MI->getOperand(0).getReg()) 142334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(WBReg).addReg(0).addImm(0).addImm(Pred); 143334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin else 144334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MemMI = BuildMI(MF, MI->getDebugLoc(), 145334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin get(MemOpc)).addReg(MI->getOperand(1).getReg()) 146334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(WBReg).addReg(0).addImm(0).addImm(Pred); 147334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin NewMIs.push_back(MemMI); 148334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin NewMIs.push_back(UpdateMI); 149334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } else { 150334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (isLoad) 151334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MemMI = BuildMI(MF, MI->getDebugLoc(), 152334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin get(MemOpc), MI->getOperand(0).getReg()) 153334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred); 154334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin else 155334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MemMI = BuildMI(MF, MI->getDebugLoc(), 156334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin get(MemOpc)).addReg(MI->getOperand(1).getReg()) 157334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred); 158334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (WB.isDead()) 159334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin UpdateMI->getOperand(0).setIsDead(); 160334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin NewMIs.push_back(UpdateMI); 161334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin NewMIs.push_back(MemMI); 162334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 163334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 164334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Transfer LiveVariables states, kill / dead info. 165334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (LV) { 166334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 167334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineOperand &MO = MI->getOperand(i); 168334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (MO.isReg() && MO.getReg() && 169334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin TargetRegisterInfo::isVirtualRegister(MO.getReg())) { 170334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned Reg = MO.getReg(); 171334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 172334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin LiveVariables::VarInfo &VI = LV->getVarInfo(Reg); 173334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (MO.isDef()) { 174334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineInstr *NewMI = (Reg == WBReg) ? UpdateMI : MemMI; 175334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (MO.isDead()) 176334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin LV->addVirtualRegisterDead(Reg, NewMI); 177334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 178334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (MO.isUse() && MO.isKill()) { 179334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin for (unsigned j = 0; j < 2; ++j) { 180334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Look at the two new MI's in reverse order. 181334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineInstr *NewMI = NewMIs[j]; 182334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (!NewMI->readsRegister(Reg)) 183334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin continue; 184334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin LV->addVirtualRegisterKilled(Reg, NewMI); 185334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (VI.removeKill(MI)) 186334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin VI.Kills.push_back(NewMI); 187334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin break; 188334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 189334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 190334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 191334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 192334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 193334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 194334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MFI->insert(MBBI, NewMIs[1]); 195334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MFI->insert(MBBI, NewMIs[0]); 196334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return NewMIs[0]; 197334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 198334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 199334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// Branch analysis. 200334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinbool 201334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinARMBaseInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB, 202334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineBasicBlock *&FBB, 203334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin SmallVectorImpl<MachineOperand> &Cond, 204334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool AllowModify) const { 205334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // If the block has no terminators, it just falls into the block after it. 206334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineBasicBlock::iterator I = MBB.end(); 20793d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen if (I == MBB.begin()) 20893d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen return false; 20993d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen --I; 21093d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen while (I->isDebugValue()) { 21193d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen if (I == MBB.begin()) 21293d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen return false; 21393d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen --I; 21493d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen } 21593d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen if (!isUnpredicatedTerminator(I)) 216334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 217334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 218334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Get the last instruction in the block. 219334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineInstr *LastInst = I; 220334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 221334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // If there is only one terminator instruction, process it. 222334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned LastOpc = LastInst->getOpcode(); 223334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) { 2245ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng if (isUncondBranchOpcode(LastOpc)) { 225334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin TBB = LastInst->getOperand(0).getMBB(); 226334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 227334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 2285ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng if (isCondBranchOpcode(LastOpc)) { 229334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Block ends with fall-through condbranch. 230334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin TBB = LastInst->getOperand(0).getMBB(); 231334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin Cond.push_back(LastInst->getOperand(1)); 232334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin Cond.push_back(LastInst->getOperand(2)); 233334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 234334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 235334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; // Can't handle indirect branch. 236334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 237334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 238334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Get the instruction before it if it is a terminator. 239334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineInstr *SecondLastInst = I; 240334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 241334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // If there are three terminators, we don't know what sort of block this is. 242334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(--I)) 243334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; 244334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 2455ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng // If the block ends with a B and a Bcc, handle it. 246334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned SecondLastOpc = SecondLastInst->getOpcode(); 2475ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng if (isCondBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) { 248334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin TBB = SecondLastInst->getOperand(0).getMBB(); 249334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin Cond.push_back(SecondLastInst->getOperand(1)); 250334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin Cond.push_back(SecondLastInst->getOperand(2)); 251334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin FBB = LastInst->getOperand(0).getMBB(); 252334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 253334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 254334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 255334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // If the block ends with two unconditional branches, handle it. The second 256334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // one is not executed, so remove it. 2575ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng if (isUncondBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) { 258334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin TBB = SecondLastInst->getOperand(0).getMBB(); 259334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin I = LastInst; 260334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (AllowModify) 261334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin I->eraseFromParent(); 262334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 263334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 264334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 265334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // ...likewise if it ends with a branch table followed by an unconditional 266334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // branch. The branch folder can create these, and we must get rid of them for 267334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // correctness of Thumb constant islands. 2688d4de5abfa1bcd974554ea14904ebf7af289e84dBob Wilson if ((isJumpTableBranchOpcode(SecondLastOpc) || 2698d4de5abfa1bcd974554ea14904ebf7af289e84dBob Wilson isIndirectBranchOpcode(SecondLastOpc)) && 2705ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng isUncondBranchOpcode(LastOpc)) { 271334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin I = LastInst; 272334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (AllowModify) 273334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin I->eraseFromParent(); 274334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; 275334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 276334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 277334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Otherwise, can't handle this. 278334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; 279334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 280334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 281334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 282334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinunsigned ARMBaseInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const { 283334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineBasicBlock::iterator I = MBB.end(); 284334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (I == MBB.begin()) return 0; 285334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin --I; 28693d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen while (I->isDebugValue()) { 28793d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen if (I == MBB.begin()) 28893d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen return 0; 28993d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen --I; 29093d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen } 2915ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng if (!isUncondBranchOpcode(I->getOpcode()) && 2925ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng !isCondBranchOpcode(I->getOpcode())) 293334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 0; 294334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 295334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Remove the branch. 296334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin I->eraseFromParent(); 297334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 298334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin I = MBB.end(); 299334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 300334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (I == MBB.begin()) return 1; 301334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin --I; 3025ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng if (!isCondBranchOpcode(I->getOpcode())) 303334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 1; 304334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 305334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Remove the branch. 306334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin I->eraseFromParent(); 307334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 2; 308334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 309334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 310334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinunsigned 311334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinARMBaseInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 312334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineBasicBlock *FBB, 313334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const SmallVectorImpl<MachineOperand> &Cond) const { 314334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // FIXME this should probably have a DebugLoc argument 315c7f3ace20c325521c68335a1689645b43b06ddf0Chris Lattner DebugLoc dl; 3166495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 3176495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ARMFunctionInfo *AFI = MBB.getParent()->getInfo<ARMFunctionInfo>(); 3186495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng int BOpc = !AFI->isThumbFunction() 3196495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ? ARM::B : (AFI->isThumb2Function() ? ARM::t2B : ARM::tB); 3206495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng int BccOpc = !AFI->isThumbFunction() 3216495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ? ARM::Bcc : (AFI->isThumb2Function() ? ARM::t2Bcc : ARM::tBcc); 322334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 323334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Shouldn't be a fall through. 324334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin assert(TBB && "InsertBranch must not be told to insert a fallthrough"); 325334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin assert((Cond.size() == 2 || Cond.size() == 0) && 326334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin "ARM branch conditions have two components!"); 327334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 328334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (FBB == 0) { 329334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (Cond.empty()) // Unconditional branch? 330334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin BuildMI(&MBB, dl, get(BOpc)).addMBB(TBB); 331334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin else 332334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin BuildMI(&MBB, dl, get(BccOpc)).addMBB(TBB) 333334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()); 334334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 1; 335334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 336334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 337334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Two-way conditional branch. 338334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin BuildMI(&MBB, dl, get(BccOpc)).addMBB(TBB) 339334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()); 340334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin BuildMI(&MBB, dl, get(BOpc)).addMBB(FBB); 341334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 2; 342334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 343334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 344334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinbool ARMBaseInstrInfo:: 345334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const { 346334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin ARMCC::CondCodes CC = (ARMCC::CondCodes)(int)Cond[0].getImm(); 347334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin Cond[0].setImm(ARMCC::getOppositeCondition(CC)); 348334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 349334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 350334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 351334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinbool ARMBaseInstrInfo:: 352334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinPredicateInstruction(MachineInstr *MI, 353334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const SmallVectorImpl<MachineOperand> &Pred) const { 354334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned Opc = MI->getOpcode(); 3555ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng if (isUncondBranchOpcode(Opc)) { 3565ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng MI->setDesc(get(getMatchingCondBranchOpcode(Opc))); 357334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI->addOperand(MachineOperand::CreateImm(Pred[0].getImm())); 358334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI->addOperand(MachineOperand::CreateReg(Pred[1].getReg(), false)); 359334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; 360334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 361334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 362334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin int PIdx = MI->findFirstPredOperandIdx(); 363334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (PIdx != -1) { 364334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineOperand &PMO = MI->getOperand(PIdx); 365334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin PMO.setImm(Pred[0].getImm()); 366334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI->getOperand(PIdx+1).setReg(Pred[1].getReg()); 367334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; 368334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 369334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 370334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 371334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 372334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinbool ARMBaseInstrInfo:: 373334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinSubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1, 374334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const SmallVectorImpl<MachineOperand> &Pred2) const { 375334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (Pred1.size() > 2 || Pred2.size() > 2) 376334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 377334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 378334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin ARMCC::CondCodes CC1 = (ARMCC::CondCodes)Pred1[0].getImm(); 379334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin ARMCC::CondCodes CC2 = (ARMCC::CondCodes)Pred2[0].getImm(); 380334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (CC1 == CC2) 381334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; 382334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 383334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin switch (CC1) { 384334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin default: 385334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 386334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMCC::AL: 387334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; 388334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMCC::HS: 389334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return CC2 == ARMCC::HI; 390334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMCC::LS: 391334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return CC2 == ARMCC::LO || CC2 == ARMCC::EQ; 392334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMCC::GE: 393334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return CC2 == ARMCC::GT; 394334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMCC::LE: 395334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return CC2 == ARMCC::LT; 396334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 397334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 398334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 399334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinbool ARMBaseInstrInfo::DefinesPredicate(MachineInstr *MI, 400334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin std::vector<MachineOperand> &Pred) const { 4018fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng // FIXME: This confuses implicit_def with optional CPSR def. 402334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const TargetInstrDesc &TID = MI->getDesc(); 403334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (!TID.getImplicitDefs() && !TID.hasOptionalDef()) 404334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 405334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 406334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool Found = false; 407334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 408334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const MachineOperand &MO = MI->getOperand(i); 409334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (MO.isReg() && MO.getReg() == ARM::CPSR) { 410334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin Pred.push_back(MO); 411334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin Found = true; 412334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 413334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 414334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 415334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return Found; 416334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 417334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 418ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng/// isPredicable - Return true if the specified instruction can be predicated. 419ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng/// By default, this returns true for every instruction with a 420ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng/// PredicateOperand. 421ac0869dc8a7986855c5557cc67d4709600158ef5Evan Chengbool ARMBaseInstrInfo::isPredicable(MachineInstr *MI) const { 422ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng const TargetInstrDesc &TID = MI->getDesc(); 423ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng if (!TID.isPredicable()) 424ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng return false; 425ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng 426ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng if ((TID.TSFlags & ARMII::DomainMask) == ARMII::DomainNEON) { 427ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng ARMFunctionInfo *AFI = 428ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng MI->getParent()->getParent()->getInfo<ARMFunctionInfo>(); 429d7f0810c934a7d13acb28c42d737ce58ec990ea8Evan Cheng return AFI->isThumb2Function(); 430ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng } 431ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng return true; 432ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng} 433334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 43456856b1f46ec1f073ceef4e826c544b8b1691608Chris Lattner/// FIXME: Works around a gcc miscompilation with -fstrict-aliasing. 43556856b1f46ec1f073ceef4e826c544b8b1691608Chris LattnerDISABLE_INLINE 436334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinstatic unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT, 43756856b1f46ec1f073ceef4e826c544b8b1691608Chris Lattner unsigned JTI); 438334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinstatic unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT, 439334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned JTI) { 44056856b1f46ec1f073ceef4e826c544b8b1691608Chris Lattner assert(JTI < JT.size()); 441334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return JT[JTI].MBBs.size(); 442334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 443334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 444334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin/// GetInstSize - Return the size of the specified MachineInstr. 445334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin/// 446334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinunsigned ARMBaseInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const { 447334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const MachineBasicBlock &MBB = *MI->getParent(); 448334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const MachineFunction *MF = MBB.getParent(); 44933adcfb4d217f5f23d9bde8ba02b8e48f9605fc5Chris Lattner const MCAsmInfo *MAI = MF->getTarget().getMCAsmInfo(); 450334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 451334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Basic size info comes from the TSFlags field. 452334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const TargetInstrDesc &TID = MI->getDesc(); 453334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned TSFlags = TID.TSFlags; 454334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 455a0ee862f2e3a0d202244e02459ddcf0dca0e8607Evan Cheng unsigned Opc = MI->getOpcode(); 456334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin switch ((TSFlags & ARMII::SizeMask) >> ARMII::SizeShift) { 457334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin default: { 458334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // If this machine instr is an inline asm, measure it. 459334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (MI->getOpcode() == ARM::INLINEASM) 46033adcfb4d217f5f23d9bde8ba02b8e48f9605fc5Chris Lattner return getInlineAsmLength(MI->getOperand(0).getSymbolName(), *MAI); 461334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (MI->isLabel()) 462334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 0; 463a0ee862f2e3a0d202244e02459ddcf0dca0e8607Evan Cheng switch (Opc) { 464334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin default: 465c23197a26f34f559ea9797de51e187087c039c42Torok Edwin llvm_unreachable("Unknown or unset size field for instr!"); 466518bb53485df640d7b7e3f6b0544099020c42aa7Chris Lattner case TargetOpcode::IMPLICIT_DEF: 467518bb53485df640d7b7e3f6b0544099020c42aa7Chris Lattner case TargetOpcode::KILL: 468518bb53485df640d7b7e3f6b0544099020c42aa7Chris Lattner case TargetOpcode::DBG_LABEL: 469518bb53485df640d7b7e3f6b0544099020c42aa7Chris Lattner case TargetOpcode::EH_LABEL: 470375be7730a6f3dee7a6dc319ee6c355a11ac99adDale Johannesen case TargetOpcode::DBG_VALUE: 471334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 0; 472334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 473334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin break; 474334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 475789476240d6b6f8ad9366cadf790a82bd41bb0b3Evan Cheng case ARMII::Size8Bytes: return 8; // ARM instruction x 2. 476789476240d6b6f8ad9366cadf790a82bd41bb0b3Evan Cheng case ARMII::Size4Bytes: return 4; // ARM / Thumb2 instruction. 477789476240d6b6f8ad9366cadf790a82bd41bb0b3Evan Cheng case ARMII::Size2Bytes: return 2; // Thumb1 instruction. 478334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMII::SizeSpecial: { 479a0ee862f2e3a0d202244e02459ddcf0dca0e8607Evan Cheng switch (Opc) { 480334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARM::CONSTPOOL_ENTRY: 481334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // If this machine instr is a constant pool entry, its size is recorded as 482334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // operand #2. 483334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return MI->getOperand(2).getImm(); 484789476240d6b6f8ad9366cadf790a82bd41bb0b3Evan Cheng case ARM::Int_eh_sjlj_setjmp: 485d100755bab38784703f677b8b8eb174b624b346bJim Grosbach case ARM::Int_eh_sjlj_setjmp_nofp: 486cdc17ebc2b2e9e18ac516b9d246a5c5a3af227d3Jim Grosbach return 24; 487d122874996a6faa8832569b632fd73a32ace7ae7Jim Grosbach case ARM::tInt_eh_sjlj_setjmp: 4885aa1684e5da9a85286bf7d29da419d261a70c2f2Jim Grosbach case ARM::t2Int_eh_sjlj_setjmp: 489d100755bab38784703f677b8b8eb174b624b346bJim Grosbach case ARM::t2Int_eh_sjlj_setjmp_nofp: 490a87ded2695e5bce30dbd0d2d2ac10c571bf1d161Jim Grosbach return 14; 491334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARM::BR_JTr: 492334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARM::BR_JTm: 493334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARM::BR_JTadd: 494a0ee862f2e3a0d202244e02459ddcf0dca0e8607Evan Cheng case ARM::tBR_JTr: 495d26b14c34cbcee1448b86b524578fc51cc979023Evan Cheng case ARM::t2BR_JT: 496d26b14c34cbcee1448b86b524578fc51cc979023Evan Cheng case ARM::t2TBB: 497d26b14c34cbcee1448b86b524578fc51cc979023Evan Cheng case ARM::t2TBH: { 498334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // These are jumptable branches, i.e. a branch followed by an inlined 499d26b14c34cbcee1448b86b524578fc51cc979023Evan Cheng // jumptable. The size is 4 + 4 * number of entries. For TBB, each 500d26b14c34cbcee1448b86b524578fc51cc979023Evan Cheng // entry is one byte; TBH two byte each. 501a0ee862f2e3a0d202244e02459ddcf0dca0e8607Evan Cheng unsigned EntrySize = (Opc == ARM::t2TBB) 502a0ee862f2e3a0d202244e02459ddcf0dca0e8607Evan Cheng ? 1 : ((Opc == ARM::t2TBH) ? 2 : 4); 503334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned NumOps = TID.getNumOperands(); 504334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineOperand JTOP = 505334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI->getOperand(NumOps - (TID.isPredicable() ? 3 : 2)); 506334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned JTI = JTOP.getIndex(); 507334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo(); 508b1e803985d3378538ae9cff7eed4102c002d1e22Chris Lattner assert(MJTI != 0); 509334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables(); 510334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin assert(JTI < JT.size()); 511334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Thumb instructions are 2 byte aligned, but JT entries are 4 byte 512334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // 4 aligned. The assembler / linker may add 2 byte padding just before 513334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // the JT entries. The size does not include this padding; the 514334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // constant islands pass does separate bookkeeping for it. 515334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // FIXME: If we know the size of the function is less than (1 << 16) *2 516334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // bytes, we can use 16-bit entries instead. Then there won't be an 517334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // alignment issue. 51825f7cfc3cccba6f569f29f79ea533bae960b93c0Evan Cheng unsigned InstSize = (Opc == ARM::tBR_JTr || Opc == ARM::t2BR_JT) ? 2 : 4; 51925f7cfc3cccba6f569f29f79ea533bae960b93c0Evan Cheng unsigned NumEntries = getNumJTEntries(JT, JTI); 52025f7cfc3cccba6f569f29f79ea533bae960b93c0Evan Cheng if (Opc == ARM::t2TBB && (NumEntries & 1)) 52125f7cfc3cccba6f569f29f79ea533bae960b93c0Evan Cheng // Make sure the instruction that follows TBB is 2-byte aligned. 52225f7cfc3cccba6f569f29f79ea533bae960b93c0Evan Cheng // FIXME: Constant island pass should insert an "ALIGN" instruction 52325f7cfc3cccba6f569f29f79ea533bae960b93c0Evan Cheng // instead. 52425f7cfc3cccba6f569f29f79ea533bae960b93c0Evan Cheng ++NumEntries; 52525f7cfc3cccba6f569f29f79ea533bae960b93c0Evan Cheng return NumEntries * EntrySize + InstSize; 526334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 527334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin default: 528334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Otherwise, pseudo-instruction sizes are zero. 529334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 0; 530334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 531334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 532334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 533334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 0; // Not reached 534334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 535334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 536334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin/// Return true if the instruction is a register to register move and 537334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin/// leave the source and dest operands in the passed parameters. 538334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin/// 539334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinbool 540334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinARMBaseInstrInfo::isMoveInstr(const MachineInstr &MI, 541334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned &SrcReg, unsigned &DstReg, 542334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned& SrcSubIdx, unsigned& DstSubIdx) const { 54368e3c6ae49ff67cba98403e43b5bd0c2499caa41Evan Cheng switch (MI.getOpcode()) { 544dced03fc846fa7cd9558ecb8e33ca98ec29bdcf0Evan Cheng default: break; 545e5165490b7ba24bb2f3043399e0d60e7f3bcf8a5Jim Grosbach case ARM::VMOVS: 54668e3c6ae49ff67cba98403e43b5bd0c2499caa41Evan Cheng case ARM::VMOVD: 547e5165490b7ba24bb2f3043399e0d60e7f3bcf8a5Jim Grosbach case ARM::VMOVDneon: 548b63387afc6b10e88631d1ef232c41ab6c18c8581Evan Cheng case ARM::VMOVQ: 549b63387afc6b10e88631d1ef232c41ab6c18c8581Evan Cheng case ARM::VMOVQQ : { 550334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin SrcReg = MI.getOperand(1).getReg(); 551334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin DstReg = MI.getOperand(0).getReg(); 552b63387afc6b10e88631d1ef232c41ab6c18c8581Evan Cheng SrcSubIdx = MI.getOperand(1).getSubReg(); 553b63387afc6b10e88631d1ef232c41ab6c18c8581Evan Cheng DstSubIdx = MI.getOperand(0).getSubReg(); 554334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; 555334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 55668e3c6ae49ff67cba98403e43b5bd0c2499caa41Evan Cheng case ARM::MOVr: 55768e3c6ae49ff67cba98403e43b5bd0c2499caa41Evan Cheng case ARM::tMOVr: 55868e3c6ae49ff67cba98403e43b5bd0c2499caa41Evan Cheng case ARM::tMOVgpr2tgpr: 55968e3c6ae49ff67cba98403e43b5bd0c2499caa41Evan Cheng case ARM::tMOVtgpr2gpr: 56068e3c6ae49ff67cba98403e43b5bd0c2499caa41Evan Cheng case ARM::tMOVgpr2gpr: 56168e3c6ae49ff67cba98403e43b5bd0c2499caa41Evan Cheng case ARM::t2MOVr: { 562334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin assert(MI.getDesc().getNumOperands() >= 2 && 563334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI.getOperand(0).isReg() && 564334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI.getOperand(1).isReg() && 565334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin "Invalid ARM MOV instruction"); 566334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin SrcReg = MI.getOperand(1).getReg(); 567334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin DstReg = MI.getOperand(0).getReg(); 568b63387afc6b10e88631d1ef232c41ab6c18c8581Evan Cheng SrcSubIdx = MI.getOperand(1).getSubReg(); 569b63387afc6b10e88631d1ef232c41ab6c18c8581Evan Cheng DstSubIdx = MI.getOperand(0).getSubReg(); 570334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; 571334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 57268e3c6ae49ff67cba98403e43b5bd0c2499caa41Evan Cheng } 573334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 574334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 575334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 576334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 577764ab52dd80310a205c9888bf166d09dab858f90Jim Grosbachunsigned 578334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinARMBaseInstrInfo::isLoadFromStackSlot(const MachineInstr *MI, 579334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin int &FrameIndex) const { 580dced03fc846fa7cd9558ecb8e33ca98ec29bdcf0Evan Cheng switch (MI->getOpcode()) { 581dced03fc846fa7cd9558ecb8e33ca98ec29bdcf0Evan Cheng default: break; 582dced03fc846fa7cd9558ecb8e33ca98ec29bdcf0Evan Cheng case ARM::LDR: 583dced03fc846fa7cd9558ecb8e33ca98ec29bdcf0Evan Cheng case ARM::t2LDRs: // FIXME: don't use t2LDRs to access frame. 584334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (MI->getOperand(1).isFI() && 585334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI->getOperand(2).isReg() && 586334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI->getOperand(3).isImm() && 587334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI->getOperand(2).getReg() == 0 && 588334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI->getOperand(3).getImm() == 0) { 589334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin FrameIndex = MI->getOperand(1).getIndex(); 590334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return MI->getOperand(0).getReg(); 591334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 592dced03fc846fa7cd9558ecb8e33ca98ec29bdcf0Evan Cheng break; 593dced03fc846fa7cd9558ecb8e33ca98ec29bdcf0Evan Cheng case ARM::t2LDRi12: 594dced03fc846fa7cd9558ecb8e33ca98ec29bdcf0Evan Cheng case ARM::tRestore: 5955ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin if (MI->getOperand(1).isFI() && 5965ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin MI->getOperand(2).isImm() && 5975ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin MI->getOperand(2).getImm() == 0) { 5985ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin FrameIndex = MI->getOperand(1).getIndex(); 5995ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin return MI->getOperand(0).getReg(); 6005ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin } 601dced03fc846fa7cd9558ecb8e33ca98ec29bdcf0Evan Cheng break; 602e5165490b7ba24bb2f3043399e0d60e7f3bcf8a5Jim Grosbach case ARM::VLDRD: 603e5165490b7ba24bb2f3043399e0d60e7f3bcf8a5Jim Grosbach case ARM::VLDRS: 604334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (MI->getOperand(1).isFI() && 605334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI->getOperand(2).isImm() && 606334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI->getOperand(2).getImm() == 0) { 607334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin FrameIndex = MI->getOperand(1).getIndex(); 608334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return MI->getOperand(0).getReg(); 609334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 610dced03fc846fa7cd9558ecb8e33ca98ec29bdcf0Evan Cheng break; 611334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 612334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 613334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 0; 614334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 615334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 616334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinunsigned 617334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinARMBaseInstrInfo::isStoreToStackSlot(const MachineInstr *MI, 618334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin int &FrameIndex) const { 619dced03fc846fa7cd9558ecb8e33ca98ec29bdcf0Evan Cheng switch (MI->getOpcode()) { 620dced03fc846fa7cd9558ecb8e33ca98ec29bdcf0Evan Cheng default: break; 621dced03fc846fa7cd9558ecb8e33ca98ec29bdcf0Evan Cheng case ARM::STR: 622dced03fc846fa7cd9558ecb8e33ca98ec29bdcf0Evan Cheng case ARM::t2STRs: // FIXME: don't use t2STRs to access frame. 623334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (MI->getOperand(1).isFI() && 624334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI->getOperand(2).isReg() && 625334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI->getOperand(3).isImm() && 626334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI->getOperand(2).getReg() == 0 && 627334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI->getOperand(3).getImm() == 0) { 628334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin FrameIndex = MI->getOperand(1).getIndex(); 629334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return MI->getOperand(0).getReg(); 630334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 631dced03fc846fa7cd9558ecb8e33ca98ec29bdcf0Evan Cheng break; 632dced03fc846fa7cd9558ecb8e33ca98ec29bdcf0Evan Cheng case ARM::t2STRi12: 633dced03fc846fa7cd9558ecb8e33ca98ec29bdcf0Evan Cheng case ARM::tSpill: 6345ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin if (MI->getOperand(1).isFI() && 6355ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin MI->getOperand(2).isImm() && 6365ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin MI->getOperand(2).getImm() == 0) { 6375ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin FrameIndex = MI->getOperand(1).getIndex(); 6385ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin return MI->getOperand(0).getReg(); 6395ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin } 640dced03fc846fa7cd9558ecb8e33ca98ec29bdcf0Evan Cheng break; 641e5165490b7ba24bb2f3043399e0d60e7f3bcf8a5Jim Grosbach case ARM::VSTRD: 642e5165490b7ba24bb2f3043399e0d60e7f3bcf8a5Jim Grosbach case ARM::VSTRS: 643334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (MI->getOperand(1).isFI() && 644334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI->getOperand(2).isImm() && 645334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI->getOperand(2).getImm() == 0) { 646334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin FrameIndex = MI->getOperand(1).getIndex(); 647334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return MI->getOperand(0).getReg(); 648334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 649dced03fc846fa7cd9558ecb8e33ca98ec29bdcf0Evan Cheng break; 650334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 651334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 652334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 0; 653334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 654334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 655334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinbool 656334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinARMBaseInstrInfo::copyRegToReg(MachineBasicBlock &MBB, 657334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineBasicBlock::iterator I, 658334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned DestReg, unsigned SrcReg, 659334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const TargetRegisterClass *DestRC, 66034dcc6fadca0a1117cdbd0e9b35c991a55b6e556Dan Gohman const TargetRegisterClass *SrcRC, 66134dcc6fadca0a1117cdbd0e9b35c991a55b6e556Dan Gohman DebugLoc DL) const { 6621665b0a2246c83a2c123be105a1a167cf2b423feBob Wilson // tGPR is used sometimes in ARM instructions that need to avoid using 6631665b0a2246c83a2c123be105a1a167cf2b423feBob Wilson // certain registers. Just treat it as GPR here. 6641665b0a2246c83a2c123be105a1a167cf2b423feBob Wilson if (DestRC == ARM::tGPRRegisterClass) 6651665b0a2246c83a2c123be105a1a167cf2b423feBob Wilson DestRC = ARM::GPRRegisterClass; 6661665b0a2246c83a2c123be105a1a167cf2b423feBob Wilson if (SrcRC == ARM::tGPRRegisterClass) 6671665b0a2246c83a2c123be105a1a167cf2b423feBob Wilson SrcRC = ARM::GPRRegisterClass; 6681665b0a2246c83a2c123be105a1a167cf2b423feBob Wilson 6696755d97a62fd6796f4146833efb1051fc96a61c0Anton Korobeynikov // Allow DPR / DPR_VFP2 / DPR_8 cross-class copies. 6706755d97a62fd6796f4146833efb1051fc96a61c0Anton Korobeynikov if (DestRC == ARM::DPR_8RegisterClass) 6716755d97a62fd6796f4146833efb1051fc96a61c0Anton Korobeynikov DestRC = ARM::DPR_VFP2RegisterClass; 6726755d97a62fd6796f4146833efb1051fc96a61c0Anton Korobeynikov if (SrcRC == ARM::DPR_8RegisterClass) 6736755d97a62fd6796f4146833efb1051fc96a61c0Anton Korobeynikov SrcRC = ARM::DPR_VFP2RegisterClass; 6746755d97a62fd6796f4146833efb1051fc96a61c0Anton Korobeynikov 6756755d97a62fd6796f4146833efb1051fc96a61c0Anton Korobeynikov // Allow QPR / QPR_VFP2 / QPR_8 cross-class copies. 6766755d97a62fd6796f4146833efb1051fc96a61c0Anton Korobeynikov if (DestRC == ARM::QPR_VFP2RegisterClass || 6776755d97a62fd6796f4146833efb1051fc96a61c0Anton Korobeynikov DestRC == ARM::QPR_8RegisterClass) 6786755d97a62fd6796f4146833efb1051fc96a61c0Anton Korobeynikov DestRC = ARM::QPRRegisterClass; 6796755d97a62fd6796f4146833efb1051fc96a61c0Anton Korobeynikov if (SrcRC == ARM::QPR_VFP2RegisterClass || 6806755d97a62fd6796f4146833efb1051fc96a61c0Anton Korobeynikov SrcRC == ARM::QPR_8RegisterClass) 6816755d97a62fd6796f4146833efb1051fc96a61c0Anton Korobeynikov SrcRC = ARM::QPRRegisterClass; 6826755d97a62fd6796f4146833efb1051fc96a61c0Anton Korobeynikov 683b63387afc6b10e88631d1ef232c41ab6c18c8581Evan Cheng // Allow QQPR / QQPR_VFP2 / QQPR_8 cross-class copies. 684b63387afc6b10e88631d1ef232c41ab6c18c8581Evan Cheng if (DestRC == ARM::QQPR_VFP2RegisterClass || 685b63387afc6b10e88631d1ef232c41ab6c18c8581Evan Cheng DestRC == ARM::QQPR_8RegisterClass) 686b63387afc6b10e88631d1ef232c41ab6c18c8581Evan Cheng DestRC = ARM::QQPRRegisterClass; 687b63387afc6b10e88631d1ef232c41ab6c18c8581Evan Cheng if (SrcRC == ARM::QQPR_VFP2RegisterClass || 688b63387afc6b10e88631d1ef232c41ab6c18c8581Evan Cheng SrcRC == ARM::QQPR_8RegisterClass) 689b63387afc6b10e88631d1ef232c41ab6c18c8581Evan Cheng SrcRC = ARM::QQPRRegisterClass; 690b63387afc6b10e88631d1ef232c41ab6c18c8581Evan Cheng 6916755d97a62fd6796f4146833efb1051fc96a61c0Anton Korobeynikov // Disallow copies of unequal sizes. 6926755d97a62fd6796f4146833efb1051fc96a61c0Anton Korobeynikov if (DestRC != SrcRC && DestRC->getSize() != SrcRC->getSize()) 6936755d97a62fd6796f4146833efb1051fc96a61c0Anton Korobeynikov return false; 694b4db6a46e0de3283fa70ea0a7d3623f2e4e2d2a3Evan Cheng 6956755d97a62fd6796f4146833efb1051fc96a61c0Anton Korobeynikov if (DestRC == ARM::GPRRegisterClass) { 6966755d97a62fd6796f4146833efb1051fc96a61c0Anton Korobeynikov if (SrcRC == ARM::SPRRegisterClass) 6976755d97a62fd6796f4146833efb1051fc96a61c0Anton Korobeynikov AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VMOVRS), DestReg) 6986755d97a62fd6796f4146833efb1051fc96a61c0Anton Korobeynikov .addReg(SrcReg)); 6996755d97a62fd6796f4146833efb1051fc96a61c0Anton Korobeynikov else 7006755d97a62fd6796f4146833efb1051fc96a61c0Anton Korobeynikov AddDefaultCC(AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::MOVr), 7016755d97a62fd6796f4146833efb1051fc96a61c0Anton Korobeynikov DestReg).addReg(SrcReg))); 7026755d97a62fd6796f4146833efb1051fc96a61c0Anton Korobeynikov } else { 7036755d97a62fd6796f4146833efb1051fc96a61c0Anton Korobeynikov unsigned Opc; 7046755d97a62fd6796f4146833efb1051fc96a61c0Anton Korobeynikov 7056755d97a62fd6796f4146833efb1051fc96a61c0Anton Korobeynikov if (DestRC == ARM::SPRRegisterClass) 7066755d97a62fd6796f4146833efb1051fc96a61c0Anton Korobeynikov Opc = (SrcRC == ARM::GPRRegisterClass ? ARM::VMOVSR : ARM::VMOVS); 7076755d97a62fd6796f4146833efb1051fc96a61c0Anton Korobeynikov else if (DestRC == ARM::DPRRegisterClass) 7086755d97a62fd6796f4146833efb1051fc96a61c0Anton Korobeynikov Opc = ARM::VMOVD; 7096755d97a62fd6796f4146833efb1051fc96a61c0Anton Korobeynikov else if (DestRC == ARM::DPR_VFP2RegisterClass || 7106755d97a62fd6796f4146833efb1051fc96a61c0Anton Korobeynikov SrcRC == ARM::DPR_VFP2RegisterClass) 7116755d97a62fd6796f4146833efb1051fc96a61c0Anton Korobeynikov // Always use neon reg-reg move if source or dest is NEON-only regclass. 7126755d97a62fd6796f4146833efb1051fc96a61c0Anton Korobeynikov Opc = ARM::VMOVDneon; 7136755d97a62fd6796f4146833efb1051fc96a61c0Anton Korobeynikov else if (DestRC == ARM::QPRRegisterClass) 7146755d97a62fd6796f4146833efb1051fc96a61c0Anton Korobeynikov Opc = ARM::VMOVQ; 715b63387afc6b10e88631d1ef232c41ab6c18c8581Evan Cheng else if (DestRC == ARM::QQPRRegisterClass) 716b63387afc6b10e88631d1ef232c41ab6c18c8581Evan Cheng Opc = ARM::VMOVQQ; 7176755d97a62fd6796f4146833efb1051fc96a61c0Anton Korobeynikov else 7187bfdca0206f51132b26094c6f83a5ac97ee0f943David Goodwin return false; 719334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 720b63387afc6b10e88631d1ef232c41ab6c18c8581Evan Cheng AddDefaultPred(BuildMI(MBB, I, DL, get(Opc), DestReg).addReg(SrcReg)); 7217bfdca0206f51132b26094c6f83a5ac97ee0f943David Goodwin } 722334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 723334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; 724334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 725334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 726c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Chengstatic const 727c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan ChengMachineInstrBuilder &AddDReg(MachineInstrBuilder &MIB, 728c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Cheng unsigned Reg, unsigned SubIdx, unsigned State, 729c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Cheng const TargetRegisterInfo *TRI) { 730c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Cheng if (!SubIdx) 731c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Cheng return MIB.addReg(Reg, State); 732c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Cheng 733c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Cheng if (TargetRegisterInfo::isPhysicalRegister(Reg)) 734c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Cheng return MIB.addReg(TRI->getSubReg(Reg, SubIdx), State); 735c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Cheng return MIB.addReg(Reg, State, SubIdx); 736c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Cheng} 737c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Cheng 738334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinvoid ARMBaseInstrInfo:: 739334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinstoreRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 740334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned SrcReg, bool isKill, int FI, 741746ad69e088176819981b4b2c5ac8dcd49f5e60eEvan Cheng const TargetRegisterClass *RC, 742746ad69e088176819981b4b2c5ac8dcd49f5e60eEvan Cheng const TargetRegisterInfo *TRI) const { 743c7f3ace20c325521c68335a1689645b43b06ddf0Chris Lattner DebugLoc DL; 744334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (I != MBB.end()) DL = I->getDebugLoc(); 745249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MachineFunction &MF = *MBB.getParent(); 746249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MachineFrameInfo &MFI = *MF.getFrameInfo(); 74731bc849123011b8eae6bb3c79876d9a3c26a6a1dJim Grosbach unsigned Align = MFI.getObjectAlignment(FI); 748249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov 749249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MachineMemOperand *MMO = 750ff89dcb06fbd103373436e2d0ae85f252fae2254Evan Cheng MF.getMachineMemOperand(PseudoSourceValue::getFixedStack(FI), 751249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MachineMemOperand::MOStore, 0, 752249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MFI.getObjectSize(FI), 75331bc849123011b8eae6bb3c79876d9a3c26a6a1dJim Grosbach Align); 754334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 7550eb0c7401c34c0b4604f732ce54db995eead14e6Bob Wilson // tGPR is used sometimes in ARM instructions that need to avoid using 7560eb0c7401c34c0b4604f732ce54db995eead14e6Bob Wilson // certain registers. Just treat it as GPR here. 7570eb0c7401c34c0b4604f732ce54db995eead14e6Bob Wilson if (RC == ARM::tGPRRegisterClass) 7580eb0c7401c34c0b4604f732ce54db995eead14e6Bob Wilson RC = ARM::GPRRegisterClass; 7590eb0c7401c34c0b4604f732ce54db995eead14e6Bob Wilson 760334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (RC == ARM::GPRRegisterClass) { 7615732ca084aaa0cd26149e50dd4b487efff37fe41Evan Cheng AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::STR)) 762334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(SrcReg, getKillRegState(isKill)) 763249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov .addFrameIndex(FI).addReg(0).addImm(0).addMemOperand(MMO)); 764d31c5496d7e1580058b5c6fbc8fd537a641ea590Evan Cheng } else if (RC == ARM::SPRRegisterClass) { 765d31c5496d7e1580058b5c6fbc8fd537a641ea590Evan Cheng AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTRS)) 766d31c5496d7e1580058b5c6fbc8fd537a641ea590Evan Cheng .addReg(SrcReg, getKillRegState(isKill)) 767d31c5496d7e1580058b5c6fbc8fd537a641ea590Evan Cheng .addFrameIndex(FI).addImm(0).addMemOperand(MMO)); 7686ca0b9e7220911a6d1fccf34e532e69c7e37cd2fAnton Korobeynikov } else if (RC == ARM::DPRRegisterClass || 7696ca0b9e7220911a6d1fccf34e532e69c7e37cd2fAnton Korobeynikov RC == ARM::DPR_VFP2RegisterClass || 7706ca0b9e7220911a6d1fccf34e532e69c7e37cd2fAnton Korobeynikov RC == ARM::DPR_8RegisterClass) { 771e5165490b7ba24bb2f3043399e0d60e7f3bcf8a5Jim Grosbach AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTRD)) 772334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(SrcReg, getKillRegState(isKill)) 773249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov .addFrameIndex(FI).addImm(0).addMemOperand(MMO)); 774b63387afc6b10e88631d1ef232c41ab6c18c8581Evan Cheng } else if (RC == ARM::QPRRegisterClass || 775b63387afc6b10e88631d1ef232c41ab6c18c8581Evan Cheng RC == ARM::QPR_VFP2RegisterClass || 776b63387afc6b10e88631d1ef232c41ab6c18c8581Evan Cheng RC == ARM::QPR_8RegisterClass) { 777baf31088f1472f48ea5ae81f0b93636cc44ca444Anton Korobeynikov // FIXME: Neon instructions should support predicates 778b63387afc6b10e88631d1ef232c41ab6c18c8581Evan Cheng if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) { 779c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Cheng MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::VST1q64)) 780c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Cheng .addFrameIndex(FI).addImm(128); 781c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Cheng MIB = AddDReg(MIB, SrcReg, ARM::DSUBREG_0, getKillRegState(isKill), TRI); 782c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Cheng MIB = AddDReg(MIB, SrcReg, ARM::DSUBREG_1, 0, TRI); 783c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Cheng AddDefaultPred(MIB.addMemOperand(MMO)); 78431bc849123011b8eae6bb3c79876d9a3c26a6a1dJim Grosbach } else { 785c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Cheng AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMQ)) 786c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Cheng .addReg(SrcReg, getKillRegState(isKill)) 787df9a4f0591e3f3e7ae3b3c119a0c8cf678594f6bBob Wilson .addFrameIndex(FI) 788df9a4f0591e3f3e7ae3b3c119a0c8cf678594f6bBob Wilson .addImm(ARM_AM::getAM5Opc(ARM_AM::ia, 4)) 789df9a4f0591e3f3e7ae3b3c119a0c8cf678594f6bBob Wilson .addMemOperand(MMO)); 79031bc849123011b8eae6bb3c79876d9a3c26a6a1dJim Grosbach } 791b63387afc6b10e88631d1ef232c41ab6c18c8581Evan Cheng } else { 792b63387afc6b10e88631d1ef232c41ab6c18c8581Evan Cheng assert((RC == ARM::QQPRRegisterClass || 793b63387afc6b10e88631d1ef232c41ab6c18c8581Evan Cheng RC == ARM::QQPR_VFP2RegisterClass || 794b63387afc6b10e88631d1ef232c41ab6c18c8581Evan Cheng RC == ARM::QQPR_8RegisterClass) && "Unknown regclass!"); 795b63387afc6b10e88631d1ef232c41ab6c18c8581Evan Cheng llvm_unreachable("Not yet implemented!"); 796334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 797334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 798334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 799334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinvoid ARMBaseInstrInfo:: 800334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinloadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 801334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned DestReg, int FI, 802746ad69e088176819981b4b2c5ac8dcd49f5e60eEvan Cheng const TargetRegisterClass *RC, 803746ad69e088176819981b4b2c5ac8dcd49f5e60eEvan Cheng const TargetRegisterInfo *TRI) const { 804c7f3ace20c325521c68335a1689645b43b06ddf0Chris Lattner DebugLoc DL; 805334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (I != MBB.end()) DL = I->getDebugLoc(); 806249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MachineFunction &MF = *MBB.getParent(); 807249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MachineFrameInfo &MFI = *MF.getFrameInfo(); 80831bc849123011b8eae6bb3c79876d9a3c26a6a1dJim Grosbach unsigned Align = MFI.getObjectAlignment(FI); 809249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov 810249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MachineMemOperand *MMO = 811ff89dcb06fbd103373436e2d0ae85f252fae2254Evan Cheng MF.getMachineMemOperand(PseudoSourceValue::getFixedStack(FI), 812249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MachineMemOperand::MOLoad, 0, 813249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MFI.getObjectSize(FI), 81431bc849123011b8eae6bb3c79876d9a3c26a6a1dJim Grosbach Align); 815334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 8160eb0c7401c34c0b4604f732ce54db995eead14e6Bob Wilson // tGPR is used sometimes in ARM instructions that need to avoid using 8170eb0c7401c34c0b4604f732ce54db995eead14e6Bob Wilson // certain registers. Just treat it as GPR here. 8180eb0c7401c34c0b4604f732ce54db995eead14e6Bob Wilson if (RC == ARM::tGPRRegisterClass) 8190eb0c7401c34c0b4604f732ce54db995eead14e6Bob Wilson RC = ARM::GPRRegisterClass; 8200eb0c7401c34c0b4604f732ce54db995eead14e6Bob Wilson 821334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (RC == ARM::GPRRegisterClass) { 8225732ca084aaa0cd26149e50dd4b487efff37fe41Evan Cheng AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::LDR), DestReg) 823249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov .addFrameIndex(FI).addReg(0).addImm(0).addMemOperand(MMO)); 824d31c5496d7e1580058b5c6fbc8fd537a641ea590Evan Cheng } else if (RC == ARM::SPRRegisterClass) { 825d31c5496d7e1580058b5c6fbc8fd537a641ea590Evan Cheng AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRS), DestReg) 826d31c5496d7e1580058b5c6fbc8fd537a641ea590Evan Cheng .addFrameIndex(FI).addImm(0).addMemOperand(MMO)); 8276ca0b9e7220911a6d1fccf34e532e69c7e37cd2fAnton Korobeynikov } else if (RC == ARM::DPRRegisterClass || 8286ca0b9e7220911a6d1fccf34e532e69c7e37cd2fAnton Korobeynikov RC == ARM::DPR_VFP2RegisterClass || 8296ca0b9e7220911a6d1fccf34e532e69c7e37cd2fAnton Korobeynikov RC == ARM::DPR_8RegisterClass) { 830e5165490b7ba24bb2f3043399e0d60e7f3bcf8a5Jim Grosbach AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRD), DestReg) 831249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov .addFrameIndex(FI).addImm(0).addMemOperand(MMO)); 832b63387afc6b10e88631d1ef232c41ab6c18c8581Evan Cheng } else if (RC == ARM::QPRRegisterClass || 833b63387afc6b10e88631d1ef232c41ab6c18c8581Evan Cheng RC == ARM::QPR_VFP2RegisterClass || 834b63387afc6b10e88631d1ef232c41ab6c18c8581Evan Cheng RC == ARM::QPR_8RegisterClass) { 835b63387afc6b10e88631d1ef232c41ab6c18c8581Evan Cheng if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) { 836c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Cheng MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::VLD1q64)); 837c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Cheng MIB = AddDReg(MIB, DestReg, ARM::DSUBREG_0, RegState::Define, TRI); 838c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Cheng MIB = AddDReg(MIB, DestReg, ARM::DSUBREG_1, RegState::Define, TRI); 839c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Cheng AddDefaultPred(MIB.addFrameIndex(FI).addImm(128).addMemOperand(MMO)); 84031bc849123011b8eae6bb3c79876d9a3c26a6a1dJim Grosbach } else { 841c289a0252bba42248d7b11699dda27feca8860b6Bob Wilson AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMQ), DestReg) 842df9a4f0591e3f3e7ae3b3c119a0c8cf678594f6bBob Wilson .addFrameIndex(FI) 843df9a4f0591e3f3e7ae3b3c119a0c8cf678594f6bBob Wilson .addImm(ARM_AM::getAM5Opc(ARM_AM::ia, 4)) 844df9a4f0591e3f3e7ae3b3c119a0c8cf678594f6bBob Wilson .addMemOperand(MMO)); 84531bc849123011b8eae6bb3c79876d9a3c26a6a1dJim Grosbach } 846b63387afc6b10e88631d1ef232c41ab6c18c8581Evan Cheng } else { 847b63387afc6b10e88631d1ef232c41ab6c18c8581Evan Cheng assert((RC == ARM::QQPRRegisterClass || 848b63387afc6b10e88631d1ef232c41ab6c18c8581Evan Cheng RC == ARM::QQPR_VFP2RegisterClass || 849b63387afc6b10e88631d1ef232c41ab6c18c8581Evan Cheng RC == ARM::QQPR_8RegisterClass) && "Unknown regclass!"); 850b63387afc6b10e88631d1ef232c41ab6c18c8581Evan Cheng llvm_unreachable("Not yet implemented!"); 851334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 852334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 853334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 85462b50656ceb854eb0be265d63b2a1d46e7400d8aEvan ChengMachineInstr* 85562b50656ceb854eb0be265d63b2a1d46e7400d8aEvan ChengARMBaseInstrInfo::emitFrameIndexDebugValue(MachineFunction &MF, 8568601a3d4decff0a380e059b037dabf71075497d3Evan Cheng int FrameIx, uint64_t Offset, 85762b50656ceb854eb0be265d63b2a1d46e7400d8aEvan Cheng const MDNode *MDPtr, 85862b50656ceb854eb0be265d63b2a1d46e7400d8aEvan Cheng DebugLoc DL) const { 85962b50656ceb854eb0be265d63b2a1d46e7400d8aEvan Cheng MachineInstrBuilder MIB = BuildMI(MF, DL, get(ARM::DBG_VALUE)) 86062b50656ceb854eb0be265d63b2a1d46e7400d8aEvan Cheng .addFrameIndex(FrameIx).addImm(0).addImm(Offset).addMetadata(MDPtr); 86162b50656ceb854eb0be265d63b2a1d46e7400d8aEvan Cheng return &*MIB; 86262b50656ceb854eb0be265d63b2a1d46e7400d8aEvan Cheng} 86362b50656ceb854eb0be265d63b2a1d46e7400d8aEvan Cheng 864334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinMachineInstr *ARMBaseInstrInfo:: 865334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinfoldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI, 866334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const SmallVectorImpl<unsigned> &Ops, int FI) const { 867334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (Ops.size() != 1) return NULL; 868334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 869334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned OpNum = Ops[0]; 870334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned Opc = MI->getOpcode(); 871334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineInstr *NewMI = NULL; 87219068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng if (Opc == ARM::MOVr || Opc == ARM::t2MOVr) { 873334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // If it is updating CPSR, then it cannot be folded. 87419068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng if (MI->getOperand(4).getReg() == ARM::CPSR && !MI->getOperand(4).isDead()) 87519068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng return NULL; 87619068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng unsigned Pred = MI->getOperand(2).getImm(); 87719068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng unsigned PredReg = MI->getOperand(3).getReg(); 87819068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng if (OpNum == 0) { // move -> store 87919068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng unsigned SrcReg = MI->getOperand(1).getReg(); 880ed3ad212ec34fa2866fb70f9e52ddda31032ea3bEvan Cheng unsigned SrcSubReg = MI->getOperand(1).getSubReg(); 88119068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng bool isKill = MI->getOperand(1).isKill(); 88219068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng bool isUndef = MI->getOperand(1).isUndef(); 88319068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng if (Opc == ARM::MOVr) 88419068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::STR)) 885ed3ad212ec34fa2866fb70f9e52ddda31032ea3bEvan Cheng .addReg(SrcReg, 886ed3ad212ec34fa2866fb70f9e52ddda31032ea3bEvan Cheng getKillRegState(isKill) | getUndefRegState(isUndef), 887ed3ad212ec34fa2866fb70f9e52ddda31032ea3bEvan Cheng SrcSubReg) 88819068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng .addFrameIndex(FI).addReg(0).addImm(0).addImm(Pred).addReg(PredReg); 88919068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng else // ARM::t2MOVr 89019068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::t2STRi12)) 891ed3ad212ec34fa2866fb70f9e52ddda31032ea3bEvan Cheng .addReg(SrcReg, 892ed3ad212ec34fa2866fb70f9e52ddda31032ea3bEvan Cheng getKillRegState(isKill) | getUndefRegState(isUndef), 893ed3ad212ec34fa2866fb70f9e52ddda31032ea3bEvan Cheng SrcSubReg) 89419068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg); 89519068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng } else { // move -> load 89619068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng unsigned DstReg = MI->getOperand(0).getReg(); 897ed3ad212ec34fa2866fb70f9e52ddda31032ea3bEvan Cheng unsigned DstSubReg = MI->getOperand(0).getSubReg(); 89819068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng bool isDead = MI->getOperand(0).isDead(); 89919068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng bool isUndef = MI->getOperand(0).isUndef(); 90019068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng if (Opc == ARM::MOVr) 90119068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::LDR)) 90219068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng .addReg(DstReg, 90319068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng RegState::Define | 90419068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng getDeadRegState(isDead) | 905ed3ad212ec34fa2866fb70f9e52ddda31032ea3bEvan Cheng getUndefRegState(isUndef), DstSubReg) 90619068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng .addFrameIndex(FI).addReg(0).addImm(0).addImm(Pred).addReg(PredReg); 90719068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng else // ARM::t2MOVr 90819068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::t2LDRi12)) 90919068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng .addReg(DstReg, 91019068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng RegState::Define | 91119068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng getDeadRegState(isDead) | 912ed3ad212ec34fa2866fb70f9e52ddda31032ea3bEvan Cheng getUndefRegState(isUndef), DstSubReg) 91319068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg); 914334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 91519068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng } else if (Opc == ARM::tMOVgpr2gpr || 91619068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng Opc == ARM::tMOVtgpr2gpr || 91719068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng Opc == ARM::tMOVgpr2tgpr) { 91819068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng if (OpNum == 0) { // move -> store 91919068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng unsigned SrcReg = MI->getOperand(1).getReg(); 920ed3ad212ec34fa2866fb70f9e52ddda31032ea3bEvan Cheng unsigned SrcSubReg = MI->getOperand(1).getSubReg(); 92119068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng bool isKill = MI->getOperand(1).isKill(); 92219068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng bool isUndef = MI->getOperand(1).isUndef(); 92319068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::t2STRi12)) 924ed3ad212ec34fa2866fb70f9e52ddda31032ea3bEvan Cheng .addReg(SrcReg, 925ed3ad212ec34fa2866fb70f9e52ddda31032ea3bEvan Cheng getKillRegState(isKill) | getUndefRegState(isUndef), 926ed3ad212ec34fa2866fb70f9e52ddda31032ea3bEvan Cheng SrcSubReg) 92719068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng .addFrameIndex(FI).addImm(0).addImm(ARMCC::AL).addReg(0); 92819068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng } else { // move -> load 92919068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng unsigned DstReg = MI->getOperand(0).getReg(); 930ed3ad212ec34fa2866fb70f9e52ddda31032ea3bEvan Cheng unsigned DstSubReg = MI->getOperand(0).getSubReg(); 93119068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng bool isDead = MI->getOperand(0).isDead(); 93219068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng bool isUndef = MI->getOperand(0).isUndef(); 93319068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::t2LDRi12)) 93419068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng .addReg(DstReg, 93519068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng RegState::Define | 93619068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng getDeadRegState(isDead) | 937ed3ad212ec34fa2866fb70f9e52ddda31032ea3bEvan Cheng getUndefRegState(isUndef), 938ed3ad212ec34fa2866fb70f9e52ddda31032ea3bEvan Cheng DstSubReg) 93919068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng .addFrameIndex(FI).addImm(0).addImm(ARMCC::AL).addReg(0); 94019068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng } 941e5165490b7ba24bb2f3043399e0d60e7f3bcf8a5Jim Grosbach } else if (Opc == ARM::VMOVS) { 942334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned Pred = MI->getOperand(2).getImm(); 943334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned PredReg = MI->getOperand(3).getReg(); 944334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (OpNum == 0) { // move -> store 945334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned SrcReg = MI->getOperand(1).getReg(); 946ed3ad212ec34fa2866fb70f9e52ddda31032ea3bEvan Cheng unsigned SrcSubReg = MI->getOperand(1).getSubReg(); 947334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool isKill = MI->getOperand(1).isKill(); 948334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool isUndef = MI->getOperand(1).isUndef(); 949e5165490b7ba24bb2f3043399e0d60e7f3bcf8a5Jim Grosbach NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::VSTRS)) 950ed3ad212ec34fa2866fb70f9e52ddda31032ea3bEvan Cheng .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef), 951ed3ad212ec34fa2866fb70f9e52ddda31032ea3bEvan Cheng SrcSubReg) 952334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addFrameIndex(FI) 953334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addImm(0).addImm(Pred).addReg(PredReg); 954334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } else { // move -> load 955334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned DstReg = MI->getOperand(0).getReg(); 956ed3ad212ec34fa2866fb70f9e52ddda31032ea3bEvan Cheng unsigned DstSubReg = MI->getOperand(0).getSubReg(); 957334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool isDead = MI->getOperand(0).isDead(); 958334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool isUndef = MI->getOperand(0).isUndef(); 959e5165490b7ba24bb2f3043399e0d60e7f3bcf8a5Jim Grosbach NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::VLDRS)) 960334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(DstReg, 961334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin RegState::Define | 962334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin getDeadRegState(isDead) | 963ed3ad212ec34fa2866fb70f9e52ddda31032ea3bEvan Cheng getUndefRegState(isUndef), 964ed3ad212ec34fa2866fb70f9e52ddda31032ea3bEvan Cheng DstSubReg) 965334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg); 966334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 967334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 968e5165490b7ba24bb2f3043399e0d60e7f3bcf8a5Jim Grosbach else if (Opc == ARM::VMOVD) { 969334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned Pred = MI->getOperand(2).getImm(); 970334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned PredReg = MI->getOperand(3).getReg(); 971334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (OpNum == 0) { // move -> store 972334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned SrcReg = MI->getOperand(1).getReg(); 973ed3ad212ec34fa2866fb70f9e52ddda31032ea3bEvan Cheng unsigned SrcSubReg = MI->getOperand(1).getSubReg(); 974334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool isKill = MI->getOperand(1).isKill(); 975334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool isUndef = MI->getOperand(1).isUndef(); 976e5165490b7ba24bb2f3043399e0d60e7f3bcf8a5Jim Grosbach NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::VSTRD)) 977ed3ad212ec34fa2866fb70f9e52ddda31032ea3bEvan Cheng .addReg(SrcReg, 978ed3ad212ec34fa2866fb70f9e52ddda31032ea3bEvan Cheng getKillRegState(isKill) | getUndefRegState(isUndef), 979ed3ad212ec34fa2866fb70f9e52ddda31032ea3bEvan Cheng SrcSubReg) 980334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg); 981334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } else { // move -> load 982334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned DstReg = MI->getOperand(0).getReg(); 983ed3ad212ec34fa2866fb70f9e52ddda31032ea3bEvan Cheng unsigned DstSubReg = MI->getOperand(0).getSubReg(); 984334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool isDead = MI->getOperand(0).isDead(); 985334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool isUndef = MI->getOperand(0).isUndef(); 986e5165490b7ba24bb2f3043399e0d60e7f3bcf8a5Jim Grosbach NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::VLDRD)) 987334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(DstReg, 988334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin RegState::Define | 989334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin getDeadRegState(isDead) | 990ed3ad212ec34fa2866fb70f9e52ddda31032ea3bEvan Cheng getUndefRegState(isUndef), 991ed3ad212ec34fa2866fb70f9e52ddda31032ea3bEvan Cheng DstSubReg) 992334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg); 993334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 994334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 995334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 996334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return NewMI; 997334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 998334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 999764ab52dd80310a205c9888bf166d09dab858f90Jim GrosbachMachineInstr* 1000334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinARMBaseInstrInfo::foldMemoryOperandImpl(MachineFunction &MF, 1001334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineInstr* MI, 1002334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const SmallVectorImpl<unsigned> &Ops, 1003334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineInstr* LoadMI) const { 10041f5c9887544ac2cb39d48e35cc6fa7a7b73ed3b0Evan Cheng // FIXME 1005334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 0; 1006334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 1007334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 1008334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinbool 1009334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinARMBaseInstrInfo::canFoldMemoryOperand(const MachineInstr *MI, 1010229464564243b24fb12cece515d727673e726994Evan Cheng const SmallVectorImpl<unsigned> &Ops) const { 1011334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (Ops.size() != 1) return false; 1012334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 1013334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned Opc = MI->getOpcode(); 10145732ca084aaa0cd26149e50dd4b487efff37fe41Evan Cheng if (Opc == ARM::MOVr || Opc == ARM::t2MOVr) { 1015334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // If it is updating CPSR, then it cannot be folded. 1016229464564243b24fb12cece515d727673e726994Evan Cheng return MI->getOperand(4).getReg() != ARM::CPSR || 1017229464564243b24fb12cece515d727673e726994Evan Cheng MI->getOperand(4).isDead(); 101819068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng } else if (Opc == ARM::tMOVgpr2gpr || 101919068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng Opc == ARM::tMOVtgpr2gpr || 102019068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng Opc == ARM::tMOVgpr2tgpr) { 102119068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng return true; 1022e5165490b7ba24bb2f3043399e0d60e7f3bcf8a5Jim Grosbach } else if (Opc == ARM::VMOVS || Opc == ARM::VMOVD) { 1023334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; 1024e5165490b7ba24bb2f3043399e0d60e7f3bcf8a5Jim Grosbach } else if (Opc == ARM::VMOVDneon || Opc == ARM::VMOVQ) { 1025334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; // FIXME 1026334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 1027334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 1028334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 1029334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 10305ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng 103130ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen/// Create a copy of a const pool value. Update CPI to the new index and return 103230ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen/// the label UID. 103330ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesenstatic unsigned duplicateCPV(MachineFunction &MF, unsigned &CPI) { 103430ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen MachineConstantPool *MCP = MF.getConstantPool(); 103530ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 103630ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen 103730ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPI]; 103830ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen assert(MCPE.isMachineConstantPoolEntry() && 103930ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen "Expecting a machine constantpool entry!"); 104030ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen ARMConstantPoolValue *ACPV = 104130ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal); 104230ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen 104330ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen unsigned PCLabelId = AFI->createConstPoolEntryUId(); 104430ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen ARMConstantPoolValue *NewCPV = 0; 104530ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen if (ACPV->isGlobalValue()) 104630ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen NewCPV = new ARMConstantPoolValue(ACPV->getGV(), PCLabelId, 104730ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen ARMCP::CPValue, 4); 104830ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen else if (ACPV->isExtSymbol()) 104930ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen NewCPV = new ARMConstantPoolValue(MF.getFunction()->getContext(), 105030ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen ACPV->getSymbol(), PCLabelId, 4); 105130ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen else if (ACPV->isBlockAddress()) 105230ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen NewCPV = new ARMConstantPoolValue(ACPV->getBlockAddress(), PCLabelId, 105330ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen ARMCP::CPBlockAddress, 4); 105430ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen else 105530ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen llvm_unreachable("Unexpected ARM constantpool value type!!"); 105630ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen CPI = MCP->getConstantPoolIndex(NewCPV, MCPE.getAlignment()); 105730ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen return PCLabelId; 105830ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen} 105930ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen 1060fdc834046efd427d474e3b899ec69354c05071e0Evan Chengvoid ARMBaseInstrInfo:: 1061fdc834046efd427d474e3b899ec69354c05071e0Evan ChengreMaterialize(MachineBasicBlock &MBB, 1062fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng MachineBasicBlock::iterator I, 1063fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng unsigned DestReg, unsigned SubIdx, 1064d57cdd5683ea926e489067364fb7ffe5fd5d35eeEvan Cheng const MachineInstr *Orig, 1065d57cdd5683ea926e489067364fb7ffe5fd5d35eeEvan Cheng const TargetRegisterInfo *TRI) const { 1066d57cdd5683ea926e489067364fb7ffe5fd5d35eeEvan Cheng if (SubIdx && TargetRegisterInfo::isPhysicalRegister(DestReg)) { 1067d57cdd5683ea926e489067364fb7ffe5fd5d35eeEvan Cheng DestReg = TRI->getSubReg(DestReg, SubIdx); 1068d57cdd5683ea926e489067364fb7ffe5fd5d35eeEvan Cheng SubIdx = 0; 1069d57cdd5683ea926e489067364fb7ffe5fd5d35eeEvan Cheng } 1070d57cdd5683ea926e489067364fb7ffe5fd5d35eeEvan Cheng 1071fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng unsigned Opcode = Orig->getOpcode(); 1072fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng switch (Opcode) { 1073fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng default: { 1074fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig); 1075fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng MI->getOperand(0).setReg(DestReg); 1076fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng MBB.insert(I, MI); 1077fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng break; 1078fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng } 1079fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng case ARM::tLDRpci_pic: 1080fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng case ARM::t2LDRpci_pic: { 1081fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng MachineFunction &MF = *MBB.getParent(); 1082fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng unsigned CPI = Orig->getOperand(1).getIndex(); 108330ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen unsigned PCLabelId = duplicateCPV(MF, CPI); 1084fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng MachineInstrBuilder MIB = BuildMI(MBB, I, Orig->getDebugLoc(), get(Opcode), 1085fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng DestReg) 1086fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng .addConstantPoolIndex(CPI).addImm(PCLabelId); 1087fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng (*MIB).setMemRefs(Orig->memoperands_begin(), Orig->memoperands_end()); 1088fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng break; 1089fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng } 1090fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng } 1091fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng 1092fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng MachineInstr *NewMI = prior(I); 1093fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng NewMI->getOperand(0).setSubReg(SubIdx); 1094fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng} 1095fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng 109630ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund OlesenMachineInstr * 109730ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund OlesenARMBaseInstrInfo::duplicate(MachineInstr *Orig, MachineFunction &MF) const { 109830ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen MachineInstr *MI = TargetInstrInfoImpl::duplicate(Orig, MF); 109930ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen switch(Orig->getOpcode()) { 110030ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen case ARM::tLDRpci_pic: 110130ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen case ARM::t2LDRpci_pic: { 110230ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen unsigned CPI = Orig->getOperand(1).getIndex(); 110330ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen unsigned PCLabelId = duplicateCPV(MF, CPI); 110430ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen Orig->getOperand(1).setIndex(CPI); 110530ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen Orig->getOperand(2).setImm(PCLabelId); 110630ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen break; 110730ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen } 110830ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen } 110930ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen return MI; 111030ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen} 111130ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen 1112506049f29f4f202a8e45feb916cc0264440a7f6dEvan Chengbool ARMBaseInstrInfo::produceSameValue(const MachineInstr *MI0, 1113506049f29f4f202a8e45feb916cc0264440a7f6dEvan Cheng const MachineInstr *MI1) const { 1114d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng int Opcode = MI0->getOpcode(); 11159b82425cb0105fd5704f6b9bcd5e7693b05b1759Evan Cheng if (Opcode == ARM::t2LDRpci || 11169b82425cb0105fd5704f6b9bcd5e7693b05b1759Evan Cheng Opcode == ARM::t2LDRpci_pic || 11179b82425cb0105fd5704f6b9bcd5e7693b05b1759Evan Cheng Opcode == ARM::tLDRpci || 11189b82425cb0105fd5704f6b9bcd5e7693b05b1759Evan Cheng Opcode == ARM::tLDRpci_pic) { 1119d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng if (MI1->getOpcode() != Opcode) 1120d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng return false; 1121d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng if (MI0->getNumOperands() != MI1->getNumOperands()) 1122d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng return false; 1123d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng 1124d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng const MachineOperand &MO0 = MI0->getOperand(1); 1125d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng const MachineOperand &MO1 = MI1->getOperand(1); 1126d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng if (MO0.getOffset() != MO1.getOffset()) 1127d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng return false; 1128d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng 1129d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng const MachineFunction *MF = MI0->getParent()->getParent(); 1130d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng const MachineConstantPool *MCP = MF->getConstantPool(); 1131d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng int CPI0 = MO0.getIndex(); 1132d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng int CPI1 = MO1.getIndex(); 1133d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng const MachineConstantPoolEntry &MCPE0 = MCP->getConstants()[CPI0]; 1134d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng const MachineConstantPoolEntry &MCPE1 = MCP->getConstants()[CPI1]; 1135d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng ARMConstantPoolValue *ACPV0 = 1136d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng static_cast<ARMConstantPoolValue*>(MCPE0.Val.MachineCPVal); 1137d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng ARMConstantPoolValue *ACPV1 = 1138d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng static_cast<ARMConstantPoolValue*>(MCPE1.Val.MachineCPVal); 1139d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng return ACPV0->hasSameValue(ACPV1); 1140d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng } 1141d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng 1142506049f29f4f202a8e45feb916cc0264440a7f6dEvan Cheng return MI0->isIdenticalTo(MI1, MachineInstr::IgnoreVRegDefs); 1143d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng} 1144d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng 11458fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng/// getInstrPredicate - If instruction is predicated, returns its predicate 11468fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng/// condition, otherwise returns AL. It also returns the condition code 11478fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng/// register by reference. 11485adb66a646e2ec32265263739f5b01c3f50c176aEvan ChengARMCC::CondCodes 11495adb66a646e2ec32265263739f5b01c3f50c176aEvan Chengllvm::getInstrPredicate(const MachineInstr *MI, unsigned &PredReg) { 11508fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng int PIdx = MI->findFirstPredOperandIdx(); 11518fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng if (PIdx == -1) { 11528fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng PredReg = 0; 11538fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng return ARMCC::AL; 11548fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng } 11558fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng 11568fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng PredReg = MI->getOperand(PIdx+1).getReg(); 11578fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng return (ARMCC::CondCodes)MI->getOperand(PIdx).getImm(); 11588fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng} 11598fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng 11608fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng 11616495f63945e8dbde81f03a1dc2ab421993b9a495Evan Chengint llvm::getMatchingCondBranchOpcode(int Opc) { 11625ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng if (Opc == ARM::B) 11635ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng return ARM::Bcc; 11645ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng else if (Opc == ARM::tB) 11655ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng return ARM::tBcc; 11665ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng else if (Opc == ARM::t2B) 11675ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng return ARM::t2Bcc; 11685ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng 11695ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng llvm_unreachable("Unknown unconditional branch opcode!"); 11705ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng return 0; 11715ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng} 11725ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng 11736495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 11746495f63945e8dbde81f03a1dc2ab421993b9a495Evan Chengvoid llvm::emitARMRegPlusImmediate(MachineBasicBlock &MBB, 11756495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MachineBasicBlock::iterator &MBBI, DebugLoc dl, 11766495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned DestReg, unsigned BaseReg, int NumBytes, 11776495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ARMCC::CondCodes Pred, unsigned PredReg, 11786495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng const ARMBaseInstrInfo &TII) { 11796495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng bool isSub = NumBytes < 0; 11806495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (isSub) NumBytes = -NumBytes; 11816495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 11826495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng while (NumBytes) { 11836495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned RotAmt = ARM_AM::getSOImmValRotate(NumBytes); 11846495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned ThisVal = NumBytes & ARM_AM::rotr32(0xFF, RotAmt); 11856495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng assert(ThisVal && "Didn't extract field correctly"); 11866495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 11876495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // We will handle these bits from offset, clear them. 11886495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng NumBytes &= ~ThisVal; 11896495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 11906495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng assert(ARM_AM::getSOImmVal(ThisVal) != -1 && "Bit extraction didn't work?"); 11916495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 11926495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Build the new ADD / SUB. 11936495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned Opc = isSub ? ARM::SUBri : ARM::ADDri; 11946495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg) 11956495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng .addReg(BaseReg, RegState::Kill).addImm(ThisVal) 11966495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng .addImm((unsigned)Pred).addReg(PredReg).addReg(0); 11976495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng BaseReg = DestReg; 11986495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 11996495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng} 12006495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 1201cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Chengbool llvm::rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx, 1202cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng unsigned FrameReg, int &Offset, 1203cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng const ARMBaseInstrInfo &TII) { 12046495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned Opcode = MI.getOpcode(); 12056495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng const TargetInstrDesc &Desc = MI.getDesc(); 12066495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask); 12076495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng bool isSub = false; 1208764ab52dd80310a205c9888bf166d09dab858f90Jim Grosbach 12096495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Memory operands in inline assembly always use AddrMode2. 12106495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (Opcode == ARM::INLINEASM) 12116495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng AddrMode = ARMII::AddrMode2; 1212764ab52dd80310a205c9888bf166d09dab858f90Jim Grosbach 12136495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (Opcode == ARM::ADDri) { 12146495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng Offset += MI.getOperand(FrameRegIdx+1).getImm(); 12156495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (Offset == 0) { 12166495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Turn it into a move. 12176495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MI.setDesc(TII.get(ARM::MOVr)); 12186495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false); 12196495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MI.RemoveOperand(FrameRegIdx+1); 1220cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng Offset = 0; 1221cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng return true; 12226495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } else if (Offset < 0) { 12236495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng Offset = -Offset; 12246495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng isSub = true; 12256495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MI.setDesc(TII.get(ARM::SUBri)); 12266495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 12276495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 12286495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Common case: small offset, fits into instruction. 12296495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (ARM_AM::getSOImmVal(Offset) != -1) { 12306495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Replace the FrameIndex with sp / fp 12316495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false); 12326495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset); 1233cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng Offset = 0; 1234cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng return true; 12356495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 12366495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 12376495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Otherwise, pull as much of the immedidate into this ADDri/SUBri 12386495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // as possible. 12396495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned RotAmt = ARM_AM::getSOImmValRotate(Offset); 12406495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xFF, RotAmt); 12416495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 12426495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // We will handle these bits from offset, clear them. 12436495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng Offset &= ~ThisImmVal; 12446495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 12456495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Get the properly encoded SOImmVal field. 12466495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng assert(ARM_AM::getSOImmVal(ThisImmVal) != -1 && 12476495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng "Bit extraction didn't work?"); 12486495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MI.getOperand(FrameRegIdx+1).ChangeToImmediate(ThisImmVal); 12496495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } else { 12506495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned ImmIdx = 0; 12516495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng int InstrOffs = 0; 12526495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned NumBits = 0; 12536495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned Scale = 1; 12546495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng switch (AddrMode) { 12556495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng case ARMII::AddrMode2: { 12566495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ImmIdx = FrameRegIdx+2; 12576495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng InstrOffs = ARM_AM::getAM2Offset(MI.getOperand(ImmIdx).getImm()); 12586495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (ARM_AM::getAM2Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub) 12596495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng InstrOffs *= -1; 12606495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng NumBits = 12; 12616495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng break; 12626495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 12636495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng case ARMII::AddrMode3: { 12646495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ImmIdx = FrameRegIdx+2; 12656495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng InstrOffs = ARM_AM::getAM3Offset(MI.getOperand(ImmIdx).getImm()); 12666495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (ARM_AM::getAM3Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub) 12676495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng InstrOffs *= -1; 12686495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng NumBits = 8; 12696495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng break; 12706495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 1271baf31088f1472f48ea5ae81f0b93636cc44ca444Anton Korobeynikov case ARMII::AddrMode4: 1272a44321776ecd96fa0344335d3027758be3386e45Jim Grosbach case ARMII::AddrMode6: 1273cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng // Can't fold any offset even if it's zero. 1274cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng return false; 12756495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng case ARMII::AddrMode5: { 12766495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ImmIdx = FrameRegIdx+1; 12776495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng InstrOffs = ARM_AM::getAM5Offset(MI.getOperand(ImmIdx).getImm()); 12786495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (ARM_AM::getAM5Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub) 12796495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng InstrOffs *= -1; 12806495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng NumBits = 8; 12816495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng Scale = 4; 12826495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng break; 12836495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 12846495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng default: 12856495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng llvm_unreachable("Unsupported addressing mode!"); 12866495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng break; 12876495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 12886495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 12896495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng Offset += InstrOffs * Scale; 12906495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!"); 12916495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (Offset < 0) { 12926495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng Offset = -Offset; 12936495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng isSub = true; 12946495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 12956495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 12966495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Attempt to fold address comp. if opcode has offset bits 12976495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (NumBits > 0) { 12986495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Common case: small offset, fits into instruction. 12996495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MachineOperand &ImmOp = MI.getOperand(ImmIdx); 13006495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng int ImmedOffset = Offset / Scale; 13016495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned Mask = (1 << NumBits) - 1; 13026495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if ((unsigned)Offset <= Mask * Scale) { 13036495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Replace the FrameIndex with sp 13046495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false); 13056495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (isSub) 13066495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ImmedOffset |= 1 << NumBits; 13076495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ImmOp.ChangeToImmediate(ImmedOffset); 1308cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng Offset = 0; 1309cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng return true; 13106495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 1311764ab52dd80310a205c9888bf166d09dab858f90Jim Grosbach 13126495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Otherwise, it didn't fit. Pull in what we can to simplify the immed. 13136495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ImmedOffset = ImmedOffset & Mask; 13146495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (isSub) 13156495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ImmedOffset |= 1 << NumBits; 13166495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ImmOp.ChangeToImmediate(ImmedOffset); 13176495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng Offset &= ~(Mask*Scale); 13186495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 13196495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 13206495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 1321cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng Offset = (isSub) ? -Offset : Offset; 1322cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng return Offset == 0; 13236495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng} 1324