ARMBaseInstrInfo.cpp revision c289a0252bba42248d7b11699dda27feca8860b6
131c24bf5b39cc8391d4cfdbf8cf5163975fdb81eJim Grosbach//===- ARMBaseInstrInfo.cpp - ARM Instruction Information -------*- C++ -*-===// 2334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// 3334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// The LLVM Compiler Infrastructure 4334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// 5334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// This file is distributed under the University of Illinois Open Source 6334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// License. See LICENSE.TXT for details. 7334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// 8334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin//===----------------------------------------------------------------------===// 9334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// 10334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// This file contains the Base ARM implementation of the TargetInstrInfo class. 11334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// 12334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin//===----------------------------------------------------------------------===// 13334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 14334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "ARMBaseInstrInfo.h" 15334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "ARM.h" 16334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "ARMAddressingModes.h" 17d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng#include "ARMConstantPoolValue.h" 18334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "ARMGenInstrInfo.inc" 19334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "ARMMachineFunctionInfo.h" 20f95215f551949d5e5adfbf4753aa833b9009b77aAnton Korobeynikov#include "ARMRegisterInfo.h" 21fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng#include "llvm/Constants.h" 22fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng#include "llvm/Function.h" 23fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng#include "llvm/GlobalValue.h" 24334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "llvm/ADT/STLExtras.h" 25334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "llvm/CodeGen/LiveVariables.h" 26d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng#include "llvm/CodeGen/MachineConstantPool.h" 27334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "llvm/CodeGen/MachineFrameInfo.h" 28334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "llvm/CodeGen/MachineInstrBuilder.h" 29334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "llvm/CodeGen/MachineJumpTableInfo.h" 30249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov#include "llvm/CodeGen/MachineMemOperand.h" 31249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov#include "llvm/CodeGen/PseudoSourceValue.h" 32af76e592c7f9deff0e55c13dbb4a34f07f1c7f64Chris Lattner#include "llvm/MC/MCAsmInfo.h" 33334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "llvm/Support/CommandLine.h" 34f95215f551949d5e5adfbf4753aa833b9009b77aAnton Korobeynikov#include "llvm/Support/Debug.h" 35c25e7581b9b8088910da31702d4ca21c4734c6d7Torok Edwin#include "llvm/Support/ErrorHandling.h" 36334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinusing namespace llvm; 37334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 38334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinstatic cl::opt<bool> 39334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinEnableARM3Addr("enable-arm-3-addr-conv", cl::Hidden, 40334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin cl::desc("Enable ARM 2-addr to 3-addr conv")); 41334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 42f95215f551949d5e5adfbf4753aa833b9009b77aAnton KorobeynikovARMBaseInstrInfo::ARMBaseInstrInfo(const ARMSubtarget& STI) 43f95215f551949d5e5adfbf4753aa833b9009b77aAnton Korobeynikov : TargetInstrInfoImpl(ARMInsts, array_lengthof(ARMInsts)), 44f95215f551949d5e5adfbf4753aa833b9009b77aAnton Korobeynikov Subtarget(STI) { 45334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 46334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 47334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinMachineInstr * 48334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinARMBaseInstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI, 49334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineBasicBlock::iterator &MBBI, 50334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin LiveVariables *LV) const { 5178703ddafe3d037f75d8ca188e4829d238289ac3Evan Cheng // FIXME: Thumb2 support. 5278703ddafe3d037f75d8ca188e4829d238289ac3Evan Cheng 53334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (!EnableARM3Addr) 54334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return NULL; 55334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 56334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineInstr *MI = MBBI; 57334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineFunction &MF = *MI->getParent()->getParent(); 58334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned TSFlags = MI->getDesc().TSFlags; 59334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool isPre = false; 60334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin switch ((TSFlags & ARMII::IndexModeMask) >> ARMII::IndexModeShift) { 61334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin default: return NULL; 62334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMII::IndexModePre: 63334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin isPre = true; 64334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin break; 65334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMII::IndexModePost: 66334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin break; 67334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 68334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 69334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Try splitting an indexed load/store to an un-indexed one plus an add/sub 70334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // operation. 71334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned MemOpc = getUnindexedOpcode(MI->getOpcode()); 72334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (MemOpc == 0) 73334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return NULL; 74334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 75334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineInstr *UpdateMI = NULL; 76334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineInstr *MemMI = NULL; 77334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned AddrMode = (TSFlags & ARMII::AddrModeMask); 78334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const TargetInstrDesc &TID = MI->getDesc(); 79334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned NumOps = TID.getNumOperands(); 80334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool isLoad = !TID.mayStore(); 81334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const MachineOperand &WB = isLoad ? MI->getOperand(1) : MI->getOperand(0); 82334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const MachineOperand &Base = MI->getOperand(2); 83334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const MachineOperand &Offset = MI->getOperand(NumOps-3); 84334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned WBReg = WB.getReg(); 85334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned BaseReg = Base.getReg(); 86334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned OffReg = Offset.getReg(); 87334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned OffImm = MI->getOperand(NumOps-2).getImm(); 88334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin ARMCC::CondCodes Pred = (ARMCC::CondCodes)MI->getOperand(NumOps-1).getImm(); 89334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin switch (AddrMode) { 90334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin default: 91334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin assert(false && "Unknown indexed op!"); 92334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return NULL; 93334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMII::AddrMode2: { 94334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool isSub = ARM_AM::getAM2Op(OffImm) == ARM_AM::sub; 95334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned Amt = ARM_AM::getAM2Offset(OffImm); 96334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (OffReg == 0) { 97e7cbe4118b7ddf05032ff8772a98c51e1637bb5cEvan Cheng if (ARM_AM::getSOImmVal(Amt) == -1) 98334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Can't encode it in a so_imm operand. This transformation will 99334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // add more than 1 instruction. Abandon! 100334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return NULL; 101334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin UpdateMI = BuildMI(MF, MI->getDebugLoc(), 10278703ddafe3d037f75d8ca188e4829d238289ac3Evan Cheng get(isSub ? ARM::SUBri : ARM::ADDri), WBReg) 103e7cbe4118b7ddf05032ff8772a98c51e1637bb5cEvan Cheng .addReg(BaseReg).addImm(Amt) 104334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addImm(Pred).addReg(0).addReg(0); 105334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } else if (Amt != 0) { 106334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin ARM_AM::ShiftOpc ShOpc = ARM_AM::getAM2ShiftOpc(OffImm); 107334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned SOOpc = ARM_AM::getSORegOpc(ShOpc, Amt); 108334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin UpdateMI = BuildMI(MF, MI->getDebugLoc(), 10978703ddafe3d037f75d8ca188e4829d238289ac3Evan Cheng get(isSub ? ARM::SUBrs : ARM::ADDrs), WBReg) 110334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(BaseReg).addReg(OffReg).addReg(0).addImm(SOOpc) 111334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addImm(Pred).addReg(0).addReg(0); 112334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } else 113334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin UpdateMI = BuildMI(MF, MI->getDebugLoc(), 11478703ddafe3d037f75d8ca188e4829d238289ac3Evan Cheng get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg) 115334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(BaseReg).addReg(OffReg) 116334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addImm(Pred).addReg(0).addReg(0); 117334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin break; 118334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 119334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMII::AddrMode3 : { 120334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool isSub = ARM_AM::getAM3Op(OffImm) == ARM_AM::sub; 121334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned Amt = ARM_AM::getAM3Offset(OffImm); 122334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (OffReg == 0) 123334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Immediate is 8-bits. It's guaranteed to fit in a so_imm operand. 124334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin UpdateMI = BuildMI(MF, MI->getDebugLoc(), 12578703ddafe3d037f75d8ca188e4829d238289ac3Evan Cheng get(isSub ? ARM::SUBri : ARM::ADDri), WBReg) 126334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(BaseReg).addImm(Amt) 127334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addImm(Pred).addReg(0).addReg(0); 128334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin else 129334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin UpdateMI = BuildMI(MF, MI->getDebugLoc(), 13078703ddafe3d037f75d8ca188e4829d238289ac3Evan Cheng get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg) 131334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(BaseReg).addReg(OffReg) 132334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addImm(Pred).addReg(0).addReg(0); 133334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin break; 134334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 135334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 136334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 137334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin std::vector<MachineInstr*> NewMIs; 138334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (isPre) { 139334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (isLoad) 140334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MemMI = BuildMI(MF, MI->getDebugLoc(), 141334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin get(MemOpc), MI->getOperand(0).getReg()) 142334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(WBReg).addReg(0).addImm(0).addImm(Pred); 143334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin else 144334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MemMI = BuildMI(MF, MI->getDebugLoc(), 145334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin get(MemOpc)).addReg(MI->getOperand(1).getReg()) 146334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(WBReg).addReg(0).addImm(0).addImm(Pred); 147334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin NewMIs.push_back(MemMI); 148334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin NewMIs.push_back(UpdateMI); 149334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } else { 150334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (isLoad) 151334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MemMI = BuildMI(MF, MI->getDebugLoc(), 152334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin get(MemOpc), MI->getOperand(0).getReg()) 153334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred); 154334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin else 155334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MemMI = BuildMI(MF, MI->getDebugLoc(), 156334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin get(MemOpc)).addReg(MI->getOperand(1).getReg()) 157334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred); 158334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (WB.isDead()) 159334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin UpdateMI->getOperand(0).setIsDead(); 160334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin NewMIs.push_back(UpdateMI); 161334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin NewMIs.push_back(MemMI); 162334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 163334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 164334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Transfer LiveVariables states, kill / dead info. 165334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (LV) { 166334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 167334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineOperand &MO = MI->getOperand(i); 168334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (MO.isReg() && MO.getReg() && 169334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin TargetRegisterInfo::isVirtualRegister(MO.getReg())) { 170334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned Reg = MO.getReg(); 171334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 172334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin LiveVariables::VarInfo &VI = LV->getVarInfo(Reg); 173334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (MO.isDef()) { 174334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineInstr *NewMI = (Reg == WBReg) ? UpdateMI : MemMI; 175334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (MO.isDead()) 176334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin LV->addVirtualRegisterDead(Reg, NewMI); 177334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 178334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (MO.isUse() && MO.isKill()) { 179334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin for (unsigned j = 0; j < 2; ++j) { 180334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Look at the two new MI's in reverse order. 181334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineInstr *NewMI = NewMIs[j]; 182334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (!NewMI->readsRegister(Reg)) 183334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin continue; 184334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin LV->addVirtualRegisterKilled(Reg, NewMI); 185334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (VI.removeKill(MI)) 186334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin VI.Kills.push_back(NewMI); 187334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin break; 188334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 189334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 190334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 191334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 192334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 193334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 194334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MFI->insert(MBBI, NewMIs[1]); 195334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MFI->insert(MBBI, NewMIs[0]); 196334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return NewMIs[0]; 197334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 198334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 199334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// Branch analysis. 200334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinbool 201334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinARMBaseInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB, 202334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineBasicBlock *&FBB, 203334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin SmallVectorImpl<MachineOperand> &Cond, 204334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool AllowModify) const { 205334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // If the block has no terminators, it just falls into the block after it. 206334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineBasicBlock::iterator I = MBB.end(); 207334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) 208334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 209334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 210334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Get the last instruction in the block. 211334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineInstr *LastInst = I; 212334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 213334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // If there is only one terminator instruction, process it. 214334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned LastOpc = LastInst->getOpcode(); 215334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) { 2165ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng if (isUncondBranchOpcode(LastOpc)) { 217334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin TBB = LastInst->getOperand(0).getMBB(); 218334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 219334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 2205ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng if (isCondBranchOpcode(LastOpc)) { 221334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Block ends with fall-through condbranch. 222334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin TBB = LastInst->getOperand(0).getMBB(); 223334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin Cond.push_back(LastInst->getOperand(1)); 224334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin Cond.push_back(LastInst->getOperand(2)); 225334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 226334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 227334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; // Can't handle indirect branch. 228334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 229334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 230334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Get the instruction before it if it is a terminator. 231334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineInstr *SecondLastInst = I; 232334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 233334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // If there are three terminators, we don't know what sort of block this is. 234334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(--I)) 235334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; 236334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 2375ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng // If the block ends with a B and a Bcc, handle it. 238334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned SecondLastOpc = SecondLastInst->getOpcode(); 2395ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng if (isCondBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) { 240334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin TBB = SecondLastInst->getOperand(0).getMBB(); 241334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin Cond.push_back(SecondLastInst->getOperand(1)); 242334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin Cond.push_back(SecondLastInst->getOperand(2)); 243334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin FBB = LastInst->getOperand(0).getMBB(); 244334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 245334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 246334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 247334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // If the block ends with two unconditional branches, handle it. The second 248334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // one is not executed, so remove it. 2495ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng if (isUncondBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) { 250334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin TBB = SecondLastInst->getOperand(0).getMBB(); 251334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin I = LastInst; 252334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (AllowModify) 253334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin I->eraseFromParent(); 254334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 255334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 256334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 257334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // ...likewise if it ends with a branch table followed by an unconditional 258334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // branch. The branch folder can create these, and we must get rid of them for 259334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // correctness of Thumb constant islands. 2608d4de5abfa1bcd974554ea14904ebf7af289e84dBob Wilson if ((isJumpTableBranchOpcode(SecondLastOpc) || 2618d4de5abfa1bcd974554ea14904ebf7af289e84dBob Wilson isIndirectBranchOpcode(SecondLastOpc)) && 2625ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng isUncondBranchOpcode(LastOpc)) { 263334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin I = LastInst; 264334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (AllowModify) 265334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin I->eraseFromParent(); 266334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; 267334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 268334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 269334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Otherwise, can't handle this. 270334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; 271334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 272334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 273334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 274334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinunsigned ARMBaseInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const { 275334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineBasicBlock::iterator I = MBB.end(); 276334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (I == MBB.begin()) return 0; 277334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin --I; 2785ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng if (!isUncondBranchOpcode(I->getOpcode()) && 2795ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng !isCondBranchOpcode(I->getOpcode())) 280334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 0; 281334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 282334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Remove the branch. 283334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin I->eraseFromParent(); 284334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 285334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin I = MBB.end(); 286334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 287334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (I == MBB.begin()) return 1; 288334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin --I; 2895ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng if (!isCondBranchOpcode(I->getOpcode())) 290334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 1; 291334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 292334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Remove the branch. 293334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin I->eraseFromParent(); 294334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 2; 295334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 296334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 297334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinunsigned 298334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinARMBaseInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 299334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineBasicBlock *FBB, 300334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const SmallVectorImpl<MachineOperand> &Cond) const { 301334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // FIXME this should probably have a DebugLoc argument 302334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin DebugLoc dl = DebugLoc::getUnknownLoc(); 3036495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 3046495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ARMFunctionInfo *AFI = MBB.getParent()->getInfo<ARMFunctionInfo>(); 3056495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng int BOpc = !AFI->isThumbFunction() 3066495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ? ARM::B : (AFI->isThumb2Function() ? ARM::t2B : ARM::tB); 3076495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng int BccOpc = !AFI->isThumbFunction() 3086495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ? ARM::Bcc : (AFI->isThumb2Function() ? ARM::t2Bcc : ARM::tBcc); 309334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 310334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Shouldn't be a fall through. 311334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin assert(TBB && "InsertBranch must not be told to insert a fallthrough"); 312334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin assert((Cond.size() == 2 || Cond.size() == 0) && 313334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin "ARM branch conditions have two components!"); 314334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 315334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (FBB == 0) { 316334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (Cond.empty()) // Unconditional branch? 317334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin BuildMI(&MBB, dl, get(BOpc)).addMBB(TBB); 318334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin else 319334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin BuildMI(&MBB, dl, get(BccOpc)).addMBB(TBB) 320334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()); 321334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 1; 322334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 323334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 324334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Two-way conditional branch. 325334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin BuildMI(&MBB, dl, get(BccOpc)).addMBB(TBB) 326334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()); 327334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin BuildMI(&MBB, dl, get(BOpc)).addMBB(FBB); 328334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 2; 329334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 330334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 331334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinbool ARMBaseInstrInfo:: 332334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const { 333334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin ARMCC::CondCodes CC = (ARMCC::CondCodes)(int)Cond[0].getImm(); 334334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin Cond[0].setImm(ARMCC::getOppositeCondition(CC)); 335334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 336334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 337334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 338334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinbool ARMBaseInstrInfo:: 339334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinPredicateInstruction(MachineInstr *MI, 340334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const SmallVectorImpl<MachineOperand> &Pred) const { 341334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned Opc = MI->getOpcode(); 3425ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng if (isUncondBranchOpcode(Opc)) { 3435ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng MI->setDesc(get(getMatchingCondBranchOpcode(Opc))); 344334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI->addOperand(MachineOperand::CreateImm(Pred[0].getImm())); 345334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI->addOperand(MachineOperand::CreateReg(Pred[1].getReg(), false)); 346334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; 347334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 348334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 349334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin int PIdx = MI->findFirstPredOperandIdx(); 350334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (PIdx != -1) { 351334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineOperand &PMO = MI->getOperand(PIdx); 352334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin PMO.setImm(Pred[0].getImm()); 353334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI->getOperand(PIdx+1).setReg(Pred[1].getReg()); 354334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; 355334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 356334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 357334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 358334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 359334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinbool ARMBaseInstrInfo:: 360334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinSubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1, 361334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const SmallVectorImpl<MachineOperand> &Pred2) const { 362334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (Pred1.size() > 2 || Pred2.size() > 2) 363334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 364334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 365334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin ARMCC::CondCodes CC1 = (ARMCC::CondCodes)Pred1[0].getImm(); 366334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin ARMCC::CondCodes CC2 = (ARMCC::CondCodes)Pred2[0].getImm(); 367334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (CC1 == CC2) 368334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; 369334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 370334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin switch (CC1) { 371334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin default: 372334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 373334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMCC::AL: 374334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; 375334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMCC::HS: 376334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return CC2 == ARMCC::HI; 377334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMCC::LS: 378334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return CC2 == ARMCC::LO || CC2 == ARMCC::EQ; 379334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMCC::GE: 380334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return CC2 == ARMCC::GT; 381334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMCC::LE: 382334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return CC2 == ARMCC::LT; 383334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 384334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 385334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 386334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinbool ARMBaseInstrInfo::DefinesPredicate(MachineInstr *MI, 387334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin std::vector<MachineOperand> &Pred) const { 3888fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng // FIXME: This confuses implicit_def with optional CPSR def. 389334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const TargetInstrDesc &TID = MI->getDesc(); 390334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (!TID.getImplicitDefs() && !TID.hasOptionalDef()) 391334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 392334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 393334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool Found = false; 394334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 395334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const MachineOperand &MO = MI->getOperand(i); 396334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (MO.isReg() && MO.getReg() == ARM::CPSR) { 397334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin Pred.push_back(MO); 398334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin Found = true; 399334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 400334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 401334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 402334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return Found; 403334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 404334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 405ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng/// isPredicable - Return true if the specified instruction can be predicated. 406ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng/// By default, this returns true for every instruction with a 407ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng/// PredicateOperand. 408ac0869dc8a7986855c5557cc67d4709600158ef5Evan Chengbool ARMBaseInstrInfo::isPredicable(MachineInstr *MI) const { 409ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng const TargetInstrDesc &TID = MI->getDesc(); 410ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng if (!TID.isPredicable()) 411ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng return false; 412ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng 413ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng if ((TID.TSFlags & ARMII::DomainMask) == ARMII::DomainNEON) { 414ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng ARMFunctionInfo *AFI = 415ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng MI->getParent()->getParent()->getInfo<ARMFunctionInfo>(); 416d7f0810c934a7d13acb28c42d737ce58ec990ea8Evan Cheng return AFI->isThumb2Function(); 417ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng } 418ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng return true; 419ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng} 420334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 42156856b1f46ec1f073ceef4e826c544b8b1691608Chris Lattner/// FIXME: Works around a gcc miscompilation with -fstrict-aliasing. 42256856b1f46ec1f073ceef4e826c544b8b1691608Chris LattnerDISABLE_INLINE 423334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinstatic unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT, 42456856b1f46ec1f073ceef4e826c544b8b1691608Chris Lattner unsigned JTI); 425334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinstatic unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT, 426334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned JTI) { 42756856b1f46ec1f073ceef4e826c544b8b1691608Chris Lattner assert(JTI < JT.size()); 428334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return JT[JTI].MBBs.size(); 429334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 430334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 431334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin/// GetInstSize - Return the size of the specified MachineInstr. 432334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin/// 433334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinunsigned ARMBaseInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const { 434334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const MachineBasicBlock &MBB = *MI->getParent(); 435334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const MachineFunction *MF = MBB.getParent(); 43633adcfb4d217f5f23d9bde8ba02b8e48f9605fc5Chris Lattner const MCAsmInfo *MAI = MF->getTarget().getMCAsmInfo(); 437334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 438334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Basic size info comes from the TSFlags field. 439334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const TargetInstrDesc &TID = MI->getDesc(); 440334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned TSFlags = TID.TSFlags; 441334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 442a0ee862f2e3a0d202244e02459ddcf0dca0e8607Evan Cheng unsigned Opc = MI->getOpcode(); 443334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin switch ((TSFlags & ARMII::SizeMask) >> ARMII::SizeShift) { 444334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin default: { 445334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // If this machine instr is an inline asm, measure it. 446334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (MI->getOpcode() == ARM::INLINEASM) 44733adcfb4d217f5f23d9bde8ba02b8e48f9605fc5Chris Lattner return getInlineAsmLength(MI->getOperand(0).getSymbolName(), *MAI); 448334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (MI->isLabel()) 449334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 0; 450a0ee862f2e3a0d202244e02459ddcf0dca0e8607Evan Cheng switch (Opc) { 451334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin default: 452c23197a26f34f559ea9797de51e187087c039c42Torok Edwin llvm_unreachable("Unknown or unset size field for instr!"); 453518bb53485df640d7b7e3f6b0544099020c42aa7Chris Lattner case TargetOpcode::IMPLICIT_DEF: 454518bb53485df640d7b7e3f6b0544099020c42aa7Chris Lattner case TargetOpcode::KILL: 455518bb53485df640d7b7e3f6b0544099020c42aa7Chris Lattner case TargetOpcode::DBG_LABEL: 456518bb53485df640d7b7e3f6b0544099020c42aa7Chris Lattner case TargetOpcode::EH_LABEL: 457334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 0; 458334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 459334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin break; 460334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 461789476240d6b6f8ad9366cadf790a82bd41bb0b3Evan Cheng case ARMII::Size8Bytes: return 8; // ARM instruction x 2. 462789476240d6b6f8ad9366cadf790a82bd41bb0b3Evan Cheng case ARMII::Size4Bytes: return 4; // ARM / Thumb2 instruction. 463789476240d6b6f8ad9366cadf790a82bd41bb0b3Evan Cheng case ARMII::Size2Bytes: return 2; // Thumb1 instruction. 464334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMII::SizeSpecial: { 465a0ee862f2e3a0d202244e02459ddcf0dca0e8607Evan Cheng switch (Opc) { 466334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARM::CONSTPOOL_ENTRY: 467334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // If this machine instr is a constant pool entry, its size is recorded as 468334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // operand #2. 469334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return MI->getOperand(2).getImm(); 470789476240d6b6f8ad9366cadf790a82bd41bb0b3Evan Cheng case ARM::Int_eh_sjlj_setjmp: 471cdc17ebc2b2e9e18ac516b9d246a5c5a3af227d3Jim Grosbach return 24; 472d122874996a6faa8832569b632fd73a32ace7ae7Jim Grosbach case ARM::tInt_eh_sjlj_setjmp: 473a87ded2695e5bce30dbd0d2d2ac10c571bf1d161Jim Grosbach return 14; 4745aa1684e5da9a85286bf7d29da419d261a70c2f2Jim Grosbach case ARM::t2Int_eh_sjlj_setjmp: 475a87ded2695e5bce30dbd0d2d2ac10c571bf1d161Jim Grosbach return 14; 476334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARM::BR_JTr: 477334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARM::BR_JTm: 478334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARM::BR_JTadd: 479a0ee862f2e3a0d202244e02459ddcf0dca0e8607Evan Cheng case ARM::tBR_JTr: 480d26b14c34cbcee1448b86b524578fc51cc979023Evan Cheng case ARM::t2BR_JT: 481d26b14c34cbcee1448b86b524578fc51cc979023Evan Cheng case ARM::t2TBB: 482d26b14c34cbcee1448b86b524578fc51cc979023Evan Cheng case ARM::t2TBH: { 483334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // These are jumptable branches, i.e. a branch followed by an inlined 484d26b14c34cbcee1448b86b524578fc51cc979023Evan Cheng // jumptable. The size is 4 + 4 * number of entries. For TBB, each 485d26b14c34cbcee1448b86b524578fc51cc979023Evan Cheng // entry is one byte; TBH two byte each. 486a0ee862f2e3a0d202244e02459ddcf0dca0e8607Evan Cheng unsigned EntrySize = (Opc == ARM::t2TBB) 487a0ee862f2e3a0d202244e02459ddcf0dca0e8607Evan Cheng ? 1 : ((Opc == ARM::t2TBH) ? 2 : 4); 488334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned NumOps = TID.getNumOperands(); 489334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineOperand JTOP = 490334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI->getOperand(NumOps - (TID.isPredicable() ? 3 : 2)); 491334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned JTI = JTOP.getIndex(); 492334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo(); 493b1e803985d3378538ae9cff7eed4102c002d1e22Chris Lattner assert(MJTI != 0); 494334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables(); 495334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin assert(JTI < JT.size()); 496334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Thumb instructions are 2 byte aligned, but JT entries are 4 byte 497334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // 4 aligned. The assembler / linker may add 2 byte padding just before 498334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // the JT entries. The size does not include this padding; the 499334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // constant islands pass does separate bookkeeping for it. 500334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // FIXME: If we know the size of the function is less than (1 << 16) *2 501334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // bytes, we can use 16-bit entries instead. Then there won't be an 502334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // alignment issue. 50325f7cfc3cccba6f569f29f79ea533bae960b93c0Evan Cheng unsigned InstSize = (Opc == ARM::tBR_JTr || Opc == ARM::t2BR_JT) ? 2 : 4; 50425f7cfc3cccba6f569f29f79ea533bae960b93c0Evan Cheng unsigned NumEntries = getNumJTEntries(JT, JTI); 50525f7cfc3cccba6f569f29f79ea533bae960b93c0Evan Cheng if (Opc == ARM::t2TBB && (NumEntries & 1)) 50625f7cfc3cccba6f569f29f79ea533bae960b93c0Evan Cheng // Make sure the instruction that follows TBB is 2-byte aligned. 50725f7cfc3cccba6f569f29f79ea533bae960b93c0Evan Cheng // FIXME: Constant island pass should insert an "ALIGN" instruction 50825f7cfc3cccba6f569f29f79ea533bae960b93c0Evan Cheng // instead. 50925f7cfc3cccba6f569f29f79ea533bae960b93c0Evan Cheng ++NumEntries; 51025f7cfc3cccba6f569f29f79ea533bae960b93c0Evan Cheng return NumEntries * EntrySize + InstSize; 511334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 512334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin default: 513334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Otherwise, pseudo-instruction sizes are zero. 514334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 0; 515334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 516334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 517334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 518334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 0; // Not reached 519334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 520334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 521334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin/// Return true if the instruction is a register to register move and 522334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin/// leave the source and dest operands in the passed parameters. 523334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin/// 524334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinbool 525334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinARMBaseInstrInfo::isMoveInstr(const MachineInstr &MI, 526334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned &SrcReg, unsigned &DstReg, 527334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned& SrcSubIdx, unsigned& DstSubIdx) const { 528334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin SrcSubIdx = DstSubIdx = 0; // No sub-registers. 529334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 53068e3c6ae49ff67cba98403e43b5bd0c2499caa41Evan Cheng switch (MI.getOpcode()) { 531dced03fc846fa7cd9558ecb8e33ca98ec29bdcf0Evan Cheng default: break; 532e5165490b7ba24bb2f3043399e0d60e7f3bcf8a5Jim Grosbach case ARM::VMOVS: 53368e3c6ae49ff67cba98403e43b5bd0c2499caa41Evan Cheng case ARM::VMOVD: 534e5165490b7ba24bb2f3043399e0d60e7f3bcf8a5Jim Grosbach case ARM::VMOVDneon: 535f95215f551949d5e5adfbf4753aa833b9009b77aAnton Korobeynikov case ARM::VMOVQ: { 536334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin SrcReg = MI.getOperand(1).getReg(); 537334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin DstReg = MI.getOperand(0).getReg(); 538334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; 539334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 54068e3c6ae49ff67cba98403e43b5bd0c2499caa41Evan Cheng case ARM::MOVr: 54168e3c6ae49ff67cba98403e43b5bd0c2499caa41Evan Cheng case ARM::tMOVr: 54268e3c6ae49ff67cba98403e43b5bd0c2499caa41Evan Cheng case ARM::tMOVgpr2tgpr: 54368e3c6ae49ff67cba98403e43b5bd0c2499caa41Evan Cheng case ARM::tMOVtgpr2gpr: 54468e3c6ae49ff67cba98403e43b5bd0c2499caa41Evan Cheng case ARM::tMOVgpr2gpr: 54568e3c6ae49ff67cba98403e43b5bd0c2499caa41Evan Cheng case ARM::t2MOVr: { 546334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin assert(MI.getDesc().getNumOperands() >= 2 && 547334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI.getOperand(0).isReg() && 548334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI.getOperand(1).isReg() && 549334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin "Invalid ARM MOV instruction"); 550334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin SrcReg = MI.getOperand(1).getReg(); 551334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin DstReg = MI.getOperand(0).getReg(); 552334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; 553334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 55468e3c6ae49ff67cba98403e43b5bd0c2499caa41Evan Cheng } 555334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 556334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 557334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 558334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 559764ab52dd80310a205c9888bf166d09dab858f90Jim Grosbachunsigned 560334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinARMBaseInstrInfo::isLoadFromStackSlot(const MachineInstr *MI, 561334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin int &FrameIndex) const { 562dced03fc846fa7cd9558ecb8e33ca98ec29bdcf0Evan Cheng switch (MI->getOpcode()) { 563dced03fc846fa7cd9558ecb8e33ca98ec29bdcf0Evan Cheng default: break; 564dced03fc846fa7cd9558ecb8e33ca98ec29bdcf0Evan Cheng case ARM::LDR: 565dced03fc846fa7cd9558ecb8e33ca98ec29bdcf0Evan Cheng case ARM::t2LDRs: // FIXME: don't use t2LDRs to access frame. 566334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (MI->getOperand(1).isFI() && 567334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI->getOperand(2).isReg() && 568334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI->getOperand(3).isImm() && 569334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI->getOperand(2).getReg() == 0 && 570334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI->getOperand(3).getImm() == 0) { 571334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin FrameIndex = MI->getOperand(1).getIndex(); 572334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return MI->getOperand(0).getReg(); 573334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 574dced03fc846fa7cd9558ecb8e33ca98ec29bdcf0Evan Cheng break; 575dced03fc846fa7cd9558ecb8e33ca98ec29bdcf0Evan Cheng case ARM::t2LDRi12: 576dced03fc846fa7cd9558ecb8e33ca98ec29bdcf0Evan Cheng case ARM::tRestore: 5775ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin if (MI->getOperand(1).isFI() && 5785ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin MI->getOperand(2).isImm() && 5795ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin MI->getOperand(2).getImm() == 0) { 5805ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin FrameIndex = MI->getOperand(1).getIndex(); 5815ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin return MI->getOperand(0).getReg(); 5825ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin } 583dced03fc846fa7cd9558ecb8e33ca98ec29bdcf0Evan Cheng break; 584e5165490b7ba24bb2f3043399e0d60e7f3bcf8a5Jim Grosbach case ARM::VLDRD: 585e5165490b7ba24bb2f3043399e0d60e7f3bcf8a5Jim Grosbach case ARM::VLDRS: 586334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (MI->getOperand(1).isFI() && 587334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI->getOperand(2).isImm() && 588334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI->getOperand(2).getImm() == 0) { 589334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin FrameIndex = MI->getOperand(1).getIndex(); 590334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return MI->getOperand(0).getReg(); 591334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 592dced03fc846fa7cd9558ecb8e33ca98ec29bdcf0Evan Cheng break; 593334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 594334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 595334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 0; 596334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 597334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 598334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinunsigned 599334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinARMBaseInstrInfo::isStoreToStackSlot(const MachineInstr *MI, 600334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin int &FrameIndex) const { 601dced03fc846fa7cd9558ecb8e33ca98ec29bdcf0Evan Cheng switch (MI->getOpcode()) { 602dced03fc846fa7cd9558ecb8e33ca98ec29bdcf0Evan Cheng default: break; 603dced03fc846fa7cd9558ecb8e33ca98ec29bdcf0Evan Cheng case ARM::STR: 604dced03fc846fa7cd9558ecb8e33ca98ec29bdcf0Evan Cheng case ARM::t2STRs: // FIXME: don't use t2STRs to access frame. 605334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (MI->getOperand(1).isFI() && 606334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI->getOperand(2).isReg() && 607334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI->getOperand(3).isImm() && 608334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI->getOperand(2).getReg() == 0 && 609334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI->getOperand(3).getImm() == 0) { 610334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin FrameIndex = MI->getOperand(1).getIndex(); 611334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return MI->getOperand(0).getReg(); 612334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 613dced03fc846fa7cd9558ecb8e33ca98ec29bdcf0Evan Cheng break; 614dced03fc846fa7cd9558ecb8e33ca98ec29bdcf0Evan Cheng case ARM::t2STRi12: 615dced03fc846fa7cd9558ecb8e33ca98ec29bdcf0Evan Cheng case ARM::tSpill: 6165ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin if (MI->getOperand(1).isFI() && 6175ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin MI->getOperand(2).isImm() && 6185ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin MI->getOperand(2).getImm() == 0) { 6195ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin FrameIndex = MI->getOperand(1).getIndex(); 6205ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin return MI->getOperand(0).getReg(); 6215ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin } 622dced03fc846fa7cd9558ecb8e33ca98ec29bdcf0Evan Cheng break; 623e5165490b7ba24bb2f3043399e0d60e7f3bcf8a5Jim Grosbach case ARM::VSTRD: 624e5165490b7ba24bb2f3043399e0d60e7f3bcf8a5Jim Grosbach case ARM::VSTRS: 625334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (MI->getOperand(1).isFI() && 626334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI->getOperand(2).isImm() && 627334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI->getOperand(2).getImm() == 0) { 628334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin FrameIndex = MI->getOperand(1).getIndex(); 629334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return MI->getOperand(0).getReg(); 630334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 631dced03fc846fa7cd9558ecb8e33ca98ec29bdcf0Evan Cheng break; 632334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 633334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 634334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 0; 635334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 636334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 637334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinbool 638334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinARMBaseInstrInfo::copyRegToReg(MachineBasicBlock &MBB, 639334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineBasicBlock::iterator I, 640334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned DestReg, unsigned SrcReg, 641334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const TargetRegisterClass *DestRC, 642334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const TargetRegisterClass *SrcRC) const { 643334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin DebugLoc DL = DebugLoc::getUnknownLoc(); 644334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (I != MBB.end()) DL = I->getDebugLoc(); 645334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 6461665b0a2246c83a2c123be105a1a167cf2b423feBob Wilson // tGPR is used sometimes in ARM instructions that need to avoid using 6471665b0a2246c83a2c123be105a1a167cf2b423feBob Wilson // certain registers. Just treat it as GPR here. 6481665b0a2246c83a2c123be105a1a167cf2b423feBob Wilson if (DestRC == ARM::tGPRRegisterClass) 6491665b0a2246c83a2c123be105a1a167cf2b423feBob Wilson DestRC = ARM::GPRRegisterClass; 6501665b0a2246c83a2c123be105a1a167cf2b423feBob Wilson if (SrcRC == ARM::tGPRRegisterClass) 6511665b0a2246c83a2c123be105a1a167cf2b423feBob Wilson SrcRC = ARM::GPRRegisterClass; 6521665b0a2246c83a2c123be105a1a167cf2b423feBob Wilson 6536755d97a62fd6796f4146833efb1051fc96a61c0Anton Korobeynikov // Allow DPR / DPR_VFP2 / DPR_8 cross-class copies. 6546755d97a62fd6796f4146833efb1051fc96a61c0Anton Korobeynikov if (DestRC == ARM::DPR_8RegisterClass) 6556755d97a62fd6796f4146833efb1051fc96a61c0Anton Korobeynikov DestRC = ARM::DPR_VFP2RegisterClass; 6566755d97a62fd6796f4146833efb1051fc96a61c0Anton Korobeynikov if (SrcRC == ARM::DPR_8RegisterClass) 6576755d97a62fd6796f4146833efb1051fc96a61c0Anton Korobeynikov SrcRC = ARM::DPR_VFP2RegisterClass; 6586755d97a62fd6796f4146833efb1051fc96a61c0Anton Korobeynikov 6596755d97a62fd6796f4146833efb1051fc96a61c0Anton Korobeynikov // Allow QPR / QPR_VFP2 / QPR_8 cross-class copies. 6606755d97a62fd6796f4146833efb1051fc96a61c0Anton Korobeynikov if (DestRC == ARM::QPR_VFP2RegisterClass || 6616755d97a62fd6796f4146833efb1051fc96a61c0Anton Korobeynikov DestRC == ARM::QPR_8RegisterClass) 6626755d97a62fd6796f4146833efb1051fc96a61c0Anton Korobeynikov DestRC = ARM::QPRRegisterClass; 6636755d97a62fd6796f4146833efb1051fc96a61c0Anton Korobeynikov if (SrcRC == ARM::QPR_VFP2RegisterClass || 6646755d97a62fd6796f4146833efb1051fc96a61c0Anton Korobeynikov SrcRC == ARM::QPR_8RegisterClass) 6656755d97a62fd6796f4146833efb1051fc96a61c0Anton Korobeynikov SrcRC = ARM::QPRRegisterClass; 6666755d97a62fd6796f4146833efb1051fc96a61c0Anton Korobeynikov 6676755d97a62fd6796f4146833efb1051fc96a61c0Anton Korobeynikov // Disallow copies of unequal sizes. 6686755d97a62fd6796f4146833efb1051fc96a61c0Anton Korobeynikov if (DestRC != SrcRC && DestRC->getSize() != SrcRC->getSize()) 6696755d97a62fd6796f4146833efb1051fc96a61c0Anton Korobeynikov return false; 670b4db6a46e0de3283fa70ea0a7d3623f2e4e2d2a3Evan Cheng 6716755d97a62fd6796f4146833efb1051fc96a61c0Anton Korobeynikov if (DestRC == ARM::GPRRegisterClass) { 6726755d97a62fd6796f4146833efb1051fc96a61c0Anton Korobeynikov if (SrcRC == ARM::SPRRegisterClass) 6736755d97a62fd6796f4146833efb1051fc96a61c0Anton Korobeynikov AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VMOVRS), DestReg) 6746755d97a62fd6796f4146833efb1051fc96a61c0Anton Korobeynikov .addReg(SrcReg)); 6756755d97a62fd6796f4146833efb1051fc96a61c0Anton Korobeynikov else 6766755d97a62fd6796f4146833efb1051fc96a61c0Anton Korobeynikov AddDefaultCC(AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::MOVr), 6776755d97a62fd6796f4146833efb1051fc96a61c0Anton Korobeynikov DestReg).addReg(SrcReg))); 6786755d97a62fd6796f4146833efb1051fc96a61c0Anton Korobeynikov } else { 6796755d97a62fd6796f4146833efb1051fc96a61c0Anton Korobeynikov unsigned Opc; 6806755d97a62fd6796f4146833efb1051fc96a61c0Anton Korobeynikov 6816755d97a62fd6796f4146833efb1051fc96a61c0Anton Korobeynikov if (DestRC == ARM::SPRRegisterClass) 6826755d97a62fd6796f4146833efb1051fc96a61c0Anton Korobeynikov Opc = (SrcRC == ARM::GPRRegisterClass ? ARM::VMOVSR : ARM::VMOVS); 6836755d97a62fd6796f4146833efb1051fc96a61c0Anton Korobeynikov else if (DestRC == ARM::DPRRegisterClass) 6846755d97a62fd6796f4146833efb1051fc96a61c0Anton Korobeynikov Opc = ARM::VMOVD; 6856755d97a62fd6796f4146833efb1051fc96a61c0Anton Korobeynikov else if (DestRC == ARM::DPR_VFP2RegisterClass || 6866755d97a62fd6796f4146833efb1051fc96a61c0Anton Korobeynikov SrcRC == ARM::DPR_VFP2RegisterClass) 6876755d97a62fd6796f4146833efb1051fc96a61c0Anton Korobeynikov // Always use neon reg-reg move if source or dest is NEON-only regclass. 6886755d97a62fd6796f4146833efb1051fc96a61c0Anton Korobeynikov Opc = ARM::VMOVDneon; 6896755d97a62fd6796f4146833efb1051fc96a61c0Anton Korobeynikov else if (DestRC == ARM::QPRRegisterClass) 6906755d97a62fd6796f4146833efb1051fc96a61c0Anton Korobeynikov Opc = ARM::VMOVQ; 6916755d97a62fd6796f4146833efb1051fc96a61c0Anton Korobeynikov else 6927bfdca0206f51132b26094c6f83a5ac97ee0f943David Goodwin return false; 693334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 6946755d97a62fd6796f4146833efb1051fc96a61c0Anton Korobeynikov AddDefaultPred(BuildMI(MBB, I, DL, get(Opc), DestReg) 695b4db6a46e0de3283fa70ea0a7d3623f2e4e2d2a3Evan Cheng .addReg(SrcReg)); 6967bfdca0206f51132b26094c6f83a5ac97ee0f943David Goodwin } 697334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 698334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; 699334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 700334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 701334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinvoid ARMBaseInstrInfo:: 702334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinstoreRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 703334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned SrcReg, bool isKill, int FI, 704334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const TargetRegisterClass *RC) const { 705334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin DebugLoc DL = DebugLoc::getUnknownLoc(); 706334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (I != MBB.end()) DL = I->getDebugLoc(); 707249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MachineFunction &MF = *MBB.getParent(); 708249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MachineFrameInfo &MFI = *MF.getFrameInfo(); 70931bc849123011b8eae6bb3c79876d9a3c26a6a1dJim Grosbach unsigned Align = MFI.getObjectAlignment(FI); 710249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov 711249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MachineMemOperand *MMO = 712ff89dcb06fbd103373436e2d0ae85f252fae2254Evan Cheng MF.getMachineMemOperand(PseudoSourceValue::getFixedStack(FI), 713249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MachineMemOperand::MOStore, 0, 714249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MFI.getObjectSize(FI), 71531bc849123011b8eae6bb3c79876d9a3c26a6a1dJim Grosbach Align); 716334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 7170eb0c7401c34c0b4604f732ce54db995eead14e6Bob Wilson // tGPR is used sometimes in ARM instructions that need to avoid using 7180eb0c7401c34c0b4604f732ce54db995eead14e6Bob Wilson // certain registers. Just treat it as GPR here. 7190eb0c7401c34c0b4604f732ce54db995eead14e6Bob Wilson if (RC == ARM::tGPRRegisterClass) 7200eb0c7401c34c0b4604f732ce54db995eead14e6Bob Wilson RC = ARM::GPRRegisterClass; 7210eb0c7401c34c0b4604f732ce54db995eead14e6Bob Wilson 722334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (RC == ARM::GPRRegisterClass) { 7235732ca084aaa0cd26149e50dd4b487efff37fe41Evan Cheng AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::STR)) 724334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(SrcReg, getKillRegState(isKill)) 725249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov .addFrameIndex(FI).addReg(0).addImm(0).addMemOperand(MMO)); 7266ca0b9e7220911a6d1fccf34e532e69c7e37cd2fAnton Korobeynikov } else if (RC == ARM::DPRRegisterClass || 7276ca0b9e7220911a6d1fccf34e532e69c7e37cd2fAnton Korobeynikov RC == ARM::DPR_VFP2RegisterClass || 7286ca0b9e7220911a6d1fccf34e532e69c7e37cd2fAnton Korobeynikov RC == ARM::DPR_8RegisterClass) { 729e5165490b7ba24bb2f3043399e0d60e7f3bcf8a5Jim Grosbach AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTRD)) 730334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(SrcReg, getKillRegState(isKill)) 731249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov .addFrameIndex(FI).addImm(0).addMemOperand(MMO)); 732baf31088f1472f48ea5ae81f0b93636cc44ca444Anton Korobeynikov } else if (RC == ARM::SPRRegisterClass) { 733e5165490b7ba24bb2f3043399e0d60e7f3bcf8a5Jim Grosbach AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTRS)) 734334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(SrcReg, getKillRegState(isKill)) 735249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov .addFrameIndex(FI).addImm(0).addMemOperand(MMO)); 736baf31088f1472f48ea5ae81f0b93636cc44ca444Anton Korobeynikov } else { 737e56f9085b1e96f0cc302c678f1c00877676e455eAnton Korobeynikov assert((RC == ARM::QPRRegisterClass || 738e56f9085b1e96f0cc302c678f1c00877676e455eAnton Korobeynikov RC == ARM::QPR_VFP2RegisterClass) && "Unknown regclass!"); 739baf31088f1472f48ea5ae81f0b93636cc44ca444Anton Korobeynikov // FIXME: Neon instructions should support predicates 740226036ee731a2041f37f28f958d2b6a50373f4f4Bob Wilson if (Align >= 16 && (getRegisterInfo().canRealignStack(MF))) { 74111d98997590a1d636b04c4f0756eded6b2d037f3Bob Wilson AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1q)) 742226036ee731a2041f37f28f958d2b6a50373f4f4Bob Wilson .addFrameIndex(FI).addImm(128) 743ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng .addMemOperand(MMO) 744ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng .addReg(SrcReg, getKillRegState(isKill))); 74531bc849123011b8eae6bb3c79876d9a3c26a6a1dJim Grosbach } else { 746c289a0252bba42248d7b11699dda27feca8860b6Bob Wilson AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMQ)). 747ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng addReg(SrcReg, getKillRegState(isKill)) 748ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng .addFrameIndex(FI).addImm(0).addMemOperand(MMO)); 74931bc849123011b8eae6bb3c79876d9a3c26a6a1dJim Grosbach } 750334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 751334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 752334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 753334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinvoid ARMBaseInstrInfo:: 754334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinloadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 755334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned DestReg, int FI, 756334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const TargetRegisterClass *RC) const { 757334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin DebugLoc DL = DebugLoc::getUnknownLoc(); 758334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (I != MBB.end()) DL = I->getDebugLoc(); 759249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MachineFunction &MF = *MBB.getParent(); 760249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MachineFrameInfo &MFI = *MF.getFrameInfo(); 76131bc849123011b8eae6bb3c79876d9a3c26a6a1dJim Grosbach unsigned Align = MFI.getObjectAlignment(FI); 762249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov 763249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MachineMemOperand *MMO = 764ff89dcb06fbd103373436e2d0ae85f252fae2254Evan Cheng MF.getMachineMemOperand(PseudoSourceValue::getFixedStack(FI), 765249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MachineMemOperand::MOLoad, 0, 766249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MFI.getObjectSize(FI), 76731bc849123011b8eae6bb3c79876d9a3c26a6a1dJim Grosbach Align); 768334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 7690eb0c7401c34c0b4604f732ce54db995eead14e6Bob Wilson // tGPR is used sometimes in ARM instructions that need to avoid using 7700eb0c7401c34c0b4604f732ce54db995eead14e6Bob Wilson // certain registers. Just treat it as GPR here. 7710eb0c7401c34c0b4604f732ce54db995eead14e6Bob Wilson if (RC == ARM::tGPRRegisterClass) 7720eb0c7401c34c0b4604f732ce54db995eead14e6Bob Wilson RC = ARM::GPRRegisterClass; 7730eb0c7401c34c0b4604f732ce54db995eead14e6Bob Wilson 774334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (RC == ARM::GPRRegisterClass) { 7755732ca084aaa0cd26149e50dd4b487efff37fe41Evan Cheng AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::LDR), DestReg) 776249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov .addFrameIndex(FI).addReg(0).addImm(0).addMemOperand(MMO)); 7776ca0b9e7220911a6d1fccf34e532e69c7e37cd2fAnton Korobeynikov } else if (RC == ARM::DPRRegisterClass || 7786ca0b9e7220911a6d1fccf34e532e69c7e37cd2fAnton Korobeynikov RC == ARM::DPR_VFP2RegisterClass || 7796ca0b9e7220911a6d1fccf34e532e69c7e37cd2fAnton Korobeynikov RC == ARM::DPR_8RegisterClass) { 780e5165490b7ba24bb2f3043399e0d60e7f3bcf8a5Jim Grosbach AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRD), DestReg) 781249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov .addFrameIndex(FI).addImm(0).addMemOperand(MMO)); 782baf31088f1472f48ea5ae81f0b93636cc44ca444Anton Korobeynikov } else if (RC == ARM::SPRRegisterClass) { 783e5165490b7ba24bb2f3043399e0d60e7f3bcf8a5Jim Grosbach AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRS), DestReg) 784249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov .addFrameIndex(FI).addImm(0).addMemOperand(MMO)); 785baf31088f1472f48ea5ae81f0b93636cc44ca444Anton Korobeynikov } else { 786e56f9085b1e96f0cc302c678f1c00877676e455eAnton Korobeynikov assert((RC == ARM::QPRRegisterClass || 787b4db6a46e0de3283fa70ea0a7d3623f2e4e2d2a3Evan Cheng RC == ARM::QPR_VFP2RegisterClass || 788b4db6a46e0de3283fa70ea0a7d3623f2e4e2d2a3Evan Cheng RC == ARM::QPR_8RegisterClass) && "Unknown regclass!"); 78931bc849123011b8eae6bb3c79876d9a3c26a6a1dJim Grosbach if (Align >= 16 790e45ab8a0a90e4f3a59d8c38038ae3e495ee1fef3Jim Grosbach && (getRegisterInfo().canRealignStack(MF))) { 791621f1952430ee8b01b21ac94404e52500d79838bBob Wilson AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1q), DestReg) 792226036ee731a2041f37f28f958d2b6a50373f4f4Bob Wilson .addFrameIndex(FI).addImm(128) 793ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng .addMemOperand(MMO)); 79431bc849123011b8eae6bb3c79876d9a3c26a6a1dJim Grosbach } else { 795c289a0252bba42248d7b11699dda27feca8860b6Bob Wilson AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMQ), DestReg) 796ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng .addFrameIndex(FI).addImm(0).addMemOperand(MMO)); 79731bc849123011b8eae6bb3c79876d9a3c26a6a1dJim Grosbach } 798334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 799334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 800334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 801334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinMachineInstr *ARMBaseInstrInfo:: 802334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinfoldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI, 803334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const SmallVectorImpl<unsigned> &Ops, int FI) const { 804334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (Ops.size() != 1) return NULL; 805334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 806334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned OpNum = Ops[0]; 807334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned Opc = MI->getOpcode(); 808334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineInstr *NewMI = NULL; 80919068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng if (Opc == ARM::MOVr || Opc == ARM::t2MOVr) { 810334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // If it is updating CPSR, then it cannot be folded. 81119068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng if (MI->getOperand(4).getReg() == ARM::CPSR && !MI->getOperand(4).isDead()) 81219068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng return NULL; 81319068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng unsigned Pred = MI->getOperand(2).getImm(); 81419068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng unsigned PredReg = MI->getOperand(3).getReg(); 81519068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng if (OpNum == 0) { // move -> store 81619068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng unsigned SrcReg = MI->getOperand(1).getReg(); 817ed3ad212ec34fa2866fb70f9e52ddda31032ea3bEvan Cheng unsigned SrcSubReg = MI->getOperand(1).getSubReg(); 81819068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng bool isKill = MI->getOperand(1).isKill(); 81919068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng bool isUndef = MI->getOperand(1).isUndef(); 82019068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng if (Opc == ARM::MOVr) 82119068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::STR)) 822ed3ad212ec34fa2866fb70f9e52ddda31032ea3bEvan Cheng .addReg(SrcReg, 823ed3ad212ec34fa2866fb70f9e52ddda31032ea3bEvan Cheng getKillRegState(isKill) | getUndefRegState(isUndef), 824ed3ad212ec34fa2866fb70f9e52ddda31032ea3bEvan Cheng SrcSubReg) 82519068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng .addFrameIndex(FI).addReg(0).addImm(0).addImm(Pred).addReg(PredReg); 82619068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng else // ARM::t2MOVr 82719068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::t2STRi12)) 828ed3ad212ec34fa2866fb70f9e52ddda31032ea3bEvan Cheng .addReg(SrcReg, 829ed3ad212ec34fa2866fb70f9e52ddda31032ea3bEvan Cheng getKillRegState(isKill) | getUndefRegState(isUndef), 830ed3ad212ec34fa2866fb70f9e52ddda31032ea3bEvan Cheng SrcSubReg) 83119068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg); 83219068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng } else { // move -> load 83319068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng unsigned DstReg = MI->getOperand(0).getReg(); 834ed3ad212ec34fa2866fb70f9e52ddda31032ea3bEvan Cheng unsigned DstSubReg = MI->getOperand(0).getSubReg(); 83519068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng bool isDead = MI->getOperand(0).isDead(); 83619068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng bool isUndef = MI->getOperand(0).isUndef(); 83719068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng if (Opc == ARM::MOVr) 83819068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::LDR)) 83919068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng .addReg(DstReg, 84019068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng RegState::Define | 84119068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng getDeadRegState(isDead) | 842ed3ad212ec34fa2866fb70f9e52ddda31032ea3bEvan Cheng getUndefRegState(isUndef), DstSubReg) 84319068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng .addFrameIndex(FI).addReg(0).addImm(0).addImm(Pred).addReg(PredReg); 84419068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng else // ARM::t2MOVr 84519068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::t2LDRi12)) 84619068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng .addReg(DstReg, 84719068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng RegState::Define | 84819068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng getDeadRegState(isDead) | 849ed3ad212ec34fa2866fb70f9e52ddda31032ea3bEvan Cheng getUndefRegState(isUndef), DstSubReg) 85019068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg); 851334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 85219068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng } else if (Opc == ARM::tMOVgpr2gpr || 85319068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng Opc == ARM::tMOVtgpr2gpr || 85419068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng Opc == ARM::tMOVgpr2tgpr) { 85519068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng if (OpNum == 0) { // move -> store 85619068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng unsigned SrcReg = MI->getOperand(1).getReg(); 857ed3ad212ec34fa2866fb70f9e52ddda31032ea3bEvan Cheng unsigned SrcSubReg = MI->getOperand(1).getSubReg(); 85819068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng bool isKill = MI->getOperand(1).isKill(); 85919068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng bool isUndef = MI->getOperand(1).isUndef(); 86019068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::t2STRi12)) 861ed3ad212ec34fa2866fb70f9e52ddda31032ea3bEvan Cheng .addReg(SrcReg, 862ed3ad212ec34fa2866fb70f9e52ddda31032ea3bEvan Cheng getKillRegState(isKill) | getUndefRegState(isUndef), 863ed3ad212ec34fa2866fb70f9e52ddda31032ea3bEvan Cheng SrcSubReg) 86419068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng .addFrameIndex(FI).addImm(0).addImm(ARMCC::AL).addReg(0); 86519068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng } else { // move -> load 86619068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng unsigned DstReg = MI->getOperand(0).getReg(); 867ed3ad212ec34fa2866fb70f9e52ddda31032ea3bEvan Cheng unsigned DstSubReg = MI->getOperand(0).getSubReg(); 86819068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng bool isDead = MI->getOperand(0).isDead(); 86919068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng bool isUndef = MI->getOperand(0).isUndef(); 87019068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::t2LDRi12)) 87119068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng .addReg(DstReg, 87219068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng RegState::Define | 87319068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng getDeadRegState(isDead) | 874ed3ad212ec34fa2866fb70f9e52ddda31032ea3bEvan Cheng getUndefRegState(isUndef), 875ed3ad212ec34fa2866fb70f9e52ddda31032ea3bEvan Cheng DstSubReg) 87619068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng .addFrameIndex(FI).addImm(0).addImm(ARMCC::AL).addReg(0); 87719068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng } 878e5165490b7ba24bb2f3043399e0d60e7f3bcf8a5Jim Grosbach } else if (Opc == ARM::VMOVS) { 879334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned Pred = MI->getOperand(2).getImm(); 880334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned PredReg = MI->getOperand(3).getReg(); 881334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (OpNum == 0) { // move -> store 882334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned SrcReg = MI->getOperand(1).getReg(); 883ed3ad212ec34fa2866fb70f9e52ddda31032ea3bEvan Cheng unsigned SrcSubReg = MI->getOperand(1).getSubReg(); 884334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool isKill = MI->getOperand(1).isKill(); 885334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool isUndef = MI->getOperand(1).isUndef(); 886e5165490b7ba24bb2f3043399e0d60e7f3bcf8a5Jim Grosbach NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::VSTRS)) 887ed3ad212ec34fa2866fb70f9e52ddda31032ea3bEvan Cheng .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef), 888ed3ad212ec34fa2866fb70f9e52ddda31032ea3bEvan Cheng SrcSubReg) 889334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addFrameIndex(FI) 890334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addImm(0).addImm(Pred).addReg(PredReg); 891334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } else { // move -> load 892334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned DstReg = MI->getOperand(0).getReg(); 893ed3ad212ec34fa2866fb70f9e52ddda31032ea3bEvan Cheng unsigned DstSubReg = MI->getOperand(0).getSubReg(); 894334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool isDead = MI->getOperand(0).isDead(); 895334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool isUndef = MI->getOperand(0).isUndef(); 896e5165490b7ba24bb2f3043399e0d60e7f3bcf8a5Jim Grosbach NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::VLDRS)) 897334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(DstReg, 898334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin RegState::Define | 899334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin getDeadRegState(isDead) | 900ed3ad212ec34fa2866fb70f9e52ddda31032ea3bEvan Cheng getUndefRegState(isUndef), 901ed3ad212ec34fa2866fb70f9e52ddda31032ea3bEvan Cheng DstSubReg) 902334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg); 903334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 904334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 905e5165490b7ba24bb2f3043399e0d60e7f3bcf8a5Jim Grosbach else if (Opc == ARM::VMOVD) { 906334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned Pred = MI->getOperand(2).getImm(); 907334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned PredReg = MI->getOperand(3).getReg(); 908334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (OpNum == 0) { // move -> store 909334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned SrcReg = MI->getOperand(1).getReg(); 910ed3ad212ec34fa2866fb70f9e52ddda31032ea3bEvan Cheng unsigned SrcSubReg = MI->getOperand(1).getSubReg(); 911334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool isKill = MI->getOperand(1).isKill(); 912334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool isUndef = MI->getOperand(1).isUndef(); 913e5165490b7ba24bb2f3043399e0d60e7f3bcf8a5Jim Grosbach NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::VSTRD)) 914ed3ad212ec34fa2866fb70f9e52ddda31032ea3bEvan Cheng .addReg(SrcReg, 915ed3ad212ec34fa2866fb70f9e52ddda31032ea3bEvan Cheng getKillRegState(isKill) | getUndefRegState(isUndef), 916ed3ad212ec34fa2866fb70f9e52ddda31032ea3bEvan Cheng SrcSubReg) 917334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg); 918334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } else { // move -> load 919334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned DstReg = MI->getOperand(0).getReg(); 920ed3ad212ec34fa2866fb70f9e52ddda31032ea3bEvan Cheng unsigned DstSubReg = MI->getOperand(0).getSubReg(); 921334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool isDead = MI->getOperand(0).isDead(); 922334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool isUndef = MI->getOperand(0).isUndef(); 923e5165490b7ba24bb2f3043399e0d60e7f3bcf8a5Jim Grosbach NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::VLDRD)) 924334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(DstReg, 925334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin RegState::Define | 926334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin getDeadRegState(isDead) | 927ed3ad212ec34fa2866fb70f9e52ddda31032ea3bEvan Cheng getUndefRegState(isUndef), 928ed3ad212ec34fa2866fb70f9e52ddda31032ea3bEvan Cheng DstSubReg) 929334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg); 930334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 931334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 932334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 933334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return NewMI; 934334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 935334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 936764ab52dd80310a205c9888bf166d09dab858f90Jim GrosbachMachineInstr* 937334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinARMBaseInstrInfo::foldMemoryOperandImpl(MachineFunction &MF, 938334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineInstr* MI, 939334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const SmallVectorImpl<unsigned> &Ops, 940334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineInstr* LoadMI) const { 9411f5c9887544ac2cb39d48e35cc6fa7a7b73ed3b0Evan Cheng // FIXME 942334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 0; 943334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 944334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 945334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinbool 946334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinARMBaseInstrInfo::canFoldMemoryOperand(const MachineInstr *MI, 947229464564243b24fb12cece515d727673e726994Evan Cheng const SmallVectorImpl<unsigned> &Ops) const { 948334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (Ops.size() != 1) return false; 949334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 950334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned Opc = MI->getOpcode(); 9515732ca084aaa0cd26149e50dd4b487efff37fe41Evan Cheng if (Opc == ARM::MOVr || Opc == ARM::t2MOVr) { 952334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // If it is updating CPSR, then it cannot be folded. 953229464564243b24fb12cece515d727673e726994Evan Cheng return MI->getOperand(4).getReg() != ARM::CPSR || 954229464564243b24fb12cece515d727673e726994Evan Cheng MI->getOperand(4).isDead(); 95519068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng } else if (Opc == ARM::tMOVgpr2gpr || 95619068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng Opc == ARM::tMOVtgpr2gpr || 95719068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng Opc == ARM::tMOVgpr2tgpr) { 95819068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng return true; 959e5165490b7ba24bb2f3043399e0d60e7f3bcf8a5Jim Grosbach } else if (Opc == ARM::VMOVS || Opc == ARM::VMOVD) { 960334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; 961e5165490b7ba24bb2f3043399e0d60e7f3bcf8a5Jim Grosbach } else if (Opc == ARM::VMOVDneon || Opc == ARM::VMOVQ) { 962334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; // FIXME 963334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 964334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 965334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 966334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 9675ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng 96830ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen/// Create a copy of a const pool value. Update CPI to the new index and return 96930ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen/// the label UID. 97030ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesenstatic unsigned duplicateCPV(MachineFunction &MF, unsigned &CPI) { 97130ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen MachineConstantPool *MCP = MF.getConstantPool(); 97230ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 97330ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen 97430ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPI]; 97530ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen assert(MCPE.isMachineConstantPoolEntry() && 97630ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen "Expecting a machine constantpool entry!"); 97730ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen ARMConstantPoolValue *ACPV = 97830ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal); 97930ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen 98030ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen unsigned PCLabelId = AFI->createConstPoolEntryUId(); 98130ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen ARMConstantPoolValue *NewCPV = 0; 98230ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen if (ACPV->isGlobalValue()) 98330ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen NewCPV = new ARMConstantPoolValue(ACPV->getGV(), PCLabelId, 98430ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen ARMCP::CPValue, 4); 98530ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen else if (ACPV->isExtSymbol()) 98630ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen NewCPV = new ARMConstantPoolValue(MF.getFunction()->getContext(), 98730ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen ACPV->getSymbol(), PCLabelId, 4); 98830ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen else if (ACPV->isBlockAddress()) 98930ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen NewCPV = new ARMConstantPoolValue(ACPV->getBlockAddress(), PCLabelId, 99030ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen ARMCP::CPBlockAddress, 4); 99130ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen else 99230ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen llvm_unreachable("Unexpected ARM constantpool value type!!"); 99330ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen CPI = MCP->getConstantPoolIndex(NewCPV, MCPE.getAlignment()); 99430ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen return PCLabelId; 99530ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen} 99630ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen 997fdc834046efd427d474e3b899ec69354c05071e0Evan Chengvoid ARMBaseInstrInfo:: 998fdc834046efd427d474e3b899ec69354c05071e0Evan ChengreMaterialize(MachineBasicBlock &MBB, 999fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng MachineBasicBlock::iterator I, 1000fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng unsigned DestReg, unsigned SubIdx, 1001d57cdd5683ea926e489067364fb7ffe5fd5d35eeEvan Cheng const MachineInstr *Orig, 1002d57cdd5683ea926e489067364fb7ffe5fd5d35eeEvan Cheng const TargetRegisterInfo *TRI) const { 1003d57cdd5683ea926e489067364fb7ffe5fd5d35eeEvan Cheng if (SubIdx && TargetRegisterInfo::isPhysicalRegister(DestReg)) { 1004d57cdd5683ea926e489067364fb7ffe5fd5d35eeEvan Cheng DestReg = TRI->getSubReg(DestReg, SubIdx); 1005d57cdd5683ea926e489067364fb7ffe5fd5d35eeEvan Cheng SubIdx = 0; 1006d57cdd5683ea926e489067364fb7ffe5fd5d35eeEvan Cheng } 1007d57cdd5683ea926e489067364fb7ffe5fd5d35eeEvan Cheng 1008fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng unsigned Opcode = Orig->getOpcode(); 1009fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng switch (Opcode) { 1010fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng default: { 1011fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig); 1012fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng MI->getOperand(0).setReg(DestReg); 1013fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng MBB.insert(I, MI); 1014fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng break; 1015fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng } 1016fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng case ARM::tLDRpci_pic: 1017fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng case ARM::t2LDRpci_pic: { 1018fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng MachineFunction &MF = *MBB.getParent(); 1019fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng unsigned CPI = Orig->getOperand(1).getIndex(); 102030ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen unsigned PCLabelId = duplicateCPV(MF, CPI); 1021fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng MachineInstrBuilder MIB = BuildMI(MBB, I, Orig->getDebugLoc(), get(Opcode), 1022fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng DestReg) 1023fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng .addConstantPoolIndex(CPI).addImm(PCLabelId); 1024fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng (*MIB).setMemRefs(Orig->memoperands_begin(), Orig->memoperands_end()); 1025fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng break; 1026fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng } 1027fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng } 1028fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng 1029fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng MachineInstr *NewMI = prior(I); 1030fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng NewMI->getOperand(0).setSubReg(SubIdx); 1031fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng} 1032fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng 103330ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund OlesenMachineInstr * 103430ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund OlesenARMBaseInstrInfo::duplicate(MachineInstr *Orig, MachineFunction &MF) const { 103530ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen MachineInstr *MI = TargetInstrInfoImpl::duplicate(Orig, MF); 103630ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen switch(Orig->getOpcode()) { 103730ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen case ARM::tLDRpci_pic: 103830ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen case ARM::t2LDRpci_pic: { 103930ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen unsigned CPI = Orig->getOperand(1).getIndex(); 104030ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen unsigned PCLabelId = duplicateCPV(MF, CPI); 104130ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen Orig->getOperand(1).setIndex(CPI); 104230ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen Orig->getOperand(2).setImm(PCLabelId); 104330ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen break; 104430ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen } 104530ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen } 104630ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen return MI; 104730ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen} 104830ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen 1049506049f29f4f202a8e45feb916cc0264440a7f6dEvan Chengbool ARMBaseInstrInfo::produceSameValue(const MachineInstr *MI0, 1050506049f29f4f202a8e45feb916cc0264440a7f6dEvan Cheng const MachineInstr *MI1) const { 1051d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng int Opcode = MI0->getOpcode(); 10529b82425cb0105fd5704f6b9bcd5e7693b05b1759Evan Cheng if (Opcode == ARM::t2LDRpci || 10539b82425cb0105fd5704f6b9bcd5e7693b05b1759Evan Cheng Opcode == ARM::t2LDRpci_pic || 10549b82425cb0105fd5704f6b9bcd5e7693b05b1759Evan Cheng Opcode == ARM::tLDRpci || 10559b82425cb0105fd5704f6b9bcd5e7693b05b1759Evan Cheng Opcode == ARM::tLDRpci_pic) { 1056d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng if (MI1->getOpcode() != Opcode) 1057d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng return false; 1058d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng if (MI0->getNumOperands() != MI1->getNumOperands()) 1059d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng return false; 1060d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng 1061d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng const MachineOperand &MO0 = MI0->getOperand(1); 1062d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng const MachineOperand &MO1 = MI1->getOperand(1); 1063d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng if (MO0.getOffset() != MO1.getOffset()) 1064d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng return false; 1065d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng 1066d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng const MachineFunction *MF = MI0->getParent()->getParent(); 1067d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng const MachineConstantPool *MCP = MF->getConstantPool(); 1068d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng int CPI0 = MO0.getIndex(); 1069d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng int CPI1 = MO1.getIndex(); 1070d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng const MachineConstantPoolEntry &MCPE0 = MCP->getConstants()[CPI0]; 1071d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng const MachineConstantPoolEntry &MCPE1 = MCP->getConstants()[CPI1]; 1072d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng ARMConstantPoolValue *ACPV0 = 1073d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng static_cast<ARMConstantPoolValue*>(MCPE0.Val.MachineCPVal); 1074d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng ARMConstantPoolValue *ACPV1 = 1075d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng static_cast<ARMConstantPoolValue*>(MCPE1.Val.MachineCPVal); 1076d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng return ACPV0->hasSameValue(ACPV1); 1077d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng } 1078d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng 1079506049f29f4f202a8e45feb916cc0264440a7f6dEvan Cheng return MI0->isIdenticalTo(MI1, MachineInstr::IgnoreVRegDefs); 1080d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng} 1081d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng 10828fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng/// getInstrPredicate - If instruction is predicated, returns its predicate 10838fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng/// condition, otherwise returns AL. It also returns the condition code 10848fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng/// register by reference. 10855adb66a646e2ec32265263739f5b01c3f50c176aEvan ChengARMCC::CondCodes 10865adb66a646e2ec32265263739f5b01c3f50c176aEvan Chengllvm::getInstrPredicate(const MachineInstr *MI, unsigned &PredReg) { 10878fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng int PIdx = MI->findFirstPredOperandIdx(); 10888fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng if (PIdx == -1) { 10898fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng PredReg = 0; 10908fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng return ARMCC::AL; 10918fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng } 10928fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng 10938fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng PredReg = MI->getOperand(PIdx+1).getReg(); 10948fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng return (ARMCC::CondCodes)MI->getOperand(PIdx).getImm(); 10958fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng} 10968fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng 10978fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng 10986495f63945e8dbde81f03a1dc2ab421993b9a495Evan Chengint llvm::getMatchingCondBranchOpcode(int Opc) { 10995ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng if (Opc == ARM::B) 11005ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng return ARM::Bcc; 11015ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng else if (Opc == ARM::tB) 11025ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng return ARM::tBcc; 11035ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng else if (Opc == ARM::t2B) 11045ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng return ARM::t2Bcc; 11055ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng 11065ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng llvm_unreachable("Unknown unconditional branch opcode!"); 11075ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng return 0; 11085ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng} 11095ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng 11106495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 11116495f63945e8dbde81f03a1dc2ab421993b9a495Evan Chengvoid llvm::emitARMRegPlusImmediate(MachineBasicBlock &MBB, 11126495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MachineBasicBlock::iterator &MBBI, DebugLoc dl, 11136495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned DestReg, unsigned BaseReg, int NumBytes, 11146495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ARMCC::CondCodes Pred, unsigned PredReg, 11156495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng const ARMBaseInstrInfo &TII) { 11166495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng bool isSub = NumBytes < 0; 11176495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (isSub) NumBytes = -NumBytes; 11186495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 11196495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng while (NumBytes) { 11206495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned RotAmt = ARM_AM::getSOImmValRotate(NumBytes); 11216495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned ThisVal = NumBytes & ARM_AM::rotr32(0xFF, RotAmt); 11226495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng assert(ThisVal && "Didn't extract field correctly"); 11236495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 11246495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // We will handle these bits from offset, clear them. 11256495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng NumBytes &= ~ThisVal; 11266495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 11276495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng assert(ARM_AM::getSOImmVal(ThisVal) != -1 && "Bit extraction didn't work?"); 11286495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 11296495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Build the new ADD / SUB. 11306495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned Opc = isSub ? ARM::SUBri : ARM::ADDri; 11316495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg) 11326495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng .addReg(BaseReg, RegState::Kill).addImm(ThisVal) 11336495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng .addImm((unsigned)Pred).addReg(PredReg).addReg(0); 11346495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng BaseReg = DestReg; 11356495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 11366495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng} 11376495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 1138cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Chengbool llvm::rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx, 1139cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng unsigned FrameReg, int &Offset, 1140cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng const ARMBaseInstrInfo &TII) { 11416495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned Opcode = MI.getOpcode(); 11426495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng const TargetInstrDesc &Desc = MI.getDesc(); 11436495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask); 11446495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng bool isSub = false; 1145764ab52dd80310a205c9888bf166d09dab858f90Jim Grosbach 11466495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Memory operands in inline assembly always use AddrMode2. 11476495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (Opcode == ARM::INLINEASM) 11486495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng AddrMode = ARMII::AddrMode2; 1149764ab52dd80310a205c9888bf166d09dab858f90Jim Grosbach 11506495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (Opcode == ARM::ADDri) { 11516495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng Offset += MI.getOperand(FrameRegIdx+1).getImm(); 11526495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (Offset == 0) { 11536495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Turn it into a move. 11546495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MI.setDesc(TII.get(ARM::MOVr)); 11556495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false); 11566495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MI.RemoveOperand(FrameRegIdx+1); 1157cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng Offset = 0; 1158cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng return true; 11596495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } else if (Offset < 0) { 11606495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng Offset = -Offset; 11616495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng isSub = true; 11626495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MI.setDesc(TII.get(ARM::SUBri)); 11636495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 11646495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 11656495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Common case: small offset, fits into instruction. 11666495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (ARM_AM::getSOImmVal(Offset) != -1) { 11676495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Replace the FrameIndex with sp / fp 11686495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false); 11696495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset); 1170cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng Offset = 0; 1171cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng return true; 11726495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 11736495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 11746495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Otherwise, pull as much of the immedidate into this ADDri/SUBri 11756495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // as possible. 11766495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned RotAmt = ARM_AM::getSOImmValRotate(Offset); 11776495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xFF, RotAmt); 11786495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 11796495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // We will handle these bits from offset, clear them. 11806495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng Offset &= ~ThisImmVal; 11816495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 11826495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Get the properly encoded SOImmVal field. 11836495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng assert(ARM_AM::getSOImmVal(ThisImmVal) != -1 && 11846495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng "Bit extraction didn't work?"); 11856495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MI.getOperand(FrameRegIdx+1).ChangeToImmediate(ThisImmVal); 11866495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } else { 11876495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned ImmIdx = 0; 11886495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng int InstrOffs = 0; 11896495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned NumBits = 0; 11906495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned Scale = 1; 11916495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng switch (AddrMode) { 11926495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng case ARMII::AddrMode2: { 11936495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ImmIdx = FrameRegIdx+2; 11946495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng InstrOffs = ARM_AM::getAM2Offset(MI.getOperand(ImmIdx).getImm()); 11956495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (ARM_AM::getAM2Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub) 11966495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng InstrOffs *= -1; 11976495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng NumBits = 12; 11986495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng break; 11996495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 12006495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng case ARMII::AddrMode3: { 12016495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ImmIdx = FrameRegIdx+2; 12026495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng InstrOffs = ARM_AM::getAM3Offset(MI.getOperand(ImmIdx).getImm()); 12036495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (ARM_AM::getAM3Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub) 12046495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng InstrOffs *= -1; 12056495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng NumBits = 8; 12066495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng break; 12076495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 1208baf31088f1472f48ea5ae81f0b93636cc44ca444Anton Korobeynikov case ARMII::AddrMode4: 1209a44321776ecd96fa0344335d3027758be3386e45Jim Grosbach case ARMII::AddrMode6: 1210cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng // Can't fold any offset even if it's zero. 1211cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng return false; 12126495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng case ARMII::AddrMode5: { 12136495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ImmIdx = FrameRegIdx+1; 12146495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng InstrOffs = ARM_AM::getAM5Offset(MI.getOperand(ImmIdx).getImm()); 12156495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (ARM_AM::getAM5Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub) 12166495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng InstrOffs *= -1; 12176495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng NumBits = 8; 12186495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng Scale = 4; 12196495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng break; 12206495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 12216495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng default: 12226495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng llvm_unreachable("Unsupported addressing mode!"); 12236495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng break; 12246495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 12256495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 12266495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng Offset += InstrOffs * Scale; 12276495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!"); 12286495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (Offset < 0) { 12296495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng Offset = -Offset; 12306495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng isSub = true; 12316495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 12326495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 12336495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Attempt to fold address comp. if opcode has offset bits 12346495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (NumBits > 0) { 12356495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Common case: small offset, fits into instruction. 12366495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MachineOperand &ImmOp = MI.getOperand(ImmIdx); 12376495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng int ImmedOffset = Offset / Scale; 12386495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned Mask = (1 << NumBits) - 1; 12396495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if ((unsigned)Offset <= Mask * Scale) { 12406495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Replace the FrameIndex with sp 12416495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false); 12426495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (isSub) 12436495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ImmedOffset |= 1 << NumBits; 12446495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ImmOp.ChangeToImmediate(ImmedOffset); 1245cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng Offset = 0; 1246cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng return true; 12476495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 1248764ab52dd80310a205c9888bf166d09dab858f90Jim Grosbach 12496495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Otherwise, it didn't fit. Pull in what we can to simplify the immed. 12506495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ImmedOffset = ImmedOffset & Mask; 12516495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (isSub) 12526495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ImmedOffset |= 1 << NumBits; 12536495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ImmOp.ChangeToImmediate(ImmedOffset); 12546495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng Offset &= ~(Mask*Scale); 12556495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 12566495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 12576495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 1258cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng Offset = (isSub) ? -Offset : Offset; 1259cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng return Offset == 0; 12606495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng} 1261