ARMBaseInstrInfo.cpp revision d57cdd5683ea926e489067364fb7ffe5fd5d35ee 
1//===- ARMBaseInstrInfo.cpp - ARM Instruction Information -------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the Base ARM implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "ARMBaseInstrInfo.h"
15#include "ARM.h"
16#include "ARMAddressingModes.h"
17#include "ARMConstantPoolValue.h"
18#include "ARMGenInstrInfo.inc"
19#include "ARMMachineFunctionInfo.h"
20#include "ARMRegisterInfo.h"
21#include "llvm/Constants.h"
22#include "llvm/Function.h"
23#include "llvm/GlobalValue.h"
24#include "llvm/ADT/STLExtras.h"
25#include "llvm/CodeGen/LiveVariables.h"
26#include "llvm/CodeGen/MachineConstantPool.h"
27#include "llvm/CodeGen/MachineFrameInfo.h"
28#include "llvm/CodeGen/MachineInstrBuilder.h"
29#include "llvm/CodeGen/MachineJumpTableInfo.h"
30#include "llvm/CodeGen/MachineMemOperand.h"
31#include "llvm/CodeGen/PseudoSourceValue.h"
32#include "llvm/MC/MCAsmInfo.h"
33#include "llvm/Support/CommandLine.h"
34#include "llvm/Support/Debug.h"
35#include "llvm/Support/ErrorHandling.h"
36using namespace llvm;
37
38static cl::opt<bool>
39EnableARM3Addr("enable-arm-3-addr-conv", cl::Hidden,
40               cl::desc("Enable ARM 2-addr to 3-addr conv"));
41
42ARMBaseInstrInfo::ARMBaseInstrInfo(const ARMSubtarget& STI)
43  : TargetInstrInfoImpl(ARMInsts, array_lengthof(ARMInsts)),
44    Subtarget(STI) {
45}
46
47MachineInstr *
48ARMBaseInstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
49                                        MachineBasicBlock::iterator &MBBI,
50                                        LiveVariables *LV) const {
51  // FIXME: Thumb2 support.
52
53  if (!EnableARM3Addr)
54    return NULL;
55
56  MachineInstr *MI = MBBI;
57  MachineFunction &MF = *MI->getParent()->getParent();
58  unsigned TSFlags = MI->getDesc().TSFlags;
59  bool isPre = false;
60  switch ((TSFlags & ARMII::IndexModeMask) >> ARMII::IndexModeShift) {
61  default: return NULL;
62  case ARMII::IndexModePre:
63    isPre = true;
64    break;
65  case ARMII::IndexModePost:
66    break;
67  }
68
69  // Try splitting an indexed load/store to an un-indexed one plus an add/sub
70  // operation.
71  unsigned MemOpc = getUnindexedOpcode(MI->getOpcode());
72  if (MemOpc == 0)
73    return NULL;
74
75  MachineInstr *UpdateMI = NULL;
76  MachineInstr *MemMI = NULL;
77  unsigned AddrMode = (TSFlags & ARMII::AddrModeMask);
78  const TargetInstrDesc &TID = MI->getDesc();
79  unsigned NumOps = TID.getNumOperands();
80  bool isLoad = !TID.mayStore();
81  const MachineOperand &WB = isLoad ? MI->getOperand(1) : MI->getOperand(0);
82  const MachineOperand &Base = MI->getOperand(2);
83  const MachineOperand &Offset = MI->getOperand(NumOps-3);
84  unsigned WBReg = WB.getReg();
85  unsigned BaseReg = Base.getReg();
86  unsigned OffReg = Offset.getReg();
87  unsigned OffImm = MI->getOperand(NumOps-2).getImm();
88  ARMCC::CondCodes Pred = (ARMCC::CondCodes)MI->getOperand(NumOps-1).getImm();
89  switch (AddrMode) {
90  default:
91    assert(false && "Unknown indexed op!");
92    return NULL;
93  case ARMII::AddrMode2: {
94    bool isSub = ARM_AM::getAM2Op(OffImm) == ARM_AM::sub;
95    unsigned Amt = ARM_AM::getAM2Offset(OffImm);
96    if (OffReg == 0) {
97      if (ARM_AM::getSOImmVal(Amt) == -1)
98        // Can't encode it in a so_imm operand. This transformation will
99        // add more than 1 instruction. Abandon!
100        return NULL;
101      UpdateMI = BuildMI(MF, MI->getDebugLoc(),
102                         get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
103        .addReg(BaseReg).addImm(Amt)
104        .addImm(Pred).addReg(0).addReg(0);
105    } else if (Amt != 0) {
106      ARM_AM::ShiftOpc ShOpc = ARM_AM::getAM2ShiftOpc(OffImm);
107      unsigned SOOpc = ARM_AM::getSORegOpc(ShOpc, Amt);
108      UpdateMI = BuildMI(MF, MI->getDebugLoc(),
109                         get(isSub ? ARM::SUBrs : ARM::ADDrs), WBReg)
110        .addReg(BaseReg).addReg(OffReg).addReg(0).addImm(SOOpc)
111        .addImm(Pred).addReg(0).addReg(0);
112    } else
113      UpdateMI = BuildMI(MF, MI->getDebugLoc(),
114                         get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
115        .addReg(BaseReg).addReg(OffReg)
116        .addImm(Pred).addReg(0).addReg(0);
117    break;
118  }
119  case ARMII::AddrMode3 : {
120    bool isSub = ARM_AM::getAM3Op(OffImm) == ARM_AM::sub;
121    unsigned Amt = ARM_AM::getAM3Offset(OffImm);
122    if (OffReg == 0)
123      // Immediate is 8-bits. It's guaranteed to fit in a so_imm operand.
124      UpdateMI = BuildMI(MF, MI->getDebugLoc(),
125                         get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
126        .addReg(BaseReg).addImm(Amt)
127        .addImm(Pred).addReg(0).addReg(0);
128    else
129      UpdateMI = BuildMI(MF, MI->getDebugLoc(),
130                         get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
131        .addReg(BaseReg).addReg(OffReg)
132        .addImm(Pred).addReg(0).addReg(0);
133    break;
134  }
135  }
136
137  std::vector<MachineInstr*> NewMIs;
138  if (isPre) {
139    if (isLoad)
140      MemMI = BuildMI(MF, MI->getDebugLoc(),
141                      get(MemOpc), MI->getOperand(0).getReg())
142        .addReg(WBReg).addReg(0).addImm(0).addImm(Pred);
143    else
144      MemMI = BuildMI(MF, MI->getDebugLoc(),
145                      get(MemOpc)).addReg(MI->getOperand(1).getReg())
146        .addReg(WBReg).addReg(0).addImm(0).addImm(Pred);
147    NewMIs.push_back(MemMI);
148    NewMIs.push_back(UpdateMI);
149  } else {
150    if (isLoad)
151      MemMI = BuildMI(MF, MI->getDebugLoc(),
152                      get(MemOpc), MI->getOperand(0).getReg())
153        .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred);
154    else
155      MemMI = BuildMI(MF, MI->getDebugLoc(),
156                      get(MemOpc)).addReg(MI->getOperand(1).getReg())
157        .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred);
158    if (WB.isDead())
159      UpdateMI->getOperand(0).setIsDead();
160    NewMIs.push_back(UpdateMI);
161    NewMIs.push_back(MemMI);
162  }
163
164  // Transfer LiveVariables states, kill / dead info.
165  if (LV) {
166    for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
167      MachineOperand &MO = MI->getOperand(i);
168      if (MO.isReg() && MO.getReg() &&
169          TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
170        unsigned Reg = MO.getReg();
171
172        LiveVariables::VarInfo &VI = LV->getVarInfo(Reg);
173        if (MO.isDef()) {
174          MachineInstr *NewMI = (Reg == WBReg) ? UpdateMI : MemMI;
175          if (MO.isDead())
176            LV->addVirtualRegisterDead(Reg, NewMI);
177        }
178        if (MO.isUse() && MO.isKill()) {
179          for (unsigned j = 0; j < 2; ++j) {
180            // Look at the two new MI's in reverse order.
181            MachineInstr *NewMI = NewMIs[j];
182            if (!NewMI->readsRegister(Reg))
183              continue;
184            LV->addVirtualRegisterKilled(Reg, NewMI);
185            if (VI.removeKill(MI))
186              VI.Kills.push_back(NewMI);
187            break;
188          }
189        }
190      }
191    }
192  }
193
194  MFI->insert(MBBI, NewMIs[1]);
195  MFI->insert(MBBI, NewMIs[0]);
196  return NewMIs[0];
197}
198
199// Branch analysis.
200bool
201ARMBaseInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
202                                MachineBasicBlock *&FBB,
203                                SmallVectorImpl<MachineOperand> &Cond,
204                                bool AllowModify) const {
205  // If the block has no terminators, it just falls into the block after it.
206  MachineBasicBlock::iterator I = MBB.end();
207  if (I == MBB.begin() || !isUnpredicatedTerminator(--I))
208    return false;
209
210  // Get the last instruction in the block.
211  MachineInstr *LastInst = I;
212
213  // If there is only one terminator instruction, process it.
214  unsigned LastOpc = LastInst->getOpcode();
215  if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
216    if (isUncondBranchOpcode(LastOpc)) {
217      TBB = LastInst->getOperand(0).getMBB();
218      return false;
219    }
220    if (isCondBranchOpcode(LastOpc)) {
221      // Block ends with fall-through condbranch.
222      TBB = LastInst->getOperand(0).getMBB();
223      Cond.push_back(LastInst->getOperand(1));
224      Cond.push_back(LastInst->getOperand(2));
225      return false;
226    }
227    return true;  // Can't handle indirect branch.
228  }
229
230  // Get the instruction before it if it is a terminator.
231  MachineInstr *SecondLastInst = I;
232
233  // If there are three terminators, we don't know what sort of block this is.
234  if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(--I))
235    return true;
236
237  // If the block ends with a B and a Bcc, handle it.
238  unsigned SecondLastOpc = SecondLastInst->getOpcode();
239  if (isCondBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) {
240    TBB =  SecondLastInst->getOperand(0).getMBB();
241    Cond.push_back(SecondLastInst->getOperand(1));
242    Cond.push_back(SecondLastInst->getOperand(2));
243    FBB = LastInst->getOperand(0).getMBB();
244    return false;
245  }
246
247  // If the block ends with two unconditional branches, handle it.  The second
248  // one is not executed, so remove it.
249  if (isUncondBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) {
250    TBB = SecondLastInst->getOperand(0).getMBB();
251    I = LastInst;
252    if (AllowModify)
253      I->eraseFromParent();
254    return false;
255  }
256
257  // ...likewise if it ends with a branch table followed by an unconditional
258  // branch. The branch folder can create these, and we must get rid of them for
259  // correctness of Thumb constant islands.
260  if ((isJumpTableBranchOpcode(SecondLastOpc) ||
261       isIndirectBranchOpcode(SecondLastOpc)) &&
262      isUncondBranchOpcode(LastOpc)) {
263    I = LastInst;
264    if (AllowModify)
265      I->eraseFromParent();
266    return true;
267  }
268
269  // Otherwise, can't handle this.
270  return true;
271}
272
273
274unsigned ARMBaseInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
275  MachineBasicBlock::iterator I = MBB.end();
276  if (I == MBB.begin()) return 0;
277  --I;
278  if (!isUncondBranchOpcode(I->getOpcode()) &&
279      !isCondBranchOpcode(I->getOpcode()))
280    return 0;
281
282  // Remove the branch.
283  I->eraseFromParent();
284
285  I = MBB.end();
286
287  if (I == MBB.begin()) return 1;
288  --I;
289  if (!isCondBranchOpcode(I->getOpcode()))
290    return 1;
291
292  // Remove the branch.
293  I->eraseFromParent();
294  return 2;
295}
296
297unsigned
298ARMBaseInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
299                               MachineBasicBlock *FBB,
300                             const SmallVectorImpl<MachineOperand> &Cond) const {
301  // FIXME this should probably have a DebugLoc argument
302  DebugLoc dl = DebugLoc::getUnknownLoc();
303
304  ARMFunctionInfo *AFI = MBB.getParent()->getInfo<ARMFunctionInfo>();
305  int BOpc   = !AFI->isThumbFunction()
306    ? ARM::B : (AFI->isThumb2Function() ? ARM::t2B : ARM::tB);
307  int BccOpc = !AFI->isThumbFunction()
308    ? ARM::Bcc : (AFI->isThumb2Function() ? ARM::t2Bcc : ARM::tBcc);
309
310  // Shouldn't be a fall through.
311  assert(TBB && "InsertBranch must not be told to insert a fallthrough");
312  assert((Cond.size() == 2 || Cond.size() == 0) &&
313         "ARM branch conditions have two components!");
314
315  if (FBB == 0) {
316    if (Cond.empty()) // Unconditional branch?
317      BuildMI(&MBB, dl, get(BOpc)).addMBB(TBB);
318    else
319      BuildMI(&MBB, dl, get(BccOpc)).addMBB(TBB)
320        .addImm(Cond[0].getImm()).addReg(Cond[1].getReg());
321    return 1;
322  }
323
324  // Two-way conditional branch.
325  BuildMI(&MBB, dl, get(BccOpc)).addMBB(TBB)
326    .addImm(Cond[0].getImm()).addReg(Cond[1].getReg());
327  BuildMI(&MBB, dl, get(BOpc)).addMBB(FBB);
328  return 2;
329}
330
331bool ARMBaseInstrInfo::
332ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
333  ARMCC::CondCodes CC = (ARMCC::CondCodes)(int)Cond[0].getImm();
334  Cond[0].setImm(ARMCC::getOppositeCondition(CC));
335  return false;
336}
337
338bool ARMBaseInstrInfo::
339PredicateInstruction(MachineInstr *MI,
340                     const SmallVectorImpl<MachineOperand> &Pred) const {
341  unsigned Opc = MI->getOpcode();
342  if (isUncondBranchOpcode(Opc)) {
343    MI->setDesc(get(getMatchingCondBranchOpcode(Opc)));
344    MI->addOperand(MachineOperand::CreateImm(Pred[0].getImm()));
345    MI->addOperand(MachineOperand::CreateReg(Pred[1].getReg(), false));
346    return true;
347  }
348
349  int PIdx = MI->findFirstPredOperandIdx();
350  if (PIdx != -1) {
351    MachineOperand &PMO = MI->getOperand(PIdx);
352    PMO.setImm(Pred[0].getImm());
353    MI->getOperand(PIdx+1).setReg(Pred[1].getReg());
354    return true;
355  }
356  return false;
357}
358
359bool ARMBaseInstrInfo::
360SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
361                  const SmallVectorImpl<MachineOperand> &Pred2) const {
362  if (Pred1.size() > 2 || Pred2.size() > 2)
363    return false;
364
365  ARMCC::CondCodes CC1 = (ARMCC::CondCodes)Pred1[0].getImm();
366  ARMCC::CondCodes CC2 = (ARMCC::CondCodes)Pred2[0].getImm();
367  if (CC1 == CC2)
368    return true;
369
370  switch (CC1) {
371  default:
372    return false;
373  case ARMCC::AL:
374    return true;
375  case ARMCC::HS:
376    return CC2 == ARMCC::HI;
377  case ARMCC::LS:
378    return CC2 == ARMCC::LO || CC2 == ARMCC::EQ;
379  case ARMCC::GE:
380    return CC2 == ARMCC::GT;
381  case ARMCC::LE:
382    return CC2 == ARMCC::LT;
383  }
384}
385
386bool ARMBaseInstrInfo::DefinesPredicate(MachineInstr *MI,
387                                    std::vector<MachineOperand> &Pred) const {
388  // FIXME: This confuses implicit_def with optional CPSR def.
389  const TargetInstrDesc &TID = MI->getDesc();
390  if (!TID.getImplicitDefs() && !TID.hasOptionalDef())
391    return false;
392
393  bool Found = false;
394  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
395    const MachineOperand &MO = MI->getOperand(i);
396    if (MO.isReg() && MO.getReg() == ARM::CPSR) {
397      Pred.push_back(MO);
398      Found = true;
399    }
400  }
401
402  return Found;
403}
404
405
406/// FIXME: Works around a gcc miscompilation with -fstrict-aliasing
407static unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT,
408                                unsigned JTI) DISABLE_INLINE;
409static unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT,
410                                unsigned JTI) {
411  return JT[JTI].MBBs.size();
412}
413
414/// GetInstSize - Return the size of the specified MachineInstr.
415///
416unsigned ARMBaseInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
417  const MachineBasicBlock &MBB = *MI->getParent();
418  const MachineFunction *MF = MBB.getParent();
419  const MCAsmInfo *MAI = MF->getTarget().getMCAsmInfo();
420
421  // Basic size info comes from the TSFlags field.
422  const TargetInstrDesc &TID = MI->getDesc();
423  unsigned TSFlags = TID.TSFlags;
424
425  unsigned Opc = MI->getOpcode();
426  switch ((TSFlags & ARMII::SizeMask) >> ARMII::SizeShift) {
427  default: {
428    // If this machine instr is an inline asm, measure it.
429    if (MI->getOpcode() == ARM::INLINEASM)
430      return getInlineAsmLength(MI->getOperand(0).getSymbolName(), *MAI);
431    if (MI->isLabel())
432      return 0;
433    switch (Opc) {
434    default:
435      llvm_unreachable("Unknown or unset size field for instr!");
436    case TargetInstrInfo::IMPLICIT_DEF:
437    case TargetInstrInfo::KILL:
438    case TargetInstrInfo::DBG_LABEL:
439    case TargetInstrInfo::EH_LABEL:
440      return 0;
441    }
442    break;
443  }
444  case ARMII::Size8Bytes: return 8;          // ARM instruction x 2.
445  case ARMII::Size4Bytes: return 4;          // ARM / Thumb2 instruction.
446  case ARMII::Size2Bytes: return 2;          // Thumb1 instruction.
447  case ARMII::SizeSpecial: {
448    switch (Opc) {
449    case ARM::CONSTPOOL_ENTRY:
450      // If this machine instr is a constant pool entry, its size is recorded as
451      // operand #2.
452      return MI->getOperand(2).getImm();
453    case ARM::Int_eh_sjlj_setjmp:
454      return 24;
455    case ARM::t2Int_eh_sjlj_setjmp:
456      return 22;
457    case ARM::BR_JTr:
458    case ARM::BR_JTm:
459    case ARM::BR_JTadd:
460    case ARM::tBR_JTr:
461    case ARM::t2BR_JT:
462    case ARM::t2TBB:
463    case ARM::t2TBH: {
464      // These are jumptable branches, i.e. a branch followed by an inlined
465      // jumptable. The size is 4 + 4 * number of entries. For TBB, each
466      // entry is one byte; TBH two byte each.
467      unsigned EntrySize = (Opc == ARM::t2TBB)
468        ? 1 : ((Opc == ARM::t2TBH) ? 2 : 4);
469      unsigned NumOps = TID.getNumOperands();
470      MachineOperand JTOP =
471        MI->getOperand(NumOps - (TID.isPredicable() ? 3 : 2));
472      unsigned JTI = JTOP.getIndex();
473      const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
474      const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
475      assert(JTI < JT.size());
476      // Thumb instructions are 2 byte aligned, but JT entries are 4 byte
477      // 4 aligned. The assembler / linker may add 2 byte padding just before
478      // the JT entries.  The size does not include this padding; the
479      // constant islands pass does separate bookkeeping for it.
480      // FIXME: If we know the size of the function is less than (1 << 16) *2
481      // bytes, we can use 16-bit entries instead. Then there won't be an
482      // alignment issue.
483      unsigned InstSize = (Opc == ARM::tBR_JTr || Opc == ARM::t2BR_JT) ? 2 : 4;
484      unsigned NumEntries = getNumJTEntries(JT, JTI);
485      if (Opc == ARM::t2TBB && (NumEntries & 1))
486        // Make sure the instruction that follows TBB is 2-byte aligned.
487        // FIXME: Constant island pass should insert an "ALIGN" instruction
488        // instead.
489        ++NumEntries;
490      return NumEntries * EntrySize + InstSize;
491    }
492    default:
493      // Otherwise, pseudo-instruction sizes are zero.
494      return 0;
495    }
496  }
497  }
498  return 0; // Not reached
499}
500
501/// Return true if the instruction is a register to register move and
502/// leave the source and dest operands in the passed parameters.
503///
504bool
505ARMBaseInstrInfo::isMoveInstr(const MachineInstr &MI,
506                              unsigned &SrcReg, unsigned &DstReg,
507                              unsigned& SrcSubIdx, unsigned& DstSubIdx) const {
508  SrcSubIdx = DstSubIdx = 0; // No sub-registers.
509
510  switch (MI.getOpcode()) {
511  default: break;
512  case ARM::VMOVS:
513  case ARM::VMOVD:
514  case ARM::VMOVDneon:
515  case ARM::VMOVQ: {
516    SrcReg = MI.getOperand(1).getReg();
517    DstReg = MI.getOperand(0).getReg();
518    return true;
519  }
520  case ARM::MOVr:
521  case ARM::tMOVr:
522  case ARM::tMOVgpr2tgpr:
523  case ARM::tMOVtgpr2gpr:
524  case ARM::tMOVgpr2gpr:
525  case ARM::t2MOVr: {
526    assert(MI.getDesc().getNumOperands() >= 2 &&
527           MI.getOperand(0).isReg() &&
528           MI.getOperand(1).isReg() &&
529           "Invalid ARM MOV instruction");
530    SrcReg = MI.getOperand(1).getReg();
531    DstReg = MI.getOperand(0).getReg();
532    return true;
533  }
534  }
535
536  return false;
537}
538
539unsigned
540ARMBaseInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
541                                      int &FrameIndex) const {
542  switch (MI->getOpcode()) {
543  default: break;
544  case ARM::LDR:
545  case ARM::t2LDRs:  // FIXME: don't use t2LDRs to access frame.
546    if (MI->getOperand(1).isFI() &&
547        MI->getOperand(2).isReg() &&
548        MI->getOperand(3).isImm() &&
549        MI->getOperand(2).getReg() == 0 &&
550        MI->getOperand(3).getImm() == 0) {
551      FrameIndex = MI->getOperand(1).getIndex();
552      return MI->getOperand(0).getReg();
553    }
554    break;
555  case ARM::t2LDRi12:
556  case ARM::tRestore:
557    if (MI->getOperand(1).isFI() &&
558        MI->getOperand(2).isImm() &&
559        MI->getOperand(2).getImm() == 0) {
560      FrameIndex = MI->getOperand(1).getIndex();
561      return MI->getOperand(0).getReg();
562    }
563    break;
564  case ARM::VLDRD:
565  case ARM::VLDRS:
566    if (MI->getOperand(1).isFI() &&
567        MI->getOperand(2).isImm() &&
568        MI->getOperand(2).getImm() == 0) {
569      FrameIndex = MI->getOperand(1).getIndex();
570      return MI->getOperand(0).getReg();
571    }
572    break;
573  }
574
575  return 0;
576}
577
578unsigned
579ARMBaseInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
580                                     int &FrameIndex) const {
581  switch (MI->getOpcode()) {
582  default: break;
583  case ARM::STR:
584  case ARM::t2STRs: // FIXME: don't use t2STRs to access frame.
585    if (MI->getOperand(1).isFI() &&
586        MI->getOperand(2).isReg() &&
587        MI->getOperand(3).isImm() &&
588        MI->getOperand(2).getReg() == 0 &&
589        MI->getOperand(3).getImm() == 0) {
590      FrameIndex = MI->getOperand(1).getIndex();
591      return MI->getOperand(0).getReg();
592    }
593    break;
594  case ARM::t2STRi12:
595  case ARM::tSpill:
596    if (MI->getOperand(1).isFI() &&
597        MI->getOperand(2).isImm() &&
598        MI->getOperand(2).getImm() == 0) {
599      FrameIndex = MI->getOperand(1).getIndex();
600      return MI->getOperand(0).getReg();
601    }
602    break;
603  case ARM::VSTRD:
604  case ARM::VSTRS:
605    if (MI->getOperand(1).isFI() &&
606        MI->getOperand(2).isImm() &&
607        MI->getOperand(2).getImm() == 0) {
608      FrameIndex = MI->getOperand(1).getIndex();
609      return MI->getOperand(0).getReg();
610    }
611    break;
612  }
613
614  return 0;
615}
616
617bool
618ARMBaseInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
619                               MachineBasicBlock::iterator I,
620                               unsigned DestReg, unsigned SrcReg,
621                               const TargetRegisterClass *DestRC,
622                               const TargetRegisterClass *SrcRC) const {
623  DebugLoc DL = DebugLoc::getUnknownLoc();
624  if (I != MBB.end()) DL = I->getDebugLoc();
625
626  if (DestRC != SrcRC) {
627    if (DestRC->getSize() != SrcRC->getSize())
628      return false;
629
630    // Allow DPR / DPR_VFP2 / DPR_8 cross-class copies.
631    // Allow QPR / QPR_VFP2 / QPR_8 cross-class copies.
632    if (DestRC->getSize() != 8 && DestRC->getSize() != 16)
633      return false;
634  }
635
636  if (DestRC == ARM::GPRRegisterClass) {
637    AddDefaultCC(AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::MOVr),
638                                        DestReg).addReg(SrcReg)));
639  } else if (DestRC == ARM::SPRRegisterClass) {
640    AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VMOVS), DestReg)
641                   .addReg(SrcReg));
642  } else if (DestRC == ARM::DPRRegisterClass) {
643    AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VMOVD), DestReg)
644                   .addReg(SrcReg));
645  } else if (DestRC == ARM::DPR_VFP2RegisterClass ||
646             DestRC == ARM::DPR_8RegisterClass ||
647             SrcRC == ARM::DPR_VFP2RegisterClass ||
648             SrcRC == ARM::DPR_8RegisterClass) {
649    // Always use neon reg-reg move if source or dest is NEON-only regclass.
650    BuildMI(MBB, I, DL, get(ARM::VMOVDneon), DestReg).addReg(SrcReg);
651  } else if (DestRC == ARM::QPRRegisterClass ||
652             DestRC == ARM::QPR_VFP2RegisterClass ||
653             DestRC == ARM::QPR_8RegisterClass) {
654    BuildMI(MBB, I, DL, get(ARM::VMOVQ), DestReg).addReg(SrcReg);
655  } else {
656    return false;
657  }
658
659  return true;
660}
661
662void ARMBaseInstrInfo::
663storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
664                    unsigned SrcReg, bool isKill, int FI,
665                    const TargetRegisterClass *RC) const {
666  DebugLoc DL = DebugLoc::getUnknownLoc();
667  if (I != MBB.end()) DL = I->getDebugLoc();
668  MachineFunction &MF = *MBB.getParent();
669  MachineFrameInfo &MFI = *MF.getFrameInfo();
670  unsigned Align = MFI.getObjectAlignment(FI);
671
672  MachineMemOperand *MMO =
673    MF.getMachineMemOperand(PseudoSourceValue::getFixedStack(FI),
674                            MachineMemOperand::MOStore, 0,
675                            MFI.getObjectSize(FI),
676                            Align);
677
678  if (RC == ARM::GPRRegisterClass) {
679    AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::STR))
680                   .addReg(SrcReg, getKillRegState(isKill))
681                   .addFrameIndex(FI).addReg(0).addImm(0).addMemOperand(MMO));
682  } else if (RC == ARM::DPRRegisterClass ||
683             RC == ARM::DPR_VFP2RegisterClass ||
684             RC == ARM::DPR_8RegisterClass) {
685    AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTRD))
686                   .addReg(SrcReg, getKillRegState(isKill))
687                   .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
688  } else if (RC == ARM::SPRRegisterClass) {
689    AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTRS))
690                   .addReg(SrcReg, getKillRegState(isKill))
691                   .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
692  } else {
693    assert((RC == ARM::QPRRegisterClass ||
694            RC == ARM::QPR_VFP2RegisterClass) && "Unknown regclass!");
695    // FIXME: Neon instructions should support predicates
696    if (Align >= 16
697        && (getRegisterInfo().needsStackRealignment(MF))) {
698      BuildMI(MBB, I, DL, get(ARM::VST1q64))
699        .addFrameIndex(FI).addImm(0).addImm(0).addImm(128).addMemOperand(MMO)
700        .addReg(SrcReg, getKillRegState(isKill));
701    } else {
702      BuildMI(MBB, I, DL, get(ARM::VSTRQ)).
703        addReg(SrcReg, getKillRegState(isKill))
704        .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
705    }
706  }
707}
708
709void ARMBaseInstrInfo::
710loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
711                     unsigned DestReg, int FI,
712                     const TargetRegisterClass *RC) const {
713  DebugLoc DL = DebugLoc::getUnknownLoc();
714  if (I != MBB.end()) DL = I->getDebugLoc();
715  MachineFunction &MF = *MBB.getParent();
716  MachineFrameInfo &MFI = *MF.getFrameInfo();
717  unsigned Align = MFI.getObjectAlignment(FI);
718
719  MachineMemOperand *MMO =
720    MF.getMachineMemOperand(PseudoSourceValue::getFixedStack(FI),
721                            MachineMemOperand::MOLoad, 0,
722                            MFI.getObjectSize(FI),
723                            Align);
724
725  if (RC == ARM::GPRRegisterClass) {
726    AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::LDR), DestReg)
727                   .addFrameIndex(FI).addReg(0).addImm(0).addMemOperand(MMO));
728  } else if (RC == ARM::DPRRegisterClass ||
729             RC == ARM::DPR_VFP2RegisterClass ||
730             RC == ARM::DPR_8RegisterClass) {
731    AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRD), DestReg)
732                   .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
733  } else if (RC == ARM::SPRRegisterClass) {
734    AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRS), DestReg)
735                   .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
736  } else {
737    assert((RC == ARM::QPRRegisterClass ||
738            RC == ARM::QPR_VFP2RegisterClass ||
739            RC == ARM::QPR_8RegisterClass) && "Unknown regclass!");
740    // FIXME: Neon instructions should support predicates
741    if (Align >= 16
742        && (getRegisterInfo().needsStackRealignment(MF))) {
743      BuildMI(MBB, I, DL, get(ARM::VLD1q64))
744        .addReg(DestReg)
745        .addFrameIndex(FI).addImm(0).addImm(0).addImm(128).addMemOperand(MMO);
746    } else {
747      BuildMI(MBB, I, DL, get(ARM::VLDRQ), DestReg).addFrameIndex(FI).addImm(0).
748        addMemOperand(MMO);
749    }
750  }
751}
752
753MachineInstr *ARMBaseInstrInfo::
754foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI,
755                      const SmallVectorImpl<unsigned> &Ops, int FI) const {
756  if (Ops.size() != 1) return NULL;
757
758  unsigned OpNum = Ops[0];
759  unsigned Opc = MI->getOpcode();
760  MachineInstr *NewMI = NULL;
761  if (Opc == ARM::MOVr || Opc == ARM::t2MOVr) {
762    // If it is updating CPSR, then it cannot be folded.
763    if (MI->getOperand(4).getReg() == ARM::CPSR && !MI->getOperand(4).isDead())
764      return NULL;
765    unsigned Pred = MI->getOperand(2).getImm();
766    unsigned PredReg = MI->getOperand(3).getReg();
767    if (OpNum == 0) { // move -> store
768      unsigned SrcReg = MI->getOperand(1).getReg();
769      unsigned SrcSubReg = MI->getOperand(1).getSubReg();
770      bool isKill = MI->getOperand(1).isKill();
771      bool isUndef = MI->getOperand(1).isUndef();
772      if (Opc == ARM::MOVr)
773        NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::STR))
774          .addReg(SrcReg,
775                  getKillRegState(isKill) | getUndefRegState(isUndef),
776                  SrcSubReg)
777          .addFrameIndex(FI).addReg(0).addImm(0).addImm(Pred).addReg(PredReg);
778      else // ARM::t2MOVr
779        NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::t2STRi12))
780          .addReg(SrcReg,
781                  getKillRegState(isKill) | getUndefRegState(isUndef),
782                  SrcSubReg)
783          .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg);
784    } else {          // move -> load
785      unsigned DstReg = MI->getOperand(0).getReg();
786      unsigned DstSubReg = MI->getOperand(0).getSubReg();
787      bool isDead = MI->getOperand(0).isDead();
788      bool isUndef = MI->getOperand(0).isUndef();
789      if (Opc == ARM::MOVr)
790        NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::LDR))
791          .addReg(DstReg,
792                  RegState::Define |
793                  getDeadRegState(isDead) |
794                  getUndefRegState(isUndef), DstSubReg)
795          .addFrameIndex(FI).addReg(0).addImm(0).addImm(Pred).addReg(PredReg);
796      else // ARM::t2MOVr
797        NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::t2LDRi12))
798          .addReg(DstReg,
799                  RegState::Define |
800                  getDeadRegState(isDead) |
801                  getUndefRegState(isUndef), DstSubReg)
802          .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg);
803    }
804  } else if (Opc == ARM::tMOVgpr2gpr ||
805             Opc == ARM::tMOVtgpr2gpr ||
806             Opc == ARM::tMOVgpr2tgpr) {
807    if (OpNum == 0) { // move -> store
808      unsigned SrcReg = MI->getOperand(1).getReg();
809      unsigned SrcSubReg = MI->getOperand(1).getSubReg();
810      bool isKill = MI->getOperand(1).isKill();
811      bool isUndef = MI->getOperand(1).isUndef();
812      NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::t2STRi12))
813        .addReg(SrcReg,
814                getKillRegState(isKill) | getUndefRegState(isUndef),
815                SrcSubReg)
816        .addFrameIndex(FI).addImm(0).addImm(ARMCC::AL).addReg(0);
817    } else {          // move -> load
818      unsigned DstReg = MI->getOperand(0).getReg();
819      unsigned DstSubReg = MI->getOperand(0).getSubReg();
820      bool isDead = MI->getOperand(0).isDead();
821      bool isUndef = MI->getOperand(0).isUndef();
822      NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::t2LDRi12))
823        .addReg(DstReg,
824                RegState::Define |
825                getDeadRegState(isDead) |
826                getUndefRegState(isUndef),
827                DstSubReg)
828        .addFrameIndex(FI).addImm(0).addImm(ARMCC::AL).addReg(0);
829    }
830  } else if (Opc == ARM::VMOVS) {
831    unsigned Pred = MI->getOperand(2).getImm();
832    unsigned PredReg = MI->getOperand(3).getReg();
833    if (OpNum == 0) { // move -> store
834      unsigned SrcReg = MI->getOperand(1).getReg();
835      unsigned SrcSubReg = MI->getOperand(1).getSubReg();
836      bool isKill = MI->getOperand(1).isKill();
837      bool isUndef = MI->getOperand(1).isUndef();
838      NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::VSTRS))
839        .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef),
840                SrcSubReg)
841        .addFrameIndex(FI)
842        .addImm(0).addImm(Pred).addReg(PredReg);
843    } else {          // move -> load
844      unsigned DstReg = MI->getOperand(0).getReg();
845      unsigned DstSubReg = MI->getOperand(0).getSubReg();
846      bool isDead = MI->getOperand(0).isDead();
847      bool isUndef = MI->getOperand(0).isUndef();
848      NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::VLDRS))
849        .addReg(DstReg,
850                RegState::Define |
851                getDeadRegState(isDead) |
852                getUndefRegState(isUndef),
853                DstSubReg)
854        .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg);
855    }
856  }
857  else if (Opc == ARM::VMOVD) {
858    unsigned Pred = MI->getOperand(2).getImm();
859    unsigned PredReg = MI->getOperand(3).getReg();
860    if (OpNum == 0) { // move -> store
861      unsigned SrcReg = MI->getOperand(1).getReg();
862      unsigned SrcSubReg = MI->getOperand(1).getSubReg();
863      bool isKill = MI->getOperand(1).isKill();
864      bool isUndef = MI->getOperand(1).isUndef();
865      NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::VSTRD))
866        .addReg(SrcReg,
867                getKillRegState(isKill) | getUndefRegState(isUndef),
868                SrcSubReg)
869        .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg);
870    } else {          // move -> load
871      unsigned DstReg = MI->getOperand(0).getReg();
872      unsigned DstSubReg = MI->getOperand(0).getSubReg();
873      bool isDead = MI->getOperand(0).isDead();
874      bool isUndef = MI->getOperand(0).isUndef();
875      NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::VLDRD))
876        .addReg(DstReg,
877                RegState::Define |
878                getDeadRegState(isDead) |
879                getUndefRegState(isUndef),
880                DstSubReg)
881        .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg);
882    }
883  }
884
885  return NewMI;
886}
887
888MachineInstr*
889ARMBaseInstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
890                                        MachineInstr* MI,
891                                        const SmallVectorImpl<unsigned> &Ops,
892                                        MachineInstr* LoadMI) const {
893  // FIXME
894  return 0;
895}
896
897bool
898ARMBaseInstrInfo::canFoldMemoryOperand(const MachineInstr *MI,
899                                   const SmallVectorImpl<unsigned> &Ops) const {
900  if (Ops.size() != 1) return false;
901
902  unsigned Opc = MI->getOpcode();
903  if (Opc == ARM::MOVr || Opc == ARM::t2MOVr) {
904    // If it is updating CPSR, then it cannot be folded.
905    return MI->getOperand(4).getReg() != ARM::CPSR ||
906      MI->getOperand(4).isDead();
907  } else if (Opc == ARM::tMOVgpr2gpr ||
908             Opc == ARM::tMOVtgpr2gpr ||
909             Opc == ARM::tMOVgpr2tgpr) {
910    return true;
911  } else if (Opc == ARM::VMOVS || Opc == ARM::VMOVD) {
912    return true;
913  } else if (Opc == ARM::VMOVDneon || Opc == ARM::VMOVQ) {
914    return false; // FIXME
915  }
916
917  return false;
918}
919
920void ARMBaseInstrInfo::
921reMaterialize(MachineBasicBlock &MBB,
922              MachineBasicBlock::iterator I,
923              unsigned DestReg, unsigned SubIdx,
924              const MachineInstr *Orig,
925              const TargetRegisterInfo *TRI) const {
926  DebugLoc dl = Orig->getDebugLoc();
927
928  if (SubIdx && TargetRegisterInfo::isPhysicalRegister(DestReg)) {
929    DestReg = TRI->getSubReg(DestReg, SubIdx);
930    SubIdx = 0;
931  }
932
933  unsigned Opcode = Orig->getOpcode();
934  switch (Opcode) {
935  default: {
936    MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig);
937    MI->getOperand(0).setReg(DestReg);
938    MBB.insert(I, MI);
939    break;
940  }
941  case ARM::tLDRpci_pic:
942  case ARM::t2LDRpci_pic: {
943    MachineFunction &MF = *MBB.getParent();
944    ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
945    MachineConstantPool *MCP = MF.getConstantPool();
946    unsigned CPI = Orig->getOperand(1).getIndex();
947    const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPI];
948    assert(MCPE.isMachineConstantPoolEntry() &&
949           "Expecting a machine constantpool entry!");
950    ARMConstantPoolValue *ACPV =
951      static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal);
952    unsigned PCLabelId = AFI->createConstPoolEntryUId();
953    ARMConstantPoolValue *NewCPV = 0;
954    if (ACPV->isGlobalValue())
955      NewCPV = new ARMConstantPoolValue(ACPV->getGV(), PCLabelId,
956                                        ARMCP::CPValue, 4);
957    else if (ACPV->isExtSymbol())
958      NewCPV = new ARMConstantPoolValue(MF.getFunction()->getContext(),
959                                        ACPV->getSymbol(), PCLabelId, 4);
960    else if (ACPV->isBlockAddress())
961      NewCPV = new ARMConstantPoolValue(ACPV->getBlockAddress(), PCLabelId,
962                                        ARMCP::CPBlockAddress, 4);
963    else
964      llvm_unreachable("Unexpected ARM constantpool value type!!");
965    CPI = MCP->getConstantPoolIndex(NewCPV, MCPE.getAlignment());
966    MachineInstrBuilder MIB = BuildMI(MBB, I, Orig->getDebugLoc(), get(Opcode),
967                                      DestReg)
968      .addConstantPoolIndex(CPI).addImm(PCLabelId);
969    (*MIB).setMemRefs(Orig->memoperands_begin(), Orig->memoperands_end());
970    break;
971  }
972  }
973
974  MachineInstr *NewMI = prior(I);
975  NewMI->getOperand(0).setSubReg(SubIdx);
976}
977
978bool ARMBaseInstrInfo::isIdentical(const MachineInstr *MI0,
979                                  const MachineInstr *MI1,
980                                  const MachineRegisterInfo *MRI) const {
981  int Opcode = MI0->getOpcode();
982  if (Opcode == ARM::t2LDRpci_pic || Opcode == ARM::tLDRpci_pic) {
983    if (MI1->getOpcode() != Opcode)
984      return false;
985    if (MI0->getNumOperands() != MI1->getNumOperands())
986      return false;
987
988    const MachineOperand &MO0 = MI0->getOperand(1);
989    const MachineOperand &MO1 = MI1->getOperand(1);
990    if (MO0.getOffset() != MO1.getOffset())
991      return false;
992
993    const MachineFunction *MF = MI0->getParent()->getParent();
994    const MachineConstantPool *MCP = MF->getConstantPool();
995    int CPI0 = MO0.getIndex();
996    int CPI1 = MO1.getIndex();
997    const MachineConstantPoolEntry &MCPE0 = MCP->getConstants()[CPI0];
998    const MachineConstantPoolEntry &MCPE1 = MCP->getConstants()[CPI1];
999    ARMConstantPoolValue *ACPV0 =
1000      static_cast<ARMConstantPoolValue*>(MCPE0.Val.MachineCPVal);
1001    ARMConstantPoolValue *ACPV1 =
1002      static_cast<ARMConstantPoolValue*>(MCPE1.Val.MachineCPVal);
1003    return ACPV0->hasSameValue(ACPV1);
1004  }
1005
1006  return TargetInstrInfoImpl::isIdentical(MI0, MI1, MRI);
1007}
1008
1009/// getInstrPredicate - If instruction is predicated, returns its predicate
1010/// condition, otherwise returns AL. It also returns the condition code
1011/// register by reference.
1012ARMCC::CondCodes
1013llvm::getInstrPredicate(const MachineInstr *MI, unsigned &PredReg) {
1014  int PIdx = MI->findFirstPredOperandIdx();
1015  if (PIdx == -1) {
1016    PredReg = 0;
1017    return ARMCC::AL;
1018  }
1019
1020  PredReg = MI->getOperand(PIdx+1).getReg();
1021  return (ARMCC::CondCodes)MI->getOperand(PIdx).getImm();
1022}
1023
1024
1025int llvm::getMatchingCondBranchOpcode(int Opc) {
1026  if (Opc == ARM::B)
1027    return ARM::Bcc;
1028  else if (Opc == ARM::tB)
1029    return ARM::tBcc;
1030  else if (Opc == ARM::t2B)
1031      return ARM::t2Bcc;
1032
1033  llvm_unreachable("Unknown unconditional branch opcode!");
1034  return 0;
1035}
1036
1037
1038void llvm::emitARMRegPlusImmediate(MachineBasicBlock &MBB,
1039                               MachineBasicBlock::iterator &MBBI, DebugLoc dl,
1040                               unsigned DestReg, unsigned BaseReg, int NumBytes,
1041                               ARMCC::CondCodes Pred, unsigned PredReg,
1042                               const ARMBaseInstrInfo &TII) {
1043  bool isSub = NumBytes < 0;
1044  if (isSub) NumBytes = -NumBytes;
1045
1046  while (NumBytes) {
1047    unsigned RotAmt = ARM_AM::getSOImmValRotate(NumBytes);
1048    unsigned ThisVal = NumBytes & ARM_AM::rotr32(0xFF, RotAmt);
1049    assert(ThisVal && "Didn't extract field correctly");
1050
1051    // We will handle these bits from offset, clear them.
1052    NumBytes &= ~ThisVal;
1053
1054    assert(ARM_AM::getSOImmVal(ThisVal) != -1 && "Bit extraction didn't work?");
1055
1056    // Build the new ADD / SUB.
1057    unsigned Opc = isSub ? ARM::SUBri : ARM::ADDri;
1058    BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)
1059      .addReg(BaseReg, RegState::Kill).addImm(ThisVal)
1060      .addImm((unsigned)Pred).addReg(PredReg).addReg(0);
1061    BaseReg = DestReg;
1062  }
1063}
1064
1065bool llvm::rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
1066                                unsigned FrameReg, int &Offset,
1067                                const ARMBaseInstrInfo &TII) {
1068  unsigned Opcode = MI.getOpcode();
1069  const TargetInstrDesc &Desc = MI.getDesc();
1070  unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
1071  bool isSub = false;
1072
1073  // Memory operands in inline assembly always use AddrMode2.
1074  if (Opcode == ARM::INLINEASM)
1075    AddrMode = ARMII::AddrMode2;
1076
1077  if (Opcode == ARM::ADDri) {
1078    Offset += MI.getOperand(FrameRegIdx+1).getImm();
1079    if (Offset == 0) {
1080      // Turn it into a move.
1081      MI.setDesc(TII.get(ARM::MOVr));
1082      MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
1083      MI.RemoveOperand(FrameRegIdx+1);
1084      Offset = 0;
1085      return true;
1086    } else if (Offset < 0) {
1087      Offset = -Offset;
1088      isSub = true;
1089      MI.setDesc(TII.get(ARM::SUBri));
1090    }
1091
1092    // Common case: small offset, fits into instruction.
1093    if (ARM_AM::getSOImmVal(Offset) != -1) {
1094      // Replace the FrameIndex with sp / fp
1095      MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
1096      MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset);
1097      Offset = 0;
1098      return true;
1099    }
1100
1101    // Otherwise, pull as much of the immedidate into this ADDri/SUBri
1102    // as possible.
1103    unsigned RotAmt = ARM_AM::getSOImmValRotate(Offset);
1104    unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xFF, RotAmt);
1105
1106    // We will handle these bits from offset, clear them.
1107    Offset &= ~ThisImmVal;
1108
1109    // Get the properly encoded SOImmVal field.
1110    assert(ARM_AM::getSOImmVal(ThisImmVal) != -1 &&
1111           "Bit extraction didn't work?");
1112    MI.getOperand(FrameRegIdx+1).ChangeToImmediate(ThisImmVal);
1113 } else {
1114    unsigned ImmIdx = 0;
1115    int InstrOffs = 0;
1116    unsigned NumBits = 0;
1117    unsigned Scale = 1;
1118    switch (AddrMode) {
1119    case ARMII::AddrMode2: {
1120      ImmIdx = FrameRegIdx+2;
1121      InstrOffs = ARM_AM::getAM2Offset(MI.getOperand(ImmIdx).getImm());
1122      if (ARM_AM::getAM2Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
1123        InstrOffs *= -1;
1124      NumBits = 12;
1125      break;
1126    }
1127    case ARMII::AddrMode3: {
1128      ImmIdx = FrameRegIdx+2;
1129      InstrOffs = ARM_AM::getAM3Offset(MI.getOperand(ImmIdx).getImm());
1130      if (ARM_AM::getAM3Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
1131        InstrOffs *= -1;
1132      NumBits = 8;
1133      break;
1134    }
1135    case ARMII::AddrMode4:
1136      // Can't fold any offset even if it's zero.
1137      return false;
1138    case ARMII::AddrMode5: {
1139      ImmIdx = FrameRegIdx+1;
1140      InstrOffs = ARM_AM::getAM5Offset(MI.getOperand(ImmIdx).getImm());
1141      if (ARM_AM::getAM5Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
1142        InstrOffs *= -1;
1143      NumBits = 8;
1144      Scale = 4;
1145      break;
1146    }
1147    default:
1148      llvm_unreachable("Unsupported addressing mode!");
1149      break;
1150    }
1151
1152    Offset += InstrOffs * Scale;
1153    assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!");
1154    if (Offset < 0) {
1155      Offset = -Offset;
1156      isSub = true;
1157    }
1158
1159    // Attempt to fold address comp. if opcode has offset bits
1160    if (NumBits > 0) {
1161      // Common case: small offset, fits into instruction.
1162      MachineOperand &ImmOp = MI.getOperand(ImmIdx);
1163      int ImmedOffset = Offset / Scale;
1164      unsigned Mask = (1 << NumBits) - 1;
1165      if ((unsigned)Offset <= Mask * Scale) {
1166        // Replace the FrameIndex with sp
1167        MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
1168        if (isSub)
1169          ImmedOffset |= 1 << NumBits;
1170        ImmOp.ChangeToImmediate(ImmedOffset);
1171        Offset = 0;
1172        return true;
1173      }
1174
1175      // Otherwise, it didn't fit. Pull in what we can to simplify the immed.
1176      ImmedOffset = ImmedOffset & Mask;
1177      if (isSub)
1178        ImmedOffset |= 1 << NumBits;
1179      ImmOp.ChangeToImmediate(ImmedOffset);
1180      Offset &= ~(Mask*Scale);
1181    }
1182  }
1183
1184  Offset = (isSub) ? -Offset : Offset;
1185  return Offset == 0;
1186}
1187