ARMBaseInstrInfo.cpp revision dce4a407a24b04eebc6a376f8e62b41aaa7b071f
131d157ae1ac2cd9c787dc3c1d28e64c682803844Jia Liu//===-- ARMBaseInstrInfo.cpp - ARM Instruction Information ----------------===// 2334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// 3334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// The LLVM Compiler Infrastructure 4334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// 5334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// This file is distributed under the University of Illinois Open Source 6334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// License. See LICENSE.TXT for details. 7334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// 8334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin//===----------------------------------------------------------------------===// 9334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// 10334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// This file contains the Base ARM implementation of the TargetInstrInfo class. 11334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// 12334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin//===----------------------------------------------------------------------===// 13334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 14334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "ARM.h" 156eef361b73b457896b310d411251aedd5e72476aAmara Emerson#include "ARMBaseInstrInfo.h" 160e5233a9e5ee9385c6a940e3985194d77bee0bbbCraig Topper#include "ARMBaseRegisterInfo.h" 17d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng#include "ARMConstantPoolValue.h" 186eef361b73b457896b310d411251aedd5e72476aAmara Emerson#include "ARMFeatures.h" 1948575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng#include "ARMHazardRecognizer.h" 20334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "ARMMachineFunctionInfo.h" 21ee04a6d3a40c3017124e3fd89a0db473a2824498Evan Cheng#include "MCTargetDesc/ARMAddressingModes.h" 22d04a8d4b33ff316ca4cf961e06c9e312eff8e64fChandler Carruth#include "llvm/ADT/STLExtras.h" 23334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "llvm/CodeGen/LiveVariables.h" 24d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng#include "llvm/CodeGen/MachineConstantPool.h" 25334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "llvm/CodeGen/MachineFrameInfo.h" 26334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "llvm/CodeGen/MachineInstrBuilder.h" 27334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "llvm/CodeGen/MachineJumpTableInfo.h" 28249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov#include "llvm/CodeGen/MachineMemOperand.h" 292457f2c66184e978d4ed8fa9e2128effff26cb0bEvan Cheng#include "llvm/CodeGen/MachineRegisterInfo.h" 30ee04a6d3a40c3017124e3fd89a0db473a2824498Evan Cheng#include "llvm/CodeGen/SelectionDAGNodes.h" 310b8c9a80f20772c3793201ab5b251d3520b9cea3Chandler Carruth#include "llvm/IR/Constants.h" 320b8c9a80f20772c3793201ab5b251d3520b9cea3Chandler Carruth#include "llvm/IR/Function.h" 330b8c9a80f20772c3793201ab5b251d3520b9cea3Chandler Carruth#include "llvm/IR/GlobalValue.h" 34af76e592c7f9deff0e55c13dbb4a34f07f1c7f64Chris Lattner#include "llvm/MC/MCAsmInfo.h" 35f81b7f6069b27c0a515070dcb392f6828437412fJakub Staszak#include "llvm/Support/BranchProbability.h" 36334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "llvm/Support/CommandLine.h" 37f95215f551949d5e5adfbf4753aa833b9009b77aAnton Korobeynikov#include "llvm/Support/Debug.h" 38c25e7581b9b8088910da31702d4ca21c4734c6d7Torok Edwin#include "llvm/Support/ErrorHandling.h" 3922fee2dff4c43b551aefa44a96ca74fcade6bfacEvan Cheng 40dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hinesusing namespace llvm; 41dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines 42dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines#define DEBUG_TYPE "arm-instrinfo" 43dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines 44354362524a72b3fa43a6c09380b7ae3b2380cbbaJuergen Ributzka#define GET_INSTRINFO_CTOR_DTOR 4522fee2dff4c43b551aefa44a96ca74fcade6bfacEvan Cheng#include "ARMGenInstrInfo.inc" 4622fee2dff4c43b551aefa44a96ca74fcade6bfacEvan Cheng 47334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinstatic cl::opt<bool> 48334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinEnableARM3Addr("enable-arm-3-addr-conv", cl::Hidden, 49334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin cl::desc("Enable ARM 2-addr to 3-addr conv")); 50334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 5161545829832ba0375249c42c84843d0b62c8f55fJakob Stoklund Olesenstatic cl::opt<bool> 523805d85e38c29d9106c758b63851eb847201f315Jakob Stoklund OlesenWidenVMOVS("widen-vmovs", cl::Hidden, cl::init(true), 5361545829832ba0375249c42c84843d0b62c8f55fJakob Stoklund Olesen cl::desc("Widen ARM vmovs to vmovd when possible")); 5461545829832ba0375249c42c84843d0b62c8f55fJakob Stoklund Olesen 55eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilsonstatic cl::opt<unsigned> 56eb1641d54a7eda7717304bc4d55d059208d8ebedBob WilsonSwiftPartialUpdateClearance("swift-partial-update-clearance", 57eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson cl::Hidden, cl::init(12), 58eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson cl::desc("Clearance before partial register updates")); 59eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson 6048575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng/// ARM_MLxEntry - Record information about MLA / MLS instructions. 6148575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Chengstruct ARM_MLxEntry { 62cd2859eef83708c00330c94f6842499b48d5ed02Craig Topper uint16_t MLxOpc; // MLA / MLS opcode 63cd2859eef83708c00330c94f6842499b48d5ed02Craig Topper uint16_t MulOpc; // Expanded multiplication opcode 64cd2859eef83708c00330c94f6842499b48d5ed02Craig Topper uint16_t AddSubOpc; // Expanded add / sub opcode 6548575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng bool NegAcc; // True if the acc is negated before the add / sub. 6648575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng bool HasLane; // True if instruction has an extra "lane" operand. 6748575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng}; 6848575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng 6948575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Chengstatic const ARM_MLxEntry ARM_MLxTable[] = { 7048575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng // MLxOpc, MulOpc, AddSubOpc, NegAcc, HasLane 7148575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng // fp scalar ops 7248575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng { ARM::VMLAS, ARM::VMULS, ARM::VADDS, false, false }, 7348575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng { ARM::VMLSS, ARM::VMULS, ARM::VSUBS, false, false }, 7448575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng { ARM::VMLAD, ARM::VMULD, ARM::VADDD, false, false }, 7548575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng { ARM::VMLSD, ARM::VMULD, ARM::VSUBD, false, false }, 7648575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng { ARM::VNMLAS, ARM::VNMULS, ARM::VSUBS, true, false }, 7748575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng { ARM::VNMLSS, ARM::VMULS, ARM::VSUBS, true, false }, 7848575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng { ARM::VNMLAD, ARM::VNMULD, ARM::VSUBD, true, false }, 7948575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng { ARM::VNMLSD, ARM::VMULD, ARM::VSUBD, true, false }, 8048575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng 8148575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng // fp SIMD ops 8248575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng { ARM::VMLAfd, ARM::VMULfd, ARM::VADDfd, false, false }, 8348575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng { ARM::VMLSfd, ARM::VMULfd, ARM::VSUBfd, false, false }, 8448575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng { ARM::VMLAfq, ARM::VMULfq, ARM::VADDfq, false, false }, 8548575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng { ARM::VMLSfq, ARM::VMULfq, ARM::VSUBfq, false, false }, 8648575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng { ARM::VMLAslfd, ARM::VMULslfd, ARM::VADDfd, false, true }, 8748575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng { ARM::VMLSslfd, ARM::VMULslfd, ARM::VSUBfd, false, true }, 8848575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng { ARM::VMLAslfq, ARM::VMULslfq, ARM::VADDfq, false, true }, 8948575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng { ARM::VMLSslfq, ARM::VMULslfq, ARM::VSUBfq, false, true }, 9048575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng}; 9148575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng 92f95215f551949d5e5adfbf4753aa833b9009b77aAnton KorobeynikovARMBaseInstrInfo::ARMBaseInstrInfo(const ARMSubtarget& STI) 934db3cffe94a5285239cc0056f939c6b74a5ca0b6Evan Cheng : ARMGenInstrInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP), 94f95215f551949d5e5adfbf4753aa833b9009b77aAnton Korobeynikov Subtarget(STI) { 9548575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng for (unsigned i = 0, e = array_lengthof(ARM_MLxTable); i != e; ++i) { 9648575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng if (!MLxEntryMap.insert(std::make_pair(ARM_MLxTable[i].MLxOpc, i)).second) 9748575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng assert(false && "Duplicated entries?"); 9848575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng MLxHazardOpcodes.insert(ARM_MLxTable[i].AddSubOpc); 9948575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng MLxHazardOpcodes.insert(ARM_MLxTable[i].MulOpc); 10048575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng } 10148575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng} 10248575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng 1032da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick// Use a ScoreboardHazardRecognizer for prepass ARM scheduling. TargetInstrImpl 1042da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick// currently defaults to no prepass hazard recognizer. 10548575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan ChengScheduleHazardRecognizer *ARMBaseInstrInfo:: 1062da8bc8a5f7705ac131184cd247f48500da0d74eAndrew TrickCreateTargetHazardRecognizer(const TargetMachine *TM, 1072da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick const ScheduleDAG *DAG) const { 108c8bfd1d78ff9a307d1d4cb57cce4549b538e60f4Andrew Trick if (usePreRAHazardRecognizer()) { 1092da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick const InstrItineraryData *II = TM->getInstrItineraryData(); 1102da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick return new ScoreboardHazardRecognizer(II, DAG, "pre-RA-sched"); 1112da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick } 112a9fa4fd9736f7d1066223f32fa54efbe86c0fcebJakob Stoklund Olesen return TargetInstrInfo::CreateTargetHazardRecognizer(TM, DAG); 1132da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick} 1142da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick 1152da8bc8a5f7705ac131184cd247f48500da0d74eAndrew TrickScheduleHazardRecognizer *ARMBaseInstrInfo:: 1162da8bc8a5f7705ac131184cd247f48500da0d74eAndrew TrickCreateTargetPostRAHazardRecognizer(const InstrItineraryData *II, 1172da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick const ScheduleDAG *DAG) const { 11848575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng if (Subtarget.isThumb2() || Subtarget.hasVFP2()) 11957148c166ab232191098492633c924fad9c44ef3Bill Wendling return (ScheduleHazardRecognizer *)new ARMHazardRecognizer(II, DAG); 120a9fa4fd9736f7d1066223f32fa54efbe86c0fcebJakob Stoklund Olesen return TargetInstrInfo::CreateTargetPostRAHazardRecognizer(II, DAG); 121334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 122334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 123334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinMachineInstr * 124334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinARMBaseInstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI, 125334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineBasicBlock::iterator &MBBI, 126334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin LiveVariables *LV) const { 12778703ddafe3d037f75d8ca188e4829d238289ac3Evan Cheng // FIXME: Thumb2 support. 12878703ddafe3d037f75d8ca188e4829d238289ac3Evan Cheng 129334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (!EnableARM3Addr) 130dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines return nullptr; 131334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 132334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineInstr *MI = MBBI; 133334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineFunction &MF = *MI->getParent()->getParent(); 13499405df044f2c584242e711cc9023ec90356da82Bruno Cardoso Lopes uint64_t TSFlags = MI->getDesc().TSFlags; 135334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool isPre = false; 136334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin switch ((TSFlags & ARMII::IndexModeMask) >> ARMII::IndexModeShift) { 137dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines default: return nullptr; 138334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMII::IndexModePre: 139334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin isPre = true; 140334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin break; 141334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMII::IndexModePost: 142334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin break; 143334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 144334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 145334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Try splitting an indexed load/store to an un-indexed one plus an add/sub 146334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // operation. 147334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned MemOpc = getUnindexedOpcode(MI->getOpcode()); 148334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (MemOpc == 0) 149dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines return nullptr; 150334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 151dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines MachineInstr *UpdateMI = nullptr; 152dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines MachineInstr *MemMI = nullptr; 153334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned AddrMode = (TSFlags & ARMII::AddrModeMask); 154e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng const MCInstrDesc &MCID = MI->getDesc(); 155e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng unsigned NumOps = MCID.getNumOperands(); 1565a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng bool isLoad = !MI->mayStore(); 157334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const MachineOperand &WB = isLoad ? MI->getOperand(1) : MI->getOperand(0); 158334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const MachineOperand &Base = MI->getOperand(2); 159334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const MachineOperand &Offset = MI->getOperand(NumOps-3); 160334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned WBReg = WB.getReg(); 161334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned BaseReg = Base.getReg(); 162334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned OffReg = Offset.getReg(); 163334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned OffImm = MI->getOperand(NumOps-2).getImm(); 164334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin ARMCC::CondCodes Pred = (ARMCC::CondCodes)MI->getOperand(NumOps-1).getImm(); 165334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin switch (AddrMode) { 166bc2198133a1836598b54b943420748e75d5dea94Craig Topper default: llvm_unreachable("Unknown indexed op!"); 167334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMII::AddrMode2: { 168334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool isSub = ARM_AM::getAM2Op(OffImm) == ARM_AM::sub; 169334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned Amt = ARM_AM::getAM2Offset(OffImm); 170334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (OffReg == 0) { 171e7cbe4118b7ddf05032ff8772a98c51e1637bb5cEvan Cheng if (ARM_AM::getSOImmVal(Amt) == -1) 172334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Can't encode it in a so_imm operand. This transformation will 173334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // add more than 1 instruction. Abandon! 174dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines return nullptr; 175334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin UpdateMI = BuildMI(MF, MI->getDebugLoc(), 17678703ddafe3d037f75d8ca188e4829d238289ac3Evan Cheng get(isSub ? ARM::SUBri : ARM::ADDri), WBReg) 177e7cbe4118b7ddf05032ff8772a98c51e1637bb5cEvan Cheng .addReg(BaseReg).addImm(Amt) 178334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addImm(Pred).addReg(0).addReg(0); 179334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } else if (Amt != 0) { 180334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin ARM_AM::ShiftOpc ShOpc = ARM_AM::getAM2ShiftOpc(OffImm); 181334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned SOOpc = ARM_AM::getSORegOpc(ShOpc, Amt); 182334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin UpdateMI = BuildMI(MF, MI->getDebugLoc(), 18392a202213bb4c20301abf6ab64e46df3695e60bfOwen Anderson get(isSub ? ARM::SUBrsi : ARM::ADDrsi), WBReg) 184334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(BaseReg).addReg(OffReg).addReg(0).addImm(SOOpc) 185334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addImm(Pred).addReg(0).addReg(0); 186334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } else 187334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin UpdateMI = BuildMI(MF, MI->getDebugLoc(), 18878703ddafe3d037f75d8ca188e4829d238289ac3Evan Cheng get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg) 189334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(BaseReg).addReg(OffReg) 190334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addImm(Pred).addReg(0).addReg(0); 191334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin break; 192334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 193334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMII::AddrMode3 : { 194334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool isSub = ARM_AM::getAM3Op(OffImm) == ARM_AM::sub; 195334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned Amt = ARM_AM::getAM3Offset(OffImm); 196334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (OffReg == 0) 197334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Immediate is 8-bits. It's guaranteed to fit in a so_imm operand. 198334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin UpdateMI = BuildMI(MF, MI->getDebugLoc(), 19978703ddafe3d037f75d8ca188e4829d238289ac3Evan Cheng get(isSub ? ARM::SUBri : ARM::ADDri), WBReg) 200334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(BaseReg).addImm(Amt) 201334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addImm(Pred).addReg(0).addReg(0); 202334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin else 203334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin UpdateMI = BuildMI(MF, MI->getDebugLoc(), 20478703ddafe3d037f75d8ca188e4829d238289ac3Evan Cheng get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg) 205334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(BaseReg).addReg(OffReg) 206334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addImm(Pred).addReg(0).addReg(0); 207334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin break; 208334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 209334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 210334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 211334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin std::vector<MachineInstr*> NewMIs; 212334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (isPre) { 213334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (isLoad) 214334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MemMI = BuildMI(MF, MI->getDebugLoc(), 215334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin get(MemOpc), MI->getOperand(0).getReg()) 2163e5561247202bae994dd259a2d8dc4eff8f799f3Jim Grosbach .addReg(WBReg).addImm(0).addImm(Pred); 217334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin else 218334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MemMI = BuildMI(MF, MI->getDebugLoc(), 219334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin get(MemOpc)).addReg(MI->getOperand(1).getReg()) 220334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(WBReg).addReg(0).addImm(0).addImm(Pred); 221334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin NewMIs.push_back(MemMI); 222334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin NewMIs.push_back(UpdateMI); 223334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } else { 224334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (isLoad) 225334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MemMI = BuildMI(MF, MI->getDebugLoc(), 226334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin get(MemOpc), MI->getOperand(0).getReg()) 2273e5561247202bae994dd259a2d8dc4eff8f799f3Jim Grosbach .addReg(BaseReg).addImm(0).addImm(Pred); 228334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin else 229334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MemMI = BuildMI(MF, MI->getDebugLoc(), 230334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin get(MemOpc)).addReg(MI->getOperand(1).getReg()) 231334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred); 232334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (WB.isDead()) 233334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin UpdateMI->getOperand(0).setIsDead(); 234334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin NewMIs.push_back(UpdateMI); 235334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin NewMIs.push_back(MemMI); 236334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 237334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 238334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Transfer LiveVariables states, kill / dead info. 239334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (LV) { 240334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 241334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineOperand &MO = MI->getOperand(i); 242c9df025e33ac435adb3b3318d237c36ca7cec659Jakob Stoklund Olesen if (MO.isReg() && TargetRegisterInfo::isVirtualRegister(MO.getReg())) { 243334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned Reg = MO.getReg(); 244334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 245334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin LiveVariables::VarInfo &VI = LV->getVarInfo(Reg); 246334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (MO.isDef()) { 247334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineInstr *NewMI = (Reg == WBReg) ? UpdateMI : MemMI; 248334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (MO.isDead()) 249334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin LV->addVirtualRegisterDead(Reg, NewMI); 250334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 251334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (MO.isUse() && MO.isKill()) { 252334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin for (unsigned j = 0; j < 2; ++j) { 253334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Look at the two new MI's in reverse order. 254334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineInstr *NewMI = NewMIs[j]; 255334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (!NewMI->readsRegister(Reg)) 256334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin continue; 257334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin LV->addVirtualRegisterKilled(Reg, NewMI); 258334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (VI.removeKill(MI)) 259334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin VI.Kills.push_back(NewMI); 260334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin break; 261334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 262334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 263334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 264334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 265334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 266334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 267334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MFI->insert(MBBI, NewMIs[1]); 268334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MFI->insert(MBBI, NewMIs[0]); 269334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return NewMIs[0]; 270334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 271334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 272334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// Branch analysis. 273334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinbool 274334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinARMBaseInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB, 275334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineBasicBlock *&FBB, 276334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin SmallVectorImpl<MachineOperand> &Cond, 277334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool AllowModify) const { 278dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines TBB = nullptr; 279dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines FBB = nullptr; 2807b61a701932d850d2777fafda1fea5ec841d893bLang Hames 281334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineBasicBlock::iterator I = MBB.end(); 28293d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen if (I == MBB.begin()) 2837b61a701932d850d2777fafda1fea5ec841d893bLang Hames return false; // Empty blocks are easy. 28493d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen --I; 285334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 2867b61a701932d850d2777fafda1fea5ec841d893bLang Hames // Walk backwards from the end of the basic block until the branch is 2877b61a701932d850d2777fafda1fea5ec841d893bLang Hames // analyzed or we give up. 28836b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines while (isPredicated(I) || I->isTerminator() || I->isDebugValue()) { 2890553e1efcd3f8ccd8b45302e033924d9f85a5d2fEvan Cheng 2907b61a701932d850d2777fafda1fea5ec841d893bLang Hames // Flag to be raised on unanalyzeable instructions. This is useful in cases 2917b61a701932d850d2777fafda1fea5ec841d893bLang Hames // where we want to clean up on the end of the basic block before we bail 2927b61a701932d850d2777fafda1fea5ec841d893bLang Hames // out. 2937b61a701932d850d2777fafda1fea5ec841d893bLang Hames bool CantAnalyze = false; 2940553e1efcd3f8ccd8b45302e033924d9f85a5d2fEvan Cheng 2957b61a701932d850d2777fafda1fea5ec841d893bLang Hames // Skip over DEBUG values and predicated nonterminators. 2967b61a701932d850d2777fafda1fea5ec841d893bLang Hames while (I->isDebugValue() || !I->isTerminator()) { 2977b61a701932d850d2777fafda1fea5ec841d893bLang Hames if (I == MBB.begin()) 2987b61a701932d850d2777fafda1fea5ec841d893bLang Hames return false; 2997b61a701932d850d2777fafda1fea5ec841d893bLang Hames --I; 300334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 3017b61a701932d850d2777fafda1fea5ec841d893bLang Hames 3027b61a701932d850d2777fafda1fea5ec841d893bLang Hames if (isIndirectBranchOpcode(I->getOpcode()) || 3037b61a701932d850d2777fafda1fea5ec841d893bLang Hames isJumpTableBranchOpcode(I->getOpcode())) { 3047b61a701932d850d2777fafda1fea5ec841d893bLang Hames // Indirect branches and jump tables can't be analyzed, but we still want 3057b61a701932d850d2777fafda1fea5ec841d893bLang Hames // to clean up any instructions at the tail of the basic block. 3067b61a701932d850d2777fafda1fea5ec841d893bLang Hames CantAnalyze = true; 3077b61a701932d850d2777fafda1fea5ec841d893bLang Hames } else if (isUncondBranchOpcode(I->getOpcode())) { 3087b61a701932d850d2777fafda1fea5ec841d893bLang Hames TBB = I->getOperand(0).getMBB(); 3097b61a701932d850d2777fafda1fea5ec841d893bLang Hames } else if (isCondBranchOpcode(I->getOpcode())) { 3107b61a701932d850d2777fafda1fea5ec841d893bLang Hames // Bail out if we encounter multiple conditional branches. 3117b61a701932d850d2777fafda1fea5ec841d893bLang Hames if (!Cond.empty()) 3127b61a701932d850d2777fafda1fea5ec841d893bLang Hames return true; 3137b61a701932d850d2777fafda1fea5ec841d893bLang Hames 3147b61a701932d850d2777fafda1fea5ec841d893bLang Hames assert(!FBB && "FBB should have been null."); 3157b61a701932d850d2777fafda1fea5ec841d893bLang Hames FBB = TBB; 3167b61a701932d850d2777fafda1fea5ec841d893bLang Hames TBB = I->getOperand(0).getMBB(); 3177b61a701932d850d2777fafda1fea5ec841d893bLang Hames Cond.push_back(I->getOperand(1)); 3187b61a701932d850d2777fafda1fea5ec841d893bLang Hames Cond.push_back(I->getOperand(2)); 3197b61a701932d850d2777fafda1fea5ec841d893bLang Hames } else if (I->isReturn()) { 3207b61a701932d850d2777fafda1fea5ec841d893bLang Hames // Returns can't be analyzed, but we should run cleanup. 3217b61a701932d850d2777fafda1fea5ec841d893bLang Hames CantAnalyze = !isPredicated(I); 3227b61a701932d850d2777fafda1fea5ec841d893bLang Hames } else { 3237b61a701932d850d2777fafda1fea5ec841d893bLang Hames // We encountered other unrecognized terminator. Bail out immediately. 3247b61a701932d850d2777fafda1fea5ec841d893bLang Hames return true; 325334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 326334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 3277b61a701932d850d2777fafda1fea5ec841d893bLang Hames // Cleanup code - to be run for unpredicated unconditional branches and 3287b61a701932d850d2777fafda1fea5ec841d893bLang Hames // returns. 3297b61a701932d850d2777fafda1fea5ec841d893bLang Hames if (!isPredicated(I) && 3307b61a701932d850d2777fafda1fea5ec841d893bLang Hames (isUncondBranchOpcode(I->getOpcode()) || 3317b61a701932d850d2777fafda1fea5ec841d893bLang Hames isIndirectBranchOpcode(I->getOpcode()) || 3327b61a701932d850d2777fafda1fea5ec841d893bLang Hames isJumpTableBranchOpcode(I->getOpcode()) || 3337b61a701932d850d2777fafda1fea5ec841d893bLang Hames I->isReturn())) { 3347b61a701932d850d2777fafda1fea5ec841d893bLang Hames // Forget any previous condition branch information - it no longer applies. 3357b61a701932d850d2777fafda1fea5ec841d893bLang Hames Cond.clear(); 336dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines FBB = nullptr; 3377b61a701932d850d2777fafda1fea5ec841d893bLang Hames 3387b61a701932d850d2777fafda1fea5ec841d893bLang Hames // If we can modify the function, delete everything below this 3397b61a701932d850d2777fafda1fea5ec841d893bLang Hames // unconditional branch. 3407b61a701932d850d2777fafda1fea5ec841d893bLang Hames if (AllowModify) { 34136b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines MachineBasicBlock::iterator DI = std::next(I); 3427b61a701932d850d2777fafda1fea5ec841d893bLang Hames while (DI != MBB.end()) { 3437b61a701932d850d2777fafda1fea5ec841d893bLang Hames MachineInstr *InstToDelete = DI; 3447b61a701932d850d2777fafda1fea5ec841d893bLang Hames ++DI; 3457b61a701932d850d2777fafda1fea5ec841d893bLang Hames InstToDelete->eraseFromParent(); 3467b61a701932d850d2777fafda1fea5ec841d893bLang Hames } 347108c8724663354050dc09bb1262c3e4511adf82fEvan Cheng } 348108c8724663354050dc09bb1262c3e4511adf82fEvan Cheng } 349334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 3507b61a701932d850d2777fafda1fea5ec841d893bLang Hames if (CantAnalyze) 3517b61a701932d850d2777fafda1fea5ec841d893bLang Hames return true; 352334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 3537b61a701932d850d2777fafda1fea5ec841d893bLang Hames if (I == MBB.begin()) 3547b61a701932d850d2777fafda1fea5ec841d893bLang Hames return false; 355334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 3567b61a701932d850d2777fafda1fea5ec841d893bLang Hames --I; 357334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 358334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 3597b61a701932d850d2777fafda1fea5ec841d893bLang Hames // We made it past the terminators without bailing out - we must have 3607b61a701932d850d2777fafda1fea5ec841d893bLang Hames // analyzed this branch successfully. 3617b61a701932d850d2777fafda1fea5ec841d893bLang Hames return false; 362334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 363334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 364334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 365334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinunsigned ARMBaseInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const { 366334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineBasicBlock::iterator I = MBB.end(); 367334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (I == MBB.begin()) return 0; 368334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin --I; 36993d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen while (I->isDebugValue()) { 37093d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen if (I == MBB.begin()) 37193d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen return 0; 37293d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen --I; 37393d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen } 3745ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng if (!isUncondBranchOpcode(I->getOpcode()) && 3755ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng !isCondBranchOpcode(I->getOpcode())) 376334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 0; 377334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 378334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Remove the branch. 379334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin I->eraseFromParent(); 380334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 381334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin I = MBB.end(); 382334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 383334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (I == MBB.begin()) return 1; 384334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin --I; 3855ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng if (!isCondBranchOpcode(I->getOpcode())) 386334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 1; 387334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 388334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Remove the branch. 389334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin I->eraseFromParent(); 390334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 2; 391334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 392334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 393334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinunsigned 394334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinARMBaseInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 3953bf912593301152b65accb9d9c37a95172f1df5aStuart Hastings MachineBasicBlock *FBB, 3963bf912593301152b65accb9d9c37a95172f1df5aStuart Hastings const SmallVectorImpl<MachineOperand> &Cond, 3973bf912593301152b65accb9d9c37a95172f1df5aStuart Hastings DebugLoc DL) const { 3986495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ARMFunctionInfo *AFI = MBB.getParent()->getInfo<ARMFunctionInfo>(); 3996495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng int BOpc = !AFI->isThumbFunction() 4006495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ? ARM::B : (AFI->isThumb2Function() ? ARM::t2B : ARM::tB); 4016495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng int BccOpc = !AFI->isThumbFunction() 4026495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ? ARM::Bcc : (AFI->isThumb2Function() ? ARM::t2Bcc : ARM::tBcc); 40351f6a7abf27fc92c3d8904c2334feab8b498e8e9Owen Anderson bool isThumb = AFI->isThumbFunction() || AFI->isThumb2Function(); 404e23dc9c0ef50b0a1934c04c1786f3a0478d62f41Andrew Trick 405334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Shouldn't be a fall through. 406334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin assert(TBB && "InsertBranch must not be told to insert a fallthrough"); 407334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin assert((Cond.size() == 2 || Cond.size() == 0) && 408334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin "ARM branch conditions have two components!"); 409334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 410dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines if (!FBB) { 411112fb73502d54dd7dd61ae2de24c92d4df181294Owen Anderson if (Cond.empty()) { // Unconditional branch? 41251f6a7abf27fc92c3d8904c2334feab8b498e8e9Owen Anderson if (isThumb) 41351f6a7abf27fc92c3d8904c2334feab8b498e8e9Owen Anderson BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB).addImm(ARMCC::AL).addReg(0); 41451f6a7abf27fc92c3d8904c2334feab8b498e8e9Owen Anderson else 41551f6a7abf27fc92c3d8904c2334feab8b498e8e9Owen Anderson BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB); 416112fb73502d54dd7dd61ae2de24c92d4df181294Owen Anderson } else 4173bf912593301152b65accb9d9c37a95172f1df5aStuart Hastings BuildMI(&MBB, DL, get(BccOpc)).addMBB(TBB) 418334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()); 419334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 1; 420334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 421334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 422334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Two-way conditional branch. 4233bf912593301152b65accb9d9c37a95172f1df5aStuart Hastings BuildMI(&MBB, DL, get(BccOpc)).addMBB(TBB) 424334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()); 42551f6a7abf27fc92c3d8904c2334feab8b498e8e9Owen Anderson if (isThumb) 42651f6a7abf27fc92c3d8904c2334feab8b498e8e9Owen Anderson BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB).addImm(ARMCC::AL).addReg(0); 42751f6a7abf27fc92c3d8904c2334feab8b498e8e9Owen Anderson else 42851f6a7abf27fc92c3d8904c2334feab8b498e8e9Owen Anderson BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB); 429334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 2; 430334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 431334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 432334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinbool ARMBaseInstrInfo:: 433334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const { 434334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin ARMCC::CondCodes CC = (ARMCC::CondCodes)(int)Cond[0].getImm(); 435334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin Cond[0].setImm(ARMCC::getOppositeCondition(CC)); 436334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 437334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 438334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 439ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Chengbool ARMBaseInstrInfo::isPredicated(const MachineInstr *MI) const { 440ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng if (MI->isBundle()) { 441ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng MachineBasicBlock::const_instr_iterator I = MI; 442ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end(); 443ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng while (++I != E && I->isInsideBundle()) { 444ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng int PIdx = I->findFirstPredOperandIdx(); 445ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng if (PIdx != -1 && I->getOperand(PIdx).getImm() != ARMCC::AL) 446ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng return true; 447ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng } 448ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng return false; 449ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng } 450ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng 451ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng int PIdx = MI->findFirstPredOperandIdx(); 452ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng return PIdx != -1 && MI->getOperand(PIdx).getImm() != ARMCC::AL; 453ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng} 454ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng 455334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinbool ARMBaseInstrInfo:: 456334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinPredicateInstruction(MachineInstr *MI, 457334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const SmallVectorImpl<MachineOperand> &Pred) const { 458334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned Opc = MI->getOpcode(); 4595ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng if (isUncondBranchOpcode(Opc)) { 4605ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng MI->setDesc(get(getMatchingCondBranchOpcode(Opc))); 461b9efafe54d61e85ca5209c4043aa814f89785195Jakob Stoklund Olesen MachineInstrBuilder(*MI->getParent()->getParent(), MI) 462b9efafe54d61e85ca5209c4043aa814f89785195Jakob Stoklund Olesen .addImm(Pred[0].getImm()) 463b9efafe54d61e85ca5209c4043aa814f89785195Jakob Stoklund Olesen .addReg(Pred[1].getReg()); 464334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; 465334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 466334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 467334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin int PIdx = MI->findFirstPredOperandIdx(); 468334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (PIdx != -1) { 469334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineOperand &PMO = MI->getOperand(PIdx); 470334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin PMO.setImm(Pred[0].getImm()); 471334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI->getOperand(PIdx+1).setReg(Pred[1].getReg()); 472334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; 473334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 474334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 475334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 476334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 477334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinbool ARMBaseInstrInfo:: 478334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinSubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1, 479334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const SmallVectorImpl<MachineOperand> &Pred2) const { 480334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (Pred1.size() > 2 || Pred2.size() > 2) 481334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 482334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 483334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin ARMCC::CondCodes CC1 = (ARMCC::CondCodes)Pred1[0].getImm(); 484334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin ARMCC::CondCodes CC2 = (ARMCC::CondCodes)Pred2[0].getImm(); 485334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (CC1 == CC2) 486334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; 487334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 488334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin switch (CC1) { 489334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin default: 490334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 491334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMCC::AL: 492334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; 493334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMCC::HS: 494334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return CC2 == ARMCC::HI; 495334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMCC::LS: 496334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return CC2 == ARMCC::LO || CC2 == ARMCC::EQ; 497334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMCC::GE: 498334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return CC2 == ARMCC::GT; 499334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMCC::LE: 500334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return CC2 == ARMCC::LT; 501334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 502334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 503334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 504334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinbool ARMBaseInstrInfo::DefinesPredicate(MachineInstr *MI, 505334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin std::vector<MachineOperand> &Pred) const { 506334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool Found = false; 507334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 508334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const MachineOperand &MO = MI->getOperand(i); 5092420b558de5d291d8503c1339004e5b5bf99a48aJakob Stoklund Olesen if ((MO.isRegMask() && MO.clobbersPhysReg(ARM::CPSR)) || 5102420b558de5d291d8503c1339004e5b5bf99a48aJakob Stoklund Olesen (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR)) { 511334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin Pred.push_back(MO); 512334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin Found = true; 513334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 514334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 515334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 516334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return Found; 517334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 518334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 519ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng/// isPredicable - Return true if the specified instruction can be predicated. 520ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng/// By default, this returns true for every instruction with a 521ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng/// PredicateOperand. 522ac0869dc8a7986855c5557cc67d4709600158ef5Evan Chengbool ARMBaseInstrInfo::isPredicable(MachineInstr *MI) const { 5235a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng if (!MI->isPredicable()) 524ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng return false; 525ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng 526b57d99694b87326a2eea26d76becf67bf5784b49Joey Gouly ARMFunctionInfo *AFI = 527b57d99694b87326a2eea26d76becf67bf5784b49Joey Gouly MI->getParent()->getParent()->getInfo<ARMFunctionInfo>(); 528b57d99694b87326a2eea26d76becf67bf5784b49Joey Gouly 529b57d99694b87326a2eea26d76becf67bf5784b49Joey Gouly if (AFI->isThumb2Function()) { 530929bdb23794b615dc6b0cc59db21f0450c3ce33bWeiming Zhao if (getSubtarget().restrictIT()) 531b57d99694b87326a2eea26d76becf67bf5784b49Joey Gouly return isV8EligibleForIT(MI); 532b57d99694b87326a2eea26d76becf67bf5784b49Joey Gouly } else { // non-Thumb 533b57d99694b87326a2eea26d76becf67bf5784b49Joey Gouly if ((MI->getDesc().TSFlags & ARMII::DomainMask) == ARMII::DomainNEON) 534b57d99694b87326a2eea26d76becf67bf5784b49Joey Gouly return false; 535ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng } 536b57d99694b87326a2eea26d76becf67bf5784b49Joey Gouly 537ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng return true; 538ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng} 539334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 540dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hinesnamespace llvm { 541dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hinestemplate <> bool IsCPSRDead<MachineInstr>(MachineInstr *MI) { 54236b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 54336b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines const MachineOperand &MO = MI->getOperand(i); 54436b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines if (!MO.isReg() || MO.isUndef() || MO.isUse()) 54536b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines continue; 54636b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines if (MO.getReg() != ARM::CPSR) 54736b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines continue; 54836b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines if (!MO.isDead()) 54936b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines return false; 55036b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines } 55136b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines // all definitions of CPSR are dead 55236b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines return true; 55336b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines} 554dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines} 55536b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines 55656856b1f46ec1f073ceef4e826c544b8b1691608Chris Lattner/// FIXME: Works around a gcc miscompilation with -fstrict-aliasing. 55719e57025d458d3cb50804fd821fd89b868a819bdChandler CarruthLLVM_ATTRIBUTE_NOINLINE 558334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinstatic unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT, 55956856b1f46ec1f073ceef4e826c544b8b1691608Chris Lattner unsigned JTI); 560334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinstatic unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT, 561334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned JTI) { 56256856b1f46ec1f073ceef4e826c544b8b1691608Chris Lattner assert(JTI < JT.size()); 563334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return JT[JTI].MBBs.size(); 564334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 565334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 566334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin/// GetInstSize - Return the size of the specified MachineInstr. 567334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin/// 568334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinunsigned ARMBaseInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const { 569334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const MachineBasicBlock &MBB = *MI->getParent(); 570334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const MachineFunction *MF = MBB.getParent(); 57133adcfb4d217f5f23d9bde8ba02b8e48f9605fc5Chris Lattner const MCAsmInfo *MAI = MF->getTarget().getMCAsmInfo(); 572334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 573e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng const MCInstrDesc &MCID = MI->getDesc(); 57416884415db751c75f2133bd04921393c792b1158Owen Anderson if (MCID.getSize()) 57516884415db751c75f2133bd04921393c792b1158Owen Anderson return MCID.getSize(); 576334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 5774d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie // If this machine instr is an inline asm, measure it. 5784d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie if (MI->getOpcode() == ARM::INLINEASM) 5794d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie return getInlineAsmLength(MI->getOperand(0).getSymbolName(), *MAI); 5804d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie unsigned Opc = MI->getOpcode(); 5814d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie switch (Opc) { 58236b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines default: 58336b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines // pseudo-instruction sizes are zero. 5844d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie return 0; 5854d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie case TargetOpcode::BUNDLE: 5864d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie return getInstBundleLength(MI); 5874d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie case ARM::MOVi16_ga_pcrel: 5884d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie case ARM::MOVTi16_ga_pcrel: 5894d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie case ARM::t2MOVi16_ga_pcrel: 5904d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie case ARM::t2MOVTi16_ga_pcrel: 5914d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie return 4; 5924d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie case ARM::MOVi32imm: 5934d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie case ARM::t2MOVi32imm: 5944d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie return 8; 5954d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie case ARM::CONSTPOOL_ENTRY: 5964d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie // If this machine instr is a constant pool entry, its size is recorded as 5974d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie // operand #2. 5984d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie return MI->getOperand(2).getImm(); 5994d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie case ARM::Int_eh_sjlj_longjmp: 6004d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie return 16; 6014d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie case ARM::tInt_eh_sjlj_longjmp: 6024d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie return 10; 6034d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie case ARM::Int_eh_sjlj_setjmp: 6044d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie case ARM::Int_eh_sjlj_setjmp_nofp: 6054d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie return 20; 6064d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie case ARM::tInt_eh_sjlj_setjmp: 6074d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie case ARM::t2Int_eh_sjlj_setjmp: 6084d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie case ARM::t2Int_eh_sjlj_setjmp_nofp: 6094d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie return 12; 6104d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie case ARM::BR_JTr: 6114d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie case ARM::BR_JTm: 6124d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie case ARM::BR_JTadd: 6134d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie case ARM::tBR_JTr: 6144d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie case ARM::t2BR_JT: 6154d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie case ARM::t2TBB_JT: 6164d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie case ARM::t2TBH_JT: { 6174d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie // These are jumptable branches, i.e. a branch followed by an inlined 6184d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie // jumptable. The size is 4 + 4 * number of entries. For TBB, each 6194d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie // entry is one byte; TBH two byte each. 6204d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie unsigned EntrySize = (Opc == ARM::t2TBB_JT) 6214d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie ? 1 : ((Opc == ARM::t2TBH_JT) ? 2 : 4); 6224d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie unsigned NumOps = MCID.getNumOperands(); 6234d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie MachineOperand JTOP = 6244d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie MI->getOperand(NumOps - (MI->isPredicable() ? 3 : 2)); 6254d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie unsigned JTI = JTOP.getIndex(); 6264d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo(); 627dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines assert(MJTI != nullptr); 6284d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables(); 6294d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie assert(JTI < JT.size()); 6304d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie // Thumb instructions are 2 byte aligned, but JT entries are 4 byte 6314d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie // 4 aligned. The assembler / linker may add 2 byte padding just before 6324d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie // the JT entries. The size does not include this padding; the 6334d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie // constant islands pass does separate bookkeeping for it. 6344d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie // FIXME: If we know the size of the function is less than (1 << 16) *2 6354d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie // bytes, we can use 16-bit entries instead. Then there won't be an 6364d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie // alignment issue. 6374d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie unsigned InstSize = (Opc == ARM::tBR_JTr || Opc == ARM::t2BR_JT) ? 2 : 4; 6384d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie unsigned NumEntries = getNumJTEntries(JT, JTI); 6394d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie if (Opc == ARM::t2TBB_JT && (NumEntries & 1)) 6404d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie // Make sure the instruction that follows TBB is 2-byte aligned. 6414d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie // FIXME: Constant island pass should insert an "ALIGN" instruction 6424d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie // instead. 6434d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie ++NumEntries; 6444d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie return NumEntries * EntrySize + InstSize; 6454d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie } 6464d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie } 647334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 648334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 649ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Chengunsigned ARMBaseInstrInfo::getInstBundleLength(const MachineInstr *MI) const { 650ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng unsigned Size = 0; 651ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng MachineBasicBlock::const_instr_iterator I = MI; 652ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end(); 653ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng while (++I != E && I->isInsideBundle()) { 654ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng assert(!I->isBundle() && "No nested bundle!"); 655ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng Size += GetInstSizeInBytes(&*I); 656ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng } 657ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng return Size; 658ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng} 659ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng 660ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesenvoid ARMBaseInstrInfo::copyPhysReg(MachineBasicBlock &MBB, 661ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen MachineBasicBlock::iterator I, DebugLoc DL, 662ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen unsigned DestReg, unsigned SrcReg, 663ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen bool KillSrc) const { 664ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen bool GPRDest = ARM::GPRRegClass.contains(DestReg); 6656c28682963e96699e7e0ab15282319c152bd6373Jim Grosbach bool GPRSrc = ARM::GPRRegClass.contains(SrcReg); 666ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen 667ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen if (GPRDest && GPRSrc) { 668ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen AddDefaultCC(AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::MOVr), DestReg) 6696c28682963e96699e7e0ab15282319c152bd6373Jim Grosbach .addReg(SrcReg, getKillRegState(KillSrc)))); 670ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen return; 6717bfdca0206f51132b26094c6f83a5ac97ee0f943David Goodwin } 672334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 673ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen bool SPRDest = ARM::SPRRegClass.contains(DestReg); 6746c28682963e96699e7e0ab15282319c152bd6373Jim Grosbach bool SPRSrc = ARM::SPRRegClass.contains(SrcReg); 675ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen 676e5038e191db82d4d92fdeec1b5bce5cae21f6d8fChad Rosier unsigned Opc = 0; 677142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen if (SPRDest && SPRSrc) 678ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen Opc = ARM::VMOVS; 679142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen else if (GPRDest && SPRSrc) 680ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen Opc = ARM::VMOVRS; 681ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen else if (SPRDest && GPRSrc) 682ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen Opc = ARM::VMOVSR; 683ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen else if (ARM::DPRRegClass.contains(DestReg, SrcReg)) 684ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen Opc = ARM::VMOVD; 685ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen else if (ARM::QPRRegClass.contains(DestReg, SrcReg)) 68643967a97cf9a296623e1cf5ed643e2f40b7e5766Owen Anderson Opc = ARM::VORRq; 687e5038e191db82d4d92fdeec1b5bce5cae21f6d8fChad Rosier 688e5038e191db82d4d92fdeec1b5bce5cae21f6d8fChad Rosier if (Opc) { 689e5038e191db82d4d92fdeec1b5bce5cae21f6d8fChad Rosier MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc), DestReg); 69043967a97cf9a296623e1cf5ed643e2f40b7e5766Owen Anderson MIB.addReg(SrcReg, getKillRegState(KillSrc)); 691e5038e191db82d4d92fdeec1b5bce5cae21f6d8fChad Rosier if (Opc == ARM::VORRq) 692e5038e191db82d4d92fdeec1b5bce5cae21f6d8fChad Rosier MIB.addReg(SrcReg, getKillRegState(KillSrc)); 693fea95c6bade86fcfa5bd07efdda9bd902f53be8cChad Rosier AddDefaultPred(MIB); 694e5038e191db82d4d92fdeec1b5bce5cae21f6d8fChad Rosier return; 695e5038e191db82d4d92fdeec1b5bce5cae21f6d8fChad Rosier } 696e5038e191db82d4d92fdeec1b5bce5cae21f6d8fChad Rosier 69785bdf2e76a0351468f231f48069c64bc6938f140Jakob Stoklund Olesen // Handle register classes that require multiple instructions. 69885bdf2e76a0351468f231f48069c64bc6938f140Jakob Stoklund Olesen unsigned BeginIdx = 0; 69985bdf2e76a0351468f231f48069c64bc6938f140Jakob Stoklund Olesen unsigned SubRegs = 0; 7007611a88b58e0a6960cdb5c72dc18a6c93e44cdc2Andrew Trick int Spacing = 1; 70185bdf2e76a0351468f231f48069c64bc6938f140Jakob Stoklund Olesen 70285bdf2e76a0351468f231f48069c64bc6938f140Jakob Stoklund Olesen // Use VORRq when possible. 7036c28682963e96699e7e0ab15282319c152bd6373Jim Grosbach if (ARM::QQPRRegClass.contains(DestReg, SrcReg)) { 7046c28682963e96699e7e0ab15282319c152bd6373Jim Grosbach Opc = ARM::VORRq; 7056c28682963e96699e7e0ab15282319c152bd6373Jim Grosbach BeginIdx = ARM::qsub_0; 7066c28682963e96699e7e0ab15282319c152bd6373Jim Grosbach SubRegs = 2; 7076c28682963e96699e7e0ab15282319c152bd6373Jim Grosbach } else if (ARM::QQQQPRRegClass.contains(DestReg, SrcReg)) { 7086c28682963e96699e7e0ab15282319c152bd6373Jim Grosbach Opc = ARM::VORRq; 7096c28682963e96699e7e0ab15282319c152bd6373Jim Grosbach BeginIdx = ARM::qsub_0; 7106c28682963e96699e7e0ab15282319c152bd6373Jim Grosbach SubRegs = 4; 71185bdf2e76a0351468f231f48069c64bc6938f140Jakob Stoklund Olesen // Fall back to VMOVD. 7126c28682963e96699e7e0ab15282319c152bd6373Jim Grosbach } else if (ARM::DPairRegClass.contains(DestReg, SrcReg)) { 7136c28682963e96699e7e0ab15282319c152bd6373Jim Grosbach Opc = ARM::VMOVD; 7146c28682963e96699e7e0ab15282319c152bd6373Jim Grosbach BeginIdx = ARM::dsub_0; 7156c28682963e96699e7e0ab15282319c152bd6373Jim Grosbach SubRegs = 2; 7166c28682963e96699e7e0ab15282319c152bd6373Jim Grosbach } else if (ARM::DTripleRegClass.contains(DestReg, SrcReg)) { 7176c28682963e96699e7e0ab15282319c152bd6373Jim Grosbach Opc = ARM::VMOVD; 7186c28682963e96699e7e0ab15282319c152bd6373Jim Grosbach BeginIdx = ARM::dsub_0; 7196c28682963e96699e7e0ab15282319c152bd6373Jim Grosbach SubRegs = 3; 7206c28682963e96699e7e0ab15282319c152bd6373Jim Grosbach } else if (ARM::DQuadRegClass.contains(DestReg, SrcReg)) { 7216c28682963e96699e7e0ab15282319c152bd6373Jim Grosbach Opc = ARM::VMOVD; 7226c28682963e96699e7e0ab15282319c152bd6373Jim Grosbach BeginIdx = ARM::dsub_0; 7236c28682963e96699e7e0ab15282319c152bd6373Jim Grosbach SubRegs = 4; 7246c28682963e96699e7e0ab15282319c152bd6373Jim Grosbach } else if (ARM::GPRPairRegClass.contains(DestReg, SrcReg)) { 7255b46ad4faf3216b4faaf30fa3a32f0af06f1ae36Jim Grosbach Opc = Subtarget.isThumb2() ? ARM::tMOVr : ARM::MOVr; 7266c28682963e96699e7e0ab15282319c152bd6373Jim Grosbach BeginIdx = ARM::gsub_0; 7276c28682963e96699e7e0ab15282319c152bd6373Jim Grosbach SubRegs = 2; 7286c28682963e96699e7e0ab15282319c152bd6373Jim Grosbach } else if (ARM::DPairSpcRegClass.contains(DestReg, SrcReg)) { 7296c28682963e96699e7e0ab15282319c152bd6373Jim Grosbach Opc = ARM::VMOVD; 7306c28682963e96699e7e0ab15282319c152bd6373Jim Grosbach BeginIdx = ARM::dsub_0; 7316c28682963e96699e7e0ab15282319c152bd6373Jim Grosbach SubRegs = 2; 7326c28682963e96699e7e0ab15282319c152bd6373Jim Grosbach Spacing = 2; 7336c28682963e96699e7e0ab15282319c152bd6373Jim Grosbach } else if (ARM::DTripleSpcRegClass.contains(DestReg, SrcReg)) { 7346c28682963e96699e7e0ab15282319c152bd6373Jim Grosbach Opc = ARM::VMOVD; 7356c28682963e96699e7e0ab15282319c152bd6373Jim Grosbach BeginIdx = ARM::dsub_0; 7366c28682963e96699e7e0ab15282319c152bd6373Jim Grosbach SubRegs = 3; 7376c28682963e96699e7e0ab15282319c152bd6373Jim Grosbach Spacing = 2; 7386c28682963e96699e7e0ab15282319c152bd6373Jim Grosbach } else if (ARM::DQuadSpcRegClass.contains(DestReg, SrcReg)) { 7396c28682963e96699e7e0ab15282319c152bd6373Jim Grosbach Opc = ARM::VMOVD; 7406c28682963e96699e7e0ab15282319c152bd6373Jim Grosbach BeginIdx = ARM::dsub_0; 7416c28682963e96699e7e0ab15282319c152bd6373Jim Grosbach SubRegs = 4; 7426c28682963e96699e7e0ab15282319c152bd6373Jim Grosbach Spacing = 2; 7436c28682963e96699e7e0ab15282319c152bd6373Jim Grosbach } 74485bdf2e76a0351468f231f48069c64bc6938f140Jakob Stoklund Olesen 7457611a88b58e0a6960cdb5c72dc18a6c93e44cdc2Andrew Trick assert(Opc && "Impossible reg-to-reg copy"); 746d79dedd458c1de07fbc568ea8c3b4194e94df48eAndrew Trick 747d79dedd458c1de07fbc568ea8c3b4194e94df48eAndrew Trick const TargetRegisterInfo *TRI = &getRegisterInfo(); 748d79dedd458c1de07fbc568ea8c3b4194e94df48eAndrew Trick MachineInstrBuilder Mov; 749f26e43df26bb7b0c7bf4853477e36611e2c90deaAndrew Trick 750f26e43df26bb7b0c7bf4853477e36611e2c90deaAndrew Trick // Copy register tuples backward when the first Dest reg overlaps with SrcReg. 751f26e43df26bb7b0c7bf4853477e36611e2c90deaAndrew Trick if (TRI->regsOverlap(SrcReg, TRI->getSubReg(DestReg, BeginIdx))) { 7526c28682963e96699e7e0ab15282319c152bd6373Jim Grosbach BeginIdx = BeginIdx + ((SubRegs - 1) * Spacing); 753f26e43df26bb7b0c7bf4853477e36611e2c90deaAndrew Trick Spacing = -Spacing; 754f26e43df26bb7b0c7bf4853477e36611e2c90deaAndrew Trick } 755f26e43df26bb7b0c7bf4853477e36611e2c90deaAndrew Trick#ifndef NDEBUG 756f26e43df26bb7b0c7bf4853477e36611e2c90deaAndrew Trick SmallSet<unsigned, 4> DstRegs; 757f26e43df26bb7b0c7bf4853477e36611e2c90deaAndrew Trick#endif 758d79dedd458c1de07fbc568ea8c3b4194e94df48eAndrew Trick for (unsigned i = 0; i != SubRegs; ++i) { 7596c28682963e96699e7e0ab15282319c152bd6373Jim Grosbach unsigned Dst = TRI->getSubReg(DestReg, BeginIdx + i * Spacing); 7606c28682963e96699e7e0ab15282319c152bd6373Jim Grosbach unsigned Src = TRI->getSubReg(SrcReg, BeginIdx + i * Spacing); 761d79dedd458c1de07fbc568ea8c3b4194e94df48eAndrew Trick assert(Dst && Src && "Bad sub-register"); 762f26e43df26bb7b0c7bf4853477e36611e2c90deaAndrew Trick#ifndef NDEBUG 763f26e43df26bb7b0c7bf4853477e36611e2c90deaAndrew Trick assert(!DstRegs.count(Src) && "destructive vector copy"); 7647611a88b58e0a6960cdb5c72dc18a6c93e44cdc2Andrew Trick DstRegs.insert(Dst); 765f26e43df26bb7b0c7bf4853477e36611e2c90deaAndrew Trick#endif 7666c28682963e96699e7e0ab15282319c152bd6373Jim Grosbach Mov = BuildMI(MBB, I, I->getDebugLoc(), get(Opc), Dst).addReg(Src); 767d79dedd458c1de07fbc568ea8c3b4194e94df48eAndrew Trick // VORR takes two source operands. 768d79dedd458c1de07fbc568ea8c3b4194e94df48eAndrew Trick if (Opc == ARM::VORRq) 769d79dedd458c1de07fbc568ea8c3b4194e94df48eAndrew Trick Mov.addReg(Src); 770d79dedd458c1de07fbc568ea8c3b4194e94df48eAndrew Trick Mov = AddDefaultPred(Mov); 7711b6f5a29ab62fd3e763983f31200b4cc69fa752bJF Bastien // MOVr can set CC. 7721b6f5a29ab62fd3e763983f31200b4cc69fa752bJF Bastien if (Opc == ARM::MOVr) 7731b6f5a29ab62fd3e763983f31200b4cc69fa752bJF Bastien Mov = AddDefaultCC(Mov); 774e5038e191db82d4d92fdeec1b5bce5cae21f6d8fChad Rosier } 775d79dedd458c1de07fbc568ea8c3b4194e94df48eAndrew Trick // Add implicit super-register defs and kills to the last instruction. 776d79dedd458c1de07fbc568ea8c3b4194e94df48eAndrew Trick Mov->addRegisterDefined(DestReg, TRI); 777d79dedd458c1de07fbc568ea8c3b4194e94df48eAndrew Trick if (KillSrc) 778d79dedd458c1de07fbc568ea8c3b4194e94df48eAndrew Trick Mov->addRegisterKilled(SrcReg, TRI); 779334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 780334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 7814cc1407b84dc6dbbc0d62b1d1b8db7c0ddec86ccTim Northoverconst MachineInstrBuilder & 7824cc1407b84dc6dbbc0d62b1d1b8db7c0ddec86ccTim NorthoverARMBaseInstrInfo::AddDReg(MachineInstrBuilder &MIB, unsigned Reg, 7834cc1407b84dc6dbbc0d62b1d1b8db7c0ddec86ccTim Northover unsigned SubIdx, unsigned State, 7844cc1407b84dc6dbbc0d62b1d1b8db7c0ddec86ccTim Northover const TargetRegisterInfo *TRI) const { 785c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Cheng if (!SubIdx) 786c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Cheng return MIB.addReg(Reg, State); 787c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Cheng 788c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Cheng if (TargetRegisterInfo::isPhysicalRegister(Reg)) 789c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Cheng return MIB.addReg(TRI->getSubReg(Reg, SubIdx), State); 790c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Cheng return MIB.addReg(Reg, State, SubIdx); 791c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Cheng} 792c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cbEvan Cheng 793334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinvoid ARMBaseInstrInfo:: 794334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinstoreRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 795334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned SrcReg, bool isKill, int FI, 796746ad69e088176819981b4b2c5ac8dcd49f5e60eEvan Cheng const TargetRegisterClass *RC, 797746ad69e088176819981b4b2c5ac8dcd49f5e60eEvan Cheng const TargetRegisterInfo *TRI) const { 798c7f3ace20c325521c68335a1689645b43b06ddf0Chris Lattner DebugLoc DL; 799334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (I != MBB.end()) DL = I->getDebugLoc(); 800249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MachineFunction &MF = *MBB.getParent(); 801249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MachineFrameInfo &MFI = *MF.getFrameInfo(); 80231bc849123011b8eae6bb3c79876d9a3c26a6a1dJim Grosbach unsigned Align = MFI.getObjectAlignment(FI); 803249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov 804249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MachineMemOperand *MMO = 805978e0dfe46e481bfb1281e683aa308329e879e95Jay Foad MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FI), 80659db5496f4fc2ef6111569e542f8b65480ef14c1Chris Lattner MachineMemOperand::MOStore, 807249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MFI.getObjectSize(FI), 80831bc849123011b8eae6bb3c79876d9a3c26a6a1dJim Grosbach Align); 809334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 810e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson switch (RC->getSize()) { 811e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson case 4: 812e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson if (ARM::GPRRegClass.hasSubClassEq(RC)) { 813e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::STRi12)) 814334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(SrcReg, getKillRegState(isKill)) 8157e3383c007f53b3a00675af225e428cb66ddf404Jim Grosbach .addFrameIndex(FI).addImm(0).addMemOperand(MMO)); 816e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson } else if (ARM::SPRRegClass.hasSubClassEq(RC)) { 817e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTRS)) 818d31c5496d7e1580058b5c6fbc8fd537a641ea590Evan Cheng .addReg(SrcReg, getKillRegState(isKill)) 819d31c5496d7e1580058b5c6fbc8fd537a641ea590Evan Cheng .addFrameIndex(FI).addImm(0).addMemOperand(MMO)); 820e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson } else 821e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson llvm_unreachable("Unknown reg class!"); 822e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson break; 823e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson case 8: 824e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson if (ARM::DPRRegClass.hasSubClassEq(RC)) { 825e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTRD)) 826334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(SrcReg, getKillRegState(isKill)) 827249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov .addFrameIndex(FI).addImm(0).addMemOperand(MMO)); 828cd275f5687799e63956beabe35fc1718dc022f70Jakob Stoklund Olesen } else if (ARM::GPRPairRegClass.hasSubClassEq(RC)) { 8294cc1407b84dc6dbbc0d62b1d1b8db7c0ddec86ccTim Northover if (Subtarget.hasV5TEOps()) { 8304cc1407b84dc6dbbc0d62b1d1b8db7c0ddec86ccTim Northover MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::STRD)); 8314cc1407b84dc6dbbc0d62b1d1b8db7c0ddec86ccTim Northover AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill), TRI); 8324cc1407b84dc6dbbc0d62b1d1b8db7c0ddec86ccTim Northover AddDReg(MIB, SrcReg, ARM::gsub_1, 0, TRI); 8334cc1407b84dc6dbbc0d62b1d1b8db7c0ddec86ccTim Northover MIB.addFrameIndex(FI).addReg(0).addImm(0).addMemOperand(MMO); 8344cc1407b84dc6dbbc0d62b1d1b8db7c0ddec86ccTim Northover 8354cc1407b84dc6dbbc0d62b1d1b8db7c0ddec86ccTim Northover AddDefaultPred(MIB); 8364cc1407b84dc6dbbc0d62b1d1b8db7c0ddec86ccTim Northover } else { 8374cc1407b84dc6dbbc0d62b1d1b8db7c0ddec86ccTim Northover // Fallback to STM instruction, which has existed since the dawn of 8384cc1407b84dc6dbbc0d62b1d1b8db7c0ddec86ccTim Northover // time. 8394cc1407b84dc6dbbc0d62b1d1b8db7c0ddec86ccTim Northover MachineInstrBuilder MIB = 8404cc1407b84dc6dbbc0d62b1d1b8db7c0ddec86ccTim Northover AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::STMIA)) 8414cc1407b84dc6dbbc0d62b1d1b8db7c0ddec86ccTim Northover .addFrameIndex(FI).addMemOperand(MMO)); 8424cc1407b84dc6dbbc0d62b1d1b8db7c0ddec86ccTim Northover AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill), TRI); 8434cc1407b84dc6dbbc0d62b1d1b8db7c0ddec86ccTim Northover AddDReg(MIB, SrcReg, ARM::gsub_1, 0, TRI); 8444cc1407b84dc6dbbc0d62b1d1b8db7c0ddec86ccTim Northover } 845e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson } else 846e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson llvm_unreachable("Unknown reg class!"); 847e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson break; 848e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson case 16: 8495b2f9136644c58ae32e00d8317540692a697d1c9Jakob Stoklund Olesen if (ARM::DPairRegClass.hasSubClassEq(RC)) { 8507255a4e1332ccb69918ebe041dff05f9e4e5815dJakob Stoklund Olesen // Use aligned spills if the stack can be realigned. 8517255a4e1332ccb69918ebe041dff05f9e4e5815dJakob Stoklund Olesen if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) { 85228f08c93e75d291695ea89b9004145103292e85bJim Grosbach AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1q64)) 853f967ca0eaf30325cabe3c1971bf0dba16cf1b027Bob Wilson .addFrameIndex(FI).addImm(16) 85469b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng .addReg(SrcReg, getKillRegState(isKill)) 85569b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng .addMemOperand(MMO)); 856e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson } else { 857e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMQIA)) 85869b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng .addReg(SrcReg, getKillRegState(isKill)) 85969b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng .addFrameIndex(FI) 86069b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng .addMemOperand(MMO)); 861e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson } 862e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson } else 863e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson llvm_unreachable("Unknown reg class!"); 864e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson break; 865b58d7d03125526c152ade0c75be302b3c9eab997Anton Korobeynikov case 24: 866b58d7d03125526c152ade0c75be302b3c9eab997Anton Korobeynikov if (ARM::DTripleRegClass.hasSubClassEq(RC)) { 867b58d7d03125526c152ade0c75be302b3c9eab997Anton Korobeynikov // Use aligned spills if the stack can be realigned. 868b58d7d03125526c152ade0c75be302b3c9eab997Anton Korobeynikov if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) { 869b58d7d03125526c152ade0c75be302b3c9eab997Anton Korobeynikov AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1d64TPseudo)) 870b58d7d03125526c152ade0c75be302b3c9eab997Anton Korobeynikov .addFrameIndex(FI).addImm(16) 871b58d7d03125526c152ade0c75be302b3c9eab997Anton Korobeynikov .addReg(SrcReg, getKillRegState(isKill)) 872b58d7d03125526c152ade0c75be302b3c9eab997Anton Korobeynikov .addMemOperand(MMO)); 873b58d7d03125526c152ade0c75be302b3c9eab997Anton Korobeynikov } else { 874b58d7d03125526c152ade0c75be302b3c9eab997Anton Korobeynikov MachineInstrBuilder MIB = 875b58d7d03125526c152ade0c75be302b3c9eab997Anton Korobeynikov AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMDIA)) 876b58d7d03125526c152ade0c75be302b3c9eab997Anton Korobeynikov .addFrameIndex(FI)) 877b58d7d03125526c152ade0c75be302b3c9eab997Anton Korobeynikov .addMemOperand(MMO); 878b58d7d03125526c152ade0c75be302b3c9eab997Anton Korobeynikov MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI); 879b58d7d03125526c152ade0c75be302b3c9eab997Anton Korobeynikov MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI); 880b58d7d03125526c152ade0c75be302b3c9eab997Anton Korobeynikov AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI); 881b58d7d03125526c152ade0c75be302b3c9eab997Anton Korobeynikov } 882b58d7d03125526c152ade0c75be302b3c9eab997Anton Korobeynikov } else 883b58d7d03125526c152ade0c75be302b3c9eab997Anton Korobeynikov llvm_unreachable("Unknown reg class!"); 884b58d7d03125526c152ade0c75be302b3c9eab997Anton Korobeynikov break; 885e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson case 32: 886b58d7d03125526c152ade0c75be302b3c9eab997Anton Korobeynikov if (ARM::QQPRRegClass.hasSubClassEq(RC) || ARM::DQuadRegClass.hasSubClassEq(RC)) { 887e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) { 888e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson // FIXME: It's possible to only store part of the QQ register if the 889e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson // spilled def has a sub-register index. 890e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1d64QPseudo)) 891168f382dc67e5940cabdb28dc933c4f91cdd3137Bob Wilson .addFrameIndex(FI).addImm(16) 892168f382dc67e5940cabdb28dc933c4f91cdd3137Bob Wilson .addReg(SrcReg, getKillRegState(isKill)) 893168f382dc67e5940cabdb28dc933c4f91cdd3137Bob Wilson .addMemOperand(MMO)); 894e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson } else { 895e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson MachineInstrBuilder MIB = 896e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMDIA)) 89773fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling .addFrameIndex(FI)) 898e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson .addMemOperand(MMO); 899e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI); 900e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI); 901e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI); 902e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI); 903e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson } 904e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson } else 905e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson llvm_unreachable("Unknown reg class!"); 906e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson break; 907e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson case 64: 908e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson if (ARM::QQQQPRRegClass.hasSubClassEq(RC)) { 909e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson MachineInstrBuilder MIB = 910e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMDIA)) 911e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson .addFrameIndex(FI)) 912e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson .addMemOperand(MMO); 913e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI); 914e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI); 915e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI); 916e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson MIB = AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI); 917e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson MIB = AddDReg(MIB, SrcReg, ARM::dsub_4, 0, TRI); 918e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson MIB = AddDReg(MIB, SrcReg, ARM::dsub_5, 0, TRI); 919e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson MIB = AddDReg(MIB, SrcReg, ARM::dsub_6, 0, TRI); 920e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson AddDReg(MIB, SrcReg, ARM::dsub_7, 0, TRI); 921e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson } else 922e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson llvm_unreachable("Unknown reg class!"); 923e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson break; 924e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson default: 925e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson llvm_unreachable("Unknown reg class!"); 926334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 927334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 928334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 92934327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesenunsigned 93034327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund OlesenARMBaseInstrInfo::isStoreToStackSlot(const MachineInstr *MI, 93134327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen int &FrameIndex) const { 93234327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen switch (MI->getOpcode()) { 93334327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen default: break; 9347e3383c007f53b3a00675af225e428cb66ddf404Jim Grosbach case ARM::STRrs: 93534327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen case ARM::t2STRs: // FIXME: don't use t2STRs to access frame. 93634327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen if (MI->getOperand(1).isFI() && 93734327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen MI->getOperand(2).isReg() && 93834327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen MI->getOperand(3).isImm() && 93934327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen MI->getOperand(2).getReg() == 0 && 94034327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen MI->getOperand(3).getImm() == 0) { 94134327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen FrameIndex = MI->getOperand(1).getIndex(); 94234327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen return MI->getOperand(0).getReg(); 94334327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen } 94434327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen break; 9457e3383c007f53b3a00675af225e428cb66ddf404Jim Grosbach case ARM::STRi12: 94634327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen case ARM::t2STRi12: 94774472b4bf963c424da04f42dffdb94c85ef964bcJim Grosbach case ARM::tSTRspi: 94834327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen case ARM::VSTRD: 94934327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen case ARM::VSTRS: 95034327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen if (MI->getOperand(1).isFI() && 95134327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen MI->getOperand(2).isImm() && 95234327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen MI->getOperand(2).getImm() == 0) { 95334327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen FrameIndex = MI->getOperand(1).getIndex(); 95434327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen return MI->getOperand(0).getReg(); 95534327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen } 95634327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen break; 95728f08c93e75d291695ea89b9004145103292e85bJim Grosbach case ARM::VST1q64: 958161474d198d44ab505861c1ec55f022b27314b35Anton Korobeynikov case ARM::VST1d64TPseudo: 959161474d198d44ab505861c1ec55f022b27314b35Anton Korobeynikov case ARM::VST1d64QPseudo: 960d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen if (MI->getOperand(0).isFI() && 961d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen MI->getOperand(2).getSubReg() == 0) { 962d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen FrameIndex = MI->getOperand(0).getIndex(); 963d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen return MI->getOperand(2).getReg(); 964d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen } 96531bbc51ac9245bc82c933c9db8358ca9bb558ac5Jakob Stoklund Olesen break; 96673fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMQIA: 967d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen if (MI->getOperand(1).isFI() && 968d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen MI->getOperand(0).getSubReg() == 0) { 969d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen FrameIndex = MI->getOperand(1).getIndex(); 970d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen return MI->getOperand(0).getReg(); 971d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen } 972d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen break; 97334327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen } 97434327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen 97534327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen return 0; 97634327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen} 97734327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen 97836ee0e640554b8cc6ad1658fc3049e05d9967160Jakob Stoklund Olesenunsigned ARMBaseInstrInfo::isStoreToStackSlotPostFE(const MachineInstr *MI, 97936ee0e640554b8cc6ad1658fc3049e05d9967160Jakob Stoklund Olesen int &FrameIndex) const { 98036ee0e640554b8cc6ad1658fc3049e05d9967160Jakob Stoklund Olesen const MachineMemOperand *Dummy; 9815a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng return MI->mayStore() && hasStoreToStackSlot(MI, Dummy, FrameIndex); 98236ee0e640554b8cc6ad1658fc3049e05d9967160Jakob Stoklund Olesen} 98336ee0e640554b8cc6ad1658fc3049e05d9967160Jakob Stoklund Olesen 984334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinvoid ARMBaseInstrInfo:: 985334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinloadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 986334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned DestReg, int FI, 987746ad69e088176819981b4b2c5ac8dcd49f5e60eEvan Cheng const TargetRegisterClass *RC, 988746ad69e088176819981b4b2c5ac8dcd49f5e60eEvan Cheng const TargetRegisterInfo *TRI) const { 989c7f3ace20c325521c68335a1689645b43b06ddf0Chris Lattner DebugLoc DL; 990334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (I != MBB.end()) DL = I->getDebugLoc(); 991249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MachineFunction &MF = *MBB.getParent(); 992249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MachineFrameInfo &MFI = *MF.getFrameInfo(); 99331bc849123011b8eae6bb3c79876d9a3c26a6a1dJim Grosbach unsigned Align = MFI.getObjectAlignment(FI); 994249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MachineMemOperand *MMO = 99559db5496f4fc2ef6111569e542f8b65480ef14c1Chris Lattner MF.getMachineMemOperand( 996978e0dfe46e481bfb1281e683aa308329e879e95Jay Foad MachinePointerInfo::getFixedStack(FI), 99759db5496f4fc2ef6111569e542f8b65480ef14c1Chris Lattner MachineMemOperand::MOLoad, 998249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MFI.getObjectSize(FI), 99931bc849123011b8eae6bb3c79876d9a3c26a6a1dJim Grosbach Align); 1000334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 1001e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson switch (RC->getSize()) { 1002e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson case 4: 1003e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson if (ARM::GPRRegClass.hasSubClassEq(RC)) { 1004e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::LDRi12), DestReg) 10053e5561247202bae994dd259a2d8dc4eff8f799f3Jim Grosbach .addFrameIndex(FI).addImm(0).addMemOperand(MMO)); 1006e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson 1007e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson } else if (ARM::SPRRegClass.hasSubClassEq(RC)) { 1008e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRS), DestReg) 1009d31c5496d7e1580058b5c6fbc8fd537a641ea590Evan Cheng .addFrameIndex(FI).addImm(0).addMemOperand(MMO)); 1010e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson } else 1011e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson llvm_unreachable("Unknown reg class!"); 1012ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson break; 1013e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson case 8: 1014e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson if (ARM::DPRRegClass.hasSubClassEq(RC)) { 1015e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRD), DestReg) 1016249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov .addFrameIndex(FI).addImm(0).addMemOperand(MMO)); 1017cd275f5687799e63956beabe35fc1718dc022f70Jakob Stoklund Olesen } else if (ARM::GPRPairRegClass.hasSubClassEq(RC)) { 10184cc1407b84dc6dbbc0d62b1d1b8db7c0ddec86ccTim Northover MachineInstrBuilder MIB; 10194cc1407b84dc6dbbc0d62b1d1b8db7c0ddec86ccTim Northover 10204cc1407b84dc6dbbc0d62b1d1b8db7c0ddec86ccTim Northover if (Subtarget.hasV5TEOps()) { 10214cc1407b84dc6dbbc0d62b1d1b8db7c0ddec86ccTim Northover MIB = BuildMI(MBB, I, DL, get(ARM::LDRD)); 10224cc1407b84dc6dbbc0d62b1d1b8db7c0ddec86ccTim Northover AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI); 10234cc1407b84dc6dbbc0d62b1d1b8db7c0ddec86ccTim Northover AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI); 10244cc1407b84dc6dbbc0d62b1d1b8db7c0ddec86ccTim Northover MIB.addFrameIndex(FI).addReg(0).addImm(0).addMemOperand(MMO); 10254cc1407b84dc6dbbc0d62b1d1b8db7c0ddec86ccTim Northover 10264cc1407b84dc6dbbc0d62b1d1b8db7c0ddec86ccTim Northover AddDefaultPred(MIB); 10274cc1407b84dc6dbbc0d62b1d1b8db7c0ddec86ccTim Northover } else { 10284cc1407b84dc6dbbc0d62b1d1b8db7c0ddec86ccTim Northover // Fallback to LDM instruction, which has existed since the dawn of 10294cc1407b84dc6dbbc0d62b1d1b8db7c0ddec86ccTim Northover // time. 10304cc1407b84dc6dbbc0d62b1d1b8db7c0ddec86ccTim Northover MIB = AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::LDMIA)) 10314cc1407b84dc6dbbc0d62b1d1b8db7c0ddec86ccTim Northover .addFrameIndex(FI).addMemOperand(MMO)); 10324cc1407b84dc6dbbc0d62b1d1b8db7c0ddec86ccTim Northover MIB = AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI); 10334cc1407b84dc6dbbc0d62b1d1b8db7c0ddec86ccTim Northover MIB = AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI); 10344cc1407b84dc6dbbc0d62b1d1b8db7c0ddec86ccTim Northover } 10354cc1407b84dc6dbbc0d62b1d1b8db7c0ddec86ccTim Northover 1036cd275f5687799e63956beabe35fc1718dc022f70Jakob Stoklund Olesen if (TargetRegisterInfo::isPhysicalRegister(DestReg)) 1037cd275f5687799e63956beabe35fc1718dc022f70Jakob Stoklund Olesen MIB.addReg(DestReg, RegState::ImplicitDefine); 1038e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson } else 1039e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson llvm_unreachable("Unknown reg class!"); 1040ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson break; 1041e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson case 16: 10425b2f9136644c58ae32e00d8317540692a697d1c9Jakob Stoklund Olesen if (ARM::DPairRegClass.hasSubClassEq(RC)) { 10437255a4e1332ccb69918ebe041dff05f9e4e5815dJakob Stoklund Olesen if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) { 104428f08c93e75d291695ea89b9004145103292e85bJim Grosbach AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1q64), DestReg) 1045f967ca0eaf30325cabe3c1971bf0dba16cf1b027Bob Wilson .addFrameIndex(FI).addImm(16) 104669b9f9883e10efa266d59a5dd2f4d99de92c6707Evan Cheng .addMemOperand(MMO)); 1047e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson } else { 1048e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMQIA), DestReg) 1049e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson .addFrameIndex(FI) 1050e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson .addMemOperand(MMO)); 1051e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson } 1052e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson } else 1053e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson llvm_unreachable("Unknown reg class!"); 1054ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson break; 1055b58d7d03125526c152ade0c75be302b3c9eab997Anton Korobeynikov case 24: 1056b58d7d03125526c152ade0c75be302b3c9eab997Anton Korobeynikov if (ARM::DTripleRegClass.hasSubClassEq(RC)) { 1057b58d7d03125526c152ade0c75be302b3c9eab997Anton Korobeynikov if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) { 1058b58d7d03125526c152ade0c75be302b3c9eab997Anton Korobeynikov AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1d64TPseudo), DestReg) 1059b58d7d03125526c152ade0c75be302b3c9eab997Anton Korobeynikov .addFrameIndex(FI).addImm(16) 1060b58d7d03125526c152ade0c75be302b3c9eab997Anton Korobeynikov .addMemOperand(MMO)); 1061b58d7d03125526c152ade0c75be302b3c9eab997Anton Korobeynikov } else { 1062b58d7d03125526c152ade0c75be302b3c9eab997Anton Korobeynikov MachineInstrBuilder MIB = 1063b58d7d03125526c152ade0c75be302b3c9eab997Anton Korobeynikov AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMDIA)) 1064b58d7d03125526c152ade0c75be302b3c9eab997Anton Korobeynikov .addFrameIndex(FI) 1065b58d7d03125526c152ade0c75be302b3c9eab997Anton Korobeynikov .addMemOperand(MMO)); 1066b58d7d03125526c152ade0c75be302b3c9eab997Anton Korobeynikov MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI); 1067b58d7d03125526c152ade0c75be302b3c9eab997Anton Korobeynikov MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI); 1068b58d7d03125526c152ade0c75be302b3c9eab997Anton Korobeynikov MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI); 1069b58d7d03125526c152ade0c75be302b3c9eab997Anton Korobeynikov if (TargetRegisterInfo::isPhysicalRegister(DestReg)) 1070b58d7d03125526c152ade0c75be302b3c9eab997Anton Korobeynikov MIB.addReg(DestReg, RegState::ImplicitDefine); 1071b58d7d03125526c152ade0c75be302b3c9eab997Anton Korobeynikov } 1072b58d7d03125526c152ade0c75be302b3c9eab997Anton Korobeynikov } else 1073b58d7d03125526c152ade0c75be302b3c9eab997Anton Korobeynikov llvm_unreachable("Unknown reg class!"); 1074b58d7d03125526c152ade0c75be302b3c9eab997Anton Korobeynikov break; 1075b58d7d03125526c152ade0c75be302b3c9eab997Anton Korobeynikov case 32: 1076b58d7d03125526c152ade0c75be302b3c9eab997Anton Korobeynikov if (ARM::QQPRRegClass.hasSubClassEq(RC) || ARM::DQuadRegClass.hasSubClassEq(RC)) { 1077e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) { 1078e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1d64QPseudo), DestReg) 1079168f382dc67e5940cabdb28dc933c4f91cdd3137Bob Wilson .addFrameIndex(FI).addImm(16) 1080168f382dc67e5940cabdb28dc933c4f91cdd3137Bob Wilson .addMemOperand(MMO)); 1081e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson } else { 1082e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson MachineInstrBuilder MIB = 108373fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMDIA)) 108473fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling .addFrameIndex(FI)) 1085e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson .addMemOperand(MMO); 1086fce711cb65716f86b4e150f42cbb597bbecf7dbeJakob Stoklund Olesen MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI); 1087fce711cb65716f86b4e150f42cbb597bbecf7dbeJakob Stoklund Olesen MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI); 1088fce711cb65716f86b4e150f42cbb597bbecf7dbeJakob Stoklund Olesen MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI); 1089fce711cb65716f86b4e150f42cbb597bbecf7dbeJakob Stoklund Olesen MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::DefineNoRead, TRI); 10903247af294996ff8588077c06505b64966ad41542Jakob Stoklund Olesen if (TargetRegisterInfo::isPhysicalRegister(DestReg)) 10913247af294996ff8588077c06505b64966ad41542Jakob Stoklund Olesen MIB.addReg(DestReg, RegState::ImplicitDefine); 1092e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson } 1093e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson } else 1094e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson llvm_unreachable("Unknown reg class!"); 1095ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson break; 1096e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson case 64: 1097e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson if (ARM::QQQQPRRegClass.hasSubClassEq(RC)) { 1098e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson MachineInstrBuilder MIB = 109973fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMDIA)) 110073fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling .addFrameIndex(FI)) 1101e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson .addMemOperand(MMO); 1102fce711cb65716f86b4e150f42cbb597bbecf7dbeJakob Stoklund Olesen MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI); 1103fce711cb65716f86b4e150f42cbb597bbecf7dbeJakob Stoklund Olesen MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI); 1104fce711cb65716f86b4e150f42cbb597bbecf7dbeJakob Stoklund Olesen MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI); 1105fce711cb65716f86b4e150f42cbb597bbecf7dbeJakob Stoklund Olesen MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::DefineNoRead, TRI); 1106fce711cb65716f86b4e150f42cbb597bbecf7dbeJakob Stoklund Olesen MIB = AddDReg(MIB, DestReg, ARM::dsub_4, RegState::DefineNoRead, TRI); 1107fce711cb65716f86b4e150f42cbb597bbecf7dbeJakob Stoklund Olesen MIB = AddDReg(MIB, DestReg, ARM::dsub_5, RegState::DefineNoRead, TRI); 1108fce711cb65716f86b4e150f42cbb597bbecf7dbeJakob Stoklund Olesen MIB = AddDReg(MIB, DestReg, ARM::dsub_6, RegState::DefineNoRead, TRI); 1109fce711cb65716f86b4e150f42cbb597bbecf7dbeJakob Stoklund Olesen MIB = AddDReg(MIB, DestReg, ARM::dsub_7, RegState::DefineNoRead, TRI); 11103247af294996ff8588077c06505b64966ad41542Jakob Stoklund Olesen if (TargetRegisterInfo::isPhysicalRegister(DestReg)) 11113247af294996ff8588077c06505b64966ad41542Jakob Stoklund Olesen MIB.addReg(DestReg, RegState::ImplicitDefine); 1112e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson } else 1113e66ef2d5f54391e53d2c0febb1ef854d060716f0Owen Anderson llvm_unreachable("Unknown reg class!"); 1114ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson break; 1115ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson default: 1116ebe99b2c198ec08c5e4a032ec0afb0345c747706Bob Wilson llvm_unreachable("Unknown regclass!"); 1117334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 1118334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 1119334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 112034327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesenunsigned 112134327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund OlesenARMBaseInstrInfo::isLoadFromStackSlot(const MachineInstr *MI, 112234327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen int &FrameIndex) const { 112334327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen switch (MI->getOpcode()) { 112434327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen default: break; 11253e5561247202bae994dd259a2d8dc4eff8f799f3Jim Grosbach case ARM::LDRrs: 112634327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen case ARM::t2LDRs: // FIXME: don't use t2LDRs to access frame. 112734327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen if (MI->getOperand(1).isFI() && 112834327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen MI->getOperand(2).isReg() && 112934327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen MI->getOperand(3).isImm() && 113034327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen MI->getOperand(2).getReg() == 0 && 113134327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen MI->getOperand(3).getImm() == 0) { 113234327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen FrameIndex = MI->getOperand(1).getIndex(); 113334327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen return MI->getOperand(0).getReg(); 113434327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen } 113534327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen break; 11363e5561247202bae994dd259a2d8dc4eff8f799f3Jim Grosbach case ARM::LDRi12: 113734327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen case ARM::t2LDRi12: 113874472b4bf963c424da04f42dffdb94c85ef964bcJim Grosbach case ARM::tLDRspi: 113934327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen case ARM::VLDRD: 114034327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen case ARM::VLDRS: 114134327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen if (MI->getOperand(1).isFI() && 114234327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen MI->getOperand(2).isImm() && 114334327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen MI->getOperand(2).getImm() == 0) { 114434327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen FrameIndex = MI->getOperand(1).getIndex(); 1145d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen return MI->getOperand(0).getReg(); 1146d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen } 1147d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen break; 114828f08c93e75d291695ea89b9004145103292e85bJim Grosbach case ARM::VLD1q64: 1149161474d198d44ab505861c1ec55f022b27314b35Anton Korobeynikov case ARM::VLD1d64TPseudo: 1150161474d198d44ab505861c1ec55f022b27314b35Anton Korobeynikov case ARM::VLD1d64QPseudo: 1151d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen if (MI->getOperand(1).isFI() && 1152d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen MI->getOperand(0).getSubReg() == 0) { 1153d64816a8d04e5b20b7a0628bc1f22607c07e8f69Jakob Stoklund Olesen FrameIndex = MI->getOperand(1).getIndex(); 115406f264e504d75f0426eea55b9f9e36c780d8a4fcJakob Stoklund Olesen return MI->getOperand(0).getReg(); 115506f264e504d75f0426eea55b9f9e36c780d8a4fcJakob Stoklund Olesen } 115606f264e504d75f0426eea55b9f9e36c780d8a4fcJakob Stoklund Olesen break; 115773fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMQIA: 115806f264e504d75f0426eea55b9f9e36c780d8a4fcJakob Stoklund Olesen if (MI->getOperand(1).isFI() && 115906f264e504d75f0426eea55b9f9e36c780d8a4fcJakob Stoklund Olesen MI->getOperand(0).getSubReg() == 0) { 116006f264e504d75f0426eea55b9f9e36c780d8a4fcJakob Stoklund Olesen FrameIndex = MI->getOperand(1).getIndex(); 116134327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen return MI->getOperand(0).getReg(); 116234327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen } 116334327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen break; 116434327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen } 116534327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen 116634327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen return 0; 116734327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen} 116834327856d92d027733524b9418bd188a9e8db5dbJakob Stoklund Olesen 116936ee0e640554b8cc6ad1658fc3049e05d9967160Jakob Stoklund Olesenunsigned ARMBaseInstrInfo::isLoadFromStackSlotPostFE(const MachineInstr *MI, 117036ee0e640554b8cc6ad1658fc3049e05d9967160Jakob Stoklund Olesen int &FrameIndex) const { 117136ee0e640554b8cc6ad1658fc3049e05d9967160Jakob Stoklund Olesen const MachineMemOperand *Dummy; 11725a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng return MI->mayLoad() && hasLoadFromStackSlot(MI, Dummy, FrameIndex); 117336ee0e640554b8cc6ad1658fc3049e05d9967160Jakob Stoklund Olesen} 117436ee0e640554b8cc6ad1658fc3049e05d9967160Jakob Stoklund Olesen 1175142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesenbool ARMBaseInstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const{ 1176142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen // This hook gets to expand COPY instructions before they become 1177142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen // copyPhysReg() calls. Look for VMOVS instructions that can legally be 1178142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen // widened to VMOVD. We prefer the VMOVD when possible because it may be 1179142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen // changed into a VORR that can go down the NEON pipeline. 1180bcbf3fddef46f1f6e2f2408064c4b75e4b6c90f5Silviu Baranga if (!WidenVMOVS || !MI->isCopy() || Subtarget.isCortexA15()) 1181142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen return false; 1182142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen 1183142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen // Look for a copy between even S-registers. That is where we keep floats 1184142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen // when using NEON v2f32 instructions for f32 arithmetic. 1185142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen unsigned DstRegS = MI->getOperand(0).getReg(); 1186142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen unsigned SrcRegS = MI->getOperand(1).getReg(); 1187142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen if (!ARM::SPRRegClass.contains(DstRegS, SrcRegS)) 1188142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen return false; 1189142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen 1190142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen const TargetRegisterInfo *TRI = &getRegisterInfo(); 1191142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen unsigned DstRegD = TRI->getMatchingSuperReg(DstRegS, ARM::ssub_0, 1192142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen &ARM::DPRRegClass); 1193142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen unsigned SrcRegD = TRI->getMatchingSuperReg(SrcRegS, ARM::ssub_0, 1194142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen &ARM::DPRRegClass); 1195142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen if (!DstRegD || !SrcRegD) 1196142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen return false; 1197142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen 1198142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen // We want to widen this into a DstRegD = VMOVD SrcRegD copy. This is only 1199142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen // legal if the COPY already defines the full DstRegD, and it isn't a 1200142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen // sub-register insertion. 1201142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen if (!MI->definesRegister(DstRegD, TRI) || MI->readsRegister(DstRegD, TRI)) 1202142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen return false; 1203142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen 12041c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen // A dead copy shouldn't show up here, but reject it just in case. 12051c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen if (MI->getOperand(0).isDead()) 12061c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen return false; 12071c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen 12081c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen // All clear, widen the COPY. 1209142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen DEBUG(dbgs() << "widening: " << *MI); 121037a942cd52725b1d390989a8267a764b42fcb5d3Jakob Stoklund Olesen MachineInstrBuilder MIB(*MI->getParent()->getParent(), MI); 12111c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen 12121c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen // Get rid of the old <imp-def> of DstRegD. Leave it if it defines a Q-reg 12131c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen // or some other super-register. 12141c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen int ImpDefIdx = MI->findRegisterDefOperandIdx(DstRegD); 12151c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen if (ImpDefIdx != -1) 12161c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen MI->RemoveOperand(ImpDefIdx); 12171c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen 12181c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen // Change the opcode and operands. 1219142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen MI->setDesc(get(ARM::VMOVD)); 1220142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen MI->getOperand(0).setReg(DstRegD); 1221142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen MI->getOperand(1).setReg(SrcRegD); 122237a942cd52725b1d390989a8267a764b42fcb5d3Jakob Stoklund Olesen AddDefaultPred(MIB); 12231c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen 12241c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen // We are now reading SrcRegD instead of SrcRegS. This may upset the 12251c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen // register scavenger and machine verifier, so we need to indicate that we 12261c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen // are reading an undefined value from SrcRegD, but a proper value from 12271c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen // SrcRegS. 12281c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen MI->getOperand(1).setIsUndef(); 122937a942cd52725b1d390989a8267a764b42fcb5d3Jakob Stoklund Olesen MIB.addReg(SrcRegS, RegState::Implicit); 12301c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen 12311c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen // SrcRegD may actually contain an unrelated value in the ssub_1 12321c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen // sub-register. Don't kill it. Only kill the ssub_0 sub-register. 12331c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen if (MI->getOperand(1).isKill()) { 12341c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen MI->getOperand(1).setIsKill(false); 12351c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen MI->addRegisterKilled(SrcRegS, TRI, true); 12361c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen } 12371c062c24aba08962b4687f56b274f182e5b7a8e5Jakob Stoklund Olesen 1238142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen DEBUG(dbgs() << "replaced by: " << *MI); 1239142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen return true; 1240142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen} 1241142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen 124230ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen/// Create a copy of a const pool value. Update CPI to the new index and return 124330ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen/// the label UID. 124430ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesenstatic unsigned duplicateCPV(MachineFunction &MF, unsigned &CPI) { 124530ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen MachineConstantPool *MCP = MF.getConstantPool(); 124630ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 124730ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen 124830ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPI]; 124930ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen assert(MCPE.isMachineConstantPoolEntry() && 125030ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen "Expecting a machine constantpool entry!"); 125130ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen ARMConstantPoolValue *ACPV = 125230ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal); 125330ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen 12545de5d4b6d0eb3fd379fa571d82f6fa764460b3b8Evan Cheng unsigned PCLabelId = AFI->createPICLabelUId(); 1255dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines ARMConstantPoolValue *NewCPV = nullptr; 125636b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines 125751f5b67395780b8421f4aa6ee998ed51b23dae9dJim Grosbach // FIXME: The below assumes PIC relocation model and that the function 125851f5b67395780b8421f4aa6ee998ed51b23dae9dJim Grosbach // is Thumb mode (t1 or t2). PCAdjustment would be 8 for ARM mode PIC, and 125951f5b67395780b8421f4aa6ee998ed51b23dae9dJim Grosbach // zero for non-PIC in ARM or Thumb. The callers are all of thumb LDR 126051f5b67395780b8421f4aa6ee998ed51b23dae9dJim Grosbach // instructions, so that's probably OK, but is PIC always correct when 126151f5b67395780b8421f4aa6ee998ed51b23dae9dJim Grosbach // we get here? 126230ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen if (ACPV->isGlobalValue()) 12635bb779976a7d8e48408051ec2289fe69206dc072Bill Wendling NewCPV = ARMConstantPoolConstant:: 12645bb779976a7d8e48408051ec2289fe69206dc072Bill Wendling Create(cast<ARMConstantPoolConstant>(ACPV)->getGV(), PCLabelId, 12655bb779976a7d8e48408051ec2289fe69206dc072Bill Wendling ARMCP::CPValue, 4); 126630ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen else if (ACPV->isExtSymbol()) 1267fe31e673506ef9a1080eaa684b43b34178c6f447Bill Wendling NewCPV = ARMConstantPoolSymbol:: 1268fe31e673506ef9a1080eaa684b43b34178c6f447Bill Wendling Create(MF.getFunction()->getContext(), 1269fe31e673506ef9a1080eaa684b43b34178c6f447Bill Wendling cast<ARMConstantPoolSymbol>(ACPV)->getSymbol(), PCLabelId, 4); 127030ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen else if (ACPV->isBlockAddress()) 12715bb779976a7d8e48408051ec2289fe69206dc072Bill Wendling NewCPV = ARMConstantPoolConstant:: 12725bb779976a7d8e48408051ec2289fe69206dc072Bill Wendling Create(cast<ARMConstantPoolConstant>(ACPV)->getBlockAddress(), PCLabelId, 12735bb779976a7d8e48408051ec2289fe69206dc072Bill Wendling ARMCP::CPBlockAddress, 4); 127451f5b67395780b8421f4aa6ee998ed51b23dae9dJim Grosbach else if (ACPV->isLSDA()) 12755bb779976a7d8e48408051ec2289fe69206dc072Bill Wendling NewCPV = ARMConstantPoolConstant::Create(MF.getFunction(), PCLabelId, 12765bb779976a7d8e48408051ec2289fe69206dc072Bill Wendling ARMCP::CPLSDA, 4); 1277e00897c5a91febe90ba21082fc636be892bf9bf1Bill Wendling else if (ACPV->isMachineBasicBlock()) 12783320f2a3bfd4daec23ba7ceb50525140cc6316daBill Wendling NewCPV = ARMConstantPoolMBB:: 12793320f2a3bfd4daec23ba7ceb50525140cc6316daBill Wendling Create(MF.getFunction()->getContext(), 12803320f2a3bfd4daec23ba7ceb50525140cc6316daBill Wendling cast<ARMConstantPoolMBB>(ACPV)->getMBB(), PCLabelId, 4); 128130ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen else 128230ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen llvm_unreachable("Unexpected ARM constantpool value type!!"); 128330ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen CPI = MCP->getConstantPoolIndex(NewCPV, MCPE.getAlignment()); 128430ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen return PCLabelId; 128530ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen} 128630ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen 1287fdc834046efd427d474e3b899ec69354c05071e0Evan Chengvoid ARMBaseInstrInfo:: 1288fdc834046efd427d474e3b899ec69354c05071e0Evan ChengreMaterialize(MachineBasicBlock &MBB, 1289fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng MachineBasicBlock::iterator I, 1290fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng unsigned DestReg, unsigned SubIdx, 1291d57cdd5683ea926e489067364fb7ffe5fd5d35eeEvan Cheng const MachineInstr *Orig, 12929edf7deb37f0f97664f279040fa15d89f32e23d9Jakob Stoklund Olesen const TargetRegisterInfo &TRI) const { 1293fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng unsigned Opcode = Orig->getOpcode(); 1294fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng switch (Opcode) { 1295fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng default: { 1296fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig); 12979edf7deb37f0f97664f279040fa15d89f32e23d9Jakob Stoklund Olesen MI->substituteRegister(Orig->getOperand(0).getReg(), DestReg, SubIdx, TRI); 1298fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng MBB.insert(I, MI); 1299fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng break; 1300fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng } 1301fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng case ARM::tLDRpci_pic: 1302fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng case ARM::t2LDRpci_pic: { 1303fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng MachineFunction &MF = *MBB.getParent(); 1304fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng unsigned CPI = Orig->getOperand(1).getIndex(); 130530ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen unsigned PCLabelId = duplicateCPV(MF, CPI); 1306fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng MachineInstrBuilder MIB = BuildMI(MBB, I, Orig->getDebugLoc(), get(Opcode), 1307fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng DestReg) 1308fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng .addConstantPoolIndex(CPI).addImm(PCLabelId); 1309d7d030a44796adc73a6eaa939cd17e52047734c1Chris Lattner MIB->setMemRefs(Orig->memoperands_begin(), Orig->memoperands_end()); 1310fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng break; 1311fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng } 1312fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng } 1313fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng} 1314fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng 131530ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund OlesenMachineInstr * 131630ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund OlesenARMBaseInstrInfo::duplicate(MachineInstr *Orig, MachineFunction &MF) const { 1317a9fa4fd9736f7d1066223f32fa54efbe86c0fcebJakob Stoklund Olesen MachineInstr *MI = TargetInstrInfo::duplicate(Orig, MF); 131830ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen switch(Orig->getOpcode()) { 131930ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen case ARM::tLDRpci_pic: 132030ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen case ARM::t2LDRpci_pic: { 132130ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen unsigned CPI = Orig->getOperand(1).getIndex(); 132230ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen unsigned PCLabelId = duplicateCPV(MF, CPI); 132330ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen Orig->getOperand(1).setIndex(CPI); 132430ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen Orig->getOperand(2).setImm(PCLabelId); 132530ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen break; 132630ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen } 132730ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen } 132830ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen return MI; 132930ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen} 133030ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen 1331506049f29f4f202a8e45feb916cc0264440a7f6dEvan Chengbool ARMBaseInstrInfo::produceSameValue(const MachineInstr *MI0, 13329fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng const MachineInstr *MI1, 13339fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng const MachineRegisterInfo *MRI) const { 1334d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng int Opcode = MI0->getOpcode(); 1335d7e3cc840b81b0438e47f05d9664137a198876dfEvan Cheng if (Opcode == ARM::t2LDRpci || 13369b82425cb0105fd5704f6b9bcd5e7693b05b1759Evan Cheng Opcode == ARM::t2LDRpci_pic || 13379b82425cb0105fd5704f6b9bcd5e7693b05b1759Evan Cheng Opcode == ARM::tLDRpci || 13389fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng Opcode == ARM::tLDRpci_pic || 133936b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines Opcode == ARM::LDRLIT_ga_pcrel || 134036b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines Opcode == ARM::LDRLIT_ga_pcrel_ldr || 134136b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines Opcode == ARM::tLDRLIT_ga_pcrel || 134253519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng Opcode == ARM::MOV_ga_pcrel || 134353519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng Opcode == ARM::MOV_ga_pcrel_ldr || 134453519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng Opcode == ARM::t2MOV_ga_pcrel) { 1345d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng if (MI1->getOpcode() != Opcode) 1346d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng return false; 1347d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng if (MI0->getNumOperands() != MI1->getNumOperands()) 1348d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng return false; 1349d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng 1350d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng const MachineOperand &MO0 = MI0->getOperand(1); 1351d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng const MachineOperand &MO1 = MI1->getOperand(1); 1352d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng if (MO0.getOffset() != MO1.getOffset()) 1353d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng return false; 1354d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng 135536b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines if (Opcode == ARM::LDRLIT_ga_pcrel || 135636b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines Opcode == ARM::LDRLIT_ga_pcrel_ldr || 135736b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines Opcode == ARM::tLDRLIT_ga_pcrel || 135853519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng Opcode == ARM::MOV_ga_pcrel || 135953519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng Opcode == ARM::MOV_ga_pcrel_ldr || 136053519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng Opcode == ARM::t2MOV_ga_pcrel) 13619fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng // Ignore the PC labels. 13629fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng return MO0.getGlobal() == MO1.getGlobal(); 13639fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng 1364d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng const MachineFunction *MF = MI0->getParent()->getParent(); 1365d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng const MachineConstantPool *MCP = MF->getConstantPool(); 1366d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng int CPI0 = MO0.getIndex(); 1367d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng int CPI1 = MO1.getIndex(); 1368d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng const MachineConstantPoolEntry &MCPE0 = MCP->getConstants()[CPI0]; 1369d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng const MachineConstantPoolEntry &MCPE1 = MCP->getConstants()[CPI1]; 1370d700617193f3d11deb83cd56c4ababbc8e0ea19fEvan Cheng bool isARMCP0 = MCPE0.isMachineConstantPoolEntry(); 1371d700617193f3d11deb83cd56c4ababbc8e0ea19fEvan Cheng bool isARMCP1 = MCPE1.isMachineConstantPoolEntry(); 1372d700617193f3d11deb83cd56c4ababbc8e0ea19fEvan Cheng if (isARMCP0 && isARMCP1) { 1373d700617193f3d11deb83cd56c4ababbc8e0ea19fEvan Cheng ARMConstantPoolValue *ACPV0 = 1374d700617193f3d11deb83cd56c4ababbc8e0ea19fEvan Cheng static_cast<ARMConstantPoolValue*>(MCPE0.Val.MachineCPVal); 1375d700617193f3d11deb83cd56c4ababbc8e0ea19fEvan Cheng ARMConstantPoolValue *ACPV1 = 1376d700617193f3d11deb83cd56c4ababbc8e0ea19fEvan Cheng static_cast<ARMConstantPoolValue*>(MCPE1.Val.MachineCPVal); 1377d700617193f3d11deb83cd56c4ababbc8e0ea19fEvan Cheng return ACPV0->hasSameValue(ACPV1); 1378d700617193f3d11deb83cd56c4ababbc8e0ea19fEvan Cheng } else if (!isARMCP0 && !isARMCP1) { 1379d700617193f3d11deb83cd56c4ababbc8e0ea19fEvan Cheng return MCPE0.Val.ConstVal == MCPE1.Val.ConstVal; 1380d700617193f3d11deb83cd56c4ababbc8e0ea19fEvan Cheng } 1381d700617193f3d11deb83cd56c4ababbc8e0ea19fEvan Cheng return false; 13829fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng } else if (Opcode == ARM::PICLDR) { 13839fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng if (MI1->getOpcode() != Opcode) 13849fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng return false; 13859fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng if (MI0->getNumOperands() != MI1->getNumOperands()) 13869fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng return false; 13879fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng 13889fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng unsigned Addr0 = MI0->getOperand(1).getReg(); 13899fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng unsigned Addr1 = MI1->getOperand(1).getReg(); 13909fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng if (Addr0 != Addr1) { 13919fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng if (!MRI || 13929fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng !TargetRegisterInfo::isVirtualRegister(Addr0) || 13939fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng !TargetRegisterInfo::isVirtualRegister(Addr1)) 13949fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng return false; 13959fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng 13969fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng // This assumes SSA form. 13979fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng MachineInstr *Def0 = MRI->getVRegDef(Addr0); 13989fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng MachineInstr *Def1 = MRI->getVRegDef(Addr1); 13999fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng // Check if the loaded value, e.g. a constantpool of a global address, are 14009fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng // the same. 14019fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng if (!produceSameValue(Def0, Def1, MRI)) 14029fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng return false; 14039fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng } 14049fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng 14059fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng for (unsigned i = 3, e = MI0->getNumOperands(); i != e; ++i) { 14069fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng // %vreg12<def> = PICLDR %vreg11, 0, pred:14, pred:%noreg 14079fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng const MachineOperand &MO0 = MI0->getOperand(i); 14089fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng const MachineOperand &MO1 = MI1->getOperand(i); 14099fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng if (!MO0.isIdenticalTo(MO1)) 14109fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng return false; 14119fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng } 14129fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng return true; 1413d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng } 1414d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng 1415506049f29f4f202a8e45feb916cc0264440a7f6dEvan Cheng return MI0->isIdenticalTo(MI1, MachineInstr::IgnoreVRegDefs); 1416d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng} 1417d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng 14184b722108e2cf8e77157e0879a23789cd44829933Bill Wendling/// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to 14194b722108e2cf8e77157e0879a23789cd44829933Bill Wendling/// determine if two loads are loading from the same base address. It should 14204b722108e2cf8e77157e0879a23789cd44829933Bill Wendling/// only return true if the base pointers are the same and the only differences 14214b722108e2cf8e77157e0879a23789cd44829933Bill Wendling/// between the two addresses is the offset. It also returns the offsets by 14224b722108e2cf8e77157e0879a23789cd44829933Bill Wendling/// reference. 14239b5caaa9c452f262a52dd5ac7ebbc722da5a63deAndrew Trick/// 14249b5caaa9c452f262a52dd5ac7ebbc722da5a63deAndrew Trick/// FIXME: remove this in favor of the MachineInstr interface once pre-RA-sched 14259b5caaa9c452f262a52dd5ac7ebbc722da5a63deAndrew Trick/// is permanently disabled. 14264b722108e2cf8e77157e0879a23789cd44829933Bill Wendlingbool ARMBaseInstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, 14274b722108e2cf8e77157e0879a23789cd44829933Bill Wendling int64_t &Offset1, 14284b722108e2cf8e77157e0879a23789cd44829933Bill Wendling int64_t &Offset2) const { 14294b722108e2cf8e77157e0879a23789cd44829933Bill Wendling // Don't worry about Thumb: just ARM and Thumb2. 14304b722108e2cf8e77157e0879a23789cd44829933Bill Wendling if (Subtarget.isThumb1Only()) return false; 14314b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 14324b722108e2cf8e77157e0879a23789cd44829933Bill Wendling if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode()) 14334b722108e2cf8e77157e0879a23789cd44829933Bill Wendling return false; 14344b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 14354b722108e2cf8e77157e0879a23789cd44829933Bill Wendling switch (Load1->getMachineOpcode()) { 14364b722108e2cf8e77157e0879a23789cd44829933Bill Wendling default: 14374b722108e2cf8e77157e0879a23789cd44829933Bill Wendling return false; 14383e5561247202bae994dd259a2d8dc4eff8f799f3Jim Grosbach case ARM::LDRi12: 1439c1d30212e911d1e55ff6b25bffefb503708883c3Jim Grosbach case ARM::LDRBi12: 14404b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::LDRD: 14414b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::LDRH: 14424b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::LDRSB: 14434b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::LDRSH: 14444b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::VLDRD: 14454b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::VLDRS: 14464b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::t2LDRi8: 1447dd34dc99fdf66edc52b5fc2ddf8132ebaa134aeeRenato Golin case ARM::t2LDRBi8: 14484b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::t2LDRDi8: 14494b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::t2LDRSHi8: 14504b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::t2LDRi12: 1451dd34dc99fdf66edc52b5fc2ddf8132ebaa134aeeRenato Golin case ARM::t2LDRBi12: 14524b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::t2LDRSHi12: 14534b722108e2cf8e77157e0879a23789cd44829933Bill Wendling break; 14544b722108e2cf8e77157e0879a23789cd44829933Bill Wendling } 14554b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 14564b722108e2cf8e77157e0879a23789cd44829933Bill Wendling switch (Load2->getMachineOpcode()) { 14574b722108e2cf8e77157e0879a23789cd44829933Bill Wendling default: 14584b722108e2cf8e77157e0879a23789cd44829933Bill Wendling return false; 14593e5561247202bae994dd259a2d8dc4eff8f799f3Jim Grosbach case ARM::LDRi12: 1460c1d30212e911d1e55ff6b25bffefb503708883c3Jim Grosbach case ARM::LDRBi12: 14614b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::LDRD: 14624b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::LDRH: 14634b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::LDRSB: 14644b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::LDRSH: 14654b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::VLDRD: 14664b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::VLDRS: 14674b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::t2LDRi8: 1468dd34dc99fdf66edc52b5fc2ddf8132ebaa134aeeRenato Golin case ARM::t2LDRBi8: 14694b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::t2LDRSHi8: 14704b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::t2LDRi12: 1471dd34dc99fdf66edc52b5fc2ddf8132ebaa134aeeRenato Golin case ARM::t2LDRBi12: 14724b722108e2cf8e77157e0879a23789cd44829933Bill Wendling case ARM::t2LDRSHi12: 14734b722108e2cf8e77157e0879a23789cd44829933Bill Wendling break; 14744b722108e2cf8e77157e0879a23789cd44829933Bill Wendling } 14754b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 14764b722108e2cf8e77157e0879a23789cd44829933Bill Wendling // Check if base addresses and chain operands match. 14774b722108e2cf8e77157e0879a23789cd44829933Bill Wendling if (Load1->getOperand(0) != Load2->getOperand(0) || 14784b722108e2cf8e77157e0879a23789cd44829933Bill Wendling Load1->getOperand(4) != Load2->getOperand(4)) 14794b722108e2cf8e77157e0879a23789cd44829933Bill Wendling return false; 14804b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 14814b722108e2cf8e77157e0879a23789cd44829933Bill Wendling // Index should be Reg0. 14824b722108e2cf8e77157e0879a23789cd44829933Bill Wendling if (Load1->getOperand(3) != Load2->getOperand(3)) 14834b722108e2cf8e77157e0879a23789cd44829933Bill Wendling return false; 14844b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 14854b722108e2cf8e77157e0879a23789cd44829933Bill Wendling // Determine the offsets. 14864b722108e2cf8e77157e0879a23789cd44829933Bill Wendling if (isa<ConstantSDNode>(Load1->getOperand(1)) && 14874b722108e2cf8e77157e0879a23789cd44829933Bill Wendling isa<ConstantSDNode>(Load2->getOperand(1))) { 14884b722108e2cf8e77157e0879a23789cd44829933Bill Wendling Offset1 = cast<ConstantSDNode>(Load1->getOperand(1))->getSExtValue(); 14894b722108e2cf8e77157e0879a23789cd44829933Bill Wendling Offset2 = cast<ConstantSDNode>(Load2->getOperand(1))->getSExtValue(); 14904b722108e2cf8e77157e0879a23789cd44829933Bill Wendling return true; 14914b722108e2cf8e77157e0879a23789cd44829933Bill Wendling } 14924b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 14934b722108e2cf8e77157e0879a23789cd44829933Bill Wendling return false; 14944b722108e2cf8e77157e0879a23789cd44829933Bill Wendling} 14954b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 14964b722108e2cf8e77157e0879a23789cd44829933Bill Wendling/// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to 14977a2bdde0a0eebcd2125055e0eacaca040f0b766cChris Lattner/// determine (in conjunction with areLoadsFromSameBasePtr) if two loads should 14984b722108e2cf8e77157e0879a23789cd44829933Bill Wendling/// be scheduled togther. On some targets if two loads are loading from 14994b722108e2cf8e77157e0879a23789cd44829933Bill Wendling/// addresses in the same cache line, it's better if they are scheduled 15004b722108e2cf8e77157e0879a23789cd44829933Bill Wendling/// together. This function takes two integers that represent the load offsets 15014b722108e2cf8e77157e0879a23789cd44829933Bill Wendling/// from the common base address. It returns true if it decides it's desirable 15024b722108e2cf8e77157e0879a23789cd44829933Bill Wendling/// to schedule the two loads together. "NumLoads" is the number of loads that 15034b722108e2cf8e77157e0879a23789cd44829933Bill Wendling/// have already been scheduled after Load1. 15049b5caaa9c452f262a52dd5ac7ebbc722da5a63deAndrew Trick/// 15059b5caaa9c452f262a52dd5ac7ebbc722da5a63deAndrew Trick/// FIXME: remove this in favor of the MachineInstr interface once pre-RA-sched 15069b5caaa9c452f262a52dd5ac7ebbc722da5a63deAndrew Trick/// is permanently disabled. 15074b722108e2cf8e77157e0879a23789cd44829933Bill Wendlingbool ARMBaseInstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, 15084b722108e2cf8e77157e0879a23789cd44829933Bill Wendling int64_t Offset1, int64_t Offset2, 15094b722108e2cf8e77157e0879a23789cd44829933Bill Wendling unsigned NumLoads) const { 15104b722108e2cf8e77157e0879a23789cd44829933Bill Wendling // Don't worry about Thumb: just ARM and Thumb2. 15114b722108e2cf8e77157e0879a23789cd44829933Bill Wendling if (Subtarget.isThumb1Only()) return false; 15124b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 15134b722108e2cf8e77157e0879a23789cd44829933Bill Wendling assert(Offset2 > Offset1); 15144b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 15154b722108e2cf8e77157e0879a23789cd44829933Bill Wendling if ((Offset2 - Offset1) / 8 > 64) 15164b722108e2cf8e77157e0879a23789cd44829933Bill Wendling return false; 15174b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 1518dd34dc99fdf66edc52b5fc2ddf8132ebaa134aeeRenato Golin // Check if the machine opcodes are different. If they are different 1519dd34dc99fdf66edc52b5fc2ddf8132ebaa134aeeRenato Golin // then we consider them to not be of the same base address, 1520dd34dc99fdf66edc52b5fc2ddf8132ebaa134aeeRenato Golin // EXCEPT in the case of Thumb2 byte loads where one is LDRBi8 and the other LDRBi12. 1521dd34dc99fdf66edc52b5fc2ddf8132ebaa134aeeRenato Golin // In this case, they are considered to be the same because they are different 1522dd34dc99fdf66edc52b5fc2ddf8132ebaa134aeeRenato Golin // encoding forms of the same basic instruction. 1523dd34dc99fdf66edc52b5fc2ddf8132ebaa134aeeRenato Golin if ((Load1->getMachineOpcode() != Load2->getMachineOpcode()) && 1524dd34dc99fdf66edc52b5fc2ddf8132ebaa134aeeRenato Golin !((Load1->getMachineOpcode() == ARM::t2LDRBi8 && 1525dd34dc99fdf66edc52b5fc2ddf8132ebaa134aeeRenato Golin Load2->getMachineOpcode() == ARM::t2LDRBi12) || 1526dd34dc99fdf66edc52b5fc2ddf8132ebaa134aeeRenato Golin (Load1->getMachineOpcode() == ARM::t2LDRBi12 && 1527dd34dc99fdf66edc52b5fc2ddf8132ebaa134aeeRenato Golin Load2->getMachineOpcode() == ARM::t2LDRBi8))) 15284b722108e2cf8e77157e0879a23789cd44829933Bill Wendling return false; // FIXME: overly conservative? 15294b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 15304b722108e2cf8e77157e0879a23789cd44829933Bill Wendling // Four loads in a row should be sufficient. 15314b722108e2cf8e77157e0879a23789cd44829933Bill Wendling if (NumLoads >= 3) 15324b722108e2cf8e77157e0879a23789cd44829933Bill Wendling return false; 15334b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 15344b722108e2cf8e77157e0879a23789cd44829933Bill Wendling return true; 15354b722108e2cf8e77157e0879a23789cd44829933Bill Wendling} 15364b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 153786050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Chengbool ARMBaseInstrInfo::isSchedulingBoundary(const MachineInstr *MI, 153886050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng const MachineBasicBlock *MBB, 153986050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng const MachineFunction &MF) const { 154057bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach // Debug info is never a scheduling boundary. It's necessary to be explicit 154157bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach // due to the special treatment of IT instructions below, otherwise a 154257bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach // dbg_value followed by an IT will result in the IT instruction being 154357bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach // considered a scheduling hazard, which is wrong. It should be the actual 154457bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach // instruction preceding the dbg_value instruction(s), just like it is 154557bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach // when debug info is not present. 154657bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach if (MI->isDebugValue()) 154757bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach return false; 154857bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach 154986050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // Terminators and labels can't be scheduled around. 155036b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines if (MI->isTerminator() || MI->isPosition()) 155186050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng return true; 155286050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng 155386050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // Treat the start of the IT block as a scheduling boundary, but schedule 155486050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // t2IT along with all instructions following it. 155586050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // FIXME: This is a big hammer. But the alternative is to add all potential 155686050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // true and anti dependencies to IT block instructions as implicit operands 155786050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // to the t2IT instruction. The added compile time and complexity does not 155886050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // seem worth it. 155986050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng MachineBasicBlock::const_iterator I = MI; 156057bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach // Make sure to skip any dbg_value instructions 156157bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach while (++I != MBB->end() && I->isDebugValue()) 156257bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach ; 156357bb3948034436a458f5ef857eb2e831a47e7401Jim Grosbach if (I != MBB->end() && I->getOpcode() == ARM::t2IT) 156486050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng return true; 156586050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng 156686050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // Don't attempt to schedule around any instruction that defines 156786050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // a stack-oriented pointer, as it's unlikely to be profitable. This 156886050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // saves compile time, because it doesn't require every single 156986050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // stack slot reference to depend on the instruction that does the 157086050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // modification. 1571a1aa8db51715bdd21770fbe4f7d7abf2c5d28829Jakob Stoklund Olesen // Calls don't actually change the stack pointer, even if they have imp-defs. 1572209600bb8830036f981238494ab0188c25364837Jakob Stoklund Olesen // No ARM calling conventions change the stack pointer. (X86 calling 1573209600bb8830036f981238494ab0188c25364837Jakob Stoklund Olesen // conventions sometimes do). 1574a1aa8db51715bdd21770fbe4f7d7abf2c5d28829Jakob Stoklund Olesen if (!MI->isCall() && MI->definesRegister(ARM::SP)) 157586050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng return true; 157686050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng 157786050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng return false; 157886050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng} 157986050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng 1580f81b7f6069b27c0a515070dcb392f6828437412fJakub Staszakbool ARMBaseInstrInfo:: 1581f81b7f6069b27c0a515070dcb392f6828437412fJakub StaszakisProfitableToIfCvt(MachineBasicBlock &MBB, 1582f81b7f6069b27c0a515070dcb392f6828437412fJakub Staszak unsigned NumCycles, unsigned ExtraPredCycles, 1583f81b7f6069b27c0a515070dcb392f6828437412fJakub Staszak const BranchProbability &Probability) const { 15845876db7a66fcc4ec4444a9f3e387c1cdc8baf9e5Cameron Zwarich if (!NumCycles) 158513151432edace19ee867a93b5c14573df4f75d24Evan Cheng return false; 15862bbb76909126db5bed6bde84b16d94ab5de4d372Michael J. Spencer 1587b20b85168c0e9819e6545f08281e9b83c82108f0Owen Anderson // Attempt to estimate the relative costs of predication versus branching. 1588f81b7f6069b27c0a515070dcb392f6828437412fJakub Staszak unsigned UnpredCost = Probability.getNumerator() * NumCycles; 1589f81b7f6069b27c0a515070dcb392f6828437412fJakub Staszak UnpredCost /= Probability.getDenominator(); 1590f81b7f6069b27c0a515070dcb392f6828437412fJakub Staszak UnpredCost += 1; // The branch itself 1591f81b7f6069b27c0a515070dcb392f6828437412fJakub Staszak UnpredCost += Subtarget.getMispredictionPenalty() / 10; 15922bbb76909126db5bed6bde84b16d94ab5de4d372Michael J. Spencer 1593f81b7f6069b27c0a515070dcb392f6828437412fJakub Staszak return (NumCycles + ExtraPredCycles) <= UnpredCost; 159413151432edace19ee867a93b5c14573df4f75d24Evan Cheng} 15952bbb76909126db5bed6bde84b16d94ab5de4d372Michael J. Spencer 159613151432edace19ee867a93b5c14573df4f75d24Evan Chengbool ARMBaseInstrInfo:: 15978239daf7c83a65a189c352cce3191cdc3bbfe151Evan ChengisProfitableToIfCvt(MachineBasicBlock &TMBB, 15988239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng unsigned TCycles, unsigned TExtra, 15998239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng MachineBasicBlock &FMBB, 16008239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng unsigned FCycles, unsigned FExtra, 1601f81b7f6069b27c0a515070dcb392f6828437412fJakub Staszak const BranchProbability &Probability) const { 16028239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng if (!TCycles || !FCycles) 1603b20b85168c0e9819e6545f08281e9b83c82108f0Owen Anderson return false; 16042bbb76909126db5bed6bde84b16d94ab5de4d372Michael J. Spencer 1605b20b85168c0e9819e6545f08281e9b83c82108f0Owen Anderson // Attempt to estimate the relative costs of predication versus branching. 1606f81b7f6069b27c0a515070dcb392f6828437412fJakub Staszak unsigned TUnpredCost = Probability.getNumerator() * TCycles; 1607f81b7f6069b27c0a515070dcb392f6828437412fJakub Staszak TUnpredCost /= Probability.getDenominator(); 1608e23dc9c0ef50b0a1934c04c1786f3a0478d62f41Andrew Trick 1609f81b7f6069b27c0a515070dcb392f6828437412fJakub Staszak uint32_t Comp = Probability.getDenominator() - Probability.getNumerator(); 1610f81b7f6069b27c0a515070dcb392f6828437412fJakub Staszak unsigned FUnpredCost = Comp * FCycles; 1611f81b7f6069b27c0a515070dcb392f6828437412fJakub Staszak FUnpredCost /= Probability.getDenominator(); 1612f81b7f6069b27c0a515070dcb392f6828437412fJakub Staszak 1613f81b7f6069b27c0a515070dcb392f6828437412fJakub Staszak unsigned UnpredCost = TUnpredCost + FUnpredCost; 1614f81b7f6069b27c0a515070dcb392f6828437412fJakub Staszak UnpredCost += 1; // The branch itself 1615f81b7f6069b27c0a515070dcb392f6828437412fJakub Staszak UnpredCost += Subtarget.getMispredictionPenalty() / 10; 1616f81b7f6069b27c0a515070dcb392f6828437412fJakub Staszak 1617f81b7f6069b27c0a515070dcb392f6828437412fJakub Staszak return (TCycles + FCycles + TExtra + FExtra) <= UnpredCost; 161813151432edace19ee867a93b5c14573df4f75d24Evan Cheng} 161913151432edace19ee867a93b5c14573df4f75d24Evan Cheng 1620eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilsonbool 1621eb1641d54a7eda7717304bc4d55d059208d8ebedBob WilsonARMBaseInstrInfo::isProfitableToUnpredicate(MachineBasicBlock &TMBB, 1622eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson MachineBasicBlock &FMBB) const { 1623eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson // Reduce false anti-dependencies to let Swift's out-of-order execution 1624eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson // engine do its thing. 1625eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson return Subtarget.isSwift(); 1626eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson} 1627eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson 16288fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng/// getInstrPredicate - If instruction is predicated, returns its predicate 16298fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng/// condition, otherwise returns AL. It also returns the condition code 16308fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng/// register by reference. 16315adb66a646e2ec32265263739f5b01c3f50c176aEvan ChengARMCC::CondCodes 16325adb66a646e2ec32265263739f5b01c3f50c176aEvan Chengllvm::getInstrPredicate(const MachineInstr *MI, unsigned &PredReg) { 16338fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng int PIdx = MI->findFirstPredOperandIdx(); 16348fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng if (PIdx == -1) { 16358fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng PredReg = 0; 16368fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng return ARMCC::AL; 16378fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng } 16388fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng 16398fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng PredReg = MI->getOperand(PIdx+1).getReg(); 16408fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng return (ARMCC::CondCodes)MI->getOperand(PIdx).getImm(); 16418fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng} 16428fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng 16438fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng 16446495f63945e8dbde81f03a1dc2ab421993b9a495Evan Chengint llvm::getMatchingCondBranchOpcode(int Opc) { 16455ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng if (Opc == ARM::B) 16465ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng return ARM::Bcc; 16474d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie if (Opc == ARM::tB) 16485ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng return ARM::tBcc; 16494d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie if (Opc == ARM::t2B) 16504d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie return ARM::t2Bcc; 16515ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng 16525ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng llvm_unreachable("Unknown unconditional branch opcode!"); 16535ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng} 16545ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng 1655c5041cac7d3aeaa7350abadf2a7ada92e8da27dcJakob Stoklund Olesen/// commuteInstruction - Handle commutable instructions. 1656c5041cac7d3aeaa7350abadf2a7ada92e8da27dcJakob Stoklund OlesenMachineInstr * 1657c5041cac7d3aeaa7350abadf2a7ada92e8da27dcJakob Stoklund OlesenARMBaseInstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const { 1658c5041cac7d3aeaa7350abadf2a7ada92e8da27dcJakob Stoklund Olesen switch (MI->getOpcode()) { 1659c5041cac7d3aeaa7350abadf2a7ada92e8da27dcJakob Stoklund Olesen case ARM::MOVCCr: 1660c5041cac7d3aeaa7350abadf2a7ada92e8da27dcJakob Stoklund Olesen case ARM::t2MOVCCr: { 1661c5041cac7d3aeaa7350abadf2a7ada92e8da27dcJakob Stoklund Olesen // MOVCC can be commuted by inverting the condition. 1662c5041cac7d3aeaa7350abadf2a7ada92e8da27dcJakob Stoklund Olesen unsigned PredReg = 0; 1663c5041cac7d3aeaa7350abadf2a7ada92e8da27dcJakob Stoklund Olesen ARMCC::CondCodes CC = getInstrPredicate(MI, PredReg); 1664c5041cac7d3aeaa7350abadf2a7ada92e8da27dcJakob Stoklund Olesen // MOVCC AL can't be inverted. Shouldn't happen. 1665c5041cac7d3aeaa7350abadf2a7ada92e8da27dcJakob Stoklund Olesen if (CC == ARMCC::AL || PredReg != ARM::CPSR) 1666dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines return nullptr; 1667a9fa4fd9736f7d1066223f32fa54efbe86c0fcebJakob Stoklund Olesen MI = TargetInstrInfo::commuteInstruction(MI, NewMI); 1668c5041cac7d3aeaa7350abadf2a7ada92e8da27dcJakob Stoklund Olesen if (!MI) 1669dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines return nullptr; 1670c5041cac7d3aeaa7350abadf2a7ada92e8da27dcJakob Stoklund Olesen // After swapping the MOVCC operands, also invert the condition. 1671c5041cac7d3aeaa7350abadf2a7ada92e8da27dcJakob Stoklund Olesen MI->getOperand(MI->findFirstPredOperandIdx()) 1672c5041cac7d3aeaa7350abadf2a7ada92e8da27dcJakob Stoklund Olesen .setImm(ARMCC::getOppositeCondition(CC)); 1673c5041cac7d3aeaa7350abadf2a7ada92e8da27dcJakob Stoklund Olesen return MI; 1674c5041cac7d3aeaa7350abadf2a7ada92e8da27dcJakob Stoklund Olesen } 1675c5041cac7d3aeaa7350abadf2a7ada92e8da27dcJakob Stoklund Olesen } 1676a9fa4fd9736f7d1066223f32fa54efbe86c0fcebJakob Stoklund Olesen return TargetInstrInfo::commuteInstruction(MI, NewMI); 1677c5041cac7d3aeaa7350abadf2a7ada92e8da27dcJakob Stoklund Olesen} 16786495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 16792860b7ea3a1d60213ee7228bd274bc4f8b170772Jakob Stoklund Olesen/// Identify instructions that can be folded into a MOVCC instruction, and 1680098c6a547fe540b3bbace4c3d4713f400c67b8a9Jakob Stoklund Olesen/// return the defining instruction. 1681098c6a547fe540b3bbace4c3d4713f400c67b8a9Jakob Stoklund Olesenstatic MachineInstr *canFoldIntoMOVCC(unsigned Reg, 1682098c6a547fe540b3bbace4c3d4713f400c67b8a9Jakob Stoklund Olesen const MachineRegisterInfo &MRI, 1683098c6a547fe540b3bbace4c3d4713f400c67b8a9Jakob Stoklund Olesen const TargetInstrInfo *TII) { 16842860b7ea3a1d60213ee7228bd274bc4f8b170772Jakob Stoklund Olesen if (!TargetRegisterInfo::isVirtualRegister(Reg)) 1685dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines return nullptr; 16862860b7ea3a1d60213ee7228bd274bc4f8b170772Jakob Stoklund Olesen if (!MRI.hasOneNonDBGUse(Reg)) 1687dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines return nullptr; 1688098c6a547fe540b3bbace4c3d4713f400c67b8a9Jakob Stoklund Olesen MachineInstr *MI = MRI.getVRegDef(Reg); 16892860b7ea3a1d60213ee7228bd274bc4f8b170772Jakob Stoklund Olesen if (!MI) 1690dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines return nullptr; 1691098c6a547fe540b3bbace4c3d4713f400c67b8a9Jakob Stoklund Olesen // MI is folded into the MOVCC by predicating it. 1692098c6a547fe540b3bbace4c3d4713f400c67b8a9Jakob Stoklund Olesen if (!MI->isPredicable()) 1693dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines return nullptr; 16942860b7ea3a1d60213ee7228bd274bc4f8b170772Jakob Stoklund Olesen // Check if MI has any non-dead defs or physreg uses. This also detects 16952860b7ea3a1d60213ee7228bd274bc4f8b170772Jakob Stoklund Olesen // predicated instructions which will be reading CPSR. 16962860b7ea3a1d60213ee7228bd274bc4f8b170772Jakob Stoklund Olesen for (unsigned i = 1, e = MI->getNumOperands(); i != e; ++i) { 16972860b7ea3a1d60213ee7228bd274bc4f8b170772Jakob Stoklund Olesen const MachineOperand &MO = MI->getOperand(i); 1698a7fb3f68047556a7355e1f1080fb3d1ca9eb7078Jakob Stoklund Olesen // Reject frame index operands, PEI can't handle the predicated pseudos. 1699a7fb3f68047556a7355e1f1080fb3d1ca9eb7078Jakob Stoklund Olesen if (MO.isFI() || MO.isCPI() || MO.isJTI()) 1700dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines return nullptr; 17012860b7ea3a1d60213ee7228bd274bc4f8b170772Jakob Stoklund Olesen if (!MO.isReg()) 17022860b7ea3a1d60213ee7228bd274bc4f8b170772Jakob Stoklund Olesen continue; 1703098c6a547fe540b3bbace4c3d4713f400c67b8a9Jakob Stoklund Olesen // MI can't have any tied operands, that would conflict with predication. 1704098c6a547fe540b3bbace4c3d4713f400c67b8a9Jakob Stoklund Olesen if (MO.isTied()) 1705dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines return nullptr; 17062860b7ea3a1d60213ee7228bd274bc4f8b170772Jakob Stoklund Olesen if (TargetRegisterInfo::isPhysicalRegister(MO.getReg())) 1707dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines return nullptr; 17082860b7ea3a1d60213ee7228bd274bc4f8b170772Jakob Stoklund Olesen if (MO.isDef() && !MO.isDead()) 1709dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines return nullptr; 17102860b7ea3a1d60213ee7228bd274bc4f8b170772Jakob Stoklund Olesen } 1711098c6a547fe540b3bbace4c3d4713f400c67b8a9Jakob Stoklund Olesen bool DontMoveAcrossStores = true; 1712dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines if (!MI->isSafeToMove(TII, /* AliasAnalysis = */ nullptr, 1713dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines DontMoveAcrossStores)) 1714dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines return nullptr; 1715098c6a547fe540b3bbace4c3d4713f400c67b8a9Jakob Stoklund Olesen return MI; 17162860b7ea3a1d60213ee7228bd274bc4f8b170772Jakob Stoklund Olesen} 17172860b7ea3a1d60213ee7228bd274bc4f8b170772Jakob Stoklund Olesen 1718053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesenbool ARMBaseInstrInfo::analyzeSelect(const MachineInstr *MI, 1719053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen SmallVectorImpl<MachineOperand> &Cond, 1720053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen unsigned &TrueOp, unsigned &FalseOp, 1721053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen bool &Optimizable) const { 1722053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen assert((MI->getOpcode() == ARM::MOVCCr || MI->getOpcode() == ARM::t2MOVCCr) && 1723053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen "Unknown select instruction"); 1724053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen // MOVCC operands: 1725053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen // 0: Def. 1726053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen // 1: True use. 1727053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen // 2: False use. 1728053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen // 3: Condition code. 1729053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen // 4: CPSR use. 1730053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen TrueOp = 1; 1731053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen FalseOp = 2; 1732053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen Cond.push_back(MI->getOperand(3)); 1733053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen Cond.push_back(MI->getOperand(4)); 1734053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen // We can always fold a def. 1735053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen Optimizable = true; 1736053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen return false; 1737053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen} 1738053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen 1739053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund OlesenMachineInstr *ARMBaseInstrInfo::optimizeSelect(MachineInstr *MI, 1740053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen bool PreferFalse) const { 1741053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen assert((MI->getOpcode() == ARM::MOVCCr || MI->getOpcode() == ARM::t2MOVCCr) && 1742053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen "Unknown select instruction"); 1743d1bd8d904c5adbe14f700be02f1e6479b5a6d04bMatthias Braun MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo(); 1744098c6a547fe540b3bbace4c3d4713f400c67b8a9Jakob Stoklund Olesen MachineInstr *DefMI = canFoldIntoMOVCC(MI->getOperand(2).getReg(), MRI, this); 1745098c6a547fe540b3bbace4c3d4713f400c67b8a9Jakob Stoklund Olesen bool Invert = !DefMI; 1746098c6a547fe540b3bbace4c3d4713f400c67b8a9Jakob Stoklund Olesen if (!DefMI) 1747098c6a547fe540b3bbace4c3d4713f400c67b8a9Jakob Stoklund Olesen DefMI = canFoldIntoMOVCC(MI->getOperand(1).getReg(), MRI, this); 1748098c6a547fe540b3bbace4c3d4713f400c67b8a9Jakob Stoklund Olesen if (!DefMI) 1749dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines return nullptr; 1750053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen 1751d1bd8d904c5adbe14f700be02f1e6479b5a6d04bMatthias Braun // Find new register class to use. 1752d1bd8d904c5adbe14f700be02f1e6479b5a6d04bMatthias Braun MachineOperand FalseReg = MI->getOperand(Invert ? 2 : 1); 1753d1bd8d904c5adbe14f700be02f1e6479b5a6d04bMatthias Braun unsigned DestReg = MI->getOperand(0).getReg(); 1754d1bd8d904c5adbe14f700be02f1e6479b5a6d04bMatthias Braun const TargetRegisterClass *PreviousClass = MRI.getRegClass(FalseReg.getReg()); 1755d1bd8d904c5adbe14f700be02f1e6479b5a6d04bMatthias Braun if (!MRI.constrainRegClass(DestReg, PreviousClass)) 1756dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines return nullptr; 1757d1bd8d904c5adbe14f700be02f1e6479b5a6d04bMatthias Braun 1758053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen // Create a new predicated version of DefMI. 1759053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen // Rfalse is the first use. 1760053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen MachineInstrBuilder NewMI = BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), 1761d1bd8d904c5adbe14f700be02f1e6479b5a6d04bMatthias Braun DefMI->getDesc(), DestReg); 1762053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen 1763053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen // Copy all the DefMI operands, excluding its (null) predicate. 1764053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen const MCInstrDesc &DefDesc = DefMI->getDesc(); 1765053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen for (unsigned i = 1, e = DefDesc.getNumOperands(); 1766053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen i != e && !DefDesc.OpInfo[i].isPredicate(); ++i) 1767053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen NewMI.addOperand(DefMI->getOperand(i)); 1768053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen 1769053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen unsigned CondCode = MI->getOperand(3).getImm(); 1770053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen if (Invert) 1771053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen NewMI.addImm(ARMCC::getOppositeCondition(ARMCC::CondCodes(CondCode))); 1772053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen else 1773053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen NewMI.addImm(CondCode); 1774053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen NewMI.addOperand(MI->getOperand(4)); 1775053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen 1776053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen // DefMI is not the -S version that sets CPSR, so add an optional %noreg. 1777053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen if (NewMI->hasOptionalDef()) 1778053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen AddDefaultCC(NewMI); 1779053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen 1780098c6a547fe540b3bbace4c3d4713f400c67b8a9Jakob Stoklund Olesen // The output register value when the predicate is false is an implicit 1781098c6a547fe540b3bbace4c3d4713f400c67b8a9Jakob Stoklund Olesen // register operand tied to the first def. 1782098c6a547fe540b3bbace4c3d4713f400c67b8a9Jakob Stoklund Olesen // The tie makes the register allocator ensure the FalseReg is allocated the 1783098c6a547fe540b3bbace4c3d4713f400c67b8a9Jakob Stoklund Olesen // same register as operand 0. 1784098c6a547fe540b3bbace4c3d4713f400c67b8a9Jakob Stoklund Olesen FalseReg.setImplicit(); 1785b9efafe54d61e85ca5209c4043aa814f89785195Jakob Stoklund Olesen NewMI.addOperand(FalseReg); 1786098c6a547fe540b3bbace4c3d4713f400c67b8a9Jakob Stoklund Olesen NewMI->tieOperands(0, NewMI->getNumOperands() - 1); 1787098c6a547fe540b3bbace4c3d4713f400c67b8a9Jakob Stoklund Olesen 1788053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen // The caller will erase MI, but not DefMI. 1789053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen DefMI->eraseFromParent(); 1790053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen return NewMI; 1791053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen} 1792053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen 17933be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick/// Map pseudo instructions that imply an 'S' bit onto real opcodes. Whether the 17943be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick/// instruction is encoded with an 'S' bit is determined by the optional CPSR 17953be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick/// def operand. 17963be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick/// 17973be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick/// This will go away once we can teach tblgen how to set the optional CPSR def 17983be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick/// operand itself. 17993be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trickstruct AddSubFlagsOpcodePair { 1800cd2859eef83708c00330c94f6842499b48d5ed02Craig Topper uint16_t PseudoOpc; 1801cd2859eef83708c00330c94f6842499b48d5ed02Craig Topper uint16_t MachineOpc; 18023be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick}; 18033be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick 1804cd2859eef83708c00330c94f6842499b48d5ed02Craig Topperstatic const AddSubFlagsOpcodePair AddSubFlagsOpcodeMap[] = { 18053be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick {ARM::ADDSri, ARM::ADDri}, 18063be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick {ARM::ADDSrr, ARM::ADDrr}, 18073be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick {ARM::ADDSrsi, ARM::ADDrsi}, 18083be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick {ARM::ADDSrsr, ARM::ADDrsr}, 18093be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick 18103be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick {ARM::SUBSri, ARM::SUBri}, 18113be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick {ARM::SUBSrr, ARM::SUBrr}, 18123be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick {ARM::SUBSrsi, ARM::SUBrsi}, 18133be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick {ARM::SUBSrsr, ARM::SUBrsr}, 18143be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick 18153be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick {ARM::RSBSri, ARM::RSBri}, 18163be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick {ARM::RSBSrsi, ARM::RSBrsi}, 18173be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick {ARM::RSBSrsr, ARM::RSBrsr}, 18183be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick 18193be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick {ARM::t2ADDSri, ARM::t2ADDri}, 18203be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick {ARM::t2ADDSrr, ARM::t2ADDrr}, 18213be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick {ARM::t2ADDSrs, ARM::t2ADDrs}, 18223be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick 18233be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick {ARM::t2SUBSri, ARM::t2SUBri}, 18243be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick {ARM::t2SUBSrr, ARM::t2SUBrr}, 18253be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick {ARM::t2SUBSrs, ARM::t2SUBrs}, 18263be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick 18273be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick {ARM::t2RSBSri, ARM::t2RSBri}, 18283be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick {ARM::t2RSBSrs, ARM::t2RSBrs}, 18293be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick}; 18303be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick 18313be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trickunsigned llvm::convertAddSubFlagsOpcode(unsigned OldOpc) { 1832cd2859eef83708c00330c94f6842499b48d5ed02Craig Topper for (unsigned i = 0, e = array_lengthof(AddSubFlagsOpcodeMap); i != e; ++i) 1833cd2859eef83708c00330c94f6842499b48d5ed02Craig Topper if (OldOpc == AddSubFlagsOpcodeMap[i].PseudoOpc) 1834cd2859eef83708c00330c94f6842499b48d5ed02Craig Topper return AddSubFlagsOpcodeMap[i].MachineOpc; 18353be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick return 0; 18363be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick} 18373be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick 18386495f63945e8dbde81f03a1dc2ab421993b9a495Evan Chengvoid llvm::emitARMRegPlusImmediate(MachineBasicBlock &MBB, 18396495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MachineBasicBlock::iterator &MBBI, DebugLoc dl, 18406495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned DestReg, unsigned BaseReg, int NumBytes, 18416495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ARMCC::CondCodes Pred, unsigned PredReg, 184257caad7a33ff145b71545f10dcfbbf2fd0f595d3Anton Korobeynikov const ARMBaseInstrInfo &TII, unsigned MIFlags) { 1843e53abc20724ddde4e91467671328b531361a734fTim Northover if (NumBytes == 0 && DestReg != BaseReg) { 1844e53abc20724ddde4e91467671328b531361a734fTim Northover BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), DestReg) 1845e53abc20724ddde4e91467671328b531361a734fTim Northover .addReg(BaseReg, RegState::Kill) 1846e53abc20724ddde4e91467671328b531361a734fTim Northover .addImm((unsigned)Pred).addReg(PredReg).addReg(0) 1847e53abc20724ddde4e91467671328b531361a734fTim Northover .setMIFlags(MIFlags); 1848e53abc20724ddde4e91467671328b531361a734fTim Northover return; 1849e53abc20724ddde4e91467671328b531361a734fTim Northover } 1850e53abc20724ddde4e91467671328b531361a734fTim Northover 18516495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng bool isSub = NumBytes < 0; 18526495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (isSub) NumBytes = -NumBytes; 18536495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 18546495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng while (NumBytes) { 18556495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned RotAmt = ARM_AM::getSOImmValRotate(NumBytes); 18566495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned ThisVal = NumBytes & ARM_AM::rotr32(0xFF, RotAmt); 18576495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng assert(ThisVal && "Didn't extract field correctly"); 18586495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 18596495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // We will handle these bits from offset, clear them. 18606495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng NumBytes &= ~ThisVal; 18616495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 18626495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng assert(ARM_AM::getSOImmVal(ThisVal) != -1 && "Bit extraction didn't work?"); 18636495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 18646495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Build the new ADD / SUB. 18656495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned Opc = isSub ? ARM::SUBri : ARM::ADDri; 18666495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg) 18676495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng .addReg(BaseReg, RegState::Kill).addImm(ThisVal) 186857caad7a33ff145b71545f10dcfbbf2fd0f595d3Anton Korobeynikov .addImm((unsigned)Pred).addReg(PredReg).addReg(0) 186957caad7a33ff145b71545f10dcfbbf2fd0f595d3Anton Korobeynikov .setMIFlags(MIFlags); 18706495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng BaseReg = DestReg; 18716495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 18726495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng} 18736495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 187436b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hinesstatic bool isAnySubRegLive(unsigned Reg, const TargetRegisterInfo *TRI, 187536b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines MachineInstr *MI) { 187636b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines for (MCSubRegIterator Subreg(Reg, TRI, /* IncludeSelf */ true); 187736b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines Subreg.isValid(); ++Subreg) 187836b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines if (MI->getParent()->computeRegisterLiveness(TRI, *Subreg, MI) != 187936b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines MachineBasicBlock::LQR_Dead) 188036b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines return true; 188136b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines return false; 188236b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines} 188336b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hinesbool llvm::tryFoldSPUpdateIntoPushPop(const ARMSubtarget &Subtarget, 188436b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines MachineFunction &MF, MachineInstr *MI, 1885323ac85d6ad7ba5d9593d8e151d879bd91d82e08Tim Northover unsigned NumBytes) { 1886323ac85d6ad7ba5d9593d8e151d879bd91d82e08Tim Northover // This optimisation potentially adds lots of load and store 1887323ac85d6ad7ba5d9593d8e151d879bd91d82e08Tim Northover // micro-operations, it's only really a great benefit to code-size. 188836b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines if (!Subtarget.isMinSize()) 1889323ac85d6ad7ba5d9593d8e151d879bd91d82e08Tim Northover return false; 1890323ac85d6ad7ba5d9593d8e151d879bd91d82e08Tim Northover 1891323ac85d6ad7ba5d9593d8e151d879bd91d82e08Tim Northover // If only one register is pushed/popped, LLVM can use an LDR/STR 1892323ac85d6ad7ba5d9593d8e151d879bd91d82e08Tim Northover // instead. We can't modify those so make sure we're dealing with an 1893323ac85d6ad7ba5d9593d8e151d879bd91d82e08Tim Northover // instruction we understand. 1894323ac85d6ad7ba5d9593d8e151d879bd91d82e08Tim Northover bool IsPop = isPopOpcode(MI->getOpcode()); 1895323ac85d6ad7ba5d9593d8e151d879bd91d82e08Tim Northover bool IsPush = isPushOpcode(MI->getOpcode()); 1896323ac85d6ad7ba5d9593d8e151d879bd91d82e08Tim Northover if (!IsPush && !IsPop) 1897323ac85d6ad7ba5d9593d8e151d879bd91d82e08Tim Northover return false; 1898323ac85d6ad7ba5d9593d8e151d879bd91d82e08Tim Northover 1899323ac85d6ad7ba5d9593d8e151d879bd91d82e08Tim Northover bool IsVFPPushPop = MI->getOpcode() == ARM::VSTMDDB_UPD || 1900323ac85d6ad7ba5d9593d8e151d879bd91d82e08Tim Northover MI->getOpcode() == ARM::VLDMDIA_UPD; 1901323ac85d6ad7ba5d9593d8e151d879bd91d82e08Tim Northover bool IsT1PushPop = MI->getOpcode() == ARM::tPUSH || 1902323ac85d6ad7ba5d9593d8e151d879bd91d82e08Tim Northover MI->getOpcode() == ARM::tPOP || 1903323ac85d6ad7ba5d9593d8e151d879bd91d82e08Tim Northover MI->getOpcode() == ARM::tPOP_RET; 1904323ac85d6ad7ba5d9593d8e151d879bd91d82e08Tim Northover 1905323ac85d6ad7ba5d9593d8e151d879bd91d82e08Tim Northover assert((IsT1PushPop || (MI->getOperand(0).getReg() == ARM::SP && 1906323ac85d6ad7ba5d9593d8e151d879bd91d82e08Tim Northover MI->getOperand(1).getReg() == ARM::SP)) && 1907323ac85d6ad7ba5d9593d8e151d879bd91d82e08Tim Northover "trying to fold sp update into non-sp-updating push/pop"); 1908323ac85d6ad7ba5d9593d8e151d879bd91d82e08Tim Northover 1909323ac85d6ad7ba5d9593d8e151d879bd91d82e08Tim Northover // The VFP push & pop act on D-registers, so we can only fold an adjustment 1910323ac85d6ad7ba5d9593d8e151d879bd91d82e08Tim Northover // by a multiple of 8 bytes in correctly. Similarly rN is 4-bytes. Don't try 1911323ac85d6ad7ba5d9593d8e151d879bd91d82e08Tim Northover // if this is violated. 1912323ac85d6ad7ba5d9593d8e151d879bd91d82e08Tim Northover if (NumBytes % (IsVFPPushPop ? 8 : 4) != 0) 1913323ac85d6ad7ba5d9593d8e151d879bd91d82e08Tim Northover return false; 1914323ac85d6ad7ba5d9593d8e151d879bd91d82e08Tim Northover 1915323ac85d6ad7ba5d9593d8e151d879bd91d82e08Tim Northover // ARM and Thumb2 push/pop insts have explicit "sp, sp" operands (+ 1916323ac85d6ad7ba5d9593d8e151d879bd91d82e08Tim Northover // pred) so the list starts at 4. Thumb1 starts after the predicate. 1917323ac85d6ad7ba5d9593d8e151d879bd91d82e08Tim Northover int RegListIdx = IsT1PushPop ? 2 : 4; 1918323ac85d6ad7ba5d9593d8e151d879bd91d82e08Tim Northover 1919323ac85d6ad7ba5d9593d8e151d879bd91d82e08Tim Northover // Calculate the space we'll need in terms of registers. 1920323ac85d6ad7ba5d9593d8e151d879bd91d82e08Tim Northover unsigned FirstReg = MI->getOperand(RegListIdx).getReg(); 1921323ac85d6ad7ba5d9593d8e151d879bd91d82e08Tim Northover unsigned RD0Reg, RegsNeeded; 1922323ac85d6ad7ba5d9593d8e151d879bd91d82e08Tim Northover if (IsVFPPushPop) { 1923323ac85d6ad7ba5d9593d8e151d879bd91d82e08Tim Northover RD0Reg = ARM::D0; 1924323ac85d6ad7ba5d9593d8e151d879bd91d82e08Tim Northover RegsNeeded = NumBytes / 8; 1925323ac85d6ad7ba5d9593d8e151d879bd91d82e08Tim Northover } else { 1926323ac85d6ad7ba5d9593d8e151d879bd91d82e08Tim Northover RD0Reg = ARM::R0; 1927323ac85d6ad7ba5d9593d8e151d879bd91d82e08Tim Northover RegsNeeded = NumBytes / 4; 1928323ac85d6ad7ba5d9593d8e151d879bd91d82e08Tim Northover } 1929323ac85d6ad7ba5d9593d8e151d879bd91d82e08Tim Northover 1930323ac85d6ad7ba5d9593d8e151d879bd91d82e08Tim Northover // We're going to have to strip all list operands off before 1931323ac85d6ad7ba5d9593d8e151d879bd91d82e08Tim Northover // re-adding them since the order matters, so save the existing ones 1932323ac85d6ad7ba5d9593d8e151d879bd91d82e08Tim Northover // for later. 1933323ac85d6ad7ba5d9593d8e151d879bd91d82e08Tim Northover SmallVector<MachineOperand, 4> RegList; 1934323ac85d6ad7ba5d9593d8e151d879bd91d82e08Tim Northover for (int i = MI->getNumOperands() - 1; i >= RegListIdx; --i) 1935323ac85d6ad7ba5d9593d8e151d879bd91d82e08Tim Northover RegList.push_back(MI->getOperand(i)); 1936323ac85d6ad7ba5d9593d8e151d879bd91d82e08Tim Northover 1937323ac85d6ad7ba5d9593d8e151d879bd91d82e08Tim Northover const TargetRegisterInfo *TRI = MF.getRegInfo().getTargetRegisterInfo(); 19381b26fdbf1f01e90b803cc035b6b932cd95c76830Bill Wendling const MCPhysReg *CSRegs = TRI->getCalleeSavedRegs(&MF); 1939323ac85d6ad7ba5d9593d8e151d879bd91d82e08Tim Northover 1940323ac85d6ad7ba5d9593d8e151d879bd91d82e08Tim Northover // Now try to find enough space in the reglist to allocate NumBytes. 1941323ac85d6ad7ba5d9593d8e151d879bd91d82e08Tim Northover for (unsigned CurReg = FirstReg - 1; CurReg >= RD0Reg && RegsNeeded; 19421b26fdbf1f01e90b803cc035b6b932cd95c76830Bill Wendling --CurReg) { 1943323ac85d6ad7ba5d9593d8e151d879bd91d82e08Tim Northover if (!IsPop) { 1944323ac85d6ad7ba5d9593d8e151d879bd91d82e08Tim Northover // Pushing any register is completely harmless, mark the 1945323ac85d6ad7ba5d9593d8e151d879bd91d82e08Tim Northover // register involved as undef since we don't care about it in 1946323ac85d6ad7ba5d9593d8e151d879bd91d82e08Tim Northover // the slightest. 1947323ac85d6ad7ba5d9593d8e151d879bd91d82e08Tim Northover RegList.push_back(MachineOperand::CreateReg(CurReg, false, false, 1948323ac85d6ad7ba5d9593d8e151d879bd91d82e08Tim Northover false, false, true)); 19491b26fdbf1f01e90b803cc035b6b932cd95c76830Bill Wendling --RegsNeeded; 1950323ac85d6ad7ba5d9593d8e151d879bd91d82e08Tim Northover continue; 1951323ac85d6ad7ba5d9593d8e151d879bd91d82e08Tim Northover } 1952323ac85d6ad7ba5d9593d8e151d879bd91d82e08Tim Northover 19531b26fdbf1f01e90b803cc035b6b932cd95c76830Bill Wendling // However, we can only pop an extra register if it's not live. For 19541b26fdbf1f01e90b803cc035b6b932cd95c76830Bill Wendling // registers live within the function we might clobber a return value 19551b26fdbf1f01e90b803cc035b6b932cd95c76830Bill Wendling // register; the other way a register can be live here is if it's 19561b26fdbf1f01e90b803cc035b6b932cd95c76830Bill Wendling // callee-saved. 195736b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines // TODO: Currently, computeRegisterLiveness() does not report "live" if a 195836b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines // sub reg is live. When computeRegisterLiveness() works for sub reg, it 195936b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines // can replace isAnySubRegLive(). 19601b26fdbf1f01e90b803cc035b6b932cd95c76830Bill Wendling if (isCalleeSavedRegister(CurReg, CSRegs) || 196136b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines isAnySubRegLive(CurReg, TRI, MI)) { 19621b26fdbf1f01e90b803cc035b6b932cd95c76830Bill Wendling // VFP pops don't allow holes in the register list, so any skip is fatal 19631b26fdbf1f01e90b803cc035b6b932cd95c76830Bill Wendling // for our transformation. GPR pops do, so we should just keep looking. 19641b26fdbf1f01e90b803cc035b6b932cd95c76830Bill Wendling if (IsVFPPushPop) 19651b26fdbf1f01e90b803cc035b6b932cd95c76830Bill Wendling return false; 19661b26fdbf1f01e90b803cc035b6b932cd95c76830Bill Wendling else 19671b26fdbf1f01e90b803cc035b6b932cd95c76830Bill Wendling continue; 19681b26fdbf1f01e90b803cc035b6b932cd95c76830Bill Wendling } 1969323ac85d6ad7ba5d9593d8e151d879bd91d82e08Tim Northover 1970323ac85d6ad7ba5d9593d8e151d879bd91d82e08Tim Northover // Mark the unimportant registers as <def,dead> in the POP. 19713d238de4d54eb0b16afd96a57f49f92b2f7748e0Bill Wendling RegList.push_back(MachineOperand::CreateReg(CurReg, true, false, false, 19723d238de4d54eb0b16afd96a57f49f92b2f7748e0Bill Wendling true)); 19731b26fdbf1f01e90b803cc035b6b932cd95c76830Bill Wendling --RegsNeeded; 1974323ac85d6ad7ba5d9593d8e151d879bd91d82e08Tim Northover } 1975323ac85d6ad7ba5d9593d8e151d879bd91d82e08Tim Northover 1976323ac85d6ad7ba5d9593d8e151d879bd91d82e08Tim Northover if (RegsNeeded > 0) 1977323ac85d6ad7ba5d9593d8e151d879bd91d82e08Tim Northover return false; 1978323ac85d6ad7ba5d9593d8e151d879bd91d82e08Tim Northover 1979323ac85d6ad7ba5d9593d8e151d879bd91d82e08Tim Northover // Finally we know we can profitably perform the optimisation so go 1980323ac85d6ad7ba5d9593d8e151d879bd91d82e08Tim Northover // ahead: strip all existing registers off and add them back again 1981323ac85d6ad7ba5d9593d8e151d879bd91d82e08Tim Northover // in the right order. 1982323ac85d6ad7ba5d9593d8e151d879bd91d82e08Tim Northover for (int i = MI->getNumOperands() - 1; i >= RegListIdx; --i) 1983323ac85d6ad7ba5d9593d8e151d879bd91d82e08Tim Northover MI->RemoveOperand(i); 1984323ac85d6ad7ba5d9593d8e151d879bd91d82e08Tim Northover 1985323ac85d6ad7ba5d9593d8e151d879bd91d82e08Tim Northover // Add the complete list back in. 1986323ac85d6ad7ba5d9593d8e151d879bd91d82e08Tim Northover MachineInstrBuilder MIB(MF, &*MI); 1987323ac85d6ad7ba5d9593d8e151d879bd91d82e08Tim Northover for (int i = RegList.size() - 1; i >= 0; --i) 1988323ac85d6ad7ba5d9593d8e151d879bd91d82e08Tim Northover MIB.addOperand(RegList[i]); 1989323ac85d6ad7ba5d9593d8e151d879bd91d82e08Tim Northover 1990323ac85d6ad7ba5d9593d8e151d879bd91d82e08Tim Northover return true; 1991323ac85d6ad7ba5d9593d8e151d879bd91d82e08Tim Northover} 1992323ac85d6ad7ba5d9593d8e151d879bd91d82e08Tim Northover 1993cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Chengbool llvm::rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx, 1994cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng unsigned FrameReg, int &Offset, 1995cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng const ARMBaseInstrInfo &TII) { 19966495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned Opcode = MI.getOpcode(); 1997e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng const MCInstrDesc &Desc = MI.getDesc(); 19986495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask); 19996495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng bool isSub = false; 2000764ab52dd80310a205c9888bf166d09dab858f90Jim Grosbach 20016495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Memory operands in inline assembly always use AddrMode2. 20026495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (Opcode == ARM::INLINEASM) 20036495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng AddrMode = ARMII::AddrMode2; 2004764ab52dd80310a205c9888bf166d09dab858f90Jim Grosbach 20056495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (Opcode == ARM::ADDri) { 20066495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng Offset += MI.getOperand(FrameRegIdx+1).getImm(); 20076495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (Offset == 0) { 20086495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Turn it into a move. 20096495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MI.setDesc(TII.get(ARM::MOVr)); 20106495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false); 20116495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MI.RemoveOperand(FrameRegIdx+1); 2012cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng Offset = 0; 2013cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng return true; 20146495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } else if (Offset < 0) { 20156495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng Offset = -Offset; 20166495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng isSub = true; 20176495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MI.setDesc(TII.get(ARM::SUBri)); 20186495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 20196495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 20206495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Common case: small offset, fits into instruction. 20216495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (ARM_AM::getSOImmVal(Offset) != -1) { 20226495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Replace the FrameIndex with sp / fp 20236495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false); 20246495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset); 2025cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng Offset = 0; 2026cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng return true; 20276495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 20286495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 20296495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Otherwise, pull as much of the immedidate into this ADDri/SUBri 20306495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // as possible. 20316495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned RotAmt = ARM_AM::getSOImmValRotate(Offset); 20326495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xFF, RotAmt); 20336495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 20346495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // We will handle these bits from offset, clear them. 20356495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng Offset &= ~ThisImmVal; 20366495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 20376495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Get the properly encoded SOImmVal field. 20386495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng assert(ARM_AM::getSOImmVal(ThisImmVal) != -1 && 20396495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng "Bit extraction didn't work?"); 20406495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MI.getOperand(FrameRegIdx+1).ChangeToImmediate(ThisImmVal); 20416495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } else { 20426495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned ImmIdx = 0; 20436495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng int InstrOffs = 0; 20446495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned NumBits = 0; 20456495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned Scale = 1; 20466495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng switch (AddrMode) { 20473e5561247202bae994dd259a2d8dc4eff8f799f3Jim Grosbach case ARMII::AddrMode_i12: { 20483e5561247202bae994dd259a2d8dc4eff8f799f3Jim Grosbach ImmIdx = FrameRegIdx + 1; 20493e5561247202bae994dd259a2d8dc4eff8f799f3Jim Grosbach InstrOffs = MI.getOperand(ImmIdx).getImm(); 20503e5561247202bae994dd259a2d8dc4eff8f799f3Jim Grosbach NumBits = 12; 20513e5561247202bae994dd259a2d8dc4eff8f799f3Jim Grosbach break; 20523e5561247202bae994dd259a2d8dc4eff8f799f3Jim Grosbach } 20536495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng case ARMII::AddrMode2: { 20546495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ImmIdx = FrameRegIdx+2; 20556495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng InstrOffs = ARM_AM::getAM2Offset(MI.getOperand(ImmIdx).getImm()); 20566495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (ARM_AM::getAM2Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub) 20576495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng InstrOffs *= -1; 20586495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng NumBits = 12; 20596495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng break; 20606495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 20616495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng case ARMII::AddrMode3: { 20626495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ImmIdx = FrameRegIdx+2; 20636495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng InstrOffs = ARM_AM::getAM3Offset(MI.getOperand(ImmIdx).getImm()); 20646495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (ARM_AM::getAM3Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub) 20656495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng InstrOffs *= -1; 20666495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng NumBits = 8; 20676495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng break; 20686495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 2069baf31088f1472f48ea5ae81f0b93636cc44ca444Anton Korobeynikov case ARMII::AddrMode4: 2070a44321776ecd96fa0344335d3027758be3386e45Jim Grosbach case ARMII::AddrMode6: 2071cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng // Can't fold any offset even if it's zero. 2072cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng return false; 20736495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng case ARMII::AddrMode5: { 20746495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ImmIdx = FrameRegIdx+1; 20756495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng InstrOffs = ARM_AM::getAM5Offset(MI.getOperand(ImmIdx).getImm()); 20766495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (ARM_AM::getAM5Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub) 20776495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng InstrOffs *= -1; 20786495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng NumBits = 8; 20796495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng Scale = 4; 20806495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng break; 20816495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 20826495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng default: 20836495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng llvm_unreachable("Unsupported addressing mode!"); 20846495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 20856495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 20866495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng Offset += InstrOffs * Scale; 20876495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!"); 20886495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (Offset < 0) { 20896495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng Offset = -Offset; 20906495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng isSub = true; 20916495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 20926495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 20936495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Attempt to fold address comp. if opcode has offset bits 20946495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (NumBits > 0) { 20956495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Common case: small offset, fits into instruction. 20966495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MachineOperand &ImmOp = MI.getOperand(ImmIdx); 20976495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng int ImmedOffset = Offset / Scale; 20986495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned Mask = (1 << NumBits) - 1; 20996495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if ((unsigned)Offset <= Mask * Scale) { 21006495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Replace the FrameIndex with sp 21016495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false); 210277aee8e22c36257716c2df2f275724765704f20cJim Grosbach // FIXME: When addrmode2 goes away, this will simplify (like the 210377aee8e22c36257716c2df2f275724765704f20cJim Grosbach // T2 version), as the LDR.i12 versions don't need the encoding 210477aee8e22c36257716c2df2f275724765704f20cJim Grosbach // tricks for the offset value. 210577aee8e22c36257716c2df2f275724765704f20cJim Grosbach if (isSub) { 210677aee8e22c36257716c2df2f275724765704f20cJim Grosbach if (AddrMode == ARMII::AddrMode_i12) 210777aee8e22c36257716c2df2f275724765704f20cJim Grosbach ImmedOffset = -ImmedOffset; 210877aee8e22c36257716c2df2f275724765704f20cJim Grosbach else 210977aee8e22c36257716c2df2f275724765704f20cJim Grosbach ImmedOffset |= 1 << NumBits; 211077aee8e22c36257716c2df2f275724765704f20cJim Grosbach } 21116495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ImmOp.ChangeToImmediate(ImmedOffset); 2112cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng Offset = 0; 2113cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng return true; 21146495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 2115764ab52dd80310a205c9888bf166d09dab858f90Jim Grosbach 21166495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Otherwise, it didn't fit. Pull in what we can to simplify the immed. 21176495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ImmedOffset = ImmedOffset & Mask; 2118063efbf569e46776093ddf50099c98fdbb362167Jim Grosbach if (isSub) { 2119063efbf569e46776093ddf50099c98fdbb362167Jim Grosbach if (AddrMode == ARMII::AddrMode_i12) 2120063efbf569e46776093ddf50099c98fdbb362167Jim Grosbach ImmedOffset = -ImmedOffset; 2121063efbf569e46776093ddf50099c98fdbb362167Jim Grosbach else 2122063efbf569e46776093ddf50099c98fdbb362167Jim Grosbach ImmedOffset |= 1 << NumBits; 2123063efbf569e46776093ddf50099c98fdbb362167Jim Grosbach } 21246495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ImmOp.ChangeToImmediate(ImmedOffset); 21256495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng Offset &= ~(Mask*Scale); 21266495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 21276495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 21286495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 2129cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng Offset = (isSub) ? -Offset : Offset; 2130cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng return Offset == 0; 21316495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng} 2132e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling 2133de7266c611b37ec050efb53b73166081a98cea13Manman Ren/// analyzeCompare - For a comparison instruction, return the source registers 2134de7266c611b37ec050efb53b73166081a98cea13Manman Ren/// in SrcReg and SrcReg2 if having two register operands, and the value it 2135de7266c611b37ec050efb53b73166081a98cea13Manman Ren/// compares against in CmpValue. Return true if the comparison instruction 2136de7266c611b37ec050efb53b73166081a98cea13Manman Ren/// can be analyzed. 2137e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendlingbool ARMBaseInstrInfo:: 2138de7266c611b37ec050efb53b73166081a98cea13Manman RenanalyzeCompare(const MachineInstr *MI, unsigned &SrcReg, unsigned &SrcReg2, 2139de7266c611b37ec050efb53b73166081a98cea13Manman Ren int &CmpMask, int &CmpValue) const { 2140e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling switch (MI->getOpcode()) { 2141e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling default: break; 214238ae997e63e3e1bb2c8679e01ea74cf8fd0be893Bill Wendling case ARM::CMPri: 2143e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling case ARM::t2CMPri: 2144e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling SrcReg = MI->getOperand(0).getReg(); 2145de7266c611b37ec050efb53b73166081a98cea13Manman Ren SrcReg2 = 0; 214604ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif CmpMask = ~0; 2147e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling CmpValue = MI->getOperand(1).getImm(); 2148e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling return true; 2149247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren case ARM::CMPrr: 2150247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren case ARM::t2CMPrr: 2151247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren SrcReg = MI->getOperand(0).getReg(); 2152de7266c611b37ec050efb53b73166081a98cea13Manman Ren SrcReg2 = MI->getOperand(1).getReg(); 2153247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren CmpMask = ~0; 2154247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren CmpValue = 0; 2155247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren return true; 215604ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif case ARM::TSTri: 215704ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif case ARM::t2TSTri: 215804ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif SrcReg = MI->getOperand(0).getReg(); 2159de7266c611b37ec050efb53b73166081a98cea13Manman Ren SrcReg2 = 0; 216004ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif CmpMask = MI->getOperand(1).getImm(); 216104ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif CmpValue = 0; 216204ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif return true; 216304ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif } 216404ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif 216504ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif return false; 216604ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif} 216704ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif 216805642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif/// isSuitableForMask - Identify a suitable 'and' instruction that 216905642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif/// operates on the given source register and applies the same mask 217005642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif/// as a 'tst' instruction. Provide a limited look-through for copies. 217105642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif/// When successful, MI will hold the found instruction. 217205642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greifstatic bool isSuitableForMask(MachineInstr *&MI, unsigned SrcReg, 21738ff9bb189ce188452e6cae6ed65cb2745814126cGabor Greif int CmpMask, bool CommonUse) { 217405642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif switch (MI->getOpcode()) { 217504ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif case ARM::ANDri: 217604ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif case ARM::t2ANDri: 217705642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif if (CmpMask != MI->getOperand(2).getImm()) 21788ff9bb189ce188452e6cae6ed65cb2745814126cGabor Greif return false; 217905642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif if (SrcReg == MI->getOperand(CommonUse ? 1 : 0).getReg()) 218004ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif return true; 218104ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif break; 218205642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif case ARM::COPY: { 218305642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif // Walk down one instruction which is potentially an 'and'. 218405642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif const MachineInstr &Copy = *MI; 2185f000a7a212590bfd45e23c05bff5e1b683d25dd6Michael J. Spencer MachineBasicBlock::iterator AND( 218636b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines std::next(MachineBasicBlock::iterator(MI))); 218705642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif if (AND == MI->getParent()->end()) return false; 218805642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif MI = AND; 218905642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif return isSuitableForMask(MI, Copy.getOperand(0).getReg(), 219005642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif CmpMask, true); 219105642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif } 2192e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling } 2193e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling 2194e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling return false; 2195e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling} 2196e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling 219776c6ccbd4cee0637c961e32435177ab89e931fedManman Ren/// getSwappedCondition - assume the flags are set by MI(a,b), return 219876c6ccbd4cee0637c961e32435177ab89e931fedManman Ren/// the condition code if we modify the instructions such that flags are 219976c6ccbd4cee0637c961e32435177ab89e931fedManman Ren/// set by MI(b,a). 220076c6ccbd4cee0637c961e32435177ab89e931fedManman Reninline static ARMCC::CondCodes getSwappedCondition(ARMCC::CondCodes CC) { 220176c6ccbd4cee0637c961e32435177ab89e931fedManman Ren switch (CC) { 220276c6ccbd4cee0637c961e32435177ab89e931fedManman Ren default: return ARMCC::AL; 220376c6ccbd4cee0637c961e32435177ab89e931fedManman Ren case ARMCC::EQ: return ARMCC::EQ; 220476c6ccbd4cee0637c961e32435177ab89e931fedManman Ren case ARMCC::NE: return ARMCC::NE; 220576c6ccbd4cee0637c961e32435177ab89e931fedManman Ren case ARMCC::HS: return ARMCC::LS; 220676c6ccbd4cee0637c961e32435177ab89e931fedManman Ren case ARMCC::LO: return ARMCC::HI; 220776c6ccbd4cee0637c961e32435177ab89e931fedManman Ren case ARMCC::HI: return ARMCC::LO; 220876c6ccbd4cee0637c961e32435177ab89e931fedManman Ren case ARMCC::LS: return ARMCC::HS; 220976c6ccbd4cee0637c961e32435177ab89e931fedManman Ren case ARMCC::GE: return ARMCC::LE; 221076c6ccbd4cee0637c961e32435177ab89e931fedManman Ren case ARMCC::LT: return ARMCC::GT; 221176c6ccbd4cee0637c961e32435177ab89e931fedManman Ren case ARMCC::GT: return ARMCC::LT; 221276c6ccbd4cee0637c961e32435177ab89e931fedManman Ren case ARMCC::LE: return ARMCC::GE; 221376c6ccbd4cee0637c961e32435177ab89e931fedManman Ren } 221476c6ccbd4cee0637c961e32435177ab89e931fedManman Ren} 221576c6ccbd4cee0637c961e32435177ab89e931fedManman Ren 221676c6ccbd4cee0637c961e32435177ab89e931fedManman Ren/// isRedundantFlagInstr - check whether the first instruction, whose only 221776c6ccbd4cee0637c961e32435177ab89e931fedManman Ren/// purpose is to update flags, can be made redundant. 221876c6ccbd4cee0637c961e32435177ab89e931fedManman Ren/// CMPrr can be made redundant by SUBrr if the operands are the same. 221976c6ccbd4cee0637c961e32435177ab89e931fedManman Ren/// CMPri can be made redundant by SUBri if the operands are the same. 222076c6ccbd4cee0637c961e32435177ab89e931fedManman Ren/// This function can be extended later on. 222176c6ccbd4cee0637c961e32435177ab89e931fedManman Reninline static bool isRedundantFlagInstr(MachineInstr *CmpI, unsigned SrcReg, 222276c6ccbd4cee0637c961e32435177ab89e931fedManman Ren unsigned SrcReg2, int ImmValue, 222376c6ccbd4cee0637c961e32435177ab89e931fedManman Ren MachineInstr *OI) { 222476c6ccbd4cee0637c961e32435177ab89e931fedManman Ren if ((CmpI->getOpcode() == ARM::CMPrr || 222576c6ccbd4cee0637c961e32435177ab89e931fedManman Ren CmpI->getOpcode() == ARM::t2CMPrr) && 222676c6ccbd4cee0637c961e32435177ab89e931fedManman Ren (OI->getOpcode() == ARM::SUBrr || 222776c6ccbd4cee0637c961e32435177ab89e931fedManman Ren OI->getOpcode() == ARM::t2SUBrr) && 222876c6ccbd4cee0637c961e32435177ab89e931fedManman Ren ((OI->getOperand(1).getReg() == SrcReg && 222976c6ccbd4cee0637c961e32435177ab89e931fedManman Ren OI->getOperand(2).getReg() == SrcReg2) || 223076c6ccbd4cee0637c961e32435177ab89e931fedManman Ren (OI->getOperand(1).getReg() == SrcReg2 && 223176c6ccbd4cee0637c961e32435177ab89e931fedManman Ren OI->getOperand(2).getReg() == SrcReg))) 223276c6ccbd4cee0637c961e32435177ab89e931fedManman Ren return true; 223376c6ccbd4cee0637c961e32435177ab89e931fedManman Ren 223476c6ccbd4cee0637c961e32435177ab89e931fedManman Ren if ((CmpI->getOpcode() == ARM::CMPri || 223576c6ccbd4cee0637c961e32435177ab89e931fedManman Ren CmpI->getOpcode() == ARM::t2CMPri) && 223676c6ccbd4cee0637c961e32435177ab89e931fedManman Ren (OI->getOpcode() == ARM::SUBri || 223776c6ccbd4cee0637c961e32435177ab89e931fedManman Ren OI->getOpcode() == ARM::t2SUBri) && 223876c6ccbd4cee0637c961e32435177ab89e931fedManman Ren OI->getOperand(1).getReg() == SrcReg && 223976c6ccbd4cee0637c961e32435177ab89e931fedManman Ren OI->getOperand(2).getImm() == ImmValue) 224076c6ccbd4cee0637c961e32435177ab89e931fedManman Ren return true; 224176c6ccbd4cee0637c961e32435177ab89e931fedManman Ren return false; 224276c6ccbd4cee0637c961e32435177ab89e931fedManman Ren} 224376c6ccbd4cee0637c961e32435177ab89e931fedManman Ren 2244de7266c611b37ec050efb53b73166081a98cea13Manman Ren/// optimizeCompareInstr - Convert the instruction supplying the argument to the 2245de7266c611b37ec050efb53b73166081a98cea13Manman Ren/// comparison into one that sets the zero bit in the flags register; 2246de7266c611b37ec050efb53b73166081a98cea13Manman Ren/// Remove a redundant Compare instruction if an earlier instruction can set the 2247de7266c611b37ec050efb53b73166081a98cea13Manman Ren/// flags in the same way as Compare. 2248de7266c611b37ec050efb53b73166081a98cea13Manman Ren/// E.g. SUBrr(r1,r2) and CMPrr(r1,r2). We also handle the case where two 2249de7266c611b37ec050efb53b73166081a98cea13Manman Ren/// operands are swapped: SUBrr(r1,r2) and CMPrr(r2,r1), by updating the 2250de7266c611b37ec050efb53b73166081a98cea13Manman Ren/// condition code of instructions which use the flags. 2251e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendlingbool ARMBaseInstrInfo:: 2252de7266c611b37ec050efb53b73166081a98cea13Manman RenoptimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, unsigned SrcReg2, 2253de7266c611b37ec050efb53b73166081a98cea13Manman Ren int CmpMask, int CmpValue, 2254de7266c611b37ec050efb53b73166081a98cea13Manman Ren const MachineRegisterInfo *MRI) const { 225576c6ccbd4cee0637c961e32435177ab89e931fedManman Ren // Get the unique definition of SrcReg. 225676c6ccbd4cee0637c961e32435177ab89e931fedManman Ren MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg); 225776c6ccbd4cee0637c961e32435177ab89e931fedManman Ren if (!MI) return false; 225892ad57f066e9f256e4e3d72febf152e68caa80c7Bill Wendling 225904ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif // Masked compares sometimes use the same register as the corresponding 'and'. 226004ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif if (CmpMask != ~0) { 2261519daf5d2dd80614ac4e529b199e6f3e595bfc80Jakob Stoklund Olesen if (!isSuitableForMask(MI, SrcReg, CmpMask, false) || isPredicated(MI)) { 2262dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines MI = nullptr; 226336b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines for (MachineRegisterInfo::use_instr_iterator 226436b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines UI = MRI->use_instr_begin(SrcReg), UE = MRI->use_instr_end(); 226536b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines UI != UE; ++UI) { 226604ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif if (UI->getParent() != CmpInstr->getParent()) continue; 226705642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif MachineInstr *PotentialAND = &*UI; 2268519daf5d2dd80614ac4e529b199e6f3e595bfc80Jakob Stoklund Olesen if (!isSuitableForMask(PotentialAND, SrcReg, CmpMask, true) || 2269519daf5d2dd80614ac4e529b199e6f3e595bfc80Jakob Stoklund Olesen isPredicated(PotentialAND)) 227004ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif continue; 227105642a3eba3f35aa8fdf6aa16d87561560e60af3Gabor Greif MI = PotentialAND; 227204ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif break; 227304ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif } 227404ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif if (!MI) return false; 227504ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif } 227604ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif } 227704ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif 2278247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren // Get ready to iterate backward from CmpInstr. 2279247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren MachineBasicBlock::iterator I = CmpInstr, E = MI, 2280247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren B = CmpInstr->getParent()->begin(); 22810aa38b9381a5be42abd4f5ca5baa8c2930d148d3Bill Wendling 22820aa38b9381a5be42abd4f5ca5baa8c2930d148d3Bill Wendling // Early exit if CmpInstr is at the beginning of the BB. 22830aa38b9381a5be42abd4f5ca5baa8c2930d148d3Bill Wendling if (I == B) return false; 22840aa38b9381a5be42abd4f5ca5baa8c2930d148d3Bill Wendling 2285247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren // There are two possible candidates which can be changed to set CPSR: 2286247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren // One is MI, the other is a SUB instruction. 2287247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren // For CMPrr(r1,r2), we are looking for SUB(r1,r2) or SUB(r2,r1). 2288247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren // For CMPri(r1, CmpValue), we are looking for SUBri(r1, CmpValue). 2289dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines MachineInstr *Sub = nullptr; 2290de7266c611b37ec050efb53b73166081a98cea13Manman Ren if (SrcReg2 != 0) 2291247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren // MI is not a candidate for CMPrr. 2292dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines MI = nullptr; 2293de7266c611b37ec050efb53b73166081a98cea13Manman Ren else if (MI->getParent() != CmpInstr->getParent() || CmpValue != 0) { 2294247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren // Conservatively refuse to convert an instruction which isn't in the same 2295247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren // BB as the comparison. 2296247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren // For CMPri, we need to check Sub, thus we can't return here. 22974949e98cccb98abb0ba3f67c22be757d446ab108Manman Ren if (CmpInstr->getOpcode() == ARM::CMPri || 2298247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren CmpInstr->getOpcode() == ARM::t2CMPri) 2299dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines MI = nullptr; 2300247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren else 2301247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren return false; 2302247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren } 2303247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren 2304247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren // Check that CPSR isn't set between the comparison instruction and the one we 2305247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren // want to change. At the same time, search for Sub. 230676c6ccbd4cee0637c961e32435177ab89e931fedManman Ren const TargetRegisterInfo *TRI = &getRegisterInfo(); 2307e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling --I; 2308e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling for (; I != E; --I) { 2309e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling const MachineInstr &Instr = *I; 2310e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling 231176c6ccbd4cee0637c961e32435177ab89e931fedManman Ren if (Instr.modifiesRegister(ARM::CPSR, TRI) || 231276c6ccbd4cee0637c961e32435177ab89e931fedManman Ren Instr.readsRegister(ARM::CPSR, TRI)) 231340a5eb18b031fa1a5e9697e21e251e613d441cc5Bill Wendling // This instruction modifies or uses CPSR after the one we want to 231440a5eb18b031fa1a5e9697e21e251e613d441cc5Bill Wendling // change. We can't do this transformation. 231576c6ccbd4cee0637c961e32435177ab89e931fedManman Ren return false; 2316247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren 231776c6ccbd4cee0637c961e32435177ab89e931fedManman Ren // Check whether CmpInstr can be made redundant by the current instruction. 231876c6ccbd4cee0637c961e32435177ab89e931fedManman Ren if (isRedundantFlagInstr(CmpInstr, SrcReg, SrcReg2, CmpValue, &*I)) { 2319247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren Sub = &*I; 2320247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren break; 2321247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren } 2322247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren 2323691e64a54ce899409abe7c131d15ed75e3c1fef5Evan Cheng if (I == B) 2324691e64a54ce899409abe7c131d15ed75e3c1fef5Evan Cheng // The 'and' is below the comparison instruction. 2325691e64a54ce899409abe7c131d15ed75e3c1fef5Evan Cheng return false; 2326e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling } 2327e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling 2328247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren // Return false if no candidates exist. 2329247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren if (!MI && !Sub) 2330247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren return false; 2331247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren 2332247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren // The single candidate is called MI. 2333247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren if (!MI) MI = Sub; 2334247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren 2335519daf5d2dd80614ac4e529b199e6f3e595bfc80Jakob Stoklund Olesen // We can't use a predicated instruction - it doesn't always write the flags. 2336519daf5d2dd80614ac4e529b199e6f3e595bfc80Jakob Stoklund Olesen if (isPredicated(MI)) 2337519daf5d2dd80614ac4e529b199e6f3e595bfc80Jakob Stoklund Olesen return false; 2338519daf5d2dd80614ac4e529b199e6f3e595bfc80Jakob Stoklund Olesen 2339e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling switch (MI->getOpcode()) { 2340e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling default: break; 2341ca3f6a3925e9a6e91022aa211bdc1b6e3f2ff41fCameron Zwarich case ARM::RSBrr: 2342df298c9ea64eb335f63fc075d8ef6306682ffe75Owen Anderson case ARM::RSBri: 2343ca3f6a3925e9a6e91022aa211bdc1b6e3f2ff41fCameron Zwarich case ARM::RSCrr: 2344df298c9ea64eb335f63fc075d8ef6306682ffe75Owen Anderson case ARM::RSCri: 2345ca3f6a3925e9a6e91022aa211bdc1b6e3f2ff41fCameron Zwarich case ARM::ADDrr: 234638ae997e63e3e1bb2c8679e01ea74cf8fd0be893Bill Wendling case ARM::ADDri: 2347ca3f6a3925e9a6e91022aa211bdc1b6e3f2ff41fCameron Zwarich case ARM::ADCrr: 2348df298c9ea64eb335f63fc075d8ef6306682ffe75Owen Anderson case ARM::ADCri: 2349ca3f6a3925e9a6e91022aa211bdc1b6e3f2ff41fCameron Zwarich case ARM::SUBrr: 235038ae997e63e3e1bb2c8679e01ea74cf8fd0be893Bill Wendling case ARM::SUBri: 2351ca3f6a3925e9a6e91022aa211bdc1b6e3f2ff41fCameron Zwarich case ARM::SBCrr: 2352df298c9ea64eb335f63fc075d8ef6306682ffe75Owen Anderson case ARM::SBCri: 2353df298c9ea64eb335f63fc075d8ef6306682ffe75Owen Anderson case ARM::t2RSBri: 2354ca3f6a3925e9a6e91022aa211bdc1b6e3f2ff41fCameron Zwarich case ARM::t2ADDrr: 235538ae997e63e3e1bb2c8679e01ea74cf8fd0be893Bill Wendling case ARM::t2ADDri: 2356ca3f6a3925e9a6e91022aa211bdc1b6e3f2ff41fCameron Zwarich case ARM::t2ADCrr: 2357df298c9ea64eb335f63fc075d8ef6306682ffe75Owen Anderson case ARM::t2ADCri: 2358ca3f6a3925e9a6e91022aa211bdc1b6e3f2ff41fCameron Zwarich case ARM::t2SUBrr: 2359df298c9ea64eb335f63fc075d8ef6306682ffe75Owen Anderson case ARM::t2SUBri: 2360ca3f6a3925e9a6e91022aa211bdc1b6e3f2ff41fCameron Zwarich case ARM::t2SBCrr: 2361b485de5d8c3fe0c62c0b07f63f64bd10f6803c17Cameron Zwarich case ARM::t2SBCri: 2362b485de5d8c3fe0c62c0b07f63f64bd10f6803c17Cameron Zwarich case ARM::ANDrr: 2363b485de5d8c3fe0c62c0b07f63f64bd10f6803c17Cameron Zwarich case ARM::ANDri: 2364b485de5d8c3fe0c62c0b07f63f64bd10f6803c17Cameron Zwarich case ARM::t2ANDrr: 23650cb11ac32fc09c5db42fb801db242ac9fb51f6b1Cameron Zwarich case ARM::t2ANDri: 23660cb11ac32fc09c5db42fb801db242ac9fb51f6b1Cameron Zwarich case ARM::ORRrr: 23670cb11ac32fc09c5db42fb801db242ac9fb51f6b1Cameron Zwarich case ARM::ORRri: 23680cb11ac32fc09c5db42fb801db242ac9fb51f6b1Cameron Zwarich case ARM::t2ORRrr: 23690cb11ac32fc09c5db42fb801db242ac9fb51f6b1Cameron Zwarich case ARM::t2ORRri: 23700cb11ac32fc09c5db42fb801db242ac9fb51f6b1Cameron Zwarich case ARM::EORrr: 23710cb11ac32fc09c5db42fb801db242ac9fb51f6b1Cameron Zwarich case ARM::EORri: 23720cb11ac32fc09c5db42fb801db242ac9fb51f6b1Cameron Zwarich case ARM::t2EORrr: 23730cb11ac32fc09c5db42fb801db242ac9fb51f6b1Cameron Zwarich case ARM::t2EORri: { 2374247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren // Scan forward for the use of CPSR 2375247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren // When checking against MI: if it's a conditional code requires 237645ed19499b8f7025d9acf91cc37fbf6ea63abc4fManman Ren // checking of V bit, then this is not safe to do. 237745ed19499b8f7025d9acf91cc37fbf6ea63abc4fManman Ren // It is safe to remove CmpInstr if CPSR is redefined or killed. 237845ed19499b8f7025d9acf91cc37fbf6ea63abc4fManman Ren // If we are done with the basic block, we need to check whether CPSR is 237945ed19499b8f7025d9acf91cc37fbf6ea63abc4fManman Ren // live-out. 238076c6ccbd4cee0637c961e32435177ab89e931fedManman Ren SmallVector<std::pair<MachineOperand*, ARMCC::CondCodes>, 4> 238176c6ccbd4cee0637c961e32435177ab89e931fedManman Ren OperandsToUpdate; 23822c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng bool isSafe = false; 23832c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng I = CmpInstr; 2384247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren E = CmpInstr->getParent()->end(); 23852c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng while (!isSafe && ++I != E) { 23862c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng const MachineInstr &Instr = *I; 23872c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng for (unsigned IO = 0, EO = Instr.getNumOperands(); 23882c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng !isSafe && IO != EO; ++IO) { 23892c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng const MachineOperand &MO = Instr.getOperand(IO); 23902420b558de5d291d8503c1339004e5b5bf99a48aJakob Stoklund Olesen if (MO.isRegMask() && MO.clobbersPhysReg(ARM::CPSR)) { 23912420b558de5d291d8503c1339004e5b5bf99a48aJakob Stoklund Olesen isSafe = true; 23922420b558de5d291d8503c1339004e5b5bf99a48aJakob Stoklund Olesen break; 23932420b558de5d291d8503c1339004e5b5bf99a48aJakob Stoklund Olesen } 23942c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng if (!MO.isReg() || MO.getReg() != ARM::CPSR) 23952c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng continue; 23962c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng if (MO.isDef()) { 23972c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng isSafe = true; 23982c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng break; 23992c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng } 24002bdc0dd2db145591eb3fdc01fa0b2a3d831f334bBill Wendling // Condition code is after the operand before CPSR except for VSELs. 24012bdc0dd2db145591eb3fdc01fa0b2a3d831f334bBill Wendling ARMCC::CondCodes CC; 24022bdc0dd2db145591eb3fdc01fa0b2a3d831f334bBill Wendling bool IsInstrVSel = true; 24032bdc0dd2db145591eb3fdc01fa0b2a3d831f334bBill Wendling switch (Instr.getOpcode()) { 24042bdc0dd2db145591eb3fdc01fa0b2a3d831f334bBill Wendling default: 24052bdc0dd2db145591eb3fdc01fa0b2a3d831f334bBill Wendling IsInstrVSel = false; 24062bdc0dd2db145591eb3fdc01fa0b2a3d831f334bBill Wendling CC = (ARMCC::CondCodes)Instr.getOperand(IO - 1).getImm(); 24072bdc0dd2db145591eb3fdc01fa0b2a3d831f334bBill Wendling break; 24082bdc0dd2db145591eb3fdc01fa0b2a3d831f334bBill Wendling case ARM::VSELEQD: 24092bdc0dd2db145591eb3fdc01fa0b2a3d831f334bBill Wendling case ARM::VSELEQS: 24102bdc0dd2db145591eb3fdc01fa0b2a3d831f334bBill Wendling CC = ARMCC::EQ; 24112bdc0dd2db145591eb3fdc01fa0b2a3d831f334bBill Wendling break; 24122bdc0dd2db145591eb3fdc01fa0b2a3d831f334bBill Wendling case ARM::VSELGTD: 24132bdc0dd2db145591eb3fdc01fa0b2a3d831f334bBill Wendling case ARM::VSELGTS: 24142bdc0dd2db145591eb3fdc01fa0b2a3d831f334bBill Wendling CC = ARMCC::GT; 24152bdc0dd2db145591eb3fdc01fa0b2a3d831f334bBill Wendling break; 24162bdc0dd2db145591eb3fdc01fa0b2a3d831f334bBill Wendling case ARM::VSELGED: 24172bdc0dd2db145591eb3fdc01fa0b2a3d831f334bBill Wendling case ARM::VSELGES: 24182bdc0dd2db145591eb3fdc01fa0b2a3d831f334bBill Wendling CC = ARMCC::GE; 24192bdc0dd2db145591eb3fdc01fa0b2a3d831f334bBill Wendling break; 24202bdc0dd2db145591eb3fdc01fa0b2a3d831f334bBill Wendling case ARM::VSELVSS: 24212bdc0dd2db145591eb3fdc01fa0b2a3d831f334bBill Wendling case ARM::VSELVSD: 24222bdc0dd2db145591eb3fdc01fa0b2a3d831f334bBill Wendling CC = ARMCC::VS; 24232bdc0dd2db145591eb3fdc01fa0b2a3d831f334bBill Wendling break; 24242bdc0dd2db145591eb3fdc01fa0b2a3d831f334bBill Wendling } 24252bdc0dd2db145591eb3fdc01fa0b2a3d831f334bBill Wendling 242676c6ccbd4cee0637c961e32435177ab89e931fedManman Ren if (Sub) { 242776c6ccbd4cee0637c961e32435177ab89e931fedManman Ren ARMCC::CondCodes NewCC = getSwappedCondition(CC); 242876c6ccbd4cee0637c961e32435177ab89e931fedManman Ren if (NewCC == ARMCC::AL) 2429247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren return false; 243076c6ccbd4cee0637c961e32435177ab89e931fedManman Ren // If we have SUB(r1, r2) and CMP(r2, r1), the condition code based 243176c6ccbd4cee0637c961e32435177ab89e931fedManman Ren // on CMP needs to be updated to be based on SUB. 243276c6ccbd4cee0637c961e32435177ab89e931fedManman Ren // Push the condition code operands to OperandsToUpdate. 243376c6ccbd4cee0637c961e32435177ab89e931fedManman Ren // If it is safe to remove CmpInstr, the condition code of these 243476c6ccbd4cee0637c961e32435177ab89e931fedManman Ren // operands will be modified. 243576c6ccbd4cee0637c961e32435177ab89e931fedManman Ren if (SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 && 24362bdc0dd2db145591eb3fdc01fa0b2a3d831f334bBill Wendling Sub->getOperand(2).getReg() == SrcReg) { 24372bdc0dd2db145591eb3fdc01fa0b2a3d831f334bBill Wendling // VSel doesn't support condition code update. 24382bdc0dd2db145591eb3fdc01fa0b2a3d831f334bBill Wendling if (IsInstrVSel) 24392bdc0dd2db145591eb3fdc01fa0b2a3d831f334bBill Wendling return false; 24402bdc0dd2db145591eb3fdc01fa0b2a3d831f334bBill Wendling OperandsToUpdate.push_back( 24412bdc0dd2db145591eb3fdc01fa0b2a3d831f334bBill Wendling std::make_pair(&((*I).getOperand(IO - 1)), NewCC)); 24422bdc0dd2db145591eb3fdc01fa0b2a3d831f334bBill Wendling } 24432bdc0dd2db145591eb3fdc01fa0b2a3d831f334bBill Wendling } else 2444247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren switch (CC) { 2445247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren default: 24469af64303fa887a3d9b75e715787ba587c3f18139Manman Ren // CPSR can be used multiple times, we should continue. 2447247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren break; 2448247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren case ARMCC::VS: 2449247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren case ARMCC::VC: 2450247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren case ARMCC::GE: 2451247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren case ARMCC::LT: 2452247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren case ARMCC::GT: 2453247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren case ARMCC::LE: 2454247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren return false; 2455247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren } 24562c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng } 24572c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng } 24582c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng 245945ed19499b8f7025d9acf91cc37fbf6ea63abc4fManman Ren // If CPSR is not killed nor re-defined, we should check whether it is 246045ed19499b8f7025d9acf91cc37fbf6ea63abc4fManman Ren // live-out. If it is live-out, do not optimize. 246145ed19499b8f7025d9acf91cc37fbf6ea63abc4fManman Ren if (!isSafe) { 246245ed19499b8f7025d9acf91cc37fbf6ea63abc4fManman Ren MachineBasicBlock *MBB = CmpInstr->getParent(); 246345ed19499b8f7025d9acf91cc37fbf6ea63abc4fManman Ren for (MachineBasicBlock::succ_iterator SI = MBB->succ_begin(), 246445ed19499b8f7025d9acf91cc37fbf6ea63abc4fManman Ren SE = MBB->succ_end(); SI != SE; ++SI) 246545ed19499b8f7025d9acf91cc37fbf6ea63abc4fManman Ren if ((*SI)->isLiveIn(ARM::CPSR)) 246645ed19499b8f7025d9acf91cc37fbf6ea63abc4fManman Ren return false; 246745ed19499b8f7025d9acf91cc37fbf6ea63abc4fManman Ren } 24682c339156289d8398bea09c2bb4b735d00d39bdb3Evan Cheng 24693642e64c114e636548888c72c21ae023ee0121a7Evan Cheng // Toggle the optional operand to CPSR. 24703642e64c114e636548888c72c21ae023ee0121a7Evan Cheng MI->getOperand(5).setReg(ARM::CPSR); 24713642e64c114e636548888c72c21ae023ee0121a7Evan Cheng MI->getOperand(5).setIsDef(true); 2472519daf5d2dd80614ac4e529b199e6f3e595bfc80Jakob Stoklund Olesen assert(!isPredicated(MI) && "Can't use flags from predicated instruction"); 2473e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling CmpInstr->eraseFromParent(); 2474247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren 2475247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren // Modify the condition code of operands in OperandsToUpdate. 2476247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren // Since we have SUB(r1, r2) and CMP(r2, r1), the condition code needs to 2477247c5ab07c1c136f37f5ad8ade9a1ee086ca452eManman Ren // be changed from r2 > r1 to r1 < r2, from r2 < r1 to r1 > r2, etc. 247876c6ccbd4cee0637c961e32435177ab89e931fedManman Ren for (unsigned i = 0, e = OperandsToUpdate.size(); i < e; i++) 247976c6ccbd4cee0637c961e32435177ab89e931fedManman Ren OperandsToUpdate[i].first->setImm(OperandsToUpdate[i].second); 2480e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling return true; 2481e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling } 2482b485de5d8c3fe0c62c0b07f63f64bd10f6803c17Cameron Zwarich } 2483e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling 2484e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling return false; 2485e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling} 24865f54ce347368105260be2cec497b6a4199dc5789Evan Cheng 2487c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Chengbool ARMBaseInstrInfo::FoldImmediate(MachineInstr *UseMI, 2488c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng MachineInstr *DefMI, unsigned Reg, 2489c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng MachineRegisterInfo *MRI) const { 2490c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng // Fold large immediates into add, sub, or, xor. 2491c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng unsigned DefOpc = DefMI->getOpcode(); 2492c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng if (DefOpc != ARM::t2MOVi32imm && DefOpc != ARM::MOVi32imm) 2493c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng return false; 2494c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng if (!DefMI->getOperand(1).isImm()) 2495c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng // Could be t2MOVi32imm <ga:xx> 2496c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng return false; 2497c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng 2498c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng if (!MRI->hasOneNonDBGUse(Reg)) 2499c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng return false; 2500c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng 2501e279f5953e9c3d934248cd4d2f24b6179ad9d2e6Evan Cheng const MCInstrDesc &DefMCID = DefMI->getDesc(); 2502e279f5953e9c3d934248cd4d2f24b6179ad9d2e6Evan Cheng if (DefMCID.hasOptionalDef()) { 2503e279f5953e9c3d934248cd4d2f24b6179ad9d2e6Evan Cheng unsigned NumOps = DefMCID.getNumOperands(); 2504e279f5953e9c3d934248cd4d2f24b6179ad9d2e6Evan Cheng const MachineOperand &MO = DefMI->getOperand(NumOps-1); 2505e279f5953e9c3d934248cd4d2f24b6179ad9d2e6Evan Cheng if (MO.getReg() == ARM::CPSR && !MO.isDead()) 2506e279f5953e9c3d934248cd4d2f24b6179ad9d2e6Evan Cheng // If DefMI defines CPSR and it is not dead, it's obviously not safe 2507e279f5953e9c3d934248cd4d2f24b6179ad9d2e6Evan Cheng // to delete DefMI. 2508e279f5953e9c3d934248cd4d2f24b6179ad9d2e6Evan Cheng return false; 2509e279f5953e9c3d934248cd4d2f24b6179ad9d2e6Evan Cheng } 2510e279f5953e9c3d934248cd4d2f24b6179ad9d2e6Evan Cheng 2511e279f5953e9c3d934248cd4d2f24b6179ad9d2e6Evan Cheng const MCInstrDesc &UseMCID = UseMI->getDesc(); 2512e279f5953e9c3d934248cd4d2f24b6179ad9d2e6Evan Cheng if (UseMCID.hasOptionalDef()) { 2513e279f5953e9c3d934248cd4d2f24b6179ad9d2e6Evan Cheng unsigned NumOps = UseMCID.getNumOperands(); 2514e279f5953e9c3d934248cd4d2f24b6179ad9d2e6Evan Cheng if (UseMI->getOperand(NumOps-1).getReg() == ARM::CPSR) 2515e279f5953e9c3d934248cd4d2f24b6179ad9d2e6Evan Cheng // If the instruction sets the flag, do not attempt this optimization 2516e279f5953e9c3d934248cd4d2f24b6179ad9d2e6Evan Cheng // since it may change the semantics of the code. 2517e279f5953e9c3d934248cd4d2f24b6179ad9d2e6Evan Cheng return false; 2518e279f5953e9c3d934248cd4d2f24b6179ad9d2e6Evan Cheng } 2519e279f5953e9c3d934248cd4d2f24b6179ad9d2e6Evan Cheng 2520c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng unsigned UseOpc = UseMI->getOpcode(); 25215c71c7a13715ed6f5bfdd5497172ddec316b68b0Evan Cheng unsigned NewUseOpc = 0; 2522c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng uint32_t ImmVal = (uint32_t)DefMI->getOperand(1).getImm(); 25235c71c7a13715ed6f5bfdd5497172ddec316b68b0Evan Cheng uint32_t SOImmValV1 = 0, SOImmValV2 = 0; 2524c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng bool Commute = false; 2525c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng switch (UseOpc) { 2526c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng default: return false; 2527c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::SUBrr: 2528c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::ADDrr: 2529c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::ORRrr: 2530c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::EORrr: 2531c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::t2SUBrr: 2532c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::t2ADDrr: 2533c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::t2ORRrr: 2534c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::t2EORrr: { 2535c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng Commute = UseMI->getOperand(2).getReg() != Reg; 2536c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng switch (UseOpc) { 2537c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng default: break; 2538c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::SUBrr: { 2539c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng if (Commute) 2540c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng return false; 2541c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng ImmVal = -ImmVal; 2542c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng NewUseOpc = ARM::SUBri; 2543c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng // Fallthrough 2544c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng } 2545c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::ADDrr: 2546c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::ORRrr: 2547c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::EORrr: { 2548c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng if (!ARM_AM::isSOImmTwoPartVal(ImmVal)) 2549c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng return false; 2550c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng SOImmValV1 = (uint32_t)ARM_AM::getSOImmTwoPartFirst(ImmVal); 2551c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng SOImmValV2 = (uint32_t)ARM_AM::getSOImmTwoPartSecond(ImmVal); 2552c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng switch (UseOpc) { 2553c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng default: break; 2554c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::ADDrr: NewUseOpc = ARM::ADDri; break; 2555c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::ORRrr: NewUseOpc = ARM::ORRri; break; 2556c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::EORrr: NewUseOpc = ARM::EORri; break; 2557c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng } 2558c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng break; 2559c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng } 2560c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::t2SUBrr: { 2561c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng if (Commute) 2562c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng return false; 2563c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng ImmVal = -ImmVal; 2564c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng NewUseOpc = ARM::t2SUBri; 2565c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng // Fallthrough 2566c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng } 2567c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::t2ADDrr: 2568c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::t2ORRrr: 2569c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::t2EORrr: { 2570c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng if (!ARM_AM::isT2SOImmTwoPartVal(ImmVal)) 2571c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng return false; 2572c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng SOImmValV1 = (uint32_t)ARM_AM::getT2SOImmTwoPartFirst(ImmVal); 2573c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng SOImmValV2 = (uint32_t)ARM_AM::getT2SOImmTwoPartSecond(ImmVal); 2574c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng switch (UseOpc) { 2575c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng default: break; 2576c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::t2ADDrr: NewUseOpc = ARM::t2ADDri; break; 2577c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::t2ORRrr: NewUseOpc = ARM::t2ORRri; break; 2578c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng case ARM::t2EORrr: NewUseOpc = ARM::t2EORri; break; 2579c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng } 2580c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng break; 2581c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng } 2582c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng } 2583c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng } 2584c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng } 2585c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng 2586c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng unsigned OpIdx = Commute ? 2 : 1; 2587c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng unsigned Reg1 = UseMI->getOperand(OpIdx).getReg(); 2588c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng bool isKill = UseMI->getOperand(OpIdx).isKill(); 2589c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng unsigned NewReg = MRI->createVirtualRegister(MRI->getRegClass(Reg)); 2590c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng AddDefaultCC(AddDefaultPred(BuildMI(*UseMI->getParent(), 2591ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng UseMI, UseMI->getDebugLoc(), 2592c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng get(NewUseOpc), NewReg) 2593c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng .addReg(Reg1, getKillRegState(isKill)) 2594c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng .addImm(SOImmValV1))); 2595c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng UseMI->setDesc(get(NewUseOpc)); 2596c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng UseMI->getOperand(1).setReg(NewReg); 2597c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng UseMI->getOperand(1).setIsKill(); 2598c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng UseMI->getOperand(2).ChangeToImmediate(SOImmValV2); 2599c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng DefMI->eraseFromParent(); 2600c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng return true; 2601c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng} 2602c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng 2603eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilsonstatic unsigned getNumMicroOpsSwiftLdSt(const InstrItineraryData *ItinData, 2604eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson const MachineInstr *MI) { 2605eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson switch (MI->getOpcode()) { 2606eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson default: { 2607eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson const MCInstrDesc &Desc = MI->getDesc(); 2608eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson int UOps = ItinData->getNumMicroOps(Desc.getSchedClass()); 2609eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson assert(UOps >= 0 && "bad # UOps"); 2610eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson return UOps; 2611eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson } 2612eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson 2613eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::LDRrs: 2614eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::LDRBrs: 2615eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::STRrs: 2616eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::STRBrs: { 2617eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson unsigned ShOpVal = MI->getOperand(3).getImm(); 2618eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson bool isSub = ARM_AM::getAM2Op(ShOpVal) == ARM_AM::sub; 2619eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal); 2620eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson if (!isSub && 2621eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson (ShImm == 0 || 2622eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson ((ShImm == 1 || ShImm == 2 || ShImm == 3) && 2623eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl))) 2624eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson return 1; 2625eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson return 2; 2626eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson } 2627eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson 2628eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::LDRH: 2629eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::STRH: { 2630eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson if (!MI->getOperand(2).getReg()) 2631eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson return 1; 2632eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson 2633eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson unsigned ShOpVal = MI->getOperand(3).getImm(); 2634eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson bool isSub = ARM_AM::getAM2Op(ShOpVal) == ARM_AM::sub; 2635eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal); 2636eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson if (!isSub && 2637eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson (ShImm == 0 || 2638eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson ((ShImm == 1 || ShImm == 2 || ShImm == 3) && 2639eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl))) 2640eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson return 1; 2641eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson return 2; 2642eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson } 2643eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson 2644eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::LDRSB: 2645eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::LDRSH: 2646eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson return (ARM_AM::getAM3Op(MI->getOperand(3).getImm()) == ARM_AM::sub) ? 3:2; 2647eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson 2648eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::LDRSB_POST: 2649eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::LDRSH_POST: { 2650eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson unsigned Rt = MI->getOperand(0).getReg(); 2651eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson unsigned Rm = MI->getOperand(3).getReg(); 2652eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson return (Rt == Rm) ? 4 : 3; 2653eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson } 2654eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson 2655eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::LDR_PRE_REG: 2656eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::LDRB_PRE_REG: { 2657eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson unsigned Rt = MI->getOperand(0).getReg(); 2658eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson unsigned Rm = MI->getOperand(3).getReg(); 2659eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson if (Rt == Rm) 2660eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson return 3; 2661eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson unsigned ShOpVal = MI->getOperand(4).getImm(); 2662eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson bool isSub = ARM_AM::getAM2Op(ShOpVal) == ARM_AM::sub; 2663eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal); 2664eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson if (!isSub && 2665eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson (ShImm == 0 || 2666eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson ((ShImm == 1 || ShImm == 2 || ShImm == 3) && 2667eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl))) 2668eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson return 2; 2669eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson return 3; 2670eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson } 2671eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson 2672eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::STR_PRE_REG: 2673eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::STRB_PRE_REG: { 2674eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson unsigned ShOpVal = MI->getOperand(4).getImm(); 2675eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson bool isSub = ARM_AM::getAM2Op(ShOpVal) == ARM_AM::sub; 2676eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal); 2677eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson if (!isSub && 2678eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson (ShImm == 0 || 2679eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson ((ShImm == 1 || ShImm == 2 || ShImm == 3) && 2680eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl))) 2681eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson return 2; 2682eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson return 3; 2683eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson } 2684eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson 2685eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::LDRH_PRE: 2686eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::STRH_PRE: { 2687eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson unsigned Rt = MI->getOperand(0).getReg(); 2688eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson unsigned Rm = MI->getOperand(3).getReg(); 2689eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson if (!Rm) 2690eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson return 2; 2691eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson if (Rt == Rm) 2692eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson return 3; 2693eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson return (ARM_AM::getAM3Op(MI->getOperand(4).getImm()) == ARM_AM::sub) 2694eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson ? 3 : 2; 2695eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson } 2696eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson 2697eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::LDR_POST_REG: 2698eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::LDRB_POST_REG: 2699eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::LDRH_POST: { 2700eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson unsigned Rt = MI->getOperand(0).getReg(); 2701eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson unsigned Rm = MI->getOperand(3).getReg(); 2702eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson return (Rt == Rm) ? 3 : 2; 2703eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson } 2704eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson 2705eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::LDR_PRE_IMM: 2706eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::LDRB_PRE_IMM: 2707eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::LDR_POST_IMM: 2708eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::LDRB_POST_IMM: 2709eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::STRB_POST_IMM: 2710eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::STRB_POST_REG: 2711eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::STRB_PRE_IMM: 2712eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::STRH_POST: 2713eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::STR_POST_IMM: 2714eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::STR_POST_REG: 2715eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::STR_PRE_IMM: 2716eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson return 2; 2717eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson 2718eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::LDRSB_PRE: 2719eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::LDRSH_PRE: { 2720eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson unsigned Rm = MI->getOperand(3).getReg(); 2721eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson if (Rm == 0) 2722eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson return 3; 2723eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson unsigned Rt = MI->getOperand(0).getReg(); 2724eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson if (Rt == Rm) 2725eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson return 4; 2726eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson unsigned ShOpVal = MI->getOperand(4).getImm(); 2727eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson bool isSub = ARM_AM::getAM2Op(ShOpVal) == ARM_AM::sub; 2728eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal); 2729eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson if (!isSub && 2730eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson (ShImm == 0 || 2731eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson ((ShImm == 1 || ShImm == 2 || ShImm == 3) && 2732eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl))) 2733eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson return 3; 2734eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson return 4; 2735eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson } 2736eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson 2737eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::LDRD: { 2738eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson unsigned Rt = MI->getOperand(0).getReg(); 2739eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson unsigned Rn = MI->getOperand(2).getReg(); 2740eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson unsigned Rm = MI->getOperand(3).getReg(); 2741eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson if (Rm) 2742eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson return (ARM_AM::getAM3Op(MI->getOperand(4).getImm()) == ARM_AM::sub) ?4:3; 2743eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson return (Rt == Rn) ? 3 : 2; 2744eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson } 2745eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson 2746eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::STRD: { 2747eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson unsigned Rm = MI->getOperand(3).getReg(); 2748eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson if (Rm) 2749eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson return (ARM_AM::getAM3Op(MI->getOperand(4).getImm()) == ARM_AM::sub) ?4:3; 2750eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson return 2; 2751eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson } 2752eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson 2753eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::LDRD_POST: 2754eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::t2LDRD_POST: 2755eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson return 3; 2756eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson 2757eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::STRD_POST: 2758eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::t2STRD_POST: 2759eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson return 4; 2760eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson 2761eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::LDRD_PRE: { 2762eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson unsigned Rt = MI->getOperand(0).getReg(); 2763eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson unsigned Rn = MI->getOperand(3).getReg(); 2764eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson unsigned Rm = MI->getOperand(4).getReg(); 2765eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson if (Rm) 2766eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson return (ARM_AM::getAM3Op(MI->getOperand(5).getImm()) == ARM_AM::sub) ?5:4; 2767eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson return (Rt == Rn) ? 4 : 3; 2768eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson } 2769eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson 2770eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::t2LDRD_PRE: { 2771eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson unsigned Rt = MI->getOperand(0).getReg(); 2772eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson unsigned Rn = MI->getOperand(3).getReg(); 2773eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson return (Rt == Rn) ? 4 : 3; 2774eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson } 2775eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson 2776eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::STRD_PRE: { 2777eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson unsigned Rm = MI->getOperand(4).getReg(); 2778eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson if (Rm) 2779eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson return (ARM_AM::getAM3Op(MI->getOperand(5).getImm()) == ARM_AM::sub) ?5:4; 2780eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson return 3; 2781eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson } 2782eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson 2783eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::t2STRD_PRE: 2784eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson return 3; 2785eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson 2786eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::t2LDR_POST: 2787eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::t2LDRB_POST: 2788eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::t2LDRB_PRE: 2789eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::t2LDRSBi12: 2790eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::t2LDRSBi8: 2791eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::t2LDRSBpci: 2792eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::t2LDRSBs: 2793eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::t2LDRH_POST: 2794eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::t2LDRH_PRE: 2795eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::t2LDRSBT: 2796eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::t2LDRSB_POST: 2797eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::t2LDRSB_PRE: 2798eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::t2LDRSH_POST: 2799eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::t2LDRSH_PRE: 2800eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::t2LDRSHi12: 2801eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::t2LDRSHi8: 2802eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::t2LDRSHpci: 2803eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::t2LDRSHs: 2804eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson return 2; 2805eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson 2806eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::t2LDRDi8: { 2807eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson unsigned Rt = MI->getOperand(0).getReg(); 2808eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson unsigned Rn = MI->getOperand(2).getReg(); 2809eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson return (Rt == Rn) ? 3 : 2; 2810eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson } 2811eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson 2812eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::t2STRB_POST: 2813eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::t2STRB_PRE: 2814eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::t2STRBs: 2815eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::t2STRDi8: 2816eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::t2STRH_POST: 2817eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::t2STRH_PRE: 2818eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::t2STRHs: 2819eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::t2STR_POST: 2820eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::t2STR_PRE: 2821eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::t2STRs: 2822eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson return 2; 2823eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson } 2824eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson} 2825eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson 28269eed53379f19f836769a0c4a14042eeb1b587769Andrew Trick// Return the number of 32-bit words loaded by LDM or stored by STM. If this 28279eed53379f19f836769a0c4a14042eeb1b587769Andrew Trick// can't be easily determined return 0 (missing MachineMemOperand). 28289eed53379f19f836769a0c4a14042eeb1b587769Andrew Trick// 28299eed53379f19f836769a0c4a14042eeb1b587769Andrew Trick// FIXME: The current MachineInstr design does not support relying on machine 28309eed53379f19f836769a0c4a14042eeb1b587769Andrew Trick// mem operands to determine the width of a memory access. Instead, we expect 28319eed53379f19f836769a0c4a14042eeb1b587769Andrew Trick// the target to provide this information based on the instruction opcode and 28329eed53379f19f836769a0c4a14042eeb1b587769Andrew Trick// operands. However, using MachineMemOperand is a the best solution now for 28339eed53379f19f836769a0c4a14042eeb1b587769Andrew Trick// two reasons: 28349eed53379f19f836769a0c4a14042eeb1b587769Andrew Trick// 28359eed53379f19f836769a0c4a14042eeb1b587769Andrew Trick// 1) getNumMicroOps tries to infer LDM memory width from the total number of MI 28369eed53379f19f836769a0c4a14042eeb1b587769Andrew Trick// operands. This is much more dangerous than using the MachineMemOperand 28379eed53379f19f836769a0c4a14042eeb1b587769Andrew Trick// sizes because CodeGen passes can insert/remove optional machine operands. In 28389eed53379f19f836769a0c4a14042eeb1b587769Andrew Trick// fact, it's totally incorrect for preRA passes and appears to be wrong for 28399eed53379f19f836769a0c4a14042eeb1b587769Andrew Trick// postRA passes as well. 28409eed53379f19f836769a0c4a14042eeb1b587769Andrew Trick// 28419eed53379f19f836769a0c4a14042eeb1b587769Andrew Trick// 2) getNumLDMAddresses is only used by the scheduling machine model and any 28429eed53379f19f836769a0c4a14042eeb1b587769Andrew Trick// machine model that calls this should handle the unknown (zero size) case. 28439eed53379f19f836769a0c4a14042eeb1b587769Andrew Trick// 28449eed53379f19f836769a0c4a14042eeb1b587769Andrew Trick// Long term, we should require a target hook that verifies MachineMemOperand 28459eed53379f19f836769a0c4a14042eeb1b587769Andrew Trick// sizes during MC lowering. That target hook should be local to MC lowering 28469eed53379f19f836769a0c4a14042eeb1b587769Andrew Trick// because we can't ensure that it is aware of other MI forms. Doing this will 28479eed53379f19f836769a0c4a14042eeb1b587769Andrew Trick// ensure that MachineMemOperands are correctly propagated through all passes. 28489eed53379f19f836769a0c4a14042eeb1b587769Andrew Trickunsigned ARMBaseInstrInfo::getNumLDMAddresses(const MachineInstr *MI) const { 28499eed53379f19f836769a0c4a14042eeb1b587769Andrew Trick unsigned Size = 0; 28509eed53379f19f836769a0c4a14042eeb1b587769Andrew Trick for (MachineInstr::mmo_iterator I = MI->memoperands_begin(), 28519eed53379f19f836769a0c4a14042eeb1b587769Andrew Trick E = MI->memoperands_end(); I != E; ++I) { 28529eed53379f19f836769a0c4a14042eeb1b587769Andrew Trick Size += (*I)->getSize(); 28539eed53379f19f836769a0c4a14042eeb1b587769Andrew Trick } 28549eed53379f19f836769a0c4a14042eeb1b587769Andrew Trick return Size / 4; 28559eed53379f19f836769a0c4a14042eeb1b587769Andrew Trick} 28569eed53379f19f836769a0c4a14042eeb1b587769Andrew Trick 28575f54ce347368105260be2cec497b6a4199dc5789Evan Chengunsigned 28588239daf7c83a65a189c352cce3191cdc3bbfe151Evan ChengARMBaseInstrInfo::getNumMicroOps(const InstrItineraryData *ItinData, 28598239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng const MachineInstr *MI) const { 28603ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng if (!ItinData || ItinData->isEmpty()) 28615f54ce347368105260be2cec497b6a4199dc5789Evan Cheng return 1; 28625f54ce347368105260be2cec497b6a4199dc5789Evan Cheng 2863e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng const MCInstrDesc &Desc = MI->getDesc(); 28645f54ce347368105260be2cec497b6a4199dc5789Evan Cheng unsigned Class = Desc.getSchedClass(); 2865218ee74a011c0d350099c452810da0bd57a15047Andrew Trick int ItinUOps = ItinData->getNumMicroOps(Class); 2866eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson if (ItinUOps >= 0) { 2867eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson if (Subtarget.isSwift() && (Desc.mayLoad() || Desc.mayStore())) 2868eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson return getNumMicroOpsSwiftLdSt(ItinData, MI); 2869eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson 2870218ee74a011c0d350099c452810da0bd57a15047Andrew Trick return ItinUOps; 2871eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson } 28725f54ce347368105260be2cec497b6a4199dc5789Evan Cheng 28735f54ce347368105260be2cec497b6a4199dc5789Evan Cheng unsigned Opc = MI->getOpcode(); 28745f54ce347368105260be2cec497b6a4199dc5789Evan Cheng switch (Opc) { 28755f54ce347368105260be2cec497b6a4199dc5789Evan Cheng default: 28765f54ce347368105260be2cec497b6a4199dc5789Evan Cheng llvm_unreachable("Unexpected multi-uops instruction!"); 287773fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMQIA: 287873fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMQIA: 28795f54ce347368105260be2cec497b6a4199dc5789Evan Cheng return 2; 28805f54ce347368105260be2cec497b6a4199dc5789Evan Cheng 28815f54ce347368105260be2cec497b6a4199dc5789Evan Cheng // The number of uOps for load / store multiple are determined by the number 28825f54ce347368105260be2cec497b6a4199dc5789Evan Cheng // registers. 28836e8f4c404825b79f9b9176483653f1aa927dfbdeAndrew Trick // 28843ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng // On Cortex-A8, each pair of register loads / stores can be scheduled on the 28853ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng // same cycle. The scheduling for the first load / store must be done 2886c8e41c591741b3da1077f7000274ad040bef8002Sylvestre Ledru // separately by assuming the address is not 64-bit aligned. 288773fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling // 28883ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng // On Cortex-A9, the formula is simply (#reg / 2) + (#reg % 2). If the address 288973fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling // is not 64-bit aligned, then AGU would take an extra cycle. For VFP / NEON 289073fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling // load / store multiple, the formula is (#reg / 2) + (#reg % 2) + 1. 289173fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMDIA: 289273fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMDIA_UPD: 289373fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMDDB_UPD: 289473fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMSIA: 289573fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMSIA_UPD: 289673fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMSDB_UPD: 289773fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMDIA: 289873fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMDIA_UPD: 289973fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMDDB_UPD: 290073fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMSIA: 290173fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMSIA_UPD: 290273fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMSDB_UPD: { 29035f54ce347368105260be2cec497b6a4199dc5789Evan Cheng unsigned NumRegs = MI->getNumOperands() - Desc.getNumOperands(); 29045f54ce347368105260be2cec497b6a4199dc5789Evan Cheng return (NumRegs / 2) + (NumRegs % 2) + 1; 29055f54ce347368105260be2cec497b6a4199dc5789Evan Cheng } 290673fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling 290773fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMIA_RET: 290873fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMIA: 290973fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMDA: 291073fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMDB: 291173fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMIB: 291273fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMIA_UPD: 291373fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMDA_UPD: 291473fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMDB_UPD: 291573fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMIB_UPD: 291673fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::STMIA: 291773fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::STMDA: 291873fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::STMDB: 291973fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::STMIB: 292073fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::STMIA_UPD: 292173fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::STMDA_UPD: 292273fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::STMDB_UPD: 292373fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::STMIB_UPD: 292473fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::tLDMIA: 292573fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::tLDMIA_UPD: 292673fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::tSTMIA_UPD: 29275f54ce347368105260be2cec497b6a4199dc5789Evan Cheng case ARM::tPOP_RET: 29285f54ce347368105260be2cec497b6a4199dc5789Evan Cheng case ARM::tPOP: 29295f54ce347368105260be2cec497b6a4199dc5789Evan Cheng case ARM::tPUSH: 293073fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2LDMIA_RET: 293173fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2LDMIA: 293273fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2LDMDB: 293373fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2LDMIA_UPD: 293473fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2LDMDB_UPD: 293573fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2STMIA: 293673fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2STMDB: 293773fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2STMIA_UPD: 293873fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2STMDB_UPD: { 29393ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng unsigned NumRegs = MI->getNumOperands() - Desc.getNumOperands() + 1; 2940eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson if (Subtarget.isSwift()) { 2941eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson int UOps = 1 + NumRegs; // One for address computation, one for each ld / st. 2942eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson switch (Opc) { 2943eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson default: break; 2944eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::VLDMDIA_UPD: 2945eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::VLDMDDB_UPD: 2946eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::VLDMSIA_UPD: 2947eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::VLDMSDB_UPD: 2948eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::VSTMDIA_UPD: 2949eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::VSTMDDB_UPD: 2950eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::VSTMSIA_UPD: 2951eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::VSTMSDB_UPD: 2952eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::LDMIA_UPD: 2953eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::LDMDA_UPD: 2954eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::LDMDB_UPD: 2955eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::LDMIB_UPD: 2956eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::STMIA_UPD: 2957eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::STMDA_UPD: 2958eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::STMDB_UPD: 2959eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::STMIB_UPD: 2960eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::tLDMIA_UPD: 2961eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::tSTMIA_UPD: 2962eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::t2LDMIA_UPD: 2963eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::t2LDMDB_UPD: 2964eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::t2STMIA_UPD: 2965eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::t2STMDB_UPD: 2966eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson ++UOps; // One for base register writeback. 2967eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson break; 2968eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::LDMIA_RET: 2969eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::tPOP_RET: 2970eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::t2LDMIA_RET: 2971eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson UOps += 2; // One for base reg wb, one for write to pc. 2972eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson break; 2973eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson } 2974eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson return UOps; 297536b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines } else if (Subtarget.isCortexA8() || Subtarget.isCortexA7()) { 29768239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng if (NumRegs < 4) 29778239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng return 2; 29788239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng // 4 registers would be issued: 2, 2. 29798239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng // 5 registers would be issued: 2, 2, 1. 2980218ee74a011c0d350099c452810da0bd57a15047Andrew Trick int A8UOps = (NumRegs / 2); 29818239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng if (NumRegs % 2) 2982218ee74a011c0d350099c452810da0bd57a15047Andrew Trick ++A8UOps; 2983218ee74a011c0d350099c452810da0bd57a15047Andrew Trick return A8UOps; 2984eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson } else if (Subtarget.isLikeA9() || Subtarget.isSwift()) { 2985218ee74a011c0d350099c452810da0bd57a15047Andrew Trick int A9UOps = (NumRegs / 2); 29863ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng // If there are odd number of registers or if it's not 64-bit aligned, 29873ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng // then it takes an extra AGU (Address Generation Unit) cycle. 29883ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng if ((NumRegs % 2) || 29893ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng !MI->hasOneMemOperand() || 29903ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng (*MI->memoperands_begin())->getAlignment() < 8) 2991218ee74a011c0d350099c452810da0bd57a15047Andrew Trick ++A9UOps; 2992218ee74a011c0d350099c452810da0bd57a15047Andrew Trick return A9UOps; 29933ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng } else { 29943ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng // Assume the worst. 29953ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng return NumRegs; 29962bbb76909126db5bed6bde84b16d94ab5de4d372Michael J. Spencer } 29975f54ce347368105260be2cec497b6a4199dc5789Evan Cheng } 29985f54ce347368105260be2cec497b6a4199dc5789Evan Cheng } 29995f54ce347368105260be2cec497b6a4199dc5789Evan Cheng} 3000a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng 3001a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Chengint 3002344d9db97062736cd66da6c07baa9108b6cfa419Evan ChengARMBaseInstrInfo::getVLDMDefCycle(const InstrItineraryData *ItinData, 3003e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng const MCInstrDesc &DefMCID, 3004344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng unsigned DefClass, 3005344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng unsigned DefIdx, unsigned DefAlign) const { 3006e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng int RegNo = (int)(DefIdx+1) - DefMCID.getNumOperands() + 1; 3007344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng if (RegNo <= 0) 3008344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // Def is the address writeback. 3009344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng return ItinData->getOperandCycle(DefClass, DefIdx); 3010344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng 3011344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng int DefCycle; 301236b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines if (Subtarget.isCortexA8() || Subtarget.isCortexA7()) { 3013344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // (regno / 2) + (regno % 2) + 1 3014344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng DefCycle = RegNo / 2 + 1; 3015344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng if (RegNo % 2) 3016344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng ++DefCycle; 3017eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson } else if (Subtarget.isLikeA9() || Subtarget.isSwift()) { 3018344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng DefCycle = RegNo; 3019344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng bool isSLoad = false; 302073fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling 3021e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng switch (DefMCID.getOpcode()) { 3022344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng default: break; 302373fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMSIA: 302473fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMSIA_UPD: 302573fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMSDB_UPD: 3026344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng isSLoad = true; 3027344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng break; 3028344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng } 302973fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling 3030344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // If there are odd number of 'S' registers or if it's not 64-bit aligned, 3031344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // then it takes an extra cycle. 3032344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng if ((isSLoad && (RegNo % 2)) || DefAlign < 8) 3033344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng ++DefCycle; 3034344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng } else { 3035344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // Assume the worst. 3036344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng DefCycle = RegNo + 2; 3037344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng } 3038344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng 3039344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng return DefCycle; 3040344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng} 3041344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng 3042344d9db97062736cd66da6c07baa9108b6cfa419Evan Chengint 3043344d9db97062736cd66da6c07baa9108b6cfa419Evan ChengARMBaseInstrInfo::getLDMDefCycle(const InstrItineraryData *ItinData, 3044e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng const MCInstrDesc &DefMCID, 3045344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng unsigned DefClass, 3046344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng unsigned DefIdx, unsigned DefAlign) const { 3047e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng int RegNo = (int)(DefIdx+1) - DefMCID.getNumOperands() + 1; 3048344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng if (RegNo <= 0) 3049344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // Def is the address writeback. 3050344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng return ItinData->getOperandCycle(DefClass, DefIdx); 3051344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng 3052344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng int DefCycle; 305336b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines if (Subtarget.isCortexA8() || Subtarget.isCortexA7()) { 3054344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // 4 registers would be issued: 1, 2, 1. 3055344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // 5 registers would be issued: 1, 2, 2. 3056344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng DefCycle = RegNo / 2; 3057344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng if (DefCycle < 1) 3058344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng DefCycle = 1; 3059344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // Result latency is issue cycle + 2: E2. 3060344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng DefCycle += 2; 3061eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson } else if (Subtarget.isLikeA9() || Subtarget.isSwift()) { 3062344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng DefCycle = (RegNo / 2); 3063344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // If there are odd number of registers or if it's not 64-bit aligned, 3064344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // then it takes an extra AGU (Address Generation Unit) cycle. 3065344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng if ((RegNo % 2) || DefAlign < 8) 3066344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng ++DefCycle; 3067344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // Result latency is AGU cycles + 2. 3068344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng DefCycle += 2; 3069344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng } else { 3070344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // Assume the worst. 3071344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng DefCycle = RegNo + 2; 3072344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng } 3073344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng 3074344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng return DefCycle; 3075344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng} 3076344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng 3077344d9db97062736cd66da6c07baa9108b6cfa419Evan Chengint 3078344d9db97062736cd66da6c07baa9108b6cfa419Evan ChengARMBaseInstrInfo::getVSTMUseCycle(const InstrItineraryData *ItinData, 3079e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng const MCInstrDesc &UseMCID, 3080344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng unsigned UseClass, 3081344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng unsigned UseIdx, unsigned UseAlign) const { 3082e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng int RegNo = (int)(UseIdx+1) - UseMCID.getNumOperands() + 1; 3083344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng if (RegNo <= 0) 3084344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng return ItinData->getOperandCycle(UseClass, UseIdx); 3085344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng 3086344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng int UseCycle; 308736b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines if (Subtarget.isCortexA8() || Subtarget.isCortexA7()) { 3088344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // (regno / 2) + (regno % 2) + 1 3089344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng UseCycle = RegNo / 2 + 1; 3090344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng if (RegNo % 2) 3091344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng ++UseCycle; 3092eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson } else if (Subtarget.isLikeA9() || Subtarget.isSwift()) { 3093344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng UseCycle = RegNo; 3094344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng bool isSStore = false; 309573fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling 3096e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng switch (UseMCID.getOpcode()) { 3097344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng default: break; 309873fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMSIA: 309973fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMSIA_UPD: 310073fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMSDB_UPD: 3101344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng isSStore = true; 3102344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng break; 3103344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng } 310473fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling 3105344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // If there are odd number of 'S' registers or if it's not 64-bit aligned, 3106344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // then it takes an extra cycle. 3107344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng if ((isSStore && (RegNo % 2)) || UseAlign < 8) 3108344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng ++UseCycle; 3109344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng } else { 3110344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // Assume the worst. 3111344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng UseCycle = RegNo + 2; 3112344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng } 3113344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng 3114344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng return UseCycle; 3115344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng} 3116344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng 3117344d9db97062736cd66da6c07baa9108b6cfa419Evan Chengint 3118344d9db97062736cd66da6c07baa9108b6cfa419Evan ChengARMBaseInstrInfo::getSTMUseCycle(const InstrItineraryData *ItinData, 3119e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng const MCInstrDesc &UseMCID, 3120344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng unsigned UseClass, 3121344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng unsigned UseIdx, unsigned UseAlign) const { 3122e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng int RegNo = (int)(UseIdx+1) - UseMCID.getNumOperands() + 1; 3123344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng if (RegNo <= 0) 3124344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng return ItinData->getOperandCycle(UseClass, UseIdx); 3125344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng 3126344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng int UseCycle; 312736b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines if (Subtarget.isCortexA8() || Subtarget.isCortexA7()) { 3128344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng UseCycle = RegNo / 2; 3129344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng if (UseCycle < 2) 3130344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng UseCycle = 2; 3131344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // Read in E3. 3132344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng UseCycle += 2; 3133eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson } else if (Subtarget.isLikeA9() || Subtarget.isSwift()) { 3134344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng UseCycle = (RegNo / 2); 3135344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // If there are odd number of registers or if it's not 64-bit aligned, 3136344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // then it takes an extra AGU (Address Generation Unit) cycle. 3137344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng if ((RegNo % 2) || UseAlign < 8) 3138344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng ++UseCycle; 3139344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng } else { 3140344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng // Assume the worst. 3141344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng UseCycle = 1; 3142344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng } 3143344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng return UseCycle; 3144344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng} 3145344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng 3146344d9db97062736cd66da6c07baa9108b6cfa419Evan Chengint 3147a0792de66c8364d47b0a688c7f408efb7b10f31bEvan ChengARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData, 3148e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng const MCInstrDesc &DefMCID, 3149a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng unsigned DefIdx, unsigned DefAlign, 3150e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng const MCInstrDesc &UseMCID, 3151a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng unsigned UseIdx, unsigned UseAlign) const { 3152e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng unsigned DefClass = DefMCID.getSchedClass(); 3153e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng unsigned UseClass = UseMCID.getSchedClass(); 3154a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng 3155e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng if (DefIdx < DefMCID.getNumDefs() && UseIdx < UseMCID.getNumOperands()) 3156a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx); 3157a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng 3158a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng // This may be a def / use of a variable_ops instruction, the operand 3159a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng // latency might be determinable dynamically. Let the target try to 3160a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng // figure it out. 31619e08ee5d16b596078e20787f0b5f36121f099333Evan Cheng int DefCycle = -1; 31627e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng bool LdmBypass = false; 3163e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng switch (DefMCID.getOpcode()) { 3164a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng default: 3165a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng DefCycle = ItinData->getOperandCycle(DefClass, DefIdx); 3166a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng break; 316773fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling 316873fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMDIA: 316973fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMDIA_UPD: 317073fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMDDB_UPD: 317173fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMSIA: 317273fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMSIA_UPD: 317373fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMSDB_UPD: 3174e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng DefCycle = getVLDMDefCycle(ItinData, DefMCID, DefClass, DefIdx, DefAlign); 31755a50ceeaea980962c1982ad535226c7ab06c971cEvan Cheng break; 317673fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling 317773fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMIA_RET: 317873fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMIA: 317973fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMDA: 318073fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMDB: 318173fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMIB: 318273fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMIA_UPD: 318373fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMDA_UPD: 318473fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMDB_UPD: 318573fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::LDMIB_UPD: 318673fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::tLDMIA: 318773fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::tLDMIA_UPD: 3188a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng case ARM::tPUSH: 318973fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2LDMIA_RET: 319073fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2LDMIA: 319173fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2LDMDB: 319273fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2LDMIA_UPD: 319373fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2LDMDB_UPD: 3194a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng LdmBypass = 1; 3195e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng DefCycle = getLDMDefCycle(ItinData, DefMCID, DefClass, DefIdx, DefAlign); 3196344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng break; 3197a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng } 3198a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng 3199a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng if (DefCycle == -1) 3200a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng // We can't seem to determine the result latency of the def, assume it's 2. 3201a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng DefCycle = 2; 3202a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng 3203a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng int UseCycle = -1; 3204e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng switch (UseMCID.getOpcode()) { 3205a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng default: 3206a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng UseCycle = ItinData->getOperandCycle(UseClass, UseIdx); 3207a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng break; 320873fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling 320973fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMDIA: 321073fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMDIA_UPD: 321173fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMDDB_UPD: 321273fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMSIA: 321373fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMSIA_UPD: 321473fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMSDB_UPD: 3215e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng UseCycle = getVSTMUseCycle(ItinData, UseMCID, UseClass, UseIdx, UseAlign); 32165a50ceeaea980962c1982ad535226c7ab06c971cEvan Cheng break; 321773fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling 321873fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::STMIA: 321973fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::STMDA: 322073fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::STMDB: 322173fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::STMIB: 322273fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::STMIA_UPD: 322373fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::STMDA_UPD: 322473fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::STMDB_UPD: 322573fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::STMIB_UPD: 322673fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::tSTMIA_UPD: 3227a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng case ARM::tPOP_RET: 3228a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng case ARM::tPOP: 322973fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2STMIA: 323073fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2STMDB: 323173fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2STMIA_UPD: 323273fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::t2STMDB_UPD: 3233e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng UseCycle = getSTMUseCycle(ItinData, UseMCID, UseClass, UseIdx, UseAlign); 32345a50ceeaea980962c1982ad535226c7ab06c971cEvan Cheng break; 3235a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng } 3236a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng 3237a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng if (UseCycle == -1) 3238a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng // Assume it's read in the first stage. 3239a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng UseCycle = 1; 3240a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng 3241a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng UseCycle = DefCycle - UseCycle + 1; 3242a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng if (UseCycle > 0) { 3243a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng if (LdmBypass) { 3244a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng // It's a variable_ops instruction so we can't use DefIdx here. Just use 3245a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng // first def operand. 3246e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng if (ItinData->hasPipelineForwarding(DefClass, DefMCID.getNumOperands()-1, 3247a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng UseClass, UseIdx)) 3248a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng --UseCycle; 3249a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng } else if (ItinData->hasPipelineForwarding(DefClass, DefIdx, 325073fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling UseClass, UseIdx)) { 3251a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng --UseCycle; 325273fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling } 3253a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng } 3254a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng 3255a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng return UseCycle; 3256a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng} 3257a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng 3258ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Chengstatic const MachineInstr *getBundledDefMI(const TargetRegisterInfo *TRI, 3259020f4106f820648fd7e91956859844a80de13974Evan Cheng const MachineInstr *MI, unsigned Reg, 3260ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng unsigned &DefIdx, unsigned &Dist) { 3261ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng Dist = 0; 3262ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng 3263ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng MachineBasicBlock::const_iterator I = MI; ++I; 326436b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines MachineBasicBlock::const_instr_iterator II = std::prev(I.getInstrIterator()); 3265ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng assert(II->isInsideBundle() && "Empty bundle?"); 3266ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng 3267ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng int Idx = -1; 3268ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng while (II->isInsideBundle()) { 3269ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng Idx = II->findRegisterDefOperandIdx(Reg, false, true, TRI); 3270ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng if (Idx != -1) 3271ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng break; 3272ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng --II; 3273ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng ++Dist; 3274ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng } 3275ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng 3276ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng assert(Idx != -1 && "Cannot find bundled definition!"); 3277ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng DefIdx = Idx; 3278ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng return II; 3279ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng} 3280ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng 3281ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Chengstatic const MachineInstr *getBundledUseMI(const TargetRegisterInfo *TRI, 3282020f4106f820648fd7e91956859844a80de13974Evan Cheng const MachineInstr *MI, unsigned Reg, 3283ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng unsigned &UseIdx, unsigned &Dist) { 3284ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng Dist = 0; 3285ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng 3286ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng MachineBasicBlock::const_instr_iterator II = MI; ++II; 3287ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng assert(II->isInsideBundle() && "Empty bundle?"); 3288ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end(); 3289ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng 3290ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng // FIXME: This doesn't properly handle multiple uses. 3291ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng int Idx = -1; 3292ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng while (II != E && II->isInsideBundle()) { 3293ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng Idx = II->findRegisterUseOperandIdx(Reg, false, TRI); 3294ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng if (Idx != -1) 3295ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng break; 3296ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng if (II->getOpcode() != ARM::t2IT) 3297ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng ++Dist; 3298ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng ++II; 3299ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng } 3300ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng 3301020f4106f820648fd7e91956859844a80de13974Evan Cheng if (Idx == -1) { 3302020f4106f820648fd7e91956859844a80de13974Evan Cheng Dist = 0; 3303dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines return nullptr; 3304020f4106f820648fd7e91956859844a80de13974Evan Cheng } 3305020f4106f820648fd7e91956859844a80de13974Evan Cheng 3306ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng UseIdx = Idx; 3307ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng return II; 3308ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng} 3309ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng 331068b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick/// Return the number of cycles to add to (or subtract from) the static 331168b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick/// itinerary based on the def opcode and alignment. The caller will ensure that 331268b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick/// adjusted latency is at least one cycle. 331368b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trickstatic int adjustDefLatency(const ARMSubtarget &Subtarget, 331468b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick const MachineInstr *DefMI, 331568b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick const MCInstrDesc *DefMCID, unsigned DefAlign) { 331668b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick int Adjust = 0; 331736b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines if (Subtarget.isCortexA8() || Subtarget.isLikeA9() || Subtarget.isCortexA7()) { 33187e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng // FIXME: Shifter op hack: no shift (i.e. [r +/- r]) or [r + r << 2] 33197e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng // variants are one cycle cheaper. 3320ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng switch (DefMCID->getOpcode()) { 33217e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng default: break; 3322cff9baa95273bc279bf5fadb9e27afbd25cca20bJakob Stoklund Olesen case ARM::LDRrs: 3323cff9baa95273bc279bf5fadb9e27afbd25cca20bJakob Stoklund Olesen case ARM::LDRBrs: { 33247e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng unsigned ShOpVal = DefMI->getOperand(3).getImm(); 33257e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal); 33267e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng if (ShImm == 0 || 33277e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng (ShImm == 2 && ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl)) 332868b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick --Adjust; 33297e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng break; 33307e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng } 3331cff9baa95273bc279bf5fadb9e27afbd25cca20bJakob Stoklund Olesen case ARM::t2LDRs: 3332cff9baa95273bc279bf5fadb9e27afbd25cca20bJakob Stoklund Olesen case ARM::t2LDRBs: 3333cff9baa95273bc279bf5fadb9e27afbd25cca20bJakob Stoklund Olesen case ARM::t2LDRHs: 33347e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng case ARM::t2LDRSHs: { 33357e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng // Thumb2 mode: lsl only. 33367e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng unsigned ShAmt = DefMI->getOperand(3).getImm(); 33377e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng if (ShAmt == 0 || ShAmt == 2) 333868b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick --Adjust; 33397e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng break; 33407e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng } 33417e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng } 3342eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson } else if (Subtarget.isSwift()) { 3343eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson // FIXME: Properly handle all of the latency adjustments for address 3344eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson // writeback. 3345eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson switch (DefMCID->getOpcode()) { 3346eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson default: break; 3347eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::LDRrs: 3348eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::LDRBrs: { 3349eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson unsigned ShOpVal = DefMI->getOperand(3).getImm(); 3350eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson bool isSub = ARM_AM::getAM2Op(ShOpVal) == ARM_AM::sub; 3351eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal); 3352eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson if (!isSub && 3353eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson (ShImm == 0 || 3354eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson ((ShImm == 1 || ShImm == 2 || ShImm == 3) && 3355eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl))) 3356eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson Adjust -= 2; 3357eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson else if (!isSub && 3358eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson ShImm == 1 && ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsr) 3359eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson --Adjust; 3360eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson break; 3361eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson } 3362eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::t2LDRs: 3363eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::t2LDRBs: 3364eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::t2LDRHs: 3365eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::t2LDRSHs: { 3366eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson // Thumb2 mode: lsl only. 3367eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson unsigned ShAmt = DefMI->getOperand(3).getImm(); 3368eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson if (ShAmt == 0 || ShAmt == 1 || ShAmt == 2 || ShAmt == 3) 3369eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson Adjust -= 2; 3370eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson break; 3371eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson } 3372eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson } 33737e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng } 33747e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng 3375616471d4bfe4717fa86259ff4534703357b3b723Silviu Baranga if (DefAlign < 8 && Subtarget.isLikeA9()) { 3376ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng switch (DefMCID->getOpcode()) { 337775b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng default: break; 337875b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1q8: 337975b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1q16: 338075b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1q32: 338175b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1q64: 338210b90a9bbf7dcae1568c03a03f9606f5395f2144Jim Grosbach case ARM::VLD1q8wb_fixed: 338310b90a9bbf7dcae1568c03a03f9606f5395f2144Jim Grosbach case ARM::VLD1q16wb_fixed: 338410b90a9bbf7dcae1568c03a03f9606f5395f2144Jim Grosbach case ARM::VLD1q32wb_fixed: 338510b90a9bbf7dcae1568c03a03f9606f5395f2144Jim Grosbach case ARM::VLD1q64wb_fixed: 338610b90a9bbf7dcae1568c03a03f9606f5395f2144Jim Grosbach case ARM::VLD1q8wb_register: 338710b90a9bbf7dcae1568c03a03f9606f5395f2144Jim Grosbach case ARM::VLD1q16wb_register: 338810b90a9bbf7dcae1568c03a03f9606f5395f2144Jim Grosbach case ARM::VLD1q32wb_register: 338910b90a9bbf7dcae1568c03a03f9606f5395f2144Jim Grosbach case ARM::VLD1q64wb_register: 339075b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2d8: 339175b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2d16: 339275b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2d32: 339375b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2q8: 339475b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2q16: 339575b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2q32: 3396a4e3c7fc4ba2d55695b0484480685698132eba20Jim Grosbach case ARM::VLD2d8wb_fixed: 3397a4e3c7fc4ba2d55695b0484480685698132eba20Jim Grosbach case ARM::VLD2d16wb_fixed: 3398a4e3c7fc4ba2d55695b0484480685698132eba20Jim Grosbach case ARM::VLD2d32wb_fixed: 3399a4e3c7fc4ba2d55695b0484480685698132eba20Jim Grosbach case ARM::VLD2q8wb_fixed: 3400a4e3c7fc4ba2d55695b0484480685698132eba20Jim Grosbach case ARM::VLD2q16wb_fixed: 3401a4e3c7fc4ba2d55695b0484480685698132eba20Jim Grosbach case ARM::VLD2q32wb_fixed: 3402a4e3c7fc4ba2d55695b0484480685698132eba20Jim Grosbach case ARM::VLD2d8wb_register: 3403a4e3c7fc4ba2d55695b0484480685698132eba20Jim Grosbach case ARM::VLD2d16wb_register: 3404a4e3c7fc4ba2d55695b0484480685698132eba20Jim Grosbach case ARM::VLD2d32wb_register: 3405a4e3c7fc4ba2d55695b0484480685698132eba20Jim Grosbach case ARM::VLD2q8wb_register: 3406a4e3c7fc4ba2d55695b0484480685698132eba20Jim Grosbach case ARM::VLD2q16wb_register: 3407a4e3c7fc4ba2d55695b0484480685698132eba20Jim Grosbach case ARM::VLD2q32wb_register: 340875b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3d8: 340975b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3d16: 341075b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3d32: 341175b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1d64T: 341275b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3d8_UPD: 341375b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3d16_UPD: 341475b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3d32_UPD: 34155921675ff5ea632ab1e6d7aa5d1f263b858bbafaJim Grosbach case ARM::VLD1d64Twb_fixed: 34165921675ff5ea632ab1e6d7aa5d1f263b858bbafaJim Grosbach case ARM::VLD1d64Twb_register: 341775b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3q8_UPD: 341875b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3q16_UPD: 341975b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3q32_UPD: 342075b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4d8: 342175b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4d16: 342275b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4d32: 342375b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1d64Q: 342475b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4d8_UPD: 342575b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4d16_UPD: 342675b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4d32_UPD: 3427399cdca4d201f7232126c3a0643669971ede780aJim Grosbach case ARM::VLD1d64Qwb_fixed: 3428399cdca4d201f7232126c3a0643669971ede780aJim Grosbach case ARM::VLD1d64Qwb_register: 342975b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4q8_UPD: 343075b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4q16_UPD: 343175b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4q32_UPD: 343275b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1DUPq8: 343375b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1DUPq16: 343475b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1DUPq32: 3435096334e25ea68ac970942ecb680a82fbb8ad206cJim Grosbach case ARM::VLD1DUPq8wb_fixed: 3436096334e25ea68ac970942ecb680a82fbb8ad206cJim Grosbach case ARM::VLD1DUPq16wb_fixed: 3437096334e25ea68ac970942ecb680a82fbb8ad206cJim Grosbach case ARM::VLD1DUPq32wb_fixed: 3438096334e25ea68ac970942ecb680a82fbb8ad206cJim Grosbach case ARM::VLD1DUPq8wb_register: 3439096334e25ea68ac970942ecb680a82fbb8ad206cJim Grosbach case ARM::VLD1DUPq16wb_register: 3440096334e25ea68ac970942ecb680a82fbb8ad206cJim Grosbach case ARM::VLD1DUPq32wb_register: 344175b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2DUPd8: 344275b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2DUPd16: 344375b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2DUPd32: 3444e6949b13997e6d31aa4719a0e80c4b6b405e42a9Jim Grosbach case ARM::VLD2DUPd8wb_fixed: 3445e6949b13997e6d31aa4719a0e80c4b6b405e42a9Jim Grosbach case ARM::VLD2DUPd16wb_fixed: 3446e6949b13997e6d31aa4719a0e80c4b6b405e42a9Jim Grosbach case ARM::VLD2DUPd32wb_fixed: 3447e6949b13997e6d31aa4719a0e80c4b6b405e42a9Jim Grosbach case ARM::VLD2DUPd8wb_register: 3448e6949b13997e6d31aa4719a0e80c4b6b405e42a9Jim Grosbach case ARM::VLD2DUPd16wb_register: 3449e6949b13997e6d31aa4719a0e80c4b6b405e42a9Jim Grosbach case ARM::VLD2DUPd32wb_register: 345075b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4DUPd8: 345175b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4DUPd16: 345275b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4DUPd32: 345375b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4DUPd8_UPD: 345475b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4DUPd16_UPD: 345575b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4DUPd32_UPD: 345675b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1LNd8: 345775b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1LNd16: 345875b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1LNd32: 345975b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1LNd8_UPD: 346075b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1LNd16_UPD: 346175b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1LNd32_UPD: 346275b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2LNd8: 346375b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2LNd16: 346475b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2LNd32: 346575b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2LNq16: 346675b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2LNq32: 346775b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2LNd8_UPD: 346875b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2LNd16_UPD: 346975b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2LNd32_UPD: 347075b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2LNq16_UPD: 347175b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2LNq32_UPD: 347275b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4LNd8: 347375b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4LNd16: 347475b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4LNd32: 347575b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4LNq16: 347675b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4LNq32: 347775b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4LNd8_UPD: 347875b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4LNd16_UPD: 347975b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4LNd32_UPD: 348075b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4LNq16_UPD: 348175b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4LNq32_UPD: 348275b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng // If the address is not 64-bit aligned, the latencies of these 348375b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng // instructions increases by one. 348468b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick ++Adjust; 348575b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng break; 348675b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng } 348768b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick } 348868b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick return Adjust; 348968b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick} 349068b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick 349175b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng 349268b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick 349368b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trickint 349468b16541cc58411c7b0607ca4c0fb497222b668dAndrew TrickARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData, 349568b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick const MachineInstr *DefMI, unsigned DefIdx, 349668b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick const MachineInstr *UseMI, 349768b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick unsigned UseIdx) const { 349868b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick // No operand latency. The caller may fall back to getInstrLatency. 349968b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick if (!ItinData || ItinData->isEmpty()) 350068b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick return -1; 350168b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick 350268b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick const MachineOperand &DefMO = DefMI->getOperand(DefIdx); 350368b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick unsigned Reg = DefMO.getReg(); 350468b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick const MCInstrDesc *DefMCID = &DefMI->getDesc(); 350568b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick const MCInstrDesc *UseMCID = &UseMI->getDesc(); 350668b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick 350768b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick unsigned DefAdj = 0; 350868b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick if (DefMI->isBundle()) { 350968b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick DefMI = getBundledDefMI(&getRegisterInfo(), DefMI, Reg, DefIdx, DefAdj); 351068b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick DefMCID = &DefMI->getDesc(); 351168b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick } 351268b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick if (DefMI->isCopyLike() || DefMI->isInsertSubreg() || 351368b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick DefMI->isRegSequence() || DefMI->isImplicitDef()) { 351468b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick return 1; 351568b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick } 351668b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick 351768b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick unsigned UseAdj = 0; 351868b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick if (UseMI->isBundle()) { 351968b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick unsigned NewUseIdx; 352068b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick const MachineInstr *NewUseMI = getBundledUseMI(&getRegisterInfo(), UseMI, 352168b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick Reg, NewUseIdx, UseAdj); 3522e2b32bb20ee76f24708b3c9e19b6fbc651c25637Andrew Trick if (!NewUseMI) 3523e2b32bb20ee76f24708b3c9e19b6fbc651c25637Andrew Trick return -1; 3524e2b32bb20ee76f24708b3c9e19b6fbc651c25637Andrew Trick 3525e2b32bb20ee76f24708b3c9e19b6fbc651c25637Andrew Trick UseMI = NewUseMI; 3526e2b32bb20ee76f24708b3c9e19b6fbc651c25637Andrew Trick UseIdx = NewUseIdx; 3527e2b32bb20ee76f24708b3c9e19b6fbc651c25637Andrew Trick UseMCID = &UseMI->getDesc(); 352868b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick } 352968b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick 353068b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick if (Reg == ARM::CPSR) { 353168b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick if (DefMI->getOpcode() == ARM::FMSTAT) { 353268b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick // fpscr -> cpsr stalls over 20 cycles on A8 (and earlier?) 3533616471d4bfe4717fa86259ff4534703357b3b723Silviu Baranga return Subtarget.isLikeA9() ? 1 : 20; 353468b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick } 353568b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick 353668b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick // CPSR set and branch can be paired in the same cycle. 353768b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick if (UseMI->isBranch()) 353868b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick return 0; 353968b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick 354068b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick // Otherwise it takes the instruction latency (generally one). 354168b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick unsigned Latency = getInstrLatency(ItinData, DefMI); 354268b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick 354368b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick // For Thumb2 and -Os, prefer scheduling CPSR setting instruction close to 354468b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick // its uses. Instructions which are otherwise scheduled between them may 354568b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick // incur a code size penalty (not able to use the CPSR setting 16-bit 354668b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick // instructions). 354768b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick if (Latency > 0 && Subtarget.isThumb2()) { 354868b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick const MachineFunction *MF = DefMI->getParent()->getParent(); 3549831737d329a727f53a1fb0572f7b7a8127208881Bill Wendling if (MF->getFunction()->getAttributes(). 3550831737d329a727f53a1fb0572f7b7a8127208881Bill Wendling hasAttribute(AttributeSet::FunctionIndex, 3551831737d329a727f53a1fb0572f7b7a8127208881Bill Wendling Attribute::OptimizeForSize)) 355268b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick --Latency; 355368b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick } 355468b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick return Latency; 355568b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick } 355668b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick 3557e2b32bb20ee76f24708b3c9e19b6fbc651c25637Andrew Trick if (DefMO.isImplicit() || UseMI->getOperand(UseIdx).isImplicit()) 3558e2b32bb20ee76f24708b3c9e19b6fbc651c25637Andrew Trick return -1; 3559e2b32bb20ee76f24708b3c9e19b6fbc651c25637Andrew Trick 356068b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick unsigned DefAlign = DefMI->hasOneMemOperand() 356168b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick ? (*DefMI->memoperands_begin())->getAlignment() : 0; 356268b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick unsigned UseAlign = UseMI->hasOneMemOperand() 356368b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick ? (*UseMI->memoperands_begin())->getAlignment() : 0; 356468b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick 356568b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick // Get the itinerary's latency if possible, and handle variable_ops. 356668b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick int Latency = getOperandLatency(ItinData, *DefMCID, DefIdx, DefAlign, 356768b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick *UseMCID, UseIdx, UseAlign); 356868b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick // Unable to find operand latency. The caller may resort to getInstrLatency. 356968b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick if (Latency < 0) 357068b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick return Latency; 357168b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick 357268b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick // Adjust for IT block position. 357368b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick int Adj = DefAdj + UseAdj; 357468b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick 357568b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick // Adjust for dynamic def-side opcode variants not captured by the itinerary. 357668b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick Adj += adjustDefLatency(Subtarget, DefMI, DefMCID, DefAlign); 357768b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick if (Adj >= 0 || (int)Latency > -Adj) { 357868b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick return Latency + Adj; 357968b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick } 358068b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick // Return the itinerary latency, which may be zero but not less than zero. 35817e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng return Latency; 3582a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng} 3583a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng 3584a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Chengint 3585a0792de66c8364d47b0a688c7f408efb7b10f31bEvan ChengARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData, 3586a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng SDNode *DefNode, unsigned DefIdx, 3587a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng SDNode *UseNode, unsigned UseIdx) const { 3588a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng if (!DefNode->isMachineOpcode()) 3589a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng return 1; 3590a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng 3591e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng const MCInstrDesc &DefMCID = get(DefNode->getMachineOpcode()); 3592c8bfd1d78ff9a307d1d4cb57cce4549b538e60f4Andrew Trick 3593e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng if (isZeroCost(DefMCID.Opcode)) 3594c8bfd1d78ff9a307d1d4cb57cce4549b538e60f4Andrew Trick return 0; 3595c8bfd1d78ff9a307d1d4cb57cce4549b538e60f4Andrew Trick 3596a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng if (!ItinData || ItinData->isEmpty()) 3597e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng return DefMCID.mayLoad() ? 3 : 1; 3598a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng 3599089751535d6e9adf65842e2ca5867bf9a70e1e95Evan Cheng if (!UseNode->isMachineOpcode()) { 3600e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng int Latency = ItinData->getOperandCycle(DefMCID.getSchedClass(), DefIdx); 3601eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson if (Subtarget.isLikeA9() || Subtarget.isSwift()) 3602089751535d6e9adf65842e2ca5867bf9a70e1e95Evan Cheng return Latency <= 2 ? 1 : Latency - 1; 3603089751535d6e9adf65842e2ca5867bf9a70e1e95Evan Cheng else 3604089751535d6e9adf65842e2ca5867bf9a70e1e95Evan Cheng return Latency <= 3 ? 1 : Latency - 2; 3605089751535d6e9adf65842e2ca5867bf9a70e1e95Evan Cheng } 3606a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng 3607e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng const MCInstrDesc &UseMCID = get(UseNode->getMachineOpcode()); 3608a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng const MachineSDNode *DefMN = dyn_cast<MachineSDNode>(DefNode); 3609a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng unsigned DefAlign = !DefMN->memoperands_empty() 3610a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng ? (*DefMN->memoperands_begin())->getAlignment() : 0; 3611a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng const MachineSDNode *UseMN = dyn_cast<MachineSDNode>(UseNode); 3612a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng unsigned UseAlign = !UseMN->memoperands_empty() 3613a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng ? (*UseMN->memoperands_begin())->getAlignment() : 0; 3614e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng int Latency = getOperandLatency(ItinData, DefMCID, DefIdx, DefAlign, 3615e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng UseMCID, UseIdx, UseAlign); 36167e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng 36177e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng if (Latency > 1 && 361836b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines (Subtarget.isCortexA8() || Subtarget.isLikeA9() || 361936b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines Subtarget.isCortexA7())) { 36207e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng // FIXME: Shifter op hack: no shift (i.e. [r +/- r]) or [r + r << 2] 36217e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng // variants are one cycle cheaper. 3622e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng switch (DefMCID.getOpcode()) { 36237e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng default: break; 3624cff9baa95273bc279bf5fadb9e27afbd25cca20bJakob Stoklund Olesen case ARM::LDRrs: 3625cff9baa95273bc279bf5fadb9e27afbd25cca20bJakob Stoklund Olesen case ARM::LDRBrs: { 36267e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng unsigned ShOpVal = 36277e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng cast<ConstantSDNode>(DefNode->getOperand(2))->getZExtValue(); 36287e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal); 36297e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng if (ShImm == 0 || 36307e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng (ShImm == 2 && ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl)) 36317e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng --Latency; 36327e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng break; 36337e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng } 3634cff9baa95273bc279bf5fadb9e27afbd25cca20bJakob Stoklund Olesen case ARM::t2LDRs: 3635cff9baa95273bc279bf5fadb9e27afbd25cca20bJakob Stoklund Olesen case ARM::t2LDRBs: 3636cff9baa95273bc279bf5fadb9e27afbd25cca20bJakob Stoklund Olesen case ARM::t2LDRHs: 36377e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng case ARM::t2LDRSHs: { 36387e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng // Thumb2 mode: lsl only. 36397e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng unsigned ShAmt = 36407e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng cast<ConstantSDNode>(DefNode->getOperand(2))->getZExtValue(); 36417e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng if (ShAmt == 0 || ShAmt == 2) 36427e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng --Latency; 36437e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng break; 36447e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng } 36457e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng } 3646eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson } else if (DefIdx == 0 && Latency > 2 && Subtarget.isSwift()) { 3647eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson // FIXME: Properly handle all of the latency adjustments for address 3648eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson // writeback. 3649eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson switch (DefMCID.getOpcode()) { 3650eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson default: break; 3651eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::LDRrs: 3652eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::LDRBrs: { 3653eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson unsigned ShOpVal = 3654eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson cast<ConstantSDNode>(DefNode->getOperand(2))->getZExtValue(); 3655eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal); 3656eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson if (ShImm == 0 || 3657eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson ((ShImm == 1 || ShImm == 2 || ShImm == 3) && 3658eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl)) 3659eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson Latency -= 2; 3660eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson else if (ShImm == 1 && ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsr) 3661eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson --Latency; 3662eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson break; 3663eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson } 3664eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::t2LDRs: 3665eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::t2LDRBs: 3666eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::t2LDRHs: 3667eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::t2LDRSHs: { 3668eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson // Thumb2 mode: lsl 0-3 only. 3669eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson Latency -= 2; 3670eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson break; 3671eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson } 3672eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson } 36737e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng } 36747e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng 3675616471d4bfe4717fa86259ff4534703357b3b723Silviu Baranga if (DefAlign < 8 && Subtarget.isLikeA9()) 3676e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng switch (DefMCID.getOpcode()) { 367775b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng default: break; 367828f08c93e75d291695ea89b9004145103292e85bJim Grosbach case ARM::VLD1q8: 367928f08c93e75d291695ea89b9004145103292e85bJim Grosbach case ARM::VLD1q16: 368028f08c93e75d291695ea89b9004145103292e85bJim Grosbach case ARM::VLD1q32: 368128f08c93e75d291695ea89b9004145103292e85bJim Grosbach case ARM::VLD1q64: 368228f08c93e75d291695ea89b9004145103292e85bJim Grosbach case ARM::VLD1q8wb_register: 368328f08c93e75d291695ea89b9004145103292e85bJim Grosbach case ARM::VLD1q16wb_register: 368428f08c93e75d291695ea89b9004145103292e85bJim Grosbach case ARM::VLD1q32wb_register: 368528f08c93e75d291695ea89b9004145103292e85bJim Grosbach case ARM::VLD1q64wb_register: 368628f08c93e75d291695ea89b9004145103292e85bJim Grosbach case ARM::VLD1q8wb_fixed: 368728f08c93e75d291695ea89b9004145103292e85bJim Grosbach case ARM::VLD1q16wb_fixed: 368828f08c93e75d291695ea89b9004145103292e85bJim Grosbach case ARM::VLD1q32wb_fixed: 368928f08c93e75d291695ea89b9004145103292e85bJim Grosbach case ARM::VLD1q64wb_fixed: 369028f08c93e75d291695ea89b9004145103292e85bJim Grosbach case ARM::VLD2d8: 369128f08c93e75d291695ea89b9004145103292e85bJim Grosbach case ARM::VLD2d16: 369228f08c93e75d291695ea89b9004145103292e85bJim Grosbach case ARM::VLD2d32: 369375b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2q8Pseudo: 369475b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2q16Pseudo: 369575b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2q32Pseudo: 369628f08c93e75d291695ea89b9004145103292e85bJim Grosbach case ARM::VLD2d8wb_fixed: 369728f08c93e75d291695ea89b9004145103292e85bJim Grosbach case ARM::VLD2d16wb_fixed: 369828f08c93e75d291695ea89b9004145103292e85bJim Grosbach case ARM::VLD2d32wb_fixed: 3699a4e3c7fc4ba2d55695b0484480685698132eba20Jim Grosbach case ARM::VLD2q8PseudoWB_fixed: 3700a4e3c7fc4ba2d55695b0484480685698132eba20Jim Grosbach case ARM::VLD2q16PseudoWB_fixed: 3701a4e3c7fc4ba2d55695b0484480685698132eba20Jim Grosbach case ARM::VLD2q32PseudoWB_fixed: 370228f08c93e75d291695ea89b9004145103292e85bJim Grosbach case ARM::VLD2d8wb_register: 370328f08c93e75d291695ea89b9004145103292e85bJim Grosbach case ARM::VLD2d16wb_register: 370428f08c93e75d291695ea89b9004145103292e85bJim Grosbach case ARM::VLD2d32wb_register: 3705a4e3c7fc4ba2d55695b0484480685698132eba20Jim Grosbach case ARM::VLD2q8PseudoWB_register: 3706a4e3c7fc4ba2d55695b0484480685698132eba20Jim Grosbach case ARM::VLD2q16PseudoWB_register: 3707a4e3c7fc4ba2d55695b0484480685698132eba20Jim Grosbach case ARM::VLD2q32PseudoWB_register: 370875b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3d8Pseudo: 370975b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3d16Pseudo: 371075b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3d32Pseudo: 371175b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1d64TPseudo: 371236b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines case ARM::VLD1d64TPseudoWB_fixed: 371375b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3d8Pseudo_UPD: 371475b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3d16Pseudo_UPD: 371575b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3d32Pseudo_UPD: 371675b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3q8Pseudo_UPD: 371775b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3q16Pseudo_UPD: 371875b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3q32Pseudo_UPD: 371975b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3q8oddPseudo: 372075b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3q16oddPseudo: 372175b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3q32oddPseudo: 372275b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3q8oddPseudo_UPD: 372375b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3q16oddPseudo_UPD: 372475b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD3q32oddPseudo_UPD: 372575b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4d8Pseudo: 372675b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4d16Pseudo: 372775b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4d32Pseudo: 372875b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1d64QPseudo: 372936b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines case ARM::VLD1d64QPseudoWB_fixed: 373075b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4d8Pseudo_UPD: 373175b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4d16Pseudo_UPD: 373275b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4d32Pseudo_UPD: 373375b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4q8Pseudo_UPD: 373475b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4q16Pseudo_UPD: 373575b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4q32Pseudo_UPD: 373675b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4q8oddPseudo: 373775b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4q16oddPseudo: 373875b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4q32oddPseudo: 373975b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4q8oddPseudo_UPD: 374075b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4q16oddPseudo_UPD: 374175b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4q32oddPseudo_UPD: 3742c0fc450f0754508871bc70f21e528bf2f1520da1Jim Grosbach case ARM::VLD1DUPq8: 3743c0fc450f0754508871bc70f21e528bf2f1520da1Jim Grosbach case ARM::VLD1DUPq16: 3744c0fc450f0754508871bc70f21e528bf2f1520da1Jim Grosbach case ARM::VLD1DUPq32: 3745c0fc450f0754508871bc70f21e528bf2f1520da1Jim Grosbach case ARM::VLD1DUPq8wb_fixed: 3746c0fc450f0754508871bc70f21e528bf2f1520da1Jim Grosbach case ARM::VLD1DUPq16wb_fixed: 3747c0fc450f0754508871bc70f21e528bf2f1520da1Jim Grosbach case ARM::VLD1DUPq32wb_fixed: 3748c0fc450f0754508871bc70f21e528bf2f1520da1Jim Grosbach case ARM::VLD1DUPq8wb_register: 3749c0fc450f0754508871bc70f21e528bf2f1520da1Jim Grosbach case ARM::VLD1DUPq16wb_register: 3750c0fc450f0754508871bc70f21e528bf2f1520da1Jim Grosbach case ARM::VLD1DUPq32wb_register: 3751c0fc450f0754508871bc70f21e528bf2f1520da1Jim Grosbach case ARM::VLD2DUPd8: 3752c0fc450f0754508871bc70f21e528bf2f1520da1Jim Grosbach case ARM::VLD2DUPd16: 3753c0fc450f0754508871bc70f21e528bf2f1520da1Jim Grosbach case ARM::VLD2DUPd32: 3754c0fc450f0754508871bc70f21e528bf2f1520da1Jim Grosbach case ARM::VLD2DUPd8wb_fixed: 3755c0fc450f0754508871bc70f21e528bf2f1520da1Jim Grosbach case ARM::VLD2DUPd16wb_fixed: 3756c0fc450f0754508871bc70f21e528bf2f1520da1Jim Grosbach case ARM::VLD2DUPd32wb_fixed: 3757c0fc450f0754508871bc70f21e528bf2f1520da1Jim Grosbach case ARM::VLD2DUPd8wb_register: 3758c0fc450f0754508871bc70f21e528bf2f1520da1Jim Grosbach case ARM::VLD2DUPd16wb_register: 3759c0fc450f0754508871bc70f21e528bf2f1520da1Jim Grosbach case ARM::VLD2DUPd32wb_register: 376075b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4DUPd8Pseudo: 376175b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4DUPd16Pseudo: 376275b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4DUPd32Pseudo: 376375b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4DUPd8Pseudo_UPD: 376475b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4DUPd16Pseudo_UPD: 376575b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4DUPd32Pseudo_UPD: 376675b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1LNq8Pseudo: 376775b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1LNq16Pseudo: 376875b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1LNq32Pseudo: 376975b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1LNq8Pseudo_UPD: 377075b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1LNq16Pseudo_UPD: 377175b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD1LNq32Pseudo_UPD: 377275b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2LNd8Pseudo: 377375b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2LNd16Pseudo: 377475b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2LNd32Pseudo: 377575b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2LNq16Pseudo: 377675b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2LNq32Pseudo: 377775b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2LNd8Pseudo_UPD: 377875b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2LNd16Pseudo_UPD: 377975b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2LNd32Pseudo_UPD: 378075b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2LNq16Pseudo_UPD: 378175b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD2LNq32Pseudo_UPD: 378275b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4LNd8Pseudo: 378375b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4LNd16Pseudo: 378475b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4LNd32Pseudo: 378575b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4LNq16Pseudo: 378675b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4LNq32Pseudo: 378775b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4LNd8Pseudo_UPD: 378875b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4LNd16Pseudo_UPD: 378975b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4LNd32Pseudo_UPD: 379075b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4LNq16Pseudo_UPD: 379175b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng case ARM::VLD4LNq32Pseudo_UPD: 379275b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng // If the address is not 64-bit aligned, the latencies of these 379375b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng // instructions increases by one. 379475b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng ++Latency; 379575b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng break; 379675b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng } 379775b41f1540f35ef0fd5e4a52c1840f1a19debb03Evan Cheng 37987e2fe9150f905167f6685c9730911c2abc08293cEvan Cheng return Latency; 3799a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng} 38002312842de0c641107dd04d7e056d02491cc781caEvan Cheng 3801d42730dc712026cbfb1322a979e0ac72cd31a19eArnold Schwaighoferunsigned ARMBaseInstrInfo::getPredicationCost(const MachineInstr *MI) const { 3802d42730dc712026cbfb1322a979e0ac72cd31a19eArnold Schwaighofer if (MI->isCopyLike() || MI->isInsertSubreg() || 3803d42730dc712026cbfb1322a979e0ac72cd31a19eArnold Schwaighofer MI->isRegSequence() || MI->isImplicitDef()) 3804d42730dc712026cbfb1322a979e0ac72cd31a19eArnold Schwaighofer return 0; 3805d42730dc712026cbfb1322a979e0ac72cd31a19eArnold Schwaighofer 3806d42730dc712026cbfb1322a979e0ac72cd31a19eArnold Schwaighofer if (MI->isBundle()) 3807d42730dc712026cbfb1322a979e0ac72cd31a19eArnold Schwaighofer return 0; 3808d42730dc712026cbfb1322a979e0ac72cd31a19eArnold Schwaighofer 3809d42730dc712026cbfb1322a979e0ac72cd31a19eArnold Schwaighofer const MCInstrDesc &MCID = MI->getDesc(); 3810d42730dc712026cbfb1322a979e0ac72cd31a19eArnold Schwaighofer 3811d42730dc712026cbfb1322a979e0ac72cd31a19eArnold Schwaighofer if (MCID.isCall() || MCID.hasImplicitDefOfPhysReg(ARM::CPSR)) { 3812d42730dc712026cbfb1322a979e0ac72cd31a19eArnold Schwaighofer // When predicated, CPSR is an additional source operand for CPSR updating 3813d42730dc712026cbfb1322a979e0ac72cd31a19eArnold Schwaighofer // instructions, this apparently increases their latencies. 3814d42730dc712026cbfb1322a979e0ac72cd31a19eArnold Schwaighofer return 1; 3815d42730dc712026cbfb1322a979e0ac72cd31a19eArnold Schwaighofer } 3816d42730dc712026cbfb1322a979e0ac72cd31a19eArnold Schwaighofer return 0; 3817d42730dc712026cbfb1322a979e0ac72cd31a19eArnold Schwaighofer} 3818d42730dc712026cbfb1322a979e0ac72cd31a19eArnold Schwaighofer 3819b7e0289fb320c8440ba5eed121a8b932dbd806a2Andrew Trickunsigned ARMBaseInstrInfo::getInstrLatency(const InstrItineraryData *ItinData, 3820b7e0289fb320c8440ba5eed121a8b932dbd806a2Andrew Trick const MachineInstr *MI, 3821b7e0289fb320c8440ba5eed121a8b932dbd806a2Andrew Trick unsigned *PredCost) const { 38228239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng if (MI->isCopyLike() || MI->isInsertSubreg() || 38238239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng MI->isRegSequence() || MI->isImplicitDef()) 38248239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng return 1; 38258239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng 3826ed7a51e69209af87f3749d5f95740f69a1dc7711Andrew Trick // An instruction scheduler typically runs on unbundled instructions, however 3827ed7a51e69209af87f3749d5f95740f69a1dc7711Andrew Trick // other passes may query the latency of a bundled instruction. 3828ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng if (MI->isBundle()) { 3829ed7a51e69209af87f3749d5f95740f69a1dc7711Andrew Trick unsigned Latency = 0; 3830ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng MachineBasicBlock::const_instr_iterator I = MI; 3831ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end(); 3832ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng while (++I != E && I->isInsideBundle()) { 3833ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng if (I->getOpcode() != ARM::t2IT) 3834ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng Latency += getInstrLatency(ItinData, I, PredCost); 3835ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng } 3836ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng return Latency; 3837ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng } 3838ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng 3839e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng const MCInstrDesc &MCID = MI->getDesc(); 3840ed7a51e69209af87f3749d5f95740f69a1dc7711Andrew Trick if (PredCost && (MCID.isCall() || MCID.hasImplicitDefOfPhysReg(ARM::CPSR))) { 38418239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng // When predicated, CPSR is an additional source operand for CPSR updating 38428239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng // instructions, this apparently increases their latencies. 38438239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng *PredCost = 1; 3844ed7a51e69209af87f3749d5f95740f69a1dc7711Andrew Trick } 3845ed7a51e69209af87f3749d5f95740f69a1dc7711Andrew Trick // Be sure to call getStageLatency for an empty itinerary in case it has a 3846ed7a51e69209af87f3749d5f95740f69a1dc7711Andrew Trick // valid MinLatency property. 3847ed7a51e69209af87f3749d5f95740f69a1dc7711Andrew Trick if (!ItinData) 3848ed7a51e69209af87f3749d5f95740f69a1dc7711Andrew Trick return MI->mayLoad() ? 3 : 1; 3849ed7a51e69209af87f3749d5f95740f69a1dc7711Andrew Trick 3850ed7a51e69209af87f3749d5f95740f69a1dc7711Andrew Trick unsigned Class = MCID.getSchedClass(); 3851ed7a51e69209af87f3749d5f95740f69a1dc7711Andrew Trick 3852ed7a51e69209af87f3749d5f95740f69a1dc7711Andrew Trick // For instructions with variable uops, use uops as latency. 385314ccc7b963861a856b593cc4fff62decd8ce248aAndrew Trick if (!ItinData->isEmpty() && ItinData->getNumMicroOps(Class) < 0) 3854ed7a51e69209af87f3749d5f95740f69a1dc7711Andrew Trick return getNumMicroOps(ItinData, MI); 385514ccc7b963861a856b593cc4fff62decd8ce248aAndrew Trick 3856ed7a51e69209af87f3749d5f95740f69a1dc7711Andrew Trick // For the common case, fall back on the itinerary's latency. 385768b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick unsigned Latency = ItinData->getStageLatency(Class); 385868b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick 385968b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick // Adjust for dynamic def-side opcode variants not captured by the itinerary. 386068b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick unsigned DefAlign = MI->hasOneMemOperand() 386168b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick ? (*MI->memoperands_begin())->getAlignment() : 0; 386268b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick int Adj = adjustDefLatency(Subtarget, MI, &MCID, DefAlign); 386368b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick if (Adj >= 0 || (int)Latency > -Adj) { 386468b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick return Latency + Adj; 386568b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick } 386668b16541cc58411c7b0607ca4c0fb497222b668dAndrew Trick return Latency; 38678239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng} 38688239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng 38698239daf7c83a65a189c352cce3191cdc3bbfe151Evan Chengint ARMBaseInstrInfo::getInstrLatency(const InstrItineraryData *ItinData, 38708239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng SDNode *Node) const { 38718239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng if (!Node->isMachineOpcode()) 38728239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng return 1; 38738239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng 38748239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng if (!ItinData || ItinData->isEmpty()) 38758239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng return 1; 38768239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng 38778239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng unsigned Opcode = Node->getMachineOpcode(); 38788239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng switch (Opcode) { 38798239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng default: 38808239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng return ItinData->getStageLatency(get(Opcode).getSchedClass()); 388173fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMQIA: 388273fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMQIA: 38838239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng return 2; 38848b3ca6216d62bf3f729c2e122dcfeb7c4d7500dcEric Christopher } 38858239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng} 38868239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng 38872312842de0c641107dd04d7e056d02491cc781caEvan Chengbool ARMBaseInstrInfo:: 38882312842de0c641107dd04d7e056d02491cc781caEvan ChenghasHighOperandLatency(const InstrItineraryData *ItinData, 38892312842de0c641107dd04d7e056d02491cc781caEvan Cheng const MachineRegisterInfo *MRI, 38902312842de0c641107dd04d7e056d02491cc781caEvan Cheng const MachineInstr *DefMI, unsigned DefIdx, 38912312842de0c641107dd04d7e056d02491cc781caEvan Cheng const MachineInstr *UseMI, unsigned UseIdx) const { 38922312842de0c641107dd04d7e056d02491cc781caEvan Cheng unsigned DDomain = DefMI->getDesc().TSFlags & ARMII::DomainMask; 38932312842de0c641107dd04d7e056d02491cc781caEvan Cheng unsigned UDomain = UseMI->getDesc().TSFlags & ARMII::DomainMask; 38942312842de0c641107dd04d7e056d02491cc781caEvan Cheng if (Subtarget.isCortexA8() && 38952312842de0c641107dd04d7e056d02491cc781caEvan Cheng (DDomain == ARMII::DomainVFP || UDomain == ARMII::DomainVFP)) 38962312842de0c641107dd04d7e056d02491cc781caEvan Cheng // CortexA8 VFP instructions are not pipelined. 38972312842de0c641107dd04d7e056d02491cc781caEvan Cheng return true; 38982312842de0c641107dd04d7e056d02491cc781caEvan Cheng 38992312842de0c641107dd04d7e056d02491cc781caEvan Cheng // Hoist VFP / NEON instructions with 4 or higher latency. 3900b86a0cdb674549d8493043331cecd9cbf53b80daAndrew Trick int Latency = computeOperandLatency(ItinData, DefMI, DefIdx, UseMI, UseIdx); 3901f377071bf8393d35797107c753da3e84aea94ebeAndrew Trick if (Latency < 0) 3902f377071bf8393d35797107c753da3e84aea94ebeAndrew Trick Latency = getInstrLatency(ItinData, DefMI); 39032312842de0c641107dd04d7e056d02491cc781caEvan Cheng if (Latency <= 3) 39042312842de0c641107dd04d7e056d02491cc781caEvan Cheng return false; 39052312842de0c641107dd04d7e056d02491cc781caEvan Cheng return DDomain == ARMII::DomainVFP || DDomain == ARMII::DomainNEON || 39062312842de0c641107dd04d7e056d02491cc781caEvan Cheng UDomain == ARMII::DomainVFP || UDomain == ARMII::DomainNEON; 39072312842de0c641107dd04d7e056d02491cc781caEvan Cheng} 3908c8141dfc7f983cb04e65d8acd6bcbdc8e4b8a0aeEvan Cheng 3909c8141dfc7f983cb04e65d8acd6bcbdc8e4b8a0aeEvan Chengbool ARMBaseInstrInfo:: 3910c8141dfc7f983cb04e65d8acd6bcbdc8e4b8a0aeEvan ChenghasLowDefLatency(const InstrItineraryData *ItinData, 3911c8141dfc7f983cb04e65d8acd6bcbdc8e4b8a0aeEvan Cheng const MachineInstr *DefMI, unsigned DefIdx) const { 3912c8141dfc7f983cb04e65d8acd6bcbdc8e4b8a0aeEvan Cheng if (!ItinData || ItinData->isEmpty()) 3913c8141dfc7f983cb04e65d8acd6bcbdc8e4b8a0aeEvan Cheng return false; 3914c8141dfc7f983cb04e65d8acd6bcbdc8e4b8a0aeEvan Cheng 3915c8141dfc7f983cb04e65d8acd6bcbdc8e4b8a0aeEvan Cheng unsigned DDomain = DefMI->getDesc().TSFlags & ARMII::DomainMask; 3916c8141dfc7f983cb04e65d8acd6bcbdc8e4b8a0aeEvan Cheng if (DDomain == ARMII::DomainGeneral) { 3917c8141dfc7f983cb04e65d8acd6bcbdc8e4b8a0aeEvan Cheng unsigned DefClass = DefMI->getDesc().getSchedClass(); 3918c8141dfc7f983cb04e65d8acd6bcbdc8e4b8a0aeEvan Cheng int DefCycle = ItinData->getOperandCycle(DefClass, DefIdx); 3919c8141dfc7f983cb04e65d8acd6bcbdc8e4b8a0aeEvan Cheng return (DefCycle != -1 && DefCycle <= 2); 3920c8141dfc7f983cb04e65d8acd6bcbdc8e4b8a0aeEvan Cheng } 3921c8141dfc7f983cb04e65d8acd6bcbdc8e4b8a0aeEvan Cheng return false; 3922c8141dfc7f983cb04e65d8acd6bcbdc8e4b8a0aeEvan Cheng} 392348575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng 39243be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trickbool ARMBaseInstrInfo::verifyInstruction(const MachineInstr *MI, 39253be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick StringRef &ErrInfo) const { 39263be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick if (convertAddSubFlagsOpcode(MI->getOpcode())) { 39273be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick ErrInfo = "Pseudo flag setting opcodes only exist in Selection DAG"; 39283be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick return false; 39293be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick } 39303be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick return true; 39313be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick} 39323be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick 393348575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Chengbool 393448575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan ChengARMBaseInstrInfo::isFpMLxInstruction(unsigned Opcode, unsigned &MulOpc, 393548575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng unsigned &AddSubOpc, 393648575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng bool &NegAcc, bool &HasLane) const { 393748575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng DenseMap<unsigned, unsigned>::const_iterator I = MLxEntryMap.find(Opcode); 393848575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng if (I == MLxEntryMap.end()) 393948575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng return false; 394048575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng 394148575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng const ARM_MLxEntry &Entry = ARM_MLxTable[I->second]; 394248575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng MulOpc = Entry.MulOpc; 394348575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng AddSubOpc = Entry.AddSubOpc; 394448575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng NegAcc = Entry.NegAcc; 394548575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng HasLane = Entry.HasLane; 394648575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng return true; 394748575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng} 394813fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen 394913fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen//===----------------------------------------------------------------------===// 395013fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen// Execution domains. 395113fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen//===----------------------------------------------------------------------===// 395213fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen// 395313fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen// Some instructions go down the NEON pipeline, some go down the VFP pipeline, 395413fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen// and some can go down both. The vmov instructions go down the VFP pipeline, 395513fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen// but they can be changed to vorr equivalents that are executed by the NEON 395613fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen// pipeline. 395713fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen// 395813fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen// We use the following execution domain numbering: 395913fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen// 39608bb3d3cb30df06bdcb3ef5a208e3e59f4eeb4868Jakob Stoklund Olesenenum ARMExeDomain { 39618bb3d3cb30df06bdcb3ef5a208e3e59f4eeb4868Jakob Stoklund Olesen ExeGeneric = 0, 39628bb3d3cb30df06bdcb3ef5a208e3e59f4eeb4868Jakob Stoklund Olesen ExeVFP = 1, 39638bb3d3cb30df06bdcb3ef5a208e3e59f4eeb4868Jakob Stoklund Olesen ExeNEON = 2 39648bb3d3cb30df06bdcb3ef5a208e3e59f4eeb4868Jakob Stoklund Olesen}; 396513fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen// 396613fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen// Also see ARMInstrFormats.td and Domain* enums in ARMBaseInfo.h 396713fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen// 396813fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesenstd::pair<uint16_t, uint16_t> 396913fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund OlesenARMBaseInstrInfo::getExecutionDomain(const MachineInstr *MI) const { 39703c8ad92455ff06c8e69085702ef1f13944eab4ddTim Northover // VMOVD, VMOVRS and VMOVSR are VFP instructions, but can be changed to NEON 39713c8ad92455ff06c8e69085702ef1f13944eab4ddTim Northover // if they are not predicated. 397213fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen if (MI->getOpcode() == ARM::VMOVD && !isPredicated(MI)) 39738bb3d3cb30df06bdcb3ef5a208e3e59f4eeb4868Jakob Stoklund Olesen return std::make_pair(ExeVFP, (1<<ExeVFP) | (1<<ExeNEON)); 397413fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen 3975a210db781f17b5ab8e2b71d53276153a9d15eeadSilviu Baranga // CortexA9 is particularly picky about mixing the two and wants these 39763c8ad92455ff06c8e69085702ef1f13944eab4ddTim Northover // converted. 3977a210db781f17b5ab8e2b71d53276153a9d15eeadSilviu Baranga if (Subtarget.isCortexA9() && !isPredicated(MI) && 39783c8ad92455ff06c8e69085702ef1f13944eab4ddTim Northover (MI->getOpcode() == ARM::VMOVRS || 3979c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover MI->getOpcode() == ARM::VMOVSR || 3980c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover MI->getOpcode() == ARM::VMOVS)) 39813c8ad92455ff06c8e69085702ef1f13944eab4ddTim Northover return std::make_pair(ExeVFP, (1<<ExeVFP) | (1<<ExeNEON)); 39823c8ad92455ff06c8e69085702ef1f13944eab4ddTim Northover 398313fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen // No other instructions can be swizzled, so just determine their domain. 398413fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen unsigned Domain = MI->getDesc().TSFlags & ARMII::DomainMask; 398513fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen 398613fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen if (Domain & ARMII::DomainNEON) 39878bb3d3cb30df06bdcb3ef5a208e3e59f4eeb4868Jakob Stoklund Olesen return std::make_pair(ExeNEON, 0); 398813fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen 398913fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen // Certain instructions can go either way on Cortex-A8. 399013fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen // Treat them as NEON instructions. 399113fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen if ((Domain & ARMII::DomainNEONA8) && Subtarget.isCortexA8()) 39928bb3d3cb30df06bdcb3ef5a208e3e59f4eeb4868Jakob Stoklund Olesen return std::make_pair(ExeNEON, 0); 399313fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen 399413fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen if (Domain & ARMII::DomainVFP) 39958bb3d3cb30df06bdcb3ef5a208e3e59f4eeb4868Jakob Stoklund Olesen return std::make_pair(ExeVFP, 0); 399613fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen 39978bb3d3cb30df06bdcb3ef5a208e3e59f4eeb4868Jakob Stoklund Olesen return std::make_pair(ExeGeneric, 0); 399813fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen} 399913fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen 400020599ea4bced03634a54b52e98d261018366f279Tim Northoverstatic unsigned getCorrespondingDRegAndLane(const TargetRegisterInfo *TRI, 400120599ea4bced03634a54b52e98d261018366f279Tim Northover unsigned SReg, unsigned &Lane) { 400220599ea4bced03634a54b52e98d261018366f279Tim Northover unsigned DReg = TRI->getMatchingSuperReg(SReg, ARM::ssub_0, &ARM::DPRRegClass); 400320599ea4bced03634a54b52e98d261018366f279Tim Northover Lane = 0; 400420599ea4bced03634a54b52e98d261018366f279Tim Northover 400520599ea4bced03634a54b52e98d261018366f279Tim Northover if (DReg != ARM::NoRegister) 400620599ea4bced03634a54b52e98d261018366f279Tim Northover return DReg; 400720599ea4bced03634a54b52e98d261018366f279Tim Northover 400820599ea4bced03634a54b52e98d261018366f279Tim Northover Lane = 1; 400920599ea4bced03634a54b52e98d261018366f279Tim Northover DReg = TRI->getMatchingSuperReg(SReg, ARM::ssub_1, &ARM::DPRRegClass); 401020599ea4bced03634a54b52e98d261018366f279Tim Northover 401120599ea4bced03634a54b52e98d261018366f279Tim Northover assert(DReg && "S-register with no D super-register?"); 401220599ea4bced03634a54b52e98d261018366f279Tim Northover return DReg; 401320599ea4bced03634a54b52e98d261018366f279Tim Northover} 401420599ea4bced03634a54b52e98d261018366f279Tim Northover 40152d15d641aa8aa9e48c268170f1a9825bb9926fc7Andrew Trick/// getImplicitSPRUseForDPRUse - Given a use of a DPR register and lane, 401697ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy/// set ImplicitSReg to a register number that must be marked as implicit-use or 401797ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy/// zero if no register needs to be defined as implicit-use. 401897ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy/// 401997ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy/// If the function cannot determine if an SPR should be marked implicit use or 402097ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy/// not, it returns false. 402197ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy/// 402297ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy/// This function handles cases where an instruction is being modified from taking 40232d15d641aa8aa9e48c268170f1a9825bb9926fc7Andrew Trick/// an SPR to a DPR[Lane]. A use of the DPR is being added, which may conflict 402497ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy/// with an earlier def of an SPR corresponding to DPR[Lane^1] (i.e. the other 402597ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy/// lane of the DPR). 402697ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy/// 402797ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy/// If the other SPR is defined, an implicit-use of it should be added. Else, 402897ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy/// (including the case where the DPR itself is defined), it should not. 40292d15d641aa8aa9e48c268170f1a9825bb9926fc7Andrew Trick/// 403097ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloystatic bool getImplicitSPRUseForDPRUse(const TargetRegisterInfo *TRI, 403197ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy MachineInstr *MI, 403297ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy unsigned DReg, unsigned Lane, 403397ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy unsigned &ImplicitSReg) { 403497ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy // If the DPR is defined or used already, the other SPR lane will be chained 403597ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy // correctly, so there is nothing to be done. 403697ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy if (MI->definesRegister(DReg, TRI) || MI->readsRegister(DReg, TRI)) { 403797ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy ImplicitSReg = 0; 403897ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy return true; 403997ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy } 404097ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy 404197ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy // Otherwise we need to go searching to see if the SPR is set explicitly. 404297ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy ImplicitSReg = TRI->getSubReg(DReg, 404397ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy (Lane & 1) ? ARM::ssub_0 : ARM::ssub_1); 404497ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy MachineBasicBlock::LivenessQueryResult LQR = 404597ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy MI->getParent()->computeRegisterLiveness(TRI, ImplicitSReg, MI); 404697ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy 404797ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy if (LQR == MachineBasicBlock::LQR_Live) 404897ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy return true; 404997ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy else if (LQR == MachineBasicBlock::LQR_Unknown) 405097ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy return false; 405197ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy 405297ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy // If the register is known not to be live, there is no need to add an 405397ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy // implicit-use. 405497ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy ImplicitSReg = 0; 405597ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy return true; 405697ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy} 405720599ea4bced03634a54b52e98d261018366f279Tim Northover 405813fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesenvoid 405913fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund OlesenARMBaseInstrInfo::setExecutionDomain(MachineInstr *MI, unsigned Domain) const { 40603c8ad92455ff06c8e69085702ef1f13944eab4ddTim Northover unsigned DstReg, SrcReg, DReg; 40613c8ad92455ff06c8e69085702ef1f13944eab4ddTim Northover unsigned Lane; 406237a942cd52725b1d390989a8267a764b42fcb5d3Jakob Stoklund Olesen MachineInstrBuilder MIB(*MI->getParent()->getParent(), MI); 40633c8ad92455ff06c8e69085702ef1f13944eab4ddTim Northover const TargetRegisterInfo *TRI = &getRegisterInfo(); 40643c8ad92455ff06c8e69085702ef1f13944eab4ddTim Northover switch (MI->getOpcode()) { 40653c8ad92455ff06c8e69085702ef1f13944eab4ddTim Northover default: 40663c8ad92455ff06c8e69085702ef1f13944eab4ddTim Northover llvm_unreachable("cannot handle opcode!"); 40673c8ad92455ff06c8e69085702ef1f13944eab4ddTim Northover break; 40683c8ad92455ff06c8e69085702ef1f13944eab4ddTim Northover case ARM::VMOVD: 40693c8ad92455ff06c8e69085702ef1f13944eab4ddTim Northover if (Domain != ExeNEON) 40703c8ad92455ff06c8e69085702ef1f13944eab4ddTim Northover break; 40713c8ad92455ff06c8e69085702ef1f13944eab4ddTim Northover 40723c8ad92455ff06c8e69085702ef1f13944eab4ddTim Northover // Zap the predicate operands. 40733c8ad92455ff06c8e69085702ef1f13944eab4ddTim Northover assert(!isPredicated(MI) && "Cannot predicate a VORRd"); 40743c8ad92455ff06c8e69085702ef1f13944eab4ddTim Northover 407520599ea4bced03634a54b52e98d261018366f279Tim Northover // Source instruction is %DDst = VMOVD %DSrc, 14, %noreg (; implicits) 407620599ea4bced03634a54b52e98d261018366f279Tim Northover DstReg = MI->getOperand(0).getReg(); 407720599ea4bced03634a54b52e98d261018366f279Tim Northover SrcReg = MI->getOperand(1).getReg(); 40783c8ad92455ff06c8e69085702ef1f13944eab4ddTim Northover 407920599ea4bced03634a54b52e98d261018366f279Tim Northover for (unsigned i = MI->getDesc().getNumOperands(); i; --i) 408020599ea4bced03634a54b52e98d261018366f279Tim Northover MI->RemoveOperand(i-1); 408120599ea4bced03634a54b52e98d261018366f279Tim Northover 408220599ea4bced03634a54b52e98d261018366f279Tim Northover // Change to a %DDst = VORRd %DSrc, %DSrc, 14, %noreg (; implicits) 408320599ea4bced03634a54b52e98d261018366f279Tim Northover MI->setDesc(get(ARM::VORRd)); 408420599ea4bced03634a54b52e98d261018366f279Tim Northover AddDefaultPred(MIB.addReg(DstReg, RegState::Define) 408520599ea4bced03634a54b52e98d261018366f279Tim Northover .addReg(SrcReg) 408620599ea4bced03634a54b52e98d261018366f279Tim Northover .addReg(SrcReg)); 40873c8ad92455ff06c8e69085702ef1f13944eab4ddTim Northover break; 40883c8ad92455ff06c8e69085702ef1f13944eab4ddTim Northover case ARM::VMOVRS: 40893c8ad92455ff06c8e69085702ef1f13944eab4ddTim Northover if (Domain != ExeNEON) 40903c8ad92455ff06c8e69085702ef1f13944eab4ddTim Northover break; 40913c8ad92455ff06c8e69085702ef1f13944eab4ddTim Northover assert(!isPredicated(MI) && "Cannot predicate a VGETLN"); 40923c8ad92455ff06c8e69085702ef1f13944eab4ddTim Northover 409320599ea4bced03634a54b52e98d261018366f279Tim Northover // Source instruction is %RDst = VMOVRS %SSrc, 14, %noreg (; implicits) 40943c8ad92455ff06c8e69085702ef1f13944eab4ddTim Northover DstReg = MI->getOperand(0).getReg(); 40953c8ad92455ff06c8e69085702ef1f13944eab4ddTim Northover SrcReg = MI->getOperand(1).getReg(); 409613fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen 409720599ea4bced03634a54b52e98d261018366f279Tim Northover for (unsigned i = MI->getDesc().getNumOperands(); i; --i) 409820599ea4bced03634a54b52e98d261018366f279Tim Northover MI->RemoveOperand(i-1); 40993c8ad92455ff06c8e69085702ef1f13944eab4ddTim Northover 410020599ea4bced03634a54b52e98d261018366f279Tim Northover DReg = getCorrespondingDRegAndLane(TRI, SrcReg, Lane); 41013c8ad92455ff06c8e69085702ef1f13944eab4ddTim Northover 410220599ea4bced03634a54b52e98d261018366f279Tim Northover // Convert to %RDst = VGETLNi32 %DSrc, Lane, 14, %noreg (; imps) 410320599ea4bced03634a54b52e98d261018366f279Tim Northover // Note that DSrc has been widened and the other lane may be undef, which 410420599ea4bced03634a54b52e98d261018366f279Tim Northover // contaminates the entire register. 41053c8ad92455ff06c8e69085702ef1f13944eab4ddTim Northover MI->setDesc(get(ARM::VGETLNi32)); 410620599ea4bced03634a54b52e98d261018366f279Tim Northover AddDefaultPred(MIB.addReg(DstReg, RegState::Define) 410720599ea4bced03634a54b52e98d261018366f279Tim Northover .addReg(DReg, RegState::Undef) 410820599ea4bced03634a54b52e98d261018366f279Tim Northover .addImm(Lane)); 41093c8ad92455ff06c8e69085702ef1f13944eab4ddTim Northover 411020599ea4bced03634a54b52e98d261018366f279Tim Northover // The old source should be an implicit use, otherwise we might think it 411120599ea4bced03634a54b52e98d261018366f279Tim Northover // was dead before here. 41123c8ad92455ff06c8e69085702ef1f13944eab4ddTim Northover MIB.addReg(SrcReg, RegState::Implicit); 41133c8ad92455ff06c8e69085702ef1f13944eab4ddTim Northover break; 411497ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy case ARM::VMOVSR: { 41153c8ad92455ff06c8e69085702ef1f13944eab4ddTim Northover if (Domain != ExeNEON) 41163c8ad92455ff06c8e69085702ef1f13944eab4ddTim Northover break; 41173c8ad92455ff06c8e69085702ef1f13944eab4ddTim Northover assert(!isPredicated(MI) && "Cannot predicate a VSETLN"); 41183c8ad92455ff06c8e69085702ef1f13944eab4ddTim Northover 411920599ea4bced03634a54b52e98d261018366f279Tim Northover // Source instruction is %SDst = VMOVSR %RSrc, 14, %noreg (; implicits) 41203c8ad92455ff06c8e69085702ef1f13944eab4ddTim Northover DstReg = MI->getOperand(0).getReg(); 41213c8ad92455ff06c8e69085702ef1f13944eab4ddTim Northover SrcReg = MI->getOperand(1).getReg(); 41223c8ad92455ff06c8e69085702ef1f13944eab4ddTim Northover 412320599ea4bced03634a54b52e98d261018366f279Tim Northover DReg = getCorrespondingDRegAndLane(TRI, DstReg, Lane); 41243c8ad92455ff06c8e69085702ef1f13944eab4ddTim Northover 412597ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy unsigned ImplicitSReg; 412697ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy if (!getImplicitSPRUseForDPRUse(TRI, MI, DReg, Lane, ImplicitSReg)) 412797ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy break; 412889f49808ee79eebbc3267b6c595514d4ca1f3247Tim Northover 41297bebddf55ece46995f310d79195afb4e5b239886Tim Northover for (unsigned i = MI->getDesc().getNumOperands(); i; --i) 41307bebddf55ece46995f310d79195afb4e5b239886Tim Northover MI->RemoveOperand(i-1); 41317bebddf55ece46995f310d79195afb4e5b239886Tim Northover 413220599ea4bced03634a54b52e98d261018366f279Tim Northover // Convert to %DDst = VSETLNi32 %DDst, %RSrc, Lane, 14, %noreg (; imps) 413320599ea4bced03634a54b52e98d261018366f279Tim Northover // Again DDst may be undefined at the beginning of this instruction. 413420599ea4bced03634a54b52e98d261018366f279Tim Northover MI->setDesc(get(ARM::VSETLNi32)); 413589f49808ee79eebbc3267b6c595514d4ca1f3247Tim Northover MIB.addReg(DReg, RegState::Define) 413689f49808ee79eebbc3267b6c595514d4ca1f3247Tim Northover .addReg(DReg, getUndefRegState(!MI->readsRegister(DReg, TRI))) 413789f49808ee79eebbc3267b6c595514d4ca1f3247Tim Northover .addReg(SrcReg) 413889f49808ee79eebbc3267b6c595514d4ca1f3247Tim Northover .addImm(Lane); 413989f49808ee79eebbc3267b6c595514d4ca1f3247Tim Northover AddDefaultPred(MIB); 4140c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover 414189f49808ee79eebbc3267b6c595514d4ca1f3247Tim Northover // The narrower destination must be marked as set to keep previous chains 414289f49808ee79eebbc3267b6c595514d4ca1f3247Tim Northover // in place. 414320599ea4bced03634a54b52e98d261018366f279Tim Northover MIB.addReg(DstReg, RegState::Define | RegState::Implicit); 414497ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy if (ImplicitSReg != 0) 414597ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy MIB.addReg(ImplicitSReg, RegState::Implicit); 41463c8ad92455ff06c8e69085702ef1f13944eab4ddTim Northover break; 414797ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy } 4148c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover case ARM::VMOVS: { 4149c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover if (Domain != ExeNEON) 4150c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover break; 4151c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover 4152c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover // Source instruction is %SDst = VMOVS %SSrc, 14, %noreg (; implicits) 4153c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover DstReg = MI->getOperand(0).getReg(); 4154c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover SrcReg = MI->getOperand(1).getReg(); 4155c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover 4156c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover unsigned DstLane = 0, SrcLane = 0, DDst, DSrc; 4157c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover DDst = getCorrespondingDRegAndLane(TRI, DstReg, DstLane); 4158c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover DSrc = getCorrespondingDRegAndLane(TRI, SrcReg, SrcLane); 4159c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover 416097ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy unsigned ImplicitSReg; 416197ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy if (!getImplicitSPRUseForDPRUse(TRI, MI, DSrc, SrcLane, ImplicitSReg)) 416297ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy break; 416389f49808ee79eebbc3267b6c595514d4ca1f3247Tim Northover 41647bebddf55ece46995f310d79195afb4e5b239886Tim Northover for (unsigned i = MI->getDesc().getNumOperands(); i; --i) 41657bebddf55ece46995f310d79195afb4e5b239886Tim Northover MI->RemoveOperand(i-1); 41667bebddf55ece46995f310d79195afb4e5b239886Tim Northover 4167c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover if (DSrc == DDst) { 4168c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover // Destination can be: 4169c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover // %DDst = VDUPLN32d %DDst, Lane, 14, %noreg (; implicits) 4170c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover MI->setDesc(get(ARM::VDUPLN32d)); 417189f49808ee79eebbc3267b6c595514d4ca1f3247Tim Northover MIB.addReg(DDst, RegState::Define) 417289f49808ee79eebbc3267b6c595514d4ca1f3247Tim Northover .addReg(DDst, getUndefRegState(!MI->readsRegister(DDst, TRI))) 417389f49808ee79eebbc3267b6c595514d4ca1f3247Tim Northover .addImm(SrcLane); 417489f49808ee79eebbc3267b6c595514d4ca1f3247Tim Northover AddDefaultPred(MIB); 4175c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover 4176c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover // Neither the source or the destination are naturally represented any 4177c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover // more, so add them in manually. 4178c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover MIB.addReg(DstReg, RegState::Implicit | RegState::Define); 4179c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover MIB.addReg(SrcReg, RegState::Implicit); 418097ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy if (ImplicitSReg != 0) 418197ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy MIB.addReg(ImplicitSReg, RegState::Implicit); 4182c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover break; 4183c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover } 4184c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover 4185c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover // In general there's no single instruction that can perform an S <-> S 4186c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover // move in NEON space, but a pair of VEXT instructions *can* do the 4187c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover // job. It turns out that the VEXTs needed will only use DSrc once, with 4188c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover // the position based purely on the combination of lane-0 and lane-1 4189c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover // involved. For example 4190c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover // vmov s0, s2 -> vext.32 d0, d0, d1, #1 vext.32 d0, d0, d0, #1 4191c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover // vmov s1, s3 -> vext.32 d0, d1, d0, #1 vext.32 d0, d0, d0, #1 4192c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover // vmov s0, s3 -> vext.32 d0, d0, d0, #1 vext.32 d0, d1, d0, #1 4193c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover // vmov s1, s2 -> vext.32 d0, d0, d0, #1 vext.32 d0, d0, d1, #1 4194c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover // 4195c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover // Pattern of the MachineInstrs is: 4196c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover // %DDst = VEXTd32 %DSrc1, %DSrc2, Lane, 14, %noreg (;implicits) 4197c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover MachineInstrBuilder NewMIB; 4198c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover NewMIB = BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), 4199c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover get(ARM::VEXTd32), DDst); 420089f49808ee79eebbc3267b6c595514d4ca1f3247Tim Northover 420189f49808ee79eebbc3267b6c595514d4ca1f3247Tim Northover // On the first instruction, both DSrc and DDst may be <undef> if present. 420289f49808ee79eebbc3267b6c595514d4ca1f3247Tim Northover // Specifically when the original instruction didn't have them as an 420389f49808ee79eebbc3267b6c595514d4ca1f3247Tim Northover // <imp-use>. 420489f49808ee79eebbc3267b6c595514d4ca1f3247Tim Northover unsigned CurReg = SrcLane == 1 && DstLane == 1 ? DSrc : DDst; 420589f49808ee79eebbc3267b6c595514d4ca1f3247Tim Northover bool CurUndef = !MI->readsRegister(CurReg, TRI); 420689f49808ee79eebbc3267b6c595514d4ca1f3247Tim Northover NewMIB.addReg(CurReg, getUndefRegState(CurUndef)); 420789f49808ee79eebbc3267b6c595514d4ca1f3247Tim Northover 420889f49808ee79eebbc3267b6c595514d4ca1f3247Tim Northover CurReg = SrcLane == 0 && DstLane == 0 ? DSrc : DDst; 420989f49808ee79eebbc3267b6c595514d4ca1f3247Tim Northover CurUndef = !MI->readsRegister(CurReg, TRI); 421089f49808ee79eebbc3267b6c595514d4ca1f3247Tim Northover NewMIB.addReg(CurReg, getUndefRegState(CurUndef)); 421189f49808ee79eebbc3267b6c595514d4ca1f3247Tim Northover 4212c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover NewMIB.addImm(1); 4213c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover AddDefaultPred(NewMIB); 4214c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover 4215c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover if (SrcLane == DstLane) 4216c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover NewMIB.addReg(SrcReg, RegState::Implicit); 4217c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover 4218c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover MI->setDesc(get(ARM::VEXTd32)); 4219c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover MIB.addReg(DDst, RegState::Define); 422089f49808ee79eebbc3267b6c595514d4ca1f3247Tim Northover 422189f49808ee79eebbc3267b6c595514d4ca1f3247Tim Northover // On the second instruction, DDst has definitely been defined above, so 422289f49808ee79eebbc3267b6c595514d4ca1f3247Tim Northover // it is not <undef>. DSrc, if present, can be <undef> as above. 422389f49808ee79eebbc3267b6c595514d4ca1f3247Tim Northover CurReg = SrcLane == 1 && DstLane == 0 ? DSrc : DDst; 422489f49808ee79eebbc3267b6c595514d4ca1f3247Tim Northover CurUndef = CurReg == DSrc && !MI->readsRegister(CurReg, TRI); 422589f49808ee79eebbc3267b6c595514d4ca1f3247Tim Northover MIB.addReg(CurReg, getUndefRegState(CurUndef)); 422689f49808ee79eebbc3267b6c595514d4ca1f3247Tim Northover 422789f49808ee79eebbc3267b6c595514d4ca1f3247Tim Northover CurReg = SrcLane == 0 && DstLane == 1 ? DSrc : DDst; 422889f49808ee79eebbc3267b6c595514d4ca1f3247Tim Northover CurUndef = CurReg == DSrc && !MI->readsRegister(CurReg, TRI); 422989f49808ee79eebbc3267b6c595514d4ca1f3247Tim Northover MIB.addReg(CurReg, getUndefRegState(CurUndef)); 423089f49808ee79eebbc3267b6c595514d4ca1f3247Tim Northover 4231c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover MIB.addImm(1); 4232c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover AddDefaultPred(MIB); 4233c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover 4234c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover if (SrcLane != DstLane) 4235c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover MIB.addReg(SrcReg, RegState::Implicit); 4236c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover 4237c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover // As before, the original destination is no longer represented, add it 4238c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover // implicitly. 4239c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover MIB.addReg(DstReg, RegState::Define | RegState::Implicit); 424097ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy if (ImplicitSReg != 0) 424197ecb83dffb5ff78ff84e9da21189268f52c63b2James Molloy MIB.addReg(ImplicitSReg, RegState::Implicit); 4242c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover break; 4243c4a32e6596f3974a6c00322db1f5f31ea448bd58Tim Northover } 42443c8ad92455ff06c8e69085702ef1f13944eab4ddTim Northover } 42458bb3d3cb30df06bdcb3ef5a208e3e59f4eeb4868Jakob Stoklund Olesen 424613fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen} 4247c01810eeb7227010f73cb39e3c4fa0197a3c4ef0Jim Grosbach 4248eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson//===----------------------------------------------------------------------===// 4249eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson// Partial register updates 4250eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson//===----------------------------------------------------------------------===// 4251eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson// 4252eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson// Swift renames NEON registers with 64-bit granularity. That means any 4253eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson// instruction writing an S-reg implicitly reads the containing D-reg. The 4254eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson// problem is mostly avoided by translating f32 operations to v2f32 operations 4255eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson// on D-registers, but f32 loads are still a problem. 4256eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson// 4257eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson// These instructions can load an f32 into a NEON register: 4258eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson// 4259eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson// VLDRS - Only writes S, partial D update. 4260eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson// VLD1LNd32 - Writes all D-regs, explicit partial D update, 2 uops. 4261eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson// VLD1DUPd32 - Writes all D-regs, no partial reg update, 2 uops. 4262eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson// 4263eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson// FCONSTD can be used as a dependency-breaking instruction. 4264eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilsonunsigned ARMBaseInstrInfo:: 4265eb1641d54a7eda7717304bc4d55d059208d8ebedBob WilsongetPartialRegUpdateClearance(const MachineInstr *MI, 4266eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson unsigned OpNum, 4267eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson const TargetRegisterInfo *TRI) const { 4268a210db781f17b5ab8e2b71d53276153a9d15eeadSilviu Baranga if (!SwiftPartialUpdateClearance || 4269a210db781f17b5ab8e2b71d53276153a9d15eeadSilviu Baranga !(Subtarget.isSwift() || Subtarget.isCortexA15())) 4270eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson return 0; 4271eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson 4272eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson assert(TRI && "Need TRI instance"); 4273eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson 4274eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson const MachineOperand &MO = MI->getOperand(OpNum); 4275eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson if (MO.readsReg()) 4276eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson return 0; 4277eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson unsigned Reg = MO.getReg(); 4278eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson int UseOp = -1; 4279eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson 4280eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson switch(MI->getOpcode()) { 4281eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson // Normal instructions writing only an S-register. 4282eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::VLDRS: 4283eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::FCONSTS: 4284eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::VMOVSR: 4285eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::VMOVv8i8: 4286eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::VMOVv4i16: 4287eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::VMOVv2i32: 4288eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::VMOVv2f32: 4289eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::VMOVv1i64: 4290eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson UseOp = MI->findRegisterUseOperandIdx(Reg, false, TRI); 4291eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson break; 4292eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson 4293eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson // Explicitly reads the dependency. 4294eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson case ARM::VLD1LNd32: 4295a210db781f17b5ab8e2b71d53276153a9d15eeadSilviu Baranga UseOp = 3; 4296eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson break; 4297eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson default: 4298eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson return 0; 4299eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson } 4300eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson 4301eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson // If this instruction actually reads a value from Reg, there is no unwanted 4302eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson // dependency. 4303eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson if (UseOp != -1 && MI->getOperand(UseOp).readsReg()) 4304eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson return 0; 4305eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson 4306eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson // We must be able to clobber the whole D-reg. 4307eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson if (TargetRegisterInfo::isVirtualRegister(Reg)) { 4308eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson // Virtual register must be a foo:ssub_0<def,undef> operand. 4309eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson if (!MO.getSubReg() || MI->readsVirtualRegister(Reg)) 4310eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson return 0; 4311eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson } else if (ARM::SPRRegClass.contains(Reg)) { 4312eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson // Physical register: MI must define the full D-reg. 4313eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson unsigned DReg = TRI->getMatchingSuperReg(Reg, ARM::ssub_0, 4314eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson &ARM::DPRRegClass); 4315eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson if (!DReg || !MI->definesRegister(DReg, TRI)) 4316eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson return 0; 4317eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson } 4318eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson 4319eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson // MI has an unwanted D-register dependency. 4320eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson // Avoid defs in the previous N instructrions. 4321eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson return SwiftPartialUpdateClearance; 4322eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson} 4323eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson 4324eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson// Break a partial register dependency after getPartialRegUpdateClearance 4325eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson// returned non-zero. 4326eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilsonvoid ARMBaseInstrInfo:: 4327eb1641d54a7eda7717304bc4d55d059208d8ebedBob WilsonbreakPartialRegDependency(MachineBasicBlock::iterator MI, 4328eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson unsigned OpNum, 4329eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson const TargetRegisterInfo *TRI) const { 4330eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson assert(MI && OpNum < MI->getDesc().getNumDefs() && "OpNum is not a def"); 4331eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson assert(TRI && "Need TRI instance"); 4332eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson 4333eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson const MachineOperand &MO = MI->getOperand(OpNum); 4334eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson unsigned Reg = MO.getReg(); 4335eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson assert(TargetRegisterInfo::isPhysicalRegister(Reg) && 4336eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson "Can't break virtual register dependencies."); 4337eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson unsigned DReg = Reg; 4338eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson 4339eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson // If MI defines an S-reg, find the corresponding D super-register. 4340eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson if (ARM::SPRRegClass.contains(Reg)) { 4341eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson DReg = ARM::D0 + (Reg - ARM::S0) / 2; 4342eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson assert(TRI->isSuperRegister(Reg, DReg) && "Register enums broken"); 4343eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson } 4344eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson 4345eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson assert(ARM::DPRRegClass.contains(DReg) && "Can only break D-reg deps"); 4346eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson assert(MI->definesRegister(DReg, TRI) && "MI doesn't clobber full D-reg"); 4347eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson 4348eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson // FIXME: In some cases, VLDRS can be changed to a VLD1DUPd32 which defines 4349eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson // the full D-register by loading the same value to both lanes. The 4350eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson // instruction is micro-coded with 2 uops, so don't do this until we can 4351d9d6e6d59159160299a51fe5010a940db27ae89bRobert Wilhelm // properly schedule micro-coded instructions. The dispatcher stalls cause 4352eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson // too big regressions. 4353eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson 4354eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson // Insert the dependency-breaking FCONSTD before MI. 4355eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson // 96 is the encoding of 0.5, but the actual value doesn't matter here. 4356eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson AddDefaultPred(BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), 4357eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson get(ARM::FCONSTD), DReg).addImm(96)); 4358eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson MI->addRegisterKilled(DReg, TRI, true); 4359eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson} 4360eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson 4361c01810eeb7227010f73cb39e3c4fa0197a3c4ef0Jim Grosbachbool ARMBaseInstrInfo::hasNOP() const { 4362c01810eeb7227010f73cb39e3c4fa0197a3c4ef0Jim Grosbach return (Subtarget.getFeatureBits() & ARM::HasV6T2Ops) != 0; 4363c01810eeb7227010f73cb39e3c4fa0197a3c4ef0Jim Grosbach} 436408da4865576056f997a9c8013240d716018f7edfArnold Schwaighofer 436508da4865576056f997a9c8013240d716018f7edfArnold Schwaighoferbool ARMBaseInstrInfo::isSwiftFastImmShift(const MachineInstr *MI) const { 4366d87bd5627e5b78cb556d6c7b5aa76ae3d55d8acfArnold Schwaighofer if (MI->getNumOperands() < 4) 4367d87bd5627e5b78cb556d6c7b5aa76ae3d55d8acfArnold Schwaighofer return true; 436808da4865576056f997a9c8013240d716018f7edfArnold Schwaighofer unsigned ShOpVal = MI->getOperand(3).getImm(); 436908da4865576056f997a9c8013240d716018f7edfArnold Schwaighofer unsigned ShImm = ARM_AM::getSORegOffset(ShOpVal); 437008da4865576056f997a9c8013240d716018f7edfArnold Schwaighofer // Swift supports faster shifts for: lsl 2, lsl 1, and lsr 1. 437108da4865576056f997a9c8013240d716018f7edfArnold Schwaighofer if ((ShImm == 1 && ARM_AM::getSORegShOp(ShOpVal) == ARM_AM::lsr) || 437208da4865576056f997a9c8013240d716018f7edfArnold Schwaighofer ((ShImm == 1 || ShImm == 2) && 437308da4865576056f997a9c8013240d716018f7edfArnold Schwaighofer ARM_AM::getSORegShOp(ShOpVal) == ARM_AM::lsl)) 437408da4865576056f997a9c8013240d716018f7edfArnold Schwaighofer return true; 437508da4865576056f997a9c8013240d716018f7edfArnold Schwaighofer 437608da4865576056f997a9c8013240d716018f7edfArnold Schwaighofer return false; 437708da4865576056f997a9c8013240d716018f7edfArnold Schwaighofer} 4378