ARMBaseInstrInfo.cpp revision f95215f551949d5e5adfbf4753aa833b9009b77a
1334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin//===- ARMBaseInstrInfo.cpp - ARM Instruction Information -----------*- C++ -*-===// 2334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// 3334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// The LLVM Compiler Infrastructure 4334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// 5334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// This file is distributed under the University of Illinois Open Source 6334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// License. See LICENSE.TXT for details. 7334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// 8334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin//===----------------------------------------------------------------------===// 9334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// 10334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// This file contains the Base ARM implementation of the TargetInstrInfo class. 11334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// 12334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin//===----------------------------------------------------------------------===// 13334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 14334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "ARMBaseInstrInfo.h" 15334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "ARM.h" 16334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "ARMAddressingModes.h" 17334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "ARMGenInstrInfo.inc" 18334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "ARMMachineFunctionInfo.h" 19f95215f551949d5e5adfbf4753aa833b9009b77aAnton Korobeynikov#include "ARMRegisterInfo.h" 20334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "llvm/ADT/STLExtras.h" 21334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "llvm/CodeGen/LiveVariables.h" 22334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "llvm/CodeGen/MachineFrameInfo.h" 23334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "llvm/CodeGen/MachineInstrBuilder.h" 24334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "llvm/CodeGen/MachineJumpTableInfo.h" 25249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov#include "llvm/CodeGen/MachineMemOperand.h" 26f95215f551949d5e5adfbf4753aa833b9009b77aAnton Korobeynikov#include "llvm/CodeGen/MachineRegisterInfo.h" 27249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov#include "llvm/CodeGen/PseudoSourceValue.h" 28af76e592c7f9deff0e55c13dbb4a34f07f1c7f64Chris Lattner#include "llvm/MC/MCAsmInfo.h" 29334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "llvm/Support/CommandLine.h" 30f95215f551949d5e5adfbf4753aa833b9009b77aAnton Korobeynikov#include "llvm/Support/Debug.h" 31c25e7581b9b8088910da31702d4ca21c4734c6d7Torok Edwin#include "llvm/Support/ErrorHandling.h" 32334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinusing namespace llvm; 33334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 34334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinstatic cl::opt<bool> 35334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinEnableARM3Addr("enable-arm-3-addr-conv", cl::Hidden, 36334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin cl::desc("Enable ARM 2-addr to 3-addr conv")); 37334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 38f95215f551949d5e5adfbf4753aa833b9009b77aAnton KorobeynikovARMBaseInstrInfo::ARMBaseInstrInfo(const ARMSubtarget& STI) 39f95215f551949d5e5adfbf4753aa833b9009b77aAnton Korobeynikov : TargetInstrInfoImpl(ARMInsts, array_lengthof(ARMInsts)), 40f95215f551949d5e5adfbf4753aa833b9009b77aAnton Korobeynikov Subtarget(STI) { 41334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 42334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 43334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinMachineInstr * 44334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinARMBaseInstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI, 45334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineBasicBlock::iterator &MBBI, 46334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin LiveVariables *LV) const { 4778703ddafe3d037f75d8ca188e4829d238289ac3Evan Cheng // FIXME: Thumb2 support. 4878703ddafe3d037f75d8ca188e4829d238289ac3Evan Cheng 49334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (!EnableARM3Addr) 50334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return NULL; 51334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 52334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineInstr *MI = MBBI; 53334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineFunction &MF = *MI->getParent()->getParent(); 54334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned TSFlags = MI->getDesc().TSFlags; 55334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool isPre = false; 56334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin switch ((TSFlags & ARMII::IndexModeMask) >> ARMII::IndexModeShift) { 57334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin default: return NULL; 58334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMII::IndexModePre: 59334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin isPre = true; 60334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin break; 61334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMII::IndexModePost: 62334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin break; 63334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 64334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 65334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Try splitting an indexed load/store to an un-indexed one plus an add/sub 66334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // operation. 67334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned MemOpc = getUnindexedOpcode(MI->getOpcode()); 68334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (MemOpc == 0) 69334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return NULL; 70334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 71334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineInstr *UpdateMI = NULL; 72334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineInstr *MemMI = NULL; 73334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned AddrMode = (TSFlags & ARMII::AddrModeMask); 74334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const TargetInstrDesc &TID = MI->getDesc(); 75334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned NumOps = TID.getNumOperands(); 76334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool isLoad = !TID.mayStore(); 77334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const MachineOperand &WB = isLoad ? MI->getOperand(1) : MI->getOperand(0); 78334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const MachineOperand &Base = MI->getOperand(2); 79334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const MachineOperand &Offset = MI->getOperand(NumOps-3); 80334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned WBReg = WB.getReg(); 81334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned BaseReg = Base.getReg(); 82334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned OffReg = Offset.getReg(); 83334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned OffImm = MI->getOperand(NumOps-2).getImm(); 84334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin ARMCC::CondCodes Pred = (ARMCC::CondCodes)MI->getOperand(NumOps-1).getImm(); 85334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin switch (AddrMode) { 86334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin default: 87334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin assert(false && "Unknown indexed op!"); 88334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return NULL; 89334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMII::AddrMode2: { 90334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool isSub = ARM_AM::getAM2Op(OffImm) == ARM_AM::sub; 91334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned Amt = ARM_AM::getAM2Offset(OffImm); 92334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (OffReg == 0) { 93e7cbe4118b7ddf05032ff8772a98c51e1637bb5cEvan Cheng if (ARM_AM::getSOImmVal(Amt) == -1) 94334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Can't encode it in a so_imm operand. This transformation will 95334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // add more than 1 instruction. Abandon! 96334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return NULL; 97334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin UpdateMI = BuildMI(MF, MI->getDebugLoc(), 9878703ddafe3d037f75d8ca188e4829d238289ac3Evan Cheng get(isSub ? ARM::SUBri : ARM::ADDri), WBReg) 99e7cbe4118b7ddf05032ff8772a98c51e1637bb5cEvan Cheng .addReg(BaseReg).addImm(Amt) 100334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addImm(Pred).addReg(0).addReg(0); 101334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } else if (Amt != 0) { 102334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin ARM_AM::ShiftOpc ShOpc = ARM_AM::getAM2ShiftOpc(OffImm); 103334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned SOOpc = ARM_AM::getSORegOpc(ShOpc, Amt); 104334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin UpdateMI = BuildMI(MF, MI->getDebugLoc(), 10578703ddafe3d037f75d8ca188e4829d238289ac3Evan Cheng get(isSub ? ARM::SUBrs : ARM::ADDrs), WBReg) 106334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(BaseReg).addReg(OffReg).addReg(0).addImm(SOOpc) 107334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addImm(Pred).addReg(0).addReg(0); 108334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } else 109334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin UpdateMI = BuildMI(MF, MI->getDebugLoc(), 11078703ddafe3d037f75d8ca188e4829d238289ac3Evan Cheng get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg) 111334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(BaseReg).addReg(OffReg) 112334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addImm(Pred).addReg(0).addReg(0); 113334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin break; 114334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 115334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMII::AddrMode3 : { 116334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool isSub = ARM_AM::getAM3Op(OffImm) == ARM_AM::sub; 117334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned Amt = ARM_AM::getAM3Offset(OffImm); 118334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (OffReg == 0) 119334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Immediate is 8-bits. It's guaranteed to fit in a so_imm operand. 120334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin UpdateMI = BuildMI(MF, MI->getDebugLoc(), 12178703ddafe3d037f75d8ca188e4829d238289ac3Evan Cheng get(isSub ? ARM::SUBri : ARM::ADDri), WBReg) 122334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(BaseReg).addImm(Amt) 123334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addImm(Pred).addReg(0).addReg(0); 124334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin else 125334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin UpdateMI = BuildMI(MF, MI->getDebugLoc(), 12678703ddafe3d037f75d8ca188e4829d238289ac3Evan Cheng get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg) 127334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(BaseReg).addReg(OffReg) 128334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addImm(Pred).addReg(0).addReg(0); 129334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin break; 130334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 131334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 132334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 133334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin std::vector<MachineInstr*> NewMIs; 134334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (isPre) { 135334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (isLoad) 136334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MemMI = BuildMI(MF, MI->getDebugLoc(), 137334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin get(MemOpc), MI->getOperand(0).getReg()) 138334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(WBReg).addReg(0).addImm(0).addImm(Pred); 139334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin else 140334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MemMI = BuildMI(MF, MI->getDebugLoc(), 141334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin get(MemOpc)).addReg(MI->getOperand(1).getReg()) 142334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(WBReg).addReg(0).addImm(0).addImm(Pred); 143334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin NewMIs.push_back(MemMI); 144334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin NewMIs.push_back(UpdateMI); 145334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } else { 146334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (isLoad) 147334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MemMI = BuildMI(MF, MI->getDebugLoc(), 148334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin get(MemOpc), MI->getOperand(0).getReg()) 149334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred); 150334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin else 151334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MemMI = BuildMI(MF, MI->getDebugLoc(), 152334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin get(MemOpc)).addReg(MI->getOperand(1).getReg()) 153334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred); 154334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (WB.isDead()) 155334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin UpdateMI->getOperand(0).setIsDead(); 156334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin NewMIs.push_back(UpdateMI); 157334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin NewMIs.push_back(MemMI); 158334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 159334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 160334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Transfer LiveVariables states, kill / dead info. 161334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (LV) { 162334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 163334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineOperand &MO = MI->getOperand(i); 164334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (MO.isReg() && MO.getReg() && 165334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin TargetRegisterInfo::isVirtualRegister(MO.getReg())) { 166334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned Reg = MO.getReg(); 167334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 168334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin LiveVariables::VarInfo &VI = LV->getVarInfo(Reg); 169334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (MO.isDef()) { 170334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineInstr *NewMI = (Reg == WBReg) ? UpdateMI : MemMI; 171334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (MO.isDead()) 172334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin LV->addVirtualRegisterDead(Reg, NewMI); 173334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 174334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (MO.isUse() && MO.isKill()) { 175334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin for (unsigned j = 0; j < 2; ++j) { 176334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Look at the two new MI's in reverse order. 177334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineInstr *NewMI = NewMIs[j]; 178334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (!NewMI->readsRegister(Reg)) 179334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin continue; 180334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin LV->addVirtualRegisterKilled(Reg, NewMI); 181334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (VI.removeKill(MI)) 182334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin VI.Kills.push_back(NewMI); 183334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin break; 184334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 185334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 186334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 187334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 188334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 189334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 190334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MFI->insert(MBBI, NewMIs[1]); 191334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MFI->insert(MBBI, NewMIs[0]); 192334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return NewMIs[0]; 193334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 194334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 195334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// Branch analysis. 196334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinbool 197334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinARMBaseInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB, 198334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineBasicBlock *&FBB, 199334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin SmallVectorImpl<MachineOperand> &Cond, 200334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool AllowModify) const { 201334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // If the block has no terminators, it just falls into the block after it. 202334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineBasicBlock::iterator I = MBB.end(); 203334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) 204334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 205334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 206334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Get the last instruction in the block. 207334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineInstr *LastInst = I; 208334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 209334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // If there is only one terminator instruction, process it. 210334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned LastOpc = LastInst->getOpcode(); 211334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) { 2125ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng if (isUncondBranchOpcode(LastOpc)) { 213334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin TBB = LastInst->getOperand(0).getMBB(); 214334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 215334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 2165ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng if (isCondBranchOpcode(LastOpc)) { 217334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Block ends with fall-through condbranch. 218334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin TBB = LastInst->getOperand(0).getMBB(); 219334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin Cond.push_back(LastInst->getOperand(1)); 220334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin Cond.push_back(LastInst->getOperand(2)); 221334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 222334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 223334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; // Can't handle indirect branch. 224334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 225334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 226334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Get the instruction before it if it is a terminator. 227334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineInstr *SecondLastInst = I; 228334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 229334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // If there are three terminators, we don't know what sort of block this is. 230334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(--I)) 231334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; 232334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 2335ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng // If the block ends with a B and a Bcc, handle it. 234334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned SecondLastOpc = SecondLastInst->getOpcode(); 2355ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng if (isCondBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) { 236334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin TBB = SecondLastInst->getOperand(0).getMBB(); 237334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin Cond.push_back(SecondLastInst->getOperand(1)); 238334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin Cond.push_back(SecondLastInst->getOperand(2)); 239334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin FBB = LastInst->getOperand(0).getMBB(); 240334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 241334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 242334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 243334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // If the block ends with two unconditional branches, handle it. The second 244334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // one is not executed, so remove it. 2455ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng if (isUncondBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) { 246334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin TBB = SecondLastInst->getOperand(0).getMBB(); 247334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin I = LastInst; 248334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (AllowModify) 249334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin I->eraseFromParent(); 250334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 251334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 252334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 253334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // ...likewise if it ends with a branch table followed by an unconditional 254334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // branch. The branch folder can create these, and we must get rid of them for 255334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // correctness of Thumb constant islands. 2568d4de5abfa1bcd974554ea14904ebf7af289e84dBob Wilson if ((isJumpTableBranchOpcode(SecondLastOpc) || 2578d4de5abfa1bcd974554ea14904ebf7af289e84dBob Wilson isIndirectBranchOpcode(SecondLastOpc)) && 2585ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng isUncondBranchOpcode(LastOpc)) { 259334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin I = LastInst; 260334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (AllowModify) 261334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin I->eraseFromParent(); 262334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; 263334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 264334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 265334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Otherwise, can't handle this. 266334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; 267334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 268334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 269334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 270334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinunsigned ARMBaseInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const { 271334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineBasicBlock::iterator I = MBB.end(); 272334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (I == MBB.begin()) return 0; 273334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin --I; 2745ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng if (!isUncondBranchOpcode(I->getOpcode()) && 2755ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng !isCondBranchOpcode(I->getOpcode())) 276334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 0; 277334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 278334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Remove the branch. 279334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin I->eraseFromParent(); 280334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 281334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin I = MBB.end(); 282334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 283334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (I == MBB.begin()) return 1; 284334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin --I; 2855ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng if (!isCondBranchOpcode(I->getOpcode())) 286334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 1; 287334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 288334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Remove the branch. 289334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin I->eraseFromParent(); 290334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 2; 291334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 292334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 293334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinunsigned 294334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinARMBaseInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 295334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineBasicBlock *FBB, 296334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const SmallVectorImpl<MachineOperand> &Cond) const { 297334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // FIXME this should probably have a DebugLoc argument 298334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin DebugLoc dl = DebugLoc::getUnknownLoc(); 2996495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 3006495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ARMFunctionInfo *AFI = MBB.getParent()->getInfo<ARMFunctionInfo>(); 3016495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng int BOpc = !AFI->isThumbFunction() 3026495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ? ARM::B : (AFI->isThumb2Function() ? ARM::t2B : ARM::tB); 3036495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng int BccOpc = !AFI->isThumbFunction() 3046495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ? ARM::Bcc : (AFI->isThumb2Function() ? ARM::t2Bcc : ARM::tBcc); 305334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 306334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Shouldn't be a fall through. 307334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin assert(TBB && "InsertBranch must not be told to insert a fallthrough"); 308334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin assert((Cond.size() == 2 || Cond.size() == 0) && 309334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin "ARM branch conditions have two components!"); 310334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 311334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (FBB == 0) { 312334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (Cond.empty()) // Unconditional branch? 313334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin BuildMI(&MBB, dl, get(BOpc)).addMBB(TBB); 314334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin else 315334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin BuildMI(&MBB, dl, get(BccOpc)).addMBB(TBB) 316334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()); 317334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 1; 318334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 319334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 320334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Two-way conditional branch. 321334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin BuildMI(&MBB, dl, get(BccOpc)).addMBB(TBB) 322334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()); 323334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin BuildMI(&MBB, dl, get(BOpc)).addMBB(FBB); 324334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 2; 325334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 326334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 327334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinbool ARMBaseInstrInfo:: 328334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const { 329334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin ARMCC::CondCodes CC = (ARMCC::CondCodes)(int)Cond[0].getImm(); 330334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin Cond[0].setImm(ARMCC::getOppositeCondition(CC)); 331334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 332334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 333334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 334334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinbool ARMBaseInstrInfo:: 335334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinPredicateInstruction(MachineInstr *MI, 336334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const SmallVectorImpl<MachineOperand> &Pred) const { 337334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned Opc = MI->getOpcode(); 3385ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng if (isUncondBranchOpcode(Opc)) { 3395ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng MI->setDesc(get(getMatchingCondBranchOpcode(Opc))); 340334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI->addOperand(MachineOperand::CreateImm(Pred[0].getImm())); 341334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI->addOperand(MachineOperand::CreateReg(Pred[1].getReg(), false)); 342334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; 343334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 344334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 345334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin int PIdx = MI->findFirstPredOperandIdx(); 346334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (PIdx != -1) { 347334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineOperand &PMO = MI->getOperand(PIdx); 348334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin PMO.setImm(Pred[0].getImm()); 349334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI->getOperand(PIdx+1).setReg(Pred[1].getReg()); 350334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; 351334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 352334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 353334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 354334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 355334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinbool ARMBaseInstrInfo:: 356334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinSubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1, 357334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const SmallVectorImpl<MachineOperand> &Pred2) const { 358334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (Pred1.size() > 2 || Pred2.size() > 2) 359334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 360334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 361334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin ARMCC::CondCodes CC1 = (ARMCC::CondCodes)Pred1[0].getImm(); 362334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin ARMCC::CondCodes CC2 = (ARMCC::CondCodes)Pred2[0].getImm(); 363334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (CC1 == CC2) 364334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; 365334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 366334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin switch (CC1) { 367334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin default: 368334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 369334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMCC::AL: 370334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; 371334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMCC::HS: 372334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return CC2 == ARMCC::HI; 373334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMCC::LS: 374334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return CC2 == ARMCC::LO || CC2 == ARMCC::EQ; 375334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMCC::GE: 376334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return CC2 == ARMCC::GT; 377334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMCC::LE: 378334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return CC2 == ARMCC::LT; 379334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 380334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 381334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 382334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinbool ARMBaseInstrInfo::DefinesPredicate(MachineInstr *MI, 383334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin std::vector<MachineOperand> &Pred) const { 3848fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng // FIXME: This confuses implicit_def with optional CPSR def. 385334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const TargetInstrDesc &TID = MI->getDesc(); 386334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (!TID.getImplicitDefs() && !TID.hasOptionalDef()) 387334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 388334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 389334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool Found = false; 390334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 391334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const MachineOperand &MO = MI->getOperand(i); 392334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (MO.isReg() && MO.getReg() == ARM::CPSR) { 393334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin Pred.push_back(MO); 394334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin Found = true; 395334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 396334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 397334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 398334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return Found; 399334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 400334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 401334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 402334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin/// FIXME: Works around a gcc miscompilation with -fstrict-aliasing 403334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinstatic unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT, 404334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned JTI) DISABLE_INLINE; 405334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinstatic unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT, 406334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned JTI) { 407334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return JT[JTI].MBBs.size(); 408334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 409334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 410334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin/// GetInstSize - Return the size of the specified MachineInstr. 411334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin/// 412334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinunsigned ARMBaseInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const { 413334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const MachineBasicBlock &MBB = *MI->getParent(); 414334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const MachineFunction *MF = MBB.getParent(); 41533adcfb4d217f5f23d9bde8ba02b8e48f9605fc5Chris Lattner const MCAsmInfo *MAI = MF->getTarget().getMCAsmInfo(); 416334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 417334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Basic size info comes from the TSFlags field. 418334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const TargetInstrDesc &TID = MI->getDesc(); 419334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned TSFlags = TID.TSFlags; 420334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 421a0ee862f2e3a0d202244e02459ddcf0dca0e8607Evan Cheng unsigned Opc = MI->getOpcode(); 422334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin switch ((TSFlags & ARMII::SizeMask) >> ARMII::SizeShift) { 423334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin default: { 424334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // If this machine instr is an inline asm, measure it. 425334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (MI->getOpcode() == ARM::INLINEASM) 42633adcfb4d217f5f23d9bde8ba02b8e48f9605fc5Chris Lattner return getInlineAsmLength(MI->getOperand(0).getSymbolName(), *MAI); 427334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (MI->isLabel()) 428334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 0; 429a0ee862f2e3a0d202244e02459ddcf0dca0e8607Evan Cheng switch (Opc) { 430334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin default: 431c23197a26f34f559ea9797de51e187087c039c42Torok Edwin llvm_unreachable("Unknown or unset size field for instr!"); 432334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case TargetInstrInfo::IMPLICIT_DEF: 43326207e5bf1123a793bd9b38bcda2f569a6b45ef2Jakob Stoklund Olesen case TargetInstrInfo::KILL: 434334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case TargetInstrInfo::DBG_LABEL: 435334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case TargetInstrInfo::EH_LABEL: 436334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 0; 437334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 438334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin break; 439334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 440789476240d6b6f8ad9366cadf790a82bd41bb0b3Evan Cheng case ARMII::Size8Bytes: return 8; // ARM instruction x 2. 441789476240d6b6f8ad9366cadf790a82bd41bb0b3Evan Cheng case ARMII::Size4Bytes: return 4; // ARM / Thumb2 instruction. 442789476240d6b6f8ad9366cadf790a82bd41bb0b3Evan Cheng case ARMII::Size2Bytes: return 2; // Thumb1 instruction. 443334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMII::SizeSpecial: { 444a0ee862f2e3a0d202244e02459ddcf0dca0e8607Evan Cheng switch (Opc) { 445334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARM::CONSTPOOL_ENTRY: 446334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // If this machine instr is a constant pool entry, its size is recorded as 447334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // operand #2. 448334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return MI->getOperand(2).getImm(); 449789476240d6b6f8ad9366cadf790a82bd41bb0b3Evan Cheng case ARM::Int_eh_sjlj_setjmp: 450cdc17ebc2b2e9e18ac516b9d246a5c5a3af227d3Jim Grosbach return 24; 4515aa1684e5da9a85286bf7d29da419d261a70c2f2Jim Grosbach case ARM::t2Int_eh_sjlj_setjmp: 4525aa1684e5da9a85286bf7d29da419d261a70c2f2Jim Grosbach return 20; 453334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARM::BR_JTr: 454334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARM::BR_JTm: 455334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARM::BR_JTadd: 456a0ee862f2e3a0d202244e02459ddcf0dca0e8607Evan Cheng case ARM::tBR_JTr: 457d26b14c34cbcee1448b86b524578fc51cc979023Evan Cheng case ARM::t2BR_JT: 458d26b14c34cbcee1448b86b524578fc51cc979023Evan Cheng case ARM::t2TBB: 459d26b14c34cbcee1448b86b524578fc51cc979023Evan Cheng case ARM::t2TBH: { 460334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // These are jumptable branches, i.e. a branch followed by an inlined 461d26b14c34cbcee1448b86b524578fc51cc979023Evan Cheng // jumptable. The size is 4 + 4 * number of entries. For TBB, each 462d26b14c34cbcee1448b86b524578fc51cc979023Evan Cheng // entry is one byte; TBH two byte each. 463a0ee862f2e3a0d202244e02459ddcf0dca0e8607Evan Cheng unsigned EntrySize = (Opc == ARM::t2TBB) 464a0ee862f2e3a0d202244e02459ddcf0dca0e8607Evan Cheng ? 1 : ((Opc == ARM::t2TBH) ? 2 : 4); 465334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned NumOps = TID.getNumOperands(); 466334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineOperand JTOP = 467334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI->getOperand(NumOps - (TID.isPredicable() ? 3 : 2)); 468334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned JTI = JTOP.getIndex(); 469334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo(); 470334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables(); 471334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin assert(JTI < JT.size()); 472334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Thumb instructions are 2 byte aligned, but JT entries are 4 byte 473334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // 4 aligned. The assembler / linker may add 2 byte padding just before 474334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // the JT entries. The size does not include this padding; the 475334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // constant islands pass does separate bookkeeping for it. 476334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // FIXME: If we know the size of the function is less than (1 << 16) *2 477334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // bytes, we can use 16-bit entries instead. Then there won't be an 478334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // alignment issue. 47925f7cfc3cccba6f569f29f79ea533bae960b93c0Evan Cheng unsigned InstSize = (Opc == ARM::tBR_JTr || Opc == ARM::t2BR_JT) ? 2 : 4; 48025f7cfc3cccba6f569f29f79ea533bae960b93c0Evan Cheng unsigned NumEntries = getNumJTEntries(JT, JTI); 48125f7cfc3cccba6f569f29f79ea533bae960b93c0Evan Cheng if (Opc == ARM::t2TBB && (NumEntries & 1)) 48225f7cfc3cccba6f569f29f79ea533bae960b93c0Evan Cheng // Make sure the instruction that follows TBB is 2-byte aligned. 48325f7cfc3cccba6f569f29f79ea533bae960b93c0Evan Cheng // FIXME: Constant island pass should insert an "ALIGN" instruction 48425f7cfc3cccba6f569f29f79ea533bae960b93c0Evan Cheng // instead. 48525f7cfc3cccba6f569f29f79ea533bae960b93c0Evan Cheng ++NumEntries; 48625f7cfc3cccba6f569f29f79ea533bae960b93c0Evan Cheng return NumEntries * EntrySize + InstSize; 487334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 488334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin default: 489334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Otherwise, pseudo-instruction sizes are zero. 490334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 0; 491334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 492334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 493334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 494334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 0; // Not reached 495334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 496334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 497334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin/// Return true if the instruction is a register to register move and 498334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin/// leave the source and dest operands in the passed parameters. 499334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin/// 500334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinbool 501334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinARMBaseInstrInfo::isMoveInstr(const MachineInstr &MI, 502334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned &SrcReg, unsigned &DstReg, 503334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned& SrcSubIdx, unsigned& DstSubIdx) const { 504334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin SrcSubIdx = DstSubIdx = 0; // No sub-registers. 505334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 50668e3c6ae49ff67cba98403e43b5bd0c2499caa41Evan Cheng switch (MI.getOpcode()) { 507dced03fc846fa7cd9558ecb8e33ca98ec29bdcf0Evan Cheng default: break; 50868e3c6ae49ff67cba98403e43b5bd0c2499caa41Evan Cheng case ARM::FCPYS: 50968e3c6ae49ff67cba98403e43b5bd0c2499caa41Evan Cheng case ARM::FCPYD: 51068e3c6ae49ff67cba98403e43b5bd0c2499caa41Evan Cheng case ARM::VMOVD: 511f95215f551949d5e5adfbf4753aa833b9009b77aAnton Korobeynikov case ARM::VMOVQ: { 512334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin SrcReg = MI.getOperand(1).getReg(); 513334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin DstReg = MI.getOperand(0).getReg(); 514334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; 515334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 51668e3c6ae49ff67cba98403e43b5bd0c2499caa41Evan Cheng case ARM::MOVr: 51768e3c6ae49ff67cba98403e43b5bd0c2499caa41Evan Cheng case ARM::tMOVr: 51868e3c6ae49ff67cba98403e43b5bd0c2499caa41Evan Cheng case ARM::tMOVgpr2tgpr: 51968e3c6ae49ff67cba98403e43b5bd0c2499caa41Evan Cheng case ARM::tMOVtgpr2gpr: 52068e3c6ae49ff67cba98403e43b5bd0c2499caa41Evan Cheng case ARM::tMOVgpr2gpr: 52168e3c6ae49ff67cba98403e43b5bd0c2499caa41Evan Cheng case ARM::t2MOVr: { 522334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin assert(MI.getDesc().getNumOperands() >= 2 && 523334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI.getOperand(0).isReg() && 524334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI.getOperand(1).isReg() && 525334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin "Invalid ARM MOV instruction"); 526334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin SrcReg = MI.getOperand(1).getReg(); 527334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin DstReg = MI.getOperand(0).getReg(); 528334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; 529334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 53068e3c6ae49ff67cba98403e43b5bd0c2499caa41Evan Cheng } 531334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 532334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 533334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 534334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 535764ab52dd80310a205c9888bf166d09dab858f90Jim Grosbachunsigned 536334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinARMBaseInstrInfo::isLoadFromStackSlot(const MachineInstr *MI, 537334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin int &FrameIndex) const { 538dced03fc846fa7cd9558ecb8e33ca98ec29bdcf0Evan Cheng switch (MI->getOpcode()) { 539dced03fc846fa7cd9558ecb8e33ca98ec29bdcf0Evan Cheng default: break; 540dced03fc846fa7cd9558ecb8e33ca98ec29bdcf0Evan Cheng case ARM::LDR: 541dced03fc846fa7cd9558ecb8e33ca98ec29bdcf0Evan Cheng case ARM::t2LDRs: // FIXME: don't use t2LDRs to access frame. 542334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (MI->getOperand(1).isFI() && 543334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI->getOperand(2).isReg() && 544334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI->getOperand(3).isImm() && 545334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI->getOperand(2).getReg() == 0 && 546334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI->getOperand(3).getImm() == 0) { 547334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin FrameIndex = MI->getOperand(1).getIndex(); 548334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return MI->getOperand(0).getReg(); 549334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 550dced03fc846fa7cd9558ecb8e33ca98ec29bdcf0Evan Cheng break; 551dced03fc846fa7cd9558ecb8e33ca98ec29bdcf0Evan Cheng case ARM::t2LDRi12: 552dced03fc846fa7cd9558ecb8e33ca98ec29bdcf0Evan Cheng case ARM::tRestore: 5535ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin if (MI->getOperand(1).isFI() && 5545ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin MI->getOperand(2).isImm() && 5555ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin MI->getOperand(2).getImm() == 0) { 5565ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin FrameIndex = MI->getOperand(1).getIndex(); 5575ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin return MI->getOperand(0).getReg(); 5585ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin } 559dced03fc846fa7cd9558ecb8e33ca98ec29bdcf0Evan Cheng break; 560dced03fc846fa7cd9558ecb8e33ca98ec29bdcf0Evan Cheng case ARM::FLDD: 561dced03fc846fa7cd9558ecb8e33ca98ec29bdcf0Evan Cheng case ARM::FLDS: 562334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (MI->getOperand(1).isFI() && 563334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI->getOperand(2).isImm() && 564334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI->getOperand(2).getImm() == 0) { 565334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin FrameIndex = MI->getOperand(1).getIndex(); 566334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return MI->getOperand(0).getReg(); 567334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 568dced03fc846fa7cd9558ecb8e33ca98ec29bdcf0Evan Cheng break; 569334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 570334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 571334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 0; 572334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 573334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 574334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinunsigned 575334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinARMBaseInstrInfo::isStoreToStackSlot(const MachineInstr *MI, 576334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin int &FrameIndex) const { 577dced03fc846fa7cd9558ecb8e33ca98ec29bdcf0Evan Cheng switch (MI->getOpcode()) { 578dced03fc846fa7cd9558ecb8e33ca98ec29bdcf0Evan Cheng default: break; 579dced03fc846fa7cd9558ecb8e33ca98ec29bdcf0Evan Cheng case ARM::STR: 580dced03fc846fa7cd9558ecb8e33ca98ec29bdcf0Evan Cheng case ARM::t2STRs: // FIXME: don't use t2STRs to access frame. 581334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (MI->getOperand(1).isFI() && 582334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI->getOperand(2).isReg() && 583334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI->getOperand(3).isImm() && 584334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI->getOperand(2).getReg() == 0 && 585334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI->getOperand(3).getImm() == 0) { 586334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin FrameIndex = MI->getOperand(1).getIndex(); 587334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return MI->getOperand(0).getReg(); 588334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 589dced03fc846fa7cd9558ecb8e33ca98ec29bdcf0Evan Cheng break; 590dced03fc846fa7cd9558ecb8e33ca98ec29bdcf0Evan Cheng case ARM::t2STRi12: 591dced03fc846fa7cd9558ecb8e33ca98ec29bdcf0Evan Cheng case ARM::tSpill: 5925ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin if (MI->getOperand(1).isFI() && 5935ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin MI->getOperand(2).isImm() && 5945ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin MI->getOperand(2).getImm() == 0) { 5955ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin FrameIndex = MI->getOperand(1).getIndex(); 5965ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin return MI->getOperand(0).getReg(); 5975ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin } 598dced03fc846fa7cd9558ecb8e33ca98ec29bdcf0Evan Cheng break; 599dced03fc846fa7cd9558ecb8e33ca98ec29bdcf0Evan Cheng case ARM::FSTD: 6001d2426c4701650846922d312eb742cc55385c721Evan Cheng case ARM::FSTS: 601334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (MI->getOperand(1).isFI() && 602334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI->getOperand(2).isImm() && 603334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI->getOperand(2).getImm() == 0) { 604334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin FrameIndex = MI->getOperand(1).getIndex(); 605334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return MI->getOperand(0).getReg(); 606334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 607dced03fc846fa7cd9558ecb8e33ca98ec29bdcf0Evan Cheng break; 608334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 609334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 610334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 0; 611334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 612334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 613334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinbool 614334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinARMBaseInstrInfo::copyRegToReg(MachineBasicBlock &MBB, 615334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineBasicBlock::iterator I, 616334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned DestReg, unsigned SrcReg, 617334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const TargetRegisterClass *DestRC, 618334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const TargetRegisterClass *SrcRC) const { 619334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin DebugLoc DL = DebugLoc::getUnknownLoc(); 620334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (I != MBB.end()) DL = I->getDebugLoc(); 621334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 622334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (DestRC != SrcRC) { 6236ca0b9e7220911a6d1fccf34e532e69c7e37cd2fAnton Korobeynikov // Allow DPR / DPR_VFP2 / DPR_8 cross-class copies 624e56f9085b1e96f0cc302c678f1c00877676e455eAnton Korobeynikov // Allow QPR / QPR_VFP2 cross-class copies 6256ca0b9e7220911a6d1fccf34e532e69c7e37cd2fAnton Korobeynikov if (DestRC == ARM::DPRRegisterClass) { 6266ca0b9e7220911a6d1fccf34e532e69c7e37cd2fAnton Korobeynikov if (SrcRC == ARM::DPR_VFP2RegisterClass || 6276ca0b9e7220911a6d1fccf34e532e69c7e37cd2fAnton Korobeynikov SrcRC == ARM::DPR_8RegisterClass) { 6286ca0b9e7220911a6d1fccf34e532e69c7e37cd2fAnton Korobeynikov } else 6296ca0b9e7220911a6d1fccf34e532e69c7e37cd2fAnton Korobeynikov return false; 6306ca0b9e7220911a6d1fccf34e532e69c7e37cd2fAnton Korobeynikov } else if (DestRC == ARM::DPR_VFP2RegisterClass) { 6316ca0b9e7220911a6d1fccf34e532e69c7e37cd2fAnton Korobeynikov if (SrcRC == ARM::DPRRegisterClass || 6326ca0b9e7220911a6d1fccf34e532e69c7e37cd2fAnton Korobeynikov SrcRC == ARM::DPR_8RegisterClass) { 6336ca0b9e7220911a6d1fccf34e532e69c7e37cd2fAnton Korobeynikov } else 6346ca0b9e7220911a6d1fccf34e532e69c7e37cd2fAnton Korobeynikov return false; 6356ca0b9e7220911a6d1fccf34e532e69c7e37cd2fAnton Korobeynikov } else if (DestRC == ARM::DPR_8RegisterClass) { 6366ca0b9e7220911a6d1fccf34e532e69c7e37cd2fAnton Korobeynikov if (SrcRC == ARM::DPRRegisterClass || 6376ca0b9e7220911a6d1fccf34e532e69c7e37cd2fAnton Korobeynikov SrcRC == ARM::DPR_VFP2RegisterClass) { 6386ca0b9e7220911a6d1fccf34e532e69c7e37cd2fAnton Korobeynikov } else 6396ca0b9e7220911a6d1fccf34e532e69c7e37cd2fAnton Korobeynikov return false; 640e56f9085b1e96f0cc302c678f1c00877676e455eAnton Korobeynikov } else if ((DestRC == ARM::QPRRegisterClass && 641e56f9085b1e96f0cc302c678f1c00877676e455eAnton Korobeynikov SrcRC == ARM::QPR_VFP2RegisterClass) || 642e56f9085b1e96f0cc302c678f1c00877676e455eAnton Korobeynikov (DestRC == ARM::QPR_VFP2RegisterClass && 643e56f9085b1e96f0cc302c678f1c00877676e455eAnton Korobeynikov SrcRC == ARM::QPRRegisterClass)) { 6446ca0b9e7220911a6d1fccf34e532e69c7e37cd2fAnton Korobeynikov } else 6457bfdca0206f51132b26094c6f83a5ac97ee0f943David Goodwin return false; 646334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 647334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 6487bfdca0206f51132b26094c6f83a5ac97ee0f943David Goodwin if (DestRC == ARM::GPRRegisterClass) { 64908b93c6a70ae59af375f205cfcffeaa3517577abEvan Cheng AddDefaultCC(AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::MOVr), 650dd6f63209cba0003e67470938830de2cb6917336Evan Cheng DestReg).addReg(SrcReg))); 6517bfdca0206f51132b26094c6f83a5ac97ee0f943David Goodwin } else if (DestRC == ARM::SPRRegisterClass) { 652b74bb1a7a471a77e793d90de158aa4bbc67fe94dEvan Cheng AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FCPYS), DestReg) 653334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(SrcReg)); 654f95215f551949d5e5adfbf4753aa833b9009b77aAnton Korobeynikov } else if (DestRC == ARM::DPR_VFP2RegisterClass || 655f95215f551949d5e5adfbf4753aa833b9009b77aAnton Korobeynikov DestRC == ARM::DPR_8RegisterClass || 656f95215f551949d5e5adfbf4753aa833b9009b77aAnton Korobeynikov SrcRC == ARM::DPR_VFP2RegisterClass || 657f95215f551949d5e5adfbf4753aa833b9009b77aAnton Korobeynikov SrcRC == ARM::DPR_8RegisterClass) { 658f95215f551949d5e5adfbf4753aa833b9009b77aAnton Korobeynikov // Always use neon reg-reg move if source or dest is NEON-only regclass. 659f95215f551949d5e5adfbf4753aa833b9009b77aAnton Korobeynikov BuildMI(MBB, I, DL, get(ARM::VMOVD), DestReg).addReg(SrcReg); 660f95215f551949d5e5adfbf4753aa833b9009b77aAnton Korobeynikov } else if (DestRC == ARM::DPRRegisterClass) { 661f95215f551949d5e5adfbf4753aa833b9009b77aAnton Korobeynikov const ARMBaseRegisterInfo* TRI = &getRegisterInfo(); 662f95215f551949d5e5adfbf4753aa833b9009b77aAnton Korobeynikov 663f95215f551949d5e5adfbf4753aa833b9009b77aAnton Korobeynikov // Find the Machine Instruction which defines SrcReg. 664f95215f551949d5e5adfbf4753aa833b9009b77aAnton Korobeynikov MachineBasicBlock::iterator J = (I == MBB.begin() ? I : prior(I)); 665f95215f551949d5e5adfbf4753aa833b9009b77aAnton Korobeynikov while (J != MBB.begin()) { 666f95215f551949d5e5adfbf4753aa833b9009b77aAnton Korobeynikov if (J->modifiesRegister(SrcReg, TRI)) 667f95215f551949d5e5adfbf4753aa833b9009b77aAnton Korobeynikov break; 668f95215f551949d5e5adfbf4753aa833b9009b77aAnton Korobeynikov --J; 669f95215f551949d5e5adfbf4753aa833b9009b77aAnton Korobeynikov } 670f95215f551949d5e5adfbf4753aa833b9009b77aAnton Korobeynikov 671f95215f551949d5e5adfbf4753aa833b9009b77aAnton Korobeynikov unsigned Domain; 672f95215f551949d5e5adfbf4753aa833b9009b77aAnton Korobeynikov if (J->modifiesRegister(SrcReg, TRI)) { 673f95215f551949d5e5adfbf4753aa833b9009b77aAnton Korobeynikov Domain = J->getDesc().TSFlags & ARMII::DomainMask; 674f95215f551949d5e5adfbf4753aa833b9009b77aAnton Korobeynikov // Instructions in general domain are subreg accesses. 675f95215f551949d5e5adfbf4753aa833b9009b77aAnton Korobeynikov // Map them to NEON reg-reg moves. 676f95215f551949d5e5adfbf4753aa833b9009b77aAnton Korobeynikov if (Domain == ARMII::DomainGeneral) 677f95215f551949d5e5adfbf4753aa833b9009b77aAnton Korobeynikov Domain = ARMII::DomainNEON; 678f95215f551949d5e5adfbf4753aa833b9009b77aAnton Korobeynikov } else { 679f95215f551949d5e5adfbf4753aa833b9009b77aAnton Korobeynikov // We reached the beginning of the BB and found no instruction defining 680f95215f551949d5e5adfbf4753aa833b9009b77aAnton Korobeynikov // the reg. This means that register should be live-in for this BB. 681f95215f551949d5e5adfbf4753aa833b9009b77aAnton Korobeynikov // It's always to better to use NEON reg-reg moves. 682f95215f551949d5e5adfbf4753aa833b9009b77aAnton Korobeynikov Domain = ARMII::DomainNEON; 683f95215f551949d5e5adfbf4753aa833b9009b77aAnton Korobeynikov } 684f95215f551949d5e5adfbf4753aa833b9009b77aAnton Korobeynikov 685f95215f551949d5e5adfbf4753aa833b9009b77aAnton Korobeynikov if ((Domain & ARMII::DomainNEON) && getSubtarget().hasNEON()) { 686f95215f551949d5e5adfbf4753aa833b9009b77aAnton Korobeynikov BuildMI(MBB, I, DL, get(ARM::VMOVQ), DestReg).addReg(SrcReg); 687f95215f551949d5e5adfbf4753aa833b9009b77aAnton Korobeynikov } else { 688f95215f551949d5e5adfbf4753aa833b9009b77aAnton Korobeynikov assert((Domain & ARMII::DomainVFP || 689f95215f551949d5e5adfbf4753aa833b9009b77aAnton Korobeynikov !getSubtarget().hasNEON()) && "Invalid domain!"); 690f95215f551949d5e5adfbf4753aa833b9009b77aAnton Korobeynikov AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FCPYD), DestReg) 691f95215f551949d5e5adfbf4753aa833b9009b77aAnton Korobeynikov .addReg(SrcReg)); 692f95215f551949d5e5adfbf4753aa833b9009b77aAnton Korobeynikov } 693e56f9085b1e96f0cc302c678f1c00877676e455eAnton Korobeynikov } else if (DestRC == ARM::QPRRegisterClass || 694e56f9085b1e96f0cc302c678f1c00877676e455eAnton Korobeynikov DestRC == ARM::QPR_VFP2RegisterClass) { 695b74bb1a7a471a77e793d90de158aa4bbc67fe94dEvan Cheng BuildMI(MBB, I, DL, get(ARM::VMOVQ), DestReg).addReg(SrcReg); 6967bfdca0206f51132b26094c6f83a5ac97ee0f943David Goodwin } else { 697334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 6987bfdca0206f51132b26094c6f83a5ac97ee0f943David Goodwin } 699334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 700334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; 701334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 702334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 703334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinvoid ARMBaseInstrInfo:: 704334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinstoreRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 705334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned SrcReg, bool isKill, int FI, 706334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const TargetRegisterClass *RC) const { 707334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin DebugLoc DL = DebugLoc::getUnknownLoc(); 708334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (I != MBB.end()) DL = I->getDebugLoc(); 709249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MachineFunction &MF = *MBB.getParent(); 710249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MachineFrameInfo &MFI = *MF.getFrameInfo(); 711249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov 712249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MachineMemOperand *MMO = 713ff89dcb06fbd103373436e2d0ae85f252fae2254Evan Cheng MF.getMachineMemOperand(PseudoSourceValue::getFixedStack(FI), 714249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MachineMemOperand::MOStore, 0, 715249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MFI.getObjectSize(FI), 716249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MFI.getObjectAlignment(FI)); 717334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 718334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (RC == ARM::GPRRegisterClass) { 7195732ca084aaa0cd26149e50dd4b487efff37fe41Evan Cheng AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::STR)) 720334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(SrcReg, getKillRegState(isKill)) 721249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov .addFrameIndex(FI).addReg(0).addImm(0).addMemOperand(MMO)); 7226ca0b9e7220911a6d1fccf34e532e69c7e37cd2fAnton Korobeynikov } else if (RC == ARM::DPRRegisterClass || 7236ca0b9e7220911a6d1fccf34e532e69c7e37cd2fAnton Korobeynikov RC == ARM::DPR_VFP2RegisterClass || 7246ca0b9e7220911a6d1fccf34e532e69c7e37cd2fAnton Korobeynikov RC == ARM::DPR_8RegisterClass) { 725b74bb1a7a471a77e793d90de158aa4bbc67fe94dEvan Cheng AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FSTD)) 726334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(SrcReg, getKillRegState(isKill)) 727249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov .addFrameIndex(FI).addImm(0).addMemOperand(MMO)); 728baf31088f1472f48ea5ae81f0b93636cc44ca444Anton Korobeynikov } else if (RC == ARM::SPRRegisterClass) { 729b74bb1a7a471a77e793d90de158aa4bbc67fe94dEvan Cheng AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FSTS)) 730334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(SrcReg, getKillRegState(isKill)) 731249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov .addFrameIndex(FI).addImm(0).addMemOperand(MMO)); 732baf31088f1472f48ea5ae81f0b93636cc44ca444Anton Korobeynikov } else { 733e56f9085b1e96f0cc302c678f1c00877676e455eAnton Korobeynikov assert((RC == ARM::QPRRegisterClass || 734e56f9085b1e96f0cc302c678f1c00877676e455eAnton Korobeynikov RC == ARM::QPR_VFP2RegisterClass) && "Unknown regclass!"); 735baf31088f1472f48ea5ae81f0b93636cc44ca444Anton Korobeynikov // FIXME: Neon instructions should support predicates 736baf31088f1472f48ea5ae81f0b93636cc44ca444Anton Korobeynikov BuildMI(MBB, I, DL, get(ARM::VSTRQ)).addReg(SrcReg, getKillRegState(isKill)) 737249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov .addFrameIndex(FI).addImm(0).addMemOperand(MMO); 738334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 739334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 740334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 741334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinvoid ARMBaseInstrInfo:: 742334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinloadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 743334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned DestReg, int FI, 744334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const TargetRegisterClass *RC) const { 745334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin DebugLoc DL = DebugLoc::getUnknownLoc(); 746334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (I != MBB.end()) DL = I->getDebugLoc(); 747249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MachineFunction &MF = *MBB.getParent(); 748249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MachineFrameInfo &MFI = *MF.getFrameInfo(); 749249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov 750249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MachineMemOperand *MMO = 751ff89dcb06fbd103373436e2d0ae85f252fae2254Evan Cheng MF.getMachineMemOperand(PseudoSourceValue::getFixedStack(FI), 752249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MachineMemOperand::MOLoad, 0, 753249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MFI.getObjectSize(FI), 754249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MFI.getObjectAlignment(FI)); 755334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 756334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (RC == ARM::GPRRegisterClass) { 7575732ca084aaa0cd26149e50dd4b487efff37fe41Evan Cheng AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::LDR), DestReg) 758249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov .addFrameIndex(FI).addReg(0).addImm(0).addMemOperand(MMO)); 7596ca0b9e7220911a6d1fccf34e532e69c7e37cd2fAnton Korobeynikov } else if (RC == ARM::DPRRegisterClass || 7606ca0b9e7220911a6d1fccf34e532e69c7e37cd2fAnton Korobeynikov RC == ARM::DPR_VFP2RegisterClass || 7616ca0b9e7220911a6d1fccf34e532e69c7e37cd2fAnton Korobeynikov RC == ARM::DPR_8RegisterClass) { 762b74bb1a7a471a77e793d90de158aa4bbc67fe94dEvan Cheng AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FLDD), DestReg) 763249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov .addFrameIndex(FI).addImm(0).addMemOperand(MMO)); 764baf31088f1472f48ea5ae81f0b93636cc44ca444Anton Korobeynikov } else if (RC == ARM::SPRRegisterClass) { 765b74bb1a7a471a77e793d90de158aa4bbc67fe94dEvan Cheng AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FLDS), DestReg) 766249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov .addFrameIndex(FI).addImm(0).addMemOperand(MMO)); 767baf31088f1472f48ea5ae81f0b93636cc44ca444Anton Korobeynikov } else { 768e56f9085b1e96f0cc302c678f1c00877676e455eAnton Korobeynikov assert((RC == ARM::QPRRegisterClass || 769e56f9085b1e96f0cc302c678f1c00877676e455eAnton Korobeynikov RC == ARM::QPR_VFP2RegisterClass) && "Unknown regclass!"); 770baf31088f1472f48ea5ae81f0b93636cc44ca444Anton Korobeynikov // FIXME: Neon instructions should support predicates 7715a850beb2e3032e6ff3474ce5317f5454060328cEvan Cheng BuildMI(MBB, I, DL, get(ARM::VLDRQ), DestReg).addFrameIndex(FI).addImm(0). 7725a850beb2e3032e6ff3474ce5317f5454060328cEvan Cheng addMemOperand(MMO); 773334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 774334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 775334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 776334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinMachineInstr *ARMBaseInstrInfo:: 777334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinfoldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI, 778334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const SmallVectorImpl<unsigned> &Ops, int FI) const { 779334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (Ops.size() != 1) return NULL; 780334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 781334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned OpNum = Ops[0]; 782334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned Opc = MI->getOpcode(); 783334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineInstr *NewMI = NULL; 78419068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng if (Opc == ARM::MOVr || Opc == ARM::t2MOVr) { 785334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // If it is updating CPSR, then it cannot be folded. 78619068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng if (MI->getOperand(4).getReg() == ARM::CPSR && !MI->getOperand(4).isDead()) 78719068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng return NULL; 78819068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng unsigned Pred = MI->getOperand(2).getImm(); 78919068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng unsigned PredReg = MI->getOperand(3).getReg(); 79019068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng if (OpNum == 0) { // move -> store 79119068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng unsigned SrcReg = MI->getOperand(1).getReg(); 792ed3ad212ec34fa2866fb70f9e52ddda31032ea3bEvan Cheng unsigned SrcSubReg = MI->getOperand(1).getSubReg(); 79319068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng bool isKill = MI->getOperand(1).isKill(); 79419068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng bool isUndef = MI->getOperand(1).isUndef(); 79519068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng if (Opc == ARM::MOVr) 79619068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::STR)) 797ed3ad212ec34fa2866fb70f9e52ddda31032ea3bEvan Cheng .addReg(SrcReg, 798ed3ad212ec34fa2866fb70f9e52ddda31032ea3bEvan Cheng getKillRegState(isKill) | getUndefRegState(isUndef), 799ed3ad212ec34fa2866fb70f9e52ddda31032ea3bEvan Cheng SrcSubReg) 80019068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng .addFrameIndex(FI).addReg(0).addImm(0).addImm(Pred).addReg(PredReg); 80119068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng else // ARM::t2MOVr 80219068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::t2STRi12)) 803ed3ad212ec34fa2866fb70f9e52ddda31032ea3bEvan Cheng .addReg(SrcReg, 804ed3ad212ec34fa2866fb70f9e52ddda31032ea3bEvan Cheng getKillRegState(isKill) | getUndefRegState(isUndef), 805ed3ad212ec34fa2866fb70f9e52ddda31032ea3bEvan Cheng SrcSubReg) 80619068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg); 80719068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng } else { // move -> load 80819068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng unsigned DstReg = MI->getOperand(0).getReg(); 809ed3ad212ec34fa2866fb70f9e52ddda31032ea3bEvan Cheng unsigned DstSubReg = MI->getOperand(0).getSubReg(); 81019068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng bool isDead = MI->getOperand(0).isDead(); 81119068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng bool isUndef = MI->getOperand(0).isUndef(); 81219068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng if (Opc == ARM::MOVr) 81319068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::LDR)) 81419068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng .addReg(DstReg, 81519068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng RegState::Define | 81619068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng getDeadRegState(isDead) | 817ed3ad212ec34fa2866fb70f9e52ddda31032ea3bEvan Cheng getUndefRegState(isUndef), DstSubReg) 81819068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng .addFrameIndex(FI).addReg(0).addImm(0).addImm(Pred).addReg(PredReg); 81919068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng else // ARM::t2MOVr 82019068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::t2LDRi12)) 82119068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng .addReg(DstReg, 82219068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng RegState::Define | 82319068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng getDeadRegState(isDead) | 824ed3ad212ec34fa2866fb70f9e52ddda31032ea3bEvan Cheng getUndefRegState(isUndef), DstSubReg) 82519068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg); 826334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 82719068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng } else if (Opc == ARM::tMOVgpr2gpr || 82819068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng Opc == ARM::tMOVtgpr2gpr || 82919068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng Opc == ARM::tMOVgpr2tgpr) { 83019068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng if (OpNum == 0) { // move -> store 83119068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng unsigned SrcReg = MI->getOperand(1).getReg(); 832ed3ad212ec34fa2866fb70f9e52ddda31032ea3bEvan Cheng unsigned SrcSubReg = MI->getOperand(1).getSubReg(); 83319068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng bool isKill = MI->getOperand(1).isKill(); 83419068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng bool isUndef = MI->getOperand(1).isUndef(); 83519068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::t2STRi12)) 836ed3ad212ec34fa2866fb70f9e52ddda31032ea3bEvan Cheng .addReg(SrcReg, 837ed3ad212ec34fa2866fb70f9e52ddda31032ea3bEvan Cheng getKillRegState(isKill) | getUndefRegState(isUndef), 838ed3ad212ec34fa2866fb70f9e52ddda31032ea3bEvan Cheng SrcSubReg) 83919068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng .addFrameIndex(FI).addImm(0).addImm(ARMCC::AL).addReg(0); 84019068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng } else { // move -> load 84119068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng unsigned DstReg = MI->getOperand(0).getReg(); 842ed3ad212ec34fa2866fb70f9e52ddda31032ea3bEvan Cheng unsigned DstSubReg = MI->getOperand(0).getSubReg(); 84319068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng bool isDead = MI->getOperand(0).isDead(); 84419068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng bool isUndef = MI->getOperand(0).isUndef(); 84519068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::t2LDRi12)) 84619068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng .addReg(DstReg, 84719068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng RegState::Define | 84819068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng getDeadRegState(isDead) | 849ed3ad212ec34fa2866fb70f9e52ddda31032ea3bEvan Cheng getUndefRegState(isUndef), 850ed3ad212ec34fa2866fb70f9e52ddda31032ea3bEvan Cheng DstSubReg) 85119068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng .addFrameIndex(FI).addImm(0).addImm(ARMCC::AL).addReg(0); 85219068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng } 85319068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng } else if (Opc == ARM::FCPYS) { 854334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned Pred = MI->getOperand(2).getImm(); 855334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned PredReg = MI->getOperand(3).getReg(); 856334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (OpNum == 0) { // move -> store 857334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned SrcReg = MI->getOperand(1).getReg(); 858ed3ad212ec34fa2866fb70f9e52ddda31032ea3bEvan Cheng unsigned SrcSubReg = MI->getOperand(1).getSubReg(); 859334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool isKill = MI->getOperand(1).isKill(); 860334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool isUndef = MI->getOperand(1).isUndef(); 861b74bb1a7a471a77e793d90de158aa4bbc67fe94dEvan Cheng NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::FSTS)) 862ed3ad212ec34fa2866fb70f9e52ddda31032ea3bEvan Cheng .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef), 863ed3ad212ec34fa2866fb70f9e52ddda31032ea3bEvan Cheng SrcSubReg) 864334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addFrameIndex(FI) 865334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addImm(0).addImm(Pred).addReg(PredReg); 866334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } else { // move -> load 867334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned DstReg = MI->getOperand(0).getReg(); 868ed3ad212ec34fa2866fb70f9e52ddda31032ea3bEvan Cheng unsigned DstSubReg = MI->getOperand(0).getSubReg(); 869334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool isDead = MI->getOperand(0).isDead(); 870334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool isUndef = MI->getOperand(0).isUndef(); 871b74bb1a7a471a77e793d90de158aa4bbc67fe94dEvan Cheng NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::FLDS)) 872334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(DstReg, 873334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin RegState::Define | 874334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin getDeadRegState(isDead) | 875ed3ad212ec34fa2866fb70f9e52ddda31032ea3bEvan Cheng getUndefRegState(isUndef), 876ed3ad212ec34fa2866fb70f9e52ddda31032ea3bEvan Cheng DstSubReg) 877334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg); 878334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 879334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 880b74bb1a7a471a77e793d90de158aa4bbc67fe94dEvan Cheng else if (Opc == ARM::FCPYD) { 881334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned Pred = MI->getOperand(2).getImm(); 882334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned PredReg = MI->getOperand(3).getReg(); 883334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (OpNum == 0) { // move -> store 884334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned SrcReg = MI->getOperand(1).getReg(); 885ed3ad212ec34fa2866fb70f9e52ddda31032ea3bEvan Cheng unsigned SrcSubReg = MI->getOperand(1).getSubReg(); 886334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool isKill = MI->getOperand(1).isKill(); 887334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool isUndef = MI->getOperand(1).isUndef(); 888b74bb1a7a471a77e793d90de158aa4bbc67fe94dEvan Cheng NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::FSTD)) 889ed3ad212ec34fa2866fb70f9e52ddda31032ea3bEvan Cheng .addReg(SrcReg, 890ed3ad212ec34fa2866fb70f9e52ddda31032ea3bEvan Cheng getKillRegState(isKill) | getUndefRegState(isUndef), 891ed3ad212ec34fa2866fb70f9e52ddda31032ea3bEvan Cheng SrcSubReg) 892334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg); 893334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } else { // move -> load 894334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned DstReg = MI->getOperand(0).getReg(); 895ed3ad212ec34fa2866fb70f9e52ddda31032ea3bEvan Cheng unsigned DstSubReg = MI->getOperand(0).getSubReg(); 896334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool isDead = MI->getOperand(0).isDead(); 897334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool isUndef = MI->getOperand(0).isUndef(); 898b74bb1a7a471a77e793d90de158aa4bbc67fe94dEvan Cheng NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::FLDD)) 899334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(DstReg, 900334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin RegState::Define | 901334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin getDeadRegState(isDead) | 902ed3ad212ec34fa2866fb70f9e52ddda31032ea3bEvan Cheng getUndefRegState(isUndef), 903ed3ad212ec34fa2866fb70f9e52ddda31032ea3bEvan Cheng DstSubReg) 904334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg); 905334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 906334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 907334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 908334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return NewMI; 909334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 910334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 911764ab52dd80310a205c9888bf166d09dab858f90Jim GrosbachMachineInstr* 912334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinARMBaseInstrInfo::foldMemoryOperandImpl(MachineFunction &MF, 913334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineInstr* MI, 914334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const SmallVectorImpl<unsigned> &Ops, 915334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineInstr* LoadMI) const { 9161f5c9887544ac2cb39d48e35cc6fa7a7b73ed3b0Evan Cheng // FIXME 917334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 0; 918334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 919334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 920334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinbool 921334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinARMBaseInstrInfo::canFoldMemoryOperand(const MachineInstr *MI, 922229464564243b24fb12cece515d727673e726994Evan Cheng const SmallVectorImpl<unsigned> &Ops) const { 923334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (Ops.size() != 1) return false; 924334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 925334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned Opc = MI->getOpcode(); 9265732ca084aaa0cd26149e50dd4b487efff37fe41Evan Cheng if (Opc == ARM::MOVr || Opc == ARM::t2MOVr) { 927334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // If it is updating CPSR, then it cannot be folded. 928229464564243b24fb12cece515d727673e726994Evan Cheng return MI->getOperand(4).getReg() != ARM::CPSR || 929229464564243b24fb12cece515d727673e726994Evan Cheng MI->getOperand(4).isDead(); 93019068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng } else if (Opc == ARM::tMOVgpr2gpr || 93119068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng Opc == ARM::tMOVtgpr2gpr || 93219068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng Opc == ARM::tMOVgpr2tgpr) { 93319068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng return true; 934b74bb1a7a471a77e793d90de158aa4bbc67fe94dEvan Cheng } else if (Opc == ARM::FCPYS || Opc == ARM::FCPYD) { 935334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; 936b74bb1a7a471a77e793d90de158aa4bbc67fe94dEvan Cheng } else if (Opc == ARM::VMOVD || Opc == ARM::VMOVQ) { 937334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; // FIXME 938334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 939334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 940334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 941334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 9425ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng 9438fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng/// getInstrPredicate - If instruction is predicated, returns its predicate 9448fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng/// condition, otherwise returns AL. It also returns the condition code 9458fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng/// register by reference. 9465adb66a646e2ec32265263739f5b01c3f50c176aEvan ChengARMCC::CondCodes 9475adb66a646e2ec32265263739f5b01c3f50c176aEvan Chengllvm::getInstrPredicate(const MachineInstr *MI, unsigned &PredReg) { 9488fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng int PIdx = MI->findFirstPredOperandIdx(); 9498fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng if (PIdx == -1) { 9508fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng PredReg = 0; 9518fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng return ARMCC::AL; 9528fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng } 9538fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng 9548fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng PredReg = MI->getOperand(PIdx+1).getReg(); 9558fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng return (ARMCC::CondCodes)MI->getOperand(PIdx).getImm(); 9568fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng} 9578fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng 9588fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng 9596495f63945e8dbde81f03a1dc2ab421993b9a495Evan Chengint llvm::getMatchingCondBranchOpcode(int Opc) { 9605ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng if (Opc == ARM::B) 9615ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng return ARM::Bcc; 9625ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng else if (Opc == ARM::tB) 9635ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng return ARM::tBcc; 9645ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng else if (Opc == ARM::t2B) 9655ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng return ARM::t2Bcc; 9665ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng 9675ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng llvm_unreachable("Unknown unconditional branch opcode!"); 9685ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng return 0; 9695ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng} 9705ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng 9716495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 9726495f63945e8dbde81f03a1dc2ab421993b9a495Evan Chengvoid llvm::emitARMRegPlusImmediate(MachineBasicBlock &MBB, 9736495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MachineBasicBlock::iterator &MBBI, DebugLoc dl, 9746495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned DestReg, unsigned BaseReg, int NumBytes, 9756495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ARMCC::CondCodes Pred, unsigned PredReg, 9766495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng const ARMBaseInstrInfo &TII) { 9776495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng bool isSub = NumBytes < 0; 9786495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (isSub) NumBytes = -NumBytes; 9796495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 9806495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng while (NumBytes) { 9816495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned RotAmt = ARM_AM::getSOImmValRotate(NumBytes); 9826495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned ThisVal = NumBytes & ARM_AM::rotr32(0xFF, RotAmt); 9836495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng assert(ThisVal && "Didn't extract field correctly"); 9846495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 9856495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // We will handle these bits from offset, clear them. 9866495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng NumBytes &= ~ThisVal; 9876495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 9886495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng assert(ARM_AM::getSOImmVal(ThisVal) != -1 && "Bit extraction didn't work?"); 9896495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 9906495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Build the new ADD / SUB. 9916495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned Opc = isSub ? ARM::SUBri : ARM::ADDri; 9926495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg) 9936495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng .addReg(BaseReg, RegState::Kill).addImm(ThisVal) 9946495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng .addImm((unsigned)Pred).addReg(PredReg).addReg(0); 9956495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng BaseReg = DestReg; 9966495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 9976495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng} 9986495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 999cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Chengbool llvm::rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx, 1000cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng unsigned FrameReg, int &Offset, 1001cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng const ARMBaseInstrInfo &TII) { 10026495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned Opcode = MI.getOpcode(); 10036495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng const TargetInstrDesc &Desc = MI.getDesc(); 10046495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask); 10056495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng bool isSub = false; 1006764ab52dd80310a205c9888bf166d09dab858f90Jim Grosbach 10076495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Memory operands in inline assembly always use AddrMode2. 10086495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (Opcode == ARM::INLINEASM) 10096495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng AddrMode = ARMII::AddrMode2; 1010764ab52dd80310a205c9888bf166d09dab858f90Jim Grosbach 10116495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (Opcode == ARM::ADDri) { 10126495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng Offset += MI.getOperand(FrameRegIdx+1).getImm(); 10136495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (Offset == 0) { 10146495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Turn it into a move. 10156495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MI.setDesc(TII.get(ARM::MOVr)); 10166495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false); 10176495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MI.RemoveOperand(FrameRegIdx+1); 1018cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng Offset = 0; 1019cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng return true; 10206495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } else if (Offset < 0) { 10216495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng Offset = -Offset; 10226495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng isSub = true; 10236495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MI.setDesc(TII.get(ARM::SUBri)); 10246495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 10256495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 10266495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Common case: small offset, fits into instruction. 10276495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (ARM_AM::getSOImmVal(Offset) != -1) { 10286495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Replace the FrameIndex with sp / fp 10296495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false); 10306495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset); 1031cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng Offset = 0; 1032cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng return true; 10336495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 10346495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 10356495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Otherwise, pull as much of the immedidate into this ADDri/SUBri 10366495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // as possible. 10376495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned RotAmt = ARM_AM::getSOImmValRotate(Offset); 10386495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xFF, RotAmt); 10396495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 10406495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // We will handle these bits from offset, clear them. 10416495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng Offset &= ~ThisImmVal; 10426495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 10436495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Get the properly encoded SOImmVal field. 10446495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng assert(ARM_AM::getSOImmVal(ThisImmVal) != -1 && 10456495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng "Bit extraction didn't work?"); 10466495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MI.getOperand(FrameRegIdx+1).ChangeToImmediate(ThisImmVal); 10476495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } else { 10486495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned ImmIdx = 0; 10496495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng int InstrOffs = 0; 10506495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned NumBits = 0; 10516495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned Scale = 1; 10526495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng switch (AddrMode) { 10536495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng case ARMII::AddrMode2: { 10546495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ImmIdx = FrameRegIdx+2; 10556495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng InstrOffs = ARM_AM::getAM2Offset(MI.getOperand(ImmIdx).getImm()); 10566495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (ARM_AM::getAM2Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub) 10576495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng InstrOffs *= -1; 10586495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng NumBits = 12; 10596495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng break; 10606495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 10616495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng case ARMII::AddrMode3: { 10626495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ImmIdx = FrameRegIdx+2; 10636495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng InstrOffs = ARM_AM::getAM3Offset(MI.getOperand(ImmIdx).getImm()); 10646495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (ARM_AM::getAM3Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub) 10656495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng InstrOffs *= -1; 10666495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng NumBits = 8; 10676495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng break; 10686495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 1069baf31088f1472f48ea5ae81f0b93636cc44ca444Anton Korobeynikov case ARMII::AddrMode4: 1070cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng // Can't fold any offset even if it's zero. 1071cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng return false; 10726495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng case ARMII::AddrMode5: { 10736495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ImmIdx = FrameRegIdx+1; 10746495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng InstrOffs = ARM_AM::getAM5Offset(MI.getOperand(ImmIdx).getImm()); 10756495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (ARM_AM::getAM5Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub) 10766495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng InstrOffs *= -1; 10776495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng NumBits = 8; 10786495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng Scale = 4; 10796495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng break; 10806495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 10816495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng default: 10826495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng llvm_unreachable("Unsupported addressing mode!"); 10836495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng break; 10846495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 10856495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 10866495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng Offset += InstrOffs * Scale; 10876495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!"); 10886495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (Offset < 0) { 10896495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng Offset = -Offset; 10906495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng isSub = true; 10916495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 10926495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 10936495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Attempt to fold address comp. if opcode has offset bits 10946495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (NumBits > 0) { 10956495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Common case: small offset, fits into instruction. 10966495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MachineOperand &ImmOp = MI.getOperand(ImmIdx); 10976495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng int ImmedOffset = Offset / Scale; 10986495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned Mask = (1 << NumBits) - 1; 10996495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if ((unsigned)Offset <= Mask * Scale) { 11006495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Replace the FrameIndex with sp 11016495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false); 11026495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (isSub) 11036495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ImmedOffset |= 1 << NumBits; 11046495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ImmOp.ChangeToImmediate(ImmedOffset); 1105cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng Offset = 0; 1106cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng return true; 11076495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 1108764ab52dd80310a205c9888bf166d09dab858f90Jim Grosbach 11096495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Otherwise, it didn't fit. Pull in what we can to simplify the immed. 11106495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ImmedOffset = ImmedOffset & Mask; 11116495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (isSub) 11126495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ImmedOffset |= 1 << NumBits; 11136495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ImmOp.ChangeToImmediate(ImmedOffset); 11146495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng Offset &= ~(Mask*Scale); 11156495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 11166495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 11176495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 1118cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng Offset = (isSub) ? -Offset : Offset; 1119cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng return Offset == 0; 11206495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng} 1121