ARMBaseInstrInfo.cpp revision fdc834046efd427d474e3b899ec69354c05071e0
131c24bf5b39cc8391d4cfdbf8cf5163975fdb81eJim Grosbach//===- ARMBaseInstrInfo.cpp - ARM Instruction Information -------*- C++ -*-===// 2334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// 3334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// The LLVM Compiler Infrastructure 4334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// 5334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// This file is distributed under the University of Illinois Open Source 6334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// License. See LICENSE.TXT for details. 7334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// 8334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin//===----------------------------------------------------------------------===// 9334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// 10334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// This file contains the Base ARM implementation of the TargetInstrInfo class. 11334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// 12334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin//===----------------------------------------------------------------------===// 13334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 14334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "ARMBaseInstrInfo.h" 15334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "ARM.h" 16334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "ARMAddressingModes.h" 17d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng#include "ARMConstantPoolValue.h" 18334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "ARMGenInstrInfo.inc" 19334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "ARMMachineFunctionInfo.h" 20f95215f551949d5e5adfbf4753aa833b9009b77aAnton Korobeynikov#include "ARMRegisterInfo.h" 21fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng#include "llvm/Constants.h" 22fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng#include "llvm/Function.h" 23fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng#include "llvm/GlobalValue.h" 24334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "llvm/ADT/STLExtras.h" 25334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "llvm/CodeGen/LiveVariables.h" 26d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng#include "llvm/CodeGen/MachineConstantPool.h" 27334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "llvm/CodeGen/MachineFrameInfo.h" 28334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "llvm/CodeGen/MachineInstrBuilder.h" 29334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "llvm/CodeGen/MachineJumpTableInfo.h" 30249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov#include "llvm/CodeGen/MachineMemOperand.h" 31249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov#include "llvm/CodeGen/PseudoSourceValue.h" 32af76e592c7f9deff0e55c13dbb4a34f07f1c7f64Chris Lattner#include "llvm/MC/MCAsmInfo.h" 33334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "llvm/Support/CommandLine.h" 34f95215f551949d5e5adfbf4753aa833b9009b77aAnton Korobeynikov#include "llvm/Support/Debug.h" 35c25e7581b9b8088910da31702d4ca21c4734c6d7Torok Edwin#include "llvm/Support/ErrorHandling.h" 36334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinusing namespace llvm; 37334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 38334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinstatic cl::opt<bool> 39334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinEnableARM3Addr("enable-arm-3-addr-conv", cl::Hidden, 40334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin cl::desc("Enable ARM 2-addr to 3-addr conv")); 41334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 42f95215f551949d5e5adfbf4753aa833b9009b77aAnton KorobeynikovARMBaseInstrInfo::ARMBaseInstrInfo(const ARMSubtarget& STI) 43f95215f551949d5e5adfbf4753aa833b9009b77aAnton Korobeynikov : TargetInstrInfoImpl(ARMInsts, array_lengthof(ARMInsts)), 44f95215f551949d5e5adfbf4753aa833b9009b77aAnton Korobeynikov Subtarget(STI) { 45334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 46334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 47334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinMachineInstr * 48334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinARMBaseInstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI, 49334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineBasicBlock::iterator &MBBI, 50334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin LiveVariables *LV) const { 5178703ddafe3d037f75d8ca188e4829d238289ac3Evan Cheng // FIXME: Thumb2 support. 5278703ddafe3d037f75d8ca188e4829d238289ac3Evan Cheng 53334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (!EnableARM3Addr) 54334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return NULL; 55334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 56334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineInstr *MI = MBBI; 57334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineFunction &MF = *MI->getParent()->getParent(); 58334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned TSFlags = MI->getDesc().TSFlags; 59334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool isPre = false; 60334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin switch ((TSFlags & ARMII::IndexModeMask) >> ARMII::IndexModeShift) { 61334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin default: return NULL; 62334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMII::IndexModePre: 63334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin isPre = true; 64334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin break; 65334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMII::IndexModePost: 66334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin break; 67334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 68334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 69334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Try splitting an indexed load/store to an un-indexed one plus an add/sub 70334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // operation. 71334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned MemOpc = getUnindexedOpcode(MI->getOpcode()); 72334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (MemOpc == 0) 73334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return NULL; 74334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 75334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineInstr *UpdateMI = NULL; 76334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineInstr *MemMI = NULL; 77334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned AddrMode = (TSFlags & ARMII::AddrModeMask); 78334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const TargetInstrDesc &TID = MI->getDesc(); 79334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned NumOps = TID.getNumOperands(); 80334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool isLoad = !TID.mayStore(); 81334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const MachineOperand &WB = isLoad ? MI->getOperand(1) : MI->getOperand(0); 82334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const MachineOperand &Base = MI->getOperand(2); 83334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const MachineOperand &Offset = MI->getOperand(NumOps-3); 84334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned WBReg = WB.getReg(); 85334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned BaseReg = Base.getReg(); 86334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned OffReg = Offset.getReg(); 87334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned OffImm = MI->getOperand(NumOps-2).getImm(); 88334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin ARMCC::CondCodes Pred = (ARMCC::CondCodes)MI->getOperand(NumOps-1).getImm(); 89334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin switch (AddrMode) { 90334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin default: 91334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin assert(false && "Unknown indexed op!"); 92334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return NULL; 93334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMII::AddrMode2: { 94334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool isSub = ARM_AM::getAM2Op(OffImm) == ARM_AM::sub; 95334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned Amt = ARM_AM::getAM2Offset(OffImm); 96334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (OffReg == 0) { 97e7cbe4118b7ddf05032ff8772a98c51e1637bb5cEvan Cheng if (ARM_AM::getSOImmVal(Amt) == -1) 98334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Can't encode it in a so_imm operand. This transformation will 99334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // add more than 1 instruction. Abandon! 100334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return NULL; 101334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin UpdateMI = BuildMI(MF, MI->getDebugLoc(), 10278703ddafe3d037f75d8ca188e4829d238289ac3Evan Cheng get(isSub ? ARM::SUBri : ARM::ADDri), WBReg) 103e7cbe4118b7ddf05032ff8772a98c51e1637bb5cEvan Cheng .addReg(BaseReg).addImm(Amt) 104334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addImm(Pred).addReg(0).addReg(0); 105334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } else if (Amt != 0) { 106334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin ARM_AM::ShiftOpc ShOpc = ARM_AM::getAM2ShiftOpc(OffImm); 107334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned SOOpc = ARM_AM::getSORegOpc(ShOpc, Amt); 108334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin UpdateMI = BuildMI(MF, MI->getDebugLoc(), 10978703ddafe3d037f75d8ca188e4829d238289ac3Evan Cheng get(isSub ? ARM::SUBrs : ARM::ADDrs), WBReg) 110334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(BaseReg).addReg(OffReg).addReg(0).addImm(SOOpc) 111334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addImm(Pred).addReg(0).addReg(0); 112334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } else 113334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin UpdateMI = BuildMI(MF, MI->getDebugLoc(), 11478703ddafe3d037f75d8ca188e4829d238289ac3Evan Cheng get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg) 115334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(BaseReg).addReg(OffReg) 116334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addImm(Pred).addReg(0).addReg(0); 117334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin break; 118334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 119334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMII::AddrMode3 : { 120334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool isSub = ARM_AM::getAM3Op(OffImm) == ARM_AM::sub; 121334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned Amt = ARM_AM::getAM3Offset(OffImm); 122334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (OffReg == 0) 123334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Immediate is 8-bits. It's guaranteed to fit in a so_imm operand. 124334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin UpdateMI = BuildMI(MF, MI->getDebugLoc(), 12578703ddafe3d037f75d8ca188e4829d238289ac3Evan Cheng get(isSub ? ARM::SUBri : ARM::ADDri), WBReg) 126334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(BaseReg).addImm(Amt) 127334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addImm(Pred).addReg(0).addReg(0); 128334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin else 129334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin UpdateMI = BuildMI(MF, MI->getDebugLoc(), 13078703ddafe3d037f75d8ca188e4829d238289ac3Evan Cheng get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg) 131334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(BaseReg).addReg(OffReg) 132334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addImm(Pred).addReg(0).addReg(0); 133334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin break; 134334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 135334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 136334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 137334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin std::vector<MachineInstr*> NewMIs; 138334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (isPre) { 139334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (isLoad) 140334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MemMI = BuildMI(MF, MI->getDebugLoc(), 141334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin get(MemOpc), MI->getOperand(0).getReg()) 142334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(WBReg).addReg(0).addImm(0).addImm(Pred); 143334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin else 144334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MemMI = BuildMI(MF, MI->getDebugLoc(), 145334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin get(MemOpc)).addReg(MI->getOperand(1).getReg()) 146334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(WBReg).addReg(0).addImm(0).addImm(Pred); 147334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin NewMIs.push_back(MemMI); 148334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin NewMIs.push_back(UpdateMI); 149334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } else { 150334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (isLoad) 151334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MemMI = BuildMI(MF, MI->getDebugLoc(), 152334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin get(MemOpc), MI->getOperand(0).getReg()) 153334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred); 154334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin else 155334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MemMI = BuildMI(MF, MI->getDebugLoc(), 156334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin get(MemOpc)).addReg(MI->getOperand(1).getReg()) 157334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred); 158334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (WB.isDead()) 159334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin UpdateMI->getOperand(0).setIsDead(); 160334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin NewMIs.push_back(UpdateMI); 161334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin NewMIs.push_back(MemMI); 162334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 163334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 164334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Transfer LiveVariables states, kill / dead info. 165334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (LV) { 166334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 167334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineOperand &MO = MI->getOperand(i); 168334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (MO.isReg() && MO.getReg() && 169334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin TargetRegisterInfo::isVirtualRegister(MO.getReg())) { 170334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned Reg = MO.getReg(); 171334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 172334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin LiveVariables::VarInfo &VI = LV->getVarInfo(Reg); 173334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (MO.isDef()) { 174334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineInstr *NewMI = (Reg == WBReg) ? UpdateMI : MemMI; 175334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (MO.isDead()) 176334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin LV->addVirtualRegisterDead(Reg, NewMI); 177334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 178334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (MO.isUse() && MO.isKill()) { 179334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin for (unsigned j = 0; j < 2; ++j) { 180334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Look at the two new MI's in reverse order. 181334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineInstr *NewMI = NewMIs[j]; 182334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (!NewMI->readsRegister(Reg)) 183334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin continue; 184334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin LV->addVirtualRegisterKilled(Reg, NewMI); 185334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (VI.removeKill(MI)) 186334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin VI.Kills.push_back(NewMI); 187334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin break; 188334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 189334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 190334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 191334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 192334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 193334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 194334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MFI->insert(MBBI, NewMIs[1]); 195334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MFI->insert(MBBI, NewMIs[0]); 196334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return NewMIs[0]; 197334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 198334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 199334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// Branch analysis. 200334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinbool 201334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinARMBaseInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB, 202334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineBasicBlock *&FBB, 203334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin SmallVectorImpl<MachineOperand> &Cond, 204334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool AllowModify) const { 205334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // If the block has no terminators, it just falls into the block after it. 206334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineBasicBlock::iterator I = MBB.end(); 207334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) 208334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 209334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 210334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Get the last instruction in the block. 211334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineInstr *LastInst = I; 212334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 213334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // If there is only one terminator instruction, process it. 214334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned LastOpc = LastInst->getOpcode(); 215334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) { 2165ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng if (isUncondBranchOpcode(LastOpc)) { 217334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin TBB = LastInst->getOperand(0).getMBB(); 218334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 219334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 2205ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng if (isCondBranchOpcode(LastOpc)) { 221334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Block ends with fall-through condbranch. 222334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin TBB = LastInst->getOperand(0).getMBB(); 223334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin Cond.push_back(LastInst->getOperand(1)); 224334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin Cond.push_back(LastInst->getOperand(2)); 225334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 226334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 227334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; // Can't handle indirect branch. 228334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 229334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 230334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Get the instruction before it if it is a terminator. 231334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineInstr *SecondLastInst = I; 232334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 233334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // If there are three terminators, we don't know what sort of block this is. 234334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(--I)) 235334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; 236334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 2375ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng // If the block ends with a B and a Bcc, handle it. 238334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned SecondLastOpc = SecondLastInst->getOpcode(); 2395ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng if (isCondBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) { 240334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin TBB = SecondLastInst->getOperand(0).getMBB(); 241334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin Cond.push_back(SecondLastInst->getOperand(1)); 242334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin Cond.push_back(SecondLastInst->getOperand(2)); 243334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin FBB = LastInst->getOperand(0).getMBB(); 244334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 245334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 246334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 247334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // If the block ends with two unconditional branches, handle it. The second 248334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // one is not executed, so remove it. 2495ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng if (isUncondBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) { 250334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin TBB = SecondLastInst->getOperand(0).getMBB(); 251334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin I = LastInst; 252334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (AllowModify) 253334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin I->eraseFromParent(); 254334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 255334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 256334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 257334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // ...likewise if it ends with a branch table followed by an unconditional 258334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // branch. The branch folder can create these, and we must get rid of them for 259334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // correctness of Thumb constant islands. 2608d4de5abfa1bcd974554ea14904ebf7af289e84dBob Wilson if ((isJumpTableBranchOpcode(SecondLastOpc) || 2618d4de5abfa1bcd974554ea14904ebf7af289e84dBob Wilson isIndirectBranchOpcode(SecondLastOpc)) && 2625ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng isUncondBranchOpcode(LastOpc)) { 263334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin I = LastInst; 264334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (AllowModify) 265334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin I->eraseFromParent(); 266334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; 267334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 268334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 269334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Otherwise, can't handle this. 270334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; 271334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 272334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 273334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 274334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinunsigned ARMBaseInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const { 275334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineBasicBlock::iterator I = MBB.end(); 276334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (I == MBB.begin()) return 0; 277334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin --I; 2785ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng if (!isUncondBranchOpcode(I->getOpcode()) && 2795ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng !isCondBranchOpcode(I->getOpcode())) 280334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 0; 281334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 282334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Remove the branch. 283334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin I->eraseFromParent(); 284334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 285334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin I = MBB.end(); 286334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 287334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (I == MBB.begin()) return 1; 288334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin --I; 2895ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng if (!isCondBranchOpcode(I->getOpcode())) 290334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 1; 291334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 292334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Remove the branch. 293334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin I->eraseFromParent(); 294334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 2; 295334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 296334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 297334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinunsigned 298334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinARMBaseInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 299334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineBasicBlock *FBB, 300334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const SmallVectorImpl<MachineOperand> &Cond) const { 301334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // FIXME this should probably have a DebugLoc argument 302334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin DebugLoc dl = DebugLoc::getUnknownLoc(); 3036495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 3046495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ARMFunctionInfo *AFI = MBB.getParent()->getInfo<ARMFunctionInfo>(); 3056495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng int BOpc = !AFI->isThumbFunction() 3066495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ? ARM::B : (AFI->isThumb2Function() ? ARM::t2B : ARM::tB); 3076495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng int BccOpc = !AFI->isThumbFunction() 3086495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ? ARM::Bcc : (AFI->isThumb2Function() ? ARM::t2Bcc : ARM::tBcc); 309334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 310334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Shouldn't be a fall through. 311334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin assert(TBB && "InsertBranch must not be told to insert a fallthrough"); 312334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin assert((Cond.size() == 2 || Cond.size() == 0) && 313334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin "ARM branch conditions have two components!"); 314334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 315334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (FBB == 0) { 316334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (Cond.empty()) // Unconditional branch? 317334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin BuildMI(&MBB, dl, get(BOpc)).addMBB(TBB); 318334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin else 319334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin BuildMI(&MBB, dl, get(BccOpc)).addMBB(TBB) 320334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()); 321334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 1; 322334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 323334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 324334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Two-way conditional branch. 325334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin BuildMI(&MBB, dl, get(BccOpc)).addMBB(TBB) 326334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()); 327334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin BuildMI(&MBB, dl, get(BOpc)).addMBB(FBB); 328334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 2; 329334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 330334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 331334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinbool ARMBaseInstrInfo:: 332334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const { 333334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin ARMCC::CondCodes CC = (ARMCC::CondCodes)(int)Cond[0].getImm(); 334334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin Cond[0].setImm(ARMCC::getOppositeCondition(CC)); 335334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 336334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 337334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 338334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinbool ARMBaseInstrInfo:: 339334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinPredicateInstruction(MachineInstr *MI, 340334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const SmallVectorImpl<MachineOperand> &Pred) const { 341334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned Opc = MI->getOpcode(); 3425ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng if (isUncondBranchOpcode(Opc)) { 3435ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng MI->setDesc(get(getMatchingCondBranchOpcode(Opc))); 344334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI->addOperand(MachineOperand::CreateImm(Pred[0].getImm())); 345334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI->addOperand(MachineOperand::CreateReg(Pred[1].getReg(), false)); 346334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; 347334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 348334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 349334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin int PIdx = MI->findFirstPredOperandIdx(); 350334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (PIdx != -1) { 351334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineOperand &PMO = MI->getOperand(PIdx); 352334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin PMO.setImm(Pred[0].getImm()); 353334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI->getOperand(PIdx+1).setReg(Pred[1].getReg()); 354334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; 355334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 356334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 357334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 358334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 359334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinbool ARMBaseInstrInfo:: 360334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinSubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1, 361334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const SmallVectorImpl<MachineOperand> &Pred2) const { 362334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (Pred1.size() > 2 || Pred2.size() > 2) 363334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 364334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 365334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin ARMCC::CondCodes CC1 = (ARMCC::CondCodes)Pred1[0].getImm(); 366334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin ARMCC::CondCodes CC2 = (ARMCC::CondCodes)Pred2[0].getImm(); 367334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (CC1 == CC2) 368334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; 369334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 370334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin switch (CC1) { 371334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin default: 372334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 373334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMCC::AL: 374334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; 375334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMCC::HS: 376334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return CC2 == ARMCC::HI; 377334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMCC::LS: 378334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return CC2 == ARMCC::LO || CC2 == ARMCC::EQ; 379334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMCC::GE: 380334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return CC2 == ARMCC::GT; 381334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMCC::LE: 382334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return CC2 == ARMCC::LT; 383334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 384334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 385334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 386334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinbool ARMBaseInstrInfo::DefinesPredicate(MachineInstr *MI, 387334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin std::vector<MachineOperand> &Pred) const { 3888fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng // FIXME: This confuses implicit_def with optional CPSR def. 389334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const TargetInstrDesc &TID = MI->getDesc(); 390334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (!TID.getImplicitDefs() && !TID.hasOptionalDef()) 391334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 392334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 393334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool Found = false; 394334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 395334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const MachineOperand &MO = MI->getOperand(i); 396334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (MO.isReg() && MO.getReg() == ARM::CPSR) { 397334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin Pred.push_back(MO); 398334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin Found = true; 399334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 400334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 401334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 402334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return Found; 403334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 404334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 405334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 406334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin/// FIXME: Works around a gcc miscompilation with -fstrict-aliasing 407334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinstatic unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT, 408334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned JTI) DISABLE_INLINE; 409334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinstatic unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT, 410334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned JTI) { 411334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return JT[JTI].MBBs.size(); 412334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 413334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 414334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin/// GetInstSize - Return the size of the specified MachineInstr. 415334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin/// 416334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinunsigned ARMBaseInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const { 417334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const MachineBasicBlock &MBB = *MI->getParent(); 418334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const MachineFunction *MF = MBB.getParent(); 41933adcfb4d217f5f23d9bde8ba02b8e48f9605fc5Chris Lattner const MCAsmInfo *MAI = MF->getTarget().getMCAsmInfo(); 420334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 421334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Basic size info comes from the TSFlags field. 422334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const TargetInstrDesc &TID = MI->getDesc(); 423334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned TSFlags = TID.TSFlags; 424334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 425a0ee862f2e3a0d202244e02459ddcf0dca0e8607Evan Cheng unsigned Opc = MI->getOpcode(); 426334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin switch ((TSFlags & ARMII::SizeMask) >> ARMII::SizeShift) { 427334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin default: { 428334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // If this machine instr is an inline asm, measure it. 429334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (MI->getOpcode() == ARM::INLINEASM) 43033adcfb4d217f5f23d9bde8ba02b8e48f9605fc5Chris Lattner return getInlineAsmLength(MI->getOperand(0).getSymbolName(), *MAI); 431334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (MI->isLabel()) 432334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 0; 433a0ee862f2e3a0d202244e02459ddcf0dca0e8607Evan Cheng switch (Opc) { 434334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin default: 435c23197a26f34f559ea9797de51e187087c039c42Torok Edwin llvm_unreachable("Unknown or unset size field for instr!"); 436334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case TargetInstrInfo::IMPLICIT_DEF: 43726207e5bf1123a793bd9b38bcda2f569a6b45ef2Jakob Stoklund Olesen case TargetInstrInfo::KILL: 438334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case TargetInstrInfo::DBG_LABEL: 439334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case TargetInstrInfo::EH_LABEL: 440334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 0; 441334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 442334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin break; 443334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 444789476240d6b6f8ad9366cadf790a82bd41bb0b3Evan Cheng case ARMII::Size8Bytes: return 8; // ARM instruction x 2. 445789476240d6b6f8ad9366cadf790a82bd41bb0b3Evan Cheng case ARMII::Size4Bytes: return 4; // ARM / Thumb2 instruction. 446789476240d6b6f8ad9366cadf790a82bd41bb0b3Evan Cheng case ARMII::Size2Bytes: return 2; // Thumb1 instruction. 447334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARMII::SizeSpecial: { 448a0ee862f2e3a0d202244e02459ddcf0dca0e8607Evan Cheng switch (Opc) { 449334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARM::CONSTPOOL_ENTRY: 450334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // If this machine instr is a constant pool entry, its size is recorded as 451334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // operand #2. 452334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return MI->getOperand(2).getImm(); 453789476240d6b6f8ad9366cadf790a82bd41bb0b3Evan Cheng case ARM::Int_eh_sjlj_setjmp: 454cdc17ebc2b2e9e18ac516b9d246a5c5a3af227d3Jim Grosbach return 24; 4555aa1684e5da9a85286bf7d29da419d261a70c2f2Jim Grosbach case ARM::t2Int_eh_sjlj_setjmp: 4565a1cd36019ca3cbae811f2800631b5b56a9ffdc2Evan Cheng return 22; 457334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARM::BR_JTr: 458334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARM::BR_JTm: 459334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin case ARM::BR_JTadd: 460a0ee862f2e3a0d202244e02459ddcf0dca0e8607Evan Cheng case ARM::tBR_JTr: 461d26b14c34cbcee1448b86b524578fc51cc979023Evan Cheng case ARM::t2BR_JT: 462d26b14c34cbcee1448b86b524578fc51cc979023Evan Cheng case ARM::t2TBB: 463d26b14c34cbcee1448b86b524578fc51cc979023Evan Cheng case ARM::t2TBH: { 464334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // These are jumptable branches, i.e. a branch followed by an inlined 465d26b14c34cbcee1448b86b524578fc51cc979023Evan Cheng // jumptable. The size is 4 + 4 * number of entries. For TBB, each 466d26b14c34cbcee1448b86b524578fc51cc979023Evan Cheng // entry is one byte; TBH two byte each. 467a0ee862f2e3a0d202244e02459ddcf0dca0e8607Evan Cheng unsigned EntrySize = (Opc == ARM::t2TBB) 468a0ee862f2e3a0d202244e02459ddcf0dca0e8607Evan Cheng ? 1 : ((Opc == ARM::t2TBH) ? 2 : 4); 469334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned NumOps = TID.getNumOperands(); 470334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineOperand JTOP = 471334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI->getOperand(NumOps - (TID.isPredicable() ? 3 : 2)); 472334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned JTI = JTOP.getIndex(); 473334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo(); 474334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables(); 475334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin assert(JTI < JT.size()); 476334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Thumb instructions are 2 byte aligned, but JT entries are 4 byte 477334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // 4 aligned. The assembler / linker may add 2 byte padding just before 478334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // the JT entries. The size does not include this padding; the 479334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // constant islands pass does separate bookkeeping for it. 480334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // FIXME: If we know the size of the function is less than (1 << 16) *2 481334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // bytes, we can use 16-bit entries instead. Then there won't be an 482334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // alignment issue. 48325f7cfc3cccba6f569f29f79ea533bae960b93c0Evan Cheng unsigned InstSize = (Opc == ARM::tBR_JTr || Opc == ARM::t2BR_JT) ? 2 : 4; 48425f7cfc3cccba6f569f29f79ea533bae960b93c0Evan Cheng unsigned NumEntries = getNumJTEntries(JT, JTI); 48525f7cfc3cccba6f569f29f79ea533bae960b93c0Evan Cheng if (Opc == ARM::t2TBB && (NumEntries & 1)) 48625f7cfc3cccba6f569f29f79ea533bae960b93c0Evan Cheng // Make sure the instruction that follows TBB is 2-byte aligned. 48725f7cfc3cccba6f569f29f79ea533bae960b93c0Evan Cheng // FIXME: Constant island pass should insert an "ALIGN" instruction 48825f7cfc3cccba6f569f29f79ea533bae960b93c0Evan Cheng // instead. 48925f7cfc3cccba6f569f29f79ea533bae960b93c0Evan Cheng ++NumEntries; 49025f7cfc3cccba6f569f29f79ea533bae960b93c0Evan Cheng return NumEntries * EntrySize + InstSize; 491334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 492334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin default: 493334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Otherwise, pseudo-instruction sizes are zero. 494334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 0; 495334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 496334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 497334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 498334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 0; // Not reached 499334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 500334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 501334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin/// Return true if the instruction is a register to register move and 502334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin/// leave the source and dest operands in the passed parameters. 503334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin/// 504334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinbool 505334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinARMBaseInstrInfo::isMoveInstr(const MachineInstr &MI, 506334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned &SrcReg, unsigned &DstReg, 507334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned& SrcSubIdx, unsigned& DstSubIdx) const { 508334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin SrcSubIdx = DstSubIdx = 0; // No sub-registers. 509334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 51068e3c6ae49ff67cba98403e43b5bd0c2499caa41Evan Cheng switch (MI.getOpcode()) { 511dced03fc846fa7cd9558ecb8e33ca98ec29bdcf0Evan Cheng default: break; 51268e3c6ae49ff67cba98403e43b5bd0c2499caa41Evan Cheng case ARM::FCPYS: 51368e3c6ae49ff67cba98403e43b5bd0c2499caa41Evan Cheng case ARM::FCPYD: 51468e3c6ae49ff67cba98403e43b5bd0c2499caa41Evan Cheng case ARM::VMOVD: 515f95215f551949d5e5adfbf4753aa833b9009b77aAnton Korobeynikov case ARM::VMOVQ: { 516334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin SrcReg = MI.getOperand(1).getReg(); 517334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin DstReg = MI.getOperand(0).getReg(); 518334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; 519334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 52068e3c6ae49ff67cba98403e43b5bd0c2499caa41Evan Cheng case ARM::MOVr: 52168e3c6ae49ff67cba98403e43b5bd0c2499caa41Evan Cheng case ARM::tMOVr: 52268e3c6ae49ff67cba98403e43b5bd0c2499caa41Evan Cheng case ARM::tMOVgpr2tgpr: 52368e3c6ae49ff67cba98403e43b5bd0c2499caa41Evan Cheng case ARM::tMOVtgpr2gpr: 52468e3c6ae49ff67cba98403e43b5bd0c2499caa41Evan Cheng case ARM::tMOVgpr2gpr: 52568e3c6ae49ff67cba98403e43b5bd0c2499caa41Evan Cheng case ARM::t2MOVr: { 526334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin assert(MI.getDesc().getNumOperands() >= 2 && 527334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI.getOperand(0).isReg() && 528334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI.getOperand(1).isReg() && 529334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin "Invalid ARM MOV instruction"); 530334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin SrcReg = MI.getOperand(1).getReg(); 531334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin DstReg = MI.getOperand(0).getReg(); 532334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; 533334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 53468e3c6ae49ff67cba98403e43b5bd0c2499caa41Evan Cheng } 535334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 536334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 537334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 538334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 539764ab52dd80310a205c9888bf166d09dab858f90Jim Grosbachunsigned 540334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinARMBaseInstrInfo::isLoadFromStackSlot(const MachineInstr *MI, 541334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin int &FrameIndex) const { 542dced03fc846fa7cd9558ecb8e33ca98ec29bdcf0Evan Cheng switch (MI->getOpcode()) { 543dced03fc846fa7cd9558ecb8e33ca98ec29bdcf0Evan Cheng default: break; 544dced03fc846fa7cd9558ecb8e33ca98ec29bdcf0Evan Cheng case ARM::LDR: 545dced03fc846fa7cd9558ecb8e33ca98ec29bdcf0Evan Cheng case ARM::t2LDRs: // FIXME: don't use t2LDRs to access frame. 546334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (MI->getOperand(1).isFI() && 547334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI->getOperand(2).isReg() && 548334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI->getOperand(3).isImm() && 549334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI->getOperand(2).getReg() == 0 && 550334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI->getOperand(3).getImm() == 0) { 551334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin FrameIndex = MI->getOperand(1).getIndex(); 552334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return MI->getOperand(0).getReg(); 553334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 554dced03fc846fa7cd9558ecb8e33ca98ec29bdcf0Evan Cheng break; 555dced03fc846fa7cd9558ecb8e33ca98ec29bdcf0Evan Cheng case ARM::t2LDRi12: 556dced03fc846fa7cd9558ecb8e33ca98ec29bdcf0Evan Cheng case ARM::tRestore: 5575ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin if (MI->getOperand(1).isFI() && 5585ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin MI->getOperand(2).isImm() && 5595ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin MI->getOperand(2).getImm() == 0) { 5605ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin FrameIndex = MI->getOperand(1).getIndex(); 5615ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin return MI->getOperand(0).getReg(); 5625ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin } 563dced03fc846fa7cd9558ecb8e33ca98ec29bdcf0Evan Cheng break; 564dced03fc846fa7cd9558ecb8e33ca98ec29bdcf0Evan Cheng case ARM::FLDD: 565dced03fc846fa7cd9558ecb8e33ca98ec29bdcf0Evan Cheng case ARM::FLDS: 566334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (MI->getOperand(1).isFI() && 567334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI->getOperand(2).isImm() && 568334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI->getOperand(2).getImm() == 0) { 569334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin FrameIndex = MI->getOperand(1).getIndex(); 570334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return MI->getOperand(0).getReg(); 571334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 572dced03fc846fa7cd9558ecb8e33ca98ec29bdcf0Evan Cheng break; 573334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 574334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 575334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 0; 576334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 577334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 578334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinunsigned 579334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinARMBaseInstrInfo::isStoreToStackSlot(const MachineInstr *MI, 580334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin int &FrameIndex) const { 581dced03fc846fa7cd9558ecb8e33ca98ec29bdcf0Evan Cheng switch (MI->getOpcode()) { 582dced03fc846fa7cd9558ecb8e33ca98ec29bdcf0Evan Cheng default: break; 583dced03fc846fa7cd9558ecb8e33ca98ec29bdcf0Evan Cheng case ARM::STR: 584dced03fc846fa7cd9558ecb8e33ca98ec29bdcf0Evan Cheng case ARM::t2STRs: // FIXME: don't use t2STRs to access frame. 585334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (MI->getOperand(1).isFI() && 586334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI->getOperand(2).isReg() && 587334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI->getOperand(3).isImm() && 588334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI->getOperand(2).getReg() == 0 && 589334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI->getOperand(3).getImm() == 0) { 590334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin FrameIndex = MI->getOperand(1).getIndex(); 591334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return MI->getOperand(0).getReg(); 592334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 593dced03fc846fa7cd9558ecb8e33ca98ec29bdcf0Evan Cheng break; 594dced03fc846fa7cd9558ecb8e33ca98ec29bdcf0Evan Cheng case ARM::t2STRi12: 595dced03fc846fa7cd9558ecb8e33ca98ec29bdcf0Evan Cheng case ARM::tSpill: 5965ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin if (MI->getOperand(1).isFI() && 5975ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin MI->getOperand(2).isImm() && 5985ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin MI->getOperand(2).getImm() == 0) { 5995ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin FrameIndex = MI->getOperand(1).getIndex(); 6005ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin return MI->getOperand(0).getReg(); 6015ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin } 602dced03fc846fa7cd9558ecb8e33ca98ec29bdcf0Evan Cheng break; 603dced03fc846fa7cd9558ecb8e33ca98ec29bdcf0Evan Cheng case ARM::FSTD: 6041d2426c4701650846922d312eb742cc55385c721Evan Cheng case ARM::FSTS: 605334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (MI->getOperand(1).isFI() && 606334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI->getOperand(2).isImm() && 607334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MI->getOperand(2).getImm() == 0) { 608334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin FrameIndex = MI->getOperand(1).getIndex(); 609334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return MI->getOperand(0).getReg(); 610334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 611dced03fc846fa7cd9558ecb8e33ca98ec29bdcf0Evan Cheng break; 612334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 613334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 614334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 0; 615334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 616334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 617334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinbool 618334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinARMBaseInstrInfo::copyRegToReg(MachineBasicBlock &MBB, 619334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineBasicBlock::iterator I, 620334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned DestReg, unsigned SrcReg, 621334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const TargetRegisterClass *DestRC, 622334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const TargetRegisterClass *SrcRC) const { 623334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin DebugLoc DL = DebugLoc::getUnknownLoc(); 624334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (I != MBB.end()) DL = I->getDebugLoc(); 625334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 626334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (DestRC != SrcRC) { 627b4db6a46e0de3283fa70ea0a7d3623f2e4e2d2a3Evan Cheng if (DestRC->getSize() != SrcRC->getSize()) 628b4db6a46e0de3283fa70ea0a7d3623f2e4e2d2a3Evan Cheng return false; 629b4db6a46e0de3283fa70ea0a7d3623f2e4e2d2a3Evan Cheng 630b4db6a46e0de3283fa70ea0a7d3623f2e4e2d2a3Evan Cheng // Allow DPR / DPR_VFP2 / DPR_8 cross-class copies. 631b4db6a46e0de3283fa70ea0a7d3623f2e4e2d2a3Evan Cheng // Allow QPR / QPR_VFP2 / QPR_8 cross-class copies. 632b4db6a46e0de3283fa70ea0a7d3623f2e4e2d2a3Evan Cheng if (DestRC->getSize() != 8 && DestRC->getSize() != 16) 6337bfdca0206f51132b26094c6f83a5ac97ee0f943David Goodwin return false; 634334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 635334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 6367bfdca0206f51132b26094c6f83a5ac97ee0f943David Goodwin if (DestRC == ARM::GPRRegisterClass) { 63708b93c6a70ae59af375f205cfcffeaa3517577abEvan Cheng AddDefaultCC(AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::MOVr), 638dd6f63209cba0003e67470938830de2cb6917336Evan Cheng DestReg).addReg(SrcReg))); 6397bfdca0206f51132b26094c6f83a5ac97ee0f943David Goodwin } else if (DestRC == ARM::SPRRegisterClass) { 640b74bb1a7a471a77e793d90de158aa4bbc67fe94dEvan Cheng AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FCPYS), DestReg) 641334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(SrcReg)); 642b4db6a46e0de3283fa70ea0a7d3623f2e4e2d2a3Evan Cheng } else if (DestRC == ARM::DPRRegisterClass) { 643b4db6a46e0de3283fa70ea0a7d3623f2e4e2d2a3Evan Cheng AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FCPYD), DestReg) 644b4db6a46e0de3283fa70ea0a7d3623f2e4e2d2a3Evan Cheng .addReg(SrcReg)); 645f95215f551949d5e5adfbf4753aa833b9009b77aAnton Korobeynikov } else if (DestRC == ARM::DPR_VFP2RegisterClass || 646f95215f551949d5e5adfbf4753aa833b9009b77aAnton Korobeynikov DestRC == ARM::DPR_8RegisterClass || 647f95215f551949d5e5adfbf4753aa833b9009b77aAnton Korobeynikov SrcRC == ARM::DPR_VFP2RegisterClass || 648f95215f551949d5e5adfbf4753aa833b9009b77aAnton Korobeynikov SrcRC == ARM::DPR_8RegisterClass) { 649f95215f551949d5e5adfbf4753aa833b9009b77aAnton Korobeynikov // Always use neon reg-reg move if source or dest is NEON-only regclass. 650f95215f551949d5e5adfbf4753aa833b9009b77aAnton Korobeynikov BuildMI(MBB, I, DL, get(ARM::VMOVD), DestReg).addReg(SrcReg); 651e56f9085b1e96f0cc302c678f1c00877676e455eAnton Korobeynikov } else if (DestRC == ARM::QPRRegisterClass || 652b4db6a46e0de3283fa70ea0a7d3623f2e4e2d2a3Evan Cheng DestRC == ARM::QPR_VFP2RegisterClass || 653b4db6a46e0de3283fa70ea0a7d3623f2e4e2d2a3Evan Cheng DestRC == ARM::QPR_8RegisterClass) { 654b74bb1a7a471a77e793d90de158aa4bbc67fe94dEvan Cheng BuildMI(MBB, I, DL, get(ARM::VMOVQ), DestReg).addReg(SrcReg); 6557bfdca0206f51132b26094c6f83a5ac97ee0f943David Goodwin } else { 656334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 6577bfdca0206f51132b26094c6f83a5ac97ee0f943David Goodwin } 658334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 659334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; 660334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 661334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 662334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinvoid ARMBaseInstrInfo:: 663334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinstoreRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 664334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned SrcReg, bool isKill, int FI, 665334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const TargetRegisterClass *RC) const { 666334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin DebugLoc DL = DebugLoc::getUnknownLoc(); 667334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (I != MBB.end()) DL = I->getDebugLoc(); 668249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MachineFunction &MF = *MBB.getParent(); 669249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MachineFrameInfo &MFI = *MF.getFrameInfo(); 670249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov 671249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MachineMemOperand *MMO = 672ff89dcb06fbd103373436e2d0ae85f252fae2254Evan Cheng MF.getMachineMemOperand(PseudoSourceValue::getFixedStack(FI), 673249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MachineMemOperand::MOStore, 0, 674249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MFI.getObjectSize(FI), 675249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MFI.getObjectAlignment(FI)); 676334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 677334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (RC == ARM::GPRRegisterClass) { 6785732ca084aaa0cd26149e50dd4b487efff37fe41Evan Cheng AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::STR)) 679334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(SrcReg, getKillRegState(isKill)) 680249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov .addFrameIndex(FI).addReg(0).addImm(0).addMemOperand(MMO)); 6816ca0b9e7220911a6d1fccf34e532e69c7e37cd2fAnton Korobeynikov } else if (RC == ARM::DPRRegisterClass || 6826ca0b9e7220911a6d1fccf34e532e69c7e37cd2fAnton Korobeynikov RC == ARM::DPR_VFP2RegisterClass || 6836ca0b9e7220911a6d1fccf34e532e69c7e37cd2fAnton Korobeynikov RC == ARM::DPR_8RegisterClass) { 684b74bb1a7a471a77e793d90de158aa4bbc67fe94dEvan Cheng AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FSTD)) 685334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(SrcReg, getKillRegState(isKill)) 686249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov .addFrameIndex(FI).addImm(0).addMemOperand(MMO)); 687baf31088f1472f48ea5ae81f0b93636cc44ca444Anton Korobeynikov } else if (RC == ARM::SPRRegisterClass) { 688b74bb1a7a471a77e793d90de158aa4bbc67fe94dEvan Cheng AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FSTS)) 689334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(SrcReg, getKillRegState(isKill)) 690249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov .addFrameIndex(FI).addImm(0).addMemOperand(MMO)); 691baf31088f1472f48ea5ae81f0b93636cc44ca444Anton Korobeynikov } else { 692e56f9085b1e96f0cc302c678f1c00877676e455eAnton Korobeynikov assert((RC == ARM::QPRRegisterClass || 693e56f9085b1e96f0cc302c678f1c00877676e455eAnton Korobeynikov RC == ARM::QPR_VFP2RegisterClass) && "Unknown regclass!"); 694baf31088f1472f48ea5ae81f0b93636cc44ca444Anton Korobeynikov // FIXME: Neon instructions should support predicates 695baf31088f1472f48ea5ae81f0b93636cc44ca444Anton Korobeynikov BuildMI(MBB, I, DL, get(ARM::VSTRQ)).addReg(SrcReg, getKillRegState(isKill)) 696249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov .addFrameIndex(FI).addImm(0).addMemOperand(MMO); 697334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 698334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 699334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 700334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinvoid ARMBaseInstrInfo:: 701334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinloadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 702334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned DestReg, int FI, 703334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const TargetRegisterClass *RC) const { 704334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin DebugLoc DL = DebugLoc::getUnknownLoc(); 705334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (I != MBB.end()) DL = I->getDebugLoc(); 706249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MachineFunction &MF = *MBB.getParent(); 707249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MachineFrameInfo &MFI = *MF.getFrameInfo(); 708249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov 709249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MachineMemOperand *MMO = 710ff89dcb06fbd103373436e2d0ae85f252fae2254Evan Cheng MF.getMachineMemOperand(PseudoSourceValue::getFixedStack(FI), 711249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MachineMemOperand::MOLoad, 0, 712249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MFI.getObjectSize(FI), 713249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov MFI.getObjectAlignment(FI)); 714334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 715334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (RC == ARM::GPRRegisterClass) { 7165732ca084aaa0cd26149e50dd4b487efff37fe41Evan Cheng AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::LDR), DestReg) 717249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov .addFrameIndex(FI).addReg(0).addImm(0).addMemOperand(MMO)); 7186ca0b9e7220911a6d1fccf34e532e69c7e37cd2fAnton Korobeynikov } else if (RC == ARM::DPRRegisterClass || 7196ca0b9e7220911a6d1fccf34e532e69c7e37cd2fAnton Korobeynikov RC == ARM::DPR_VFP2RegisterClass || 7206ca0b9e7220911a6d1fccf34e532e69c7e37cd2fAnton Korobeynikov RC == ARM::DPR_8RegisterClass) { 721b74bb1a7a471a77e793d90de158aa4bbc67fe94dEvan Cheng AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FLDD), DestReg) 722249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov .addFrameIndex(FI).addImm(0).addMemOperand(MMO)); 723baf31088f1472f48ea5ae81f0b93636cc44ca444Anton Korobeynikov } else if (RC == ARM::SPRRegisterClass) { 724b74bb1a7a471a77e793d90de158aa4bbc67fe94dEvan Cheng AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FLDS), DestReg) 725249fb339ad9d4b921a04de738b9c67d27e328bb7Anton Korobeynikov .addFrameIndex(FI).addImm(0).addMemOperand(MMO)); 726baf31088f1472f48ea5ae81f0b93636cc44ca444Anton Korobeynikov } else { 727e56f9085b1e96f0cc302c678f1c00877676e455eAnton Korobeynikov assert((RC == ARM::QPRRegisterClass || 728b4db6a46e0de3283fa70ea0a7d3623f2e4e2d2a3Evan Cheng RC == ARM::QPR_VFP2RegisterClass || 729b4db6a46e0de3283fa70ea0a7d3623f2e4e2d2a3Evan Cheng RC == ARM::QPR_8RegisterClass) && "Unknown regclass!"); 730baf31088f1472f48ea5ae81f0b93636cc44ca444Anton Korobeynikov // FIXME: Neon instructions should support predicates 7315a850beb2e3032e6ff3474ce5317f5454060328cEvan Cheng BuildMI(MBB, I, DL, get(ARM::VLDRQ), DestReg).addFrameIndex(FI).addImm(0). 7325a850beb2e3032e6ff3474ce5317f5454060328cEvan Cheng addMemOperand(MMO); 733334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 734334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 735334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 736334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinMachineInstr *ARMBaseInstrInfo:: 737334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinfoldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI, 738334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const SmallVectorImpl<unsigned> &Ops, int FI) const { 739334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (Ops.size() != 1) return NULL; 740334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 741334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned OpNum = Ops[0]; 742334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned Opc = MI->getOpcode(); 743334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineInstr *NewMI = NULL; 74419068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng if (Opc == ARM::MOVr || Opc == ARM::t2MOVr) { 745334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // If it is updating CPSR, then it cannot be folded. 74619068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng if (MI->getOperand(4).getReg() == ARM::CPSR && !MI->getOperand(4).isDead()) 74719068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng return NULL; 74819068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng unsigned Pred = MI->getOperand(2).getImm(); 74919068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng unsigned PredReg = MI->getOperand(3).getReg(); 75019068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng if (OpNum == 0) { // move -> store 75119068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng unsigned SrcReg = MI->getOperand(1).getReg(); 752ed3ad212ec34fa2866fb70f9e52ddda31032ea3bEvan Cheng unsigned SrcSubReg = MI->getOperand(1).getSubReg(); 75319068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng bool isKill = MI->getOperand(1).isKill(); 75419068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng bool isUndef = MI->getOperand(1).isUndef(); 75519068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng if (Opc == ARM::MOVr) 75619068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::STR)) 757ed3ad212ec34fa2866fb70f9e52ddda31032ea3bEvan Cheng .addReg(SrcReg, 758ed3ad212ec34fa2866fb70f9e52ddda31032ea3bEvan Cheng getKillRegState(isKill) | getUndefRegState(isUndef), 759ed3ad212ec34fa2866fb70f9e52ddda31032ea3bEvan Cheng SrcSubReg) 76019068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng .addFrameIndex(FI).addReg(0).addImm(0).addImm(Pred).addReg(PredReg); 76119068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng else // ARM::t2MOVr 76219068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::t2STRi12)) 763ed3ad212ec34fa2866fb70f9e52ddda31032ea3bEvan Cheng .addReg(SrcReg, 764ed3ad212ec34fa2866fb70f9e52ddda31032ea3bEvan Cheng getKillRegState(isKill) | getUndefRegState(isUndef), 765ed3ad212ec34fa2866fb70f9e52ddda31032ea3bEvan Cheng SrcSubReg) 76619068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg); 76719068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng } else { // move -> load 76819068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng unsigned DstReg = MI->getOperand(0).getReg(); 769ed3ad212ec34fa2866fb70f9e52ddda31032ea3bEvan Cheng unsigned DstSubReg = MI->getOperand(0).getSubReg(); 77019068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng bool isDead = MI->getOperand(0).isDead(); 77119068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng bool isUndef = MI->getOperand(0).isUndef(); 77219068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng if (Opc == ARM::MOVr) 77319068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::LDR)) 77419068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng .addReg(DstReg, 77519068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng RegState::Define | 77619068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng getDeadRegState(isDead) | 777ed3ad212ec34fa2866fb70f9e52ddda31032ea3bEvan Cheng getUndefRegState(isUndef), DstSubReg) 77819068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng .addFrameIndex(FI).addReg(0).addImm(0).addImm(Pred).addReg(PredReg); 77919068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng else // ARM::t2MOVr 78019068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::t2LDRi12)) 78119068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng .addReg(DstReg, 78219068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng RegState::Define | 78319068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng getDeadRegState(isDead) | 784ed3ad212ec34fa2866fb70f9e52ddda31032ea3bEvan Cheng getUndefRegState(isUndef), DstSubReg) 78519068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg); 786334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 78719068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng } else if (Opc == ARM::tMOVgpr2gpr || 78819068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng Opc == ARM::tMOVtgpr2gpr || 78919068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng Opc == ARM::tMOVgpr2tgpr) { 79019068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng if (OpNum == 0) { // move -> store 79119068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng unsigned SrcReg = MI->getOperand(1).getReg(); 792ed3ad212ec34fa2866fb70f9e52ddda31032ea3bEvan Cheng unsigned SrcSubReg = MI->getOperand(1).getSubReg(); 79319068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng bool isKill = MI->getOperand(1).isKill(); 79419068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng bool isUndef = MI->getOperand(1).isUndef(); 79519068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::t2STRi12)) 796ed3ad212ec34fa2866fb70f9e52ddda31032ea3bEvan Cheng .addReg(SrcReg, 797ed3ad212ec34fa2866fb70f9e52ddda31032ea3bEvan Cheng getKillRegState(isKill) | getUndefRegState(isUndef), 798ed3ad212ec34fa2866fb70f9e52ddda31032ea3bEvan Cheng SrcSubReg) 79919068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng .addFrameIndex(FI).addImm(0).addImm(ARMCC::AL).addReg(0); 80019068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng } else { // move -> load 80119068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng unsigned DstReg = MI->getOperand(0).getReg(); 802ed3ad212ec34fa2866fb70f9e52ddda31032ea3bEvan Cheng unsigned DstSubReg = MI->getOperand(0).getSubReg(); 80319068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng bool isDead = MI->getOperand(0).isDead(); 80419068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng bool isUndef = MI->getOperand(0).isUndef(); 80519068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::t2LDRi12)) 80619068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng .addReg(DstReg, 80719068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng RegState::Define | 80819068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng getDeadRegState(isDead) | 809ed3ad212ec34fa2866fb70f9e52ddda31032ea3bEvan Cheng getUndefRegState(isUndef), 810ed3ad212ec34fa2866fb70f9e52ddda31032ea3bEvan Cheng DstSubReg) 81119068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng .addFrameIndex(FI).addImm(0).addImm(ARMCC::AL).addReg(0); 81219068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng } 81319068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng } else if (Opc == ARM::FCPYS) { 814334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned Pred = MI->getOperand(2).getImm(); 815334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned PredReg = MI->getOperand(3).getReg(); 816334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (OpNum == 0) { // move -> store 817334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned SrcReg = MI->getOperand(1).getReg(); 818ed3ad212ec34fa2866fb70f9e52ddda31032ea3bEvan Cheng unsigned SrcSubReg = MI->getOperand(1).getSubReg(); 819334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool isKill = MI->getOperand(1).isKill(); 820334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool isUndef = MI->getOperand(1).isUndef(); 821b74bb1a7a471a77e793d90de158aa4bbc67fe94dEvan Cheng NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::FSTS)) 822ed3ad212ec34fa2866fb70f9e52ddda31032ea3bEvan Cheng .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef), 823ed3ad212ec34fa2866fb70f9e52ddda31032ea3bEvan Cheng SrcSubReg) 824334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addFrameIndex(FI) 825334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addImm(0).addImm(Pred).addReg(PredReg); 826334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } else { // move -> load 827334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned DstReg = MI->getOperand(0).getReg(); 828ed3ad212ec34fa2866fb70f9e52ddda31032ea3bEvan Cheng unsigned DstSubReg = MI->getOperand(0).getSubReg(); 829334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool isDead = MI->getOperand(0).isDead(); 830334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool isUndef = MI->getOperand(0).isUndef(); 831b74bb1a7a471a77e793d90de158aa4bbc67fe94dEvan Cheng NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::FLDS)) 832334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(DstReg, 833334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin RegState::Define | 834334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin getDeadRegState(isDead) | 835ed3ad212ec34fa2866fb70f9e52ddda31032ea3bEvan Cheng getUndefRegState(isUndef), 836ed3ad212ec34fa2866fb70f9e52ddda31032ea3bEvan Cheng DstSubReg) 837334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg); 838334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 839334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 840b74bb1a7a471a77e793d90de158aa4bbc67fe94dEvan Cheng else if (Opc == ARM::FCPYD) { 841334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned Pred = MI->getOperand(2).getImm(); 842334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned PredReg = MI->getOperand(3).getReg(); 843334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (OpNum == 0) { // move -> store 844334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned SrcReg = MI->getOperand(1).getReg(); 845ed3ad212ec34fa2866fb70f9e52ddda31032ea3bEvan Cheng unsigned SrcSubReg = MI->getOperand(1).getSubReg(); 846334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool isKill = MI->getOperand(1).isKill(); 847334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool isUndef = MI->getOperand(1).isUndef(); 848b74bb1a7a471a77e793d90de158aa4bbc67fe94dEvan Cheng NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::FSTD)) 849ed3ad212ec34fa2866fb70f9e52ddda31032ea3bEvan Cheng .addReg(SrcReg, 850ed3ad212ec34fa2866fb70f9e52ddda31032ea3bEvan Cheng getKillRegState(isKill) | getUndefRegState(isUndef), 851ed3ad212ec34fa2866fb70f9e52ddda31032ea3bEvan Cheng SrcSubReg) 852334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg); 853334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } else { // move -> load 854334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned DstReg = MI->getOperand(0).getReg(); 855ed3ad212ec34fa2866fb70f9e52ddda31032ea3bEvan Cheng unsigned DstSubReg = MI->getOperand(0).getSubReg(); 856334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool isDead = MI->getOperand(0).isDead(); 857334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool isUndef = MI->getOperand(0).isUndef(); 858b74bb1a7a471a77e793d90de158aa4bbc67fe94dEvan Cheng NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::FLDD)) 859334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addReg(DstReg, 860334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin RegState::Define | 861334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin getDeadRegState(isDead) | 862ed3ad212ec34fa2866fb70f9e52ddda31032ea3bEvan Cheng getUndefRegState(isUndef), 863ed3ad212ec34fa2866fb70f9e52ddda31032ea3bEvan Cheng DstSubReg) 864334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg); 865334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 866334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 867334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 868334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return NewMI; 869334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 870334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 871764ab52dd80310a205c9888bf166d09dab858f90Jim GrosbachMachineInstr* 872334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinARMBaseInstrInfo::foldMemoryOperandImpl(MachineFunction &MF, 873334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineInstr* MI, 874334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const SmallVectorImpl<unsigned> &Ops, 875334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineInstr* LoadMI) const { 8761f5c9887544ac2cb39d48e35cc6fa7a7b73ed3b0Evan Cheng // FIXME 877334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return 0; 878334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 879334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 880334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinbool 881334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid GoodwinARMBaseInstrInfo::canFoldMemoryOperand(const MachineInstr *MI, 882229464564243b24fb12cece515d727673e726994Evan Cheng const SmallVectorImpl<unsigned> &Ops) const { 883334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin if (Ops.size() != 1) return false; 884334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 885334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned Opc = MI->getOpcode(); 8865732ca084aaa0cd26149e50dd4b487efff37fe41Evan Cheng if (Opc == ARM::MOVr || Opc == ARM::t2MOVr) { 887334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // If it is updating CPSR, then it cannot be folded. 888229464564243b24fb12cece515d727673e726994Evan Cheng return MI->getOperand(4).getReg() != ARM::CPSR || 889229464564243b24fb12cece515d727673e726994Evan Cheng MI->getOperand(4).isDead(); 89019068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng } else if (Opc == ARM::tMOVgpr2gpr || 89119068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng Opc == ARM::tMOVtgpr2gpr || 89219068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng Opc == ARM::tMOVgpr2tgpr) { 89319068ba71a480d9b5032fd9f87eb412e8beb09f4Evan Cheng return true; 894b74bb1a7a471a77e793d90de158aa4bbc67fe94dEvan Cheng } else if (Opc == ARM::FCPYS || Opc == ARM::FCPYD) { 895334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return true; 896b74bb1a7a471a77e793d90de158aa4bbc67fe94dEvan Cheng } else if (Opc == ARM::VMOVD || Opc == ARM::VMOVQ) { 897334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; // FIXME 898334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 899334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 900334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return false; 901334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 9025ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng 903fdc834046efd427d474e3b899ec69354c05071e0Evan Chengvoid ARMBaseInstrInfo:: 904fdc834046efd427d474e3b899ec69354c05071e0Evan ChengreMaterialize(MachineBasicBlock &MBB, 905fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng MachineBasicBlock::iterator I, 906fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng unsigned DestReg, unsigned SubIdx, 907fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng const MachineInstr *Orig) const { 908fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng DebugLoc dl = Orig->getDebugLoc(); 909fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng unsigned Opcode = Orig->getOpcode(); 910fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng switch (Opcode) { 911fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng default: { 912fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig); 913fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng MI->getOperand(0).setReg(DestReg); 914fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng MBB.insert(I, MI); 915fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng break; 916fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng } 917fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng case ARM::tLDRpci_pic: 918fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng case ARM::t2LDRpci_pic: { 919fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng MachineFunction &MF = *MBB.getParent(); 920fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 921fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng MachineConstantPool *MCP = MF.getConstantPool(); 922fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng unsigned CPI = Orig->getOperand(1).getIndex(); 923fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPI]; 924fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng assert(MCPE.isMachineConstantPoolEntry() && 925fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng "Expecting a machine constantpool entry!"); 926fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng ARMConstantPoolValue *ACPV = 927fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal); 928fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng unsigned PCLabelId = AFI->createConstPoolEntryUId(); 929fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng ARMConstantPoolValue *NewCPV = 0; 930fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng if (ACPV->isGlobalValue()) 931fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng NewCPV = new ARMConstantPoolValue(ACPV->getGV(), PCLabelId, 932fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng ARMCP::CPValue, 4); 933fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng else if (ACPV->isExtSymbol()) 934fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng NewCPV = new ARMConstantPoolValue(MF.getFunction()->getContext(), 935fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng ACPV->getSymbol(), PCLabelId, 4); 936fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng else if (ACPV->isBlockAddress()) 937fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng NewCPV = new ARMConstantPoolValue(ACPV->getBlockAddress(), PCLabelId, 938fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng ARMCP::CPBlockAddress, 4); 939fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng else 940fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng llvm_unreachable("Unexpected ARM constantpool value type!!"); 941fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng CPI = MCP->getConstantPoolIndex(NewCPV, MCPE.getAlignment()); 942fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng MachineInstrBuilder MIB = BuildMI(MBB, I, Orig->getDebugLoc(), get(Opcode), 943fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng DestReg) 944fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng .addConstantPoolIndex(CPI).addImm(PCLabelId); 945fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng (*MIB).setMemRefs(Orig->memoperands_begin(), Orig->memoperands_end()); 946fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng break; 947fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng } 948fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng } 949fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng 950fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng MachineInstr *NewMI = prior(I); 951fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng NewMI->getOperand(0).setSubReg(SubIdx); 952fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng} 953fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng 954d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Chengbool ARMBaseInstrInfo::isIdentical(const MachineInstr *MI0, 955d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng const MachineInstr *MI1, 956d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng const MachineRegisterInfo *MRI) const { 957d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng int Opcode = MI0->getOpcode(); 958d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng if (Opcode == ARM::t2LDRpci_pic || Opcode == ARM::tLDRpci_pic) { 959d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng if (MI1->getOpcode() != Opcode) 960d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng return false; 961d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng if (MI0->getNumOperands() != MI1->getNumOperands()) 962d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng return false; 963d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng 964d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng const MachineOperand &MO0 = MI0->getOperand(1); 965d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng const MachineOperand &MO1 = MI1->getOperand(1); 966d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng if (MO0.getOffset() != MO1.getOffset()) 967d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng return false; 968d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng 969d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng const MachineFunction *MF = MI0->getParent()->getParent(); 970d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng const MachineConstantPool *MCP = MF->getConstantPool(); 971d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng int CPI0 = MO0.getIndex(); 972d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng int CPI1 = MO1.getIndex(); 973d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng const MachineConstantPoolEntry &MCPE0 = MCP->getConstants()[CPI0]; 974d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng const MachineConstantPoolEntry &MCPE1 = MCP->getConstants()[CPI1]; 975d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng ARMConstantPoolValue *ACPV0 = 976d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng static_cast<ARMConstantPoolValue*>(MCPE0.Val.MachineCPVal); 977d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng ARMConstantPoolValue *ACPV1 = 978d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng static_cast<ARMConstantPoolValue*>(MCPE1.Val.MachineCPVal); 979d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng return ACPV0->hasSameValue(ACPV1); 980d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng } 981d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng 982d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng return TargetInstrInfoImpl::isIdentical(MI0, MI1, MRI); 983d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng} 984d457e6e9a5cd975baf4d1f0578382ab8373e6153Evan Cheng 9858fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng/// getInstrPredicate - If instruction is predicated, returns its predicate 9868fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng/// condition, otherwise returns AL. It also returns the condition code 9878fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng/// register by reference. 9885adb66a646e2ec32265263739f5b01c3f50c176aEvan ChengARMCC::CondCodes 9895adb66a646e2ec32265263739f5b01c3f50c176aEvan Chengllvm::getInstrPredicate(const MachineInstr *MI, unsigned &PredReg) { 9908fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng int PIdx = MI->findFirstPredOperandIdx(); 9918fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng if (PIdx == -1) { 9928fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng PredReg = 0; 9938fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng return ARMCC::AL; 9948fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng } 9958fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng 9968fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng PredReg = MI->getOperand(PIdx+1).getReg(); 9978fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng return (ARMCC::CondCodes)MI->getOperand(PIdx).getImm(); 9988fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng} 9998fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng 10008fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng 10016495f63945e8dbde81f03a1dc2ab421993b9a495Evan Chengint llvm::getMatchingCondBranchOpcode(int Opc) { 10025ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng if (Opc == ARM::B) 10035ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng return ARM::Bcc; 10045ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng else if (Opc == ARM::tB) 10055ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng return ARM::tBcc; 10065ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng else if (Opc == ARM::t2B) 10075ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng return ARM::t2Bcc; 10085ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng 10095ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng llvm_unreachable("Unknown unconditional branch opcode!"); 10105ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng return 0; 10115ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng} 10125ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng 10136495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 10146495f63945e8dbde81f03a1dc2ab421993b9a495Evan Chengvoid llvm::emitARMRegPlusImmediate(MachineBasicBlock &MBB, 10156495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MachineBasicBlock::iterator &MBBI, DebugLoc dl, 10166495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned DestReg, unsigned BaseReg, int NumBytes, 10176495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ARMCC::CondCodes Pred, unsigned PredReg, 10186495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng const ARMBaseInstrInfo &TII) { 10196495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng bool isSub = NumBytes < 0; 10206495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (isSub) NumBytes = -NumBytes; 10216495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 10226495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng while (NumBytes) { 10236495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned RotAmt = ARM_AM::getSOImmValRotate(NumBytes); 10246495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned ThisVal = NumBytes & ARM_AM::rotr32(0xFF, RotAmt); 10256495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng assert(ThisVal && "Didn't extract field correctly"); 10266495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 10276495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // We will handle these bits from offset, clear them. 10286495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng NumBytes &= ~ThisVal; 10296495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 10306495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng assert(ARM_AM::getSOImmVal(ThisVal) != -1 && "Bit extraction didn't work?"); 10316495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 10326495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Build the new ADD / SUB. 10336495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned Opc = isSub ? ARM::SUBri : ARM::ADDri; 10346495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg) 10356495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng .addReg(BaseReg, RegState::Kill).addImm(ThisVal) 10366495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng .addImm((unsigned)Pred).addReg(PredReg).addReg(0); 10376495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng BaseReg = DestReg; 10386495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 10396495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng} 10406495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 1041cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Chengbool llvm::rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx, 1042cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng unsigned FrameReg, int &Offset, 1043cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng const ARMBaseInstrInfo &TII) { 10446495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned Opcode = MI.getOpcode(); 10456495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng const TargetInstrDesc &Desc = MI.getDesc(); 10466495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask); 10476495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng bool isSub = false; 1048764ab52dd80310a205c9888bf166d09dab858f90Jim Grosbach 10496495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Memory operands in inline assembly always use AddrMode2. 10506495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (Opcode == ARM::INLINEASM) 10516495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng AddrMode = ARMII::AddrMode2; 1052764ab52dd80310a205c9888bf166d09dab858f90Jim Grosbach 10536495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (Opcode == ARM::ADDri) { 10546495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng Offset += MI.getOperand(FrameRegIdx+1).getImm(); 10556495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (Offset == 0) { 10566495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Turn it into a move. 10576495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MI.setDesc(TII.get(ARM::MOVr)); 10586495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false); 10596495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MI.RemoveOperand(FrameRegIdx+1); 1060cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng Offset = 0; 1061cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng return true; 10626495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } else if (Offset < 0) { 10636495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng Offset = -Offset; 10646495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng isSub = true; 10656495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MI.setDesc(TII.get(ARM::SUBri)); 10666495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 10676495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 10686495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Common case: small offset, fits into instruction. 10696495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (ARM_AM::getSOImmVal(Offset) != -1) { 10706495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Replace the FrameIndex with sp / fp 10716495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false); 10726495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset); 1073cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng Offset = 0; 1074cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng return true; 10756495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 10766495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 10776495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Otherwise, pull as much of the immedidate into this ADDri/SUBri 10786495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // as possible. 10796495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned RotAmt = ARM_AM::getSOImmValRotate(Offset); 10806495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xFF, RotAmt); 10816495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 10826495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // We will handle these bits from offset, clear them. 10836495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng Offset &= ~ThisImmVal; 10846495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 10856495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Get the properly encoded SOImmVal field. 10866495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng assert(ARM_AM::getSOImmVal(ThisImmVal) != -1 && 10876495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng "Bit extraction didn't work?"); 10886495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MI.getOperand(FrameRegIdx+1).ChangeToImmediate(ThisImmVal); 10896495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } else { 10906495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned ImmIdx = 0; 10916495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng int InstrOffs = 0; 10926495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned NumBits = 0; 10936495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned Scale = 1; 10946495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng switch (AddrMode) { 10956495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng case ARMII::AddrMode2: { 10966495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ImmIdx = FrameRegIdx+2; 10976495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng InstrOffs = ARM_AM::getAM2Offset(MI.getOperand(ImmIdx).getImm()); 10986495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (ARM_AM::getAM2Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub) 10996495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng InstrOffs *= -1; 11006495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng NumBits = 12; 11016495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng break; 11026495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 11036495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng case ARMII::AddrMode3: { 11046495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ImmIdx = FrameRegIdx+2; 11056495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng InstrOffs = ARM_AM::getAM3Offset(MI.getOperand(ImmIdx).getImm()); 11066495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (ARM_AM::getAM3Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub) 11076495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng InstrOffs *= -1; 11086495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng NumBits = 8; 11096495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng break; 11106495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 1111baf31088f1472f48ea5ae81f0b93636cc44ca444Anton Korobeynikov case ARMII::AddrMode4: 1112cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng // Can't fold any offset even if it's zero. 1113cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng return false; 11146495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng case ARMII::AddrMode5: { 11156495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ImmIdx = FrameRegIdx+1; 11166495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng InstrOffs = ARM_AM::getAM5Offset(MI.getOperand(ImmIdx).getImm()); 11176495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (ARM_AM::getAM5Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub) 11186495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng InstrOffs *= -1; 11196495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng NumBits = 8; 11206495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng Scale = 4; 11216495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng break; 11226495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 11236495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng default: 11246495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng llvm_unreachable("Unsupported addressing mode!"); 11256495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng break; 11266495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 11276495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 11286495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng Offset += InstrOffs * Scale; 11296495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!"); 11306495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (Offset < 0) { 11316495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng Offset = -Offset; 11326495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng isSub = true; 11336495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 11346495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 11356495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Attempt to fold address comp. if opcode has offset bits 11366495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (NumBits > 0) { 11376495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Common case: small offset, fits into instruction. 11386495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MachineOperand &ImmOp = MI.getOperand(ImmIdx); 11396495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng int ImmedOffset = Offset / Scale; 11406495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned Mask = (1 << NumBits) - 1; 11416495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if ((unsigned)Offset <= Mask * Scale) { 11426495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Replace the FrameIndex with sp 11436495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false); 11446495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (isSub) 11456495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ImmedOffset |= 1 << NumBits; 11466495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ImmOp.ChangeToImmediate(ImmedOffset); 1147cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng Offset = 0; 1148cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng return true; 11496495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 1150764ab52dd80310a205c9888bf166d09dab858f90Jim Grosbach 11516495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Otherwise, it didn't fit. Pull in what we can to simplify the immed. 11526495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ImmedOffset = ImmedOffset & Mask; 11536495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (isSub) 11546495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ImmedOffset |= 1 << NumBits; 11556495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ImmOp.ChangeToImmediate(ImmedOffset); 11566495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng Offset &= ~(Mask*Scale); 11576495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 11586495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 11596495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 1160cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng Offset = (isSub) ? -Offset : Offset; 1161cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng return Offset == 0; 11626495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng} 1163