ARMBaseInstrInfo.cpp revision 218ee74a011c0d350099c452810da0bd57a15047
1//===-- ARMBaseInstrInfo.cpp - ARM Instruction Information ----------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the Base ARM implementation of the TargetInstrInfo class. 11// 12//===----------------------------------------------------------------------===// 13 14#include "ARMBaseInstrInfo.h" 15#include "ARM.h" 16#include "ARMBaseRegisterInfo.h" 17#include "ARMConstantPoolValue.h" 18#include "ARMHazardRecognizer.h" 19#include "ARMMachineFunctionInfo.h" 20#include "MCTargetDesc/ARMAddressingModes.h" 21#include "llvm/Constants.h" 22#include "llvm/Function.h" 23#include "llvm/GlobalValue.h" 24#include "llvm/CodeGen/LiveVariables.h" 25#include "llvm/CodeGen/MachineConstantPool.h" 26#include "llvm/CodeGen/MachineFrameInfo.h" 27#include "llvm/CodeGen/MachineInstrBuilder.h" 28#include "llvm/CodeGen/MachineJumpTableInfo.h" 29#include "llvm/CodeGen/MachineMemOperand.h" 30#include "llvm/CodeGen/MachineRegisterInfo.h" 31#include "llvm/CodeGen/SelectionDAGNodes.h" 32#include "llvm/MC/MCAsmInfo.h" 33#include "llvm/Support/BranchProbability.h" 34#include "llvm/Support/CommandLine.h" 35#include "llvm/Support/Debug.h" 36#include "llvm/Support/ErrorHandling.h" 37#include "llvm/ADT/STLExtras.h" 38 39#define GET_INSTRINFO_CTOR 40#include "ARMGenInstrInfo.inc" 41 42using namespace llvm; 43 44static cl::opt<bool> 45EnableARM3Addr("enable-arm-3-addr-conv", cl::Hidden, 46 cl::desc("Enable ARM 2-addr to 3-addr conv")); 47 48static cl::opt<bool> 49WidenVMOVS("widen-vmovs", cl::Hidden, cl::init(true), 50 cl::desc("Widen ARM vmovs to vmovd when possible")); 51 52/// ARM_MLxEntry - Record information about MLA / MLS instructions. 53struct ARM_MLxEntry { 54 uint16_t MLxOpc; // MLA / MLS opcode 55 uint16_t MulOpc; // Expanded multiplication opcode 56 uint16_t AddSubOpc; // Expanded add / sub opcode 57 bool NegAcc; // True if the acc is negated before the add / sub. 58 bool HasLane; // True if instruction has an extra "lane" operand. 59}; 60 61static const ARM_MLxEntry ARM_MLxTable[] = { 62 // MLxOpc, MulOpc, AddSubOpc, NegAcc, HasLane 63 // fp scalar ops 64 { ARM::VMLAS, ARM::VMULS, ARM::VADDS, false, false }, 65 { ARM::VMLSS, ARM::VMULS, ARM::VSUBS, false, false }, 66 { ARM::VMLAD, ARM::VMULD, ARM::VADDD, false, false }, 67 { ARM::VMLSD, ARM::VMULD, ARM::VSUBD, false, false }, 68 { ARM::VNMLAS, ARM::VNMULS, ARM::VSUBS, true, false }, 69 { ARM::VNMLSS, ARM::VMULS, ARM::VSUBS, true, false }, 70 { ARM::VNMLAD, ARM::VNMULD, ARM::VSUBD, true, false }, 71 { ARM::VNMLSD, ARM::VMULD, ARM::VSUBD, true, false }, 72 73 // fp SIMD ops 74 { ARM::VMLAfd, ARM::VMULfd, ARM::VADDfd, false, false }, 75 { ARM::VMLSfd, ARM::VMULfd, ARM::VSUBfd, false, false }, 76 { ARM::VMLAfq, ARM::VMULfq, ARM::VADDfq, false, false }, 77 { ARM::VMLSfq, ARM::VMULfq, ARM::VSUBfq, false, false }, 78 { ARM::VMLAslfd, ARM::VMULslfd, ARM::VADDfd, false, true }, 79 { ARM::VMLSslfd, ARM::VMULslfd, ARM::VSUBfd, false, true }, 80 { ARM::VMLAslfq, ARM::VMULslfq, ARM::VADDfq, false, true }, 81 { ARM::VMLSslfq, ARM::VMULslfq, ARM::VSUBfq, false, true }, 82}; 83 84ARMBaseInstrInfo::ARMBaseInstrInfo(const ARMSubtarget& STI) 85 : ARMGenInstrInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP), 86 Subtarget(STI) { 87 for (unsigned i = 0, e = array_lengthof(ARM_MLxTable); i != e; ++i) { 88 if (!MLxEntryMap.insert(std::make_pair(ARM_MLxTable[i].MLxOpc, i)).second) 89 assert(false && "Duplicated entries?"); 90 MLxHazardOpcodes.insert(ARM_MLxTable[i].AddSubOpc); 91 MLxHazardOpcodes.insert(ARM_MLxTable[i].MulOpc); 92 } 93} 94 95// Use a ScoreboardHazardRecognizer for prepass ARM scheduling. TargetInstrImpl 96// currently defaults to no prepass hazard recognizer. 97ScheduleHazardRecognizer *ARMBaseInstrInfo:: 98CreateTargetHazardRecognizer(const TargetMachine *TM, 99 const ScheduleDAG *DAG) const { 100 if (usePreRAHazardRecognizer()) { 101 const InstrItineraryData *II = TM->getInstrItineraryData(); 102 return new ScoreboardHazardRecognizer(II, DAG, "pre-RA-sched"); 103 } 104 return TargetInstrInfoImpl::CreateTargetHazardRecognizer(TM, DAG); 105} 106 107ScheduleHazardRecognizer *ARMBaseInstrInfo:: 108CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II, 109 const ScheduleDAG *DAG) const { 110 if (Subtarget.isThumb2() || Subtarget.hasVFP2()) 111 return (ScheduleHazardRecognizer *) 112 new ARMHazardRecognizer(II, *this, getRegisterInfo(), Subtarget, DAG); 113 return TargetInstrInfoImpl::CreateTargetPostRAHazardRecognizer(II, DAG); 114} 115 116MachineInstr * 117ARMBaseInstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI, 118 MachineBasicBlock::iterator &MBBI, 119 LiveVariables *LV) const { 120 // FIXME: Thumb2 support. 121 122 if (!EnableARM3Addr) 123 return NULL; 124 125 MachineInstr *MI = MBBI; 126 MachineFunction &MF = *MI->getParent()->getParent(); 127 uint64_t TSFlags = MI->getDesc().TSFlags; 128 bool isPre = false; 129 switch ((TSFlags & ARMII::IndexModeMask) >> ARMII::IndexModeShift) { 130 default: return NULL; 131 case ARMII::IndexModePre: 132 isPre = true; 133 break; 134 case ARMII::IndexModePost: 135 break; 136 } 137 138 // Try splitting an indexed load/store to an un-indexed one plus an add/sub 139 // operation. 140 unsigned MemOpc = getUnindexedOpcode(MI->getOpcode()); 141 if (MemOpc == 0) 142 return NULL; 143 144 MachineInstr *UpdateMI = NULL; 145 MachineInstr *MemMI = NULL; 146 unsigned AddrMode = (TSFlags & ARMII::AddrModeMask); 147 const MCInstrDesc &MCID = MI->getDesc(); 148 unsigned NumOps = MCID.getNumOperands(); 149 bool isLoad = !MI->mayStore(); 150 const MachineOperand &WB = isLoad ? MI->getOperand(1) : MI->getOperand(0); 151 const MachineOperand &Base = MI->getOperand(2); 152 const MachineOperand &Offset = MI->getOperand(NumOps-3); 153 unsigned WBReg = WB.getReg(); 154 unsigned BaseReg = Base.getReg(); 155 unsigned OffReg = Offset.getReg(); 156 unsigned OffImm = MI->getOperand(NumOps-2).getImm(); 157 ARMCC::CondCodes Pred = (ARMCC::CondCodes)MI->getOperand(NumOps-1).getImm(); 158 switch (AddrMode) { 159 default: llvm_unreachable("Unknown indexed op!"); 160 case ARMII::AddrMode2: { 161 bool isSub = ARM_AM::getAM2Op(OffImm) == ARM_AM::sub; 162 unsigned Amt = ARM_AM::getAM2Offset(OffImm); 163 if (OffReg == 0) { 164 if (ARM_AM::getSOImmVal(Amt) == -1) 165 // Can't encode it in a so_imm operand. This transformation will 166 // add more than 1 instruction. Abandon! 167 return NULL; 168 UpdateMI = BuildMI(MF, MI->getDebugLoc(), 169 get(isSub ? ARM::SUBri : ARM::ADDri), WBReg) 170 .addReg(BaseReg).addImm(Amt) 171 .addImm(Pred).addReg(0).addReg(0); 172 } else if (Amt != 0) { 173 ARM_AM::ShiftOpc ShOpc = ARM_AM::getAM2ShiftOpc(OffImm); 174 unsigned SOOpc = ARM_AM::getSORegOpc(ShOpc, Amt); 175 UpdateMI = BuildMI(MF, MI->getDebugLoc(), 176 get(isSub ? ARM::SUBrsi : ARM::ADDrsi), WBReg) 177 .addReg(BaseReg).addReg(OffReg).addReg(0).addImm(SOOpc) 178 .addImm(Pred).addReg(0).addReg(0); 179 } else 180 UpdateMI = BuildMI(MF, MI->getDebugLoc(), 181 get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg) 182 .addReg(BaseReg).addReg(OffReg) 183 .addImm(Pred).addReg(0).addReg(0); 184 break; 185 } 186 case ARMII::AddrMode3 : { 187 bool isSub = ARM_AM::getAM3Op(OffImm) == ARM_AM::sub; 188 unsigned Amt = ARM_AM::getAM3Offset(OffImm); 189 if (OffReg == 0) 190 // Immediate is 8-bits. It's guaranteed to fit in a so_imm operand. 191 UpdateMI = BuildMI(MF, MI->getDebugLoc(), 192 get(isSub ? ARM::SUBri : ARM::ADDri), WBReg) 193 .addReg(BaseReg).addImm(Amt) 194 .addImm(Pred).addReg(0).addReg(0); 195 else 196 UpdateMI = BuildMI(MF, MI->getDebugLoc(), 197 get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg) 198 .addReg(BaseReg).addReg(OffReg) 199 .addImm(Pred).addReg(0).addReg(0); 200 break; 201 } 202 } 203 204 std::vector<MachineInstr*> NewMIs; 205 if (isPre) { 206 if (isLoad) 207 MemMI = BuildMI(MF, MI->getDebugLoc(), 208 get(MemOpc), MI->getOperand(0).getReg()) 209 .addReg(WBReg).addImm(0).addImm(Pred); 210 else 211 MemMI = BuildMI(MF, MI->getDebugLoc(), 212 get(MemOpc)).addReg(MI->getOperand(1).getReg()) 213 .addReg(WBReg).addReg(0).addImm(0).addImm(Pred); 214 NewMIs.push_back(MemMI); 215 NewMIs.push_back(UpdateMI); 216 } else { 217 if (isLoad) 218 MemMI = BuildMI(MF, MI->getDebugLoc(), 219 get(MemOpc), MI->getOperand(0).getReg()) 220 .addReg(BaseReg).addImm(0).addImm(Pred); 221 else 222 MemMI = BuildMI(MF, MI->getDebugLoc(), 223 get(MemOpc)).addReg(MI->getOperand(1).getReg()) 224 .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred); 225 if (WB.isDead()) 226 UpdateMI->getOperand(0).setIsDead(); 227 NewMIs.push_back(UpdateMI); 228 NewMIs.push_back(MemMI); 229 } 230 231 // Transfer LiveVariables states, kill / dead info. 232 if (LV) { 233 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 234 MachineOperand &MO = MI->getOperand(i); 235 if (MO.isReg() && TargetRegisterInfo::isVirtualRegister(MO.getReg())) { 236 unsigned Reg = MO.getReg(); 237 238 LiveVariables::VarInfo &VI = LV->getVarInfo(Reg); 239 if (MO.isDef()) { 240 MachineInstr *NewMI = (Reg == WBReg) ? UpdateMI : MemMI; 241 if (MO.isDead()) 242 LV->addVirtualRegisterDead(Reg, NewMI); 243 } 244 if (MO.isUse() && MO.isKill()) { 245 for (unsigned j = 0; j < 2; ++j) { 246 // Look at the two new MI's in reverse order. 247 MachineInstr *NewMI = NewMIs[j]; 248 if (!NewMI->readsRegister(Reg)) 249 continue; 250 LV->addVirtualRegisterKilled(Reg, NewMI); 251 if (VI.removeKill(MI)) 252 VI.Kills.push_back(NewMI); 253 break; 254 } 255 } 256 } 257 } 258 } 259 260 MFI->insert(MBBI, NewMIs[1]); 261 MFI->insert(MBBI, NewMIs[0]); 262 return NewMIs[0]; 263} 264 265// Branch analysis. 266bool 267ARMBaseInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB, 268 MachineBasicBlock *&FBB, 269 SmallVectorImpl<MachineOperand> &Cond, 270 bool AllowModify) const { 271 // If the block has no terminators, it just falls into the block after it. 272 MachineBasicBlock::iterator I = MBB.end(); 273 if (I == MBB.begin()) 274 return false; 275 --I; 276 while (I->isDebugValue()) { 277 if (I == MBB.begin()) 278 return false; 279 --I; 280 } 281 if (!isUnpredicatedTerminator(I)) 282 return false; 283 284 // Get the last instruction in the block. 285 MachineInstr *LastInst = I; 286 287 // If there is only one terminator instruction, process it. 288 unsigned LastOpc = LastInst->getOpcode(); 289 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) { 290 if (isUncondBranchOpcode(LastOpc)) { 291 TBB = LastInst->getOperand(0).getMBB(); 292 return false; 293 } 294 if (isCondBranchOpcode(LastOpc)) { 295 // Block ends with fall-through condbranch. 296 TBB = LastInst->getOperand(0).getMBB(); 297 Cond.push_back(LastInst->getOperand(1)); 298 Cond.push_back(LastInst->getOperand(2)); 299 return false; 300 } 301 return true; // Can't handle indirect branch. 302 } 303 304 // Get the instruction before it if it is a terminator. 305 MachineInstr *SecondLastInst = I; 306 unsigned SecondLastOpc = SecondLastInst->getOpcode(); 307 308 // If AllowModify is true and the block ends with two or more unconditional 309 // branches, delete all but the first unconditional branch. 310 if (AllowModify && isUncondBranchOpcode(LastOpc)) { 311 while (isUncondBranchOpcode(SecondLastOpc)) { 312 LastInst->eraseFromParent(); 313 LastInst = SecondLastInst; 314 LastOpc = LastInst->getOpcode(); 315 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) { 316 // Return now the only terminator is an unconditional branch. 317 TBB = LastInst->getOperand(0).getMBB(); 318 return false; 319 } else { 320 SecondLastInst = I; 321 SecondLastOpc = SecondLastInst->getOpcode(); 322 } 323 } 324 } 325 326 // If there are three terminators, we don't know what sort of block this is. 327 if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(--I)) 328 return true; 329 330 // If the block ends with a B and a Bcc, handle it. 331 if (isCondBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) { 332 TBB = SecondLastInst->getOperand(0).getMBB(); 333 Cond.push_back(SecondLastInst->getOperand(1)); 334 Cond.push_back(SecondLastInst->getOperand(2)); 335 FBB = LastInst->getOperand(0).getMBB(); 336 return false; 337 } 338 339 // If the block ends with two unconditional branches, handle it. The second 340 // one is not executed, so remove it. 341 if (isUncondBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) { 342 TBB = SecondLastInst->getOperand(0).getMBB(); 343 I = LastInst; 344 if (AllowModify) 345 I->eraseFromParent(); 346 return false; 347 } 348 349 // ...likewise if it ends with a branch table followed by an unconditional 350 // branch. The branch folder can create these, and we must get rid of them for 351 // correctness of Thumb constant islands. 352 if ((isJumpTableBranchOpcode(SecondLastOpc) || 353 isIndirectBranchOpcode(SecondLastOpc)) && 354 isUncondBranchOpcode(LastOpc)) { 355 I = LastInst; 356 if (AllowModify) 357 I->eraseFromParent(); 358 return true; 359 } 360 361 // Otherwise, can't handle this. 362 return true; 363} 364 365 366unsigned ARMBaseInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const { 367 MachineBasicBlock::iterator I = MBB.end(); 368 if (I == MBB.begin()) return 0; 369 --I; 370 while (I->isDebugValue()) { 371 if (I == MBB.begin()) 372 return 0; 373 --I; 374 } 375 if (!isUncondBranchOpcode(I->getOpcode()) && 376 !isCondBranchOpcode(I->getOpcode())) 377 return 0; 378 379 // Remove the branch. 380 I->eraseFromParent(); 381 382 I = MBB.end(); 383 384 if (I == MBB.begin()) return 1; 385 --I; 386 if (!isCondBranchOpcode(I->getOpcode())) 387 return 1; 388 389 // Remove the branch. 390 I->eraseFromParent(); 391 return 2; 392} 393 394unsigned 395ARMBaseInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 396 MachineBasicBlock *FBB, 397 const SmallVectorImpl<MachineOperand> &Cond, 398 DebugLoc DL) const { 399 ARMFunctionInfo *AFI = MBB.getParent()->getInfo<ARMFunctionInfo>(); 400 int BOpc = !AFI->isThumbFunction() 401 ? ARM::B : (AFI->isThumb2Function() ? ARM::t2B : ARM::tB); 402 int BccOpc = !AFI->isThumbFunction() 403 ? ARM::Bcc : (AFI->isThumb2Function() ? ARM::t2Bcc : ARM::tBcc); 404 bool isThumb = AFI->isThumbFunction() || AFI->isThumb2Function(); 405 406 // Shouldn't be a fall through. 407 assert(TBB && "InsertBranch must not be told to insert a fallthrough"); 408 assert((Cond.size() == 2 || Cond.size() == 0) && 409 "ARM branch conditions have two components!"); 410 411 if (FBB == 0) { 412 if (Cond.empty()) { // Unconditional branch? 413 if (isThumb) 414 BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB).addImm(ARMCC::AL).addReg(0); 415 else 416 BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB); 417 } else 418 BuildMI(&MBB, DL, get(BccOpc)).addMBB(TBB) 419 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()); 420 return 1; 421 } 422 423 // Two-way conditional branch. 424 BuildMI(&MBB, DL, get(BccOpc)).addMBB(TBB) 425 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()); 426 if (isThumb) 427 BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB).addImm(ARMCC::AL).addReg(0); 428 else 429 BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB); 430 return 2; 431} 432 433bool ARMBaseInstrInfo:: 434ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const { 435 ARMCC::CondCodes CC = (ARMCC::CondCodes)(int)Cond[0].getImm(); 436 Cond[0].setImm(ARMCC::getOppositeCondition(CC)); 437 return false; 438} 439 440bool ARMBaseInstrInfo::isPredicated(const MachineInstr *MI) const { 441 if (MI->isBundle()) { 442 MachineBasicBlock::const_instr_iterator I = MI; 443 MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end(); 444 while (++I != E && I->isInsideBundle()) { 445 int PIdx = I->findFirstPredOperandIdx(); 446 if (PIdx != -1 && I->getOperand(PIdx).getImm() != ARMCC::AL) 447 return true; 448 } 449 return false; 450 } 451 452 int PIdx = MI->findFirstPredOperandIdx(); 453 return PIdx != -1 && MI->getOperand(PIdx).getImm() != ARMCC::AL; 454} 455 456bool ARMBaseInstrInfo:: 457PredicateInstruction(MachineInstr *MI, 458 const SmallVectorImpl<MachineOperand> &Pred) const { 459 unsigned Opc = MI->getOpcode(); 460 if (isUncondBranchOpcode(Opc)) { 461 MI->setDesc(get(getMatchingCondBranchOpcode(Opc))); 462 MI->addOperand(MachineOperand::CreateImm(Pred[0].getImm())); 463 MI->addOperand(MachineOperand::CreateReg(Pred[1].getReg(), false)); 464 return true; 465 } 466 467 int PIdx = MI->findFirstPredOperandIdx(); 468 if (PIdx != -1) { 469 MachineOperand &PMO = MI->getOperand(PIdx); 470 PMO.setImm(Pred[0].getImm()); 471 MI->getOperand(PIdx+1).setReg(Pred[1].getReg()); 472 return true; 473 } 474 return false; 475} 476 477bool ARMBaseInstrInfo:: 478SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1, 479 const SmallVectorImpl<MachineOperand> &Pred2) const { 480 if (Pred1.size() > 2 || Pred2.size() > 2) 481 return false; 482 483 ARMCC::CondCodes CC1 = (ARMCC::CondCodes)Pred1[0].getImm(); 484 ARMCC::CondCodes CC2 = (ARMCC::CondCodes)Pred2[0].getImm(); 485 if (CC1 == CC2) 486 return true; 487 488 switch (CC1) { 489 default: 490 return false; 491 case ARMCC::AL: 492 return true; 493 case ARMCC::HS: 494 return CC2 == ARMCC::HI; 495 case ARMCC::LS: 496 return CC2 == ARMCC::LO || CC2 == ARMCC::EQ; 497 case ARMCC::GE: 498 return CC2 == ARMCC::GT; 499 case ARMCC::LE: 500 return CC2 == ARMCC::LT; 501 } 502} 503 504bool ARMBaseInstrInfo::DefinesPredicate(MachineInstr *MI, 505 std::vector<MachineOperand> &Pred) const { 506 bool Found = false; 507 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 508 const MachineOperand &MO = MI->getOperand(i); 509 if ((MO.isRegMask() && MO.clobbersPhysReg(ARM::CPSR)) || 510 (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR)) { 511 Pred.push_back(MO); 512 Found = true; 513 } 514 } 515 516 return Found; 517} 518 519/// isPredicable - Return true if the specified instruction can be predicated. 520/// By default, this returns true for every instruction with a 521/// PredicateOperand. 522bool ARMBaseInstrInfo::isPredicable(MachineInstr *MI) const { 523 if (!MI->isPredicable()) 524 return false; 525 526 if ((MI->getDesc().TSFlags & ARMII::DomainMask) == ARMII::DomainNEON) { 527 ARMFunctionInfo *AFI = 528 MI->getParent()->getParent()->getInfo<ARMFunctionInfo>(); 529 return AFI->isThumb2Function(); 530 } 531 return true; 532} 533 534/// FIXME: Works around a gcc miscompilation with -fstrict-aliasing. 535LLVM_ATTRIBUTE_NOINLINE 536static unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT, 537 unsigned JTI); 538static unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT, 539 unsigned JTI) { 540 assert(JTI < JT.size()); 541 return JT[JTI].MBBs.size(); 542} 543 544/// GetInstSize - Return the size of the specified MachineInstr. 545/// 546unsigned ARMBaseInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const { 547 const MachineBasicBlock &MBB = *MI->getParent(); 548 const MachineFunction *MF = MBB.getParent(); 549 const MCAsmInfo *MAI = MF->getTarget().getMCAsmInfo(); 550 551 const MCInstrDesc &MCID = MI->getDesc(); 552 if (MCID.getSize()) 553 return MCID.getSize(); 554 555 // If this machine instr is an inline asm, measure it. 556 if (MI->getOpcode() == ARM::INLINEASM) 557 return getInlineAsmLength(MI->getOperand(0).getSymbolName(), *MAI); 558 if (MI->isLabel()) 559 return 0; 560 unsigned Opc = MI->getOpcode(); 561 switch (Opc) { 562 case TargetOpcode::IMPLICIT_DEF: 563 case TargetOpcode::KILL: 564 case TargetOpcode::PROLOG_LABEL: 565 case TargetOpcode::EH_LABEL: 566 case TargetOpcode::DBG_VALUE: 567 return 0; 568 case TargetOpcode::BUNDLE: 569 return getInstBundleLength(MI); 570 case ARM::MOVi16_ga_pcrel: 571 case ARM::MOVTi16_ga_pcrel: 572 case ARM::t2MOVi16_ga_pcrel: 573 case ARM::t2MOVTi16_ga_pcrel: 574 return 4; 575 case ARM::MOVi32imm: 576 case ARM::t2MOVi32imm: 577 return 8; 578 case ARM::CONSTPOOL_ENTRY: 579 // If this machine instr is a constant pool entry, its size is recorded as 580 // operand #2. 581 return MI->getOperand(2).getImm(); 582 case ARM::Int_eh_sjlj_longjmp: 583 return 16; 584 case ARM::tInt_eh_sjlj_longjmp: 585 return 10; 586 case ARM::Int_eh_sjlj_setjmp: 587 case ARM::Int_eh_sjlj_setjmp_nofp: 588 return 20; 589 case ARM::tInt_eh_sjlj_setjmp: 590 case ARM::t2Int_eh_sjlj_setjmp: 591 case ARM::t2Int_eh_sjlj_setjmp_nofp: 592 return 12; 593 case ARM::BR_JTr: 594 case ARM::BR_JTm: 595 case ARM::BR_JTadd: 596 case ARM::tBR_JTr: 597 case ARM::t2BR_JT: 598 case ARM::t2TBB_JT: 599 case ARM::t2TBH_JT: { 600 // These are jumptable branches, i.e. a branch followed by an inlined 601 // jumptable. The size is 4 + 4 * number of entries. For TBB, each 602 // entry is one byte; TBH two byte each. 603 unsigned EntrySize = (Opc == ARM::t2TBB_JT) 604 ? 1 : ((Opc == ARM::t2TBH_JT) ? 2 : 4); 605 unsigned NumOps = MCID.getNumOperands(); 606 MachineOperand JTOP = 607 MI->getOperand(NumOps - (MI->isPredicable() ? 3 : 2)); 608 unsigned JTI = JTOP.getIndex(); 609 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo(); 610 assert(MJTI != 0); 611 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables(); 612 assert(JTI < JT.size()); 613 // Thumb instructions are 2 byte aligned, but JT entries are 4 byte 614 // 4 aligned. The assembler / linker may add 2 byte padding just before 615 // the JT entries. The size does not include this padding; the 616 // constant islands pass does separate bookkeeping for it. 617 // FIXME: If we know the size of the function is less than (1 << 16) *2 618 // bytes, we can use 16-bit entries instead. Then there won't be an 619 // alignment issue. 620 unsigned InstSize = (Opc == ARM::tBR_JTr || Opc == ARM::t2BR_JT) ? 2 : 4; 621 unsigned NumEntries = getNumJTEntries(JT, JTI); 622 if (Opc == ARM::t2TBB_JT && (NumEntries & 1)) 623 // Make sure the instruction that follows TBB is 2-byte aligned. 624 // FIXME: Constant island pass should insert an "ALIGN" instruction 625 // instead. 626 ++NumEntries; 627 return NumEntries * EntrySize + InstSize; 628 } 629 default: 630 // Otherwise, pseudo-instruction sizes are zero. 631 return 0; 632 } 633} 634 635unsigned ARMBaseInstrInfo::getInstBundleLength(const MachineInstr *MI) const { 636 unsigned Size = 0; 637 MachineBasicBlock::const_instr_iterator I = MI; 638 MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end(); 639 while (++I != E && I->isInsideBundle()) { 640 assert(!I->isBundle() && "No nested bundle!"); 641 Size += GetInstSizeInBytes(&*I); 642 } 643 return Size; 644} 645 646void ARMBaseInstrInfo::copyPhysReg(MachineBasicBlock &MBB, 647 MachineBasicBlock::iterator I, DebugLoc DL, 648 unsigned DestReg, unsigned SrcReg, 649 bool KillSrc) const { 650 bool GPRDest = ARM::GPRRegClass.contains(DestReg); 651 bool GPRSrc = ARM::GPRRegClass.contains(SrcReg); 652 653 if (GPRDest && GPRSrc) { 654 AddDefaultCC(AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::MOVr), DestReg) 655 .addReg(SrcReg, getKillRegState(KillSrc)))); 656 return; 657 } 658 659 bool SPRDest = ARM::SPRRegClass.contains(DestReg); 660 bool SPRSrc = ARM::SPRRegClass.contains(SrcReg); 661 662 unsigned Opc = 0; 663 if (SPRDest && SPRSrc) 664 Opc = ARM::VMOVS; 665 else if (GPRDest && SPRSrc) 666 Opc = ARM::VMOVRS; 667 else if (SPRDest && GPRSrc) 668 Opc = ARM::VMOVSR; 669 else if (ARM::DPRRegClass.contains(DestReg, SrcReg)) 670 Opc = ARM::VMOVD; 671 else if (ARM::QPRRegClass.contains(DestReg, SrcReg)) 672 Opc = ARM::VORRq; 673 674 if (Opc) { 675 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc), DestReg); 676 MIB.addReg(SrcReg, getKillRegState(KillSrc)); 677 if (Opc == ARM::VORRq) 678 MIB.addReg(SrcReg, getKillRegState(KillSrc)); 679 AddDefaultPred(MIB); 680 return; 681 } 682 683 // Handle register classes that require multiple instructions. 684 unsigned BeginIdx = 0; 685 unsigned SubRegs = 0; 686 unsigned Spacing = 1; 687 688 // Use VORRq when possible. 689 if (ARM::QQPRRegClass.contains(DestReg, SrcReg)) 690 Opc = ARM::VORRq, BeginIdx = ARM::qsub_0, SubRegs = 2; 691 else if (ARM::QQQQPRRegClass.contains(DestReg, SrcReg)) 692 Opc = ARM::VORRq, BeginIdx = ARM::qsub_0, SubRegs = 4; 693 // Fall back to VMOVD. 694 else if (ARM::DPairRegClass.contains(DestReg, SrcReg)) 695 Opc = ARM::VMOVD, BeginIdx = ARM::dsub_0, SubRegs = 2; 696 else if (ARM::DTripleRegClass.contains(DestReg, SrcReg)) 697 Opc = ARM::VMOVD, BeginIdx = ARM::dsub_0, SubRegs = 3; 698 else if (ARM::DQuadRegClass.contains(DestReg, SrcReg)) 699 Opc = ARM::VMOVD, BeginIdx = ARM::dsub_0, SubRegs = 4; 700 701 else if (ARM::DPairSpcRegClass.contains(DestReg, SrcReg)) 702 Opc = ARM::VMOVD, BeginIdx = ARM::dsub_0, SubRegs = 2, Spacing = 2; 703 else if (ARM::DTripleSpcRegClass.contains(DestReg, SrcReg)) 704 Opc = ARM::VMOVD, BeginIdx = ARM::dsub_0, SubRegs = 3, Spacing = 2; 705 else if (ARM::DQuadSpcRegClass.contains(DestReg, SrcReg)) 706 Opc = ARM::VMOVD, BeginIdx = ARM::dsub_0, SubRegs = 4, Spacing = 2; 707 708 if (Opc) { 709 const TargetRegisterInfo *TRI = &getRegisterInfo(); 710 MachineInstrBuilder Mov; 711 for (unsigned i = 0; i != SubRegs; ++i) { 712 unsigned Dst = TRI->getSubReg(DestReg, BeginIdx + i*Spacing); 713 unsigned Src = TRI->getSubReg(SrcReg, BeginIdx + i*Spacing); 714 assert(Dst && Src && "Bad sub-register"); 715 Mov = AddDefaultPred(BuildMI(MBB, I, I->getDebugLoc(), get(Opc), Dst) 716 .addReg(Src)); 717 // VORR takes two source operands. 718 if (Opc == ARM::VORRq) 719 Mov.addReg(Src); 720 } 721 // Add implicit super-register defs and kills to the last instruction. 722 Mov->addRegisterDefined(DestReg, TRI); 723 if (KillSrc) 724 Mov->addRegisterKilled(SrcReg, TRI); 725 return; 726 } 727 728 llvm_unreachable("Impossible reg-to-reg copy"); 729} 730 731static const 732MachineInstrBuilder &AddDReg(MachineInstrBuilder &MIB, 733 unsigned Reg, unsigned SubIdx, unsigned State, 734 const TargetRegisterInfo *TRI) { 735 if (!SubIdx) 736 return MIB.addReg(Reg, State); 737 738 if (TargetRegisterInfo::isPhysicalRegister(Reg)) 739 return MIB.addReg(TRI->getSubReg(Reg, SubIdx), State); 740 return MIB.addReg(Reg, State, SubIdx); 741} 742 743void ARMBaseInstrInfo:: 744storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 745 unsigned SrcReg, bool isKill, int FI, 746 const TargetRegisterClass *RC, 747 const TargetRegisterInfo *TRI) const { 748 DebugLoc DL; 749 if (I != MBB.end()) DL = I->getDebugLoc(); 750 MachineFunction &MF = *MBB.getParent(); 751 MachineFrameInfo &MFI = *MF.getFrameInfo(); 752 unsigned Align = MFI.getObjectAlignment(FI); 753 754 MachineMemOperand *MMO = 755 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FI), 756 MachineMemOperand::MOStore, 757 MFI.getObjectSize(FI), 758 Align); 759 760 switch (RC->getSize()) { 761 case 4: 762 if (ARM::GPRRegClass.hasSubClassEq(RC)) { 763 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::STRi12)) 764 .addReg(SrcReg, getKillRegState(isKill)) 765 .addFrameIndex(FI).addImm(0).addMemOperand(MMO)); 766 } else if (ARM::SPRRegClass.hasSubClassEq(RC)) { 767 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTRS)) 768 .addReg(SrcReg, getKillRegState(isKill)) 769 .addFrameIndex(FI).addImm(0).addMemOperand(MMO)); 770 } else 771 llvm_unreachable("Unknown reg class!"); 772 break; 773 case 8: 774 if (ARM::DPRRegClass.hasSubClassEq(RC)) { 775 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTRD)) 776 .addReg(SrcReg, getKillRegState(isKill)) 777 .addFrameIndex(FI).addImm(0).addMemOperand(MMO)); 778 } else 779 llvm_unreachable("Unknown reg class!"); 780 break; 781 case 16: 782 if (ARM::DPairRegClass.hasSubClassEq(RC)) { 783 // Use aligned spills if the stack can be realigned. 784 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) { 785 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1q64)) 786 .addFrameIndex(FI).addImm(16) 787 .addReg(SrcReg, getKillRegState(isKill)) 788 .addMemOperand(MMO)); 789 } else { 790 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMQIA)) 791 .addReg(SrcReg, getKillRegState(isKill)) 792 .addFrameIndex(FI) 793 .addMemOperand(MMO)); 794 } 795 } else 796 llvm_unreachable("Unknown reg class!"); 797 break; 798 case 32: 799 if (ARM::QQPRRegClass.hasSubClassEq(RC)) { 800 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) { 801 // FIXME: It's possible to only store part of the QQ register if the 802 // spilled def has a sub-register index. 803 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1d64QPseudo)) 804 .addFrameIndex(FI).addImm(16) 805 .addReg(SrcReg, getKillRegState(isKill)) 806 .addMemOperand(MMO)); 807 } else { 808 MachineInstrBuilder MIB = 809 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMDIA)) 810 .addFrameIndex(FI)) 811 .addMemOperand(MMO); 812 MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI); 813 MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI); 814 MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI); 815 AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI); 816 } 817 } else 818 llvm_unreachable("Unknown reg class!"); 819 break; 820 case 64: 821 if (ARM::QQQQPRRegClass.hasSubClassEq(RC)) { 822 MachineInstrBuilder MIB = 823 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMDIA)) 824 .addFrameIndex(FI)) 825 .addMemOperand(MMO); 826 MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI); 827 MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI); 828 MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI); 829 MIB = AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI); 830 MIB = AddDReg(MIB, SrcReg, ARM::dsub_4, 0, TRI); 831 MIB = AddDReg(MIB, SrcReg, ARM::dsub_5, 0, TRI); 832 MIB = AddDReg(MIB, SrcReg, ARM::dsub_6, 0, TRI); 833 AddDReg(MIB, SrcReg, ARM::dsub_7, 0, TRI); 834 } else 835 llvm_unreachable("Unknown reg class!"); 836 break; 837 default: 838 llvm_unreachable("Unknown reg class!"); 839 } 840} 841 842unsigned 843ARMBaseInstrInfo::isStoreToStackSlot(const MachineInstr *MI, 844 int &FrameIndex) const { 845 switch (MI->getOpcode()) { 846 default: break; 847 case ARM::STRrs: 848 case ARM::t2STRs: // FIXME: don't use t2STRs to access frame. 849 if (MI->getOperand(1).isFI() && 850 MI->getOperand(2).isReg() && 851 MI->getOperand(3).isImm() && 852 MI->getOperand(2).getReg() == 0 && 853 MI->getOperand(3).getImm() == 0) { 854 FrameIndex = MI->getOperand(1).getIndex(); 855 return MI->getOperand(0).getReg(); 856 } 857 break; 858 case ARM::STRi12: 859 case ARM::t2STRi12: 860 case ARM::tSTRspi: 861 case ARM::VSTRD: 862 case ARM::VSTRS: 863 if (MI->getOperand(1).isFI() && 864 MI->getOperand(2).isImm() && 865 MI->getOperand(2).getImm() == 0) { 866 FrameIndex = MI->getOperand(1).getIndex(); 867 return MI->getOperand(0).getReg(); 868 } 869 break; 870 case ARM::VST1q64: 871 if (MI->getOperand(0).isFI() && 872 MI->getOperand(2).getSubReg() == 0) { 873 FrameIndex = MI->getOperand(0).getIndex(); 874 return MI->getOperand(2).getReg(); 875 } 876 break; 877 case ARM::VSTMQIA: 878 if (MI->getOperand(1).isFI() && 879 MI->getOperand(0).getSubReg() == 0) { 880 FrameIndex = MI->getOperand(1).getIndex(); 881 return MI->getOperand(0).getReg(); 882 } 883 break; 884 } 885 886 return 0; 887} 888 889unsigned ARMBaseInstrInfo::isStoreToStackSlotPostFE(const MachineInstr *MI, 890 int &FrameIndex) const { 891 const MachineMemOperand *Dummy; 892 return MI->mayStore() && hasStoreToStackSlot(MI, Dummy, FrameIndex); 893} 894 895void ARMBaseInstrInfo:: 896loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 897 unsigned DestReg, int FI, 898 const TargetRegisterClass *RC, 899 const TargetRegisterInfo *TRI) const { 900 DebugLoc DL; 901 if (I != MBB.end()) DL = I->getDebugLoc(); 902 MachineFunction &MF = *MBB.getParent(); 903 MachineFrameInfo &MFI = *MF.getFrameInfo(); 904 unsigned Align = MFI.getObjectAlignment(FI); 905 MachineMemOperand *MMO = 906 MF.getMachineMemOperand( 907 MachinePointerInfo::getFixedStack(FI), 908 MachineMemOperand::MOLoad, 909 MFI.getObjectSize(FI), 910 Align); 911 912 switch (RC->getSize()) { 913 case 4: 914 if (ARM::GPRRegClass.hasSubClassEq(RC)) { 915 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::LDRi12), DestReg) 916 .addFrameIndex(FI).addImm(0).addMemOperand(MMO)); 917 918 } else if (ARM::SPRRegClass.hasSubClassEq(RC)) { 919 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRS), DestReg) 920 .addFrameIndex(FI).addImm(0).addMemOperand(MMO)); 921 } else 922 llvm_unreachable("Unknown reg class!"); 923 break; 924 case 8: 925 if (ARM::DPRRegClass.hasSubClassEq(RC)) { 926 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRD), DestReg) 927 .addFrameIndex(FI).addImm(0).addMemOperand(MMO)); 928 } else 929 llvm_unreachable("Unknown reg class!"); 930 break; 931 case 16: 932 if (ARM::DPairRegClass.hasSubClassEq(RC)) { 933 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) { 934 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1q64), DestReg) 935 .addFrameIndex(FI).addImm(16) 936 .addMemOperand(MMO)); 937 } else { 938 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMQIA), DestReg) 939 .addFrameIndex(FI) 940 .addMemOperand(MMO)); 941 } 942 } else 943 llvm_unreachable("Unknown reg class!"); 944 break; 945 case 32: 946 if (ARM::QQPRRegClass.hasSubClassEq(RC)) { 947 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) { 948 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1d64QPseudo), DestReg) 949 .addFrameIndex(FI).addImm(16) 950 .addMemOperand(MMO)); 951 } else { 952 MachineInstrBuilder MIB = 953 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMDIA)) 954 .addFrameIndex(FI)) 955 .addMemOperand(MMO); 956 MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI); 957 MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI); 958 MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI); 959 MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::DefineNoRead, TRI); 960 if (TargetRegisterInfo::isPhysicalRegister(DestReg)) 961 MIB.addReg(DestReg, RegState::ImplicitDefine); 962 } 963 } else 964 llvm_unreachable("Unknown reg class!"); 965 break; 966 case 64: 967 if (ARM::QQQQPRRegClass.hasSubClassEq(RC)) { 968 MachineInstrBuilder MIB = 969 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMDIA)) 970 .addFrameIndex(FI)) 971 .addMemOperand(MMO); 972 MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI); 973 MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI); 974 MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI); 975 MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::DefineNoRead, TRI); 976 MIB = AddDReg(MIB, DestReg, ARM::dsub_4, RegState::DefineNoRead, TRI); 977 MIB = AddDReg(MIB, DestReg, ARM::dsub_5, RegState::DefineNoRead, TRI); 978 MIB = AddDReg(MIB, DestReg, ARM::dsub_6, RegState::DefineNoRead, TRI); 979 MIB = AddDReg(MIB, DestReg, ARM::dsub_7, RegState::DefineNoRead, TRI); 980 if (TargetRegisterInfo::isPhysicalRegister(DestReg)) 981 MIB.addReg(DestReg, RegState::ImplicitDefine); 982 } else 983 llvm_unreachable("Unknown reg class!"); 984 break; 985 default: 986 llvm_unreachable("Unknown regclass!"); 987 } 988} 989 990unsigned 991ARMBaseInstrInfo::isLoadFromStackSlot(const MachineInstr *MI, 992 int &FrameIndex) const { 993 switch (MI->getOpcode()) { 994 default: break; 995 case ARM::LDRrs: 996 case ARM::t2LDRs: // FIXME: don't use t2LDRs to access frame. 997 if (MI->getOperand(1).isFI() && 998 MI->getOperand(2).isReg() && 999 MI->getOperand(3).isImm() && 1000 MI->getOperand(2).getReg() == 0 && 1001 MI->getOperand(3).getImm() == 0) { 1002 FrameIndex = MI->getOperand(1).getIndex(); 1003 return MI->getOperand(0).getReg(); 1004 } 1005 break; 1006 case ARM::LDRi12: 1007 case ARM::t2LDRi12: 1008 case ARM::tLDRspi: 1009 case ARM::VLDRD: 1010 case ARM::VLDRS: 1011 if (MI->getOperand(1).isFI() && 1012 MI->getOperand(2).isImm() && 1013 MI->getOperand(2).getImm() == 0) { 1014 FrameIndex = MI->getOperand(1).getIndex(); 1015 return MI->getOperand(0).getReg(); 1016 } 1017 break; 1018 case ARM::VLD1q64: 1019 if (MI->getOperand(1).isFI() && 1020 MI->getOperand(0).getSubReg() == 0) { 1021 FrameIndex = MI->getOperand(1).getIndex(); 1022 return MI->getOperand(0).getReg(); 1023 } 1024 break; 1025 case ARM::VLDMQIA: 1026 if (MI->getOperand(1).isFI() && 1027 MI->getOperand(0).getSubReg() == 0) { 1028 FrameIndex = MI->getOperand(1).getIndex(); 1029 return MI->getOperand(0).getReg(); 1030 } 1031 break; 1032 } 1033 1034 return 0; 1035} 1036 1037unsigned ARMBaseInstrInfo::isLoadFromStackSlotPostFE(const MachineInstr *MI, 1038 int &FrameIndex) const { 1039 const MachineMemOperand *Dummy; 1040 return MI->mayLoad() && hasLoadFromStackSlot(MI, Dummy, FrameIndex); 1041} 1042 1043bool ARMBaseInstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const{ 1044 // This hook gets to expand COPY instructions before they become 1045 // copyPhysReg() calls. Look for VMOVS instructions that can legally be 1046 // widened to VMOVD. We prefer the VMOVD when possible because it may be 1047 // changed into a VORR that can go down the NEON pipeline. 1048 if (!WidenVMOVS || !MI->isCopy()) 1049 return false; 1050 1051 // Look for a copy between even S-registers. That is where we keep floats 1052 // when using NEON v2f32 instructions for f32 arithmetic. 1053 unsigned DstRegS = MI->getOperand(0).getReg(); 1054 unsigned SrcRegS = MI->getOperand(1).getReg(); 1055 if (!ARM::SPRRegClass.contains(DstRegS, SrcRegS)) 1056 return false; 1057 1058 const TargetRegisterInfo *TRI = &getRegisterInfo(); 1059 unsigned DstRegD = TRI->getMatchingSuperReg(DstRegS, ARM::ssub_0, 1060 &ARM::DPRRegClass); 1061 unsigned SrcRegD = TRI->getMatchingSuperReg(SrcRegS, ARM::ssub_0, 1062 &ARM::DPRRegClass); 1063 if (!DstRegD || !SrcRegD) 1064 return false; 1065 1066 // We want to widen this into a DstRegD = VMOVD SrcRegD copy. This is only 1067 // legal if the COPY already defines the full DstRegD, and it isn't a 1068 // sub-register insertion. 1069 if (!MI->definesRegister(DstRegD, TRI) || MI->readsRegister(DstRegD, TRI)) 1070 return false; 1071 1072 // A dead copy shouldn't show up here, but reject it just in case. 1073 if (MI->getOperand(0).isDead()) 1074 return false; 1075 1076 // All clear, widen the COPY. 1077 DEBUG(dbgs() << "widening: " << *MI); 1078 1079 // Get rid of the old <imp-def> of DstRegD. Leave it if it defines a Q-reg 1080 // or some other super-register. 1081 int ImpDefIdx = MI->findRegisterDefOperandIdx(DstRegD); 1082 if (ImpDefIdx != -1) 1083 MI->RemoveOperand(ImpDefIdx); 1084 1085 // Change the opcode and operands. 1086 MI->setDesc(get(ARM::VMOVD)); 1087 MI->getOperand(0).setReg(DstRegD); 1088 MI->getOperand(1).setReg(SrcRegD); 1089 AddDefaultPred(MachineInstrBuilder(MI)); 1090 1091 // We are now reading SrcRegD instead of SrcRegS. This may upset the 1092 // register scavenger and machine verifier, so we need to indicate that we 1093 // are reading an undefined value from SrcRegD, but a proper value from 1094 // SrcRegS. 1095 MI->getOperand(1).setIsUndef(); 1096 MachineInstrBuilder(MI).addReg(SrcRegS, RegState::Implicit); 1097 1098 // SrcRegD may actually contain an unrelated value in the ssub_1 1099 // sub-register. Don't kill it. Only kill the ssub_0 sub-register. 1100 if (MI->getOperand(1).isKill()) { 1101 MI->getOperand(1).setIsKill(false); 1102 MI->addRegisterKilled(SrcRegS, TRI, true); 1103 } 1104 1105 DEBUG(dbgs() << "replaced by: " << *MI); 1106 return true; 1107} 1108 1109MachineInstr* 1110ARMBaseInstrInfo::emitFrameIndexDebugValue(MachineFunction &MF, 1111 int FrameIx, uint64_t Offset, 1112 const MDNode *MDPtr, 1113 DebugLoc DL) const { 1114 MachineInstrBuilder MIB = BuildMI(MF, DL, get(ARM::DBG_VALUE)) 1115 .addFrameIndex(FrameIx).addImm(0).addImm(Offset).addMetadata(MDPtr); 1116 return &*MIB; 1117} 1118 1119/// Create a copy of a const pool value. Update CPI to the new index and return 1120/// the label UID. 1121static unsigned duplicateCPV(MachineFunction &MF, unsigned &CPI) { 1122 MachineConstantPool *MCP = MF.getConstantPool(); 1123 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 1124 1125 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPI]; 1126 assert(MCPE.isMachineConstantPoolEntry() && 1127 "Expecting a machine constantpool entry!"); 1128 ARMConstantPoolValue *ACPV = 1129 static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal); 1130 1131 unsigned PCLabelId = AFI->createPICLabelUId(); 1132 ARMConstantPoolValue *NewCPV = 0; 1133 // FIXME: The below assumes PIC relocation model and that the function 1134 // is Thumb mode (t1 or t2). PCAdjustment would be 8 for ARM mode PIC, and 1135 // zero for non-PIC in ARM or Thumb. The callers are all of thumb LDR 1136 // instructions, so that's probably OK, but is PIC always correct when 1137 // we get here? 1138 if (ACPV->isGlobalValue()) 1139 NewCPV = ARMConstantPoolConstant:: 1140 Create(cast<ARMConstantPoolConstant>(ACPV)->getGV(), PCLabelId, 1141 ARMCP::CPValue, 4); 1142 else if (ACPV->isExtSymbol()) 1143 NewCPV = ARMConstantPoolSymbol:: 1144 Create(MF.getFunction()->getContext(), 1145 cast<ARMConstantPoolSymbol>(ACPV)->getSymbol(), PCLabelId, 4); 1146 else if (ACPV->isBlockAddress()) 1147 NewCPV = ARMConstantPoolConstant:: 1148 Create(cast<ARMConstantPoolConstant>(ACPV)->getBlockAddress(), PCLabelId, 1149 ARMCP::CPBlockAddress, 4); 1150 else if (ACPV->isLSDA()) 1151 NewCPV = ARMConstantPoolConstant::Create(MF.getFunction(), PCLabelId, 1152 ARMCP::CPLSDA, 4); 1153 else if (ACPV->isMachineBasicBlock()) 1154 NewCPV = ARMConstantPoolMBB:: 1155 Create(MF.getFunction()->getContext(), 1156 cast<ARMConstantPoolMBB>(ACPV)->getMBB(), PCLabelId, 4); 1157 else 1158 llvm_unreachable("Unexpected ARM constantpool value type!!"); 1159 CPI = MCP->getConstantPoolIndex(NewCPV, MCPE.getAlignment()); 1160 return PCLabelId; 1161} 1162 1163void ARMBaseInstrInfo:: 1164reMaterialize(MachineBasicBlock &MBB, 1165 MachineBasicBlock::iterator I, 1166 unsigned DestReg, unsigned SubIdx, 1167 const MachineInstr *Orig, 1168 const TargetRegisterInfo &TRI) const { 1169 unsigned Opcode = Orig->getOpcode(); 1170 switch (Opcode) { 1171 default: { 1172 MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig); 1173 MI->substituteRegister(Orig->getOperand(0).getReg(), DestReg, SubIdx, TRI); 1174 MBB.insert(I, MI); 1175 break; 1176 } 1177 case ARM::tLDRpci_pic: 1178 case ARM::t2LDRpci_pic: { 1179 MachineFunction &MF = *MBB.getParent(); 1180 unsigned CPI = Orig->getOperand(1).getIndex(); 1181 unsigned PCLabelId = duplicateCPV(MF, CPI); 1182 MachineInstrBuilder MIB = BuildMI(MBB, I, Orig->getDebugLoc(), get(Opcode), 1183 DestReg) 1184 .addConstantPoolIndex(CPI).addImm(PCLabelId); 1185 MIB->setMemRefs(Orig->memoperands_begin(), Orig->memoperands_end()); 1186 break; 1187 } 1188 } 1189} 1190 1191MachineInstr * 1192ARMBaseInstrInfo::duplicate(MachineInstr *Orig, MachineFunction &MF) const { 1193 MachineInstr *MI = TargetInstrInfoImpl::duplicate(Orig, MF); 1194 switch(Orig->getOpcode()) { 1195 case ARM::tLDRpci_pic: 1196 case ARM::t2LDRpci_pic: { 1197 unsigned CPI = Orig->getOperand(1).getIndex(); 1198 unsigned PCLabelId = duplicateCPV(MF, CPI); 1199 Orig->getOperand(1).setIndex(CPI); 1200 Orig->getOperand(2).setImm(PCLabelId); 1201 break; 1202 } 1203 } 1204 return MI; 1205} 1206 1207bool ARMBaseInstrInfo::produceSameValue(const MachineInstr *MI0, 1208 const MachineInstr *MI1, 1209 const MachineRegisterInfo *MRI) const { 1210 int Opcode = MI0->getOpcode(); 1211 if (Opcode == ARM::t2LDRpci || 1212 Opcode == ARM::t2LDRpci_pic || 1213 Opcode == ARM::tLDRpci || 1214 Opcode == ARM::tLDRpci_pic || 1215 Opcode == ARM::MOV_ga_dyn || 1216 Opcode == ARM::MOV_ga_pcrel || 1217 Opcode == ARM::MOV_ga_pcrel_ldr || 1218 Opcode == ARM::t2MOV_ga_dyn || 1219 Opcode == ARM::t2MOV_ga_pcrel) { 1220 if (MI1->getOpcode() != Opcode) 1221 return false; 1222 if (MI0->getNumOperands() != MI1->getNumOperands()) 1223 return false; 1224 1225 const MachineOperand &MO0 = MI0->getOperand(1); 1226 const MachineOperand &MO1 = MI1->getOperand(1); 1227 if (MO0.getOffset() != MO1.getOffset()) 1228 return false; 1229 1230 if (Opcode == ARM::MOV_ga_dyn || 1231 Opcode == ARM::MOV_ga_pcrel || 1232 Opcode == ARM::MOV_ga_pcrel_ldr || 1233 Opcode == ARM::t2MOV_ga_dyn || 1234 Opcode == ARM::t2MOV_ga_pcrel) 1235 // Ignore the PC labels. 1236 return MO0.getGlobal() == MO1.getGlobal(); 1237 1238 const MachineFunction *MF = MI0->getParent()->getParent(); 1239 const MachineConstantPool *MCP = MF->getConstantPool(); 1240 int CPI0 = MO0.getIndex(); 1241 int CPI1 = MO1.getIndex(); 1242 const MachineConstantPoolEntry &MCPE0 = MCP->getConstants()[CPI0]; 1243 const MachineConstantPoolEntry &MCPE1 = MCP->getConstants()[CPI1]; 1244 bool isARMCP0 = MCPE0.isMachineConstantPoolEntry(); 1245 bool isARMCP1 = MCPE1.isMachineConstantPoolEntry(); 1246 if (isARMCP0 && isARMCP1) { 1247 ARMConstantPoolValue *ACPV0 = 1248 static_cast<ARMConstantPoolValue*>(MCPE0.Val.MachineCPVal); 1249 ARMConstantPoolValue *ACPV1 = 1250 static_cast<ARMConstantPoolValue*>(MCPE1.Val.MachineCPVal); 1251 return ACPV0->hasSameValue(ACPV1); 1252 } else if (!isARMCP0 && !isARMCP1) { 1253 return MCPE0.Val.ConstVal == MCPE1.Val.ConstVal; 1254 } 1255 return false; 1256 } else if (Opcode == ARM::PICLDR) { 1257 if (MI1->getOpcode() != Opcode) 1258 return false; 1259 if (MI0->getNumOperands() != MI1->getNumOperands()) 1260 return false; 1261 1262 unsigned Addr0 = MI0->getOperand(1).getReg(); 1263 unsigned Addr1 = MI1->getOperand(1).getReg(); 1264 if (Addr0 != Addr1) { 1265 if (!MRI || 1266 !TargetRegisterInfo::isVirtualRegister(Addr0) || 1267 !TargetRegisterInfo::isVirtualRegister(Addr1)) 1268 return false; 1269 1270 // This assumes SSA form. 1271 MachineInstr *Def0 = MRI->getVRegDef(Addr0); 1272 MachineInstr *Def1 = MRI->getVRegDef(Addr1); 1273 // Check if the loaded value, e.g. a constantpool of a global address, are 1274 // the same. 1275 if (!produceSameValue(Def0, Def1, MRI)) 1276 return false; 1277 } 1278 1279 for (unsigned i = 3, e = MI0->getNumOperands(); i != e; ++i) { 1280 // %vreg12<def> = PICLDR %vreg11, 0, pred:14, pred:%noreg 1281 const MachineOperand &MO0 = MI0->getOperand(i); 1282 const MachineOperand &MO1 = MI1->getOperand(i); 1283 if (!MO0.isIdenticalTo(MO1)) 1284 return false; 1285 } 1286 return true; 1287 } 1288 1289 return MI0->isIdenticalTo(MI1, MachineInstr::IgnoreVRegDefs); 1290} 1291 1292/// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to 1293/// determine if two loads are loading from the same base address. It should 1294/// only return true if the base pointers are the same and the only differences 1295/// between the two addresses is the offset. It also returns the offsets by 1296/// reference. 1297bool ARMBaseInstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, 1298 int64_t &Offset1, 1299 int64_t &Offset2) const { 1300 // Don't worry about Thumb: just ARM and Thumb2. 1301 if (Subtarget.isThumb1Only()) return false; 1302 1303 if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode()) 1304 return false; 1305 1306 switch (Load1->getMachineOpcode()) { 1307 default: 1308 return false; 1309 case ARM::LDRi12: 1310 case ARM::LDRBi12: 1311 case ARM::LDRD: 1312 case ARM::LDRH: 1313 case ARM::LDRSB: 1314 case ARM::LDRSH: 1315 case ARM::VLDRD: 1316 case ARM::VLDRS: 1317 case ARM::t2LDRi8: 1318 case ARM::t2LDRDi8: 1319 case ARM::t2LDRSHi8: 1320 case ARM::t2LDRi12: 1321 case ARM::t2LDRSHi12: 1322 break; 1323 } 1324 1325 switch (Load2->getMachineOpcode()) { 1326 default: 1327 return false; 1328 case ARM::LDRi12: 1329 case ARM::LDRBi12: 1330 case ARM::LDRD: 1331 case ARM::LDRH: 1332 case ARM::LDRSB: 1333 case ARM::LDRSH: 1334 case ARM::VLDRD: 1335 case ARM::VLDRS: 1336 case ARM::t2LDRi8: 1337 case ARM::t2LDRDi8: 1338 case ARM::t2LDRSHi8: 1339 case ARM::t2LDRi12: 1340 case ARM::t2LDRSHi12: 1341 break; 1342 } 1343 1344 // Check if base addresses and chain operands match. 1345 if (Load1->getOperand(0) != Load2->getOperand(0) || 1346 Load1->getOperand(4) != Load2->getOperand(4)) 1347 return false; 1348 1349 // Index should be Reg0. 1350 if (Load1->getOperand(3) != Load2->getOperand(3)) 1351 return false; 1352 1353 // Determine the offsets. 1354 if (isa<ConstantSDNode>(Load1->getOperand(1)) && 1355 isa<ConstantSDNode>(Load2->getOperand(1))) { 1356 Offset1 = cast<ConstantSDNode>(Load1->getOperand(1))->getSExtValue(); 1357 Offset2 = cast<ConstantSDNode>(Load2->getOperand(1))->getSExtValue(); 1358 return true; 1359 } 1360 1361 return false; 1362} 1363 1364/// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to 1365/// determine (in conjunction with areLoadsFromSameBasePtr) if two loads should 1366/// be scheduled togther. On some targets if two loads are loading from 1367/// addresses in the same cache line, it's better if they are scheduled 1368/// together. This function takes two integers that represent the load offsets 1369/// from the common base address. It returns true if it decides it's desirable 1370/// to schedule the two loads together. "NumLoads" is the number of loads that 1371/// have already been scheduled after Load1. 1372bool ARMBaseInstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, 1373 int64_t Offset1, int64_t Offset2, 1374 unsigned NumLoads) const { 1375 // Don't worry about Thumb: just ARM and Thumb2. 1376 if (Subtarget.isThumb1Only()) return false; 1377 1378 assert(Offset2 > Offset1); 1379 1380 if ((Offset2 - Offset1) / 8 > 64) 1381 return false; 1382 1383 if (Load1->getMachineOpcode() != Load2->getMachineOpcode()) 1384 return false; // FIXME: overly conservative? 1385 1386 // Four loads in a row should be sufficient. 1387 if (NumLoads >= 3) 1388 return false; 1389 1390 return true; 1391} 1392 1393bool ARMBaseInstrInfo::isSchedulingBoundary(const MachineInstr *MI, 1394 const MachineBasicBlock *MBB, 1395 const MachineFunction &MF) const { 1396 // Debug info is never a scheduling boundary. It's necessary to be explicit 1397 // due to the special treatment of IT instructions below, otherwise a 1398 // dbg_value followed by an IT will result in the IT instruction being 1399 // considered a scheduling hazard, which is wrong. It should be the actual 1400 // instruction preceding the dbg_value instruction(s), just like it is 1401 // when debug info is not present. 1402 if (MI->isDebugValue()) 1403 return false; 1404 1405 // Terminators and labels can't be scheduled around. 1406 if (MI->isTerminator() || MI->isLabel()) 1407 return true; 1408 1409 // Treat the start of the IT block as a scheduling boundary, but schedule 1410 // t2IT along with all instructions following it. 1411 // FIXME: This is a big hammer. But the alternative is to add all potential 1412 // true and anti dependencies to IT block instructions as implicit operands 1413 // to the t2IT instruction. The added compile time and complexity does not 1414 // seem worth it. 1415 MachineBasicBlock::const_iterator I = MI; 1416 // Make sure to skip any dbg_value instructions 1417 while (++I != MBB->end() && I->isDebugValue()) 1418 ; 1419 if (I != MBB->end() && I->getOpcode() == ARM::t2IT) 1420 return true; 1421 1422 // Don't attempt to schedule around any instruction that defines 1423 // a stack-oriented pointer, as it's unlikely to be profitable. This 1424 // saves compile time, because it doesn't require every single 1425 // stack slot reference to depend on the instruction that does the 1426 // modification. 1427 // Calls don't actually change the stack pointer, even if they have imp-defs. 1428 // No ARM calling conventions change the stack pointer. (X86 calling 1429 // conventions sometimes do). 1430 if (!MI->isCall() && MI->definesRegister(ARM::SP)) 1431 return true; 1432 1433 return false; 1434} 1435 1436bool ARMBaseInstrInfo:: 1437isProfitableToIfCvt(MachineBasicBlock &MBB, 1438 unsigned NumCycles, unsigned ExtraPredCycles, 1439 const BranchProbability &Probability) const { 1440 if (!NumCycles) 1441 return false; 1442 1443 // Attempt to estimate the relative costs of predication versus branching. 1444 unsigned UnpredCost = Probability.getNumerator() * NumCycles; 1445 UnpredCost /= Probability.getDenominator(); 1446 UnpredCost += 1; // The branch itself 1447 UnpredCost += Subtarget.getMispredictionPenalty() / 10; 1448 1449 return (NumCycles + ExtraPredCycles) <= UnpredCost; 1450} 1451 1452bool ARMBaseInstrInfo:: 1453isProfitableToIfCvt(MachineBasicBlock &TMBB, 1454 unsigned TCycles, unsigned TExtra, 1455 MachineBasicBlock &FMBB, 1456 unsigned FCycles, unsigned FExtra, 1457 const BranchProbability &Probability) const { 1458 if (!TCycles || !FCycles) 1459 return false; 1460 1461 // Attempt to estimate the relative costs of predication versus branching. 1462 unsigned TUnpredCost = Probability.getNumerator() * TCycles; 1463 TUnpredCost /= Probability.getDenominator(); 1464 1465 uint32_t Comp = Probability.getDenominator() - Probability.getNumerator(); 1466 unsigned FUnpredCost = Comp * FCycles; 1467 FUnpredCost /= Probability.getDenominator(); 1468 1469 unsigned UnpredCost = TUnpredCost + FUnpredCost; 1470 UnpredCost += 1; // The branch itself 1471 UnpredCost += Subtarget.getMispredictionPenalty() / 10; 1472 1473 return (TCycles + FCycles + TExtra + FExtra) <= UnpredCost; 1474} 1475 1476/// getInstrPredicate - If instruction is predicated, returns its predicate 1477/// condition, otherwise returns AL. It also returns the condition code 1478/// register by reference. 1479ARMCC::CondCodes 1480llvm::getInstrPredicate(const MachineInstr *MI, unsigned &PredReg) { 1481 int PIdx = MI->findFirstPredOperandIdx(); 1482 if (PIdx == -1) { 1483 PredReg = 0; 1484 return ARMCC::AL; 1485 } 1486 1487 PredReg = MI->getOperand(PIdx+1).getReg(); 1488 return (ARMCC::CondCodes)MI->getOperand(PIdx).getImm(); 1489} 1490 1491 1492int llvm::getMatchingCondBranchOpcode(int Opc) { 1493 if (Opc == ARM::B) 1494 return ARM::Bcc; 1495 if (Opc == ARM::tB) 1496 return ARM::tBcc; 1497 if (Opc == ARM::t2B) 1498 return ARM::t2Bcc; 1499 1500 llvm_unreachable("Unknown unconditional branch opcode!"); 1501} 1502 1503/// commuteInstruction - Handle commutable instructions. 1504MachineInstr * 1505ARMBaseInstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const { 1506 switch (MI->getOpcode()) { 1507 case ARM::MOVCCr: 1508 case ARM::t2MOVCCr: { 1509 // MOVCC can be commuted by inverting the condition. 1510 unsigned PredReg = 0; 1511 ARMCC::CondCodes CC = getInstrPredicate(MI, PredReg); 1512 // MOVCC AL can't be inverted. Shouldn't happen. 1513 if (CC == ARMCC::AL || PredReg != ARM::CPSR) 1514 return NULL; 1515 MI = TargetInstrInfoImpl::commuteInstruction(MI, NewMI); 1516 if (!MI) 1517 return NULL; 1518 // After swapping the MOVCC operands, also invert the condition. 1519 MI->getOperand(MI->findFirstPredOperandIdx()) 1520 .setImm(ARMCC::getOppositeCondition(CC)); 1521 return MI; 1522 } 1523 } 1524 return TargetInstrInfoImpl::commuteInstruction(MI, NewMI); 1525} 1526 1527/// Map pseudo instructions that imply an 'S' bit onto real opcodes. Whether the 1528/// instruction is encoded with an 'S' bit is determined by the optional CPSR 1529/// def operand. 1530/// 1531/// This will go away once we can teach tblgen how to set the optional CPSR def 1532/// operand itself. 1533struct AddSubFlagsOpcodePair { 1534 uint16_t PseudoOpc; 1535 uint16_t MachineOpc; 1536}; 1537 1538static const AddSubFlagsOpcodePair AddSubFlagsOpcodeMap[] = { 1539 {ARM::ADDSri, ARM::ADDri}, 1540 {ARM::ADDSrr, ARM::ADDrr}, 1541 {ARM::ADDSrsi, ARM::ADDrsi}, 1542 {ARM::ADDSrsr, ARM::ADDrsr}, 1543 1544 {ARM::SUBSri, ARM::SUBri}, 1545 {ARM::SUBSrr, ARM::SUBrr}, 1546 {ARM::SUBSrsi, ARM::SUBrsi}, 1547 {ARM::SUBSrsr, ARM::SUBrsr}, 1548 1549 {ARM::RSBSri, ARM::RSBri}, 1550 {ARM::RSBSrsi, ARM::RSBrsi}, 1551 {ARM::RSBSrsr, ARM::RSBrsr}, 1552 1553 {ARM::t2ADDSri, ARM::t2ADDri}, 1554 {ARM::t2ADDSrr, ARM::t2ADDrr}, 1555 {ARM::t2ADDSrs, ARM::t2ADDrs}, 1556 1557 {ARM::t2SUBSri, ARM::t2SUBri}, 1558 {ARM::t2SUBSrr, ARM::t2SUBrr}, 1559 {ARM::t2SUBSrs, ARM::t2SUBrs}, 1560 1561 {ARM::t2RSBSri, ARM::t2RSBri}, 1562 {ARM::t2RSBSrs, ARM::t2RSBrs}, 1563}; 1564 1565unsigned llvm::convertAddSubFlagsOpcode(unsigned OldOpc) { 1566 for (unsigned i = 0, e = array_lengthof(AddSubFlagsOpcodeMap); i != e; ++i) 1567 if (OldOpc == AddSubFlagsOpcodeMap[i].PseudoOpc) 1568 return AddSubFlagsOpcodeMap[i].MachineOpc; 1569 return 0; 1570} 1571 1572void llvm::emitARMRegPlusImmediate(MachineBasicBlock &MBB, 1573 MachineBasicBlock::iterator &MBBI, DebugLoc dl, 1574 unsigned DestReg, unsigned BaseReg, int NumBytes, 1575 ARMCC::CondCodes Pred, unsigned PredReg, 1576 const ARMBaseInstrInfo &TII, unsigned MIFlags) { 1577 bool isSub = NumBytes < 0; 1578 if (isSub) NumBytes = -NumBytes; 1579 1580 while (NumBytes) { 1581 unsigned RotAmt = ARM_AM::getSOImmValRotate(NumBytes); 1582 unsigned ThisVal = NumBytes & ARM_AM::rotr32(0xFF, RotAmt); 1583 assert(ThisVal && "Didn't extract field correctly"); 1584 1585 // We will handle these bits from offset, clear them. 1586 NumBytes &= ~ThisVal; 1587 1588 assert(ARM_AM::getSOImmVal(ThisVal) != -1 && "Bit extraction didn't work?"); 1589 1590 // Build the new ADD / SUB. 1591 unsigned Opc = isSub ? ARM::SUBri : ARM::ADDri; 1592 BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg) 1593 .addReg(BaseReg, RegState::Kill).addImm(ThisVal) 1594 .addImm((unsigned)Pred).addReg(PredReg).addReg(0) 1595 .setMIFlags(MIFlags); 1596 BaseReg = DestReg; 1597 } 1598} 1599 1600bool llvm::rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx, 1601 unsigned FrameReg, int &Offset, 1602 const ARMBaseInstrInfo &TII) { 1603 unsigned Opcode = MI.getOpcode(); 1604 const MCInstrDesc &Desc = MI.getDesc(); 1605 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask); 1606 bool isSub = false; 1607 1608 // Memory operands in inline assembly always use AddrMode2. 1609 if (Opcode == ARM::INLINEASM) 1610 AddrMode = ARMII::AddrMode2; 1611 1612 if (Opcode == ARM::ADDri) { 1613 Offset += MI.getOperand(FrameRegIdx+1).getImm(); 1614 if (Offset == 0) { 1615 // Turn it into a move. 1616 MI.setDesc(TII.get(ARM::MOVr)); 1617 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false); 1618 MI.RemoveOperand(FrameRegIdx+1); 1619 Offset = 0; 1620 return true; 1621 } else if (Offset < 0) { 1622 Offset = -Offset; 1623 isSub = true; 1624 MI.setDesc(TII.get(ARM::SUBri)); 1625 } 1626 1627 // Common case: small offset, fits into instruction. 1628 if (ARM_AM::getSOImmVal(Offset) != -1) { 1629 // Replace the FrameIndex with sp / fp 1630 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false); 1631 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset); 1632 Offset = 0; 1633 return true; 1634 } 1635 1636 // Otherwise, pull as much of the immedidate into this ADDri/SUBri 1637 // as possible. 1638 unsigned RotAmt = ARM_AM::getSOImmValRotate(Offset); 1639 unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xFF, RotAmt); 1640 1641 // We will handle these bits from offset, clear them. 1642 Offset &= ~ThisImmVal; 1643 1644 // Get the properly encoded SOImmVal field. 1645 assert(ARM_AM::getSOImmVal(ThisImmVal) != -1 && 1646 "Bit extraction didn't work?"); 1647 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(ThisImmVal); 1648 } else { 1649 unsigned ImmIdx = 0; 1650 int InstrOffs = 0; 1651 unsigned NumBits = 0; 1652 unsigned Scale = 1; 1653 switch (AddrMode) { 1654 case ARMII::AddrMode_i12: { 1655 ImmIdx = FrameRegIdx + 1; 1656 InstrOffs = MI.getOperand(ImmIdx).getImm(); 1657 NumBits = 12; 1658 break; 1659 } 1660 case ARMII::AddrMode2: { 1661 ImmIdx = FrameRegIdx+2; 1662 InstrOffs = ARM_AM::getAM2Offset(MI.getOperand(ImmIdx).getImm()); 1663 if (ARM_AM::getAM2Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub) 1664 InstrOffs *= -1; 1665 NumBits = 12; 1666 break; 1667 } 1668 case ARMII::AddrMode3: { 1669 ImmIdx = FrameRegIdx+2; 1670 InstrOffs = ARM_AM::getAM3Offset(MI.getOperand(ImmIdx).getImm()); 1671 if (ARM_AM::getAM3Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub) 1672 InstrOffs *= -1; 1673 NumBits = 8; 1674 break; 1675 } 1676 case ARMII::AddrMode4: 1677 case ARMII::AddrMode6: 1678 // Can't fold any offset even if it's zero. 1679 return false; 1680 case ARMII::AddrMode5: { 1681 ImmIdx = FrameRegIdx+1; 1682 InstrOffs = ARM_AM::getAM5Offset(MI.getOperand(ImmIdx).getImm()); 1683 if (ARM_AM::getAM5Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub) 1684 InstrOffs *= -1; 1685 NumBits = 8; 1686 Scale = 4; 1687 break; 1688 } 1689 default: 1690 llvm_unreachable("Unsupported addressing mode!"); 1691 } 1692 1693 Offset += InstrOffs * Scale; 1694 assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!"); 1695 if (Offset < 0) { 1696 Offset = -Offset; 1697 isSub = true; 1698 } 1699 1700 // Attempt to fold address comp. if opcode has offset bits 1701 if (NumBits > 0) { 1702 // Common case: small offset, fits into instruction. 1703 MachineOperand &ImmOp = MI.getOperand(ImmIdx); 1704 int ImmedOffset = Offset / Scale; 1705 unsigned Mask = (1 << NumBits) - 1; 1706 if ((unsigned)Offset <= Mask * Scale) { 1707 // Replace the FrameIndex with sp 1708 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false); 1709 // FIXME: When addrmode2 goes away, this will simplify (like the 1710 // T2 version), as the LDR.i12 versions don't need the encoding 1711 // tricks for the offset value. 1712 if (isSub) { 1713 if (AddrMode == ARMII::AddrMode_i12) 1714 ImmedOffset = -ImmedOffset; 1715 else 1716 ImmedOffset |= 1 << NumBits; 1717 } 1718 ImmOp.ChangeToImmediate(ImmedOffset); 1719 Offset = 0; 1720 return true; 1721 } 1722 1723 // Otherwise, it didn't fit. Pull in what we can to simplify the immed. 1724 ImmedOffset = ImmedOffset & Mask; 1725 if (isSub) { 1726 if (AddrMode == ARMII::AddrMode_i12) 1727 ImmedOffset = -ImmedOffset; 1728 else 1729 ImmedOffset |= 1 << NumBits; 1730 } 1731 ImmOp.ChangeToImmediate(ImmedOffset); 1732 Offset &= ~(Mask*Scale); 1733 } 1734 } 1735 1736 Offset = (isSub) ? -Offset : Offset; 1737 return Offset == 0; 1738} 1739 1740/// analyzeCompare - For a comparison instruction, return the source registers 1741/// in SrcReg and SrcReg2 if having two register operands, and the value it 1742/// compares against in CmpValue. Return true if the comparison instruction 1743/// can be analyzed. 1744bool ARMBaseInstrInfo:: 1745analyzeCompare(const MachineInstr *MI, unsigned &SrcReg, unsigned &SrcReg2, 1746 int &CmpMask, int &CmpValue) const { 1747 switch (MI->getOpcode()) { 1748 default: break; 1749 case ARM::CMPri: 1750 case ARM::t2CMPri: 1751 SrcReg = MI->getOperand(0).getReg(); 1752 SrcReg2 = 0; 1753 CmpMask = ~0; 1754 CmpValue = MI->getOperand(1).getImm(); 1755 return true; 1756 case ARM::CMPrr: 1757 case ARM::t2CMPrr: 1758 SrcReg = MI->getOperand(0).getReg(); 1759 SrcReg2 = MI->getOperand(1).getReg(); 1760 CmpMask = ~0; 1761 CmpValue = 0; 1762 return true; 1763 case ARM::TSTri: 1764 case ARM::t2TSTri: 1765 SrcReg = MI->getOperand(0).getReg(); 1766 SrcReg2 = 0; 1767 CmpMask = MI->getOperand(1).getImm(); 1768 CmpValue = 0; 1769 return true; 1770 } 1771 1772 return false; 1773} 1774 1775/// isSuitableForMask - Identify a suitable 'and' instruction that 1776/// operates on the given source register and applies the same mask 1777/// as a 'tst' instruction. Provide a limited look-through for copies. 1778/// When successful, MI will hold the found instruction. 1779static bool isSuitableForMask(MachineInstr *&MI, unsigned SrcReg, 1780 int CmpMask, bool CommonUse) { 1781 switch (MI->getOpcode()) { 1782 case ARM::ANDri: 1783 case ARM::t2ANDri: 1784 if (CmpMask != MI->getOperand(2).getImm()) 1785 return false; 1786 if (SrcReg == MI->getOperand(CommonUse ? 1 : 0).getReg()) 1787 return true; 1788 break; 1789 case ARM::COPY: { 1790 // Walk down one instruction which is potentially an 'and'. 1791 const MachineInstr &Copy = *MI; 1792 MachineBasicBlock::iterator AND( 1793 llvm::next(MachineBasicBlock::iterator(MI))); 1794 if (AND == MI->getParent()->end()) return false; 1795 MI = AND; 1796 return isSuitableForMask(MI, Copy.getOperand(0).getReg(), 1797 CmpMask, true); 1798 } 1799 } 1800 1801 return false; 1802} 1803 1804/// getSwappedCondition - assume the flags are set by MI(a,b), return 1805/// the condition code if we modify the instructions such that flags are 1806/// set by MI(b,a). 1807inline static ARMCC::CondCodes getSwappedCondition(ARMCC::CondCodes CC) { 1808 switch (CC) { 1809 default: return ARMCC::AL; 1810 case ARMCC::EQ: return ARMCC::EQ; 1811 case ARMCC::NE: return ARMCC::NE; 1812 case ARMCC::HS: return ARMCC::LS; 1813 case ARMCC::LO: return ARMCC::HI; 1814 case ARMCC::HI: return ARMCC::LO; 1815 case ARMCC::LS: return ARMCC::HS; 1816 case ARMCC::GE: return ARMCC::LE; 1817 case ARMCC::LT: return ARMCC::GT; 1818 case ARMCC::GT: return ARMCC::LT; 1819 case ARMCC::LE: return ARMCC::GE; 1820 } 1821} 1822 1823/// isRedundantFlagInstr - check whether the first instruction, whose only 1824/// purpose is to update flags, can be made redundant. 1825/// CMPrr can be made redundant by SUBrr if the operands are the same. 1826/// CMPri can be made redundant by SUBri if the operands are the same. 1827/// This function can be extended later on. 1828inline static bool isRedundantFlagInstr(MachineInstr *CmpI, unsigned SrcReg, 1829 unsigned SrcReg2, int ImmValue, 1830 MachineInstr *OI) { 1831 if ((CmpI->getOpcode() == ARM::CMPrr || 1832 CmpI->getOpcode() == ARM::t2CMPrr) && 1833 (OI->getOpcode() == ARM::SUBrr || 1834 OI->getOpcode() == ARM::t2SUBrr) && 1835 ((OI->getOperand(1).getReg() == SrcReg && 1836 OI->getOperand(2).getReg() == SrcReg2) || 1837 (OI->getOperand(1).getReg() == SrcReg2 && 1838 OI->getOperand(2).getReg() == SrcReg))) 1839 return true; 1840 1841 if ((CmpI->getOpcode() == ARM::CMPri || 1842 CmpI->getOpcode() == ARM::t2CMPri) && 1843 (OI->getOpcode() == ARM::SUBri || 1844 OI->getOpcode() == ARM::t2SUBri) && 1845 OI->getOperand(1).getReg() == SrcReg && 1846 OI->getOperand(2).getImm() == ImmValue) 1847 return true; 1848 return false; 1849} 1850 1851/// optimizeCompareInstr - Convert the instruction supplying the argument to the 1852/// comparison into one that sets the zero bit in the flags register; 1853/// Remove a redundant Compare instruction if an earlier instruction can set the 1854/// flags in the same way as Compare. 1855/// E.g. SUBrr(r1,r2) and CMPrr(r1,r2). We also handle the case where two 1856/// operands are swapped: SUBrr(r1,r2) and CMPrr(r2,r1), by updating the 1857/// condition code of instructions which use the flags. 1858bool ARMBaseInstrInfo:: 1859optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, unsigned SrcReg2, 1860 int CmpMask, int CmpValue, 1861 const MachineRegisterInfo *MRI) const { 1862 // Get the unique definition of SrcReg. 1863 MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg); 1864 if (!MI) return false; 1865 1866 // Masked compares sometimes use the same register as the corresponding 'and'. 1867 if (CmpMask != ~0) { 1868 if (!isSuitableForMask(MI, SrcReg, CmpMask, false)) { 1869 MI = 0; 1870 for (MachineRegisterInfo::use_iterator UI = MRI->use_begin(SrcReg), 1871 UE = MRI->use_end(); UI != UE; ++UI) { 1872 if (UI->getParent() != CmpInstr->getParent()) continue; 1873 MachineInstr *PotentialAND = &*UI; 1874 if (!isSuitableForMask(PotentialAND, SrcReg, CmpMask, true)) 1875 continue; 1876 MI = PotentialAND; 1877 break; 1878 } 1879 if (!MI) return false; 1880 } 1881 } 1882 1883 // Get ready to iterate backward from CmpInstr. 1884 MachineBasicBlock::iterator I = CmpInstr, E = MI, 1885 B = CmpInstr->getParent()->begin(); 1886 1887 // Early exit if CmpInstr is at the beginning of the BB. 1888 if (I == B) return false; 1889 1890 // There are two possible candidates which can be changed to set CPSR: 1891 // One is MI, the other is a SUB instruction. 1892 // For CMPrr(r1,r2), we are looking for SUB(r1,r2) or SUB(r2,r1). 1893 // For CMPri(r1, CmpValue), we are looking for SUBri(r1, CmpValue). 1894 MachineInstr *Sub = NULL; 1895 if (SrcReg2 != 0) 1896 // MI is not a candidate for CMPrr. 1897 MI = NULL; 1898 else if (MI->getParent() != CmpInstr->getParent() || CmpValue != 0) { 1899 // Conservatively refuse to convert an instruction which isn't in the same 1900 // BB as the comparison. 1901 // For CMPri, we need to check Sub, thus we can't return here. 1902 if (CmpInstr->getOpcode() == ARM::CMPri || 1903 CmpInstr->getOpcode() == ARM::t2CMPri) 1904 MI = NULL; 1905 else 1906 return false; 1907 } 1908 1909 // Check that CPSR isn't set between the comparison instruction and the one we 1910 // want to change. At the same time, search for Sub. 1911 const TargetRegisterInfo *TRI = &getRegisterInfo(); 1912 --I; 1913 for (; I != E; --I) { 1914 const MachineInstr &Instr = *I; 1915 1916 if (Instr.modifiesRegister(ARM::CPSR, TRI) || 1917 Instr.readsRegister(ARM::CPSR, TRI)) 1918 // This instruction modifies or uses CPSR after the one we want to 1919 // change. We can't do this transformation. 1920 return false; 1921 1922 // Check whether CmpInstr can be made redundant by the current instruction. 1923 if (isRedundantFlagInstr(CmpInstr, SrcReg, SrcReg2, CmpValue, &*I)) { 1924 Sub = &*I; 1925 break; 1926 } 1927 1928 if (I == B) 1929 // The 'and' is below the comparison instruction. 1930 return false; 1931 } 1932 1933 // Return false if no candidates exist. 1934 if (!MI && !Sub) 1935 return false; 1936 1937 // The single candidate is called MI. 1938 if (!MI) MI = Sub; 1939 1940 switch (MI->getOpcode()) { 1941 default: break; 1942 case ARM::RSBrr: 1943 case ARM::RSBri: 1944 case ARM::RSCrr: 1945 case ARM::RSCri: 1946 case ARM::ADDrr: 1947 case ARM::ADDri: 1948 case ARM::ADCrr: 1949 case ARM::ADCri: 1950 case ARM::SUBrr: 1951 case ARM::SUBri: 1952 case ARM::SBCrr: 1953 case ARM::SBCri: 1954 case ARM::t2RSBri: 1955 case ARM::t2ADDrr: 1956 case ARM::t2ADDri: 1957 case ARM::t2ADCrr: 1958 case ARM::t2ADCri: 1959 case ARM::t2SUBrr: 1960 case ARM::t2SUBri: 1961 case ARM::t2SBCrr: 1962 case ARM::t2SBCri: 1963 case ARM::ANDrr: 1964 case ARM::ANDri: 1965 case ARM::t2ANDrr: 1966 case ARM::t2ANDri: 1967 case ARM::ORRrr: 1968 case ARM::ORRri: 1969 case ARM::t2ORRrr: 1970 case ARM::t2ORRri: 1971 case ARM::EORrr: 1972 case ARM::EORri: 1973 case ARM::t2EORrr: 1974 case ARM::t2EORri: { 1975 // Scan forward for the use of CPSR 1976 // When checking against MI: if it's a conditional code requires 1977 // checking of V bit, then this is not safe to do. If we can't find the 1978 // CPSR use (i.e. used in another block), then it's not safe to perform 1979 // the optimization. 1980 // When checking against Sub, we handle the condition codes GE, LT, GT, LE. 1981 SmallVector<std::pair<MachineOperand*, ARMCC::CondCodes>, 4> 1982 OperandsToUpdate; 1983 bool isSafe = false; 1984 I = CmpInstr; 1985 E = CmpInstr->getParent()->end(); 1986 while (!isSafe && ++I != E) { 1987 const MachineInstr &Instr = *I; 1988 for (unsigned IO = 0, EO = Instr.getNumOperands(); 1989 !isSafe && IO != EO; ++IO) { 1990 const MachineOperand &MO = Instr.getOperand(IO); 1991 if (MO.isRegMask() && MO.clobbersPhysReg(ARM::CPSR)) { 1992 isSafe = true; 1993 break; 1994 } 1995 if (!MO.isReg() || MO.getReg() != ARM::CPSR) 1996 continue; 1997 if (MO.isDef()) { 1998 isSafe = true; 1999 break; 2000 } 2001 // Condition code is after the operand before CPSR. 2002 ARMCC::CondCodes CC = (ARMCC::CondCodes)Instr.getOperand(IO-1).getImm(); 2003 if (Sub) { 2004 ARMCC::CondCodes NewCC = getSwappedCondition(CC); 2005 if (NewCC == ARMCC::AL) 2006 return false; 2007 // If we have SUB(r1, r2) and CMP(r2, r1), the condition code based 2008 // on CMP needs to be updated to be based on SUB. 2009 // Push the condition code operands to OperandsToUpdate. 2010 // If it is safe to remove CmpInstr, the condition code of these 2011 // operands will be modified. 2012 if (SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 && 2013 Sub->getOperand(2).getReg() == SrcReg) 2014 OperandsToUpdate.push_back(std::make_pair(&((*I).getOperand(IO-1)), 2015 NewCC)); 2016 } 2017 else 2018 switch (CC) { 2019 default: 2020 isSafe = true; 2021 break; 2022 case ARMCC::VS: 2023 case ARMCC::VC: 2024 case ARMCC::GE: 2025 case ARMCC::LT: 2026 case ARMCC::GT: 2027 case ARMCC::LE: 2028 return false; 2029 } 2030 } 2031 } 2032 2033 // If the candidate is Sub, we may exit the loop at end of the basic block. 2034 // In that case, it is still safe to remove CmpInstr. 2035 if (!isSafe && !Sub) 2036 return false; 2037 2038 // Toggle the optional operand to CPSR. 2039 MI->getOperand(5).setReg(ARM::CPSR); 2040 MI->getOperand(5).setIsDef(true); 2041 CmpInstr->eraseFromParent(); 2042 2043 // Modify the condition code of operands in OperandsToUpdate. 2044 // Since we have SUB(r1, r2) and CMP(r2, r1), the condition code needs to 2045 // be changed from r2 > r1 to r1 < r2, from r2 < r1 to r1 > r2, etc. 2046 for (unsigned i = 0, e = OperandsToUpdate.size(); i < e; i++) 2047 OperandsToUpdate[i].first->setImm(OperandsToUpdate[i].second); 2048 return true; 2049 } 2050 } 2051 2052 return false; 2053} 2054 2055bool ARMBaseInstrInfo::FoldImmediate(MachineInstr *UseMI, 2056 MachineInstr *DefMI, unsigned Reg, 2057 MachineRegisterInfo *MRI) const { 2058 // Fold large immediates into add, sub, or, xor. 2059 unsigned DefOpc = DefMI->getOpcode(); 2060 if (DefOpc != ARM::t2MOVi32imm && DefOpc != ARM::MOVi32imm) 2061 return false; 2062 if (!DefMI->getOperand(1).isImm()) 2063 // Could be t2MOVi32imm <ga:xx> 2064 return false; 2065 2066 if (!MRI->hasOneNonDBGUse(Reg)) 2067 return false; 2068 2069 const MCInstrDesc &DefMCID = DefMI->getDesc(); 2070 if (DefMCID.hasOptionalDef()) { 2071 unsigned NumOps = DefMCID.getNumOperands(); 2072 const MachineOperand &MO = DefMI->getOperand(NumOps-1); 2073 if (MO.getReg() == ARM::CPSR && !MO.isDead()) 2074 // If DefMI defines CPSR and it is not dead, it's obviously not safe 2075 // to delete DefMI. 2076 return false; 2077 } 2078 2079 const MCInstrDesc &UseMCID = UseMI->getDesc(); 2080 if (UseMCID.hasOptionalDef()) { 2081 unsigned NumOps = UseMCID.getNumOperands(); 2082 if (UseMI->getOperand(NumOps-1).getReg() == ARM::CPSR) 2083 // If the instruction sets the flag, do not attempt this optimization 2084 // since it may change the semantics of the code. 2085 return false; 2086 } 2087 2088 unsigned UseOpc = UseMI->getOpcode(); 2089 unsigned NewUseOpc = 0; 2090 uint32_t ImmVal = (uint32_t)DefMI->getOperand(1).getImm(); 2091 uint32_t SOImmValV1 = 0, SOImmValV2 = 0; 2092 bool Commute = false; 2093 switch (UseOpc) { 2094 default: return false; 2095 case ARM::SUBrr: 2096 case ARM::ADDrr: 2097 case ARM::ORRrr: 2098 case ARM::EORrr: 2099 case ARM::t2SUBrr: 2100 case ARM::t2ADDrr: 2101 case ARM::t2ORRrr: 2102 case ARM::t2EORrr: { 2103 Commute = UseMI->getOperand(2).getReg() != Reg; 2104 switch (UseOpc) { 2105 default: break; 2106 case ARM::SUBrr: { 2107 if (Commute) 2108 return false; 2109 ImmVal = -ImmVal; 2110 NewUseOpc = ARM::SUBri; 2111 // Fallthrough 2112 } 2113 case ARM::ADDrr: 2114 case ARM::ORRrr: 2115 case ARM::EORrr: { 2116 if (!ARM_AM::isSOImmTwoPartVal(ImmVal)) 2117 return false; 2118 SOImmValV1 = (uint32_t)ARM_AM::getSOImmTwoPartFirst(ImmVal); 2119 SOImmValV2 = (uint32_t)ARM_AM::getSOImmTwoPartSecond(ImmVal); 2120 switch (UseOpc) { 2121 default: break; 2122 case ARM::ADDrr: NewUseOpc = ARM::ADDri; break; 2123 case ARM::ORRrr: NewUseOpc = ARM::ORRri; break; 2124 case ARM::EORrr: NewUseOpc = ARM::EORri; break; 2125 } 2126 break; 2127 } 2128 case ARM::t2SUBrr: { 2129 if (Commute) 2130 return false; 2131 ImmVal = -ImmVal; 2132 NewUseOpc = ARM::t2SUBri; 2133 // Fallthrough 2134 } 2135 case ARM::t2ADDrr: 2136 case ARM::t2ORRrr: 2137 case ARM::t2EORrr: { 2138 if (!ARM_AM::isT2SOImmTwoPartVal(ImmVal)) 2139 return false; 2140 SOImmValV1 = (uint32_t)ARM_AM::getT2SOImmTwoPartFirst(ImmVal); 2141 SOImmValV2 = (uint32_t)ARM_AM::getT2SOImmTwoPartSecond(ImmVal); 2142 switch (UseOpc) { 2143 default: break; 2144 case ARM::t2ADDrr: NewUseOpc = ARM::t2ADDri; break; 2145 case ARM::t2ORRrr: NewUseOpc = ARM::t2ORRri; break; 2146 case ARM::t2EORrr: NewUseOpc = ARM::t2EORri; break; 2147 } 2148 break; 2149 } 2150 } 2151 } 2152 } 2153 2154 unsigned OpIdx = Commute ? 2 : 1; 2155 unsigned Reg1 = UseMI->getOperand(OpIdx).getReg(); 2156 bool isKill = UseMI->getOperand(OpIdx).isKill(); 2157 unsigned NewReg = MRI->createVirtualRegister(MRI->getRegClass(Reg)); 2158 AddDefaultCC(AddDefaultPred(BuildMI(*UseMI->getParent(), 2159 UseMI, UseMI->getDebugLoc(), 2160 get(NewUseOpc), NewReg) 2161 .addReg(Reg1, getKillRegState(isKill)) 2162 .addImm(SOImmValV1))); 2163 UseMI->setDesc(get(NewUseOpc)); 2164 UseMI->getOperand(1).setReg(NewReg); 2165 UseMI->getOperand(1).setIsKill(); 2166 UseMI->getOperand(2).ChangeToImmediate(SOImmValV2); 2167 DefMI->eraseFromParent(); 2168 return true; 2169} 2170 2171unsigned 2172ARMBaseInstrInfo::getNumMicroOps(const InstrItineraryData *ItinData, 2173 const MachineInstr *MI) const { 2174 if (!ItinData || ItinData->isEmpty()) 2175 return 1; 2176 2177 const MCInstrDesc &Desc = MI->getDesc(); 2178 unsigned Class = Desc.getSchedClass(); 2179 int ItinUOps = ItinData->getNumMicroOps(Class); 2180 if (ItinUOps >= 0) 2181 return ItinUOps; 2182 2183 unsigned Opc = MI->getOpcode(); 2184 switch (Opc) { 2185 default: 2186 llvm_unreachable("Unexpected multi-uops instruction!"); 2187 case ARM::VLDMQIA: 2188 case ARM::VSTMQIA: 2189 return 2; 2190 2191 // The number of uOps for load / store multiple are determined by the number 2192 // registers. 2193 // 2194 // On Cortex-A8, each pair of register loads / stores can be scheduled on the 2195 // same cycle. The scheduling for the first load / store must be done 2196 // separately by assuming the the address is not 64-bit aligned. 2197 // 2198 // On Cortex-A9, the formula is simply (#reg / 2) + (#reg % 2). If the address 2199 // is not 64-bit aligned, then AGU would take an extra cycle. For VFP / NEON 2200 // load / store multiple, the formula is (#reg / 2) + (#reg % 2) + 1. 2201 case ARM::VLDMDIA: 2202 case ARM::VLDMDIA_UPD: 2203 case ARM::VLDMDDB_UPD: 2204 case ARM::VLDMSIA: 2205 case ARM::VLDMSIA_UPD: 2206 case ARM::VLDMSDB_UPD: 2207 case ARM::VSTMDIA: 2208 case ARM::VSTMDIA_UPD: 2209 case ARM::VSTMDDB_UPD: 2210 case ARM::VSTMSIA: 2211 case ARM::VSTMSIA_UPD: 2212 case ARM::VSTMSDB_UPD: { 2213 unsigned NumRegs = MI->getNumOperands() - Desc.getNumOperands(); 2214 return (NumRegs / 2) + (NumRegs % 2) + 1; 2215 } 2216 2217 case ARM::LDMIA_RET: 2218 case ARM::LDMIA: 2219 case ARM::LDMDA: 2220 case ARM::LDMDB: 2221 case ARM::LDMIB: 2222 case ARM::LDMIA_UPD: 2223 case ARM::LDMDA_UPD: 2224 case ARM::LDMDB_UPD: 2225 case ARM::LDMIB_UPD: 2226 case ARM::STMIA: 2227 case ARM::STMDA: 2228 case ARM::STMDB: 2229 case ARM::STMIB: 2230 case ARM::STMIA_UPD: 2231 case ARM::STMDA_UPD: 2232 case ARM::STMDB_UPD: 2233 case ARM::STMIB_UPD: 2234 case ARM::tLDMIA: 2235 case ARM::tLDMIA_UPD: 2236 case ARM::tSTMIA_UPD: 2237 case ARM::tPOP_RET: 2238 case ARM::tPOP: 2239 case ARM::tPUSH: 2240 case ARM::t2LDMIA_RET: 2241 case ARM::t2LDMIA: 2242 case ARM::t2LDMDB: 2243 case ARM::t2LDMIA_UPD: 2244 case ARM::t2LDMDB_UPD: 2245 case ARM::t2STMIA: 2246 case ARM::t2STMDB: 2247 case ARM::t2STMIA_UPD: 2248 case ARM::t2STMDB_UPD: { 2249 unsigned NumRegs = MI->getNumOperands() - Desc.getNumOperands() + 1; 2250 if (Subtarget.isCortexA8()) { 2251 if (NumRegs < 4) 2252 return 2; 2253 // 4 registers would be issued: 2, 2. 2254 // 5 registers would be issued: 2, 2, 1. 2255 int A8UOps = (NumRegs / 2); 2256 if (NumRegs % 2) 2257 ++A8UOps; 2258 return A8UOps; 2259 } else if (Subtarget.isCortexA9()) { 2260 int A9UOps = (NumRegs / 2); 2261 // If there are odd number of registers or if it's not 64-bit aligned, 2262 // then it takes an extra AGU (Address Generation Unit) cycle. 2263 if ((NumRegs % 2) || 2264 !MI->hasOneMemOperand() || 2265 (*MI->memoperands_begin())->getAlignment() < 8) 2266 ++A9UOps; 2267 return A9UOps; 2268 } else { 2269 // Assume the worst. 2270 return NumRegs; 2271 } 2272 } 2273 } 2274} 2275 2276int 2277ARMBaseInstrInfo::getVLDMDefCycle(const InstrItineraryData *ItinData, 2278 const MCInstrDesc &DefMCID, 2279 unsigned DefClass, 2280 unsigned DefIdx, unsigned DefAlign) const { 2281 int RegNo = (int)(DefIdx+1) - DefMCID.getNumOperands() + 1; 2282 if (RegNo <= 0) 2283 // Def is the address writeback. 2284 return ItinData->getOperandCycle(DefClass, DefIdx); 2285 2286 int DefCycle; 2287 if (Subtarget.isCortexA8()) { 2288 // (regno / 2) + (regno % 2) + 1 2289 DefCycle = RegNo / 2 + 1; 2290 if (RegNo % 2) 2291 ++DefCycle; 2292 } else if (Subtarget.isCortexA9()) { 2293 DefCycle = RegNo; 2294 bool isSLoad = false; 2295 2296 switch (DefMCID.getOpcode()) { 2297 default: break; 2298 case ARM::VLDMSIA: 2299 case ARM::VLDMSIA_UPD: 2300 case ARM::VLDMSDB_UPD: 2301 isSLoad = true; 2302 break; 2303 } 2304 2305 // If there are odd number of 'S' registers or if it's not 64-bit aligned, 2306 // then it takes an extra cycle. 2307 if ((isSLoad && (RegNo % 2)) || DefAlign < 8) 2308 ++DefCycle; 2309 } else { 2310 // Assume the worst. 2311 DefCycle = RegNo + 2; 2312 } 2313 2314 return DefCycle; 2315} 2316 2317int 2318ARMBaseInstrInfo::getLDMDefCycle(const InstrItineraryData *ItinData, 2319 const MCInstrDesc &DefMCID, 2320 unsigned DefClass, 2321 unsigned DefIdx, unsigned DefAlign) const { 2322 int RegNo = (int)(DefIdx+1) - DefMCID.getNumOperands() + 1; 2323 if (RegNo <= 0) 2324 // Def is the address writeback. 2325 return ItinData->getOperandCycle(DefClass, DefIdx); 2326 2327 int DefCycle; 2328 if (Subtarget.isCortexA8()) { 2329 // 4 registers would be issued: 1, 2, 1. 2330 // 5 registers would be issued: 1, 2, 2. 2331 DefCycle = RegNo / 2; 2332 if (DefCycle < 1) 2333 DefCycle = 1; 2334 // Result latency is issue cycle + 2: E2. 2335 DefCycle += 2; 2336 } else if (Subtarget.isCortexA9()) { 2337 DefCycle = (RegNo / 2); 2338 // If there are odd number of registers or if it's not 64-bit aligned, 2339 // then it takes an extra AGU (Address Generation Unit) cycle. 2340 if ((RegNo % 2) || DefAlign < 8) 2341 ++DefCycle; 2342 // Result latency is AGU cycles + 2. 2343 DefCycle += 2; 2344 } else { 2345 // Assume the worst. 2346 DefCycle = RegNo + 2; 2347 } 2348 2349 return DefCycle; 2350} 2351 2352int 2353ARMBaseInstrInfo::getVSTMUseCycle(const InstrItineraryData *ItinData, 2354 const MCInstrDesc &UseMCID, 2355 unsigned UseClass, 2356 unsigned UseIdx, unsigned UseAlign) const { 2357 int RegNo = (int)(UseIdx+1) - UseMCID.getNumOperands() + 1; 2358 if (RegNo <= 0) 2359 return ItinData->getOperandCycle(UseClass, UseIdx); 2360 2361 int UseCycle; 2362 if (Subtarget.isCortexA8()) { 2363 // (regno / 2) + (regno % 2) + 1 2364 UseCycle = RegNo / 2 + 1; 2365 if (RegNo % 2) 2366 ++UseCycle; 2367 } else if (Subtarget.isCortexA9()) { 2368 UseCycle = RegNo; 2369 bool isSStore = false; 2370 2371 switch (UseMCID.getOpcode()) { 2372 default: break; 2373 case ARM::VSTMSIA: 2374 case ARM::VSTMSIA_UPD: 2375 case ARM::VSTMSDB_UPD: 2376 isSStore = true; 2377 break; 2378 } 2379 2380 // If there are odd number of 'S' registers or if it's not 64-bit aligned, 2381 // then it takes an extra cycle. 2382 if ((isSStore && (RegNo % 2)) || UseAlign < 8) 2383 ++UseCycle; 2384 } else { 2385 // Assume the worst. 2386 UseCycle = RegNo + 2; 2387 } 2388 2389 return UseCycle; 2390} 2391 2392int 2393ARMBaseInstrInfo::getSTMUseCycle(const InstrItineraryData *ItinData, 2394 const MCInstrDesc &UseMCID, 2395 unsigned UseClass, 2396 unsigned UseIdx, unsigned UseAlign) const { 2397 int RegNo = (int)(UseIdx+1) - UseMCID.getNumOperands() + 1; 2398 if (RegNo <= 0) 2399 return ItinData->getOperandCycle(UseClass, UseIdx); 2400 2401 int UseCycle; 2402 if (Subtarget.isCortexA8()) { 2403 UseCycle = RegNo / 2; 2404 if (UseCycle < 2) 2405 UseCycle = 2; 2406 // Read in E3. 2407 UseCycle += 2; 2408 } else if (Subtarget.isCortexA9()) { 2409 UseCycle = (RegNo / 2); 2410 // If there are odd number of registers or if it's not 64-bit aligned, 2411 // then it takes an extra AGU (Address Generation Unit) cycle. 2412 if ((RegNo % 2) || UseAlign < 8) 2413 ++UseCycle; 2414 } else { 2415 // Assume the worst. 2416 UseCycle = 1; 2417 } 2418 return UseCycle; 2419} 2420 2421int 2422ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData, 2423 const MCInstrDesc &DefMCID, 2424 unsigned DefIdx, unsigned DefAlign, 2425 const MCInstrDesc &UseMCID, 2426 unsigned UseIdx, unsigned UseAlign) const { 2427 unsigned DefClass = DefMCID.getSchedClass(); 2428 unsigned UseClass = UseMCID.getSchedClass(); 2429 2430 if (DefIdx < DefMCID.getNumDefs() && UseIdx < UseMCID.getNumOperands()) 2431 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx); 2432 2433 // This may be a def / use of a variable_ops instruction, the operand 2434 // latency might be determinable dynamically. Let the target try to 2435 // figure it out. 2436 int DefCycle = -1; 2437 bool LdmBypass = false; 2438 switch (DefMCID.getOpcode()) { 2439 default: 2440 DefCycle = ItinData->getOperandCycle(DefClass, DefIdx); 2441 break; 2442 2443 case ARM::VLDMDIA: 2444 case ARM::VLDMDIA_UPD: 2445 case ARM::VLDMDDB_UPD: 2446 case ARM::VLDMSIA: 2447 case ARM::VLDMSIA_UPD: 2448 case ARM::VLDMSDB_UPD: 2449 DefCycle = getVLDMDefCycle(ItinData, DefMCID, DefClass, DefIdx, DefAlign); 2450 break; 2451 2452 case ARM::LDMIA_RET: 2453 case ARM::LDMIA: 2454 case ARM::LDMDA: 2455 case ARM::LDMDB: 2456 case ARM::LDMIB: 2457 case ARM::LDMIA_UPD: 2458 case ARM::LDMDA_UPD: 2459 case ARM::LDMDB_UPD: 2460 case ARM::LDMIB_UPD: 2461 case ARM::tLDMIA: 2462 case ARM::tLDMIA_UPD: 2463 case ARM::tPUSH: 2464 case ARM::t2LDMIA_RET: 2465 case ARM::t2LDMIA: 2466 case ARM::t2LDMDB: 2467 case ARM::t2LDMIA_UPD: 2468 case ARM::t2LDMDB_UPD: 2469 LdmBypass = 1; 2470 DefCycle = getLDMDefCycle(ItinData, DefMCID, DefClass, DefIdx, DefAlign); 2471 break; 2472 } 2473 2474 if (DefCycle == -1) 2475 // We can't seem to determine the result latency of the def, assume it's 2. 2476 DefCycle = 2; 2477 2478 int UseCycle = -1; 2479 switch (UseMCID.getOpcode()) { 2480 default: 2481 UseCycle = ItinData->getOperandCycle(UseClass, UseIdx); 2482 break; 2483 2484 case ARM::VSTMDIA: 2485 case ARM::VSTMDIA_UPD: 2486 case ARM::VSTMDDB_UPD: 2487 case ARM::VSTMSIA: 2488 case ARM::VSTMSIA_UPD: 2489 case ARM::VSTMSDB_UPD: 2490 UseCycle = getVSTMUseCycle(ItinData, UseMCID, UseClass, UseIdx, UseAlign); 2491 break; 2492 2493 case ARM::STMIA: 2494 case ARM::STMDA: 2495 case ARM::STMDB: 2496 case ARM::STMIB: 2497 case ARM::STMIA_UPD: 2498 case ARM::STMDA_UPD: 2499 case ARM::STMDB_UPD: 2500 case ARM::STMIB_UPD: 2501 case ARM::tSTMIA_UPD: 2502 case ARM::tPOP_RET: 2503 case ARM::tPOP: 2504 case ARM::t2STMIA: 2505 case ARM::t2STMDB: 2506 case ARM::t2STMIA_UPD: 2507 case ARM::t2STMDB_UPD: 2508 UseCycle = getSTMUseCycle(ItinData, UseMCID, UseClass, UseIdx, UseAlign); 2509 break; 2510 } 2511 2512 if (UseCycle == -1) 2513 // Assume it's read in the first stage. 2514 UseCycle = 1; 2515 2516 UseCycle = DefCycle - UseCycle + 1; 2517 if (UseCycle > 0) { 2518 if (LdmBypass) { 2519 // It's a variable_ops instruction so we can't use DefIdx here. Just use 2520 // first def operand. 2521 if (ItinData->hasPipelineForwarding(DefClass, DefMCID.getNumOperands()-1, 2522 UseClass, UseIdx)) 2523 --UseCycle; 2524 } else if (ItinData->hasPipelineForwarding(DefClass, DefIdx, 2525 UseClass, UseIdx)) { 2526 --UseCycle; 2527 } 2528 } 2529 2530 return UseCycle; 2531} 2532 2533static const MachineInstr *getBundledDefMI(const TargetRegisterInfo *TRI, 2534 const MachineInstr *MI, unsigned Reg, 2535 unsigned &DefIdx, unsigned &Dist) { 2536 Dist = 0; 2537 2538 MachineBasicBlock::const_iterator I = MI; ++I; 2539 MachineBasicBlock::const_instr_iterator II = 2540 llvm::prior(I.getInstrIterator()); 2541 assert(II->isInsideBundle() && "Empty bundle?"); 2542 2543 int Idx = -1; 2544 while (II->isInsideBundle()) { 2545 Idx = II->findRegisterDefOperandIdx(Reg, false, true, TRI); 2546 if (Idx != -1) 2547 break; 2548 --II; 2549 ++Dist; 2550 } 2551 2552 assert(Idx != -1 && "Cannot find bundled definition!"); 2553 DefIdx = Idx; 2554 return II; 2555} 2556 2557static const MachineInstr *getBundledUseMI(const TargetRegisterInfo *TRI, 2558 const MachineInstr *MI, unsigned Reg, 2559 unsigned &UseIdx, unsigned &Dist) { 2560 Dist = 0; 2561 2562 MachineBasicBlock::const_instr_iterator II = MI; ++II; 2563 assert(II->isInsideBundle() && "Empty bundle?"); 2564 MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end(); 2565 2566 // FIXME: This doesn't properly handle multiple uses. 2567 int Idx = -1; 2568 while (II != E && II->isInsideBundle()) { 2569 Idx = II->findRegisterUseOperandIdx(Reg, false, TRI); 2570 if (Idx != -1) 2571 break; 2572 if (II->getOpcode() != ARM::t2IT) 2573 ++Dist; 2574 ++II; 2575 } 2576 2577 if (Idx == -1) { 2578 Dist = 0; 2579 return 0; 2580 } 2581 2582 UseIdx = Idx; 2583 return II; 2584} 2585 2586/// Return the number of cycles to add to (or subtract from) the static 2587/// itinerary based on the def opcode and alignment. The caller will ensure that 2588/// adjusted latency is at least one cycle. 2589static int adjustDefLatency(const ARMSubtarget &Subtarget, 2590 const MachineInstr *DefMI, 2591 const MCInstrDesc *DefMCID, unsigned DefAlign) { 2592 int Adjust = 0; 2593 if (Subtarget.isCortexA8() || Subtarget.isCortexA9()) { 2594 // FIXME: Shifter op hack: no shift (i.e. [r +/- r]) or [r + r << 2] 2595 // variants are one cycle cheaper. 2596 switch (DefMCID->getOpcode()) { 2597 default: break; 2598 case ARM::LDRrs: 2599 case ARM::LDRBrs: { 2600 unsigned ShOpVal = DefMI->getOperand(3).getImm(); 2601 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal); 2602 if (ShImm == 0 || 2603 (ShImm == 2 && ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl)) 2604 --Adjust; 2605 break; 2606 } 2607 case ARM::t2LDRs: 2608 case ARM::t2LDRBs: 2609 case ARM::t2LDRHs: 2610 case ARM::t2LDRSHs: { 2611 // Thumb2 mode: lsl only. 2612 unsigned ShAmt = DefMI->getOperand(3).getImm(); 2613 if (ShAmt == 0 || ShAmt == 2) 2614 --Adjust; 2615 break; 2616 } 2617 } 2618 } 2619 2620 if (DefAlign < 8 && Subtarget.isCortexA9()) { 2621 switch (DefMCID->getOpcode()) { 2622 default: break; 2623 case ARM::VLD1q8: 2624 case ARM::VLD1q16: 2625 case ARM::VLD1q32: 2626 case ARM::VLD1q64: 2627 case ARM::VLD1q8wb_fixed: 2628 case ARM::VLD1q16wb_fixed: 2629 case ARM::VLD1q32wb_fixed: 2630 case ARM::VLD1q64wb_fixed: 2631 case ARM::VLD1q8wb_register: 2632 case ARM::VLD1q16wb_register: 2633 case ARM::VLD1q32wb_register: 2634 case ARM::VLD1q64wb_register: 2635 case ARM::VLD2d8: 2636 case ARM::VLD2d16: 2637 case ARM::VLD2d32: 2638 case ARM::VLD2q8: 2639 case ARM::VLD2q16: 2640 case ARM::VLD2q32: 2641 case ARM::VLD2d8wb_fixed: 2642 case ARM::VLD2d16wb_fixed: 2643 case ARM::VLD2d32wb_fixed: 2644 case ARM::VLD2q8wb_fixed: 2645 case ARM::VLD2q16wb_fixed: 2646 case ARM::VLD2q32wb_fixed: 2647 case ARM::VLD2d8wb_register: 2648 case ARM::VLD2d16wb_register: 2649 case ARM::VLD2d32wb_register: 2650 case ARM::VLD2q8wb_register: 2651 case ARM::VLD2q16wb_register: 2652 case ARM::VLD2q32wb_register: 2653 case ARM::VLD3d8: 2654 case ARM::VLD3d16: 2655 case ARM::VLD3d32: 2656 case ARM::VLD1d64T: 2657 case ARM::VLD3d8_UPD: 2658 case ARM::VLD3d16_UPD: 2659 case ARM::VLD3d32_UPD: 2660 case ARM::VLD1d64Twb_fixed: 2661 case ARM::VLD1d64Twb_register: 2662 case ARM::VLD3q8_UPD: 2663 case ARM::VLD3q16_UPD: 2664 case ARM::VLD3q32_UPD: 2665 case ARM::VLD4d8: 2666 case ARM::VLD4d16: 2667 case ARM::VLD4d32: 2668 case ARM::VLD1d64Q: 2669 case ARM::VLD4d8_UPD: 2670 case ARM::VLD4d16_UPD: 2671 case ARM::VLD4d32_UPD: 2672 case ARM::VLD1d64Qwb_fixed: 2673 case ARM::VLD1d64Qwb_register: 2674 case ARM::VLD4q8_UPD: 2675 case ARM::VLD4q16_UPD: 2676 case ARM::VLD4q32_UPD: 2677 case ARM::VLD1DUPq8: 2678 case ARM::VLD1DUPq16: 2679 case ARM::VLD1DUPq32: 2680 case ARM::VLD1DUPq8wb_fixed: 2681 case ARM::VLD1DUPq16wb_fixed: 2682 case ARM::VLD1DUPq32wb_fixed: 2683 case ARM::VLD1DUPq8wb_register: 2684 case ARM::VLD1DUPq16wb_register: 2685 case ARM::VLD1DUPq32wb_register: 2686 case ARM::VLD2DUPd8: 2687 case ARM::VLD2DUPd16: 2688 case ARM::VLD2DUPd32: 2689 case ARM::VLD2DUPd8wb_fixed: 2690 case ARM::VLD2DUPd16wb_fixed: 2691 case ARM::VLD2DUPd32wb_fixed: 2692 case ARM::VLD2DUPd8wb_register: 2693 case ARM::VLD2DUPd16wb_register: 2694 case ARM::VLD2DUPd32wb_register: 2695 case ARM::VLD4DUPd8: 2696 case ARM::VLD4DUPd16: 2697 case ARM::VLD4DUPd32: 2698 case ARM::VLD4DUPd8_UPD: 2699 case ARM::VLD4DUPd16_UPD: 2700 case ARM::VLD4DUPd32_UPD: 2701 case ARM::VLD1LNd8: 2702 case ARM::VLD1LNd16: 2703 case ARM::VLD1LNd32: 2704 case ARM::VLD1LNd8_UPD: 2705 case ARM::VLD1LNd16_UPD: 2706 case ARM::VLD1LNd32_UPD: 2707 case ARM::VLD2LNd8: 2708 case ARM::VLD2LNd16: 2709 case ARM::VLD2LNd32: 2710 case ARM::VLD2LNq16: 2711 case ARM::VLD2LNq32: 2712 case ARM::VLD2LNd8_UPD: 2713 case ARM::VLD2LNd16_UPD: 2714 case ARM::VLD2LNd32_UPD: 2715 case ARM::VLD2LNq16_UPD: 2716 case ARM::VLD2LNq32_UPD: 2717 case ARM::VLD4LNd8: 2718 case ARM::VLD4LNd16: 2719 case ARM::VLD4LNd32: 2720 case ARM::VLD4LNq16: 2721 case ARM::VLD4LNq32: 2722 case ARM::VLD4LNd8_UPD: 2723 case ARM::VLD4LNd16_UPD: 2724 case ARM::VLD4LNd32_UPD: 2725 case ARM::VLD4LNq16_UPD: 2726 case ARM::VLD4LNq32_UPD: 2727 // If the address is not 64-bit aligned, the latencies of these 2728 // instructions increases by one. 2729 ++Adjust; 2730 break; 2731 } 2732 } 2733 return Adjust; 2734} 2735 2736 2737 2738int 2739ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData, 2740 const MachineInstr *DefMI, unsigned DefIdx, 2741 const MachineInstr *UseMI, 2742 unsigned UseIdx) const { 2743 // No operand latency. The caller may fall back to getInstrLatency. 2744 if (!ItinData || ItinData->isEmpty()) 2745 return -1; 2746 2747 const MachineOperand &DefMO = DefMI->getOperand(DefIdx); 2748 unsigned Reg = DefMO.getReg(); 2749 const MCInstrDesc *DefMCID = &DefMI->getDesc(); 2750 const MCInstrDesc *UseMCID = &UseMI->getDesc(); 2751 2752 unsigned DefAdj = 0; 2753 if (DefMI->isBundle()) { 2754 DefMI = getBundledDefMI(&getRegisterInfo(), DefMI, Reg, DefIdx, DefAdj); 2755 DefMCID = &DefMI->getDesc(); 2756 } 2757 if (DefMI->isCopyLike() || DefMI->isInsertSubreg() || 2758 DefMI->isRegSequence() || DefMI->isImplicitDef()) { 2759 return 1; 2760 } 2761 2762 unsigned UseAdj = 0; 2763 if (UseMI->isBundle()) { 2764 unsigned NewUseIdx; 2765 const MachineInstr *NewUseMI = getBundledUseMI(&getRegisterInfo(), UseMI, 2766 Reg, NewUseIdx, UseAdj); 2767 if (!NewUseMI) 2768 return -1; 2769 2770 UseMI = NewUseMI; 2771 UseIdx = NewUseIdx; 2772 UseMCID = &UseMI->getDesc(); 2773 } 2774 2775 if (Reg == ARM::CPSR) { 2776 if (DefMI->getOpcode() == ARM::FMSTAT) { 2777 // fpscr -> cpsr stalls over 20 cycles on A8 (and earlier?) 2778 return Subtarget.isCortexA9() ? 1 : 20; 2779 } 2780 2781 // CPSR set and branch can be paired in the same cycle. 2782 if (UseMI->isBranch()) 2783 return 0; 2784 2785 // Otherwise it takes the instruction latency (generally one). 2786 unsigned Latency = getInstrLatency(ItinData, DefMI); 2787 2788 // For Thumb2 and -Os, prefer scheduling CPSR setting instruction close to 2789 // its uses. Instructions which are otherwise scheduled between them may 2790 // incur a code size penalty (not able to use the CPSR setting 16-bit 2791 // instructions). 2792 if (Latency > 0 && Subtarget.isThumb2()) { 2793 const MachineFunction *MF = DefMI->getParent()->getParent(); 2794 if (MF->getFunction()->hasFnAttr(Attribute::OptimizeForSize)) 2795 --Latency; 2796 } 2797 return Latency; 2798 } 2799 2800 if (DefMO.isImplicit() || UseMI->getOperand(UseIdx).isImplicit()) 2801 return -1; 2802 2803 unsigned DefAlign = DefMI->hasOneMemOperand() 2804 ? (*DefMI->memoperands_begin())->getAlignment() : 0; 2805 unsigned UseAlign = UseMI->hasOneMemOperand() 2806 ? (*UseMI->memoperands_begin())->getAlignment() : 0; 2807 2808 // Get the itinerary's latency if possible, and handle variable_ops. 2809 int Latency = getOperandLatency(ItinData, *DefMCID, DefIdx, DefAlign, 2810 *UseMCID, UseIdx, UseAlign); 2811 // Unable to find operand latency. The caller may resort to getInstrLatency. 2812 if (Latency < 0) 2813 return Latency; 2814 2815 // Adjust for IT block position. 2816 int Adj = DefAdj + UseAdj; 2817 2818 // Adjust for dynamic def-side opcode variants not captured by the itinerary. 2819 Adj += adjustDefLatency(Subtarget, DefMI, DefMCID, DefAlign); 2820 if (Adj >= 0 || (int)Latency > -Adj) { 2821 return Latency + Adj; 2822 } 2823 // Return the itinerary latency, which may be zero but not less than zero. 2824 return Latency; 2825} 2826 2827int 2828ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData, 2829 SDNode *DefNode, unsigned DefIdx, 2830 SDNode *UseNode, unsigned UseIdx) const { 2831 if (!DefNode->isMachineOpcode()) 2832 return 1; 2833 2834 const MCInstrDesc &DefMCID = get(DefNode->getMachineOpcode()); 2835 2836 if (isZeroCost(DefMCID.Opcode)) 2837 return 0; 2838 2839 if (!ItinData || ItinData->isEmpty()) 2840 return DefMCID.mayLoad() ? 3 : 1; 2841 2842 if (!UseNode->isMachineOpcode()) { 2843 int Latency = ItinData->getOperandCycle(DefMCID.getSchedClass(), DefIdx); 2844 if (Subtarget.isCortexA9()) 2845 return Latency <= 2 ? 1 : Latency - 1; 2846 else 2847 return Latency <= 3 ? 1 : Latency - 2; 2848 } 2849 2850 const MCInstrDesc &UseMCID = get(UseNode->getMachineOpcode()); 2851 const MachineSDNode *DefMN = dyn_cast<MachineSDNode>(DefNode); 2852 unsigned DefAlign = !DefMN->memoperands_empty() 2853 ? (*DefMN->memoperands_begin())->getAlignment() : 0; 2854 const MachineSDNode *UseMN = dyn_cast<MachineSDNode>(UseNode); 2855 unsigned UseAlign = !UseMN->memoperands_empty() 2856 ? (*UseMN->memoperands_begin())->getAlignment() : 0; 2857 int Latency = getOperandLatency(ItinData, DefMCID, DefIdx, DefAlign, 2858 UseMCID, UseIdx, UseAlign); 2859 2860 if (Latency > 1 && 2861 (Subtarget.isCortexA8() || Subtarget.isCortexA9())) { 2862 // FIXME: Shifter op hack: no shift (i.e. [r +/- r]) or [r + r << 2] 2863 // variants are one cycle cheaper. 2864 switch (DefMCID.getOpcode()) { 2865 default: break; 2866 case ARM::LDRrs: 2867 case ARM::LDRBrs: { 2868 unsigned ShOpVal = 2869 cast<ConstantSDNode>(DefNode->getOperand(2))->getZExtValue(); 2870 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal); 2871 if (ShImm == 0 || 2872 (ShImm == 2 && ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl)) 2873 --Latency; 2874 break; 2875 } 2876 case ARM::t2LDRs: 2877 case ARM::t2LDRBs: 2878 case ARM::t2LDRHs: 2879 case ARM::t2LDRSHs: { 2880 // Thumb2 mode: lsl only. 2881 unsigned ShAmt = 2882 cast<ConstantSDNode>(DefNode->getOperand(2))->getZExtValue(); 2883 if (ShAmt == 0 || ShAmt == 2) 2884 --Latency; 2885 break; 2886 } 2887 } 2888 } 2889 2890 if (DefAlign < 8 && Subtarget.isCortexA9()) 2891 switch (DefMCID.getOpcode()) { 2892 default: break; 2893 case ARM::VLD1q8: 2894 case ARM::VLD1q16: 2895 case ARM::VLD1q32: 2896 case ARM::VLD1q64: 2897 case ARM::VLD1q8wb_register: 2898 case ARM::VLD1q16wb_register: 2899 case ARM::VLD1q32wb_register: 2900 case ARM::VLD1q64wb_register: 2901 case ARM::VLD1q8wb_fixed: 2902 case ARM::VLD1q16wb_fixed: 2903 case ARM::VLD1q32wb_fixed: 2904 case ARM::VLD1q64wb_fixed: 2905 case ARM::VLD2d8: 2906 case ARM::VLD2d16: 2907 case ARM::VLD2d32: 2908 case ARM::VLD2q8Pseudo: 2909 case ARM::VLD2q16Pseudo: 2910 case ARM::VLD2q32Pseudo: 2911 case ARM::VLD2d8wb_fixed: 2912 case ARM::VLD2d16wb_fixed: 2913 case ARM::VLD2d32wb_fixed: 2914 case ARM::VLD2q8PseudoWB_fixed: 2915 case ARM::VLD2q16PseudoWB_fixed: 2916 case ARM::VLD2q32PseudoWB_fixed: 2917 case ARM::VLD2d8wb_register: 2918 case ARM::VLD2d16wb_register: 2919 case ARM::VLD2d32wb_register: 2920 case ARM::VLD2q8PseudoWB_register: 2921 case ARM::VLD2q16PseudoWB_register: 2922 case ARM::VLD2q32PseudoWB_register: 2923 case ARM::VLD3d8Pseudo: 2924 case ARM::VLD3d16Pseudo: 2925 case ARM::VLD3d32Pseudo: 2926 case ARM::VLD1d64TPseudo: 2927 case ARM::VLD3d8Pseudo_UPD: 2928 case ARM::VLD3d16Pseudo_UPD: 2929 case ARM::VLD3d32Pseudo_UPD: 2930 case ARM::VLD3q8Pseudo_UPD: 2931 case ARM::VLD3q16Pseudo_UPD: 2932 case ARM::VLD3q32Pseudo_UPD: 2933 case ARM::VLD3q8oddPseudo: 2934 case ARM::VLD3q16oddPseudo: 2935 case ARM::VLD3q32oddPseudo: 2936 case ARM::VLD3q8oddPseudo_UPD: 2937 case ARM::VLD3q16oddPseudo_UPD: 2938 case ARM::VLD3q32oddPseudo_UPD: 2939 case ARM::VLD4d8Pseudo: 2940 case ARM::VLD4d16Pseudo: 2941 case ARM::VLD4d32Pseudo: 2942 case ARM::VLD1d64QPseudo: 2943 case ARM::VLD4d8Pseudo_UPD: 2944 case ARM::VLD4d16Pseudo_UPD: 2945 case ARM::VLD4d32Pseudo_UPD: 2946 case ARM::VLD4q8Pseudo_UPD: 2947 case ARM::VLD4q16Pseudo_UPD: 2948 case ARM::VLD4q32Pseudo_UPD: 2949 case ARM::VLD4q8oddPseudo: 2950 case ARM::VLD4q16oddPseudo: 2951 case ARM::VLD4q32oddPseudo: 2952 case ARM::VLD4q8oddPseudo_UPD: 2953 case ARM::VLD4q16oddPseudo_UPD: 2954 case ARM::VLD4q32oddPseudo_UPD: 2955 case ARM::VLD1DUPq8: 2956 case ARM::VLD1DUPq16: 2957 case ARM::VLD1DUPq32: 2958 case ARM::VLD1DUPq8wb_fixed: 2959 case ARM::VLD1DUPq16wb_fixed: 2960 case ARM::VLD1DUPq32wb_fixed: 2961 case ARM::VLD1DUPq8wb_register: 2962 case ARM::VLD1DUPq16wb_register: 2963 case ARM::VLD1DUPq32wb_register: 2964 case ARM::VLD2DUPd8: 2965 case ARM::VLD2DUPd16: 2966 case ARM::VLD2DUPd32: 2967 case ARM::VLD2DUPd8wb_fixed: 2968 case ARM::VLD2DUPd16wb_fixed: 2969 case ARM::VLD2DUPd32wb_fixed: 2970 case ARM::VLD2DUPd8wb_register: 2971 case ARM::VLD2DUPd16wb_register: 2972 case ARM::VLD2DUPd32wb_register: 2973 case ARM::VLD4DUPd8Pseudo: 2974 case ARM::VLD4DUPd16Pseudo: 2975 case ARM::VLD4DUPd32Pseudo: 2976 case ARM::VLD4DUPd8Pseudo_UPD: 2977 case ARM::VLD4DUPd16Pseudo_UPD: 2978 case ARM::VLD4DUPd32Pseudo_UPD: 2979 case ARM::VLD1LNq8Pseudo: 2980 case ARM::VLD1LNq16Pseudo: 2981 case ARM::VLD1LNq32Pseudo: 2982 case ARM::VLD1LNq8Pseudo_UPD: 2983 case ARM::VLD1LNq16Pseudo_UPD: 2984 case ARM::VLD1LNq32Pseudo_UPD: 2985 case ARM::VLD2LNd8Pseudo: 2986 case ARM::VLD2LNd16Pseudo: 2987 case ARM::VLD2LNd32Pseudo: 2988 case ARM::VLD2LNq16Pseudo: 2989 case ARM::VLD2LNq32Pseudo: 2990 case ARM::VLD2LNd8Pseudo_UPD: 2991 case ARM::VLD2LNd16Pseudo_UPD: 2992 case ARM::VLD2LNd32Pseudo_UPD: 2993 case ARM::VLD2LNq16Pseudo_UPD: 2994 case ARM::VLD2LNq32Pseudo_UPD: 2995 case ARM::VLD4LNd8Pseudo: 2996 case ARM::VLD4LNd16Pseudo: 2997 case ARM::VLD4LNd32Pseudo: 2998 case ARM::VLD4LNq16Pseudo: 2999 case ARM::VLD4LNq32Pseudo: 3000 case ARM::VLD4LNd8Pseudo_UPD: 3001 case ARM::VLD4LNd16Pseudo_UPD: 3002 case ARM::VLD4LNd32Pseudo_UPD: 3003 case ARM::VLD4LNq16Pseudo_UPD: 3004 case ARM::VLD4LNq32Pseudo_UPD: 3005 // If the address is not 64-bit aligned, the latencies of these 3006 // instructions increases by one. 3007 ++Latency; 3008 break; 3009 } 3010 3011 return Latency; 3012} 3013 3014unsigned 3015ARMBaseInstrInfo::getOutputLatency(const InstrItineraryData *ItinData, 3016 const MachineInstr *DefMI, unsigned DefIdx, 3017 const MachineInstr *DepMI) const { 3018 unsigned Reg = DefMI->getOperand(DefIdx).getReg(); 3019 if (DepMI->readsRegister(Reg, &getRegisterInfo()) || !isPredicated(DepMI)) 3020 return 1; 3021 3022 // If the second MI is predicated, then there is an implicit use dependency. 3023 return getInstrLatency(ItinData, DefMI); 3024} 3025 3026unsigned ARMBaseInstrInfo::getInstrLatency(const InstrItineraryData *ItinData, 3027 const MachineInstr *MI, 3028 unsigned *PredCost) const { 3029 if (MI->isCopyLike() || MI->isInsertSubreg() || 3030 MI->isRegSequence() || MI->isImplicitDef()) 3031 return 1; 3032 3033 // An instruction scheduler typically runs on unbundled instructions, however 3034 // other passes may query the latency of a bundled instruction. 3035 if (MI->isBundle()) { 3036 unsigned Latency = 0; 3037 MachineBasicBlock::const_instr_iterator I = MI; 3038 MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end(); 3039 while (++I != E && I->isInsideBundle()) { 3040 if (I->getOpcode() != ARM::t2IT) 3041 Latency += getInstrLatency(ItinData, I, PredCost); 3042 } 3043 return Latency; 3044 } 3045 3046 const MCInstrDesc &MCID = MI->getDesc(); 3047 if (PredCost && (MCID.isCall() || MCID.hasImplicitDefOfPhysReg(ARM::CPSR))) { 3048 // When predicated, CPSR is an additional source operand for CPSR updating 3049 // instructions, this apparently increases their latencies. 3050 *PredCost = 1; 3051 } 3052 // Be sure to call getStageLatency for an empty itinerary in case it has a 3053 // valid MinLatency property. 3054 if (!ItinData) 3055 return MI->mayLoad() ? 3 : 1; 3056 3057 unsigned Class = MCID.getSchedClass(); 3058 3059 // For instructions with variable uops, use uops as latency. 3060 if (!ItinData->isEmpty() && ItinData->getNumMicroOps(Class) < 0) { 3061 dbgs() << "UOPS " << getNumMicroOps(ItinData, MI) << " " << *MI << '\n'; 3062 return getNumMicroOps(ItinData, MI); 3063 } 3064 // For the common case, fall back on the itinerary's latency. 3065 unsigned Latency = ItinData->getStageLatency(Class); 3066 3067 // Adjust for dynamic def-side opcode variants not captured by the itinerary. 3068 unsigned DefAlign = MI->hasOneMemOperand() 3069 ? (*MI->memoperands_begin())->getAlignment() : 0; 3070 int Adj = adjustDefLatency(Subtarget, MI, &MCID, DefAlign); 3071 if (Adj >= 0 || (int)Latency > -Adj) { 3072 return Latency + Adj; 3073 } 3074 return Latency; 3075} 3076 3077int ARMBaseInstrInfo::getInstrLatency(const InstrItineraryData *ItinData, 3078 SDNode *Node) const { 3079 if (!Node->isMachineOpcode()) 3080 return 1; 3081 3082 if (!ItinData || ItinData->isEmpty()) 3083 return 1; 3084 3085 unsigned Opcode = Node->getMachineOpcode(); 3086 switch (Opcode) { 3087 default: 3088 return ItinData->getStageLatency(get(Opcode).getSchedClass()); 3089 case ARM::VLDMQIA: 3090 case ARM::VSTMQIA: 3091 return 2; 3092 } 3093} 3094 3095bool ARMBaseInstrInfo:: 3096hasHighOperandLatency(const InstrItineraryData *ItinData, 3097 const MachineRegisterInfo *MRI, 3098 const MachineInstr *DefMI, unsigned DefIdx, 3099 const MachineInstr *UseMI, unsigned UseIdx) const { 3100 unsigned DDomain = DefMI->getDesc().TSFlags & ARMII::DomainMask; 3101 unsigned UDomain = UseMI->getDesc().TSFlags & ARMII::DomainMask; 3102 if (Subtarget.isCortexA8() && 3103 (DDomain == ARMII::DomainVFP || UDomain == ARMII::DomainVFP)) 3104 // CortexA8 VFP instructions are not pipelined. 3105 return true; 3106 3107 // Hoist VFP / NEON instructions with 4 or higher latency. 3108 int Latency = computeOperandLatency(ItinData, DefMI, DefIdx, UseMI, UseIdx, 3109 /*FindMin=*/false); 3110 if (Latency < 0) 3111 Latency = getInstrLatency(ItinData, DefMI); 3112 if (Latency <= 3) 3113 return false; 3114 return DDomain == ARMII::DomainVFP || DDomain == ARMII::DomainNEON || 3115 UDomain == ARMII::DomainVFP || UDomain == ARMII::DomainNEON; 3116} 3117 3118bool ARMBaseInstrInfo:: 3119hasLowDefLatency(const InstrItineraryData *ItinData, 3120 const MachineInstr *DefMI, unsigned DefIdx) const { 3121 if (!ItinData || ItinData->isEmpty()) 3122 return false; 3123 3124 unsigned DDomain = DefMI->getDesc().TSFlags & ARMII::DomainMask; 3125 if (DDomain == ARMII::DomainGeneral) { 3126 unsigned DefClass = DefMI->getDesc().getSchedClass(); 3127 int DefCycle = ItinData->getOperandCycle(DefClass, DefIdx); 3128 return (DefCycle != -1 && DefCycle <= 2); 3129 } 3130 return false; 3131} 3132 3133bool ARMBaseInstrInfo::verifyInstruction(const MachineInstr *MI, 3134 StringRef &ErrInfo) const { 3135 if (convertAddSubFlagsOpcode(MI->getOpcode())) { 3136 ErrInfo = "Pseudo flag setting opcodes only exist in Selection DAG"; 3137 return false; 3138 } 3139 return true; 3140} 3141 3142bool 3143ARMBaseInstrInfo::isFpMLxInstruction(unsigned Opcode, unsigned &MulOpc, 3144 unsigned &AddSubOpc, 3145 bool &NegAcc, bool &HasLane) const { 3146 DenseMap<unsigned, unsigned>::const_iterator I = MLxEntryMap.find(Opcode); 3147 if (I == MLxEntryMap.end()) 3148 return false; 3149 3150 const ARM_MLxEntry &Entry = ARM_MLxTable[I->second]; 3151 MulOpc = Entry.MulOpc; 3152 AddSubOpc = Entry.AddSubOpc; 3153 NegAcc = Entry.NegAcc; 3154 HasLane = Entry.HasLane; 3155 return true; 3156} 3157 3158//===----------------------------------------------------------------------===// 3159// Execution domains. 3160//===----------------------------------------------------------------------===// 3161// 3162// Some instructions go down the NEON pipeline, some go down the VFP pipeline, 3163// and some can go down both. The vmov instructions go down the VFP pipeline, 3164// but they can be changed to vorr equivalents that are executed by the NEON 3165// pipeline. 3166// 3167// We use the following execution domain numbering: 3168// 3169enum ARMExeDomain { 3170 ExeGeneric = 0, 3171 ExeVFP = 1, 3172 ExeNEON = 2 3173}; 3174// 3175// Also see ARMInstrFormats.td and Domain* enums in ARMBaseInfo.h 3176// 3177std::pair<uint16_t, uint16_t> 3178ARMBaseInstrInfo::getExecutionDomain(const MachineInstr *MI) const { 3179 // VMOVD is a VFP instruction, but can be changed to NEON if it isn't 3180 // predicated. 3181 if (MI->getOpcode() == ARM::VMOVD && !isPredicated(MI)) 3182 return std::make_pair(ExeVFP, (1<<ExeVFP) | (1<<ExeNEON)); 3183 3184 // No other instructions can be swizzled, so just determine their domain. 3185 unsigned Domain = MI->getDesc().TSFlags & ARMII::DomainMask; 3186 3187 if (Domain & ARMII::DomainNEON) 3188 return std::make_pair(ExeNEON, 0); 3189 3190 // Certain instructions can go either way on Cortex-A8. 3191 // Treat them as NEON instructions. 3192 if ((Domain & ARMII::DomainNEONA8) && Subtarget.isCortexA8()) 3193 return std::make_pair(ExeNEON, 0); 3194 3195 if (Domain & ARMII::DomainVFP) 3196 return std::make_pair(ExeVFP, 0); 3197 3198 return std::make_pair(ExeGeneric, 0); 3199} 3200 3201void 3202ARMBaseInstrInfo::setExecutionDomain(MachineInstr *MI, unsigned Domain) const { 3203 // We only know how to change VMOVD into VORR. 3204 assert(MI->getOpcode() == ARM::VMOVD && "Can only swizzle VMOVD"); 3205 if (Domain != ExeNEON) 3206 return; 3207 3208 // Zap the predicate operands. 3209 assert(!isPredicated(MI) && "Cannot predicate a VORRd"); 3210 MI->RemoveOperand(3); 3211 MI->RemoveOperand(2); 3212 3213 // Change to a VORRd which requires two identical use operands. 3214 MI->setDesc(get(ARM::VORRd)); 3215 3216 // Add the extra source operand and new predicates. 3217 // This will go before any implicit ops. 3218 AddDefaultPred(MachineInstrBuilder(MI).addOperand(MI->getOperand(1))); 3219} 3220 3221bool ARMBaseInstrInfo::hasNOP() const { 3222 return (Subtarget.getFeatureBits() & ARM::HasV6T2Ops) != 0; 3223} 3224