ARMBaseInstrInfo.cpp revision 86050dc8cc0aaea8c9dfeb89de02cafbd7f48d92 
1//===- ARMBaseInstrInfo.cpp - ARM Instruction Information -------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the Base ARM implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "ARMBaseInstrInfo.h"
15#include "ARM.h"
16#include "ARMAddressingModes.h"
17#include "ARMConstantPoolValue.h"
18#include "ARMGenInstrInfo.inc"
19#include "ARMMachineFunctionInfo.h"
20#include "ARMRegisterInfo.h"
21#include "llvm/Constants.h"
22#include "llvm/Function.h"
23#include "llvm/GlobalValue.h"
24#include "llvm/ADT/STLExtras.h"
25#include "llvm/CodeGen/LiveVariables.h"
26#include "llvm/CodeGen/MachineConstantPool.h"
27#include "llvm/CodeGen/MachineFrameInfo.h"
28#include "llvm/CodeGen/MachineInstrBuilder.h"
29#include "llvm/CodeGen/MachineJumpTableInfo.h"
30#include "llvm/CodeGen/MachineMemOperand.h"
31#include "llvm/CodeGen/MachineRegisterInfo.h"
32#include "llvm/CodeGen/PseudoSourceValue.h"
33#include "llvm/MC/MCAsmInfo.h"
34#include "llvm/Support/CommandLine.h"
35#include "llvm/Support/Debug.h"
36#include "llvm/Support/ErrorHandling.h"
37using namespace llvm;
38
39static cl::opt<bool>
40EnableARM3Addr("enable-arm-3-addr-conv", cl::Hidden,
41               cl::desc("Enable ARM 2-addr to 3-addr conv"));
42
43ARMBaseInstrInfo::ARMBaseInstrInfo(const ARMSubtarget& STI)
44  : TargetInstrInfoImpl(ARMInsts, array_lengthof(ARMInsts)),
45    Subtarget(STI) {
46}
47
48MachineInstr *
49ARMBaseInstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
50                                        MachineBasicBlock::iterator &MBBI,
51                                        LiveVariables *LV) const {
52  // FIXME: Thumb2 support.
53
54  if (!EnableARM3Addr)
55    return NULL;
56
57  MachineInstr *MI = MBBI;
58  MachineFunction &MF = *MI->getParent()->getParent();
59  uint64_t TSFlags = MI->getDesc().TSFlags;
60  bool isPre = false;
61  switch ((TSFlags & ARMII::IndexModeMask) >> ARMII::IndexModeShift) {
62  default: return NULL;
63  case ARMII::IndexModePre:
64    isPre = true;
65    break;
66  case ARMII::IndexModePost:
67    break;
68  }
69
70  // Try splitting an indexed load/store to an un-indexed one plus an add/sub
71  // operation.
72  unsigned MemOpc = getUnindexedOpcode(MI->getOpcode());
73  if (MemOpc == 0)
74    return NULL;
75
76  MachineInstr *UpdateMI = NULL;
77  MachineInstr *MemMI = NULL;
78  unsigned AddrMode = (TSFlags & ARMII::AddrModeMask);
79  const TargetInstrDesc &TID = MI->getDesc();
80  unsigned NumOps = TID.getNumOperands();
81  bool isLoad = !TID.mayStore();
82  const MachineOperand &WB = isLoad ? MI->getOperand(1) : MI->getOperand(0);
83  const MachineOperand &Base = MI->getOperand(2);
84  const MachineOperand &Offset = MI->getOperand(NumOps-3);
85  unsigned WBReg = WB.getReg();
86  unsigned BaseReg = Base.getReg();
87  unsigned OffReg = Offset.getReg();
88  unsigned OffImm = MI->getOperand(NumOps-2).getImm();
89  ARMCC::CondCodes Pred = (ARMCC::CondCodes)MI->getOperand(NumOps-1).getImm();
90  switch (AddrMode) {
91  default:
92    assert(false && "Unknown indexed op!");
93    return NULL;
94  case ARMII::AddrMode2: {
95    bool isSub = ARM_AM::getAM2Op(OffImm) == ARM_AM::sub;
96    unsigned Amt = ARM_AM::getAM2Offset(OffImm);
97    if (OffReg == 0) {
98      if (ARM_AM::getSOImmVal(Amt) == -1)
99        // Can't encode it in a so_imm operand. This transformation will
100        // add more than 1 instruction. Abandon!
101        return NULL;
102      UpdateMI = BuildMI(MF, MI->getDebugLoc(),
103                         get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
104        .addReg(BaseReg).addImm(Amt)
105        .addImm(Pred).addReg(0).addReg(0);
106    } else if (Amt != 0) {
107      ARM_AM::ShiftOpc ShOpc = ARM_AM::getAM2ShiftOpc(OffImm);
108      unsigned SOOpc = ARM_AM::getSORegOpc(ShOpc, Amt);
109      UpdateMI = BuildMI(MF, MI->getDebugLoc(),
110                         get(isSub ? ARM::SUBrs : ARM::ADDrs), WBReg)
111        .addReg(BaseReg).addReg(OffReg).addReg(0).addImm(SOOpc)
112        .addImm(Pred).addReg(0).addReg(0);
113    } else
114      UpdateMI = BuildMI(MF, MI->getDebugLoc(),
115                         get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
116        .addReg(BaseReg).addReg(OffReg)
117        .addImm(Pred).addReg(0).addReg(0);
118    break;
119  }
120  case ARMII::AddrMode3 : {
121    bool isSub = ARM_AM::getAM3Op(OffImm) == ARM_AM::sub;
122    unsigned Amt = ARM_AM::getAM3Offset(OffImm);
123    if (OffReg == 0)
124      // Immediate is 8-bits. It's guaranteed to fit in a so_imm operand.
125      UpdateMI = BuildMI(MF, MI->getDebugLoc(),
126                         get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
127        .addReg(BaseReg).addImm(Amt)
128        .addImm(Pred).addReg(0).addReg(0);
129    else
130      UpdateMI = BuildMI(MF, MI->getDebugLoc(),
131                         get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
132        .addReg(BaseReg).addReg(OffReg)
133        .addImm(Pred).addReg(0).addReg(0);
134    break;
135  }
136  }
137
138  std::vector<MachineInstr*> NewMIs;
139  if (isPre) {
140    if (isLoad)
141      MemMI = BuildMI(MF, MI->getDebugLoc(),
142                      get(MemOpc), MI->getOperand(0).getReg())
143        .addReg(WBReg).addReg(0).addImm(0).addImm(Pred);
144    else
145      MemMI = BuildMI(MF, MI->getDebugLoc(),
146                      get(MemOpc)).addReg(MI->getOperand(1).getReg())
147        .addReg(WBReg).addReg(0).addImm(0).addImm(Pred);
148    NewMIs.push_back(MemMI);
149    NewMIs.push_back(UpdateMI);
150  } else {
151    if (isLoad)
152      MemMI = BuildMI(MF, MI->getDebugLoc(),
153                      get(MemOpc), MI->getOperand(0).getReg())
154        .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred);
155    else
156      MemMI = BuildMI(MF, MI->getDebugLoc(),
157                      get(MemOpc)).addReg(MI->getOperand(1).getReg())
158        .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred);
159    if (WB.isDead())
160      UpdateMI->getOperand(0).setIsDead();
161    NewMIs.push_back(UpdateMI);
162    NewMIs.push_back(MemMI);
163  }
164
165  // Transfer LiveVariables states, kill / dead info.
166  if (LV) {
167    for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
168      MachineOperand &MO = MI->getOperand(i);
169      if (MO.isReg() && MO.getReg() &&
170          TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
171        unsigned Reg = MO.getReg();
172
173        LiveVariables::VarInfo &VI = LV->getVarInfo(Reg);
174        if (MO.isDef()) {
175          MachineInstr *NewMI = (Reg == WBReg) ? UpdateMI : MemMI;
176          if (MO.isDead())
177            LV->addVirtualRegisterDead(Reg, NewMI);
178        }
179        if (MO.isUse() && MO.isKill()) {
180          for (unsigned j = 0; j < 2; ++j) {
181            // Look at the two new MI's in reverse order.
182            MachineInstr *NewMI = NewMIs[j];
183            if (!NewMI->readsRegister(Reg))
184              continue;
185            LV->addVirtualRegisterKilled(Reg, NewMI);
186            if (VI.removeKill(MI))
187              VI.Kills.push_back(NewMI);
188            break;
189          }
190        }
191      }
192    }
193  }
194
195  MFI->insert(MBBI, NewMIs[1]);
196  MFI->insert(MBBI, NewMIs[0]);
197  return NewMIs[0];
198}
199
200bool
201ARMBaseInstrInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
202                                        MachineBasicBlock::iterator MI,
203                                        const std::vector<CalleeSavedInfo> &CSI,
204                                        const TargetRegisterInfo *TRI) const {
205  if (CSI.empty())
206    return false;
207
208  DebugLoc DL;
209  if (MI != MBB.end()) DL = MI->getDebugLoc();
210
211  for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
212    unsigned Reg = CSI[i].getReg();
213    bool isKill = true;
214
215    // Add the callee-saved register as live-in unless it's LR and
216    // @llvm.returnaddress is called. If LR is returned for @llvm.returnaddress
217    // then it's already added to the function and entry block live-in sets.
218    if (Reg == ARM::LR) {
219      MachineFunction &MF = *MBB.getParent();
220      if (MF.getFrameInfo()->isReturnAddressTaken() &&
221          MF.getRegInfo().isLiveIn(Reg))
222        isKill = false;
223    }
224
225    if (isKill)
226      MBB.addLiveIn(Reg);
227
228    // Insert the spill to the stack frame. The register is killed at the spill
229    //
230    const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
231    storeRegToStackSlot(MBB, MI, Reg, isKill,
232                        CSI[i].getFrameIdx(), RC, TRI);
233  }
234  return true;
235}
236
237// Branch analysis.
238bool
239ARMBaseInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
240                                MachineBasicBlock *&FBB,
241                                SmallVectorImpl<MachineOperand> &Cond,
242                                bool AllowModify) const {
243  // If the block has no terminators, it just falls into the block after it.
244  MachineBasicBlock::iterator I = MBB.end();
245  if (I == MBB.begin())
246    return false;
247  --I;
248  while (I->isDebugValue()) {
249    if (I == MBB.begin())
250      return false;
251    --I;
252  }
253  if (!isUnpredicatedTerminator(I))
254    return false;
255
256  // Get the last instruction in the block.
257  MachineInstr *LastInst = I;
258
259  // If there is only one terminator instruction, process it.
260  unsigned LastOpc = LastInst->getOpcode();
261  if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
262    if (isUncondBranchOpcode(LastOpc)) {
263      TBB = LastInst->getOperand(0).getMBB();
264      return false;
265    }
266    if (isCondBranchOpcode(LastOpc)) {
267      // Block ends with fall-through condbranch.
268      TBB = LastInst->getOperand(0).getMBB();
269      Cond.push_back(LastInst->getOperand(1));
270      Cond.push_back(LastInst->getOperand(2));
271      return false;
272    }
273    return true;  // Can't handle indirect branch.
274  }
275
276  // Get the instruction before it if it is a terminator.
277  MachineInstr *SecondLastInst = I;
278
279  // If there are three terminators, we don't know what sort of block this is.
280  if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(--I))
281    return true;
282
283  // If the block ends with a B and a Bcc, handle it.
284  unsigned SecondLastOpc = SecondLastInst->getOpcode();
285  if (isCondBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) {
286    TBB =  SecondLastInst->getOperand(0).getMBB();
287    Cond.push_back(SecondLastInst->getOperand(1));
288    Cond.push_back(SecondLastInst->getOperand(2));
289    FBB = LastInst->getOperand(0).getMBB();
290    return false;
291  }
292
293  // If the block ends with two unconditional branches, handle it.  The second
294  // one is not executed, so remove it.
295  if (isUncondBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) {
296    TBB = SecondLastInst->getOperand(0).getMBB();
297    I = LastInst;
298    if (AllowModify)
299      I->eraseFromParent();
300    return false;
301  }
302
303  // ...likewise if it ends with a branch table followed by an unconditional
304  // branch. The branch folder can create these, and we must get rid of them for
305  // correctness of Thumb constant islands.
306  if ((isJumpTableBranchOpcode(SecondLastOpc) ||
307       isIndirectBranchOpcode(SecondLastOpc)) &&
308      isUncondBranchOpcode(LastOpc)) {
309    I = LastInst;
310    if (AllowModify)
311      I->eraseFromParent();
312    return true;
313  }
314
315  // Otherwise, can't handle this.
316  return true;
317}
318
319
320unsigned ARMBaseInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
321  MachineBasicBlock::iterator I = MBB.end();
322  if (I == MBB.begin()) return 0;
323  --I;
324  while (I->isDebugValue()) {
325    if (I == MBB.begin())
326      return 0;
327    --I;
328  }
329  if (!isUncondBranchOpcode(I->getOpcode()) &&
330      !isCondBranchOpcode(I->getOpcode()))
331    return 0;
332
333  // Remove the branch.
334  I->eraseFromParent();
335
336  I = MBB.end();
337
338  if (I == MBB.begin()) return 1;
339  --I;
340  if (!isCondBranchOpcode(I->getOpcode()))
341    return 1;
342
343  // Remove the branch.
344  I->eraseFromParent();
345  return 2;
346}
347
348unsigned
349ARMBaseInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
350                               MachineBasicBlock *FBB,
351                               const SmallVectorImpl<MachineOperand> &Cond,
352                               DebugLoc DL) const {
353  ARMFunctionInfo *AFI = MBB.getParent()->getInfo<ARMFunctionInfo>();
354  int BOpc   = !AFI->isThumbFunction()
355    ? ARM::B : (AFI->isThumb2Function() ? ARM::t2B : ARM::tB);
356  int BccOpc = !AFI->isThumbFunction()
357    ? ARM::Bcc : (AFI->isThumb2Function() ? ARM::t2Bcc : ARM::tBcc);
358
359  // Shouldn't be a fall through.
360  assert(TBB && "InsertBranch must not be told to insert a fallthrough");
361  assert((Cond.size() == 2 || Cond.size() == 0) &&
362         "ARM branch conditions have two components!");
363
364  if (FBB == 0) {
365    if (Cond.empty()) // Unconditional branch?
366      BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB);
367    else
368      BuildMI(&MBB, DL, get(BccOpc)).addMBB(TBB)
369        .addImm(Cond[0].getImm()).addReg(Cond[1].getReg());
370    return 1;
371  }
372
373  // Two-way conditional branch.
374  BuildMI(&MBB, DL, get(BccOpc)).addMBB(TBB)
375    .addImm(Cond[0].getImm()).addReg(Cond[1].getReg());
376  BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB);
377  return 2;
378}
379
380bool ARMBaseInstrInfo::
381ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
382  ARMCC::CondCodes CC = (ARMCC::CondCodes)(int)Cond[0].getImm();
383  Cond[0].setImm(ARMCC::getOppositeCondition(CC));
384  return false;
385}
386
387bool ARMBaseInstrInfo::
388PredicateInstruction(MachineInstr *MI,
389                     const SmallVectorImpl<MachineOperand> &Pred) const {
390  unsigned Opc = MI->getOpcode();
391  if (isUncondBranchOpcode(Opc)) {
392    MI->setDesc(get(getMatchingCondBranchOpcode(Opc)));
393    MI->addOperand(MachineOperand::CreateImm(Pred[0].getImm()));
394    MI->addOperand(MachineOperand::CreateReg(Pred[1].getReg(), false));
395    return true;
396  }
397
398  int PIdx = MI->findFirstPredOperandIdx();
399  if (PIdx != -1) {
400    MachineOperand &PMO = MI->getOperand(PIdx);
401    PMO.setImm(Pred[0].getImm());
402    MI->getOperand(PIdx+1).setReg(Pred[1].getReg());
403    return true;
404  }
405  return false;
406}
407
408bool ARMBaseInstrInfo::
409SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
410                  const SmallVectorImpl<MachineOperand> &Pred2) const {
411  if (Pred1.size() > 2 || Pred2.size() > 2)
412    return false;
413
414  ARMCC::CondCodes CC1 = (ARMCC::CondCodes)Pred1[0].getImm();
415  ARMCC::CondCodes CC2 = (ARMCC::CondCodes)Pred2[0].getImm();
416  if (CC1 == CC2)
417    return true;
418
419  switch (CC1) {
420  default:
421    return false;
422  case ARMCC::AL:
423    return true;
424  case ARMCC::HS:
425    return CC2 == ARMCC::HI;
426  case ARMCC::LS:
427    return CC2 == ARMCC::LO || CC2 == ARMCC::EQ;
428  case ARMCC::GE:
429    return CC2 == ARMCC::GT;
430  case ARMCC::LE:
431    return CC2 == ARMCC::LT;
432  }
433}
434
435bool ARMBaseInstrInfo::DefinesPredicate(MachineInstr *MI,
436                                    std::vector<MachineOperand> &Pred) const {
437  // FIXME: This confuses implicit_def with optional CPSR def.
438  const TargetInstrDesc &TID = MI->getDesc();
439  if (!TID.getImplicitDefs() && !TID.hasOptionalDef())
440    return false;
441
442  bool Found = false;
443  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
444    const MachineOperand &MO = MI->getOperand(i);
445    if (MO.isReg() && MO.getReg() == ARM::CPSR) {
446      Pred.push_back(MO);
447      Found = true;
448    }
449  }
450
451  return Found;
452}
453
454/// isPredicable - Return true if the specified instruction can be predicated.
455/// By default, this returns true for every instruction with a
456/// PredicateOperand.
457bool ARMBaseInstrInfo::isPredicable(MachineInstr *MI) const {
458  const TargetInstrDesc &TID = MI->getDesc();
459  if (!TID.isPredicable())
460    return false;
461
462  if ((TID.TSFlags & ARMII::DomainMask) == ARMII::DomainNEON) {
463    ARMFunctionInfo *AFI =
464      MI->getParent()->getParent()->getInfo<ARMFunctionInfo>();
465    return AFI->isThumb2Function();
466  }
467  return true;
468}
469
470/// FIXME: Works around a gcc miscompilation with -fstrict-aliasing.
471DISABLE_INLINE
472static unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT,
473                                unsigned JTI);
474static unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT,
475                                unsigned JTI) {
476  assert(JTI < JT.size());
477  return JT[JTI].MBBs.size();
478}
479
480/// GetInstSize - Return the size of the specified MachineInstr.
481///
482unsigned ARMBaseInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
483  const MachineBasicBlock &MBB = *MI->getParent();
484  const MachineFunction *MF = MBB.getParent();
485  const MCAsmInfo *MAI = MF->getTarget().getMCAsmInfo();
486
487  // Basic size info comes from the TSFlags field.
488  const TargetInstrDesc &TID = MI->getDesc();
489  uint64_t TSFlags = TID.TSFlags;
490
491  unsigned Opc = MI->getOpcode();
492  switch ((TSFlags & ARMII::SizeMask) >> ARMII::SizeShift) {
493  default: {
494    // If this machine instr is an inline asm, measure it.
495    if (MI->getOpcode() == ARM::INLINEASM)
496      return getInlineAsmLength(MI->getOperand(0).getSymbolName(), *MAI);
497    if (MI->isLabel())
498      return 0;
499    switch (Opc) {
500    default:
501      llvm_unreachable("Unknown or unset size field for instr!");
502    case TargetOpcode::IMPLICIT_DEF:
503    case TargetOpcode::KILL:
504    case TargetOpcode::DBG_LABEL:
505    case TargetOpcode::EH_LABEL:
506    case TargetOpcode::DBG_VALUE:
507      return 0;
508    }
509    break;
510  }
511  case ARMII::Size8Bytes: return 8;          // ARM instruction x 2.
512  case ARMII::Size4Bytes: return 4;          // ARM / Thumb2 instruction.
513  case ARMII::Size2Bytes: return 2;          // Thumb1 instruction.
514  case ARMII::SizeSpecial: {
515    switch (Opc) {
516    case ARM::CONSTPOOL_ENTRY:
517      // If this machine instr is a constant pool entry, its size is recorded as
518      // operand #2.
519      return MI->getOperand(2).getImm();
520    case ARM::Int_eh_sjlj_longjmp:
521      return 16;
522    case ARM::tInt_eh_sjlj_longjmp:
523      return 10;
524    case ARM::Int_eh_sjlj_setjmp:
525    case ARM::Int_eh_sjlj_setjmp_nofp:
526      return 20;
527    case ARM::tInt_eh_sjlj_setjmp:
528    case ARM::t2Int_eh_sjlj_setjmp:
529    case ARM::t2Int_eh_sjlj_setjmp_nofp:
530      return 12;
531    case ARM::BR_JTr:
532    case ARM::BR_JTm:
533    case ARM::BR_JTadd:
534    case ARM::tBR_JTr:
535    case ARM::t2BR_JT:
536    case ARM::t2TBB:
537    case ARM::t2TBH: {
538      // These are jumptable branches, i.e. a branch followed by an inlined
539      // jumptable. The size is 4 + 4 * number of entries. For TBB, each
540      // entry is one byte; TBH two byte each.
541      unsigned EntrySize = (Opc == ARM::t2TBB)
542        ? 1 : ((Opc == ARM::t2TBH) ? 2 : 4);
543      unsigned NumOps = TID.getNumOperands();
544      MachineOperand JTOP =
545        MI->getOperand(NumOps - (TID.isPredicable() ? 3 : 2));
546      unsigned JTI = JTOP.getIndex();
547      const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
548      assert(MJTI != 0);
549      const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
550      assert(JTI < JT.size());
551      // Thumb instructions are 2 byte aligned, but JT entries are 4 byte
552      // 4 aligned. The assembler / linker may add 2 byte padding just before
553      // the JT entries.  The size does not include this padding; the
554      // constant islands pass does separate bookkeeping for it.
555      // FIXME: If we know the size of the function is less than (1 << 16) *2
556      // bytes, we can use 16-bit entries instead. Then there won't be an
557      // alignment issue.
558      unsigned InstSize = (Opc == ARM::tBR_JTr || Opc == ARM::t2BR_JT) ? 2 : 4;
559      unsigned NumEntries = getNumJTEntries(JT, JTI);
560      if (Opc == ARM::t2TBB && (NumEntries & 1))
561        // Make sure the instruction that follows TBB is 2-byte aligned.
562        // FIXME: Constant island pass should insert an "ALIGN" instruction
563        // instead.
564        ++NumEntries;
565      return NumEntries * EntrySize + InstSize;
566    }
567    default:
568      // Otherwise, pseudo-instruction sizes are zero.
569      return 0;
570    }
571  }
572  }
573  return 0; // Not reached
574}
575
576/// Return true if the instruction is a register to register move and
577/// leave the source and dest operands in the passed parameters.
578///
579bool
580ARMBaseInstrInfo::isMoveInstr(const MachineInstr &MI,
581                              unsigned &SrcReg, unsigned &DstReg,
582                              unsigned& SrcSubIdx, unsigned& DstSubIdx) const {
583  switch (MI.getOpcode()) {
584  default: break;
585  case ARM::VMOVS:
586  case ARM::VMOVD:
587  case ARM::VMOVDneon:
588  case ARM::VMOVQ:
589  case ARM::VMOVQQ : {
590    SrcReg = MI.getOperand(1).getReg();
591    DstReg = MI.getOperand(0).getReg();
592    SrcSubIdx = MI.getOperand(1).getSubReg();
593    DstSubIdx = MI.getOperand(0).getSubReg();
594    return true;
595  }
596  case ARM::MOVr:
597  case ARM::MOVr_TC:
598  case ARM::tMOVr:
599  case ARM::tMOVgpr2tgpr:
600  case ARM::tMOVtgpr2gpr:
601  case ARM::tMOVgpr2gpr:
602  case ARM::t2MOVr: {
603    assert(MI.getDesc().getNumOperands() >= 2 &&
604           MI.getOperand(0).isReg() &&
605           MI.getOperand(1).isReg() &&
606           "Invalid ARM MOV instruction");
607    SrcReg = MI.getOperand(1).getReg();
608    DstReg = MI.getOperand(0).getReg();
609    SrcSubIdx = MI.getOperand(1).getSubReg();
610    DstSubIdx = MI.getOperand(0).getSubReg();
611    return true;
612  }
613  }
614
615  return false;
616}
617
618unsigned
619ARMBaseInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
620                                      int &FrameIndex) const {
621  switch (MI->getOpcode()) {
622  default: break;
623  case ARM::LDR:
624  case ARM::t2LDRs:  // FIXME: don't use t2LDRs to access frame.
625    if (MI->getOperand(1).isFI() &&
626        MI->getOperand(2).isReg() &&
627        MI->getOperand(3).isImm() &&
628        MI->getOperand(2).getReg() == 0 &&
629        MI->getOperand(3).getImm() == 0) {
630      FrameIndex = MI->getOperand(1).getIndex();
631      return MI->getOperand(0).getReg();
632    }
633    break;
634  case ARM::t2LDRi12:
635  case ARM::tRestore:
636    if (MI->getOperand(1).isFI() &&
637        MI->getOperand(2).isImm() &&
638        MI->getOperand(2).getImm() == 0) {
639      FrameIndex = MI->getOperand(1).getIndex();
640      return MI->getOperand(0).getReg();
641    }
642    break;
643  case ARM::VLDRD:
644  case ARM::VLDRS:
645    if (MI->getOperand(1).isFI() &&
646        MI->getOperand(2).isImm() &&
647        MI->getOperand(2).getImm() == 0) {
648      FrameIndex = MI->getOperand(1).getIndex();
649      return MI->getOperand(0).getReg();
650    }
651    break;
652  }
653
654  return 0;
655}
656
657unsigned
658ARMBaseInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
659                                     int &FrameIndex) const {
660  switch (MI->getOpcode()) {
661  default: break;
662  case ARM::STR:
663  case ARM::t2STRs: // FIXME: don't use t2STRs to access frame.
664    if (MI->getOperand(1).isFI() &&
665        MI->getOperand(2).isReg() &&
666        MI->getOperand(3).isImm() &&
667        MI->getOperand(2).getReg() == 0 &&
668        MI->getOperand(3).getImm() == 0) {
669      FrameIndex = MI->getOperand(1).getIndex();
670      return MI->getOperand(0).getReg();
671    }
672    break;
673  case ARM::t2STRi12:
674  case ARM::tSpill:
675    if (MI->getOperand(1).isFI() &&
676        MI->getOperand(2).isImm() &&
677        MI->getOperand(2).getImm() == 0) {
678      FrameIndex = MI->getOperand(1).getIndex();
679      return MI->getOperand(0).getReg();
680    }
681    break;
682  case ARM::VSTRD:
683  case ARM::VSTRS:
684    if (MI->getOperand(1).isFI() &&
685        MI->getOperand(2).isImm() &&
686        MI->getOperand(2).getImm() == 0) {
687      FrameIndex = MI->getOperand(1).getIndex();
688      return MI->getOperand(0).getReg();
689    }
690    break;
691  }
692
693  return 0;
694}
695
696bool
697ARMBaseInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
698                               MachineBasicBlock::iterator I,
699                               unsigned DestReg, unsigned SrcReg,
700                               const TargetRegisterClass *DestRC,
701                               const TargetRegisterClass *SrcRC,
702                               DebugLoc DL) const {
703  // tGPR or tcGPR is used sometimes in ARM instructions that need to avoid
704  // using certain registers.  Just treat them as GPR here.
705  if (DestRC == ARM::tGPRRegisterClass || DestRC == ARM::tcGPRRegisterClass)
706    DestRC = ARM::GPRRegisterClass;
707  if (SrcRC == ARM::tGPRRegisterClass || SrcRC == ARM::tcGPRRegisterClass)
708    SrcRC = ARM::GPRRegisterClass;
709
710  // Allow DPR / DPR_VFP2 / DPR_8 cross-class copies.
711  if (DestRC == ARM::DPR_8RegisterClass)
712    DestRC = ARM::DPR_VFP2RegisterClass;
713  if (SrcRC == ARM::DPR_8RegisterClass)
714    SrcRC = ARM::DPR_VFP2RegisterClass;
715
716  // Allow QPR / QPR_VFP2 / QPR_8 cross-class copies.
717  if (DestRC == ARM::QPR_VFP2RegisterClass ||
718      DestRC == ARM::QPR_8RegisterClass)
719    DestRC = ARM::QPRRegisterClass;
720  if (SrcRC == ARM::QPR_VFP2RegisterClass ||
721      SrcRC == ARM::QPR_8RegisterClass)
722    SrcRC = ARM::QPRRegisterClass;
723
724  // Allow QQPR / QQPR_VFP2 cross-class copies.
725  if (DestRC == ARM::QQPR_VFP2RegisterClass)
726    DestRC = ARM::QQPRRegisterClass;
727  if (SrcRC == ARM::QQPR_VFP2RegisterClass)
728    SrcRC = ARM::QQPRRegisterClass;
729
730  // Disallow copies of unequal sizes.
731  if (DestRC != SrcRC && DestRC->getSize() != SrcRC->getSize())
732    return false;
733
734  if (DestRC == ARM::GPRRegisterClass) {
735    if (SrcRC == ARM::SPRRegisterClass)
736      AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VMOVRS), DestReg)
737                     .addReg(SrcReg));
738    else
739      AddDefaultCC(AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::MOVr),
740                                          DestReg).addReg(SrcReg)));
741  } else {
742    unsigned Opc;
743
744    if (DestRC == ARM::SPRRegisterClass)
745      Opc = (SrcRC == ARM::GPRRegisterClass ? ARM::VMOVSR : ARM::VMOVS);
746    else if (DestRC == ARM::DPRRegisterClass)
747      Opc = ARM::VMOVD;
748    else if (DestRC == ARM::DPR_VFP2RegisterClass ||
749             SrcRC == ARM::DPR_VFP2RegisterClass)
750      // Always use neon reg-reg move if source or dest is NEON-only regclass.
751      Opc = ARM::VMOVDneon;
752    else if (DestRC == ARM::QPRRegisterClass)
753      Opc = ARM::VMOVQ;
754    else if (DestRC == ARM::QQPRRegisterClass)
755      Opc = ARM::VMOVQQ;
756    else if (DestRC == ARM::QQQQPRRegisterClass)
757      Opc = ARM::VMOVQQQQ;
758    else
759      return false;
760
761    MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc), DestReg);
762    MIB.addReg(SrcReg);
763    if (Opc != ARM::VMOVQQ && Opc != ARM::VMOVQQQQ)
764      AddDefaultPred(MIB);
765  }
766
767  return true;
768}
769
770static const
771MachineInstrBuilder &AddDReg(MachineInstrBuilder &MIB,
772                             unsigned Reg, unsigned SubIdx, unsigned State,
773                             const TargetRegisterInfo *TRI) {
774  if (!SubIdx)
775    return MIB.addReg(Reg, State);
776
777  if (TargetRegisterInfo::isPhysicalRegister(Reg))
778    return MIB.addReg(TRI->getSubReg(Reg, SubIdx), State);
779  return MIB.addReg(Reg, State, SubIdx);
780}
781
782void ARMBaseInstrInfo::
783storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
784                    unsigned SrcReg, bool isKill, int FI,
785                    const TargetRegisterClass *RC,
786                    const TargetRegisterInfo *TRI) const {
787  DebugLoc DL;
788  if (I != MBB.end()) DL = I->getDebugLoc();
789  MachineFunction &MF = *MBB.getParent();
790  MachineFrameInfo &MFI = *MF.getFrameInfo();
791  unsigned Align = MFI.getObjectAlignment(FI);
792
793  MachineMemOperand *MMO =
794    MF.getMachineMemOperand(PseudoSourceValue::getFixedStack(FI),
795                            MachineMemOperand::MOStore, 0,
796                            MFI.getObjectSize(FI),
797                            Align);
798
799  // tGPR is used sometimes in ARM instructions that need to avoid using
800  // certain registers.  Just treat it as GPR here.
801  if (RC == ARM::tGPRRegisterClass || RC == ARM::tcGPRRegisterClass)
802    RC = ARM::GPRRegisterClass;
803
804  switch (RC->getID()) {
805  case ARM::GPRRegClassID:
806    AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::STR))
807                   .addReg(SrcReg, getKillRegState(isKill))
808                   .addFrameIndex(FI).addReg(0).addImm(0).addMemOperand(MMO));
809    break;
810  case ARM::SPRRegClassID:
811    AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTRS))
812                   .addReg(SrcReg, getKillRegState(isKill))
813                   .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
814    break;
815  case ARM::DPRRegClassID:
816  case ARM::DPR_VFP2RegClassID:
817  case ARM::DPR_8RegClassID:
818    AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTRD))
819                   .addReg(SrcReg, getKillRegState(isKill))
820                   .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
821    break;
822  case ARM::QPRRegClassID:
823  case ARM::QPR_VFP2RegClassID:
824  case ARM::QPR_8RegClassID:
825    // FIXME: Neon instructions should support predicates
826    if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
827      AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1q))
828                     .addFrameIndex(FI).addImm(128)
829                     .addReg(SrcReg, getKillRegState(isKill))
830                     .addMemOperand(MMO));
831    } else {
832      AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMQ))
833                     .addReg(SrcReg, getKillRegState(isKill))
834                     .addFrameIndex(FI)
835                     .addImm(ARM_AM::getAM5Opc(ARM_AM::ia, 4))
836                     .addMemOperand(MMO));
837    }
838    break;
839  case ARM::QQPRRegClassID:
840  case ARM::QQPR_VFP2RegClassID:
841    if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
842      // FIXME: It's possible to only store part of the QQ register if the
843      // spilled def has a sub-register index.
844      MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::VST2q32))
845        .addFrameIndex(FI).addImm(128);
846      MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
847      MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);
848      MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);
849      MIB = AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI);
850      AddDefaultPred(MIB.addMemOperand(MMO));
851    } else {
852      MachineInstrBuilder MIB =
853        AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMD))
854                       .addFrameIndex(FI)
855                       .addImm(ARM_AM::getAM5Opc(ARM_AM::ia, 4)))
856        .addMemOperand(MMO);
857      MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
858      MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);
859      MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);
860            AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI);
861    }
862    break;
863  case ARM::QQQQPRRegClassID: {
864    MachineInstrBuilder MIB =
865      AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMD))
866                     .addFrameIndex(FI)
867                     .addImm(ARM_AM::getAM5Opc(ARM_AM::ia, 4)))
868      .addMemOperand(MMO);
869    MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
870    MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);
871    MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);
872    MIB = AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI);
873    MIB = AddDReg(MIB, SrcReg, ARM::dsub_4, 0, TRI);
874    MIB = AddDReg(MIB, SrcReg, ARM::dsub_5, 0, TRI);
875    MIB = AddDReg(MIB, SrcReg, ARM::dsub_6, 0, TRI);
876          AddDReg(MIB, SrcReg, ARM::dsub_7, 0, TRI);
877    break;
878  }
879  default:
880    llvm_unreachable("Unknown regclass!");
881  }
882}
883
884void ARMBaseInstrInfo::
885loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
886                     unsigned DestReg, int FI,
887                     const TargetRegisterClass *RC,
888                     const TargetRegisterInfo *TRI) const {
889  DebugLoc DL;
890  if (I != MBB.end()) DL = I->getDebugLoc();
891  MachineFunction &MF = *MBB.getParent();
892  MachineFrameInfo &MFI = *MF.getFrameInfo();
893  unsigned Align = MFI.getObjectAlignment(FI);
894  MachineMemOperand *MMO =
895    MF.getMachineMemOperand(PseudoSourceValue::getFixedStack(FI),
896                            MachineMemOperand::MOLoad, 0,
897                            MFI.getObjectSize(FI),
898                            Align);
899
900  // tGPR is used sometimes in ARM instructions that need to avoid using
901  // certain registers.  Just treat it as GPR here.
902  if (RC == ARM::tGPRRegisterClass || RC == ARM::tcGPRRegisterClass)
903    RC = ARM::GPRRegisterClass;
904
905  switch (RC->getID()) {
906  case ARM::GPRRegClassID:
907    AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::LDR), DestReg)
908                   .addFrameIndex(FI).addReg(0).addImm(0).addMemOperand(MMO));
909    break;
910  case ARM::SPRRegClassID:
911    AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRS), DestReg)
912                   .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
913    break;
914  case ARM::DPRRegClassID:
915  case ARM::DPR_VFP2RegClassID:
916  case ARM::DPR_8RegClassID:
917    AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRD), DestReg)
918                   .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
919    break;
920  case ARM::QPRRegClassID:
921  case ARM::QPR_VFP2RegClassID:
922  case ARM::QPR_8RegClassID:
923    if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
924      AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1q), DestReg)
925                     .addFrameIndex(FI).addImm(128)
926                     .addMemOperand(MMO));
927    } else {
928      AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMQ), DestReg)
929                     .addFrameIndex(FI)
930                     .addImm(ARM_AM::getAM5Opc(ARM_AM::ia, 4))
931                     .addMemOperand(MMO));
932    }
933    break;
934  case ARM::QQPRRegClassID:
935  case ARM::QQPR_VFP2RegClassID:
936    if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
937      MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::VLD2q32));
938      MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::Define, TRI);
939      MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::Define, TRI);
940      MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::Define, TRI);
941      MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::Define, TRI);
942      AddDefaultPred(MIB.addFrameIndex(FI).addImm(128).addMemOperand(MMO));
943    } else {
944      MachineInstrBuilder MIB =
945        AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMD))
946                       .addFrameIndex(FI)
947                       .addImm(ARM_AM::getAM5Opc(ARM_AM::ia, 4)))
948        .addMemOperand(MMO);
949      MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::Define, TRI);
950      MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::Define, TRI);
951      MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::Define, TRI);
952            AddDReg(MIB, DestReg, ARM::dsub_3, RegState::Define, TRI);
953    }
954    break;
955  case ARM::QQQQPRRegClassID: {
956    MachineInstrBuilder MIB =
957      AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMD))
958                     .addFrameIndex(FI)
959                     .addImm(ARM_AM::getAM5Opc(ARM_AM::ia, 4)))
960      .addMemOperand(MMO);
961    MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::Define, TRI);
962    MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::Define, TRI);
963    MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::Define, TRI);
964    MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::Define, TRI);
965    MIB = AddDReg(MIB, DestReg, ARM::dsub_4, RegState::Define, TRI);
966    MIB = AddDReg(MIB, DestReg, ARM::dsub_5, RegState::Define, TRI);
967    MIB = AddDReg(MIB, DestReg, ARM::dsub_6, RegState::Define, TRI);
968    AddDReg(MIB, DestReg, ARM::dsub_7, RegState::Define, TRI);
969    break;
970  }
971  default:
972    llvm_unreachable("Unknown regclass!");
973  }
974}
975
976MachineInstr*
977ARMBaseInstrInfo::emitFrameIndexDebugValue(MachineFunction &MF,
978                                           int FrameIx, uint64_t Offset,
979                                           const MDNode *MDPtr,
980                                           DebugLoc DL) const {
981  MachineInstrBuilder MIB = BuildMI(MF, DL, get(ARM::DBG_VALUE))
982    .addFrameIndex(FrameIx).addImm(0).addImm(Offset).addMetadata(MDPtr);
983  return &*MIB;
984}
985
986MachineInstr *ARMBaseInstrInfo::
987foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI,
988                      const SmallVectorImpl<unsigned> &Ops, int FI) const {
989  if (Ops.size() != 1) return NULL;
990
991  unsigned OpNum = Ops[0];
992  unsigned Opc = MI->getOpcode();
993  MachineInstr *NewMI = NULL;
994  if (Opc == ARM::MOVr || Opc == ARM::t2MOVr) {
995    // If it is updating CPSR, then it cannot be folded.
996    if (MI->getOperand(4).getReg() == ARM::CPSR && !MI->getOperand(4).isDead())
997      return NULL;
998    unsigned Pred = MI->getOperand(2).getImm();
999    unsigned PredReg = MI->getOperand(3).getReg();
1000    if (OpNum == 0) { // move -> store
1001      unsigned SrcReg = MI->getOperand(1).getReg();
1002      unsigned SrcSubReg = MI->getOperand(1).getSubReg();
1003      bool isKill = MI->getOperand(1).isKill();
1004      bool isUndef = MI->getOperand(1).isUndef();
1005      if (Opc == ARM::MOVr)
1006        NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::STR))
1007          .addReg(SrcReg,
1008                  getKillRegState(isKill) | getUndefRegState(isUndef),
1009                  SrcSubReg)
1010          .addFrameIndex(FI).addReg(0).addImm(0).addImm(Pred).addReg(PredReg);
1011      else // ARM::t2MOVr
1012        NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::t2STRi12))
1013          .addReg(SrcReg,
1014                  getKillRegState(isKill) | getUndefRegState(isUndef),
1015                  SrcSubReg)
1016          .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg);
1017    } else {          // move -> load
1018      unsigned DstReg = MI->getOperand(0).getReg();
1019      unsigned DstSubReg = MI->getOperand(0).getSubReg();
1020      bool isDead = MI->getOperand(0).isDead();
1021      bool isUndef = MI->getOperand(0).isUndef();
1022      if (Opc == ARM::MOVr)
1023        NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::LDR))
1024          .addReg(DstReg,
1025                  RegState::Define |
1026                  getDeadRegState(isDead) |
1027                  getUndefRegState(isUndef), DstSubReg)
1028          .addFrameIndex(FI).addReg(0).addImm(0).addImm(Pred).addReg(PredReg);
1029      else // ARM::t2MOVr
1030        NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::t2LDRi12))
1031          .addReg(DstReg,
1032                  RegState::Define |
1033                  getDeadRegState(isDead) |
1034                  getUndefRegState(isUndef), DstSubReg)
1035          .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg);
1036    }
1037  } else if (Opc == ARM::tMOVgpr2gpr ||
1038             Opc == ARM::tMOVtgpr2gpr ||
1039             Opc == ARM::tMOVgpr2tgpr) {
1040    if (OpNum == 0) { // move -> store
1041      unsigned SrcReg = MI->getOperand(1).getReg();
1042      unsigned SrcSubReg = MI->getOperand(1).getSubReg();
1043      bool isKill = MI->getOperand(1).isKill();
1044      bool isUndef = MI->getOperand(1).isUndef();
1045      NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::t2STRi12))
1046        .addReg(SrcReg,
1047                getKillRegState(isKill) | getUndefRegState(isUndef),
1048                SrcSubReg)
1049        .addFrameIndex(FI).addImm(0).addImm(ARMCC::AL).addReg(0);
1050    } else {          // move -> load
1051      unsigned DstReg = MI->getOperand(0).getReg();
1052      unsigned DstSubReg = MI->getOperand(0).getSubReg();
1053      bool isDead = MI->getOperand(0).isDead();
1054      bool isUndef = MI->getOperand(0).isUndef();
1055      NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::t2LDRi12))
1056        .addReg(DstReg,
1057                RegState::Define |
1058                getDeadRegState(isDead) |
1059                getUndefRegState(isUndef),
1060                DstSubReg)
1061        .addFrameIndex(FI).addImm(0).addImm(ARMCC::AL).addReg(0);
1062    }
1063  } else if (Opc == ARM::VMOVS) {
1064    unsigned Pred = MI->getOperand(2).getImm();
1065    unsigned PredReg = MI->getOperand(3).getReg();
1066    if (OpNum == 0) { // move -> store
1067      unsigned SrcReg = MI->getOperand(1).getReg();
1068      unsigned SrcSubReg = MI->getOperand(1).getSubReg();
1069      bool isKill = MI->getOperand(1).isKill();
1070      bool isUndef = MI->getOperand(1).isUndef();
1071      NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::VSTRS))
1072        .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef),
1073                SrcSubReg)
1074        .addFrameIndex(FI)
1075        .addImm(0).addImm(Pred).addReg(PredReg);
1076    } else {          // move -> load
1077      unsigned DstReg = MI->getOperand(0).getReg();
1078      unsigned DstSubReg = MI->getOperand(0).getSubReg();
1079      bool isDead = MI->getOperand(0).isDead();
1080      bool isUndef = MI->getOperand(0).isUndef();
1081      NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::VLDRS))
1082        .addReg(DstReg,
1083                RegState::Define |
1084                getDeadRegState(isDead) |
1085                getUndefRegState(isUndef),
1086                DstSubReg)
1087        .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg);
1088    }
1089  } else if (Opc == ARM::VMOVD || Opc == ARM::VMOVDneon) {
1090    unsigned Pred = MI->getOperand(2).getImm();
1091    unsigned PredReg = MI->getOperand(3).getReg();
1092    if (OpNum == 0) { // move -> store
1093      unsigned SrcReg = MI->getOperand(1).getReg();
1094      unsigned SrcSubReg = MI->getOperand(1).getSubReg();
1095      bool isKill = MI->getOperand(1).isKill();
1096      bool isUndef = MI->getOperand(1).isUndef();
1097      NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::VSTRD))
1098        .addReg(SrcReg,
1099                getKillRegState(isKill) | getUndefRegState(isUndef),
1100                SrcSubReg)
1101        .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg);
1102    } else {          // move -> load
1103      unsigned DstReg = MI->getOperand(0).getReg();
1104      unsigned DstSubReg = MI->getOperand(0).getSubReg();
1105      bool isDead = MI->getOperand(0).isDead();
1106      bool isUndef = MI->getOperand(0).isUndef();
1107      NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::VLDRD))
1108        .addReg(DstReg,
1109                RegState::Define |
1110                getDeadRegState(isDead) |
1111                getUndefRegState(isUndef),
1112                DstSubReg)
1113        .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg);
1114    }
1115  }  else if (Opc == ARM::VMOVQ) {
1116    MachineFrameInfo &MFI = *MF.getFrameInfo();
1117    unsigned Pred = MI->getOperand(2).getImm();
1118    unsigned PredReg = MI->getOperand(3).getReg();
1119    if (OpNum == 0) { // move -> store
1120      unsigned SrcReg = MI->getOperand(1).getReg();
1121      unsigned SrcSubReg = MI->getOperand(1).getSubReg();
1122      bool isKill = MI->getOperand(1).isKill();
1123      bool isUndef = MI->getOperand(1).isUndef();
1124      if (MFI.getObjectAlignment(FI) >= 16 &&
1125          getRegisterInfo().canRealignStack(MF)) {
1126        NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::VST1q))
1127          .addFrameIndex(FI).addImm(128)
1128          .addReg(SrcReg,
1129                  getKillRegState(isKill) | getUndefRegState(isUndef),
1130                  SrcSubReg)
1131          .addImm(Pred).addReg(PredReg);
1132      } else {
1133        NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::VSTMQ))
1134          .addReg(SrcReg,
1135                  getKillRegState(isKill) | getUndefRegState(isUndef),
1136                  SrcSubReg)
1137          .addFrameIndex(FI).addImm(ARM_AM::getAM5Opc(ARM_AM::ia, 4))
1138          .addImm(Pred).addReg(PredReg);
1139      }
1140    } else {          // move -> load
1141      unsigned DstReg = MI->getOperand(0).getReg();
1142      unsigned DstSubReg = MI->getOperand(0).getSubReg();
1143      bool isDead = MI->getOperand(0).isDead();
1144      bool isUndef = MI->getOperand(0).isUndef();
1145      if (MFI.getObjectAlignment(FI) >= 16 &&
1146          getRegisterInfo().canRealignStack(MF)) {
1147        NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::VLD1q))
1148          .addReg(DstReg,
1149                  RegState::Define |
1150                  getDeadRegState(isDead) |
1151                  getUndefRegState(isUndef),
1152                  DstSubReg)
1153          .addFrameIndex(FI).addImm(128).addImm(Pred).addReg(PredReg);
1154      } else {
1155        NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::VLDMQ))
1156          .addReg(DstReg,
1157                  RegState::Define |
1158                  getDeadRegState(isDead) |
1159                  getUndefRegState(isUndef),
1160                  DstSubReg)
1161          .addFrameIndex(FI).addImm(ARM_AM::getAM5Opc(ARM_AM::ia, 4))
1162          .addImm(Pred).addReg(PredReg);
1163      }
1164    }
1165  }
1166
1167  return NewMI;
1168}
1169
1170MachineInstr*
1171ARMBaseInstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
1172                                        MachineInstr* MI,
1173                                        const SmallVectorImpl<unsigned> &Ops,
1174                                        MachineInstr* LoadMI) const {
1175  // FIXME
1176  return 0;
1177}
1178
1179bool
1180ARMBaseInstrInfo::canFoldMemoryOperand(const MachineInstr *MI,
1181                                   const SmallVectorImpl<unsigned> &Ops) const {
1182  if (Ops.size() != 1) return false;
1183
1184  unsigned Opc = MI->getOpcode();
1185  if (Opc == ARM::MOVr || Opc == ARM::t2MOVr) {
1186    // If it is updating CPSR, then it cannot be folded.
1187    return MI->getOperand(4).getReg() != ARM::CPSR ||
1188      MI->getOperand(4).isDead();
1189  } else if (Opc == ARM::tMOVgpr2gpr ||
1190             Opc == ARM::tMOVtgpr2gpr ||
1191             Opc == ARM::tMOVgpr2tgpr) {
1192    return true;
1193  } else if (Opc == ARM::VMOVS || Opc == ARM::VMOVD ||
1194             Opc == ARM::VMOVDneon || Opc == ARM::VMOVQ) {
1195    return true;
1196  }
1197
1198  // FIXME: VMOVQQ and VMOVQQQQ?
1199
1200  return false;
1201}
1202
1203/// Create a copy of a const pool value. Update CPI to the new index and return
1204/// the label UID.
1205static unsigned duplicateCPV(MachineFunction &MF, unsigned &CPI) {
1206  MachineConstantPool *MCP = MF.getConstantPool();
1207  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1208
1209  const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPI];
1210  assert(MCPE.isMachineConstantPoolEntry() &&
1211         "Expecting a machine constantpool entry!");
1212  ARMConstantPoolValue *ACPV =
1213    static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal);
1214
1215  unsigned PCLabelId = AFI->createConstPoolEntryUId();
1216  ARMConstantPoolValue *NewCPV = 0;
1217  if (ACPV->isGlobalValue())
1218    NewCPV = new ARMConstantPoolValue(ACPV->getGV(), PCLabelId,
1219                                      ARMCP::CPValue, 4);
1220  else if (ACPV->isExtSymbol())
1221    NewCPV = new ARMConstantPoolValue(MF.getFunction()->getContext(),
1222                                      ACPV->getSymbol(), PCLabelId, 4);
1223  else if (ACPV->isBlockAddress())
1224    NewCPV = new ARMConstantPoolValue(ACPV->getBlockAddress(), PCLabelId,
1225                                      ARMCP::CPBlockAddress, 4);
1226  else
1227    llvm_unreachable("Unexpected ARM constantpool value type!!");
1228  CPI = MCP->getConstantPoolIndex(NewCPV, MCPE.getAlignment());
1229  return PCLabelId;
1230}
1231
1232void ARMBaseInstrInfo::
1233reMaterialize(MachineBasicBlock &MBB,
1234              MachineBasicBlock::iterator I,
1235              unsigned DestReg, unsigned SubIdx,
1236              const MachineInstr *Orig,
1237              const TargetRegisterInfo &TRI) const {
1238  unsigned Opcode = Orig->getOpcode();
1239  switch (Opcode) {
1240  default: {
1241    MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig);
1242    MI->substituteRegister(Orig->getOperand(0).getReg(), DestReg, SubIdx, TRI);
1243    MBB.insert(I, MI);
1244    break;
1245  }
1246  case ARM::tLDRpci_pic:
1247  case ARM::t2LDRpci_pic: {
1248    MachineFunction &MF = *MBB.getParent();
1249    unsigned CPI = Orig->getOperand(1).getIndex();
1250    unsigned PCLabelId = duplicateCPV(MF, CPI);
1251    MachineInstrBuilder MIB = BuildMI(MBB, I, Orig->getDebugLoc(), get(Opcode),
1252                                      DestReg)
1253      .addConstantPoolIndex(CPI).addImm(PCLabelId);
1254    (*MIB).setMemRefs(Orig->memoperands_begin(), Orig->memoperands_end());
1255    break;
1256  }
1257  }
1258}
1259
1260MachineInstr *
1261ARMBaseInstrInfo::duplicate(MachineInstr *Orig, MachineFunction &MF) const {
1262  MachineInstr *MI = TargetInstrInfoImpl::duplicate(Orig, MF);
1263  switch(Orig->getOpcode()) {
1264  case ARM::tLDRpci_pic:
1265  case ARM::t2LDRpci_pic: {
1266    unsigned CPI = Orig->getOperand(1).getIndex();
1267    unsigned PCLabelId = duplicateCPV(MF, CPI);
1268    Orig->getOperand(1).setIndex(CPI);
1269    Orig->getOperand(2).setImm(PCLabelId);
1270    break;
1271  }
1272  }
1273  return MI;
1274}
1275
1276bool ARMBaseInstrInfo::produceSameValue(const MachineInstr *MI0,
1277                                        const MachineInstr *MI1) const {
1278  int Opcode = MI0->getOpcode();
1279  if (Opcode == ARM::t2LDRpci ||
1280      Opcode == ARM::t2LDRpci_pic ||
1281      Opcode == ARM::tLDRpci ||
1282      Opcode == ARM::tLDRpci_pic) {
1283    if (MI1->getOpcode() != Opcode)
1284      return false;
1285    if (MI0->getNumOperands() != MI1->getNumOperands())
1286      return false;
1287
1288    const MachineOperand &MO0 = MI0->getOperand(1);
1289    const MachineOperand &MO1 = MI1->getOperand(1);
1290    if (MO0.getOffset() != MO1.getOffset())
1291      return false;
1292
1293    const MachineFunction *MF = MI0->getParent()->getParent();
1294    const MachineConstantPool *MCP = MF->getConstantPool();
1295    int CPI0 = MO0.getIndex();
1296    int CPI1 = MO1.getIndex();
1297    const MachineConstantPoolEntry &MCPE0 = MCP->getConstants()[CPI0];
1298    const MachineConstantPoolEntry &MCPE1 = MCP->getConstants()[CPI1];
1299    ARMConstantPoolValue *ACPV0 =
1300      static_cast<ARMConstantPoolValue*>(MCPE0.Val.MachineCPVal);
1301    ARMConstantPoolValue *ACPV1 =
1302      static_cast<ARMConstantPoolValue*>(MCPE1.Val.MachineCPVal);
1303    return ACPV0->hasSameValue(ACPV1);
1304  }
1305
1306  return MI0->isIdenticalTo(MI1, MachineInstr::IgnoreVRegDefs);
1307}
1308
1309bool ARMBaseInstrInfo::isSchedulingBoundary(const MachineInstr *MI,
1310                                            const MachineBasicBlock *MBB,
1311                                            const MachineFunction &MF) const {
1312  // Terminators and labels can't be scheduled around.
1313  if (MI->getDesc().isTerminator() || MI->isLabel())
1314    return true;
1315
1316  // Treat the start of the IT block as a scheduling boundary, but schedule
1317  // t2IT along with all instructions following it.
1318  // FIXME: This is a big hammer. But the alternative is to add all potential
1319  // true and anti dependencies to IT block instructions as implicit operands
1320  // to the t2IT instruction. The added compile time and complexity does not
1321  // seem worth it.
1322  MachineBasicBlock::const_iterator I = MI;
1323  if (++I != MBB->end() && I->getOpcode() == ARM::t2IT)
1324    return true;
1325
1326  // Don't attempt to schedule around any instruction that defines
1327  // a stack-oriented pointer, as it's unlikely to be profitable. This
1328  // saves compile time, because it doesn't require every single
1329  // stack slot reference to depend on the instruction that does the
1330  // modification.
1331  if (MI->definesRegister(ARM::SP))
1332    return true;
1333
1334  return false;
1335}
1336
1337/// getInstrPredicate - If instruction is predicated, returns its predicate
1338/// condition, otherwise returns AL. It also returns the condition code
1339/// register by reference.
1340ARMCC::CondCodes
1341llvm::getInstrPredicate(const MachineInstr *MI, unsigned &PredReg) {
1342  int PIdx = MI->findFirstPredOperandIdx();
1343  if (PIdx == -1) {
1344    PredReg = 0;
1345    return ARMCC::AL;
1346  }
1347
1348  PredReg = MI->getOperand(PIdx+1).getReg();
1349  return (ARMCC::CondCodes)MI->getOperand(PIdx).getImm();
1350}
1351
1352
1353int llvm::getMatchingCondBranchOpcode(int Opc) {
1354  if (Opc == ARM::B)
1355    return ARM::Bcc;
1356  else if (Opc == ARM::tB)
1357    return ARM::tBcc;
1358  else if (Opc == ARM::t2B)
1359      return ARM::t2Bcc;
1360
1361  llvm_unreachable("Unknown unconditional branch opcode!");
1362  return 0;
1363}
1364
1365
1366void llvm::emitARMRegPlusImmediate(MachineBasicBlock &MBB,
1367                               MachineBasicBlock::iterator &MBBI, DebugLoc dl,
1368                               unsigned DestReg, unsigned BaseReg, int NumBytes,
1369                               ARMCC::CondCodes Pred, unsigned PredReg,
1370                               const ARMBaseInstrInfo &TII) {
1371  bool isSub = NumBytes < 0;
1372  if (isSub) NumBytes = -NumBytes;
1373
1374  while (NumBytes) {
1375    unsigned RotAmt = ARM_AM::getSOImmValRotate(NumBytes);
1376    unsigned ThisVal = NumBytes & ARM_AM::rotr32(0xFF, RotAmt);
1377    assert(ThisVal && "Didn't extract field correctly");
1378
1379    // We will handle these bits from offset, clear them.
1380    NumBytes &= ~ThisVal;
1381
1382    assert(ARM_AM::getSOImmVal(ThisVal) != -1 && "Bit extraction didn't work?");
1383
1384    // Build the new ADD / SUB.
1385    unsigned Opc = isSub ? ARM::SUBri : ARM::ADDri;
1386    BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)
1387      .addReg(BaseReg, RegState::Kill).addImm(ThisVal)
1388      .addImm((unsigned)Pred).addReg(PredReg).addReg(0);
1389    BaseReg = DestReg;
1390  }
1391}
1392
1393bool llvm::rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
1394                                unsigned FrameReg, int &Offset,
1395                                const ARMBaseInstrInfo &TII) {
1396  unsigned Opcode = MI.getOpcode();
1397  const TargetInstrDesc &Desc = MI.getDesc();
1398  unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
1399  bool isSub = false;
1400
1401  // Memory operands in inline assembly always use AddrMode2.
1402  if (Opcode == ARM::INLINEASM)
1403    AddrMode = ARMII::AddrMode2;
1404
1405  if (Opcode == ARM::ADDri) {
1406    Offset += MI.getOperand(FrameRegIdx+1).getImm();
1407    if (Offset == 0) {
1408      // Turn it into a move.
1409      MI.setDesc(TII.get(ARM::MOVr));
1410      MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
1411      MI.RemoveOperand(FrameRegIdx+1);
1412      Offset = 0;
1413      return true;
1414    } else if (Offset < 0) {
1415      Offset = -Offset;
1416      isSub = true;
1417      MI.setDesc(TII.get(ARM::SUBri));
1418    }
1419
1420    // Common case: small offset, fits into instruction.
1421    if (ARM_AM::getSOImmVal(Offset) != -1) {
1422      // Replace the FrameIndex with sp / fp
1423      MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
1424      MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset);
1425      Offset = 0;
1426      return true;
1427    }
1428
1429    // Otherwise, pull as much of the immedidate into this ADDri/SUBri
1430    // as possible.
1431    unsigned RotAmt = ARM_AM::getSOImmValRotate(Offset);
1432    unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xFF, RotAmt);
1433
1434    // We will handle these bits from offset, clear them.
1435    Offset &= ~ThisImmVal;
1436
1437    // Get the properly encoded SOImmVal field.
1438    assert(ARM_AM::getSOImmVal(ThisImmVal) != -1 &&
1439           "Bit extraction didn't work?");
1440    MI.getOperand(FrameRegIdx+1).ChangeToImmediate(ThisImmVal);
1441 } else {
1442    unsigned ImmIdx = 0;
1443    int InstrOffs = 0;
1444    unsigned NumBits = 0;
1445    unsigned Scale = 1;
1446    switch (AddrMode) {
1447    case ARMII::AddrMode2: {
1448      ImmIdx = FrameRegIdx+2;
1449      InstrOffs = ARM_AM::getAM2Offset(MI.getOperand(ImmIdx).getImm());
1450      if (ARM_AM::getAM2Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
1451        InstrOffs *= -1;
1452      NumBits = 12;
1453      break;
1454    }
1455    case ARMII::AddrMode3: {
1456      ImmIdx = FrameRegIdx+2;
1457      InstrOffs = ARM_AM::getAM3Offset(MI.getOperand(ImmIdx).getImm());
1458      if (ARM_AM::getAM3Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
1459        InstrOffs *= -1;
1460      NumBits = 8;
1461      break;
1462    }
1463    case ARMII::AddrMode4:
1464    case ARMII::AddrMode6:
1465      // Can't fold any offset even if it's zero.
1466      return false;
1467    case ARMII::AddrMode5: {
1468      ImmIdx = FrameRegIdx+1;
1469      InstrOffs = ARM_AM::getAM5Offset(MI.getOperand(ImmIdx).getImm());
1470      if (ARM_AM::getAM5Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
1471        InstrOffs *= -1;
1472      NumBits = 8;
1473      Scale = 4;
1474      break;
1475    }
1476    default:
1477      llvm_unreachable("Unsupported addressing mode!");
1478      break;
1479    }
1480
1481    Offset += InstrOffs * Scale;
1482    assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!");
1483    if (Offset < 0) {
1484      Offset = -Offset;
1485      isSub = true;
1486    }
1487
1488    // Attempt to fold address comp. if opcode has offset bits
1489    if (NumBits > 0) {
1490      // Common case: small offset, fits into instruction.
1491      MachineOperand &ImmOp = MI.getOperand(ImmIdx);
1492      int ImmedOffset = Offset / Scale;
1493      unsigned Mask = (1 << NumBits) - 1;
1494      if ((unsigned)Offset <= Mask * Scale) {
1495        // Replace the FrameIndex with sp
1496        MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
1497        if (isSub)
1498          ImmedOffset |= 1 << NumBits;
1499        ImmOp.ChangeToImmediate(ImmedOffset);
1500        Offset = 0;
1501        return true;
1502      }
1503
1504      // Otherwise, it didn't fit. Pull in what we can to simplify the immed.
1505      ImmedOffset = ImmedOffset & Mask;
1506      if (isSub)
1507        ImmedOffset |= 1 << NumBits;
1508      ImmOp.ChangeToImmediate(ImmedOffset);
1509      Offset &= ~(Mask*Scale);
1510    }
1511  }
1512
1513  Offset = (isSub) ? -Offset : Offset;
1514  return Offset == 0;
1515}
1516