ARMBaseInstrInfo.cpp revision a9fa4fd9736f7d1066223f32fa54efbe86c0fceb
1//===-- ARMBaseInstrInfo.cpp - ARM Instruction Information ----------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the Base ARM implementation of the TargetInstrInfo class. 11// 12//===----------------------------------------------------------------------===// 13 14#include "ARMBaseInstrInfo.h" 15#include "ARM.h" 16#include "ARMBaseRegisterInfo.h" 17#include "ARMConstantPoolValue.h" 18#include "ARMHazardRecognizer.h" 19#include "ARMMachineFunctionInfo.h" 20#include "MCTargetDesc/ARMAddressingModes.h" 21#include "llvm/Constants.h" 22#include "llvm/Function.h" 23#include "llvm/GlobalValue.h" 24#include "llvm/CodeGen/LiveVariables.h" 25#include "llvm/CodeGen/MachineConstantPool.h" 26#include "llvm/CodeGen/MachineFrameInfo.h" 27#include "llvm/CodeGen/MachineInstrBuilder.h" 28#include "llvm/CodeGen/MachineJumpTableInfo.h" 29#include "llvm/CodeGen/MachineMemOperand.h" 30#include "llvm/CodeGen/MachineRegisterInfo.h" 31#include "llvm/CodeGen/SelectionDAGNodes.h" 32#include "llvm/MC/MCAsmInfo.h" 33#include "llvm/Support/BranchProbability.h" 34#include "llvm/Support/CommandLine.h" 35#include "llvm/Support/Debug.h" 36#include "llvm/Support/ErrorHandling.h" 37#include "llvm/ADT/STLExtras.h" 38 39#define GET_INSTRINFO_CTOR 40#include "ARMGenInstrInfo.inc" 41 42using namespace llvm; 43 44static cl::opt<bool> 45EnableARM3Addr("enable-arm-3-addr-conv", cl::Hidden, 46 cl::desc("Enable ARM 2-addr to 3-addr conv")); 47 48static cl::opt<bool> 49WidenVMOVS("widen-vmovs", cl::Hidden, cl::init(true), 50 cl::desc("Widen ARM vmovs to vmovd when possible")); 51 52static cl::opt<unsigned> 53SwiftPartialUpdateClearance("swift-partial-update-clearance", 54 cl::Hidden, cl::init(12), 55 cl::desc("Clearance before partial register updates")); 56 57/// ARM_MLxEntry - Record information about MLA / MLS instructions. 58struct ARM_MLxEntry { 59 uint16_t MLxOpc; // MLA / MLS opcode 60 uint16_t MulOpc; // Expanded multiplication opcode 61 uint16_t AddSubOpc; // Expanded add / sub opcode 62 bool NegAcc; // True if the acc is negated before the add / sub. 63 bool HasLane; // True if instruction has an extra "lane" operand. 64}; 65 66static const ARM_MLxEntry ARM_MLxTable[] = { 67 // MLxOpc, MulOpc, AddSubOpc, NegAcc, HasLane 68 // fp scalar ops 69 { ARM::VMLAS, ARM::VMULS, ARM::VADDS, false, false }, 70 { ARM::VMLSS, ARM::VMULS, ARM::VSUBS, false, false }, 71 { ARM::VMLAD, ARM::VMULD, ARM::VADDD, false, false }, 72 { ARM::VMLSD, ARM::VMULD, ARM::VSUBD, false, false }, 73 { ARM::VNMLAS, ARM::VNMULS, ARM::VSUBS, true, false }, 74 { ARM::VNMLSS, ARM::VMULS, ARM::VSUBS, true, false }, 75 { ARM::VNMLAD, ARM::VNMULD, ARM::VSUBD, true, false }, 76 { ARM::VNMLSD, ARM::VMULD, ARM::VSUBD, true, false }, 77 78 // fp SIMD ops 79 { ARM::VMLAfd, ARM::VMULfd, ARM::VADDfd, false, false }, 80 { ARM::VMLSfd, ARM::VMULfd, ARM::VSUBfd, false, false }, 81 { ARM::VMLAfq, ARM::VMULfq, ARM::VADDfq, false, false }, 82 { ARM::VMLSfq, ARM::VMULfq, ARM::VSUBfq, false, false }, 83 { ARM::VMLAslfd, ARM::VMULslfd, ARM::VADDfd, false, true }, 84 { ARM::VMLSslfd, ARM::VMULslfd, ARM::VSUBfd, false, true }, 85 { ARM::VMLAslfq, ARM::VMULslfq, ARM::VADDfq, false, true }, 86 { ARM::VMLSslfq, ARM::VMULslfq, ARM::VSUBfq, false, true }, 87}; 88 89ARMBaseInstrInfo::ARMBaseInstrInfo(const ARMSubtarget& STI) 90 : ARMGenInstrInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP), 91 Subtarget(STI) { 92 for (unsigned i = 0, e = array_lengthof(ARM_MLxTable); i != e; ++i) { 93 if (!MLxEntryMap.insert(std::make_pair(ARM_MLxTable[i].MLxOpc, i)).second) 94 assert(false && "Duplicated entries?"); 95 MLxHazardOpcodes.insert(ARM_MLxTable[i].AddSubOpc); 96 MLxHazardOpcodes.insert(ARM_MLxTable[i].MulOpc); 97 } 98} 99 100// Use a ScoreboardHazardRecognizer for prepass ARM scheduling. TargetInstrImpl 101// currently defaults to no prepass hazard recognizer. 102ScheduleHazardRecognizer *ARMBaseInstrInfo:: 103CreateTargetHazardRecognizer(const TargetMachine *TM, 104 const ScheduleDAG *DAG) const { 105 if (usePreRAHazardRecognizer()) { 106 const InstrItineraryData *II = TM->getInstrItineraryData(); 107 return new ScoreboardHazardRecognizer(II, DAG, "pre-RA-sched"); 108 } 109 return TargetInstrInfo::CreateTargetHazardRecognizer(TM, DAG); 110} 111 112ScheduleHazardRecognizer *ARMBaseInstrInfo:: 113CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II, 114 const ScheduleDAG *DAG) const { 115 if (Subtarget.isThumb2() || Subtarget.hasVFP2()) 116 return (ScheduleHazardRecognizer *) 117 new ARMHazardRecognizer(II, *this, getRegisterInfo(), Subtarget, DAG); 118 return TargetInstrInfo::CreateTargetPostRAHazardRecognizer(II, DAG); 119} 120 121MachineInstr * 122ARMBaseInstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI, 123 MachineBasicBlock::iterator &MBBI, 124 LiveVariables *LV) const { 125 // FIXME: Thumb2 support. 126 127 if (!EnableARM3Addr) 128 return NULL; 129 130 MachineInstr *MI = MBBI; 131 MachineFunction &MF = *MI->getParent()->getParent(); 132 uint64_t TSFlags = MI->getDesc().TSFlags; 133 bool isPre = false; 134 switch ((TSFlags & ARMII::IndexModeMask) >> ARMII::IndexModeShift) { 135 default: return NULL; 136 case ARMII::IndexModePre: 137 isPre = true; 138 break; 139 case ARMII::IndexModePost: 140 break; 141 } 142 143 // Try splitting an indexed load/store to an un-indexed one plus an add/sub 144 // operation. 145 unsigned MemOpc = getUnindexedOpcode(MI->getOpcode()); 146 if (MemOpc == 0) 147 return NULL; 148 149 MachineInstr *UpdateMI = NULL; 150 MachineInstr *MemMI = NULL; 151 unsigned AddrMode = (TSFlags & ARMII::AddrModeMask); 152 const MCInstrDesc &MCID = MI->getDesc(); 153 unsigned NumOps = MCID.getNumOperands(); 154 bool isLoad = !MI->mayStore(); 155 const MachineOperand &WB = isLoad ? MI->getOperand(1) : MI->getOperand(0); 156 const MachineOperand &Base = MI->getOperand(2); 157 const MachineOperand &Offset = MI->getOperand(NumOps-3); 158 unsigned WBReg = WB.getReg(); 159 unsigned BaseReg = Base.getReg(); 160 unsigned OffReg = Offset.getReg(); 161 unsigned OffImm = MI->getOperand(NumOps-2).getImm(); 162 ARMCC::CondCodes Pred = (ARMCC::CondCodes)MI->getOperand(NumOps-1).getImm(); 163 switch (AddrMode) { 164 default: llvm_unreachable("Unknown indexed op!"); 165 case ARMII::AddrMode2: { 166 bool isSub = ARM_AM::getAM2Op(OffImm) == ARM_AM::sub; 167 unsigned Amt = ARM_AM::getAM2Offset(OffImm); 168 if (OffReg == 0) { 169 if (ARM_AM::getSOImmVal(Amt) == -1) 170 // Can't encode it in a so_imm operand. This transformation will 171 // add more than 1 instruction. Abandon! 172 return NULL; 173 UpdateMI = BuildMI(MF, MI->getDebugLoc(), 174 get(isSub ? ARM::SUBri : ARM::ADDri), WBReg) 175 .addReg(BaseReg).addImm(Amt) 176 .addImm(Pred).addReg(0).addReg(0); 177 } else if (Amt != 0) { 178 ARM_AM::ShiftOpc ShOpc = ARM_AM::getAM2ShiftOpc(OffImm); 179 unsigned SOOpc = ARM_AM::getSORegOpc(ShOpc, Amt); 180 UpdateMI = BuildMI(MF, MI->getDebugLoc(), 181 get(isSub ? ARM::SUBrsi : ARM::ADDrsi), WBReg) 182 .addReg(BaseReg).addReg(OffReg).addReg(0).addImm(SOOpc) 183 .addImm(Pred).addReg(0).addReg(0); 184 } else 185 UpdateMI = BuildMI(MF, MI->getDebugLoc(), 186 get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg) 187 .addReg(BaseReg).addReg(OffReg) 188 .addImm(Pred).addReg(0).addReg(0); 189 break; 190 } 191 case ARMII::AddrMode3 : { 192 bool isSub = ARM_AM::getAM3Op(OffImm) == ARM_AM::sub; 193 unsigned Amt = ARM_AM::getAM3Offset(OffImm); 194 if (OffReg == 0) 195 // Immediate is 8-bits. It's guaranteed to fit in a so_imm operand. 196 UpdateMI = BuildMI(MF, MI->getDebugLoc(), 197 get(isSub ? ARM::SUBri : ARM::ADDri), WBReg) 198 .addReg(BaseReg).addImm(Amt) 199 .addImm(Pred).addReg(0).addReg(0); 200 else 201 UpdateMI = BuildMI(MF, MI->getDebugLoc(), 202 get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg) 203 .addReg(BaseReg).addReg(OffReg) 204 .addImm(Pred).addReg(0).addReg(0); 205 break; 206 } 207 } 208 209 std::vector<MachineInstr*> NewMIs; 210 if (isPre) { 211 if (isLoad) 212 MemMI = BuildMI(MF, MI->getDebugLoc(), 213 get(MemOpc), MI->getOperand(0).getReg()) 214 .addReg(WBReg).addImm(0).addImm(Pred); 215 else 216 MemMI = BuildMI(MF, MI->getDebugLoc(), 217 get(MemOpc)).addReg(MI->getOperand(1).getReg()) 218 .addReg(WBReg).addReg(0).addImm(0).addImm(Pred); 219 NewMIs.push_back(MemMI); 220 NewMIs.push_back(UpdateMI); 221 } else { 222 if (isLoad) 223 MemMI = BuildMI(MF, MI->getDebugLoc(), 224 get(MemOpc), MI->getOperand(0).getReg()) 225 .addReg(BaseReg).addImm(0).addImm(Pred); 226 else 227 MemMI = BuildMI(MF, MI->getDebugLoc(), 228 get(MemOpc)).addReg(MI->getOperand(1).getReg()) 229 .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred); 230 if (WB.isDead()) 231 UpdateMI->getOperand(0).setIsDead(); 232 NewMIs.push_back(UpdateMI); 233 NewMIs.push_back(MemMI); 234 } 235 236 // Transfer LiveVariables states, kill / dead info. 237 if (LV) { 238 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 239 MachineOperand &MO = MI->getOperand(i); 240 if (MO.isReg() && TargetRegisterInfo::isVirtualRegister(MO.getReg())) { 241 unsigned Reg = MO.getReg(); 242 243 LiveVariables::VarInfo &VI = LV->getVarInfo(Reg); 244 if (MO.isDef()) { 245 MachineInstr *NewMI = (Reg == WBReg) ? UpdateMI : MemMI; 246 if (MO.isDead()) 247 LV->addVirtualRegisterDead(Reg, NewMI); 248 } 249 if (MO.isUse() && MO.isKill()) { 250 for (unsigned j = 0; j < 2; ++j) { 251 // Look at the two new MI's in reverse order. 252 MachineInstr *NewMI = NewMIs[j]; 253 if (!NewMI->readsRegister(Reg)) 254 continue; 255 LV->addVirtualRegisterKilled(Reg, NewMI); 256 if (VI.removeKill(MI)) 257 VI.Kills.push_back(NewMI); 258 break; 259 } 260 } 261 } 262 } 263 } 264 265 MFI->insert(MBBI, NewMIs[1]); 266 MFI->insert(MBBI, NewMIs[0]); 267 return NewMIs[0]; 268} 269 270// Branch analysis. 271bool 272ARMBaseInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB, 273 MachineBasicBlock *&FBB, 274 SmallVectorImpl<MachineOperand> &Cond, 275 bool AllowModify) const { 276 // If the block has no terminators, it just falls into the block after it. 277 MachineBasicBlock::iterator I = MBB.end(); 278 if (I == MBB.begin()) 279 return false; 280 --I; 281 while (I->isDebugValue()) { 282 if (I == MBB.begin()) 283 return false; 284 --I; 285 } 286 if (!isUnpredicatedTerminator(I)) 287 return false; 288 289 // Get the last instruction in the block. 290 MachineInstr *LastInst = I; 291 292 // If there is only one terminator instruction, process it. 293 unsigned LastOpc = LastInst->getOpcode(); 294 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) { 295 if (isUncondBranchOpcode(LastOpc)) { 296 TBB = LastInst->getOperand(0).getMBB(); 297 return false; 298 } 299 if (isCondBranchOpcode(LastOpc)) { 300 // Block ends with fall-through condbranch. 301 TBB = LastInst->getOperand(0).getMBB(); 302 Cond.push_back(LastInst->getOperand(1)); 303 Cond.push_back(LastInst->getOperand(2)); 304 return false; 305 } 306 return true; // Can't handle indirect branch. 307 } 308 309 // Get the instruction before it if it is a terminator. 310 MachineInstr *SecondLastInst = I; 311 unsigned SecondLastOpc = SecondLastInst->getOpcode(); 312 313 // If AllowModify is true and the block ends with two or more unconditional 314 // branches, delete all but the first unconditional branch. 315 if (AllowModify && isUncondBranchOpcode(LastOpc)) { 316 while (isUncondBranchOpcode(SecondLastOpc)) { 317 LastInst->eraseFromParent(); 318 LastInst = SecondLastInst; 319 LastOpc = LastInst->getOpcode(); 320 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) { 321 // Return now the only terminator is an unconditional branch. 322 TBB = LastInst->getOperand(0).getMBB(); 323 return false; 324 } else { 325 SecondLastInst = I; 326 SecondLastOpc = SecondLastInst->getOpcode(); 327 } 328 } 329 } 330 331 // If there are three terminators, we don't know what sort of block this is. 332 if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(--I)) 333 return true; 334 335 // If the block ends with a B and a Bcc, handle it. 336 if (isCondBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) { 337 TBB = SecondLastInst->getOperand(0).getMBB(); 338 Cond.push_back(SecondLastInst->getOperand(1)); 339 Cond.push_back(SecondLastInst->getOperand(2)); 340 FBB = LastInst->getOperand(0).getMBB(); 341 return false; 342 } 343 344 // If the block ends with two unconditional branches, handle it. The second 345 // one is not executed, so remove it. 346 if (isUncondBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) { 347 TBB = SecondLastInst->getOperand(0).getMBB(); 348 I = LastInst; 349 if (AllowModify) 350 I->eraseFromParent(); 351 return false; 352 } 353 354 // ...likewise if it ends with a branch table followed by an unconditional 355 // branch. The branch folder can create these, and we must get rid of them for 356 // correctness of Thumb constant islands. 357 if ((isJumpTableBranchOpcode(SecondLastOpc) || 358 isIndirectBranchOpcode(SecondLastOpc)) && 359 isUncondBranchOpcode(LastOpc)) { 360 I = LastInst; 361 if (AllowModify) 362 I->eraseFromParent(); 363 return true; 364 } 365 366 // Otherwise, can't handle this. 367 return true; 368} 369 370 371unsigned ARMBaseInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const { 372 MachineBasicBlock::iterator I = MBB.end(); 373 if (I == MBB.begin()) return 0; 374 --I; 375 while (I->isDebugValue()) { 376 if (I == MBB.begin()) 377 return 0; 378 --I; 379 } 380 if (!isUncondBranchOpcode(I->getOpcode()) && 381 !isCondBranchOpcode(I->getOpcode())) 382 return 0; 383 384 // Remove the branch. 385 I->eraseFromParent(); 386 387 I = MBB.end(); 388 389 if (I == MBB.begin()) return 1; 390 --I; 391 if (!isCondBranchOpcode(I->getOpcode())) 392 return 1; 393 394 // Remove the branch. 395 I->eraseFromParent(); 396 return 2; 397} 398 399unsigned 400ARMBaseInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 401 MachineBasicBlock *FBB, 402 const SmallVectorImpl<MachineOperand> &Cond, 403 DebugLoc DL) const { 404 ARMFunctionInfo *AFI = MBB.getParent()->getInfo<ARMFunctionInfo>(); 405 int BOpc = !AFI->isThumbFunction() 406 ? ARM::B : (AFI->isThumb2Function() ? ARM::t2B : ARM::tB); 407 int BccOpc = !AFI->isThumbFunction() 408 ? ARM::Bcc : (AFI->isThumb2Function() ? ARM::t2Bcc : ARM::tBcc); 409 bool isThumb = AFI->isThumbFunction() || AFI->isThumb2Function(); 410 411 // Shouldn't be a fall through. 412 assert(TBB && "InsertBranch must not be told to insert a fallthrough"); 413 assert((Cond.size() == 2 || Cond.size() == 0) && 414 "ARM branch conditions have two components!"); 415 416 if (FBB == 0) { 417 if (Cond.empty()) { // Unconditional branch? 418 if (isThumb) 419 BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB).addImm(ARMCC::AL).addReg(0); 420 else 421 BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB); 422 } else 423 BuildMI(&MBB, DL, get(BccOpc)).addMBB(TBB) 424 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()); 425 return 1; 426 } 427 428 // Two-way conditional branch. 429 BuildMI(&MBB, DL, get(BccOpc)).addMBB(TBB) 430 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()); 431 if (isThumb) 432 BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB).addImm(ARMCC::AL).addReg(0); 433 else 434 BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB); 435 return 2; 436} 437 438bool ARMBaseInstrInfo:: 439ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const { 440 ARMCC::CondCodes CC = (ARMCC::CondCodes)(int)Cond[0].getImm(); 441 Cond[0].setImm(ARMCC::getOppositeCondition(CC)); 442 return false; 443} 444 445bool ARMBaseInstrInfo::isPredicated(const MachineInstr *MI) const { 446 if (MI->isBundle()) { 447 MachineBasicBlock::const_instr_iterator I = MI; 448 MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end(); 449 while (++I != E && I->isInsideBundle()) { 450 int PIdx = I->findFirstPredOperandIdx(); 451 if (PIdx != -1 && I->getOperand(PIdx).getImm() != ARMCC::AL) 452 return true; 453 } 454 return false; 455 } 456 457 int PIdx = MI->findFirstPredOperandIdx(); 458 return PIdx != -1 && MI->getOperand(PIdx).getImm() != ARMCC::AL; 459} 460 461bool ARMBaseInstrInfo:: 462PredicateInstruction(MachineInstr *MI, 463 const SmallVectorImpl<MachineOperand> &Pred) const { 464 unsigned Opc = MI->getOpcode(); 465 if (isUncondBranchOpcode(Opc)) { 466 MI->setDesc(get(getMatchingCondBranchOpcode(Opc))); 467 MI->addOperand(MachineOperand::CreateImm(Pred[0].getImm())); 468 MI->addOperand(MachineOperand::CreateReg(Pred[1].getReg(), false)); 469 return true; 470 } 471 472 int PIdx = MI->findFirstPredOperandIdx(); 473 if (PIdx != -1) { 474 MachineOperand &PMO = MI->getOperand(PIdx); 475 PMO.setImm(Pred[0].getImm()); 476 MI->getOperand(PIdx+1).setReg(Pred[1].getReg()); 477 return true; 478 } 479 return false; 480} 481 482bool ARMBaseInstrInfo:: 483SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1, 484 const SmallVectorImpl<MachineOperand> &Pred2) const { 485 if (Pred1.size() > 2 || Pred2.size() > 2) 486 return false; 487 488 ARMCC::CondCodes CC1 = (ARMCC::CondCodes)Pred1[0].getImm(); 489 ARMCC::CondCodes CC2 = (ARMCC::CondCodes)Pred2[0].getImm(); 490 if (CC1 == CC2) 491 return true; 492 493 switch (CC1) { 494 default: 495 return false; 496 case ARMCC::AL: 497 return true; 498 case ARMCC::HS: 499 return CC2 == ARMCC::HI; 500 case ARMCC::LS: 501 return CC2 == ARMCC::LO || CC2 == ARMCC::EQ; 502 case ARMCC::GE: 503 return CC2 == ARMCC::GT; 504 case ARMCC::LE: 505 return CC2 == ARMCC::LT; 506 } 507} 508 509bool ARMBaseInstrInfo::DefinesPredicate(MachineInstr *MI, 510 std::vector<MachineOperand> &Pred) const { 511 bool Found = false; 512 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 513 const MachineOperand &MO = MI->getOperand(i); 514 if ((MO.isRegMask() && MO.clobbersPhysReg(ARM::CPSR)) || 515 (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR)) { 516 Pred.push_back(MO); 517 Found = true; 518 } 519 } 520 521 return Found; 522} 523 524/// isPredicable - Return true if the specified instruction can be predicated. 525/// By default, this returns true for every instruction with a 526/// PredicateOperand. 527bool ARMBaseInstrInfo::isPredicable(MachineInstr *MI) const { 528 if (!MI->isPredicable()) 529 return false; 530 531 if ((MI->getDesc().TSFlags & ARMII::DomainMask) == ARMII::DomainNEON) { 532 ARMFunctionInfo *AFI = 533 MI->getParent()->getParent()->getInfo<ARMFunctionInfo>(); 534 return AFI->isThumb2Function(); 535 } 536 return true; 537} 538 539/// FIXME: Works around a gcc miscompilation with -fstrict-aliasing. 540LLVM_ATTRIBUTE_NOINLINE 541static unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT, 542 unsigned JTI); 543static unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT, 544 unsigned JTI) { 545 assert(JTI < JT.size()); 546 return JT[JTI].MBBs.size(); 547} 548 549/// GetInstSize - Return the size of the specified MachineInstr. 550/// 551unsigned ARMBaseInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const { 552 const MachineBasicBlock &MBB = *MI->getParent(); 553 const MachineFunction *MF = MBB.getParent(); 554 const MCAsmInfo *MAI = MF->getTarget().getMCAsmInfo(); 555 556 const MCInstrDesc &MCID = MI->getDesc(); 557 if (MCID.getSize()) 558 return MCID.getSize(); 559 560 // If this machine instr is an inline asm, measure it. 561 if (MI->getOpcode() == ARM::INLINEASM) 562 return getInlineAsmLength(MI->getOperand(0).getSymbolName(), *MAI); 563 if (MI->isLabel()) 564 return 0; 565 unsigned Opc = MI->getOpcode(); 566 switch (Opc) { 567 case TargetOpcode::IMPLICIT_DEF: 568 case TargetOpcode::KILL: 569 case TargetOpcode::PROLOG_LABEL: 570 case TargetOpcode::EH_LABEL: 571 case TargetOpcode::DBG_VALUE: 572 return 0; 573 case TargetOpcode::BUNDLE: 574 return getInstBundleLength(MI); 575 case ARM::MOVi16_ga_pcrel: 576 case ARM::MOVTi16_ga_pcrel: 577 case ARM::t2MOVi16_ga_pcrel: 578 case ARM::t2MOVTi16_ga_pcrel: 579 return 4; 580 case ARM::MOVi32imm: 581 case ARM::t2MOVi32imm: 582 return 8; 583 case ARM::CONSTPOOL_ENTRY: 584 // If this machine instr is a constant pool entry, its size is recorded as 585 // operand #2. 586 return MI->getOperand(2).getImm(); 587 case ARM::Int_eh_sjlj_longjmp: 588 return 16; 589 case ARM::tInt_eh_sjlj_longjmp: 590 return 10; 591 case ARM::Int_eh_sjlj_setjmp: 592 case ARM::Int_eh_sjlj_setjmp_nofp: 593 return 20; 594 case ARM::tInt_eh_sjlj_setjmp: 595 case ARM::t2Int_eh_sjlj_setjmp: 596 case ARM::t2Int_eh_sjlj_setjmp_nofp: 597 return 12; 598 case ARM::BR_JTr: 599 case ARM::BR_JTm: 600 case ARM::BR_JTadd: 601 case ARM::tBR_JTr: 602 case ARM::t2BR_JT: 603 case ARM::t2TBB_JT: 604 case ARM::t2TBH_JT: { 605 // These are jumptable branches, i.e. a branch followed by an inlined 606 // jumptable. The size is 4 + 4 * number of entries. For TBB, each 607 // entry is one byte; TBH two byte each. 608 unsigned EntrySize = (Opc == ARM::t2TBB_JT) 609 ? 1 : ((Opc == ARM::t2TBH_JT) ? 2 : 4); 610 unsigned NumOps = MCID.getNumOperands(); 611 MachineOperand JTOP = 612 MI->getOperand(NumOps - (MI->isPredicable() ? 3 : 2)); 613 unsigned JTI = JTOP.getIndex(); 614 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo(); 615 assert(MJTI != 0); 616 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables(); 617 assert(JTI < JT.size()); 618 // Thumb instructions are 2 byte aligned, but JT entries are 4 byte 619 // 4 aligned. The assembler / linker may add 2 byte padding just before 620 // the JT entries. The size does not include this padding; the 621 // constant islands pass does separate bookkeeping for it. 622 // FIXME: If we know the size of the function is less than (1 << 16) *2 623 // bytes, we can use 16-bit entries instead. Then there won't be an 624 // alignment issue. 625 unsigned InstSize = (Opc == ARM::tBR_JTr || Opc == ARM::t2BR_JT) ? 2 : 4; 626 unsigned NumEntries = getNumJTEntries(JT, JTI); 627 if (Opc == ARM::t2TBB_JT && (NumEntries & 1)) 628 // Make sure the instruction that follows TBB is 2-byte aligned. 629 // FIXME: Constant island pass should insert an "ALIGN" instruction 630 // instead. 631 ++NumEntries; 632 return NumEntries * EntrySize + InstSize; 633 } 634 default: 635 // Otherwise, pseudo-instruction sizes are zero. 636 return 0; 637 } 638} 639 640unsigned ARMBaseInstrInfo::getInstBundleLength(const MachineInstr *MI) const { 641 unsigned Size = 0; 642 MachineBasicBlock::const_instr_iterator I = MI; 643 MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end(); 644 while (++I != E && I->isInsideBundle()) { 645 assert(!I->isBundle() && "No nested bundle!"); 646 Size += GetInstSizeInBytes(&*I); 647 } 648 return Size; 649} 650 651void ARMBaseInstrInfo::copyPhysReg(MachineBasicBlock &MBB, 652 MachineBasicBlock::iterator I, DebugLoc DL, 653 unsigned DestReg, unsigned SrcReg, 654 bool KillSrc) const { 655 bool GPRDest = ARM::GPRRegClass.contains(DestReg); 656 bool GPRSrc = ARM::GPRRegClass.contains(SrcReg); 657 658 if (GPRDest && GPRSrc) { 659 AddDefaultCC(AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::MOVr), DestReg) 660 .addReg(SrcReg, getKillRegState(KillSrc)))); 661 return; 662 } 663 664 bool SPRDest = ARM::SPRRegClass.contains(DestReg); 665 bool SPRSrc = ARM::SPRRegClass.contains(SrcReg); 666 667 unsigned Opc = 0; 668 if (SPRDest && SPRSrc) 669 Opc = ARM::VMOVS; 670 else if (GPRDest && SPRSrc) 671 Opc = ARM::VMOVRS; 672 else if (SPRDest && GPRSrc) 673 Opc = ARM::VMOVSR; 674 else if (ARM::DPRRegClass.contains(DestReg, SrcReg)) 675 Opc = ARM::VMOVD; 676 else if (ARM::QPRRegClass.contains(DestReg, SrcReg)) 677 Opc = ARM::VORRq; 678 679 if (Opc) { 680 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc), DestReg); 681 MIB.addReg(SrcReg, getKillRegState(KillSrc)); 682 if (Opc == ARM::VORRq) 683 MIB.addReg(SrcReg, getKillRegState(KillSrc)); 684 AddDefaultPred(MIB); 685 return; 686 } 687 688 // Handle register classes that require multiple instructions. 689 unsigned BeginIdx = 0; 690 unsigned SubRegs = 0; 691 int Spacing = 1; 692 693 // Use VORRq when possible. 694 if (ARM::QQPRRegClass.contains(DestReg, SrcReg)) 695 Opc = ARM::VORRq, BeginIdx = ARM::qsub_0, SubRegs = 2; 696 else if (ARM::QQQQPRRegClass.contains(DestReg, SrcReg)) 697 Opc = ARM::VORRq, BeginIdx = ARM::qsub_0, SubRegs = 4; 698 // Fall back to VMOVD. 699 else if (ARM::DPairRegClass.contains(DestReg, SrcReg)) 700 Opc = ARM::VMOVD, BeginIdx = ARM::dsub_0, SubRegs = 2; 701 else if (ARM::DTripleRegClass.contains(DestReg, SrcReg)) 702 Opc = ARM::VMOVD, BeginIdx = ARM::dsub_0, SubRegs = 3; 703 else if (ARM::DQuadRegClass.contains(DestReg, SrcReg)) 704 Opc = ARM::VMOVD, BeginIdx = ARM::dsub_0, SubRegs = 4; 705 else if (ARM::GPRPairRegClass.contains(DestReg, SrcReg)) 706 Opc = ARM::MOVr, BeginIdx = ARM::gsub_0, SubRegs = 2; 707 708 else if (ARM::DPairSpcRegClass.contains(DestReg, SrcReg)) 709 Opc = ARM::VMOVD, BeginIdx = ARM::dsub_0, SubRegs = 2, Spacing = 2; 710 else if (ARM::DTripleSpcRegClass.contains(DestReg, SrcReg)) 711 Opc = ARM::VMOVD, BeginIdx = ARM::dsub_0, SubRegs = 3, Spacing = 2; 712 else if (ARM::DQuadSpcRegClass.contains(DestReg, SrcReg)) 713 Opc = ARM::VMOVD, BeginIdx = ARM::dsub_0, SubRegs = 4, Spacing = 2; 714 715 assert(Opc && "Impossible reg-to-reg copy"); 716 717 const TargetRegisterInfo *TRI = &getRegisterInfo(); 718 MachineInstrBuilder Mov; 719 720 // Copy register tuples backward when the first Dest reg overlaps with SrcReg. 721 if (TRI->regsOverlap(SrcReg, TRI->getSubReg(DestReg, BeginIdx))) { 722 BeginIdx = BeginIdx + ((SubRegs-1)*Spacing); 723 Spacing = -Spacing; 724 } 725#ifndef NDEBUG 726 SmallSet<unsigned, 4> DstRegs; 727#endif 728 for (unsigned i = 0; i != SubRegs; ++i) { 729 unsigned Dst = TRI->getSubReg(DestReg, BeginIdx + i*Spacing); 730 unsigned Src = TRI->getSubReg(SrcReg, BeginIdx + i*Spacing); 731 assert(Dst && Src && "Bad sub-register"); 732#ifndef NDEBUG 733 assert(!DstRegs.count(Src) && "destructive vector copy"); 734 DstRegs.insert(Dst); 735#endif 736 Mov = BuildMI(MBB, I, I->getDebugLoc(), get(Opc), Dst) 737 .addReg(Src); 738 // VORR takes two source operands. 739 if (Opc == ARM::VORRq) 740 Mov.addReg(Src); 741 Mov = AddDefaultPred(Mov); 742 } 743 // Add implicit super-register defs and kills to the last instruction. 744 Mov->addRegisterDefined(DestReg, TRI); 745 if (KillSrc) 746 Mov->addRegisterKilled(SrcReg, TRI); 747} 748 749static const 750MachineInstrBuilder &AddDReg(MachineInstrBuilder &MIB, 751 unsigned Reg, unsigned SubIdx, unsigned State, 752 const TargetRegisterInfo *TRI) { 753 if (!SubIdx) 754 return MIB.addReg(Reg, State); 755 756 if (TargetRegisterInfo::isPhysicalRegister(Reg)) 757 return MIB.addReg(TRI->getSubReg(Reg, SubIdx), State); 758 return MIB.addReg(Reg, State, SubIdx); 759} 760 761void ARMBaseInstrInfo:: 762storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 763 unsigned SrcReg, bool isKill, int FI, 764 const TargetRegisterClass *RC, 765 const TargetRegisterInfo *TRI) const { 766 DebugLoc DL; 767 if (I != MBB.end()) DL = I->getDebugLoc(); 768 MachineFunction &MF = *MBB.getParent(); 769 MachineFrameInfo &MFI = *MF.getFrameInfo(); 770 unsigned Align = MFI.getObjectAlignment(FI); 771 772 MachineMemOperand *MMO = 773 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FI), 774 MachineMemOperand::MOStore, 775 MFI.getObjectSize(FI), 776 Align); 777 778 switch (RC->getSize()) { 779 case 4: 780 if (ARM::GPRRegClass.hasSubClassEq(RC)) { 781 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::STRi12)) 782 .addReg(SrcReg, getKillRegState(isKill)) 783 .addFrameIndex(FI).addImm(0).addMemOperand(MMO)); 784 } else if (ARM::SPRRegClass.hasSubClassEq(RC)) { 785 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTRS)) 786 .addReg(SrcReg, getKillRegState(isKill)) 787 .addFrameIndex(FI).addImm(0).addMemOperand(MMO)); 788 } else 789 llvm_unreachable("Unknown reg class!"); 790 break; 791 case 8: 792 if (ARM::DPRRegClass.hasSubClassEq(RC)) { 793 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTRD)) 794 .addReg(SrcReg, getKillRegState(isKill)) 795 .addFrameIndex(FI).addImm(0).addMemOperand(MMO)); 796 } else if (ARM::GPRPairRegClass.hasSubClassEq(RC)) { 797 MachineInstrBuilder MIB = 798 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::STMIA)) 799 .addFrameIndex(FI)) 800 .addMemOperand(MMO); 801 MIB = AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill), TRI); 802 AddDReg(MIB, SrcReg, ARM::gsub_1, 0, TRI); 803 } else 804 llvm_unreachable("Unknown reg class!"); 805 break; 806 case 16: 807 if (ARM::DPairRegClass.hasSubClassEq(RC)) { 808 // Use aligned spills if the stack can be realigned. 809 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) { 810 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1q64)) 811 .addFrameIndex(FI).addImm(16) 812 .addReg(SrcReg, getKillRegState(isKill)) 813 .addMemOperand(MMO)); 814 } else { 815 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMQIA)) 816 .addReg(SrcReg, getKillRegState(isKill)) 817 .addFrameIndex(FI) 818 .addMemOperand(MMO)); 819 } 820 } else 821 llvm_unreachable("Unknown reg class!"); 822 break; 823 case 24: 824 if (ARM::DTripleRegClass.hasSubClassEq(RC)) { 825 // Use aligned spills if the stack can be realigned. 826 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) { 827 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1d64TPseudo)) 828 .addFrameIndex(FI).addImm(16) 829 .addReg(SrcReg, getKillRegState(isKill)) 830 .addMemOperand(MMO)); 831 } else { 832 MachineInstrBuilder MIB = 833 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMDIA)) 834 .addFrameIndex(FI)) 835 .addMemOperand(MMO); 836 MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI); 837 MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI); 838 AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI); 839 } 840 } else 841 llvm_unreachable("Unknown reg class!"); 842 break; 843 case 32: 844 if (ARM::QQPRRegClass.hasSubClassEq(RC) || ARM::DQuadRegClass.hasSubClassEq(RC)) { 845 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) { 846 // FIXME: It's possible to only store part of the QQ register if the 847 // spilled def has a sub-register index. 848 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1d64QPseudo)) 849 .addFrameIndex(FI).addImm(16) 850 .addReg(SrcReg, getKillRegState(isKill)) 851 .addMemOperand(MMO)); 852 } else { 853 MachineInstrBuilder MIB = 854 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMDIA)) 855 .addFrameIndex(FI)) 856 .addMemOperand(MMO); 857 MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI); 858 MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI); 859 MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI); 860 AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI); 861 } 862 } else 863 llvm_unreachable("Unknown reg class!"); 864 break; 865 case 64: 866 if (ARM::QQQQPRRegClass.hasSubClassEq(RC)) { 867 MachineInstrBuilder MIB = 868 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMDIA)) 869 .addFrameIndex(FI)) 870 .addMemOperand(MMO); 871 MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI); 872 MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI); 873 MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI); 874 MIB = AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI); 875 MIB = AddDReg(MIB, SrcReg, ARM::dsub_4, 0, TRI); 876 MIB = AddDReg(MIB, SrcReg, ARM::dsub_5, 0, TRI); 877 MIB = AddDReg(MIB, SrcReg, ARM::dsub_6, 0, TRI); 878 AddDReg(MIB, SrcReg, ARM::dsub_7, 0, TRI); 879 } else 880 llvm_unreachable("Unknown reg class!"); 881 break; 882 default: 883 llvm_unreachable("Unknown reg class!"); 884 } 885} 886 887unsigned 888ARMBaseInstrInfo::isStoreToStackSlot(const MachineInstr *MI, 889 int &FrameIndex) const { 890 switch (MI->getOpcode()) { 891 default: break; 892 case ARM::STRrs: 893 case ARM::t2STRs: // FIXME: don't use t2STRs to access frame. 894 if (MI->getOperand(1).isFI() && 895 MI->getOperand(2).isReg() && 896 MI->getOperand(3).isImm() && 897 MI->getOperand(2).getReg() == 0 && 898 MI->getOperand(3).getImm() == 0) { 899 FrameIndex = MI->getOperand(1).getIndex(); 900 return MI->getOperand(0).getReg(); 901 } 902 break; 903 case ARM::STRi12: 904 case ARM::t2STRi12: 905 case ARM::tSTRspi: 906 case ARM::VSTRD: 907 case ARM::VSTRS: 908 if (MI->getOperand(1).isFI() && 909 MI->getOperand(2).isImm() && 910 MI->getOperand(2).getImm() == 0) { 911 FrameIndex = MI->getOperand(1).getIndex(); 912 return MI->getOperand(0).getReg(); 913 } 914 break; 915 case ARM::VST1q64: 916 case ARM::VST1d64TPseudo: 917 case ARM::VST1d64QPseudo: 918 if (MI->getOperand(0).isFI() && 919 MI->getOperand(2).getSubReg() == 0) { 920 FrameIndex = MI->getOperand(0).getIndex(); 921 return MI->getOperand(2).getReg(); 922 } 923 break; 924 case ARM::VSTMQIA: 925 if (MI->getOperand(1).isFI() && 926 MI->getOperand(0).getSubReg() == 0) { 927 FrameIndex = MI->getOperand(1).getIndex(); 928 return MI->getOperand(0).getReg(); 929 } 930 break; 931 } 932 933 return 0; 934} 935 936unsigned ARMBaseInstrInfo::isStoreToStackSlotPostFE(const MachineInstr *MI, 937 int &FrameIndex) const { 938 const MachineMemOperand *Dummy; 939 return MI->mayStore() && hasStoreToStackSlot(MI, Dummy, FrameIndex); 940} 941 942void ARMBaseInstrInfo:: 943loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 944 unsigned DestReg, int FI, 945 const TargetRegisterClass *RC, 946 const TargetRegisterInfo *TRI) const { 947 DebugLoc DL; 948 if (I != MBB.end()) DL = I->getDebugLoc(); 949 MachineFunction &MF = *MBB.getParent(); 950 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 951 MachineFrameInfo &MFI = *MF.getFrameInfo(); 952 unsigned Align = MFI.getObjectAlignment(FI); 953 MachineMemOperand *MMO = 954 MF.getMachineMemOperand( 955 MachinePointerInfo::getFixedStack(FI), 956 MachineMemOperand::MOLoad, 957 MFI.getObjectSize(FI), 958 Align); 959 960 switch (RC->getSize()) { 961 case 4: 962 if (ARM::GPRRegClass.hasSubClassEq(RC)) { 963 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::LDRi12), DestReg) 964 .addFrameIndex(FI).addImm(0).addMemOperand(MMO)); 965 966 } else if (ARM::SPRRegClass.hasSubClassEq(RC)) { 967 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRS), DestReg) 968 .addFrameIndex(FI).addImm(0).addMemOperand(MMO)); 969 } else 970 llvm_unreachable("Unknown reg class!"); 971 break; 972 case 8: 973 if (ARM::DPRRegClass.hasSubClassEq(RC)) { 974 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRD), DestReg) 975 .addFrameIndex(FI).addImm(0).addMemOperand(MMO)); 976 } else if (ARM::GPRPairRegClass.hasSubClassEq(RC)) { 977 unsigned LdmOpc = AFI->isThumbFunction() ? ARM::t2LDMIA : ARM::LDMIA; 978 MachineInstrBuilder MIB = 979 AddDefaultPred(BuildMI(MBB, I, DL, get(LdmOpc)) 980 .addFrameIndex(FI).addImm(0).addMemOperand(MMO)); 981 MIB = AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI); 982 MIB = AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI); 983 if (TargetRegisterInfo::isPhysicalRegister(DestReg)) 984 MIB.addReg(DestReg, RegState::ImplicitDefine); 985 } else 986 llvm_unreachable("Unknown reg class!"); 987 break; 988 case 16: 989 if (ARM::DPairRegClass.hasSubClassEq(RC)) { 990 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) { 991 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1q64), DestReg) 992 .addFrameIndex(FI).addImm(16) 993 .addMemOperand(MMO)); 994 } else { 995 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMQIA), DestReg) 996 .addFrameIndex(FI) 997 .addMemOperand(MMO)); 998 } 999 } else 1000 llvm_unreachable("Unknown reg class!"); 1001 break; 1002 case 24: 1003 if (ARM::DTripleRegClass.hasSubClassEq(RC)) { 1004 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) { 1005 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1d64TPseudo), DestReg) 1006 .addFrameIndex(FI).addImm(16) 1007 .addMemOperand(MMO)); 1008 } else { 1009 MachineInstrBuilder MIB = 1010 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMDIA)) 1011 .addFrameIndex(FI) 1012 .addMemOperand(MMO)); 1013 MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI); 1014 MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI); 1015 MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI); 1016 if (TargetRegisterInfo::isPhysicalRegister(DestReg)) 1017 MIB.addReg(DestReg, RegState::ImplicitDefine); 1018 } 1019 } else 1020 llvm_unreachable("Unknown reg class!"); 1021 break; 1022 case 32: 1023 if (ARM::QQPRRegClass.hasSubClassEq(RC) || ARM::DQuadRegClass.hasSubClassEq(RC)) { 1024 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) { 1025 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1d64QPseudo), DestReg) 1026 .addFrameIndex(FI).addImm(16) 1027 .addMemOperand(MMO)); 1028 } else { 1029 MachineInstrBuilder MIB = 1030 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMDIA)) 1031 .addFrameIndex(FI)) 1032 .addMemOperand(MMO); 1033 MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI); 1034 MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI); 1035 MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI); 1036 MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::DefineNoRead, TRI); 1037 if (TargetRegisterInfo::isPhysicalRegister(DestReg)) 1038 MIB.addReg(DestReg, RegState::ImplicitDefine); 1039 } 1040 } else 1041 llvm_unreachable("Unknown reg class!"); 1042 break; 1043 case 64: 1044 if (ARM::QQQQPRRegClass.hasSubClassEq(RC)) { 1045 MachineInstrBuilder MIB = 1046 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMDIA)) 1047 .addFrameIndex(FI)) 1048 .addMemOperand(MMO); 1049 MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI); 1050 MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI); 1051 MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI); 1052 MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::DefineNoRead, TRI); 1053 MIB = AddDReg(MIB, DestReg, ARM::dsub_4, RegState::DefineNoRead, TRI); 1054 MIB = AddDReg(MIB, DestReg, ARM::dsub_5, RegState::DefineNoRead, TRI); 1055 MIB = AddDReg(MIB, DestReg, ARM::dsub_6, RegState::DefineNoRead, TRI); 1056 MIB = AddDReg(MIB, DestReg, ARM::dsub_7, RegState::DefineNoRead, TRI); 1057 if (TargetRegisterInfo::isPhysicalRegister(DestReg)) 1058 MIB.addReg(DestReg, RegState::ImplicitDefine); 1059 } else 1060 llvm_unreachable("Unknown reg class!"); 1061 break; 1062 default: 1063 llvm_unreachable("Unknown regclass!"); 1064 } 1065} 1066 1067unsigned 1068ARMBaseInstrInfo::isLoadFromStackSlot(const MachineInstr *MI, 1069 int &FrameIndex) const { 1070 switch (MI->getOpcode()) { 1071 default: break; 1072 case ARM::LDRrs: 1073 case ARM::t2LDRs: // FIXME: don't use t2LDRs to access frame. 1074 if (MI->getOperand(1).isFI() && 1075 MI->getOperand(2).isReg() && 1076 MI->getOperand(3).isImm() && 1077 MI->getOperand(2).getReg() == 0 && 1078 MI->getOperand(3).getImm() == 0) { 1079 FrameIndex = MI->getOperand(1).getIndex(); 1080 return MI->getOperand(0).getReg(); 1081 } 1082 break; 1083 case ARM::LDRi12: 1084 case ARM::t2LDRi12: 1085 case ARM::tLDRspi: 1086 case ARM::VLDRD: 1087 case ARM::VLDRS: 1088 if (MI->getOperand(1).isFI() && 1089 MI->getOperand(2).isImm() && 1090 MI->getOperand(2).getImm() == 0) { 1091 FrameIndex = MI->getOperand(1).getIndex(); 1092 return MI->getOperand(0).getReg(); 1093 } 1094 break; 1095 case ARM::VLD1q64: 1096 case ARM::VLD1d64TPseudo: 1097 case ARM::VLD1d64QPseudo: 1098 if (MI->getOperand(1).isFI() && 1099 MI->getOperand(0).getSubReg() == 0) { 1100 FrameIndex = MI->getOperand(1).getIndex(); 1101 return MI->getOperand(0).getReg(); 1102 } 1103 break; 1104 case ARM::VLDMQIA: 1105 if (MI->getOperand(1).isFI() && 1106 MI->getOperand(0).getSubReg() == 0) { 1107 FrameIndex = MI->getOperand(1).getIndex(); 1108 return MI->getOperand(0).getReg(); 1109 } 1110 break; 1111 } 1112 1113 return 0; 1114} 1115 1116unsigned ARMBaseInstrInfo::isLoadFromStackSlotPostFE(const MachineInstr *MI, 1117 int &FrameIndex) const { 1118 const MachineMemOperand *Dummy; 1119 return MI->mayLoad() && hasLoadFromStackSlot(MI, Dummy, FrameIndex); 1120} 1121 1122bool ARMBaseInstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const{ 1123 // This hook gets to expand COPY instructions before they become 1124 // copyPhysReg() calls. Look for VMOVS instructions that can legally be 1125 // widened to VMOVD. We prefer the VMOVD when possible because it may be 1126 // changed into a VORR that can go down the NEON pipeline. 1127 if (!WidenVMOVS || !MI->isCopy()) 1128 return false; 1129 1130 // Look for a copy between even S-registers. That is where we keep floats 1131 // when using NEON v2f32 instructions for f32 arithmetic. 1132 unsigned DstRegS = MI->getOperand(0).getReg(); 1133 unsigned SrcRegS = MI->getOperand(1).getReg(); 1134 if (!ARM::SPRRegClass.contains(DstRegS, SrcRegS)) 1135 return false; 1136 1137 const TargetRegisterInfo *TRI = &getRegisterInfo(); 1138 unsigned DstRegD = TRI->getMatchingSuperReg(DstRegS, ARM::ssub_0, 1139 &ARM::DPRRegClass); 1140 unsigned SrcRegD = TRI->getMatchingSuperReg(SrcRegS, ARM::ssub_0, 1141 &ARM::DPRRegClass); 1142 if (!DstRegD || !SrcRegD) 1143 return false; 1144 1145 // We want to widen this into a DstRegD = VMOVD SrcRegD copy. This is only 1146 // legal if the COPY already defines the full DstRegD, and it isn't a 1147 // sub-register insertion. 1148 if (!MI->definesRegister(DstRegD, TRI) || MI->readsRegister(DstRegD, TRI)) 1149 return false; 1150 1151 // A dead copy shouldn't show up here, but reject it just in case. 1152 if (MI->getOperand(0).isDead()) 1153 return false; 1154 1155 // All clear, widen the COPY. 1156 DEBUG(dbgs() << "widening: " << *MI); 1157 1158 // Get rid of the old <imp-def> of DstRegD. Leave it if it defines a Q-reg 1159 // or some other super-register. 1160 int ImpDefIdx = MI->findRegisterDefOperandIdx(DstRegD); 1161 if (ImpDefIdx != -1) 1162 MI->RemoveOperand(ImpDefIdx); 1163 1164 // Change the opcode and operands. 1165 MI->setDesc(get(ARM::VMOVD)); 1166 MI->getOperand(0).setReg(DstRegD); 1167 MI->getOperand(1).setReg(SrcRegD); 1168 AddDefaultPred(MachineInstrBuilder(MI)); 1169 1170 // We are now reading SrcRegD instead of SrcRegS. This may upset the 1171 // register scavenger and machine verifier, so we need to indicate that we 1172 // are reading an undefined value from SrcRegD, but a proper value from 1173 // SrcRegS. 1174 MI->getOperand(1).setIsUndef(); 1175 MachineInstrBuilder(MI).addReg(SrcRegS, RegState::Implicit); 1176 1177 // SrcRegD may actually contain an unrelated value in the ssub_1 1178 // sub-register. Don't kill it. Only kill the ssub_0 sub-register. 1179 if (MI->getOperand(1).isKill()) { 1180 MI->getOperand(1).setIsKill(false); 1181 MI->addRegisterKilled(SrcRegS, TRI, true); 1182 } 1183 1184 DEBUG(dbgs() << "replaced by: " << *MI); 1185 return true; 1186} 1187 1188MachineInstr* 1189ARMBaseInstrInfo::emitFrameIndexDebugValue(MachineFunction &MF, 1190 int FrameIx, uint64_t Offset, 1191 const MDNode *MDPtr, 1192 DebugLoc DL) const { 1193 MachineInstrBuilder MIB = BuildMI(MF, DL, get(ARM::DBG_VALUE)) 1194 .addFrameIndex(FrameIx).addImm(0).addImm(Offset).addMetadata(MDPtr); 1195 return &*MIB; 1196} 1197 1198/// Create a copy of a const pool value. Update CPI to the new index and return 1199/// the label UID. 1200static unsigned duplicateCPV(MachineFunction &MF, unsigned &CPI) { 1201 MachineConstantPool *MCP = MF.getConstantPool(); 1202 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 1203 1204 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPI]; 1205 assert(MCPE.isMachineConstantPoolEntry() && 1206 "Expecting a machine constantpool entry!"); 1207 ARMConstantPoolValue *ACPV = 1208 static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal); 1209 1210 unsigned PCLabelId = AFI->createPICLabelUId(); 1211 ARMConstantPoolValue *NewCPV = 0; 1212 // FIXME: The below assumes PIC relocation model and that the function 1213 // is Thumb mode (t1 or t2). PCAdjustment would be 8 for ARM mode PIC, and 1214 // zero for non-PIC in ARM or Thumb. The callers are all of thumb LDR 1215 // instructions, so that's probably OK, but is PIC always correct when 1216 // we get here? 1217 if (ACPV->isGlobalValue()) 1218 NewCPV = ARMConstantPoolConstant:: 1219 Create(cast<ARMConstantPoolConstant>(ACPV)->getGV(), PCLabelId, 1220 ARMCP::CPValue, 4); 1221 else if (ACPV->isExtSymbol()) 1222 NewCPV = ARMConstantPoolSymbol:: 1223 Create(MF.getFunction()->getContext(), 1224 cast<ARMConstantPoolSymbol>(ACPV)->getSymbol(), PCLabelId, 4); 1225 else if (ACPV->isBlockAddress()) 1226 NewCPV = ARMConstantPoolConstant:: 1227 Create(cast<ARMConstantPoolConstant>(ACPV)->getBlockAddress(), PCLabelId, 1228 ARMCP::CPBlockAddress, 4); 1229 else if (ACPV->isLSDA()) 1230 NewCPV = ARMConstantPoolConstant::Create(MF.getFunction(), PCLabelId, 1231 ARMCP::CPLSDA, 4); 1232 else if (ACPV->isMachineBasicBlock()) 1233 NewCPV = ARMConstantPoolMBB:: 1234 Create(MF.getFunction()->getContext(), 1235 cast<ARMConstantPoolMBB>(ACPV)->getMBB(), PCLabelId, 4); 1236 else 1237 llvm_unreachable("Unexpected ARM constantpool value type!!"); 1238 CPI = MCP->getConstantPoolIndex(NewCPV, MCPE.getAlignment()); 1239 return PCLabelId; 1240} 1241 1242void ARMBaseInstrInfo:: 1243reMaterialize(MachineBasicBlock &MBB, 1244 MachineBasicBlock::iterator I, 1245 unsigned DestReg, unsigned SubIdx, 1246 const MachineInstr *Orig, 1247 const TargetRegisterInfo &TRI) const { 1248 unsigned Opcode = Orig->getOpcode(); 1249 switch (Opcode) { 1250 default: { 1251 MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig); 1252 MI->substituteRegister(Orig->getOperand(0).getReg(), DestReg, SubIdx, TRI); 1253 MBB.insert(I, MI); 1254 break; 1255 } 1256 case ARM::tLDRpci_pic: 1257 case ARM::t2LDRpci_pic: { 1258 MachineFunction &MF = *MBB.getParent(); 1259 unsigned CPI = Orig->getOperand(1).getIndex(); 1260 unsigned PCLabelId = duplicateCPV(MF, CPI); 1261 MachineInstrBuilder MIB = BuildMI(MBB, I, Orig->getDebugLoc(), get(Opcode), 1262 DestReg) 1263 .addConstantPoolIndex(CPI).addImm(PCLabelId); 1264 MIB->setMemRefs(Orig->memoperands_begin(), Orig->memoperands_end()); 1265 break; 1266 } 1267 } 1268} 1269 1270MachineInstr * 1271ARMBaseInstrInfo::duplicate(MachineInstr *Orig, MachineFunction &MF) const { 1272 MachineInstr *MI = TargetInstrInfo::duplicate(Orig, MF); 1273 switch(Orig->getOpcode()) { 1274 case ARM::tLDRpci_pic: 1275 case ARM::t2LDRpci_pic: { 1276 unsigned CPI = Orig->getOperand(1).getIndex(); 1277 unsigned PCLabelId = duplicateCPV(MF, CPI); 1278 Orig->getOperand(1).setIndex(CPI); 1279 Orig->getOperand(2).setImm(PCLabelId); 1280 break; 1281 } 1282 } 1283 return MI; 1284} 1285 1286bool ARMBaseInstrInfo::produceSameValue(const MachineInstr *MI0, 1287 const MachineInstr *MI1, 1288 const MachineRegisterInfo *MRI) const { 1289 int Opcode = MI0->getOpcode(); 1290 if (Opcode == ARM::t2LDRpci || 1291 Opcode == ARM::t2LDRpci_pic || 1292 Opcode == ARM::tLDRpci || 1293 Opcode == ARM::tLDRpci_pic || 1294 Opcode == ARM::MOV_ga_dyn || 1295 Opcode == ARM::MOV_ga_pcrel || 1296 Opcode == ARM::MOV_ga_pcrel_ldr || 1297 Opcode == ARM::t2MOV_ga_dyn || 1298 Opcode == ARM::t2MOV_ga_pcrel) { 1299 if (MI1->getOpcode() != Opcode) 1300 return false; 1301 if (MI0->getNumOperands() != MI1->getNumOperands()) 1302 return false; 1303 1304 const MachineOperand &MO0 = MI0->getOperand(1); 1305 const MachineOperand &MO1 = MI1->getOperand(1); 1306 if (MO0.getOffset() != MO1.getOffset()) 1307 return false; 1308 1309 if (Opcode == ARM::MOV_ga_dyn || 1310 Opcode == ARM::MOV_ga_pcrel || 1311 Opcode == ARM::MOV_ga_pcrel_ldr || 1312 Opcode == ARM::t2MOV_ga_dyn || 1313 Opcode == ARM::t2MOV_ga_pcrel) 1314 // Ignore the PC labels. 1315 return MO0.getGlobal() == MO1.getGlobal(); 1316 1317 const MachineFunction *MF = MI0->getParent()->getParent(); 1318 const MachineConstantPool *MCP = MF->getConstantPool(); 1319 int CPI0 = MO0.getIndex(); 1320 int CPI1 = MO1.getIndex(); 1321 const MachineConstantPoolEntry &MCPE0 = MCP->getConstants()[CPI0]; 1322 const MachineConstantPoolEntry &MCPE1 = MCP->getConstants()[CPI1]; 1323 bool isARMCP0 = MCPE0.isMachineConstantPoolEntry(); 1324 bool isARMCP1 = MCPE1.isMachineConstantPoolEntry(); 1325 if (isARMCP0 && isARMCP1) { 1326 ARMConstantPoolValue *ACPV0 = 1327 static_cast<ARMConstantPoolValue*>(MCPE0.Val.MachineCPVal); 1328 ARMConstantPoolValue *ACPV1 = 1329 static_cast<ARMConstantPoolValue*>(MCPE1.Val.MachineCPVal); 1330 return ACPV0->hasSameValue(ACPV1); 1331 } else if (!isARMCP0 && !isARMCP1) { 1332 return MCPE0.Val.ConstVal == MCPE1.Val.ConstVal; 1333 } 1334 return false; 1335 } else if (Opcode == ARM::PICLDR) { 1336 if (MI1->getOpcode() != Opcode) 1337 return false; 1338 if (MI0->getNumOperands() != MI1->getNumOperands()) 1339 return false; 1340 1341 unsigned Addr0 = MI0->getOperand(1).getReg(); 1342 unsigned Addr1 = MI1->getOperand(1).getReg(); 1343 if (Addr0 != Addr1) { 1344 if (!MRI || 1345 !TargetRegisterInfo::isVirtualRegister(Addr0) || 1346 !TargetRegisterInfo::isVirtualRegister(Addr1)) 1347 return false; 1348 1349 // This assumes SSA form. 1350 MachineInstr *Def0 = MRI->getVRegDef(Addr0); 1351 MachineInstr *Def1 = MRI->getVRegDef(Addr1); 1352 // Check if the loaded value, e.g. a constantpool of a global address, are 1353 // the same. 1354 if (!produceSameValue(Def0, Def1, MRI)) 1355 return false; 1356 } 1357 1358 for (unsigned i = 3, e = MI0->getNumOperands(); i != e; ++i) { 1359 // %vreg12<def> = PICLDR %vreg11, 0, pred:14, pred:%noreg 1360 const MachineOperand &MO0 = MI0->getOperand(i); 1361 const MachineOperand &MO1 = MI1->getOperand(i); 1362 if (!MO0.isIdenticalTo(MO1)) 1363 return false; 1364 } 1365 return true; 1366 } 1367 1368 return MI0->isIdenticalTo(MI1, MachineInstr::IgnoreVRegDefs); 1369} 1370 1371/// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to 1372/// determine if two loads are loading from the same base address. It should 1373/// only return true if the base pointers are the same and the only differences 1374/// between the two addresses is the offset. It also returns the offsets by 1375/// reference. 1376/// 1377/// FIXME: remove this in favor of the MachineInstr interface once pre-RA-sched 1378/// is permanently disabled. 1379bool ARMBaseInstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, 1380 int64_t &Offset1, 1381 int64_t &Offset2) const { 1382 // Don't worry about Thumb: just ARM and Thumb2. 1383 if (Subtarget.isThumb1Only()) return false; 1384 1385 if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode()) 1386 return false; 1387 1388 switch (Load1->getMachineOpcode()) { 1389 default: 1390 return false; 1391 case ARM::LDRi12: 1392 case ARM::LDRBi12: 1393 case ARM::LDRD: 1394 case ARM::LDRH: 1395 case ARM::LDRSB: 1396 case ARM::LDRSH: 1397 case ARM::VLDRD: 1398 case ARM::VLDRS: 1399 case ARM::t2LDRi8: 1400 case ARM::t2LDRDi8: 1401 case ARM::t2LDRSHi8: 1402 case ARM::t2LDRi12: 1403 case ARM::t2LDRSHi12: 1404 break; 1405 } 1406 1407 switch (Load2->getMachineOpcode()) { 1408 default: 1409 return false; 1410 case ARM::LDRi12: 1411 case ARM::LDRBi12: 1412 case ARM::LDRD: 1413 case ARM::LDRH: 1414 case ARM::LDRSB: 1415 case ARM::LDRSH: 1416 case ARM::VLDRD: 1417 case ARM::VLDRS: 1418 case ARM::t2LDRi8: 1419 case ARM::t2LDRSHi8: 1420 case ARM::t2LDRi12: 1421 case ARM::t2LDRSHi12: 1422 break; 1423 } 1424 1425 // Check if base addresses and chain operands match. 1426 if (Load1->getOperand(0) != Load2->getOperand(0) || 1427 Load1->getOperand(4) != Load2->getOperand(4)) 1428 return false; 1429 1430 // Index should be Reg0. 1431 if (Load1->getOperand(3) != Load2->getOperand(3)) 1432 return false; 1433 1434 // Determine the offsets. 1435 if (isa<ConstantSDNode>(Load1->getOperand(1)) && 1436 isa<ConstantSDNode>(Load2->getOperand(1))) { 1437 Offset1 = cast<ConstantSDNode>(Load1->getOperand(1))->getSExtValue(); 1438 Offset2 = cast<ConstantSDNode>(Load2->getOperand(1))->getSExtValue(); 1439 return true; 1440 } 1441 1442 return false; 1443} 1444 1445/// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to 1446/// determine (in conjunction with areLoadsFromSameBasePtr) if two loads should 1447/// be scheduled togther. On some targets if two loads are loading from 1448/// addresses in the same cache line, it's better if they are scheduled 1449/// together. This function takes two integers that represent the load offsets 1450/// from the common base address. It returns true if it decides it's desirable 1451/// to schedule the two loads together. "NumLoads" is the number of loads that 1452/// have already been scheduled after Load1. 1453/// 1454/// FIXME: remove this in favor of the MachineInstr interface once pre-RA-sched 1455/// is permanently disabled. 1456bool ARMBaseInstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, 1457 int64_t Offset1, int64_t Offset2, 1458 unsigned NumLoads) const { 1459 // Don't worry about Thumb: just ARM and Thumb2. 1460 if (Subtarget.isThumb1Only()) return false; 1461 1462 assert(Offset2 > Offset1); 1463 1464 if ((Offset2 - Offset1) / 8 > 64) 1465 return false; 1466 1467 if (Load1->getMachineOpcode() != Load2->getMachineOpcode()) 1468 return false; // FIXME: overly conservative? 1469 1470 // Four loads in a row should be sufficient. 1471 if (NumLoads >= 3) 1472 return false; 1473 1474 return true; 1475} 1476 1477bool ARMBaseInstrInfo::isSchedulingBoundary(const MachineInstr *MI, 1478 const MachineBasicBlock *MBB, 1479 const MachineFunction &MF) const { 1480 // Debug info is never a scheduling boundary. It's necessary to be explicit 1481 // due to the special treatment of IT instructions below, otherwise a 1482 // dbg_value followed by an IT will result in the IT instruction being 1483 // considered a scheduling hazard, which is wrong. It should be the actual 1484 // instruction preceding the dbg_value instruction(s), just like it is 1485 // when debug info is not present. 1486 if (MI->isDebugValue()) 1487 return false; 1488 1489 // Terminators and labels can't be scheduled around. 1490 if (MI->isTerminator() || MI->isLabel()) 1491 return true; 1492 1493 // Treat the start of the IT block as a scheduling boundary, but schedule 1494 // t2IT along with all instructions following it. 1495 // FIXME: This is a big hammer. But the alternative is to add all potential 1496 // true and anti dependencies to IT block instructions as implicit operands 1497 // to the t2IT instruction. The added compile time and complexity does not 1498 // seem worth it. 1499 MachineBasicBlock::const_iterator I = MI; 1500 // Make sure to skip any dbg_value instructions 1501 while (++I != MBB->end() && I->isDebugValue()) 1502 ; 1503 if (I != MBB->end() && I->getOpcode() == ARM::t2IT) 1504 return true; 1505 1506 // Don't attempt to schedule around any instruction that defines 1507 // a stack-oriented pointer, as it's unlikely to be profitable. This 1508 // saves compile time, because it doesn't require every single 1509 // stack slot reference to depend on the instruction that does the 1510 // modification. 1511 // Calls don't actually change the stack pointer, even if they have imp-defs. 1512 // No ARM calling conventions change the stack pointer. (X86 calling 1513 // conventions sometimes do). 1514 if (!MI->isCall() && MI->definesRegister(ARM::SP)) 1515 return true; 1516 1517 return false; 1518} 1519 1520bool ARMBaseInstrInfo:: 1521isProfitableToIfCvt(MachineBasicBlock &MBB, 1522 unsigned NumCycles, unsigned ExtraPredCycles, 1523 const BranchProbability &Probability) const { 1524 if (!NumCycles) 1525 return false; 1526 1527 // Attempt to estimate the relative costs of predication versus branching. 1528 unsigned UnpredCost = Probability.getNumerator() * NumCycles; 1529 UnpredCost /= Probability.getDenominator(); 1530 UnpredCost += 1; // The branch itself 1531 UnpredCost += Subtarget.getMispredictionPenalty() / 10; 1532 1533 return (NumCycles + ExtraPredCycles) <= UnpredCost; 1534} 1535 1536bool ARMBaseInstrInfo:: 1537isProfitableToIfCvt(MachineBasicBlock &TMBB, 1538 unsigned TCycles, unsigned TExtra, 1539 MachineBasicBlock &FMBB, 1540 unsigned FCycles, unsigned FExtra, 1541 const BranchProbability &Probability) const { 1542 if (!TCycles || !FCycles) 1543 return false; 1544 1545 // Attempt to estimate the relative costs of predication versus branching. 1546 unsigned TUnpredCost = Probability.getNumerator() * TCycles; 1547 TUnpredCost /= Probability.getDenominator(); 1548 1549 uint32_t Comp = Probability.getDenominator() - Probability.getNumerator(); 1550 unsigned FUnpredCost = Comp * FCycles; 1551 FUnpredCost /= Probability.getDenominator(); 1552 1553 unsigned UnpredCost = TUnpredCost + FUnpredCost; 1554 UnpredCost += 1; // The branch itself 1555 UnpredCost += Subtarget.getMispredictionPenalty() / 10; 1556 1557 return (TCycles + FCycles + TExtra + FExtra) <= UnpredCost; 1558} 1559 1560bool 1561ARMBaseInstrInfo::isProfitableToUnpredicate(MachineBasicBlock &TMBB, 1562 MachineBasicBlock &FMBB) const { 1563 // Reduce false anti-dependencies to let Swift's out-of-order execution 1564 // engine do its thing. 1565 return Subtarget.isSwift(); 1566} 1567 1568/// getInstrPredicate - If instruction is predicated, returns its predicate 1569/// condition, otherwise returns AL. It also returns the condition code 1570/// register by reference. 1571ARMCC::CondCodes 1572llvm::getInstrPredicate(const MachineInstr *MI, unsigned &PredReg) { 1573 int PIdx = MI->findFirstPredOperandIdx(); 1574 if (PIdx == -1) { 1575 PredReg = 0; 1576 return ARMCC::AL; 1577 } 1578 1579 PredReg = MI->getOperand(PIdx+1).getReg(); 1580 return (ARMCC::CondCodes)MI->getOperand(PIdx).getImm(); 1581} 1582 1583 1584int llvm::getMatchingCondBranchOpcode(int Opc) { 1585 if (Opc == ARM::B) 1586 return ARM::Bcc; 1587 if (Opc == ARM::tB) 1588 return ARM::tBcc; 1589 if (Opc == ARM::t2B) 1590 return ARM::t2Bcc; 1591 1592 llvm_unreachable("Unknown unconditional branch opcode!"); 1593} 1594 1595/// commuteInstruction - Handle commutable instructions. 1596MachineInstr * 1597ARMBaseInstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const { 1598 switch (MI->getOpcode()) { 1599 case ARM::MOVCCr: 1600 case ARM::t2MOVCCr: { 1601 // MOVCC can be commuted by inverting the condition. 1602 unsigned PredReg = 0; 1603 ARMCC::CondCodes CC = getInstrPredicate(MI, PredReg); 1604 // MOVCC AL can't be inverted. Shouldn't happen. 1605 if (CC == ARMCC::AL || PredReg != ARM::CPSR) 1606 return NULL; 1607 MI = TargetInstrInfo::commuteInstruction(MI, NewMI); 1608 if (!MI) 1609 return NULL; 1610 // After swapping the MOVCC operands, also invert the condition. 1611 MI->getOperand(MI->findFirstPredOperandIdx()) 1612 .setImm(ARMCC::getOppositeCondition(CC)); 1613 return MI; 1614 } 1615 } 1616 return TargetInstrInfo::commuteInstruction(MI, NewMI); 1617} 1618 1619/// Identify instructions that can be folded into a MOVCC instruction, and 1620/// return the defining instruction. 1621static MachineInstr *canFoldIntoMOVCC(unsigned Reg, 1622 const MachineRegisterInfo &MRI, 1623 const TargetInstrInfo *TII) { 1624 if (!TargetRegisterInfo::isVirtualRegister(Reg)) 1625 return 0; 1626 if (!MRI.hasOneNonDBGUse(Reg)) 1627 return 0; 1628 MachineInstr *MI = MRI.getVRegDef(Reg); 1629 if (!MI) 1630 return 0; 1631 // MI is folded into the MOVCC by predicating it. 1632 if (!MI->isPredicable()) 1633 return 0; 1634 // Check if MI has any non-dead defs or physreg uses. This also detects 1635 // predicated instructions which will be reading CPSR. 1636 for (unsigned i = 1, e = MI->getNumOperands(); i != e; ++i) { 1637 const MachineOperand &MO = MI->getOperand(i); 1638 // Reject frame index operands, PEI can't handle the predicated pseudos. 1639 if (MO.isFI() || MO.isCPI() || MO.isJTI()) 1640 return 0; 1641 if (!MO.isReg()) 1642 continue; 1643 // MI can't have any tied operands, that would conflict with predication. 1644 if (MO.isTied()) 1645 return 0; 1646 if (TargetRegisterInfo::isPhysicalRegister(MO.getReg())) 1647 return 0; 1648 if (MO.isDef() && !MO.isDead()) 1649 return 0; 1650 } 1651 bool DontMoveAcrossStores = true; 1652 if (!MI->isSafeToMove(TII, /* AliasAnalysis = */ 0, DontMoveAcrossStores)) 1653 return 0; 1654 return MI; 1655} 1656 1657bool ARMBaseInstrInfo::analyzeSelect(const MachineInstr *MI, 1658 SmallVectorImpl<MachineOperand> &Cond, 1659 unsigned &TrueOp, unsigned &FalseOp, 1660 bool &Optimizable) const { 1661 assert((MI->getOpcode() == ARM::MOVCCr || MI->getOpcode() == ARM::t2MOVCCr) && 1662 "Unknown select instruction"); 1663 // MOVCC operands: 1664 // 0: Def. 1665 // 1: True use. 1666 // 2: False use. 1667 // 3: Condition code. 1668 // 4: CPSR use. 1669 TrueOp = 1; 1670 FalseOp = 2; 1671 Cond.push_back(MI->getOperand(3)); 1672 Cond.push_back(MI->getOperand(4)); 1673 // We can always fold a def. 1674 Optimizable = true; 1675 return false; 1676} 1677 1678MachineInstr *ARMBaseInstrInfo::optimizeSelect(MachineInstr *MI, 1679 bool PreferFalse) const { 1680 assert((MI->getOpcode() == ARM::MOVCCr || MI->getOpcode() == ARM::t2MOVCCr) && 1681 "Unknown select instruction"); 1682 const MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo(); 1683 MachineInstr *DefMI = canFoldIntoMOVCC(MI->getOperand(2).getReg(), MRI, this); 1684 bool Invert = !DefMI; 1685 if (!DefMI) 1686 DefMI = canFoldIntoMOVCC(MI->getOperand(1).getReg(), MRI, this); 1687 if (!DefMI) 1688 return 0; 1689 1690 // Create a new predicated version of DefMI. 1691 // Rfalse is the first use. 1692 MachineInstrBuilder NewMI = BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), 1693 DefMI->getDesc(), 1694 MI->getOperand(0).getReg()); 1695 1696 // Copy all the DefMI operands, excluding its (null) predicate. 1697 const MCInstrDesc &DefDesc = DefMI->getDesc(); 1698 for (unsigned i = 1, e = DefDesc.getNumOperands(); 1699 i != e && !DefDesc.OpInfo[i].isPredicate(); ++i) 1700 NewMI.addOperand(DefMI->getOperand(i)); 1701 1702 unsigned CondCode = MI->getOperand(3).getImm(); 1703 if (Invert) 1704 NewMI.addImm(ARMCC::getOppositeCondition(ARMCC::CondCodes(CondCode))); 1705 else 1706 NewMI.addImm(CondCode); 1707 NewMI.addOperand(MI->getOperand(4)); 1708 1709 // DefMI is not the -S version that sets CPSR, so add an optional %noreg. 1710 if (NewMI->hasOptionalDef()) 1711 AddDefaultCC(NewMI); 1712 1713 // The output register value when the predicate is false is an implicit 1714 // register operand tied to the first def. 1715 // The tie makes the register allocator ensure the FalseReg is allocated the 1716 // same register as operand 0. 1717 MachineOperand FalseReg = MI->getOperand(Invert ? 2 : 1); 1718 FalseReg.setImplicit(); 1719 NewMI->addOperand(FalseReg); 1720 NewMI->tieOperands(0, NewMI->getNumOperands() - 1); 1721 1722 // The caller will erase MI, but not DefMI. 1723 DefMI->eraseFromParent(); 1724 return NewMI; 1725} 1726 1727/// Map pseudo instructions that imply an 'S' bit onto real opcodes. Whether the 1728/// instruction is encoded with an 'S' bit is determined by the optional CPSR 1729/// def operand. 1730/// 1731/// This will go away once we can teach tblgen how to set the optional CPSR def 1732/// operand itself. 1733struct AddSubFlagsOpcodePair { 1734 uint16_t PseudoOpc; 1735 uint16_t MachineOpc; 1736}; 1737 1738static const AddSubFlagsOpcodePair AddSubFlagsOpcodeMap[] = { 1739 {ARM::ADDSri, ARM::ADDri}, 1740 {ARM::ADDSrr, ARM::ADDrr}, 1741 {ARM::ADDSrsi, ARM::ADDrsi}, 1742 {ARM::ADDSrsr, ARM::ADDrsr}, 1743 1744 {ARM::SUBSri, ARM::SUBri}, 1745 {ARM::SUBSrr, ARM::SUBrr}, 1746 {ARM::SUBSrsi, ARM::SUBrsi}, 1747 {ARM::SUBSrsr, ARM::SUBrsr}, 1748 1749 {ARM::RSBSri, ARM::RSBri}, 1750 {ARM::RSBSrsi, ARM::RSBrsi}, 1751 {ARM::RSBSrsr, ARM::RSBrsr}, 1752 1753 {ARM::t2ADDSri, ARM::t2ADDri}, 1754 {ARM::t2ADDSrr, ARM::t2ADDrr}, 1755 {ARM::t2ADDSrs, ARM::t2ADDrs}, 1756 1757 {ARM::t2SUBSri, ARM::t2SUBri}, 1758 {ARM::t2SUBSrr, ARM::t2SUBrr}, 1759 {ARM::t2SUBSrs, ARM::t2SUBrs}, 1760 1761 {ARM::t2RSBSri, ARM::t2RSBri}, 1762 {ARM::t2RSBSrs, ARM::t2RSBrs}, 1763}; 1764 1765unsigned llvm::convertAddSubFlagsOpcode(unsigned OldOpc) { 1766 for (unsigned i = 0, e = array_lengthof(AddSubFlagsOpcodeMap); i != e; ++i) 1767 if (OldOpc == AddSubFlagsOpcodeMap[i].PseudoOpc) 1768 return AddSubFlagsOpcodeMap[i].MachineOpc; 1769 return 0; 1770} 1771 1772void llvm::emitARMRegPlusImmediate(MachineBasicBlock &MBB, 1773 MachineBasicBlock::iterator &MBBI, DebugLoc dl, 1774 unsigned DestReg, unsigned BaseReg, int NumBytes, 1775 ARMCC::CondCodes Pred, unsigned PredReg, 1776 const ARMBaseInstrInfo &TII, unsigned MIFlags) { 1777 bool isSub = NumBytes < 0; 1778 if (isSub) NumBytes = -NumBytes; 1779 1780 while (NumBytes) { 1781 unsigned RotAmt = ARM_AM::getSOImmValRotate(NumBytes); 1782 unsigned ThisVal = NumBytes & ARM_AM::rotr32(0xFF, RotAmt); 1783 assert(ThisVal && "Didn't extract field correctly"); 1784 1785 // We will handle these bits from offset, clear them. 1786 NumBytes &= ~ThisVal; 1787 1788 assert(ARM_AM::getSOImmVal(ThisVal) != -1 && "Bit extraction didn't work?"); 1789 1790 // Build the new ADD / SUB. 1791 unsigned Opc = isSub ? ARM::SUBri : ARM::ADDri; 1792 BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg) 1793 .addReg(BaseReg, RegState::Kill).addImm(ThisVal) 1794 .addImm((unsigned)Pred).addReg(PredReg).addReg(0) 1795 .setMIFlags(MIFlags); 1796 BaseReg = DestReg; 1797 } 1798} 1799 1800bool llvm::rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx, 1801 unsigned FrameReg, int &Offset, 1802 const ARMBaseInstrInfo &TII) { 1803 unsigned Opcode = MI.getOpcode(); 1804 const MCInstrDesc &Desc = MI.getDesc(); 1805 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask); 1806 bool isSub = false; 1807 1808 // Memory operands in inline assembly always use AddrMode2. 1809 if (Opcode == ARM::INLINEASM) 1810 AddrMode = ARMII::AddrMode2; 1811 1812 if (Opcode == ARM::ADDri) { 1813 Offset += MI.getOperand(FrameRegIdx+1).getImm(); 1814 if (Offset == 0) { 1815 // Turn it into a move. 1816 MI.setDesc(TII.get(ARM::MOVr)); 1817 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false); 1818 MI.RemoveOperand(FrameRegIdx+1); 1819 Offset = 0; 1820 return true; 1821 } else if (Offset < 0) { 1822 Offset = -Offset; 1823 isSub = true; 1824 MI.setDesc(TII.get(ARM::SUBri)); 1825 } 1826 1827 // Common case: small offset, fits into instruction. 1828 if (ARM_AM::getSOImmVal(Offset) != -1) { 1829 // Replace the FrameIndex with sp / fp 1830 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false); 1831 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset); 1832 Offset = 0; 1833 return true; 1834 } 1835 1836 // Otherwise, pull as much of the immedidate into this ADDri/SUBri 1837 // as possible. 1838 unsigned RotAmt = ARM_AM::getSOImmValRotate(Offset); 1839 unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xFF, RotAmt); 1840 1841 // We will handle these bits from offset, clear them. 1842 Offset &= ~ThisImmVal; 1843 1844 // Get the properly encoded SOImmVal field. 1845 assert(ARM_AM::getSOImmVal(ThisImmVal) != -1 && 1846 "Bit extraction didn't work?"); 1847 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(ThisImmVal); 1848 } else { 1849 unsigned ImmIdx = 0; 1850 int InstrOffs = 0; 1851 unsigned NumBits = 0; 1852 unsigned Scale = 1; 1853 switch (AddrMode) { 1854 case ARMII::AddrMode_i12: { 1855 ImmIdx = FrameRegIdx + 1; 1856 InstrOffs = MI.getOperand(ImmIdx).getImm(); 1857 NumBits = 12; 1858 break; 1859 } 1860 case ARMII::AddrMode2: { 1861 ImmIdx = FrameRegIdx+2; 1862 InstrOffs = ARM_AM::getAM2Offset(MI.getOperand(ImmIdx).getImm()); 1863 if (ARM_AM::getAM2Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub) 1864 InstrOffs *= -1; 1865 NumBits = 12; 1866 break; 1867 } 1868 case ARMII::AddrMode3: { 1869 ImmIdx = FrameRegIdx+2; 1870 InstrOffs = ARM_AM::getAM3Offset(MI.getOperand(ImmIdx).getImm()); 1871 if (ARM_AM::getAM3Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub) 1872 InstrOffs *= -1; 1873 NumBits = 8; 1874 break; 1875 } 1876 case ARMII::AddrMode4: 1877 case ARMII::AddrMode6: 1878 // Can't fold any offset even if it's zero. 1879 return false; 1880 case ARMII::AddrMode5: { 1881 ImmIdx = FrameRegIdx+1; 1882 InstrOffs = ARM_AM::getAM5Offset(MI.getOperand(ImmIdx).getImm()); 1883 if (ARM_AM::getAM5Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub) 1884 InstrOffs *= -1; 1885 NumBits = 8; 1886 Scale = 4; 1887 break; 1888 } 1889 default: 1890 llvm_unreachable("Unsupported addressing mode!"); 1891 } 1892 1893 Offset += InstrOffs * Scale; 1894 assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!"); 1895 if (Offset < 0) { 1896 Offset = -Offset; 1897 isSub = true; 1898 } 1899 1900 // Attempt to fold address comp. if opcode has offset bits 1901 if (NumBits > 0) { 1902 // Common case: small offset, fits into instruction. 1903 MachineOperand &ImmOp = MI.getOperand(ImmIdx); 1904 int ImmedOffset = Offset / Scale; 1905 unsigned Mask = (1 << NumBits) - 1; 1906 if ((unsigned)Offset <= Mask * Scale) { 1907 // Replace the FrameIndex with sp 1908 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false); 1909 // FIXME: When addrmode2 goes away, this will simplify (like the 1910 // T2 version), as the LDR.i12 versions don't need the encoding 1911 // tricks for the offset value. 1912 if (isSub) { 1913 if (AddrMode == ARMII::AddrMode_i12) 1914 ImmedOffset = -ImmedOffset; 1915 else 1916 ImmedOffset |= 1 << NumBits; 1917 } 1918 ImmOp.ChangeToImmediate(ImmedOffset); 1919 Offset = 0; 1920 return true; 1921 } 1922 1923 // Otherwise, it didn't fit. Pull in what we can to simplify the immed. 1924 ImmedOffset = ImmedOffset & Mask; 1925 if (isSub) { 1926 if (AddrMode == ARMII::AddrMode_i12) 1927 ImmedOffset = -ImmedOffset; 1928 else 1929 ImmedOffset |= 1 << NumBits; 1930 } 1931 ImmOp.ChangeToImmediate(ImmedOffset); 1932 Offset &= ~(Mask*Scale); 1933 } 1934 } 1935 1936 Offset = (isSub) ? -Offset : Offset; 1937 return Offset == 0; 1938} 1939 1940/// analyzeCompare - For a comparison instruction, return the source registers 1941/// in SrcReg and SrcReg2 if having two register operands, and the value it 1942/// compares against in CmpValue. Return true if the comparison instruction 1943/// can be analyzed. 1944bool ARMBaseInstrInfo:: 1945analyzeCompare(const MachineInstr *MI, unsigned &SrcReg, unsigned &SrcReg2, 1946 int &CmpMask, int &CmpValue) const { 1947 switch (MI->getOpcode()) { 1948 default: break; 1949 case ARM::CMPri: 1950 case ARM::t2CMPri: 1951 SrcReg = MI->getOperand(0).getReg(); 1952 SrcReg2 = 0; 1953 CmpMask = ~0; 1954 CmpValue = MI->getOperand(1).getImm(); 1955 return true; 1956 case ARM::CMPrr: 1957 case ARM::t2CMPrr: 1958 SrcReg = MI->getOperand(0).getReg(); 1959 SrcReg2 = MI->getOperand(1).getReg(); 1960 CmpMask = ~0; 1961 CmpValue = 0; 1962 return true; 1963 case ARM::TSTri: 1964 case ARM::t2TSTri: 1965 SrcReg = MI->getOperand(0).getReg(); 1966 SrcReg2 = 0; 1967 CmpMask = MI->getOperand(1).getImm(); 1968 CmpValue = 0; 1969 return true; 1970 } 1971 1972 return false; 1973} 1974 1975/// isSuitableForMask - Identify a suitable 'and' instruction that 1976/// operates on the given source register and applies the same mask 1977/// as a 'tst' instruction. Provide a limited look-through for copies. 1978/// When successful, MI will hold the found instruction. 1979static bool isSuitableForMask(MachineInstr *&MI, unsigned SrcReg, 1980 int CmpMask, bool CommonUse) { 1981 switch (MI->getOpcode()) { 1982 case ARM::ANDri: 1983 case ARM::t2ANDri: 1984 if (CmpMask != MI->getOperand(2).getImm()) 1985 return false; 1986 if (SrcReg == MI->getOperand(CommonUse ? 1 : 0).getReg()) 1987 return true; 1988 break; 1989 case ARM::COPY: { 1990 // Walk down one instruction which is potentially an 'and'. 1991 const MachineInstr &Copy = *MI; 1992 MachineBasicBlock::iterator AND( 1993 llvm::next(MachineBasicBlock::iterator(MI))); 1994 if (AND == MI->getParent()->end()) return false; 1995 MI = AND; 1996 return isSuitableForMask(MI, Copy.getOperand(0).getReg(), 1997 CmpMask, true); 1998 } 1999 } 2000 2001 return false; 2002} 2003 2004/// getSwappedCondition - assume the flags are set by MI(a,b), return 2005/// the condition code if we modify the instructions such that flags are 2006/// set by MI(b,a). 2007inline static ARMCC::CondCodes getSwappedCondition(ARMCC::CondCodes CC) { 2008 switch (CC) { 2009 default: return ARMCC::AL; 2010 case ARMCC::EQ: return ARMCC::EQ; 2011 case ARMCC::NE: return ARMCC::NE; 2012 case ARMCC::HS: return ARMCC::LS; 2013 case ARMCC::LO: return ARMCC::HI; 2014 case ARMCC::HI: return ARMCC::LO; 2015 case ARMCC::LS: return ARMCC::HS; 2016 case ARMCC::GE: return ARMCC::LE; 2017 case ARMCC::LT: return ARMCC::GT; 2018 case ARMCC::GT: return ARMCC::LT; 2019 case ARMCC::LE: return ARMCC::GE; 2020 } 2021} 2022 2023/// isRedundantFlagInstr - check whether the first instruction, whose only 2024/// purpose is to update flags, can be made redundant. 2025/// CMPrr can be made redundant by SUBrr if the operands are the same. 2026/// CMPri can be made redundant by SUBri if the operands are the same. 2027/// This function can be extended later on. 2028inline static bool isRedundantFlagInstr(MachineInstr *CmpI, unsigned SrcReg, 2029 unsigned SrcReg2, int ImmValue, 2030 MachineInstr *OI) { 2031 if ((CmpI->getOpcode() == ARM::CMPrr || 2032 CmpI->getOpcode() == ARM::t2CMPrr) && 2033 (OI->getOpcode() == ARM::SUBrr || 2034 OI->getOpcode() == ARM::t2SUBrr) && 2035 ((OI->getOperand(1).getReg() == SrcReg && 2036 OI->getOperand(2).getReg() == SrcReg2) || 2037 (OI->getOperand(1).getReg() == SrcReg2 && 2038 OI->getOperand(2).getReg() == SrcReg))) 2039 return true; 2040 2041 if ((CmpI->getOpcode() == ARM::CMPri || 2042 CmpI->getOpcode() == ARM::t2CMPri) && 2043 (OI->getOpcode() == ARM::SUBri || 2044 OI->getOpcode() == ARM::t2SUBri) && 2045 OI->getOperand(1).getReg() == SrcReg && 2046 OI->getOperand(2).getImm() == ImmValue) 2047 return true; 2048 return false; 2049} 2050 2051/// optimizeCompareInstr - Convert the instruction supplying the argument to the 2052/// comparison into one that sets the zero bit in the flags register; 2053/// Remove a redundant Compare instruction if an earlier instruction can set the 2054/// flags in the same way as Compare. 2055/// E.g. SUBrr(r1,r2) and CMPrr(r1,r2). We also handle the case where two 2056/// operands are swapped: SUBrr(r1,r2) and CMPrr(r2,r1), by updating the 2057/// condition code of instructions which use the flags. 2058bool ARMBaseInstrInfo:: 2059optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, unsigned SrcReg2, 2060 int CmpMask, int CmpValue, 2061 const MachineRegisterInfo *MRI) const { 2062 // Get the unique definition of SrcReg. 2063 MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg); 2064 if (!MI) return false; 2065 2066 // Masked compares sometimes use the same register as the corresponding 'and'. 2067 if (CmpMask != ~0) { 2068 if (!isSuitableForMask(MI, SrcReg, CmpMask, false) || isPredicated(MI)) { 2069 MI = 0; 2070 for (MachineRegisterInfo::use_iterator UI = MRI->use_begin(SrcReg), 2071 UE = MRI->use_end(); UI != UE; ++UI) { 2072 if (UI->getParent() != CmpInstr->getParent()) continue; 2073 MachineInstr *PotentialAND = &*UI; 2074 if (!isSuitableForMask(PotentialAND, SrcReg, CmpMask, true) || 2075 isPredicated(PotentialAND)) 2076 continue; 2077 MI = PotentialAND; 2078 break; 2079 } 2080 if (!MI) return false; 2081 } 2082 } 2083 2084 // Get ready to iterate backward from CmpInstr. 2085 MachineBasicBlock::iterator I = CmpInstr, E = MI, 2086 B = CmpInstr->getParent()->begin(); 2087 2088 // Early exit if CmpInstr is at the beginning of the BB. 2089 if (I == B) return false; 2090 2091 // There are two possible candidates which can be changed to set CPSR: 2092 // One is MI, the other is a SUB instruction. 2093 // For CMPrr(r1,r2), we are looking for SUB(r1,r2) or SUB(r2,r1). 2094 // For CMPri(r1, CmpValue), we are looking for SUBri(r1, CmpValue). 2095 MachineInstr *Sub = NULL; 2096 if (SrcReg2 != 0) 2097 // MI is not a candidate for CMPrr. 2098 MI = NULL; 2099 else if (MI->getParent() != CmpInstr->getParent() || CmpValue != 0) { 2100 // Conservatively refuse to convert an instruction which isn't in the same 2101 // BB as the comparison. 2102 // For CMPri, we need to check Sub, thus we can't return here. 2103 if (CmpInstr->getOpcode() == ARM::CMPri || 2104 CmpInstr->getOpcode() == ARM::t2CMPri) 2105 MI = NULL; 2106 else 2107 return false; 2108 } 2109 2110 // Check that CPSR isn't set between the comparison instruction and the one we 2111 // want to change. At the same time, search for Sub. 2112 const TargetRegisterInfo *TRI = &getRegisterInfo(); 2113 --I; 2114 for (; I != E; --I) { 2115 const MachineInstr &Instr = *I; 2116 2117 if (Instr.modifiesRegister(ARM::CPSR, TRI) || 2118 Instr.readsRegister(ARM::CPSR, TRI)) 2119 // This instruction modifies or uses CPSR after the one we want to 2120 // change. We can't do this transformation. 2121 return false; 2122 2123 // Check whether CmpInstr can be made redundant by the current instruction. 2124 if (isRedundantFlagInstr(CmpInstr, SrcReg, SrcReg2, CmpValue, &*I)) { 2125 Sub = &*I; 2126 break; 2127 } 2128 2129 if (I == B) 2130 // The 'and' is below the comparison instruction. 2131 return false; 2132 } 2133 2134 // Return false if no candidates exist. 2135 if (!MI && !Sub) 2136 return false; 2137 2138 // The single candidate is called MI. 2139 if (!MI) MI = Sub; 2140 2141 // We can't use a predicated instruction - it doesn't always write the flags. 2142 if (isPredicated(MI)) 2143 return false; 2144 2145 switch (MI->getOpcode()) { 2146 default: break; 2147 case ARM::RSBrr: 2148 case ARM::RSBri: 2149 case ARM::RSCrr: 2150 case ARM::RSCri: 2151 case ARM::ADDrr: 2152 case ARM::ADDri: 2153 case ARM::ADCrr: 2154 case ARM::ADCri: 2155 case ARM::SUBrr: 2156 case ARM::SUBri: 2157 case ARM::SBCrr: 2158 case ARM::SBCri: 2159 case ARM::t2RSBri: 2160 case ARM::t2ADDrr: 2161 case ARM::t2ADDri: 2162 case ARM::t2ADCrr: 2163 case ARM::t2ADCri: 2164 case ARM::t2SUBrr: 2165 case ARM::t2SUBri: 2166 case ARM::t2SBCrr: 2167 case ARM::t2SBCri: 2168 case ARM::ANDrr: 2169 case ARM::ANDri: 2170 case ARM::t2ANDrr: 2171 case ARM::t2ANDri: 2172 case ARM::ORRrr: 2173 case ARM::ORRri: 2174 case ARM::t2ORRrr: 2175 case ARM::t2ORRri: 2176 case ARM::EORrr: 2177 case ARM::EORri: 2178 case ARM::t2EORrr: 2179 case ARM::t2EORri: { 2180 // Scan forward for the use of CPSR 2181 // When checking against MI: if it's a conditional code requires 2182 // checking of V bit, then this is not safe to do. 2183 // It is safe to remove CmpInstr if CPSR is redefined or killed. 2184 // If we are done with the basic block, we need to check whether CPSR is 2185 // live-out. 2186 SmallVector<std::pair<MachineOperand*, ARMCC::CondCodes>, 4> 2187 OperandsToUpdate; 2188 bool isSafe = false; 2189 I = CmpInstr; 2190 E = CmpInstr->getParent()->end(); 2191 while (!isSafe && ++I != E) { 2192 const MachineInstr &Instr = *I; 2193 for (unsigned IO = 0, EO = Instr.getNumOperands(); 2194 !isSafe && IO != EO; ++IO) { 2195 const MachineOperand &MO = Instr.getOperand(IO); 2196 if (MO.isRegMask() && MO.clobbersPhysReg(ARM::CPSR)) { 2197 isSafe = true; 2198 break; 2199 } 2200 if (!MO.isReg() || MO.getReg() != ARM::CPSR) 2201 continue; 2202 if (MO.isDef()) { 2203 isSafe = true; 2204 break; 2205 } 2206 // Condition code is after the operand before CPSR. 2207 ARMCC::CondCodes CC = (ARMCC::CondCodes)Instr.getOperand(IO-1).getImm(); 2208 if (Sub) { 2209 ARMCC::CondCodes NewCC = getSwappedCondition(CC); 2210 if (NewCC == ARMCC::AL) 2211 return false; 2212 // If we have SUB(r1, r2) and CMP(r2, r1), the condition code based 2213 // on CMP needs to be updated to be based on SUB. 2214 // Push the condition code operands to OperandsToUpdate. 2215 // If it is safe to remove CmpInstr, the condition code of these 2216 // operands will be modified. 2217 if (SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 && 2218 Sub->getOperand(2).getReg() == SrcReg) 2219 OperandsToUpdate.push_back(std::make_pair(&((*I).getOperand(IO-1)), 2220 NewCC)); 2221 } 2222 else 2223 switch (CC) { 2224 default: 2225 // CPSR can be used multiple times, we should continue. 2226 break; 2227 case ARMCC::VS: 2228 case ARMCC::VC: 2229 case ARMCC::GE: 2230 case ARMCC::LT: 2231 case ARMCC::GT: 2232 case ARMCC::LE: 2233 return false; 2234 } 2235 } 2236 } 2237 2238 // If CPSR is not killed nor re-defined, we should check whether it is 2239 // live-out. If it is live-out, do not optimize. 2240 if (!isSafe) { 2241 MachineBasicBlock *MBB = CmpInstr->getParent(); 2242 for (MachineBasicBlock::succ_iterator SI = MBB->succ_begin(), 2243 SE = MBB->succ_end(); SI != SE; ++SI) 2244 if ((*SI)->isLiveIn(ARM::CPSR)) 2245 return false; 2246 } 2247 2248 // Toggle the optional operand to CPSR. 2249 MI->getOperand(5).setReg(ARM::CPSR); 2250 MI->getOperand(5).setIsDef(true); 2251 assert(!isPredicated(MI) && "Can't use flags from predicated instruction"); 2252 CmpInstr->eraseFromParent(); 2253 2254 // Modify the condition code of operands in OperandsToUpdate. 2255 // Since we have SUB(r1, r2) and CMP(r2, r1), the condition code needs to 2256 // be changed from r2 > r1 to r1 < r2, from r2 < r1 to r1 > r2, etc. 2257 for (unsigned i = 0, e = OperandsToUpdate.size(); i < e; i++) 2258 OperandsToUpdate[i].first->setImm(OperandsToUpdate[i].second); 2259 return true; 2260 } 2261 } 2262 2263 return false; 2264} 2265 2266bool ARMBaseInstrInfo::FoldImmediate(MachineInstr *UseMI, 2267 MachineInstr *DefMI, unsigned Reg, 2268 MachineRegisterInfo *MRI) const { 2269 // Fold large immediates into add, sub, or, xor. 2270 unsigned DefOpc = DefMI->getOpcode(); 2271 if (DefOpc != ARM::t2MOVi32imm && DefOpc != ARM::MOVi32imm) 2272 return false; 2273 if (!DefMI->getOperand(1).isImm()) 2274 // Could be t2MOVi32imm <ga:xx> 2275 return false; 2276 2277 if (!MRI->hasOneNonDBGUse(Reg)) 2278 return false; 2279 2280 const MCInstrDesc &DefMCID = DefMI->getDesc(); 2281 if (DefMCID.hasOptionalDef()) { 2282 unsigned NumOps = DefMCID.getNumOperands(); 2283 const MachineOperand &MO = DefMI->getOperand(NumOps-1); 2284 if (MO.getReg() == ARM::CPSR && !MO.isDead()) 2285 // If DefMI defines CPSR and it is not dead, it's obviously not safe 2286 // to delete DefMI. 2287 return false; 2288 } 2289 2290 const MCInstrDesc &UseMCID = UseMI->getDesc(); 2291 if (UseMCID.hasOptionalDef()) { 2292 unsigned NumOps = UseMCID.getNumOperands(); 2293 if (UseMI->getOperand(NumOps-1).getReg() == ARM::CPSR) 2294 // If the instruction sets the flag, do not attempt this optimization 2295 // since it may change the semantics of the code. 2296 return false; 2297 } 2298 2299 unsigned UseOpc = UseMI->getOpcode(); 2300 unsigned NewUseOpc = 0; 2301 uint32_t ImmVal = (uint32_t)DefMI->getOperand(1).getImm(); 2302 uint32_t SOImmValV1 = 0, SOImmValV2 = 0; 2303 bool Commute = false; 2304 switch (UseOpc) { 2305 default: return false; 2306 case ARM::SUBrr: 2307 case ARM::ADDrr: 2308 case ARM::ORRrr: 2309 case ARM::EORrr: 2310 case ARM::t2SUBrr: 2311 case ARM::t2ADDrr: 2312 case ARM::t2ORRrr: 2313 case ARM::t2EORrr: { 2314 Commute = UseMI->getOperand(2).getReg() != Reg; 2315 switch (UseOpc) { 2316 default: break; 2317 case ARM::SUBrr: { 2318 if (Commute) 2319 return false; 2320 ImmVal = -ImmVal; 2321 NewUseOpc = ARM::SUBri; 2322 // Fallthrough 2323 } 2324 case ARM::ADDrr: 2325 case ARM::ORRrr: 2326 case ARM::EORrr: { 2327 if (!ARM_AM::isSOImmTwoPartVal(ImmVal)) 2328 return false; 2329 SOImmValV1 = (uint32_t)ARM_AM::getSOImmTwoPartFirst(ImmVal); 2330 SOImmValV2 = (uint32_t)ARM_AM::getSOImmTwoPartSecond(ImmVal); 2331 switch (UseOpc) { 2332 default: break; 2333 case ARM::ADDrr: NewUseOpc = ARM::ADDri; break; 2334 case ARM::ORRrr: NewUseOpc = ARM::ORRri; break; 2335 case ARM::EORrr: NewUseOpc = ARM::EORri; break; 2336 } 2337 break; 2338 } 2339 case ARM::t2SUBrr: { 2340 if (Commute) 2341 return false; 2342 ImmVal = -ImmVal; 2343 NewUseOpc = ARM::t2SUBri; 2344 // Fallthrough 2345 } 2346 case ARM::t2ADDrr: 2347 case ARM::t2ORRrr: 2348 case ARM::t2EORrr: { 2349 if (!ARM_AM::isT2SOImmTwoPartVal(ImmVal)) 2350 return false; 2351 SOImmValV1 = (uint32_t)ARM_AM::getT2SOImmTwoPartFirst(ImmVal); 2352 SOImmValV2 = (uint32_t)ARM_AM::getT2SOImmTwoPartSecond(ImmVal); 2353 switch (UseOpc) { 2354 default: break; 2355 case ARM::t2ADDrr: NewUseOpc = ARM::t2ADDri; break; 2356 case ARM::t2ORRrr: NewUseOpc = ARM::t2ORRri; break; 2357 case ARM::t2EORrr: NewUseOpc = ARM::t2EORri; break; 2358 } 2359 break; 2360 } 2361 } 2362 } 2363 } 2364 2365 unsigned OpIdx = Commute ? 2 : 1; 2366 unsigned Reg1 = UseMI->getOperand(OpIdx).getReg(); 2367 bool isKill = UseMI->getOperand(OpIdx).isKill(); 2368 unsigned NewReg = MRI->createVirtualRegister(MRI->getRegClass(Reg)); 2369 AddDefaultCC(AddDefaultPred(BuildMI(*UseMI->getParent(), 2370 UseMI, UseMI->getDebugLoc(), 2371 get(NewUseOpc), NewReg) 2372 .addReg(Reg1, getKillRegState(isKill)) 2373 .addImm(SOImmValV1))); 2374 UseMI->setDesc(get(NewUseOpc)); 2375 UseMI->getOperand(1).setReg(NewReg); 2376 UseMI->getOperand(1).setIsKill(); 2377 UseMI->getOperand(2).ChangeToImmediate(SOImmValV2); 2378 DefMI->eraseFromParent(); 2379 return true; 2380} 2381 2382static unsigned getNumMicroOpsSwiftLdSt(const InstrItineraryData *ItinData, 2383 const MachineInstr *MI) { 2384 switch (MI->getOpcode()) { 2385 default: { 2386 const MCInstrDesc &Desc = MI->getDesc(); 2387 int UOps = ItinData->getNumMicroOps(Desc.getSchedClass()); 2388 assert(UOps >= 0 && "bad # UOps"); 2389 return UOps; 2390 } 2391 2392 case ARM::LDRrs: 2393 case ARM::LDRBrs: 2394 case ARM::STRrs: 2395 case ARM::STRBrs: { 2396 unsigned ShOpVal = MI->getOperand(3).getImm(); 2397 bool isSub = ARM_AM::getAM2Op(ShOpVal) == ARM_AM::sub; 2398 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal); 2399 if (!isSub && 2400 (ShImm == 0 || 2401 ((ShImm == 1 || ShImm == 2 || ShImm == 3) && 2402 ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl))) 2403 return 1; 2404 return 2; 2405 } 2406 2407 case ARM::LDRH: 2408 case ARM::STRH: { 2409 if (!MI->getOperand(2).getReg()) 2410 return 1; 2411 2412 unsigned ShOpVal = MI->getOperand(3).getImm(); 2413 bool isSub = ARM_AM::getAM2Op(ShOpVal) == ARM_AM::sub; 2414 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal); 2415 if (!isSub && 2416 (ShImm == 0 || 2417 ((ShImm == 1 || ShImm == 2 || ShImm == 3) && 2418 ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl))) 2419 return 1; 2420 return 2; 2421 } 2422 2423 case ARM::LDRSB: 2424 case ARM::LDRSH: 2425 return (ARM_AM::getAM3Op(MI->getOperand(3).getImm()) == ARM_AM::sub) ? 3:2; 2426 2427 case ARM::LDRSB_POST: 2428 case ARM::LDRSH_POST: { 2429 unsigned Rt = MI->getOperand(0).getReg(); 2430 unsigned Rm = MI->getOperand(3).getReg(); 2431 return (Rt == Rm) ? 4 : 3; 2432 } 2433 2434 case ARM::LDR_PRE_REG: 2435 case ARM::LDRB_PRE_REG: { 2436 unsigned Rt = MI->getOperand(0).getReg(); 2437 unsigned Rm = MI->getOperand(3).getReg(); 2438 if (Rt == Rm) 2439 return 3; 2440 unsigned ShOpVal = MI->getOperand(4).getImm(); 2441 bool isSub = ARM_AM::getAM2Op(ShOpVal) == ARM_AM::sub; 2442 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal); 2443 if (!isSub && 2444 (ShImm == 0 || 2445 ((ShImm == 1 || ShImm == 2 || ShImm == 3) && 2446 ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl))) 2447 return 2; 2448 return 3; 2449 } 2450 2451 case ARM::STR_PRE_REG: 2452 case ARM::STRB_PRE_REG: { 2453 unsigned ShOpVal = MI->getOperand(4).getImm(); 2454 bool isSub = ARM_AM::getAM2Op(ShOpVal) == ARM_AM::sub; 2455 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal); 2456 if (!isSub && 2457 (ShImm == 0 || 2458 ((ShImm == 1 || ShImm == 2 || ShImm == 3) && 2459 ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl))) 2460 return 2; 2461 return 3; 2462 } 2463 2464 case ARM::LDRH_PRE: 2465 case ARM::STRH_PRE: { 2466 unsigned Rt = MI->getOperand(0).getReg(); 2467 unsigned Rm = MI->getOperand(3).getReg(); 2468 if (!Rm) 2469 return 2; 2470 if (Rt == Rm) 2471 return 3; 2472 return (ARM_AM::getAM3Op(MI->getOperand(4).getImm()) == ARM_AM::sub) 2473 ? 3 : 2; 2474 } 2475 2476 case ARM::LDR_POST_REG: 2477 case ARM::LDRB_POST_REG: 2478 case ARM::LDRH_POST: { 2479 unsigned Rt = MI->getOperand(0).getReg(); 2480 unsigned Rm = MI->getOperand(3).getReg(); 2481 return (Rt == Rm) ? 3 : 2; 2482 } 2483 2484 case ARM::LDR_PRE_IMM: 2485 case ARM::LDRB_PRE_IMM: 2486 case ARM::LDR_POST_IMM: 2487 case ARM::LDRB_POST_IMM: 2488 case ARM::STRB_POST_IMM: 2489 case ARM::STRB_POST_REG: 2490 case ARM::STRB_PRE_IMM: 2491 case ARM::STRH_POST: 2492 case ARM::STR_POST_IMM: 2493 case ARM::STR_POST_REG: 2494 case ARM::STR_PRE_IMM: 2495 return 2; 2496 2497 case ARM::LDRSB_PRE: 2498 case ARM::LDRSH_PRE: { 2499 unsigned Rm = MI->getOperand(3).getReg(); 2500 if (Rm == 0) 2501 return 3; 2502 unsigned Rt = MI->getOperand(0).getReg(); 2503 if (Rt == Rm) 2504 return 4; 2505 unsigned ShOpVal = MI->getOperand(4).getImm(); 2506 bool isSub = ARM_AM::getAM2Op(ShOpVal) == ARM_AM::sub; 2507 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal); 2508 if (!isSub && 2509 (ShImm == 0 || 2510 ((ShImm == 1 || ShImm == 2 || ShImm == 3) && 2511 ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl))) 2512 return 3; 2513 return 4; 2514 } 2515 2516 case ARM::LDRD: { 2517 unsigned Rt = MI->getOperand(0).getReg(); 2518 unsigned Rn = MI->getOperand(2).getReg(); 2519 unsigned Rm = MI->getOperand(3).getReg(); 2520 if (Rm) 2521 return (ARM_AM::getAM3Op(MI->getOperand(4).getImm()) == ARM_AM::sub) ?4:3; 2522 return (Rt == Rn) ? 3 : 2; 2523 } 2524 2525 case ARM::STRD: { 2526 unsigned Rm = MI->getOperand(3).getReg(); 2527 if (Rm) 2528 return (ARM_AM::getAM3Op(MI->getOperand(4).getImm()) == ARM_AM::sub) ?4:3; 2529 return 2; 2530 } 2531 2532 case ARM::LDRD_POST: 2533 case ARM::t2LDRD_POST: 2534 return 3; 2535 2536 case ARM::STRD_POST: 2537 case ARM::t2STRD_POST: 2538 return 4; 2539 2540 case ARM::LDRD_PRE: { 2541 unsigned Rt = MI->getOperand(0).getReg(); 2542 unsigned Rn = MI->getOperand(3).getReg(); 2543 unsigned Rm = MI->getOperand(4).getReg(); 2544 if (Rm) 2545 return (ARM_AM::getAM3Op(MI->getOperand(5).getImm()) == ARM_AM::sub) ?5:4; 2546 return (Rt == Rn) ? 4 : 3; 2547 } 2548 2549 case ARM::t2LDRD_PRE: { 2550 unsigned Rt = MI->getOperand(0).getReg(); 2551 unsigned Rn = MI->getOperand(3).getReg(); 2552 return (Rt == Rn) ? 4 : 3; 2553 } 2554 2555 case ARM::STRD_PRE: { 2556 unsigned Rm = MI->getOperand(4).getReg(); 2557 if (Rm) 2558 return (ARM_AM::getAM3Op(MI->getOperand(5).getImm()) == ARM_AM::sub) ?5:4; 2559 return 3; 2560 } 2561 2562 case ARM::t2STRD_PRE: 2563 return 3; 2564 2565 case ARM::t2LDR_POST: 2566 case ARM::t2LDRB_POST: 2567 case ARM::t2LDRB_PRE: 2568 case ARM::t2LDRSBi12: 2569 case ARM::t2LDRSBi8: 2570 case ARM::t2LDRSBpci: 2571 case ARM::t2LDRSBs: 2572 case ARM::t2LDRH_POST: 2573 case ARM::t2LDRH_PRE: 2574 case ARM::t2LDRSBT: 2575 case ARM::t2LDRSB_POST: 2576 case ARM::t2LDRSB_PRE: 2577 case ARM::t2LDRSH_POST: 2578 case ARM::t2LDRSH_PRE: 2579 case ARM::t2LDRSHi12: 2580 case ARM::t2LDRSHi8: 2581 case ARM::t2LDRSHpci: 2582 case ARM::t2LDRSHs: 2583 return 2; 2584 2585 case ARM::t2LDRDi8: { 2586 unsigned Rt = MI->getOperand(0).getReg(); 2587 unsigned Rn = MI->getOperand(2).getReg(); 2588 return (Rt == Rn) ? 3 : 2; 2589 } 2590 2591 case ARM::t2STRB_POST: 2592 case ARM::t2STRB_PRE: 2593 case ARM::t2STRBs: 2594 case ARM::t2STRDi8: 2595 case ARM::t2STRH_POST: 2596 case ARM::t2STRH_PRE: 2597 case ARM::t2STRHs: 2598 case ARM::t2STR_POST: 2599 case ARM::t2STR_PRE: 2600 case ARM::t2STRs: 2601 return 2; 2602 } 2603} 2604 2605// Return the number of 32-bit words loaded by LDM or stored by STM. If this 2606// can't be easily determined return 0 (missing MachineMemOperand). 2607// 2608// FIXME: The current MachineInstr design does not support relying on machine 2609// mem operands to determine the width of a memory access. Instead, we expect 2610// the target to provide this information based on the instruction opcode and 2611// operands. However, using MachineMemOperand is a the best solution now for 2612// two reasons: 2613// 2614// 1) getNumMicroOps tries to infer LDM memory width from the total number of MI 2615// operands. This is much more dangerous than using the MachineMemOperand 2616// sizes because CodeGen passes can insert/remove optional machine operands. In 2617// fact, it's totally incorrect for preRA passes and appears to be wrong for 2618// postRA passes as well. 2619// 2620// 2) getNumLDMAddresses is only used by the scheduling machine model and any 2621// machine model that calls this should handle the unknown (zero size) case. 2622// 2623// Long term, we should require a target hook that verifies MachineMemOperand 2624// sizes during MC lowering. That target hook should be local to MC lowering 2625// because we can't ensure that it is aware of other MI forms. Doing this will 2626// ensure that MachineMemOperands are correctly propagated through all passes. 2627unsigned ARMBaseInstrInfo::getNumLDMAddresses(const MachineInstr *MI) const { 2628 unsigned Size = 0; 2629 for (MachineInstr::mmo_iterator I = MI->memoperands_begin(), 2630 E = MI->memoperands_end(); I != E; ++I) { 2631 Size += (*I)->getSize(); 2632 } 2633 return Size / 4; 2634} 2635 2636unsigned 2637ARMBaseInstrInfo::getNumMicroOps(const InstrItineraryData *ItinData, 2638 const MachineInstr *MI) const { 2639 if (!ItinData || ItinData->isEmpty()) 2640 return 1; 2641 2642 const MCInstrDesc &Desc = MI->getDesc(); 2643 unsigned Class = Desc.getSchedClass(); 2644 int ItinUOps = ItinData->getNumMicroOps(Class); 2645 if (ItinUOps >= 0) { 2646 if (Subtarget.isSwift() && (Desc.mayLoad() || Desc.mayStore())) 2647 return getNumMicroOpsSwiftLdSt(ItinData, MI); 2648 2649 return ItinUOps; 2650 } 2651 2652 unsigned Opc = MI->getOpcode(); 2653 switch (Opc) { 2654 default: 2655 llvm_unreachable("Unexpected multi-uops instruction!"); 2656 case ARM::VLDMQIA: 2657 case ARM::VSTMQIA: 2658 return 2; 2659 2660 // The number of uOps for load / store multiple are determined by the number 2661 // registers. 2662 // 2663 // On Cortex-A8, each pair of register loads / stores can be scheduled on the 2664 // same cycle. The scheduling for the first load / store must be done 2665 // separately by assuming the address is not 64-bit aligned. 2666 // 2667 // On Cortex-A9, the formula is simply (#reg / 2) + (#reg % 2). If the address 2668 // is not 64-bit aligned, then AGU would take an extra cycle. For VFP / NEON 2669 // load / store multiple, the formula is (#reg / 2) + (#reg % 2) + 1. 2670 case ARM::VLDMDIA: 2671 case ARM::VLDMDIA_UPD: 2672 case ARM::VLDMDDB_UPD: 2673 case ARM::VLDMSIA: 2674 case ARM::VLDMSIA_UPD: 2675 case ARM::VLDMSDB_UPD: 2676 case ARM::VSTMDIA: 2677 case ARM::VSTMDIA_UPD: 2678 case ARM::VSTMDDB_UPD: 2679 case ARM::VSTMSIA: 2680 case ARM::VSTMSIA_UPD: 2681 case ARM::VSTMSDB_UPD: { 2682 unsigned NumRegs = MI->getNumOperands() - Desc.getNumOperands(); 2683 return (NumRegs / 2) + (NumRegs % 2) + 1; 2684 } 2685 2686 case ARM::LDMIA_RET: 2687 case ARM::LDMIA: 2688 case ARM::LDMDA: 2689 case ARM::LDMDB: 2690 case ARM::LDMIB: 2691 case ARM::LDMIA_UPD: 2692 case ARM::LDMDA_UPD: 2693 case ARM::LDMDB_UPD: 2694 case ARM::LDMIB_UPD: 2695 case ARM::STMIA: 2696 case ARM::STMDA: 2697 case ARM::STMDB: 2698 case ARM::STMIB: 2699 case ARM::STMIA_UPD: 2700 case ARM::STMDA_UPD: 2701 case ARM::STMDB_UPD: 2702 case ARM::STMIB_UPD: 2703 case ARM::tLDMIA: 2704 case ARM::tLDMIA_UPD: 2705 case ARM::tSTMIA_UPD: 2706 case ARM::tPOP_RET: 2707 case ARM::tPOP: 2708 case ARM::tPUSH: 2709 case ARM::t2LDMIA_RET: 2710 case ARM::t2LDMIA: 2711 case ARM::t2LDMDB: 2712 case ARM::t2LDMIA_UPD: 2713 case ARM::t2LDMDB_UPD: 2714 case ARM::t2STMIA: 2715 case ARM::t2STMDB: 2716 case ARM::t2STMIA_UPD: 2717 case ARM::t2STMDB_UPD: { 2718 unsigned NumRegs = MI->getNumOperands() - Desc.getNumOperands() + 1; 2719 if (Subtarget.isSwift()) { 2720 // rdar://8402126 2721 int UOps = 1 + NumRegs; // One for address computation, one for each ld / st. 2722 switch (Opc) { 2723 default: break; 2724 case ARM::VLDMDIA_UPD: 2725 case ARM::VLDMDDB_UPD: 2726 case ARM::VLDMSIA_UPD: 2727 case ARM::VLDMSDB_UPD: 2728 case ARM::VSTMDIA_UPD: 2729 case ARM::VSTMDDB_UPD: 2730 case ARM::VSTMSIA_UPD: 2731 case ARM::VSTMSDB_UPD: 2732 case ARM::LDMIA_UPD: 2733 case ARM::LDMDA_UPD: 2734 case ARM::LDMDB_UPD: 2735 case ARM::LDMIB_UPD: 2736 case ARM::STMIA_UPD: 2737 case ARM::STMDA_UPD: 2738 case ARM::STMDB_UPD: 2739 case ARM::STMIB_UPD: 2740 case ARM::tLDMIA_UPD: 2741 case ARM::tSTMIA_UPD: 2742 case ARM::t2LDMIA_UPD: 2743 case ARM::t2LDMDB_UPD: 2744 case ARM::t2STMIA_UPD: 2745 case ARM::t2STMDB_UPD: 2746 ++UOps; // One for base register writeback. 2747 break; 2748 case ARM::LDMIA_RET: 2749 case ARM::tPOP_RET: 2750 case ARM::t2LDMIA_RET: 2751 UOps += 2; // One for base reg wb, one for write to pc. 2752 break; 2753 } 2754 return UOps; 2755 } else if (Subtarget.isCortexA8()) { 2756 if (NumRegs < 4) 2757 return 2; 2758 // 4 registers would be issued: 2, 2. 2759 // 5 registers would be issued: 2, 2, 1. 2760 int A8UOps = (NumRegs / 2); 2761 if (NumRegs % 2) 2762 ++A8UOps; 2763 return A8UOps; 2764 } else if (Subtarget.isLikeA9() || Subtarget.isSwift()) { 2765 int A9UOps = (NumRegs / 2); 2766 // If there are odd number of registers or if it's not 64-bit aligned, 2767 // then it takes an extra AGU (Address Generation Unit) cycle. 2768 if ((NumRegs % 2) || 2769 !MI->hasOneMemOperand() || 2770 (*MI->memoperands_begin())->getAlignment() < 8) 2771 ++A9UOps; 2772 return A9UOps; 2773 } else { 2774 // Assume the worst. 2775 return NumRegs; 2776 } 2777 } 2778 } 2779} 2780 2781int 2782ARMBaseInstrInfo::getVLDMDefCycle(const InstrItineraryData *ItinData, 2783 const MCInstrDesc &DefMCID, 2784 unsigned DefClass, 2785 unsigned DefIdx, unsigned DefAlign) const { 2786 int RegNo = (int)(DefIdx+1) - DefMCID.getNumOperands() + 1; 2787 if (RegNo <= 0) 2788 // Def is the address writeback. 2789 return ItinData->getOperandCycle(DefClass, DefIdx); 2790 2791 int DefCycle; 2792 if (Subtarget.isCortexA8()) { 2793 // (regno / 2) + (regno % 2) + 1 2794 DefCycle = RegNo / 2 + 1; 2795 if (RegNo % 2) 2796 ++DefCycle; 2797 } else if (Subtarget.isLikeA9() || Subtarget.isSwift()) { 2798 DefCycle = RegNo; 2799 bool isSLoad = false; 2800 2801 switch (DefMCID.getOpcode()) { 2802 default: break; 2803 case ARM::VLDMSIA: 2804 case ARM::VLDMSIA_UPD: 2805 case ARM::VLDMSDB_UPD: 2806 isSLoad = true; 2807 break; 2808 } 2809 2810 // If there are odd number of 'S' registers or if it's not 64-bit aligned, 2811 // then it takes an extra cycle. 2812 if ((isSLoad && (RegNo % 2)) || DefAlign < 8) 2813 ++DefCycle; 2814 } else { 2815 // Assume the worst. 2816 DefCycle = RegNo + 2; 2817 } 2818 2819 return DefCycle; 2820} 2821 2822int 2823ARMBaseInstrInfo::getLDMDefCycle(const InstrItineraryData *ItinData, 2824 const MCInstrDesc &DefMCID, 2825 unsigned DefClass, 2826 unsigned DefIdx, unsigned DefAlign) const { 2827 int RegNo = (int)(DefIdx+1) - DefMCID.getNumOperands() + 1; 2828 if (RegNo <= 0) 2829 // Def is the address writeback. 2830 return ItinData->getOperandCycle(DefClass, DefIdx); 2831 2832 int DefCycle; 2833 if (Subtarget.isCortexA8()) { 2834 // 4 registers would be issued: 1, 2, 1. 2835 // 5 registers would be issued: 1, 2, 2. 2836 DefCycle = RegNo / 2; 2837 if (DefCycle < 1) 2838 DefCycle = 1; 2839 // Result latency is issue cycle + 2: E2. 2840 DefCycle += 2; 2841 } else if (Subtarget.isLikeA9() || Subtarget.isSwift()) { 2842 DefCycle = (RegNo / 2); 2843 // If there are odd number of registers or if it's not 64-bit aligned, 2844 // then it takes an extra AGU (Address Generation Unit) cycle. 2845 if ((RegNo % 2) || DefAlign < 8) 2846 ++DefCycle; 2847 // Result latency is AGU cycles + 2. 2848 DefCycle += 2; 2849 } else { 2850 // Assume the worst. 2851 DefCycle = RegNo + 2; 2852 } 2853 2854 return DefCycle; 2855} 2856 2857int 2858ARMBaseInstrInfo::getVSTMUseCycle(const InstrItineraryData *ItinData, 2859 const MCInstrDesc &UseMCID, 2860 unsigned UseClass, 2861 unsigned UseIdx, unsigned UseAlign) const { 2862 int RegNo = (int)(UseIdx+1) - UseMCID.getNumOperands() + 1; 2863 if (RegNo <= 0) 2864 return ItinData->getOperandCycle(UseClass, UseIdx); 2865 2866 int UseCycle; 2867 if (Subtarget.isCortexA8()) { 2868 // (regno / 2) + (regno % 2) + 1 2869 UseCycle = RegNo / 2 + 1; 2870 if (RegNo % 2) 2871 ++UseCycle; 2872 } else if (Subtarget.isLikeA9() || Subtarget.isSwift()) { 2873 UseCycle = RegNo; 2874 bool isSStore = false; 2875 2876 switch (UseMCID.getOpcode()) { 2877 default: break; 2878 case ARM::VSTMSIA: 2879 case ARM::VSTMSIA_UPD: 2880 case ARM::VSTMSDB_UPD: 2881 isSStore = true; 2882 break; 2883 } 2884 2885 // If there are odd number of 'S' registers or if it's not 64-bit aligned, 2886 // then it takes an extra cycle. 2887 if ((isSStore && (RegNo % 2)) || UseAlign < 8) 2888 ++UseCycle; 2889 } else { 2890 // Assume the worst. 2891 UseCycle = RegNo + 2; 2892 } 2893 2894 return UseCycle; 2895} 2896 2897int 2898ARMBaseInstrInfo::getSTMUseCycle(const InstrItineraryData *ItinData, 2899 const MCInstrDesc &UseMCID, 2900 unsigned UseClass, 2901 unsigned UseIdx, unsigned UseAlign) const { 2902 int RegNo = (int)(UseIdx+1) - UseMCID.getNumOperands() + 1; 2903 if (RegNo <= 0) 2904 return ItinData->getOperandCycle(UseClass, UseIdx); 2905 2906 int UseCycle; 2907 if (Subtarget.isCortexA8()) { 2908 UseCycle = RegNo / 2; 2909 if (UseCycle < 2) 2910 UseCycle = 2; 2911 // Read in E3. 2912 UseCycle += 2; 2913 } else if (Subtarget.isLikeA9() || Subtarget.isSwift()) { 2914 UseCycle = (RegNo / 2); 2915 // If there are odd number of registers or if it's not 64-bit aligned, 2916 // then it takes an extra AGU (Address Generation Unit) cycle. 2917 if ((RegNo % 2) || UseAlign < 8) 2918 ++UseCycle; 2919 } else { 2920 // Assume the worst. 2921 UseCycle = 1; 2922 } 2923 return UseCycle; 2924} 2925 2926int 2927ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData, 2928 const MCInstrDesc &DefMCID, 2929 unsigned DefIdx, unsigned DefAlign, 2930 const MCInstrDesc &UseMCID, 2931 unsigned UseIdx, unsigned UseAlign) const { 2932 unsigned DefClass = DefMCID.getSchedClass(); 2933 unsigned UseClass = UseMCID.getSchedClass(); 2934 2935 if (DefIdx < DefMCID.getNumDefs() && UseIdx < UseMCID.getNumOperands()) 2936 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx); 2937 2938 // This may be a def / use of a variable_ops instruction, the operand 2939 // latency might be determinable dynamically. Let the target try to 2940 // figure it out. 2941 int DefCycle = -1; 2942 bool LdmBypass = false; 2943 switch (DefMCID.getOpcode()) { 2944 default: 2945 DefCycle = ItinData->getOperandCycle(DefClass, DefIdx); 2946 break; 2947 2948 case ARM::VLDMDIA: 2949 case ARM::VLDMDIA_UPD: 2950 case ARM::VLDMDDB_UPD: 2951 case ARM::VLDMSIA: 2952 case ARM::VLDMSIA_UPD: 2953 case ARM::VLDMSDB_UPD: 2954 DefCycle = getVLDMDefCycle(ItinData, DefMCID, DefClass, DefIdx, DefAlign); 2955 break; 2956 2957 case ARM::LDMIA_RET: 2958 case ARM::LDMIA: 2959 case ARM::LDMDA: 2960 case ARM::LDMDB: 2961 case ARM::LDMIB: 2962 case ARM::LDMIA_UPD: 2963 case ARM::LDMDA_UPD: 2964 case ARM::LDMDB_UPD: 2965 case ARM::LDMIB_UPD: 2966 case ARM::tLDMIA: 2967 case ARM::tLDMIA_UPD: 2968 case ARM::tPUSH: 2969 case ARM::t2LDMIA_RET: 2970 case ARM::t2LDMIA: 2971 case ARM::t2LDMDB: 2972 case ARM::t2LDMIA_UPD: 2973 case ARM::t2LDMDB_UPD: 2974 LdmBypass = 1; 2975 DefCycle = getLDMDefCycle(ItinData, DefMCID, DefClass, DefIdx, DefAlign); 2976 break; 2977 } 2978 2979 if (DefCycle == -1) 2980 // We can't seem to determine the result latency of the def, assume it's 2. 2981 DefCycle = 2; 2982 2983 int UseCycle = -1; 2984 switch (UseMCID.getOpcode()) { 2985 default: 2986 UseCycle = ItinData->getOperandCycle(UseClass, UseIdx); 2987 break; 2988 2989 case ARM::VSTMDIA: 2990 case ARM::VSTMDIA_UPD: 2991 case ARM::VSTMDDB_UPD: 2992 case ARM::VSTMSIA: 2993 case ARM::VSTMSIA_UPD: 2994 case ARM::VSTMSDB_UPD: 2995 UseCycle = getVSTMUseCycle(ItinData, UseMCID, UseClass, UseIdx, UseAlign); 2996 break; 2997 2998 case ARM::STMIA: 2999 case ARM::STMDA: 3000 case ARM::STMDB: 3001 case ARM::STMIB: 3002 case ARM::STMIA_UPD: 3003 case ARM::STMDA_UPD: 3004 case ARM::STMDB_UPD: 3005 case ARM::STMIB_UPD: 3006 case ARM::tSTMIA_UPD: 3007 case ARM::tPOP_RET: 3008 case ARM::tPOP: 3009 case ARM::t2STMIA: 3010 case ARM::t2STMDB: 3011 case ARM::t2STMIA_UPD: 3012 case ARM::t2STMDB_UPD: 3013 UseCycle = getSTMUseCycle(ItinData, UseMCID, UseClass, UseIdx, UseAlign); 3014 break; 3015 } 3016 3017 if (UseCycle == -1) 3018 // Assume it's read in the first stage. 3019 UseCycle = 1; 3020 3021 UseCycle = DefCycle - UseCycle + 1; 3022 if (UseCycle > 0) { 3023 if (LdmBypass) { 3024 // It's a variable_ops instruction so we can't use DefIdx here. Just use 3025 // first def operand. 3026 if (ItinData->hasPipelineForwarding(DefClass, DefMCID.getNumOperands()-1, 3027 UseClass, UseIdx)) 3028 --UseCycle; 3029 } else if (ItinData->hasPipelineForwarding(DefClass, DefIdx, 3030 UseClass, UseIdx)) { 3031 --UseCycle; 3032 } 3033 } 3034 3035 return UseCycle; 3036} 3037 3038static const MachineInstr *getBundledDefMI(const TargetRegisterInfo *TRI, 3039 const MachineInstr *MI, unsigned Reg, 3040 unsigned &DefIdx, unsigned &Dist) { 3041 Dist = 0; 3042 3043 MachineBasicBlock::const_iterator I = MI; ++I; 3044 MachineBasicBlock::const_instr_iterator II = 3045 llvm::prior(I.getInstrIterator()); 3046 assert(II->isInsideBundle() && "Empty bundle?"); 3047 3048 int Idx = -1; 3049 while (II->isInsideBundle()) { 3050 Idx = II->findRegisterDefOperandIdx(Reg, false, true, TRI); 3051 if (Idx != -1) 3052 break; 3053 --II; 3054 ++Dist; 3055 } 3056 3057 assert(Idx != -1 && "Cannot find bundled definition!"); 3058 DefIdx = Idx; 3059 return II; 3060} 3061 3062static const MachineInstr *getBundledUseMI(const TargetRegisterInfo *TRI, 3063 const MachineInstr *MI, unsigned Reg, 3064 unsigned &UseIdx, unsigned &Dist) { 3065 Dist = 0; 3066 3067 MachineBasicBlock::const_instr_iterator II = MI; ++II; 3068 assert(II->isInsideBundle() && "Empty bundle?"); 3069 MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end(); 3070 3071 // FIXME: This doesn't properly handle multiple uses. 3072 int Idx = -1; 3073 while (II != E && II->isInsideBundle()) { 3074 Idx = II->findRegisterUseOperandIdx(Reg, false, TRI); 3075 if (Idx != -1) 3076 break; 3077 if (II->getOpcode() != ARM::t2IT) 3078 ++Dist; 3079 ++II; 3080 } 3081 3082 if (Idx == -1) { 3083 Dist = 0; 3084 return 0; 3085 } 3086 3087 UseIdx = Idx; 3088 return II; 3089} 3090 3091/// Return the number of cycles to add to (or subtract from) the static 3092/// itinerary based on the def opcode and alignment. The caller will ensure that 3093/// adjusted latency is at least one cycle. 3094static int adjustDefLatency(const ARMSubtarget &Subtarget, 3095 const MachineInstr *DefMI, 3096 const MCInstrDesc *DefMCID, unsigned DefAlign) { 3097 int Adjust = 0; 3098 if (Subtarget.isCortexA8() || Subtarget.isLikeA9()) { 3099 // FIXME: Shifter op hack: no shift (i.e. [r +/- r]) or [r + r << 2] 3100 // variants are one cycle cheaper. 3101 switch (DefMCID->getOpcode()) { 3102 default: break; 3103 case ARM::LDRrs: 3104 case ARM::LDRBrs: { 3105 unsigned ShOpVal = DefMI->getOperand(3).getImm(); 3106 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal); 3107 if (ShImm == 0 || 3108 (ShImm == 2 && ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl)) 3109 --Adjust; 3110 break; 3111 } 3112 case ARM::t2LDRs: 3113 case ARM::t2LDRBs: 3114 case ARM::t2LDRHs: 3115 case ARM::t2LDRSHs: { 3116 // Thumb2 mode: lsl only. 3117 unsigned ShAmt = DefMI->getOperand(3).getImm(); 3118 if (ShAmt == 0 || ShAmt == 2) 3119 --Adjust; 3120 break; 3121 } 3122 } 3123 } else if (Subtarget.isSwift()) { 3124 // FIXME: Properly handle all of the latency adjustments for address 3125 // writeback. 3126 switch (DefMCID->getOpcode()) { 3127 default: break; 3128 case ARM::LDRrs: 3129 case ARM::LDRBrs: { 3130 unsigned ShOpVal = DefMI->getOperand(3).getImm(); 3131 bool isSub = ARM_AM::getAM2Op(ShOpVal) == ARM_AM::sub; 3132 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal); 3133 if (!isSub && 3134 (ShImm == 0 || 3135 ((ShImm == 1 || ShImm == 2 || ShImm == 3) && 3136 ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl))) 3137 Adjust -= 2; 3138 else if (!isSub && 3139 ShImm == 1 && ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsr) 3140 --Adjust; 3141 break; 3142 } 3143 case ARM::t2LDRs: 3144 case ARM::t2LDRBs: 3145 case ARM::t2LDRHs: 3146 case ARM::t2LDRSHs: { 3147 // Thumb2 mode: lsl only. 3148 unsigned ShAmt = DefMI->getOperand(3).getImm(); 3149 if (ShAmt == 0 || ShAmt == 1 || ShAmt == 2 || ShAmt == 3) 3150 Adjust -= 2; 3151 break; 3152 } 3153 } 3154 } 3155 3156 if (DefAlign < 8 && Subtarget.isLikeA9()) { 3157 switch (DefMCID->getOpcode()) { 3158 default: break; 3159 case ARM::VLD1q8: 3160 case ARM::VLD1q16: 3161 case ARM::VLD1q32: 3162 case ARM::VLD1q64: 3163 case ARM::VLD1q8wb_fixed: 3164 case ARM::VLD1q16wb_fixed: 3165 case ARM::VLD1q32wb_fixed: 3166 case ARM::VLD1q64wb_fixed: 3167 case ARM::VLD1q8wb_register: 3168 case ARM::VLD1q16wb_register: 3169 case ARM::VLD1q32wb_register: 3170 case ARM::VLD1q64wb_register: 3171 case ARM::VLD2d8: 3172 case ARM::VLD2d16: 3173 case ARM::VLD2d32: 3174 case ARM::VLD2q8: 3175 case ARM::VLD2q16: 3176 case ARM::VLD2q32: 3177 case ARM::VLD2d8wb_fixed: 3178 case ARM::VLD2d16wb_fixed: 3179 case ARM::VLD2d32wb_fixed: 3180 case ARM::VLD2q8wb_fixed: 3181 case ARM::VLD2q16wb_fixed: 3182 case ARM::VLD2q32wb_fixed: 3183 case ARM::VLD2d8wb_register: 3184 case ARM::VLD2d16wb_register: 3185 case ARM::VLD2d32wb_register: 3186 case ARM::VLD2q8wb_register: 3187 case ARM::VLD2q16wb_register: 3188 case ARM::VLD2q32wb_register: 3189 case ARM::VLD3d8: 3190 case ARM::VLD3d16: 3191 case ARM::VLD3d32: 3192 case ARM::VLD1d64T: 3193 case ARM::VLD3d8_UPD: 3194 case ARM::VLD3d16_UPD: 3195 case ARM::VLD3d32_UPD: 3196 case ARM::VLD1d64Twb_fixed: 3197 case ARM::VLD1d64Twb_register: 3198 case ARM::VLD3q8_UPD: 3199 case ARM::VLD3q16_UPD: 3200 case ARM::VLD3q32_UPD: 3201 case ARM::VLD4d8: 3202 case ARM::VLD4d16: 3203 case ARM::VLD4d32: 3204 case ARM::VLD1d64Q: 3205 case ARM::VLD4d8_UPD: 3206 case ARM::VLD4d16_UPD: 3207 case ARM::VLD4d32_UPD: 3208 case ARM::VLD1d64Qwb_fixed: 3209 case ARM::VLD1d64Qwb_register: 3210 case ARM::VLD4q8_UPD: 3211 case ARM::VLD4q16_UPD: 3212 case ARM::VLD4q32_UPD: 3213 case ARM::VLD1DUPq8: 3214 case ARM::VLD1DUPq16: 3215 case ARM::VLD1DUPq32: 3216 case ARM::VLD1DUPq8wb_fixed: 3217 case ARM::VLD1DUPq16wb_fixed: 3218 case ARM::VLD1DUPq32wb_fixed: 3219 case ARM::VLD1DUPq8wb_register: 3220 case ARM::VLD1DUPq16wb_register: 3221 case ARM::VLD1DUPq32wb_register: 3222 case ARM::VLD2DUPd8: 3223 case ARM::VLD2DUPd16: 3224 case ARM::VLD2DUPd32: 3225 case ARM::VLD2DUPd8wb_fixed: 3226 case ARM::VLD2DUPd16wb_fixed: 3227 case ARM::VLD2DUPd32wb_fixed: 3228 case ARM::VLD2DUPd8wb_register: 3229 case ARM::VLD2DUPd16wb_register: 3230 case ARM::VLD2DUPd32wb_register: 3231 case ARM::VLD4DUPd8: 3232 case ARM::VLD4DUPd16: 3233 case ARM::VLD4DUPd32: 3234 case ARM::VLD4DUPd8_UPD: 3235 case ARM::VLD4DUPd16_UPD: 3236 case ARM::VLD4DUPd32_UPD: 3237 case ARM::VLD1LNd8: 3238 case ARM::VLD1LNd16: 3239 case ARM::VLD1LNd32: 3240 case ARM::VLD1LNd8_UPD: 3241 case ARM::VLD1LNd16_UPD: 3242 case ARM::VLD1LNd32_UPD: 3243 case ARM::VLD2LNd8: 3244 case ARM::VLD2LNd16: 3245 case ARM::VLD2LNd32: 3246 case ARM::VLD2LNq16: 3247 case ARM::VLD2LNq32: 3248 case ARM::VLD2LNd8_UPD: 3249 case ARM::VLD2LNd16_UPD: 3250 case ARM::VLD2LNd32_UPD: 3251 case ARM::VLD2LNq16_UPD: 3252 case ARM::VLD2LNq32_UPD: 3253 case ARM::VLD4LNd8: 3254 case ARM::VLD4LNd16: 3255 case ARM::VLD4LNd32: 3256 case ARM::VLD4LNq16: 3257 case ARM::VLD4LNq32: 3258 case ARM::VLD4LNd8_UPD: 3259 case ARM::VLD4LNd16_UPD: 3260 case ARM::VLD4LNd32_UPD: 3261 case ARM::VLD4LNq16_UPD: 3262 case ARM::VLD4LNq32_UPD: 3263 // If the address is not 64-bit aligned, the latencies of these 3264 // instructions increases by one. 3265 ++Adjust; 3266 break; 3267 } 3268 } 3269 return Adjust; 3270} 3271 3272 3273 3274int 3275ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData, 3276 const MachineInstr *DefMI, unsigned DefIdx, 3277 const MachineInstr *UseMI, 3278 unsigned UseIdx) const { 3279 // No operand latency. The caller may fall back to getInstrLatency. 3280 if (!ItinData || ItinData->isEmpty()) 3281 return -1; 3282 3283 const MachineOperand &DefMO = DefMI->getOperand(DefIdx); 3284 unsigned Reg = DefMO.getReg(); 3285 const MCInstrDesc *DefMCID = &DefMI->getDesc(); 3286 const MCInstrDesc *UseMCID = &UseMI->getDesc(); 3287 3288 unsigned DefAdj = 0; 3289 if (DefMI->isBundle()) { 3290 DefMI = getBundledDefMI(&getRegisterInfo(), DefMI, Reg, DefIdx, DefAdj); 3291 DefMCID = &DefMI->getDesc(); 3292 } 3293 if (DefMI->isCopyLike() || DefMI->isInsertSubreg() || 3294 DefMI->isRegSequence() || DefMI->isImplicitDef()) { 3295 return 1; 3296 } 3297 3298 unsigned UseAdj = 0; 3299 if (UseMI->isBundle()) { 3300 unsigned NewUseIdx; 3301 const MachineInstr *NewUseMI = getBundledUseMI(&getRegisterInfo(), UseMI, 3302 Reg, NewUseIdx, UseAdj); 3303 if (!NewUseMI) 3304 return -1; 3305 3306 UseMI = NewUseMI; 3307 UseIdx = NewUseIdx; 3308 UseMCID = &UseMI->getDesc(); 3309 } 3310 3311 if (Reg == ARM::CPSR) { 3312 if (DefMI->getOpcode() == ARM::FMSTAT) { 3313 // fpscr -> cpsr stalls over 20 cycles on A8 (and earlier?) 3314 return Subtarget.isLikeA9() ? 1 : 20; 3315 } 3316 3317 // CPSR set and branch can be paired in the same cycle. 3318 if (UseMI->isBranch()) 3319 return 0; 3320 3321 // Otherwise it takes the instruction latency (generally one). 3322 unsigned Latency = getInstrLatency(ItinData, DefMI); 3323 3324 // For Thumb2 and -Os, prefer scheduling CPSR setting instruction close to 3325 // its uses. Instructions which are otherwise scheduled between them may 3326 // incur a code size penalty (not able to use the CPSR setting 16-bit 3327 // instructions). 3328 if (Latency > 0 && Subtarget.isThumb2()) { 3329 const MachineFunction *MF = DefMI->getParent()->getParent(); 3330 if (MF->getFunction()->getFnAttributes(). 3331 hasAttribute(Attributes::OptimizeForSize)) 3332 --Latency; 3333 } 3334 return Latency; 3335 } 3336 3337 if (DefMO.isImplicit() || UseMI->getOperand(UseIdx).isImplicit()) 3338 return -1; 3339 3340 unsigned DefAlign = DefMI->hasOneMemOperand() 3341 ? (*DefMI->memoperands_begin())->getAlignment() : 0; 3342 unsigned UseAlign = UseMI->hasOneMemOperand() 3343 ? (*UseMI->memoperands_begin())->getAlignment() : 0; 3344 3345 // Get the itinerary's latency if possible, and handle variable_ops. 3346 int Latency = getOperandLatency(ItinData, *DefMCID, DefIdx, DefAlign, 3347 *UseMCID, UseIdx, UseAlign); 3348 // Unable to find operand latency. The caller may resort to getInstrLatency. 3349 if (Latency < 0) 3350 return Latency; 3351 3352 // Adjust for IT block position. 3353 int Adj = DefAdj + UseAdj; 3354 3355 // Adjust for dynamic def-side opcode variants not captured by the itinerary. 3356 Adj += adjustDefLatency(Subtarget, DefMI, DefMCID, DefAlign); 3357 if (Adj >= 0 || (int)Latency > -Adj) { 3358 return Latency + Adj; 3359 } 3360 // Return the itinerary latency, which may be zero but not less than zero. 3361 return Latency; 3362} 3363 3364int 3365ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData, 3366 SDNode *DefNode, unsigned DefIdx, 3367 SDNode *UseNode, unsigned UseIdx) const { 3368 if (!DefNode->isMachineOpcode()) 3369 return 1; 3370 3371 const MCInstrDesc &DefMCID = get(DefNode->getMachineOpcode()); 3372 3373 if (isZeroCost(DefMCID.Opcode)) 3374 return 0; 3375 3376 if (!ItinData || ItinData->isEmpty()) 3377 return DefMCID.mayLoad() ? 3 : 1; 3378 3379 if (!UseNode->isMachineOpcode()) { 3380 int Latency = ItinData->getOperandCycle(DefMCID.getSchedClass(), DefIdx); 3381 if (Subtarget.isLikeA9() || Subtarget.isSwift()) 3382 return Latency <= 2 ? 1 : Latency - 1; 3383 else 3384 return Latency <= 3 ? 1 : Latency - 2; 3385 } 3386 3387 const MCInstrDesc &UseMCID = get(UseNode->getMachineOpcode()); 3388 const MachineSDNode *DefMN = dyn_cast<MachineSDNode>(DefNode); 3389 unsigned DefAlign = !DefMN->memoperands_empty() 3390 ? (*DefMN->memoperands_begin())->getAlignment() : 0; 3391 const MachineSDNode *UseMN = dyn_cast<MachineSDNode>(UseNode); 3392 unsigned UseAlign = !UseMN->memoperands_empty() 3393 ? (*UseMN->memoperands_begin())->getAlignment() : 0; 3394 int Latency = getOperandLatency(ItinData, DefMCID, DefIdx, DefAlign, 3395 UseMCID, UseIdx, UseAlign); 3396 3397 if (Latency > 1 && 3398 (Subtarget.isCortexA8() || Subtarget.isLikeA9())) { 3399 // FIXME: Shifter op hack: no shift (i.e. [r +/- r]) or [r + r << 2] 3400 // variants are one cycle cheaper. 3401 switch (DefMCID.getOpcode()) { 3402 default: break; 3403 case ARM::LDRrs: 3404 case ARM::LDRBrs: { 3405 unsigned ShOpVal = 3406 cast<ConstantSDNode>(DefNode->getOperand(2))->getZExtValue(); 3407 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal); 3408 if (ShImm == 0 || 3409 (ShImm == 2 && ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl)) 3410 --Latency; 3411 break; 3412 } 3413 case ARM::t2LDRs: 3414 case ARM::t2LDRBs: 3415 case ARM::t2LDRHs: 3416 case ARM::t2LDRSHs: { 3417 // Thumb2 mode: lsl only. 3418 unsigned ShAmt = 3419 cast<ConstantSDNode>(DefNode->getOperand(2))->getZExtValue(); 3420 if (ShAmt == 0 || ShAmt == 2) 3421 --Latency; 3422 break; 3423 } 3424 } 3425 } else if (DefIdx == 0 && Latency > 2 && Subtarget.isSwift()) { 3426 // FIXME: Properly handle all of the latency adjustments for address 3427 // writeback. 3428 switch (DefMCID.getOpcode()) { 3429 default: break; 3430 case ARM::LDRrs: 3431 case ARM::LDRBrs: { 3432 unsigned ShOpVal = 3433 cast<ConstantSDNode>(DefNode->getOperand(2))->getZExtValue(); 3434 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal); 3435 if (ShImm == 0 || 3436 ((ShImm == 1 || ShImm == 2 || ShImm == 3) && 3437 ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl)) 3438 Latency -= 2; 3439 else if (ShImm == 1 && ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsr) 3440 --Latency; 3441 break; 3442 } 3443 case ARM::t2LDRs: 3444 case ARM::t2LDRBs: 3445 case ARM::t2LDRHs: 3446 case ARM::t2LDRSHs: { 3447 // Thumb2 mode: lsl 0-3 only. 3448 Latency -= 2; 3449 break; 3450 } 3451 } 3452 } 3453 3454 if (DefAlign < 8 && Subtarget.isLikeA9()) 3455 switch (DefMCID.getOpcode()) { 3456 default: break; 3457 case ARM::VLD1q8: 3458 case ARM::VLD1q16: 3459 case ARM::VLD1q32: 3460 case ARM::VLD1q64: 3461 case ARM::VLD1q8wb_register: 3462 case ARM::VLD1q16wb_register: 3463 case ARM::VLD1q32wb_register: 3464 case ARM::VLD1q64wb_register: 3465 case ARM::VLD1q8wb_fixed: 3466 case ARM::VLD1q16wb_fixed: 3467 case ARM::VLD1q32wb_fixed: 3468 case ARM::VLD1q64wb_fixed: 3469 case ARM::VLD2d8: 3470 case ARM::VLD2d16: 3471 case ARM::VLD2d32: 3472 case ARM::VLD2q8Pseudo: 3473 case ARM::VLD2q16Pseudo: 3474 case ARM::VLD2q32Pseudo: 3475 case ARM::VLD2d8wb_fixed: 3476 case ARM::VLD2d16wb_fixed: 3477 case ARM::VLD2d32wb_fixed: 3478 case ARM::VLD2q8PseudoWB_fixed: 3479 case ARM::VLD2q16PseudoWB_fixed: 3480 case ARM::VLD2q32PseudoWB_fixed: 3481 case ARM::VLD2d8wb_register: 3482 case ARM::VLD2d16wb_register: 3483 case ARM::VLD2d32wb_register: 3484 case ARM::VLD2q8PseudoWB_register: 3485 case ARM::VLD2q16PseudoWB_register: 3486 case ARM::VLD2q32PseudoWB_register: 3487 case ARM::VLD3d8Pseudo: 3488 case ARM::VLD3d16Pseudo: 3489 case ARM::VLD3d32Pseudo: 3490 case ARM::VLD1d64TPseudo: 3491 case ARM::VLD3d8Pseudo_UPD: 3492 case ARM::VLD3d16Pseudo_UPD: 3493 case ARM::VLD3d32Pseudo_UPD: 3494 case ARM::VLD3q8Pseudo_UPD: 3495 case ARM::VLD3q16Pseudo_UPD: 3496 case ARM::VLD3q32Pseudo_UPD: 3497 case ARM::VLD3q8oddPseudo: 3498 case ARM::VLD3q16oddPseudo: 3499 case ARM::VLD3q32oddPseudo: 3500 case ARM::VLD3q8oddPseudo_UPD: 3501 case ARM::VLD3q16oddPseudo_UPD: 3502 case ARM::VLD3q32oddPseudo_UPD: 3503 case ARM::VLD4d8Pseudo: 3504 case ARM::VLD4d16Pseudo: 3505 case ARM::VLD4d32Pseudo: 3506 case ARM::VLD1d64QPseudo: 3507 case ARM::VLD4d8Pseudo_UPD: 3508 case ARM::VLD4d16Pseudo_UPD: 3509 case ARM::VLD4d32Pseudo_UPD: 3510 case ARM::VLD4q8Pseudo_UPD: 3511 case ARM::VLD4q16Pseudo_UPD: 3512 case ARM::VLD4q32Pseudo_UPD: 3513 case ARM::VLD4q8oddPseudo: 3514 case ARM::VLD4q16oddPseudo: 3515 case ARM::VLD4q32oddPseudo: 3516 case ARM::VLD4q8oddPseudo_UPD: 3517 case ARM::VLD4q16oddPseudo_UPD: 3518 case ARM::VLD4q32oddPseudo_UPD: 3519 case ARM::VLD1DUPq8: 3520 case ARM::VLD1DUPq16: 3521 case ARM::VLD1DUPq32: 3522 case ARM::VLD1DUPq8wb_fixed: 3523 case ARM::VLD1DUPq16wb_fixed: 3524 case ARM::VLD1DUPq32wb_fixed: 3525 case ARM::VLD1DUPq8wb_register: 3526 case ARM::VLD1DUPq16wb_register: 3527 case ARM::VLD1DUPq32wb_register: 3528 case ARM::VLD2DUPd8: 3529 case ARM::VLD2DUPd16: 3530 case ARM::VLD2DUPd32: 3531 case ARM::VLD2DUPd8wb_fixed: 3532 case ARM::VLD2DUPd16wb_fixed: 3533 case ARM::VLD2DUPd32wb_fixed: 3534 case ARM::VLD2DUPd8wb_register: 3535 case ARM::VLD2DUPd16wb_register: 3536 case ARM::VLD2DUPd32wb_register: 3537 case ARM::VLD4DUPd8Pseudo: 3538 case ARM::VLD4DUPd16Pseudo: 3539 case ARM::VLD4DUPd32Pseudo: 3540 case ARM::VLD4DUPd8Pseudo_UPD: 3541 case ARM::VLD4DUPd16Pseudo_UPD: 3542 case ARM::VLD4DUPd32Pseudo_UPD: 3543 case ARM::VLD1LNq8Pseudo: 3544 case ARM::VLD1LNq16Pseudo: 3545 case ARM::VLD1LNq32Pseudo: 3546 case ARM::VLD1LNq8Pseudo_UPD: 3547 case ARM::VLD1LNq16Pseudo_UPD: 3548 case ARM::VLD1LNq32Pseudo_UPD: 3549 case ARM::VLD2LNd8Pseudo: 3550 case ARM::VLD2LNd16Pseudo: 3551 case ARM::VLD2LNd32Pseudo: 3552 case ARM::VLD2LNq16Pseudo: 3553 case ARM::VLD2LNq32Pseudo: 3554 case ARM::VLD2LNd8Pseudo_UPD: 3555 case ARM::VLD2LNd16Pseudo_UPD: 3556 case ARM::VLD2LNd32Pseudo_UPD: 3557 case ARM::VLD2LNq16Pseudo_UPD: 3558 case ARM::VLD2LNq32Pseudo_UPD: 3559 case ARM::VLD4LNd8Pseudo: 3560 case ARM::VLD4LNd16Pseudo: 3561 case ARM::VLD4LNd32Pseudo: 3562 case ARM::VLD4LNq16Pseudo: 3563 case ARM::VLD4LNq32Pseudo: 3564 case ARM::VLD4LNd8Pseudo_UPD: 3565 case ARM::VLD4LNd16Pseudo_UPD: 3566 case ARM::VLD4LNd32Pseudo_UPD: 3567 case ARM::VLD4LNq16Pseudo_UPD: 3568 case ARM::VLD4LNq32Pseudo_UPD: 3569 // If the address is not 64-bit aligned, the latencies of these 3570 // instructions increases by one. 3571 ++Latency; 3572 break; 3573 } 3574 3575 return Latency; 3576} 3577 3578unsigned ARMBaseInstrInfo::getInstrLatency(const InstrItineraryData *ItinData, 3579 const MachineInstr *MI, 3580 unsigned *PredCost) const { 3581 if (MI->isCopyLike() || MI->isInsertSubreg() || 3582 MI->isRegSequence() || MI->isImplicitDef()) 3583 return 1; 3584 3585 // An instruction scheduler typically runs on unbundled instructions, however 3586 // other passes may query the latency of a bundled instruction. 3587 if (MI->isBundle()) { 3588 unsigned Latency = 0; 3589 MachineBasicBlock::const_instr_iterator I = MI; 3590 MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end(); 3591 while (++I != E && I->isInsideBundle()) { 3592 if (I->getOpcode() != ARM::t2IT) 3593 Latency += getInstrLatency(ItinData, I, PredCost); 3594 } 3595 return Latency; 3596 } 3597 3598 const MCInstrDesc &MCID = MI->getDesc(); 3599 if (PredCost && (MCID.isCall() || MCID.hasImplicitDefOfPhysReg(ARM::CPSR))) { 3600 // When predicated, CPSR is an additional source operand for CPSR updating 3601 // instructions, this apparently increases their latencies. 3602 *PredCost = 1; 3603 } 3604 // Be sure to call getStageLatency for an empty itinerary in case it has a 3605 // valid MinLatency property. 3606 if (!ItinData) 3607 return MI->mayLoad() ? 3 : 1; 3608 3609 unsigned Class = MCID.getSchedClass(); 3610 3611 // For instructions with variable uops, use uops as latency. 3612 if (!ItinData->isEmpty() && ItinData->getNumMicroOps(Class) < 0) 3613 return getNumMicroOps(ItinData, MI); 3614 3615 // For the common case, fall back on the itinerary's latency. 3616 unsigned Latency = ItinData->getStageLatency(Class); 3617 3618 // Adjust for dynamic def-side opcode variants not captured by the itinerary. 3619 unsigned DefAlign = MI->hasOneMemOperand() 3620 ? (*MI->memoperands_begin())->getAlignment() : 0; 3621 int Adj = adjustDefLatency(Subtarget, MI, &MCID, DefAlign); 3622 if (Adj >= 0 || (int)Latency > -Adj) { 3623 return Latency + Adj; 3624 } 3625 return Latency; 3626} 3627 3628int ARMBaseInstrInfo::getInstrLatency(const InstrItineraryData *ItinData, 3629 SDNode *Node) const { 3630 if (!Node->isMachineOpcode()) 3631 return 1; 3632 3633 if (!ItinData || ItinData->isEmpty()) 3634 return 1; 3635 3636 unsigned Opcode = Node->getMachineOpcode(); 3637 switch (Opcode) { 3638 default: 3639 return ItinData->getStageLatency(get(Opcode).getSchedClass()); 3640 case ARM::VLDMQIA: 3641 case ARM::VSTMQIA: 3642 return 2; 3643 } 3644} 3645 3646bool ARMBaseInstrInfo:: 3647hasHighOperandLatency(const InstrItineraryData *ItinData, 3648 const MachineRegisterInfo *MRI, 3649 const MachineInstr *DefMI, unsigned DefIdx, 3650 const MachineInstr *UseMI, unsigned UseIdx) const { 3651 unsigned DDomain = DefMI->getDesc().TSFlags & ARMII::DomainMask; 3652 unsigned UDomain = UseMI->getDesc().TSFlags & ARMII::DomainMask; 3653 if (Subtarget.isCortexA8() && 3654 (DDomain == ARMII::DomainVFP || UDomain == ARMII::DomainVFP)) 3655 // CortexA8 VFP instructions are not pipelined. 3656 return true; 3657 3658 // Hoist VFP / NEON instructions with 4 or higher latency. 3659 int Latency = computeOperandLatency(ItinData, DefMI, DefIdx, UseMI, UseIdx, 3660 /*FindMin=*/false); 3661 if (Latency < 0) 3662 Latency = getInstrLatency(ItinData, DefMI); 3663 if (Latency <= 3) 3664 return false; 3665 return DDomain == ARMII::DomainVFP || DDomain == ARMII::DomainNEON || 3666 UDomain == ARMII::DomainVFP || UDomain == ARMII::DomainNEON; 3667} 3668 3669bool ARMBaseInstrInfo:: 3670hasLowDefLatency(const InstrItineraryData *ItinData, 3671 const MachineInstr *DefMI, unsigned DefIdx) const { 3672 if (!ItinData || ItinData->isEmpty()) 3673 return false; 3674 3675 unsigned DDomain = DefMI->getDesc().TSFlags & ARMII::DomainMask; 3676 if (DDomain == ARMII::DomainGeneral) { 3677 unsigned DefClass = DefMI->getDesc().getSchedClass(); 3678 int DefCycle = ItinData->getOperandCycle(DefClass, DefIdx); 3679 return (DefCycle != -1 && DefCycle <= 2); 3680 } 3681 return false; 3682} 3683 3684bool ARMBaseInstrInfo::verifyInstruction(const MachineInstr *MI, 3685 StringRef &ErrInfo) const { 3686 if (convertAddSubFlagsOpcode(MI->getOpcode())) { 3687 ErrInfo = "Pseudo flag setting opcodes only exist in Selection DAG"; 3688 return false; 3689 } 3690 return true; 3691} 3692 3693bool 3694ARMBaseInstrInfo::isFpMLxInstruction(unsigned Opcode, unsigned &MulOpc, 3695 unsigned &AddSubOpc, 3696 bool &NegAcc, bool &HasLane) const { 3697 DenseMap<unsigned, unsigned>::const_iterator I = MLxEntryMap.find(Opcode); 3698 if (I == MLxEntryMap.end()) 3699 return false; 3700 3701 const ARM_MLxEntry &Entry = ARM_MLxTable[I->second]; 3702 MulOpc = Entry.MulOpc; 3703 AddSubOpc = Entry.AddSubOpc; 3704 NegAcc = Entry.NegAcc; 3705 HasLane = Entry.HasLane; 3706 return true; 3707} 3708 3709//===----------------------------------------------------------------------===// 3710// Execution domains. 3711//===----------------------------------------------------------------------===// 3712// 3713// Some instructions go down the NEON pipeline, some go down the VFP pipeline, 3714// and some can go down both. The vmov instructions go down the VFP pipeline, 3715// but they can be changed to vorr equivalents that are executed by the NEON 3716// pipeline. 3717// 3718// We use the following execution domain numbering: 3719// 3720enum ARMExeDomain { 3721 ExeGeneric = 0, 3722 ExeVFP = 1, 3723 ExeNEON = 2 3724}; 3725// 3726// Also see ARMInstrFormats.td and Domain* enums in ARMBaseInfo.h 3727// 3728std::pair<uint16_t, uint16_t> 3729ARMBaseInstrInfo::getExecutionDomain(const MachineInstr *MI) const { 3730 // VMOVD, VMOVRS and VMOVSR are VFP instructions, but can be changed to NEON 3731 // if they are not predicated. 3732 if (MI->getOpcode() == ARM::VMOVD && !isPredicated(MI)) 3733 return std::make_pair(ExeVFP, (1<<ExeVFP) | (1<<ExeNEON)); 3734 3735 // A9-like cores are particularly picky about mixing the two and want these 3736 // converted. 3737 if (Subtarget.isLikeA9() && !isPredicated(MI) && 3738 (MI->getOpcode() == ARM::VMOVRS || 3739 MI->getOpcode() == ARM::VMOVSR || 3740 MI->getOpcode() == ARM::VMOVS)) 3741 return std::make_pair(ExeVFP, (1<<ExeVFP) | (1<<ExeNEON)); 3742 3743 // No other instructions can be swizzled, so just determine their domain. 3744 unsigned Domain = MI->getDesc().TSFlags & ARMII::DomainMask; 3745 3746 if (Domain & ARMII::DomainNEON) 3747 return std::make_pair(ExeNEON, 0); 3748 3749 // Certain instructions can go either way on Cortex-A8. 3750 // Treat them as NEON instructions. 3751 if ((Domain & ARMII::DomainNEONA8) && Subtarget.isCortexA8()) 3752 return std::make_pair(ExeNEON, 0); 3753 3754 if (Domain & ARMII::DomainVFP) 3755 return std::make_pair(ExeVFP, 0); 3756 3757 return std::make_pair(ExeGeneric, 0); 3758} 3759 3760static unsigned getCorrespondingDRegAndLane(const TargetRegisterInfo *TRI, 3761 unsigned SReg, unsigned &Lane) { 3762 unsigned DReg = TRI->getMatchingSuperReg(SReg, ARM::ssub_0, &ARM::DPRRegClass); 3763 Lane = 0; 3764 3765 if (DReg != ARM::NoRegister) 3766 return DReg; 3767 3768 Lane = 1; 3769 DReg = TRI->getMatchingSuperReg(SReg, ARM::ssub_1, &ARM::DPRRegClass); 3770 3771 assert(DReg && "S-register with no D super-register?"); 3772 return DReg; 3773} 3774 3775/// getImplicitSPRUseForDPRUse - Given a use of a DPR register and lane, 3776/// set ImplicitSReg to a register number that must be marked as implicit-use or 3777/// zero if no register needs to be defined as implicit-use. 3778/// 3779/// If the function cannot determine if an SPR should be marked implicit use or 3780/// not, it returns false. 3781/// 3782/// This function handles cases where an instruction is being modified from taking 3783/// an SPR to a DPR[Lane]. A use of the DPR is being added, which may conflict 3784/// with an earlier def of an SPR corresponding to DPR[Lane^1] (i.e. the other 3785/// lane of the DPR). 3786/// 3787/// If the other SPR is defined, an implicit-use of it should be added. Else, 3788/// (including the case where the DPR itself is defined), it should not. 3789/// 3790static bool getImplicitSPRUseForDPRUse(const TargetRegisterInfo *TRI, 3791 MachineInstr *MI, 3792 unsigned DReg, unsigned Lane, 3793 unsigned &ImplicitSReg) { 3794 // If the DPR is defined or used already, the other SPR lane will be chained 3795 // correctly, so there is nothing to be done. 3796 if (MI->definesRegister(DReg, TRI) || MI->readsRegister(DReg, TRI)) { 3797 ImplicitSReg = 0; 3798 return true; 3799 } 3800 3801 // Otherwise we need to go searching to see if the SPR is set explicitly. 3802 ImplicitSReg = TRI->getSubReg(DReg, 3803 (Lane & 1) ? ARM::ssub_0 : ARM::ssub_1); 3804 MachineBasicBlock::LivenessQueryResult LQR = 3805 MI->getParent()->computeRegisterLiveness(TRI, ImplicitSReg, MI); 3806 3807 if (LQR == MachineBasicBlock::LQR_Live) 3808 return true; 3809 else if (LQR == MachineBasicBlock::LQR_Unknown) 3810 return false; 3811 3812 // If the register is known not to be live, there is no need to add an 3813 // implicit-use. 3814 ImplicitSReg = 0; 3815 return true; 3816} 3817 3818void 3819ARMBaseInstrInfo::setExecutionDomain(MachineInstr *MI, unsigned Domain) const { 3820 unsigned DstReg, SrcReg, DReg; 3821 unsigned Lane; 3822 MachineInstrBuilder MIB(MI); 3823 const TargetRegisterInfo *TRI = &getRegisterInfo(); 3824 switch (MI->getOpcode()) { 3825 default: 3826 llvm_unreachable("cannot handle opcode!"); 3827 break; 3828 case ARM::VMOVD: 3829 if (Domain != ExeNEON) 3830 break; 3831 3832 // Zap the predicate operands. 3833 assert(!isPredicated(MI) && "Cannot predicate a VORRd"); 3834 3835 // Source instruction is %DDst = VMOVD %DSrc, 14, %noreg (; implicits) 3836 DstReg = MI->getOperand(0).getReg(); 3837 SrcReg = MI->getOperand(1).getReg(); 3838 3839 for (unsigned i = MI->getDesc().getNumOperands(); i; --i) 3840 MI->RemoveOperand(i-1); 3841 3842 // Change to a %DDst = VORRd %DSrc, %DSrc, 14, %noreg (; implicits) 3843 MI->setDesc(get(ARM::VORRd)); 3844 AddDefaultPred(MIB.addReg(DstReg, RegState::Define) 3845 .addReg(SrcReg) 3846 .addReg(SrcReg)); 3847 break; 3848 case ARM::VMOVRS: 3849 if (Domain != ExeNEON) 3850 break; 3851 assert(!isPredicated(MI) && "Cannot predicate a VGETLN"); 3852 3853 // Source instruction is %RDst = VMOVRS %SSrc, 14, %noreg (; implicits) 3854 DstReg = MI->getOperand(0).getReg(); 3855 SrcReg = MI->getOperand(1).getReg(); 3856 3857 for (unsigned i = MI->getDesc().getNumOperands(); i; --i) 3858 MI->RemoveOperand(i-1); 3859 3860 DReg = getCorrespondingDRegAndLane(TRI, SrcReg, Lane); 3861 3862 // Convert to %RDst = VGETLNi32 %DSrc, Lane, 14, %noreg (; imps) 3863 // Note that DSrc has been widened and the other lane may be undef, which 3864 // contaminates the entire register. 3865 MI->setDesc(get(ARM::VGETLNi32)); 3866 AddDefaultPred(MIB.addReg(DstReg, RegState::Define) 3867 .addReg(DReg, RegState::Undef) 3868 .addImm(Lane)); 3869 3870 // The old source should be an implicit use, otherwise we might think it 3871 // was dead before here. 3872 MIB.addReg(SrcReg, RegState::Implicit); 3873 break; 3874 case ARM::VMOVSR: { 3875 if (Domain != ExeNEON) 3876 break; 3877 assert(!isPredicated(MI) && "Cannot predicate a VSETLN"); 3878 3879 // Source instruction is %SDst = VMOVSR %RSrc, 14, %noreg (; implicits) 3880 DstReg = MI->getOperand(0).getReg(); 3881 SrcReg = MI->getOperand(1).getReg(); 3882 3883 DReg = getCorrespondingDRegAndLane(TRI, DstReg, Lane); 3884 3885 unsigned ImplicitSReg; 3886 if (!getImplicitSPRUseForDPRUse(TRI, MI, DReg, Lane, ImplicitSReg)) 3887 break; 3888 3889 for (unsigned i = MI->getDesc().getNumOperands(); i; --i) 3890 MI->RemoveOperand(i-1); 3891 3892 // Convert to %DDst = VSETLNi32 %DDst, %RSrc, Lane, 14, %noreg (; imps) 3893 // Again DDst may be undefined at the beginning of this instruction. 3894 MI->setDesc(get(ARM::VSETLNi32)); 3895 MIB.addReg(DReg, RegState::Define) 3896 .addReg(DReg, getUndefRegState(!MI->readsRegister(DReg, TRI))) 3897 .addReg(SrcReg) 3898 .addImm(Lane); 3899 AddDefaultPred(MIB); 3900 3901 // The narrower destination must be marked as set to keep previous chains 3902 // in place. 3903 MIB.addReg(DstReg, RegState::Define | RegState::Implicit); 3904 if (ImplicitSReg != 0) 3905 MIB.addReg(ImplicitSReg, RegState::Implicit); 3906 break; 3907 } 3908 case ARM::VMOVS: { 3909 if (Domain != ExeNEON) 3910 break; 3911 3912 // Source instruction is %SDst = VMOVS %SSrc, 14, %noreg (; implicits) 3913 DstReg = MI->getOperand(0).getReg(); 3914 SrcReg = MI->getOperand(1).getReg(); 3915 3916 unsigned DstLane = 0, SrcLane = 0, DDst, DSrc; 3917 DDst = getCorrespondingDRegAndLane(TRI, DstReg, DstLane); 3918 DSrc = getCorrespondingDRegAndLane(TRI, SrcReg, SrcLane); 3919 3920 unsigned ImplicitSReg; 3921 if (!getImplicitSPRUseForDPRUse(TRI, MI, DSrc, SrcLane, ImplicitSReg)) 3922 break; 3923 3924 for (unsigned i = MI->getDesc().getNumOperands(); i; --i) 3925 MI->RemoveOperand(i-1); 3926 3927 if (DSrc == DDst) { 3928 // Destination can be: 3929 // %DDst = VDUPLN32d %DDst, Lane, 14, %noreg (; implicits) 3930 MI->setDesc(get(ARM::VDUPLN32d)); 3931 MIB.addReg(DDst, RegState::Define) 3932 .addReg(DDst, getUndefRegState(!MI->readsRegister(DDst, TRI))) 3933 .addImm(SrcLane); 3934 AddDefaultPred(MIB); 3935 3936 // Neither the source or the destination are naturally represented any 3937 // more, so add them in manually. 3938 MIB.addReg(DstReg, RegState::Implicit | RegState::Define); 3939 MIB.addReg(SrcReg, RegState::Implicit); 3940 if (ImplicitSReg != 0) 3941 MIB.addReg(ImplicitSReg, RegState::Implicit); 3942 break; 3943 } 3944 3945 // In general there's no single instruction that can perform an S <-> S 3946 // move in NEON space, but a pair of VEXT instructions *can* do the 3947 // job. It turns out that the VEXTs needed will only use DSrc once, with 3948 // the position based purely on the combination of lane-0 and lane-1 3949 // involved. For example 3950 // vmov s0, s2 -> vext.32 d0, d0, d1, #1 vext.32 d0, d0, d0, #1 3951 // vmov s1, s3 -> vext.32 d0, d1, d0, #1 vext.32 d0, d0, d0, #1 3952 // vmov s0, s3 -> vext.32 d0, d0, d0, #1 vext.32 d0, d1, d0, #1 3953 // vmov s1, s2 -> vext.32 d0, d0, d0, #1 vext.32 d0, d0, d1, #1 3954 // 3955 // Pattern of the MachineInstrs is: 3956 // %DDst = VEXTd32 %DSrc1, %DSrc2, Lane, 14, %noreg (;implicits) 3957 MachineInstrBuilder NewMIB; 3958 NewMIB = BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), 3959 get(ARM::VEXTd32), DDst); 3960 3961 // On the first instruction, both DSrc and DDst may be <undef> if present. 3962 // Specifically when the original instruction didn't have them as an 3963 // <imp-use>. 3964 unsigned CurReg = SrcLane == 1 && DstLane == 1 ? DSrc : DDst; 3965 bool CurUndef = !MI->readsRegister(CurReg, TRI); 3966 NewMIB.addReg(CurReg, getUndefRegState(CurUndef)); 3967 3968 CurReg = SrcLane == 0 && DstLane == 0 ? DSrc : DDst; 3969 CurUndef = !MI->readsRegister(CurReg, TRI); 3970 NewMIB.addReg(CurReg, getUndefRegState(CurUndef)); 3971 3972 NewMIB.addImm(1); 3973 AddDefaultPred(NewMIB); 3974 3975 if (SrcLane == DstLane) 3976 NewMIB.addReg(SrcReg, RegState::Implicit); 3977 3978 MI->setDesc(get(ARM::VEXTd32)); 3979 MIB.addReg(DDst, RegState::Define); 3980 3981 // On the second instruction, DDst has definitely been defined above, so 3982 // it is not <undef>. DSrc, if present, can be <undef> as above. 3983 CurReg = SrcLane == 1 && DstLane == 0 ? DSrc : DDst; 3984 CurUndef = CurReg == DSrc && !MI->readsRegister(CurReg, TRI); 3985 MIB.addReg(CurReg, getUndefRegState(CurUndef)); 3986 3987 CurReg = SrcLane == 0 && DstLane == 1 ? DSrc : DDst; 3988 CurUndef = CurReg == DSrc && !MI->readsRegister(CurReg, TRI); 3989 MIB.addReg(CurReg, getUndefRegState(CurUndef)); 3990 3991 MIB.addImm(1); 3992 AddDefaultPred(MIB); 3993 3994 if (SrcLane != DstLane) 3995 MIB.addReg(SrcReg, RegState::Implicit); 3996 3997 // As before, the original destination is no longer represented, add it 3998 // implicitly. 3999 MIB.addReg(DstReg, RegState::Define | RegState::Implicit); 4000 if (ImplicitSReg != 0) 4001 MIB.addReg(ImplicitSReg, RegState::Implicit); 4002 break; 4003 } 4004 } 4005 4006} 4007 4008//===----------------------------------------------------------------------===// 4009// Partial register updates 4010//===----------------------------------------------------------------------===// 4011// 4012// Swift renames NEON registers with 64-bit granularity. That means any 4013// instruction writing an S-reg implicitly reads the containing D-reg. The 4014// problem is mostly avoided by translating f32 operations to v2f32 operations 4015// on D-registers, but f32 loads are still a problem. 4016// 4017// These instructions can load an f32 into a NEON register: 4018// 4019// VLDRS - Only writes S, partial D update. 4020// VLD1LNd32 - Writes all D-regs, explicit partial D update, 2 uops. 4021// VLD1DUPd32 - Writes all D-regs, no partial reg update, 2 uops. 4022// 4023// FCONSTD can be used as a dependency-breaking instruction. 4024 4025 4026unsigned ARMBaseInstrInfo:: 4027getPartialRegUpdateClearance(const MachineInstr *MI, 4028 unsigned OpNum, 4029 const TargetRegisterInfo *TRI) const { 4030 // Only Swift has partial register update problems. 4031 if (!SwiftPartialUpdateClearance || !Subtarget.isSwift()) 4032 return 0; 4033 4034 assert(TRI && "Need TRI instance"); 4035 4036 const MachineOperand &MO = MI->getOperand(OpNum); 4037 if (MO.readsReg()) 4038 return 0; 4039 unsigned Reg = MO.getReg(); 4040 int UseOp = -1; 4041 4042 switch(MI->getOpcode()) { 4043 // Normal instructions writing only an S-register. 4044 case ARM::VLDRS: 4045 case ARM::FCONSTS: 4046 case ARM::VMOVSR: 4047 // rdar://problem/8791586 4048 case ARM::VMOVv8i8: 4049 case ARM::VMOVv4i16: 4050 case ARM::VMOVv2i32: 4051 case ARM::VMOVv2f32: 4052 case ARM::VMOVv1i64: 4053 UseOp = MI->findRegisterUseOperandIdx(Reg, false, TRI); 4054 break; 4055 4056 // Explicitly reads the dependency. 4057 case ARM::VLD1LNd32: 4058 UseOp = 1; 4059 break; 4060 default: 4061 return 0; 4062 } 4063 4064 // If this instruction actually reads a value from Reg, there is no unwanted 4065 // dependency. 4066 if (UseOp != -1 && MI->getOperand(UseOp).readsReg()) 4067 return 0; 4068 4069 // We must be able to clobber the whole D-reg. 4070 if (TargetRegisterInfo::isVirtualRegister(Reg)) { 4071 // Virtual register must be a foo:ssub_0<def,undef> operand. 4072 if (!MO.getSubReg() || MI->readsVirtualRegister(Reg)) 4073 return 0; 4074 } else if (ARM::SPRRegClass.contains(Reg)) { 4075 // Physical register: MI must define the full D-reg. 4076 unsigned DReg = TRI->getMatchingSuperReg(Reg, ARM::ssub_0, 4077 &ARM::DPRRegClass); 4078 if (!DReg || !MI->definesRegister(DReg, TRI)) 4079 return 0; 4080 } 4081 4082 // MI has an unwanted D-register dependency. 4083 // Avoid defs in the previous N instructrions. 4084 return SwiftPartialUpdateClearance; 4085} 4086 4087// Break a partial register dependency after getPartialRegUpdateClearance 4088// returned non-zero. 4089void ARMBaseInstrInfo:: 4090breakPartialRegDependency(MachineBasicBlock::iterator MI, 4091 unsigned OpNum, 4092 const TargetRegisterInfo *TRI) const { 4093 assert(MI && OpNum < MI->getDesc().getNumDefs() && "OpNum is not a def"); 4094 assert(TRI && "Need TRI instance"); 4095 4096 const MachineOperand &MO = MI->getOperand(OpNum); 4097 unsigned Reg = MO.getReg(); 4098 assert(TargetRegisterInfo::isPhysicalRegister(Reg) && 4099 "Can't break virtual register dependencies."); 4100 unsigned DReg = Reg; 4101 4102 // If MI defines an S-reg, find the corresponding D super-register. 4103 if (ARM::SPRRegClass.contains(Reg)) { 4104 DReg = ARM::D0 + (Reg - ARM::S0) / 2; 4105 assert(TRI->isSuperRegister(Reg, DReg) && "Register enums broken"); 4106 } 4107 4108 assert(ARM::DPRRegClass.contains(DReg) && "Can only break D-reg deps"); 4109 assert(MI->definesRegister(DReg, TRI) && "MI doesn't clobber full D-reg"); 4110 4111 // FIXME: In some cases, VLDRS can be changed to a VLD1DUPd32 which defines 4112 // the full D-register by loading the same value to both lanes. The 4113 // instruction is micro-coded with 2 uops, so don't do this until we can 4114 // properly schedule micro-coded instuctions. The dispatcher stalls cause 4115 // too big regressions. 4116 4117 // Insert the dependency-breaking FCONSTD before MI. 4118 // 96 is the encoding of 0.5, but the actual value doesn't matter here. 4119 AddDefaultPred(BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), 4120 get(ARM::FCONSTD), DReg).addImm(96)); 4121 MI->addRegisterKilled(DReg, TRI, true); 4122} 4123 4124bool ARMBaseInstrInfo::hasNOP() const { 4125 return (Subtarget.getFeatureBits() & ARM::HasV6T2Ops) != 0; 4126} 4127