ARMBaseInstrInfo.cpp revision b21ab43cfc3fa0dacf5c95f04e58b6d804b59a16
1//===-- ARMBaseInstrInfo.cpp - ARM Instruction Information ----------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the Base ARM implementation of the TargetInstrInfo class. 11// 12//===----------------------------------------------------------------------===// 13 14#include "ARM.h" 15#include "ARMBaseInstrInfo.h" 16#include "ARMBaseRegisterInfo.h" 17#include "ARMConstantPoolValue.h" 18#include "ARMFeatures.h" 19#include "ARMHazardRecognizer.h" 20#include "ARMMachineFunctionInfo.h" 21#include "MCTargetDesc/ARMAddressingModes.h" 22#include "llvm/ADT/STLExtras.h" 23#include "llvm/CodeGen/LiveVariables.h" 24#include "llvm/CodeGen/MachineConstantPool.h" 25#include "llvm/CodeGen/MachineFrameInfo.h" 26#include "llvm/CodeGen/MachineInstrBuilder.h" 27#include "llvm/CodeGen/MachineJumpTableInfo.h" 28#include "llvm/CodeGen/MachineMemOperand.h" 29#include "llvm/CodeGen/MachineRegisterInfo.h" 30#include "llvm/CodeGen/SelectionDAGNodes.h" 31#include "llvm/IR/Constants.h" 32#include "llvm/IR/Function.h" 33#include "llvm/IR/GlobalValue.h" 34#include "llvm/MC/MCAsmInfo.h" 35#include "llvm/Support/BranchProbability.h" 36#include "llvm/Support/CommandLine.h" 37#include "llvm/Support/Debug.h" 38#include "llvm/Support/ErrorHandling.h" 39 40#define GET_INSTRINFO_CTOR 41#include "ARMGenInstrInfo.inc" 42 43using namespace llvm; 44 45static cl::opt<bool> 46EnableARM3Addr("enable-arm-3-addr-conv", cl::Hidden, 47 cl::desc("Enable ARM 2-addr to 3-addr conv")); 48 49static cl::opt<bool> 50WidenVMOVS("widen-vmovs", cl::Hidden, cl::init(true), 51 cl::desc("Widen ARM vmovs to vmovd when possible")); 52 53static cl::opt<unsigned> 54SwiftPartialUpdateClearance("swift-partial-update-clearance", 55 cl::Hidden, cl::init(12), 56 cl::desc("Clearance before partial register updates")); 57 58/// ARM_MLxEntry - Record information about MLA / MLS instructions. 59struct ARM_MLxEntry { 60 uint16_t MLxOpc; // MLA / MLS opcode 61 uint16_t MulOpc; // Expanded multiplication opcode 62 uint16_t AddSubOpc; // Expanded add / sub opcode 63 bool NegAcc; // True if the acc is negated before the add / sub. 64 bool HasLane; // True if instruction has an extra "lane" operand. 65}; 66 67static const ARM_MLxEntry ARM_MLxTable[] = { 68 // MLxOpc, MulOpc, AddSubOpc, NegAcc, HasLane 69 // fp scalar ops 70 { ARM::VMLAS, ARM::VMULS, ARM::VADDS, false, false }, 71 { ARM::VMLSS, ARM::VMULS, ARM::VSUBS, false, false }, 72 { ARM::VMLAD, ARM::VMULD, ARM::VADDD, false, false }, 73 { ARM::VMLSD, ARM::VMULD, ARM::VSUBD, false, false }, 74 { ARM::VNMLAS, ARM::VNMULS, ARM::VSUBS, true, false }, 75 { ARM::VNMLSS, ARM::VMULS, ARM::VSUBS, true, false }, 76 { ARM::VNMLAD, ARM::VNMULD, ARM::VSUBD, true, false }, 77 { ARM::VNMLSD, ARM::VMULD, ARM::VSUBD, true, false }, 78 79 // fp SIMD ops 80 { ARM::VMLAfd, ARM::VMULfd, ARM::VADDfd, false, false }, 81 { ARM::VMLSfd, ARM::VMULfd, ARM::VSUBfd, false, false }, 82 { ARM::VMLAfq, ARM::VMULfq, ARM::VADDfq, false, false }, 83 { ARM::VMLSfq, ARM::VMULfq, ARM::VSUBfq, false, false }, 84 { ARM::VMLAslfd, ARM::VMULslfd, ARM::VADDfd, false, true }, 85 { ARM::VMLSslfd, ARM::VMULslfd, ARM::VSUBfd, false, true }, 86 { ARM::VMLAslfq, ARM::VMULslfq, ARM::VADDfq, false, true }, 87 { ARM::VMLSslfq, ARM::VMULslfq, ARM::VSUBfq, false, true }, 88}; 89 90ARMBaseInstrInfo::ARMBaseInstrInfo(const ARMSubtarget& STI) 91 : ARMGenInstrInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP), 92 Subtarget(STI) { 93 for (unsigned i = 0, e = array_lengthof(ARM_MLxTable); i != e; ++i) { 94 if (!MLxEntryMap.insert(std::make_pair(ARM_MLxTable[i].MLxOpc, i)).second) 95 assert(false && "Duplicated entries?"); 96 MLxHazardOpcodes.insert(ARM_MLxTable[i].AddSubOpc); 97 MLxHazardOpcodes.insert(ARM_MLxTable[i].MulOpc); 98 } 99} 100 101// Use a ScoreboardHazardRecognizer for prepass ARM scheduling. TargetInstrImpl 102// currently defaults to no prepass hazard recognizer. 103ScheduleHazardRecognizer *ARMBaseInstrInfo:: 104CreateTargetHazardRecognizer(const TargetMachine *TM, 105 const ScheduleDAG *DAG) const { 106 if (usePreRAHazardRecognizer()) { 107 const InstrItineraryData *II = TM->getInstrItineraryData(); 108 return new ScoreboardHazardRecognizer(II, DAG, "pre-RA-sched"); 109 } 110 return TargetInstrInfo::CreateTargetHazardRecognizer(TM, DAG); 111} 112 113ScheduleHazardRecognizer *ARMBaseInstrInfo:: 114CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II, 115 const ScheduleDAG *DAG) const { 116 if (Subtarget.isThumb2() || Subtarget.hasVFP2()) 117 return (ScheduleHazardRecognizer *)new ARMHazardRecognizer(II, DAG); 118 return TargetInstrInfo::CreateTargetPostRAHazardRecognizer(II, DAG); 119} 120 121MachineInstr * 122ARMBaseInstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI, 123 MachineBasicBlock::iterator &MBBI, 124 LiveVariables *LV) const { 125 // FIXME: Thumb2 support. 126 127 if (!EnableARM3Addr) 128 return NULL; 129 130 MachineInstr *MI = MBBI; 131 MachineFunction &MF = *MI->getParent()->getParent(); 132 uint64_t TSFlags = MI->getDesc().TSFlags; 133 bool isPre = false; 134 switch ((TSFlags & ARMII::IndexModeMask) >> ARMII::IndexModeShift) { 135 default: return NULL; 136 case ARMII::IndexModePre: 137 isPre = true; 138 break; 139 case ARMII::IndexModePost: 140 break; 141 } 142 143 // Try splitting an indexed load/store to an un-indexed one plus an add/sub 144 // operation. 145 unsigned MemOpc = getUnindexedOpcode(MI->getOpcode()); 146 if (MemOpc == 0) 147 return NULL; 148 149 MachineInstr *UpdateMI = NULL; 150 MachineInstr *MemMI = NULL; 151 unsigned AddrMode = (TSFlags & ARMII::AddrModeMask); 152 const MCInstrDesc &MCID = MI->getDesc(); 153 unsigned NumOps = MCID.getNumOperands(); 154 bool isLoad = !MI->mayStore(); 155 const MachineOperand &WB = isLoad ? MI->getOperand(1) : MI->getOperand(0); 156 const MachineOperand &Base = MI->getOperand(2); 157 const MachineOperand &Offset = MI->getOperand(NumOps-3); 158 unsigned WBReg = WB.getReg(); 159 unsigned BaseReg = Base.getReg(); 160 unsigned OffReg = Offset.getReg(); 161 unsigned OffImm = MI->getOperand(NumOps-2).getImm(); 162 ARMCC::CondCodes Pred = (ARMCC::CondCodes)MI->getOperand(NumOps-1).getImm(); 163 switch (AddrMode) { 164 default: llvm_unreachable("Unknown indexed op!"); 165 case ARMII::AddrMode2: { 166 bool isSub = ARM_AM::getAM2Op(OffImm) == ARM_AM::sub; 167 unsigned Amt = ARM_AM::getAM2Offset(OffImm); 168 if (OffReg == 0) { 169 if (ARM_AM::getSOImmVal(Amt) == -1) 170 // Can't encode it in a so_imm operand. This transformation will 171 // add more than 1 instruction. Abandon! 172 return NULL; 173 UpdateMI = BuildMI(MF, MI->getDebugLoc(), 174 get(isSub ? ARM::SUBri : ARM::ADDri), WBReg) 175 .addReg(BaseReg).addImm(Amt) 176 .addImm(Pred).addReg(0).addReg(0); 177 } else if (Amt != 0) { 178 ARM_AM::ShiftOpc ShOpc = ARM_AM::getAM2ShiftOpc(OffImm); 179 unsigned SOOpc = ARM_AM::getSORegOpc(ShOpc, Amt); 180 UpdateMI = BuildMI(MF, MI->getDebugLoc(), 181 get(isSub ? ARM::SUBrsi : ARM::ADDrsi), WBReg) 182 .addReg(BaseReg).addReg(OffReg).addReg(0).addImm(SOOpc) 183 .addImm(Pred).addReg(0).addReg(0); 184 } else 185 UpdateMI = BuildMI(MF, MI->getDebugLoc(), 186 get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg) 187 .addReg(BaseReg).addReg(OffReg) 188 .addImm(Pred).addReg(0).addReg(0); 189 break; 190 } 191 case ARMII::AddrMode3 : { 192 bool isSub = ARM_AM::getAM3Op(OffImm) == ARM_AM::sub; 193 unsigned Amt = ARM_AM::getAM3Offset(OffImm); 194 if (OffReg == 0) 195 // Immediate is 8-bits. It's guaranteed to fit in a so_imm operand. 196 UpdateMI = BuildMI(MF, MI->getDebugLoc(), 197 get(isSub ? ARM::SUBri : ARM::ADDri), WBReg) 198 .addReg(BaseReg).addImm(Amt) 199 .addImm(Pred).addReg(0).addReg(0); 200 else 201 UpdateMI = BuildMI(MF, MI->getDebugLoc(), 202 get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg) 203 .addReg(BaseReg).addReg(OffReg) 204 .addImm(Pred).addReg(0).addReg(0); 205 break; 206 } 207 } 208 209 std::vector<MachineInstr*> NewMIs; 210 if (isPre) { 211 if (isLoad) 212 MemMI = BuildMI(MF, MI->getDebugLoc(), 213 get(MemOpc), MI->getOperand(0).getReg()) 214 .addReg(WBReg).addImm(0).addImm(Pred); 215 else 216 MemMI = BuildMI(MF, MI->getDebugLoc(), 217 get(MemOpc)).addReg(MI->getOperand(1).getReg()) 218 .addReg(WBReg).addReg(0).addImm(0).addImm(Pred); 219 NewMIs.push_back(MemMI); 220 NewMIs.push_back(UpdateMI); 221 } else { 222 if (isLoad) 223 MemMI = BuildMI(MF, MI->getDebugLoc(), 224 get(MemOpc), MI->getOperand(0).getReg()) 225 .addReg(BaseReg).addImm(0).addImm(Pred); 226 else 227 MemMI = BuildMI(MF, MI->getDebugLoc(), 228 get(MemOpc)).addReg(MI->getOperand(1).getReg()) 229 .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred); 230 if (WB.isDead()) 231 UpdateMI->getOperand(0).setIsDead(); 232 NewMIs.push_back(UpdateMI); 233 NewMIs.push_back(MemMI); 234 } 235 236 // Transfer LiveVariables states, kill / dead info. 237 if (LV) { 238 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 239 MachineOperand &MO = MI->getOperand(i); 240 if (MO.isReg() && TargetRegisterInfo::isVirtualRegister(MO.getReg())) { 241 unsigned Reg = MO.getReg(); 242 243 LiveVariables::VarInfo &VI = LV->getVarInfo(Reg); 244 if (MO.isDef()) { 245 MachineInstr *NewMI = (Reg == WBReg) ? UpdateMI : MemMI; 246 if (MO.isDead()) 247 LV->addVirtualRegisterDead(Reg, NewMI); 248 } 249 if (MO.isUse() && MO.isKill()) { 250 for (unsigned j = 0; j < 2; ++j) { 251 // Look at the two new MI's in reverse order. 252 MachineInstr *NewMI = NewMIs[j]; 253 if (!NewMI->readsRegister(Reg)) 254 continue; 255 LV->addVirtualRegisterKilled(Reg, NewMI); 256 if (VI.removeKill(MI)) 257 VI.Kills.push_back(NewMI); 258 break; 259 } 260 } 261 } 262 } 263 } 264 265 MFI->insert(MBBI, NewMIs[1]); 266 MFI->insert(MBBI, NewMIs[0]); 267 return NewMIs[0]; 268} 269 270// Branch analysis. 271bool 272ARMBaseInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB, 273 MachineBasicBlock *&FBB, 274 SmallVectorImpl<MachineOperand> &Cond, 275 bool AllowModify) const { 276 TBB = 0; 277 FBB = 0; 278 279 MachineBasicBlock::iterator I = MBB.end(); 280 if (I == MBB.begin()) 281 return false; // Empty blocks are easy. 282 --I; 283 284 // Walk backwards from the end of the basic block until the branch is 285 // analyzed or we give up. 286 while (isPredicated(I) || I->isTerminator()) { 287 288 // Flag to be raised on unanalyzeable instructions. This is useful in cases 289 // where we want to clean up on the end of the basic block before we bail 290 // out. 291 bool CantAnalyze = false; 292 293 // Skip over DEBUG values and predicated nonterminators. 294 while (I->isDebugValue() || !I->isTerminator()) { 295 if (I == MBB.begin()) 296 return false; 297 --I; 298 } 299 300 if (isIndirectBranchOpcode(I->getOpcode()) || 301 isJumpTableBranchOpcode(I->getOpcode())) { 302 // Indirect branches and jump tables can't be analyzed, but we still want 303 // to clean up any instructions at the tail of the basic block. 304 CantAnalyze = true; 305 } else if (isUncondBranchOpcode(I->getOpcode())) { 306 TBB = I->getOperand(0).getMBB(); 307 } else if (isCondBranchOpcode(I->getOpcode())) { 308 // Bail out if we encounter multiple conditional branches. 309 if (!Cond.empty()) 310 return true; 311 312 assert(!FBB && "FBB should have been null."); 313 FBB = TBB; 314 TBB = I->getOperand(0).getMBB(); 315 Cond.push_back(I->getOperand(1)); 316 Cond.push_back(I->getOperand(2)); 317 } else if (I->isReturn()) { 318 // Returns can't be analyzed, but we should run cleanup. 319 CantAnalyze = !isPredicated(I); 320 } else { 321 // We encountered other unrecognized terminator. Bail out immediately. 322 return true; 323 } 324 325 // Cleanup code - to be run for unpredicated unconditional branches and 326 // returns. 327 if (!isPredicated(I) && 328 (isUncondBranchOpcode(I->getOpcode()) || 329 isIndirectBranchOpcode(I->getOpcode()) || 330 isJumpTableBranchOpcode(I->getOpcode()) || 331 I->isReturn())) { 332 // Forget any previous condition branch information - it no longer applies. 333 Cond.clear(); 334 FBB = 0; 335 336 // If we can modify the function, delete everything below this 337 // unconditional branch. 338 if (AllowModify) { 339 MachineBasicBlock::iterator DI = llvm::next(I); 340 while (DI != MBB.end()) { 341 MachineInstr *InstToDelete = DI; 342 ++DI; 343 InstToDelete->eraseFromParent(); 344 } 345 } 346 } 347 348 if (CantAnalyze) 349 return true; 350 351 if (I == MBB.begin()) 352 return false; 353 354 --I; 355 } 356 357 // We made it past the terminators without bailing out - we must have 358 // analyzed this branch successfully. 359 return false; 360} 361 362 363unsigned ARMBaseInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const { 364 MachineBasicBlock::iterator I = MBB.end(); 365 if (I == MBB.begin()) return 0; 366 --I; 367 while (I->isDebugValue()) { 368 if (I == MBB.begin()) 369 return 0; 370 --I; 371 } 372 if (!isUncondBranchOpcode(I->getOpcode()) && 373 !isCondBranchOpcode(I->getOpcode())) 374 return 0; 375 376 // Remove the branch. 377 I->eraseFromParent(); 378 379 I = MBB.end(); 380 381 if (I == MBB.begin()) return 1; 382 --I; 383 if (!isCondBranchOpcode(I->getOpcode())) 384 return 1; 385 386 // Remove the branch. 387 I->eraseFromParent(); 388 return 2; 389} 390 391unsigned 392ARMBaseInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 393 MachineBasicBlock *FBB, 394 const SmallVectorImpl<MachineOperand> &Cond, 395 DebugLoc DL) const { 396 ARMFunctionInfo *AFI = MBB.getParent()->getInfo<ARMFunctionInfo>(); 397 int BOpc = !AFI->isThumbFunction() 398 ? ARM::B : (AFI->isThumb2Function() ? ARM::t2B : ARM::tB); 399 int BccOpc = !AFI->isThumbFunction() 400 ? ARM::Bcc : (AFI->isThumb2Function() ? ARM::t2Bcc : ARM::tBcc); 401 bool isThumb = AFI->isThumbFunction() || AFI->isThumb2Function(); 402 403 // Shouldn't be a fall through. 404 assert(TBB && "InsertBranch must not be told to insert a fallthrough"); 405 assert((Cond.size() == 2 || Cond.size() == 0) && 406 "ARM branch conditions have two components!"); 407 408 if (FBB == 0) { 409 if (Cond.empty()) { // Unconditional branch? 410 if (isThumb) 411 BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB).addImm(ARMCC::AL).addReg(0); 412 else 413 BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB); 414 } else 415 BuildMI(&MBB, DL, get(BccOpc)).addMBB(TBB) 416 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()); 417 return 1; 418 } 419 420 // Two-way conditional branch. 421 BuildMI(&MBB, DL, get(BccOpc)).addMBB(TBB) 422 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()); 423 if (isThumb) 424 BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB).addImm(ARMCC::AL).addReg(0); 425 else 426 BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB); 427 return 2; 428} 429 430bool ARMBaseInstrInfo:: 431ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const { 432 ARMCC::CondCodes CC = (ARMCC::CondCodes)(int)Cond[0].getImm(); 433 Cond[0].setImm(ARMCC::getOppositeCondition(CC)); 434 return false; 435} 436 437bool ARMBaseInstrInfo::isPredicated(const MachineInstr *MI) const { 438 if (MI->isBundle()) { 439 MachineBasicBlock::const_instr_iterator I = MI; 440 MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end(); 441 while (++I != E && I->isInsideBundle()) { 442 int PIdx = I->findFirstPredOperandIdx(); 443 if (PIdx != -1 && I->getOperand(PIdx).getImm() != ARMCC::AL) 444 return true; 445 } 446 return false; 447 } 448 449 int PIdx = MI->findFirstPredOperandIdx(); 450 return PIdx != -1 && MI->getOperand(PIdx).getImm() != ARMCC::AL; 451} 452 453bool ARMBaseInstrInfo:: 454PredicateInstruction(MachineInstr *MI, 455 const SmallVectorImpl<MachineOperand> &Pred) const { 456 unsigned Opc = MI->getOpcode(); 457 if (isUncondBranchOpcode(Opc)) { 458 MI->setDesc(get(getMatchingCondBranchOpcode(Opc))); 459 MachineInstrBuilder(*MI->getParent()->getParent(), MI) 460 .addImm(Pred[0].getImm()) 461 .addReg(Pred[1].getReg()); 462 return true; 463 } 464 465 int PIdx = MI->findFirstPredOperandIdx(); 466 if (PIdx != -1) { 467 MachineOperand &PMO = MI->getOperand(PIdx); 468 PMO.setImm(Pred[0].getImm()); 469 MI->getOperand(PIdx+1).setReg(Pred[1].getReg()); 470 return true; 471 } 472 return false; 473} 474 475bool ARMBaseInstrInfo:: 476SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1, 477 const SmallVectorImpl<MachineOperand> &Pred2) const { 478 if (Pred1.size() > 2 || Pred2.size() > 2) 479 return false; 480 481 ARMCC::CondCodes CC1 = (ARMCC::CondCodes)Pred1[0].getImm(); 482 ARMCC::CondCodes CC2 = (ARMCC::CondCodes)Pred2[0].getImm(); 483 if (CC1 == CC2) 484 return true; 485 486 switch (CC1) { 487 default: 488 return false; 489 case ARMCC::AL: 490 return true; 491 case ARMCC::HS: 492 return CC2 == ARMCC::HI; 493 case ARMCC::LS: 494 return CC2 == ARMCC::LO || CC2 == ARMCC::EQ; 495 case ARMCC::GE: 496 return CC2 == ARMCC::GT; 497 case ARMCC::LE: 498 return CC2 == ARMCC::LT; 499 } 500} 501 502bool ARMBaseInstrInfo::DefinesPredicate(MachineInstr *MI, 503 std::vector<MachineOperand> &Pred) const { 504 bool Found = false; 505 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 506 const MachineOperand &MO = MI->getOperand(i); 507 if ((MO.isRegMask() && MO.clobbersPhysReg(ARM::CPSR)) || 508 (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR)) { 509 Pred.push_back(MO); 510 Found = true; 511 } 512 } 513 514 return Found; 515} 516 517/// isPredicable - Return true if the specified instruction can be predicated. 518/// By default, this returns true for every instruction with a 519/// PredicateOperand. 520bool ARMBaseInstrInfo::isPredicable(MachineInstr *MI) const { 521 if (!MI->isPredicable()) 522 return false; 523 524 ARMFunctionInfo *AFI = 525 MI->getParent()->getParent()->getInfo<ARMFunctionInfo>(); 526 527 if (AFI->isThumb2Function()) { 528 if (getSubtarget().restrictIT()) 529 return isV8EligibleForIT(MI); 530 } else { // non-Thumb 531 if ((MI->getDesc().TSFlags & ARMII::DomainMask) == ARMII::DomainNEON) 532 return false; 533 } 534 535 return true; 536} 537 538/// FIXME: Works around a gcc miscompilation with -fstrict-aliasing. 539LLVM_ATTRIBUTE_NOINLINE 540static unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT, 541 unsigned JTI); 542static unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT, 543 unsigned JTI) { 544 assert(JTI < JT.size()); 545 return JT[JTI].MBBs.size(); 546} 547 548/// GetInstSize - Return the size of the specified MachineInstr. 549/// 550unsigned ARMBaseInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const { 551 const MachineBasicBlock &MBB = *MI->getParent(); 552 const MachineFunction *MF = MBB.getParent(); 553 const MCAsmInfo *MAI = MF->getTarget().getMCAsmInfo(); 554 555 const MCInstrDesc &MCID = MI->getDesc(); 556 if (MCID.getSize()) 557 return MCID.getSize(); 558 559 // If this machine instr is an inline asm, measure it. 560 if (MI->getOpcode() == ARM::INLINEASM) 561 return getInlineAsmLength(MI->getOperand(0).getSymbolName(), *MAI); 562 if (MI->isLabel()) 563 return 0; 564 unsigned Opc = MI->getOpcode(); 565 switch (Opc) { 566 case TargetOpcode::IMPLICIT_DEF: 567 case TargetOpcode::KILL: 568 case TargetOpcode::PROLOG_LABEL: 569 case TargetOpcode::EH_LABEL: 570 case TargetOpcode::DBG_VALUE: 571 return 0; 572 case TargetOpcode::BUNDLE: 573 return getInstBundleLength(MI); 574 case ARM::MOVi16_ga_pcrel: 575 case ARM::MOVTi16_ga_pcrel: 576 case ARM::t2MOVi16_ga_pcrel: 577 case ARM::t2MOVTi16_ga_pcrel: 578 return 4; 579 case ARM::MOVi32imm: 580 case ARM::t2MOVi32imm: 581 return 8; 582 case ARM::CONSTPOOL_ENTRY: 583 // If this machine instr is a constant pool entry, its size is recorded as 584 // operand #2. 585 return MI->getOperand(2).getImm(); 586 case ARM::Int_eh_sjlj_longjmp: 587 return 16; 588 case ARM::tInt_eh_sjlj_longjmp: 589 return 10; 590 case ARM::Int_eh_sjlj_setjmp: 591 case ARM::Int_eh_sjlj_setjmp_nofp: 592 return 20; 593 case ARM::tInt_eh_sjlj_setjmp: 594 case ARM::t2Int_eh_sjlj_setjmp: 595 case ARM::t2Int_eh_sjlj_setjmp_nofp: 596 return 12; 597 case ARM::BR_JTr: 598 case ARM::BR_JTm: 599 case ARM::BR_JTadd: 600 case ARM::tBR_JTr: 601 case ARM::t2BR_JT: 602 case ARM::t2TBB_JT: 603 case ARM::t2TBH_JT: { 604 // These are jumptable branches, i.e. a branch followed by an inlined 605 // jumptable. The size is 4 + 4 * number of entries. For TBB, each 606 // entry is one byte; TBH two byte each. 607 unsigned EntrySize = (Opc == ARM::t2TBB_JT) 608 ? 1 : ((Opc == ARM::t2TBH_JT) ? 2 : 4); 609 unsigned NumOps = MCID.getNumOperands(); 610 MachineOperand JTOP = 611 MI->getOperand(NumOps - (MI->isPredicable() ? 3 : 2)); 612 unsigned JTI = JTOP.getIndex(); 613 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo(); 614 assert(MJTI != 0); 615 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables(); 616 assert(JTI < JT.size()); 617 // Thumb instructions are 2 byte aligned, but JT entries are 4 byte 618 // 4 aligned. The assembler / linker may add 2 byte padding just before 619 // the JT entries. The size does not include this padding; the 620 // constant islands pass does separate bookkeeping for it. 621 // FIXME: If we know the size of the function is less than (1 << 16) *2 622 // bytes, we can use 16-bit entries instead. Then there won't be an 623 // alignment issue. 624 unsigned InstSize = (Opc == ARM::tBR_JTr || Opc == ARM::t2BR_JT) ? 2 : 4; 625 unsigned NumEntries = getNumJTEntries(JT, JTI); 626 if (Opc == ARM::t2TBB_JT && (NumEntries & 1)) 627 // Make sure the instruction that follows TBB is 2-byte aligned. 628 // FIXME: Constant island pass should insert an "ALIGN" instruction 629 // instead. 630 ++NumEntries; 631 return NumEntries * EntrySize + InstSize; 632 } 633 default: 634 // Otherwise, pseudo-instruction sizes are zero. 635 return 0; 636 } 637} 638 639unsigned ARMBaseInstrInfo::getInstBundleLength(const MachineInstr *MI) const { 640 unsigned Size = 0; 641 MachineBasicBlock::const_instr_iterator I = MI; 642 MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end(); 643 while (++I != E && I->isInsideBundle()) { 644 assert(!I->isBundle() && "No nested bundle!"); 645 Size += GetInstSizeInBytes(&*I); 646 } 647 return Size; 648} 649 650void ARMBaseInstrInfo::copyPhysReg(MachineBasicBlock &MBB, 651 MachineBasicBlock::iterator I, DebugLoc DL, 652 unsigned DestReg, unsigned SrcReg, 653 bool KillSrc) const { 654 bool GPRDest = ARM::GPRRegClass.contains(DestReg); 655 bool GPRSrc = ARM::GPRRegClass.contains(SrcReg); 656 657 if (GPRDest && GPRSrc) { 658 AddDefaultCC(AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::MOVr), DestReg) 659 .addReg(SrcReg, getKillRegState(KillSrc)))); 660 return; 661 } 662 663 bool SPRDest = ARM::SPRRegClass.contains(DestReg); 664 bool SPRSrc = ARM::SPRRegClass.contains(SrcReg); 665 666 unsigned Opc = 0; 667 if (SPRDest && SPRSrc) 668 Opc = ARM::VMOVS; 669 else if (GPRDest && SPRSrc) 670 Opc = ARM::VMOVRS; 671 else if (SPRDest && GPRSrc) 672 Opc = ARM::VMOVSR; 673 else if (ARM::DPRRegClass.contains(DestReg, SrcReg)) 674 Opc = ARM::VMOVD; 675 else if (ARM::QPRRegClass.contains(DestReg, SrcReg)) 676 Opc = ARM::VORRq; 677 678 if (Opc) { 679 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc), DestReg); 680 MIB.addReg(SrcReg, getKillRegState(KillSrc)); 681 if (Opc == ARM::VORRq) 682 MIB.addReg(SrcReg, getKillRegState(KillSrc)); 683 AddDefaultPred(MIB); 684 return; 685 } 686 687 // Handle register classes that require multiple instructions. 688 unsigned BeginIdx = 0; 689 unsigned SubRegs = 0; 690 int Spacing = 1; 691 692 // Use VORRq when possible. 693 if (ARM::QQPRRegClass.contains(DestReg, SrcReg)) { 694 Opc = ARM::VORRq; 695 BeginIdx = ARM::qsub_0; 696 SubRegs = 2; 697 } else if (ARM::QQQQPRRegClass.contains(DestReg, SrcReg)) { 698 Opc = ARM::VORRq; 699 BeginIdx = ARM::qsub_0; 700 SubRegs = 4; 701 // Fall back to VMOVD. 702 } else if (ARM::DPairRegClass.contains(DestReg, SrcReg)) { 703 Opc = ARM::VMOVD; 704 BeginIdx = ARM::dsub_0; 705 SubRegs = 2; 706 } else if (ARM::DTripleRegClass.contains(DestReg, SrcReg)) { 707 Opc = ARM::VMOVD; 708 BeginIdx = ARM::dsub_0; 709 SubRegs = 3; 710 } else if (ARM::DQuadRegClass.contains(DestReg, SrcReg)) { 711 Opc = ARM::VMOVD; 712 BeginIdx = ARM::dsub_0; 713 SubRegs = 4; 714 } else if (ARM::GPRPairRegClass.contains(DestReg, SrcReg)) { 715 Opc = Subtarget.isThumb2() ? ARM::tMOVr : ARM::MOVr; 716 BeginIdx = ARM::gsub_0; 717 SubRegs = 2; 718 } else if (ARM::DPairSpcRegClass.contains(DestReg, SrcReg)) { 719 Opc = ARM::VMOVD; 720 BeginIdx = ARM::dsub_0; 721 SubRegs = 2; 722 Spacing = 2; 723 } else if (ARM::DTripleSpcRegClass.contains(DestReg, SrcReg)) { 724 Opc = ARM::VMOVD; 725 BeginIdx = ARM::dsub_0; 726 SubRegs = 3; 727 Spacing = 2; 728 } else if (ARM::DQuadSpcRegClass.contains(DestReg, SrcReg)) { 729 Opc = ARM::VMOVD; 730 BeginIdx = ARM::dsub_0; 731 SubRegs = 4; 732 Spacing = 2; 733 } 734 735 assert(Opc && "Impossible reg-to-reg copy"); 736 737 const TargetRegisterInfo *TRI = &getRegisterInfo(); 738 MachineInstrBuilder Mov; 739 740 // Copy register tuples backward when the first Dest reg overlaps with SrcReg. 741 if (TRI->regsOverlap(SrcReg, TRI->getSubReg(DestReg, BeginIdx))) { 742 BeginIdx = BeginIdx + ((SubRegs - 1) * Spacing); 743 Spacing = -Spacing; 744 } 745#ifndef NDEBUG 746 SmallSet<unsigned, 4> DstRegs; 747#endif 748 for (unsigned i = 0; i != SubRegs; ++i) { 749 unsigned Dst = TRI->getSubReg(DestReg, BeginIdx + i * Spacing); 750 unsigned Src = TRI->getSubReg(SrcReg, BeginIdx + i * Spacing); 751 assert(Dst && Src && "Bad sub-register"); 752#ifndef NDEBUG 753 assert(!DstRegs.count(Src) && "destructive vector copy"); 754 DstRegs.insert(Dst); 755#endif 756 Mov = BuildMI(MBB, I, I->getDebugLoc(), get(Opc), Dst).addReg(Src); 757 // VORR takes two source operands. 758 if (Opc == ARM::VORRq) 759 Mov.addReg(Src); 760 Mov = AddDefaultPred(Mov); 761 // MOVr can set CC. 762 if (Opc == ARM::MOVr) 763 Mov = AddDefaultCC(Mov); 764 } 765 // Add implicit super-register defs and kills to the last instruction. 766 Mov->addRegisterDefined(DestReg, TRI); 767 if (KillSrc) 768 Mov->addRegisterKilled(SrcReg, TRI); 769} 770 771const MachineInstrBuilder & 772ARMBaseInstrInfo::AddDReg(MachineInstrBuilder &MIB, unsigned Reg, 773 unsigned SubIdx, unsigned State, 774 const TargetRegisterInfo *TRI) const { 775 if (!SubIdx) 776 return MIB.addReg(Reg, State); 777 778 if (TargetRegisterInfo::isPhysicalRegister(Reg)) 779 return MIB.addReg(TRI->getSubReg(Reg, SubIdx), State); 780 return MIB.addReg(Reg, State, SubIdx); 781} 782 783void ARMBaseInstrInfo:: 784storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 785 unsigned SrcReg, bool isKill, int FI, 786 const TargetRegisterClass *RC, 787 const TargetRegisterInfo *TRI) const { 788 DebugLoc DL; 789 if (I != MBB.end()) DL = I->getDebugLoc(); 790 MachineFunction &MF = *MBB.getParent(); 791 MachineFrameInfo &MFI = *MF.getFrameInfo(); 792 unsigned Align = MFI.getObjectAlignment(FI); 793 794 MachineMemOperand *MMO = 795 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FI), 796 MachineMemOperand::MOStore, 797 MFI.getObjectSize(FI), 798 Align); 799 800 switch (RC->getSize()) { 801 case 4: 802 if (ARM::GPRRegClass.hasSubClassEq(RC)) { 803 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::STRi12)) 804 .addReg(SrcReg, getKillRegState(isKill)) 805 .addFrameIndex(FI).addImm(0).addMemOperand(MMO)); 806 } else if (ARM::SPRRegClass.hasSubClassEq(RC)) { 807 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTRS)) 808 .addReg(SrcReg, getKillRegState(isKill)) 809 .addFrameIndex(FI).addImm(0).addMemOperand(MMO)); 810 } else 811 llvm_unreachable("Unknown reg class!"); 812 break; 813 case 8: 814 if (ARM::DPRRegClass.hasSubClassEq(RC)) { 815 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTRD)) 816 .addReg(SrcReg, getKillRegState(isKill)) 817 .addFrameIndex(FI).addImm(0).addMemOperand(MMO)); 818 } else if (ARM::GPRPairRegClass.hasSubClassEq(RC)) { 819 if (Subtarget.hasV5TEOps()) { 820 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::STRD)); 821 AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill), TRI); 822 AddDReg(MIB, SrcReg, ARM::gsub_1, 0, TRI); 823 MIB.addFrameIndex(FI).addReg(0).addImm(0).addMemOperand(MMO); 824 825 AddDefaultPred(MIB); 826 } else { 827 // Fallback to STM instruction, which has existed since the dawn of 828 // time. 829 MachineInstrBuilder MIB = 830 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::STMIA)) 831 .addFrameIndex(FI).addMemOperand(MMO)); 832 AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill), TRI); 833 AddDReg(MIB, SrcReg, ARM::gsub_1, 0, TRI); 834 } 835 } else 836 llvm_unreachable("Unknown reg class!"); 837 break; 838 case 16: 839 if (ARM::DPairRegClass.hasSubClassEq(RC)) { 840 // Use aligned spills if the stack can be realigned. 841 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) { 842 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1q64)) 843 .addFrameIndex(FI).addImm(16) 844 .addReg(SrcReg, getKillRegState(isKill)) 845 .addMemOperand(MMO)); 846 } else { 847 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMQIA)) 848 .addReg(SrcReg, getKillRegState(isKill)) 849 .addFrameIndex(FI) 850 .addMemOperand(MMO)); 851 } 852 } else 853 llvm_unreachable("Unknown reg class!"); 854 break; 855 case 24: 856 if (ARM::DTripleRegClass.hasSubClassEq(RC)) { 857 // Use aligned spills if the stack can be realigned. 858 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) { 859 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1d64TPseudo)) 860 .addFrameIndex(FI).addImm(16) 861 .addReg(SrcReg, getKillRegState(isKill)) 862 .addMemOperand(MMO)); 863 } else { 864 MachineInstrBuilder MIB = 865 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMDIA)) 866 .addFrameIndex(FI)) 867 .addMemOperand(MMO); 868 MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI); 869 MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI); 870 AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI); 871 } 872 } else 873 llvm_unreachable("Unknown reg class!"); 874 break; 875 case 32: 876 if (ARM::QQPRRegClass.hasSubClassEq(RC) || ARM::DQuadRegClass.hasSubClassEq(RC)) { 877 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) { 878 // FIXME: It's possible to only store part of the QQ register if the 879 // spilled def has a sub-register index. 880 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1d64QPseudo)) 881 .addFrameIndex(FI).addImm(16) 882 .addReg(SrcReg, getKillRegState(isKill)) 883 .addMemOperand(MMO)); 884 } else { 885 MachineInstrBuilder MIB = 886 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMDIA)) 887 .addFrameIndex(FI)) 888 .addMemOperand(MMO); 889 MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI); 890 MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI); 891 MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI); 892 AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI); 893 } 894 } else 895 llvm_unreachable("Unknown reg class!"); 896 break; 897 case 64: 898 if (ARM::QQQQPRRegClass.hasSubClassEq(RC)) { 899 MachineInstrBuilder MIB = 900 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMDIA)) 901 .addFrameIndex(FI)) 902 .addMemOperand(MMO); 903 MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI); 904 MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI); 905 MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI); 906 MIB = AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI); 907 MIB = AddDReg(MIB, SrcReg, ARM::dsub_4, 0, TRI); 908 MIB = AddDReg(MIB, SrcReg, ARM::dsub_5, 0, TRI); 909 MIB = AddDReg(MIB, SrcReg, ARM::dsub_6, 0, TRI); 910 AddDReg(MIB, SrcReg, ARM::dsub_7, 0, TRI); 911 } else 912 llvm_unreachable("Unknown reg class!"); 913 break; 914 default: 915 llvm_unreachable("Unknown reg class!"); 916 } 917} 918 919unsigned 920ARMBaseInstrInfo::isStoreToStackSlot(const MachineInstr *MI, 921 int &FrameIndex) const { 922 switch (MI->getOpcode()) { 923 default: break; 924 case ARM::STRrs: 925 case ARM::t2STRs: // FIXME: don't use t2STRs to access frame. 926 if (MI->getOperand(1).isFI() && 927 MI->getOperand(2).isReg() && 928 MI->getOperand(3).isImm() && 929 MI->getOperand(2).getReg() == 0 && 930 MI->getOperand(3).getImm() == 0) { 931 FrameIndex = MI->getOperand(1).getIndex(); 932 return MI->getOperand(0).getReg(); 933 } 934 break; 935 case ARM::STRi12: 936 case ARM::t2STRi12: 937 case ARM::tSTRspi: 938 case ARM::VSTRD: 939 case ARM::VSTRS: 940 if (MI->getOperand(1).isFI() && 941 MI->getOperand(2).isImm() && 942 MI->getOperand(2).getImm() == 0) { 943 FrameIndex = MI->getOperand(1).getIndex(); 944 return MI->getOperand(0).getReg(); 945 } 946 break; 947 case ARM::VST1q64: 948 case ARM::VST1d64TPseudo: 949 case ARM::VST1d64QPseudo: 950 if (MI->getOperand(0).isFI() && 951 MI->getOperand(2).getSubReg() == 0) { 952 FrameIndex = MI->getOperand(0).getIndex(); 953 return MI->getOperand(2).getReg(); 954 } 955 break; 956 case ARM::VSTMQIA: 957 if (MI->getOperand(1).isFI() && 958 MI->getOperand(0).getSubReg() == 0) { 959 FrameIndex = MI->getOperand(1).getIndex(); 960 return MI->getOperand(0).getReg(); 961 } 962 break; 963 } 964 965 return 0; 966} 967 968unsigned ARMBaseInstrInfo::isStoreToStackSlotPostFE(const MachineInstr *MI, 969 int &FrameIndex) const { 970 const MachineMemOperand *Dummy; 971 return MI->mayStore() && hasStoreToStackSlot(MI, Dummy, FrameIndex); 972} 973 974void ARMBaseInstrInfo:: 975loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 976 unsigned DestReg, int FI, 977 const TargetRegisterClass *RC, 978 const TargetRegisterInfo *TRI) const { 979 DebugLoc DL; 980 if (I != MBB.end()) DL = I->getDebugLoc(); 981 MachineFunction &MF = *MBB.getParent(); 982 MachineFrameInfo &MFI = *MF.getFrameInfo(); 983 unsigned Align = MFI.getObjectAlignment(FI); 984 MachineMemOperand *MMO = 985 MF.getMachineMemOperand( 986 MachinePointerInfo::getFixedStack(FI), 987 MachineMemOperand::MOLoad, 988 MFI.getObjectSize(FI), 989 Align); 990 991 switch (RC->getSize()) { 992 case 4: 993 if (ARM::GPRRegClass.hasSubClassEq(RC)) { 994 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::LDRi12), DestReg) 995 .addFrameIndex(FI).addImm(0).addMemOperand(MMO)); 996 997 } else if (ARM::SPRRegClass.hasSubClassEq(RC)) { 998 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRS), DestReg) 999 .addFrameIndex(FI).addImm(0).addMemOperand(MMO)); 1000 } else 1001 llvm_unreachable("Unknown reg class!"); 1002 break; 1003 case 8: 1004 if (ARM::DPRRegClass.hasSubClassEq(RC)) { 1005 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRD), DestReg) 1006 .addFrameIndex(FI).addImm(0).addMemOperand(MMO)); 1007 } else if (ARM::GPRPairRegClass.hasSubClassEq(RC)) { 1008 MachineInstrBuilder MIB; 1009 1010 if (Subtarget.hasV5TEOps()) { 1011 MIB = BuildMI(MBB, I, DL, get(ARM::LDRD)); 1012 AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI); 1013 AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI); 1014 MIB.addFrameIndex(FI).addReg(0).addImm(0).addMemOperand(MMO); 1015 1016 AddDefaultPred(MIB); 1017 } else { 1018 // Fallback to LDM instruction, which has existed since the dawn of 1019 // time. 1020 MIB = AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::LDMIA)) 1021 .addFrameIndex(FI).addMemOperand(MMO)); 1022 MIB = AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI); 1023 MIB = AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI); 1024 } 1025 1026 if (TargetRegisterInfo::isPhysicalRegister(DestReg)) 1027 MIB.addReg(DestReg, RegState::ImplicitDefine); 1028 } else 1029 llvm_unreachable("Unknown reg class!"); 1030 break; 1031 case 16: 1032 if (ARM::DPairRegClass.hasSubClassEq(RC)) { 1033 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) { 1034 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1q64), DestReg) 1035 .addFrameIndex(FI).addImm(16) 1036 .addMemOperand(MMO)); 1037 } else { 1038 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMQIA), DestReg) 1039 .addFrameIndex(FI) 1040 .addMemOperand(MMO)); 1041 } 1042 } else 1043 llvm_unreachable("Unknown reg class!"); 1044 break; 1045 case 24: 1046 if (ARM::DTripleRegClass.hasSubClassEq(RC)) { 1047 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) { 1048 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1d64TPseudo), DestReg) 1049 .addFrameIndex(FI).addImm(16) 1050 .addMemOperand(MMO)); 1051 } else { 1052 MachineInstrBuilder MIB = 1053 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMDIA)) 1054 .addFrameIndex(FI) 1055 .addMemOperand(MMO)); 1056 MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI); 1057 MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI); 1058 MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI); 1059 if (TargetRegisterInfo::isPhysicalRegister(DestReg)) 1060 MIB.addReg(DestReg, RegState::ImplicitDefine); 1061 } 1062 } else 1063 llvm_unreachable("Unknown reg class!"); 1064 break; 1065 case 32: 1066 if (ARM::QQPRRegClass.hasSubClassEq(RC) || ARM::DQuadRegClass.hasSubClassEq(RC)) { 1067 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) { 1068 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1d64QPseudo), DestReg) 1069 .addFrameIndex(FI).addImm(16) 1070 .addMemOperand(MMO)); 1071 } else { 1072 MachineInstrBuilder MIB = 1073 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMDIA)) 1074 .addFrameIndex(FI)) 1075 .addMemOperand(MMO); 1076 MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI); 1077 MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI); 1078 MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI); 1079 MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::DefineNoRead, TRI); 1080 if (TargetRegisterInfo::isPhysicalRegister(DestReg)) 1081 MIB.addReg(DestReg, RegState::ImplicitDefine); 1082 } 1083 } else 1084 llvm_unreachable("Unknown reg class!"); 1085 break; 1086 case 64: 1087 if (ARM::QQQQPRRegClass.hasSubClassEq(RC)) { 1088 MachineInstrBuilder MIB = 1089 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMDIA)) 1090 .addFrameIndex(FI)) 1091 .addMemOperand(MMO); 1092 MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI); 1093 MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI); 1094 MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI); 1095 MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::DefineNoRead, TRI); 1096 MIB = AddDReg(MIB, DestReg, ARM::dsub_4, RegState::DefineNoRead, TRI); 1097 MIB = AddDReg(MIB, DestReg, ARM::dsub_5, RegState::DefineNoRead, TRI); 1098 MIB = AddDReg(MIB, DestReg, ARM::dsub_6, RegState::DefineNoRead, TRI); 1099 MIB = AddDReg(MIB, DestReg, ARM::dsub_7, RegState::DefineNoRead, TRI); 1100 if (TargetRegisterInfo::isPhysicalRegister(DestReg)) 1101 MIB.addReg(DestReg, RegState::ImplicitDefine); 1102 } else 1103 llvm_unreachable("Unknown reg class!"); 1104 break; 1105 default: 1106 llvm_unreachable("Unknown regclass!"); 1107 } 1108} 1109 1110unsigned 1111ARMBaseInstrInfo::isLoadFromStackSlot(const MachineInstr *MI, 1112 int &FrameIndex) const { 1113 switch (MI->getOpcode()) { 1114 default: break; 1115 case ARM::LDRrs: 1116 case ARM::t2LDRs: // FIXME: don't use t2LDRs to access frame. 1117 if (MI->getOperand(1).isFI() && 1118 MI->getOperand(2).isReg() && 1119 MI->getOperand(3).isImm() && 1120 MI->getOperand(2).getReg() == 0 && 1121 MI->getOperand(3).getImm() == 0) { 1122 FrameIndex = MI->getOperand(1).getIndex(); 1123 return MI->getOperand(0).getReg(); 1124 } 1125 break; 1126 case ARM::LDRi12: 1127 case ARM::t2LDRi12: 1128 case ARM::tLDRspi: 1129 case ARM::VLDRD: 1130 case ARM::VLDRS: 1131 if (MI->getOperand(1).isFI() && 1132 MI->getOperand(2).isImm() && 1133 MI->getOperand(2).getImm() == 0) { 1134 FrameIndex = MI->getOperand(1).getIndex(); 1135 return MI->getOperand(0).getReg(); 1136 } 1137 break; 1138 case ARM::VLD1q64: 1139 case ARM::VLD1d64TPseudo: 1140 case ARM::VLD1d64QPseudo: 1141 if (MI->getOperand(1).isFI() && 1142 MI->getOperand(0).getSubReg() == 0) { 1143 FrameIndex = MI->getOperand(1).getIndex(); 1144 return MI->getOperand(0).getReg(); 1145 } 1146 break; 1147 case ARM::VLDMQIA: 1148 if (MI->getOperand(1).isFI() && 1149 MI->getOperand(0).getSubReg() == 0) { 1150 FrameIndex = MI->getOperand(1).getIndex(); 1151 return MI->getOperand(0).getReg(); 1152 } 1153 break; 1154 } 1155 1156 return 0; 1157} 1158 1159unsigned ARMBaseInstrInfo::isLoadFromStackSlotPostFE(const MachineInstr *MI, 1160 int &FrameIndex) const { 1161 const MachineMemOperand *Dummy; 1162 return MI->mayLoad() && hasLoadFromStackSlot(MI, Dummy, FrameIndex); 1163} 1164 1165bool ARMBaseInstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const{ 1166 // This hook gets to expand COPY instructions before they become 1167 // copyPhysReg() calls. Look for VMOVS instructions that can legally be 1168 // widened to VMOVD. We prefer the VMOVD when possible because it may be 1169 // changed into a VORR that can go down the NEON pipeline. 1170 if (!WidenVMOVS || !MI->isCopy() || Subtarget.isCortexA15()) 1171 return false; 1172 1173 // Look for a copy between even S-registers. That is where we keep floats 1174 // when using NEON v2f32 instructions for f32 arithmetic. 1175 unsigned DstRegS = MI->getOperand(0).getReg(); 1176 unsigned SrcRegS = MI->getOperand(1).getReg(); 1177 if (!ARM::SPRRegClass.contains(DstRegS, SrcRegS)) 1178 return false; 1179 1180 const TargetRegisterInfo *TRI = &getRegisterInfo(); 1181 unsigned DstRegD = TRI->getMatchingSuperReg(DstRegS, ARM::ssub_0, 1182 &ARM::DPRRegClass); 1183 unsigned SrcRegD = TRI->getMatchingSuperReg(SrcRegS, ARM::ssub_0, 1184 &ARM::DPRRegClass); 1185 if (!DstRegD || !SrcRegD) 1186 return false; 1187 1188 // We want to widen this into a DstRegD = VMOVD SrcRegD copy. This is only 1189 // legal if the COPY already defines the full DstRegD, and it isn't a 1190 // sub-register insertion. 1191 if (!MI->definesRegister(DstRegD, TRI) || MI->readsRegister(DstRegD, TRI)) 1192 return false; 1193 1194 // A dead copy shouldn't show up here, but reject it just in case. 1195 if (MI->getOperand(0).isDead()) 1196 return false; 1197 1198 // All clear, widen the COPY. 1199 DEBUG(dbgs() << "widening: " << *MI); 1200 MachineInstrBuilder MIB(*MI->getParent()->getParent(), MI); 1201 1202 // Get rid of the old <imp-def> of DstRegD. Leave it if it defines a Q-reg 1203 // or some other super-register. 1204 int ImpDefIdx = MI->findRegisterDefOperandIdx(DstRegD); 1205 if (ImpDefIdx != -1) 1206 MI->RemoveOperand(ImpDefIdx); 1207 1208 // Change the opcode and operands. 1209 MI->setDesc(get(ARM::VMOVD)); 1210 MI->getOperand(0).setReg(DstRegD); 1211 MI->getOperand(1).setReg(SrcRegD); 1212 AddDefaultPred(MIB); 1213 1214 // We are now reading SrcRegD instead of SrcRegS. This may upset the 1215 // register scavenger and machine verifier, so we need to indicate that we 1216 // are reading an undefined value from SrcRegD, but a proper value from 1217 // SrcRegS. 1218 MI->getOperand(1).setIsUndef(); 1219 MIB.addReg(SrcRegS, RegState::Implicit); 1220 1221 // SrcRegD may actually contain an unrelated value in the ssub_1 1222 // sub-register. Don't kill it. Only kill the ssub_0 sub-register. 1223 if (MI->getOperand(1).isKill()) { 1224 MI->getOperand(1).setIsKill(false); 1225 MI->addRegisterKilled(SrcRegS, TRI, true); 1226 } 1227 1228 DEBUG(dbgs() << "replaced by: " << *MI); 1229 return true; 1230} 1231 1232/// Create a copy of a const pool value. Update CPI to the new index and return 1233/// the label UID. 1234static unsigned duplicateCPV(MachineFunction &MF, unsigned &CPI) { 1235 MachineConstantPool *MCP = MF.getConstantPool(); 1236 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 1237 1238 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPI]; 1239 assert(MCPE.isMachineConstantPoolEntry() && 1240 "Expecting a machine constantpool entry!"); 1241 ARMConstantPoolValue *ACPV = 1242 static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal); 1243 1244 unsigned PCLabelId = AFI->createPICLabelUId(); 1245 ARMConstantPoolValue *NewCPV = 0; 1246 // FIXME: The below assumes PIC relocation model and that the function 1247 // is Thumb mode (t1 or t2). PCAdjustment would be 8 for ARM mode PIC, and 1248 // zero for non-PIC in ARM or Thumb. The callers are all of thumb LDR 1249 // instructions, so that's probably OK, but is PIC always correct when 1250 // we get here? 1251 if (ACPV->isGlobalValue()) 1252 NewCPV = ARMConstantPoolConstant:: 1253 Create(cast<ARMConstantPoolConstant>(ACPV)->getGV(), PCLabelId, 1254 ARMCP::CPValue, 4); 1255 else if (ACPV->isExtSymbol()) 1256 NewCPV = ARMConstantPoolSymbol:: 1257 Create(MF.getFunction()->getContext(), 1258 cast<ARMConstantPoolSymbol>(ACPV)->getSymbol(), PCLabelId, 4); 1259 else if (ACPV->isBlockAddress()) 1260 NewCPV = ARMConstantPoolConstant:: 1261 Create(cast<ARMConstantPoolConstant>(ACPV)->getBlockAddress(), PCLabelId, 1262 ARMCP::CPBlockAddress, 4); 1263 else if (ACPV->isLSDA()) 1264 NewCPV = ARMConstantPoolConstant::Create(MF.getFunction(), PCLabelId, 1265 ARMCP::CPLSDA, 4); 1266 else if (ACPV->isMachineBasicBlock()) 1267 NewCPV = ARMConstantPoolMBB:: 1268 Create(MF.getFunction()->getContext(), 1269 cast<ARMConstantPoolMBB>(ACPV)->getMBB(), PCLabelId, 4); 1270 else 1271 llvm_unreachable("Unexpected ARM constantpool value type!!"); 1272 CPI = MCP->getConstantPoolIndex(NewCPV, MCPE.getAlignment()); 1273 return PCLabelId; 1274} 1275 1276void ARMBaseInstrInfo:: 1277reMaterialize(MachineBasicBlock &MBB, 1278 MachineBasicBlock::iterator I, 1279 unsigned DestReg, unsigned SubIdx, 1280 const MachineInstr *Orig, 1281 const TargetRegisterInfo &TRI) const { 1282 unsigned Opcode = Orig->getOpcode(); 1283 switch (Opcode) { 1284 default: { 1285 MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig); 1286 MI->substituteRegister(Orig->getOperand(0).getReg(), DestReg, SubIdx, TRI); 1287 MBB.insert(I, MI); 1288 break; 1289 } 1290 case ARM::tLDRpci_pic: 1291 case ARM::t2LDRpci_pic: { 1292 MachineFunction &MF = *MBB.getParent(); 1293 unsigned CPI = Orig->getOperand(1).getIndex(); 1294 unsigned PCLabelId = duplicateCPV(MF, CPI); 1295 MachineInstrBuilder MIB = BuildMI(MBB, I, Orig->getDebugLoc(), get(Opcode), 1296 DestReg) 1297 .addConstantPoolIndex(CPI).addImm(PCLabelId); 1298 MIB->setMemRefs(Orig->memoperands_begin(), Orig->memoperands_end()); 1299 break; 1300 } 1301 } 1302} 1303 1304MachineInstr * 1305ARMBaseInstrInfo::duplicate(MachineInstr *Orig, MachineFunction &MF) const { 1306 MachineInstr *MI = TargetInstrInfo::duplicate(Orig, MF); 1307 switch(Orig->getOpcode()) { 1308 case ARM::tLDRpci_pic: 1309 case ARM::t2LDRpci_pic: { 1310 unsigned CPI = Orig->getOperand(1).getIndex(); 1311 unsigned PCLabelId = duplicateCPV(MF, CPI); 1312 Orig->getOperand(1).setIndex(CPI); 1313 Orig->getOperand(2).setImm(PCLabelId); 1314 break; 1315 } 1316 } 1317 return MI; 1318} 1319 1320bool ARMBaseInstrInfo::produceSameValue(const MachineInstr *MI0, 1321 const MachineInstr *MI1, 1322 const MachineRegisterInfo *MRI) const { 1323 int Opcode = MI0->getOpcode(); 1324 if (Opcode == ARM::t2LDRpci || 1325 Opcode == ARM::t2LDRpci_pic || 1326 Opcode == ARM::tLDRpci || 1327 Opcode == ARM::tLDRpci_pic || 1328 Opcode == ARM::MOV_ga_dyn || 1329 Opcode == ARM::MOV_ga_pcrel || 1330 Opcode == ARM::MOV_ga_pcrel_ldr || 1331 Opcode == ARM::t2MOV_ga_dyn || 1332 Opcode == ARM::t2MOV_ga_pcrel) { 1333 if (MI1->getOpcode() != Opcode) 1334 return false; 1335 if (MI0->getNumOperands() != MI1->getNumOperands()) 1336 return false; 1337 1338 const MachineOperand &MO0 = MI0->getOperand(1); 1339 const MachineOperand &MO1 = MI1->getOperand(1); 1340 if (MO0.getOffset() != MO1.getOffset()) 1341 return false; 1342 1343 if (Opcode == ARM::MOV_ga_dyn || 1344 Opcode == ARM::MOV_ga_pcrel || 1345 Opcode == ARM::MOV_ga_pcrel_ldr || 1346 Opcode == ARM::t2MOV_ga_dyn || 1347 Opcode == ARM::t2MOV_ga_pcrel) 1348 // Ignore the PC labels. 1349 return MO0.getGlobal() == MO1.getGlobal(); 1350 1351 const MachineFunction *MF = MI0->getParent()->getParent(); 1352 const MachineConstantPool *MCP = MF->getConstantPool(); 1353 int CPI0 = MO0.getIndex(); 1354 int CPI1 = MO1.getIndex(); 1355 const MachineConstantPoolEntry &MCPE0 = MCP->getConstants()[CPI0]; 1356 const MachineConstantPoolEntry &MCPE1 = MCP->getConstants()[CPI1]; 1357 bool isARMCP0 = MCPE0.isMachineConstantPoolEntry(); 1358 bool isARMCP1 = MCPE1.isMachineConstantPoolEntry(); 1359 if (isARMCP0 && isARMCP1) { 1360 ARMConstantPoolValue *ACPV0 = 1361 static_cast<ARMConstantPoolValue*>(MCPE0.Val.MachineCPVal); 1362 ARMConstantPoolValue *ACPV1 = 1363 static_cast<ARMConstantPoolValue*>(MCPE1.Val.MachineCPVal); 1364 return ACPV0->hasSameValue(ACPV1); 1365 } else if (!isARMCP0 && !isARMCP1) { 1366 return MCPE0.Val.ConstVal == MCPE1.Val.ConstVal; 1367 } 1368 return false; 1369 } else if (Opcode == ARM::PICLDR) { 1370 if (MI1->getOpcode() != Opcode) 1371 return false; 1372 if (MI0->getNumOperands() != MI1->getNumOperands()) 1373 return false; 1374 1375 unsigned Addr0 = MI0->getOperand(1).getReg(); 1376 unsigned Addr1 = MI1->getOperand(1).getReg(); 1377 if (Addr0 != Addr1) { 1378 if (!MRI || 1379 !TargetRegisterInfo::isVirtualRegister(Addr0) || 1380 !TargetRegisterInfo::isVirtualRegister(Addr1)) 1381 return false; 1382 1383 // This assumes SSA form. 1384 MachineInstr *Def0 = MRI->getVRegDef(Addr0); 1385 MachineInstr *Def1 = MRI->getVRegDef(Addr1); 1386 // Check if the loaded value, e.g. a constantpool of a global address, are 1387 // the same. 1388 if (!produceSameValue(Def0, Def1, MRI)) 1389 return false; 1390 } 1391 1392 for (unsigned i = 3, e = MI0->getNumOperands(); i != e; ++i) { 1393 // %vreg12<def> = PICLDR %vreg11, 0, pred:14, pred:%noreg 1394 const MachineOperand &MO0 = MI0->getOperand(i); 1395 const MachineOperand &MO1 = MI1->getOperand(i); 1396 if (!MO0.isIdenticalTo(MO1)) 1397 return false; 1398 } 1399 return true; 1400 } 1401 1402 return MI0->isIdenticalTo(MI1, MachineInstr::IgnoreVRegDefs); 1403} 1404 1405/// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to 1406/// determine if two loads are loading from the same base address. It should 1407/// only return true if the base pointers are the same and the only differences 1408/// between the two addresses is the offset. It also returns the offsets by 1409/// reference. 1410/// 1411/// FIXME: remove this in favor of the MachineInstr interface once pre-RA-sched 1412/// is permanently disabled. 1413bool ARMBaseInstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, 1414 int64_t &Offset1, 1415 int64_t &Offset2) const { 1416 // Don't worry about Thumb: just ARM and Thumb2. 1417 if (Subtarget.isThumb1Only()) return false; 1418 1419 if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode()) 1420 return false; 1421 1422 switch (Load1->getMachineOpcode()) { 1423 default: 1424 return false; 1425 case ARM::LDRi12: 1426 case ARM::LDRBi12: 1427 case ARM::LDRD: 1428 case ARM::LDRH: 1429 case ARM::LDRSB: 1430 case ARM::LDRSH: 1431 case ARM::VLDRD: 1432 case ARM::VLDRS: 1433 case ARM::t2LDRi8: 1434 case ARM::t2LDRBi8: 1435 case ARM::t2LDRDi8: 1436 case ARM::t2LDRSHi8: 1437 case ARM::t2LDRi12: 1438 case ARM::t2LDRBi12: 1439 case ARM::t2LDRSHi12: 1440 break; 1441 } 1442 1443 switch (Load2->getMachineOpcode()) { 1444 default: 1445 return false; 1446 case ARM::LDRi12: 1447 case ARM::LDRBi12: 1448 case ARM::LDRD: 1449 case ARM::LDRH: 1450 case ARM::LDRSB: 1451 case ARM::LDRSH: 1452 case ARM::VLDRD: 1453 case ARM::VLDRS: 1454 case ARM::t2LDRi8: 1455 case ARM::t2LDRBi8: 1456 case ARM::t2LDRSHi8: 1457 case ARM::t2LDRi12: 1458 case ARM::t2LDRBi12: 1459 case ARM::t2LDRSHi12: 1460 break; 1461 } 1462 1463 // Check if base addresses and chain operands match. 1464 if (Load1->getOperand(0) != Load2->getOperand(0) || 1465 Load1->getOperand(4) != Load2->getOperand(4)) 1466 return false; 1467 1468 // Index should be Reg0. 1469 if (Load1->getOperand(3) != Load2->getOperand(3)) 1470 return false; 1471 1472 // Determine the offsets. 1473 if (isa<ConstantSDNode>(Load1->getOperand(1)) && 1474 isa<ConstantSDNode>(Load2->getOperand(1))) { 1475 Offset1 = cast<ConstantSDNode>(Load1->getOperand(1))->getSExtValue(); 1476 Offset2 = cast<ConstantSDNode>(Load2->getOperand(1))->getSExtValue(); 1477 return true; 1478 } 1479 1480 return false; 1481} 1482 1483/// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to 1484/// determine (in conjunction with areLoadsFromSameBasePtr) if two loads should 1485/// be scheduled togther. On some targets if two loads are loading from 1486/// addresses in the same cache line, it's better if they are scheduled 1487/// together. This function takes two integers that represent the load offsets 1488/// from the common base address. It returns true if it decides it's desirable 1489/// to schedule the two loads together. "NumLoads" is the number of loads that 1490/// have already been scheduled after Load1. 1491/// 1492/// FIXME: remove this in favor of the MachineInstr interface once pre-RA-sched 1493/// is permanently disabled. 1494bool ARMBaseInstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, 1495 int64_t Offset1, int64_t Offset2, 1496 unsigned NumLoads) const { 1497 // Don't worry about Thumb: just ARM and Thumb2. 1498 if (Subtarget.isThumb1Only()) return false; 1499 1500 assert(Offset2 > Offset1); 1501 1502 if ((Offset2 - Offset1) / 8 > 64) 1503 return false; 1504 1505 // Check if the machine opcodes are different. If they are different 1506 // then we consider them to not be of the same base address, 1507 // EXCEPT in the case of Thumb2 byte loads where one is LDRBi8 and the other LDRBi12. 1508 // In this case, they are considered to be the same because they are different 1509 // encoding forms of the same basic instruction. 1510 if ((Load1->getMachineOpcode() != Load2->getMachineOpcode()) && 1511 !((Load1->getMachineOpcode() == ARM::t2LDRBi8 && 1512 Load2->getMachineOpcode() == ARM::t2LDRBi12) || 1513 (Load1->getMachineOpcode() == ARM::t2LDRBi12 && 1514 Load2->getMachineOpcode() == ARM::t2LDRBi8))) 1515 return false; // FIXME: overly conservative? 1516 1517 // Four loads in a row should be sufficient. 1518 if (NumLoads >= 3) 1519 return false; 1520 1521 return true; 1522} 1523 1524bool ARMBaseInstrInfo::isSchedulingBoundary(const MachineInstr *MI, 1525 const MachineBasicBlock *MBB, 1526 const MachineFunction &MF) const { 1527 // Debug info is never a scheduling boundary. It's necessary to be explicit 1528 // due to the special treatment of IT instructions below, otherwise a 1529 // dbg_value followed by an IT will result in the IT instruction being 1530 // considered a scheduling hazard, which is wrong. It should be the actual 1531 // instruction preceding the dbg_value instruction(s), just like it is 1532 // when debug info is not present. 1533 if (MI->isDebugValue()) 1534 return false; 1535 1536 // Terminators and labels can't be scheduled around. 1537 if (MI->isTerminator() || MI->isLabel()) 1538 return true; 1539 1540 // Treat the start of the IT block as a scheduling boundary, but schedule 1541 // t2IT along with all instructions following it. 1542 // FIXME: This is a big hammer. But the alternative is to add all potential 1543 // true and anti dependencies to IT block instructions as implicit operands 1544 // to the t2IT instruction. The added compile time and complexity does not 1545 // seem worth it. 1546 MachineBasicBlock::const_iterator I = MI; 1547 // Make sure to skip any dbg_value instructions 1548 while (++I != MBB->end() && I->isDebugValue()) 1549 ; 1550 if (I != MBB->end() && I->getOpcode() == ARM::t2IT) 1551 return true; 1552 1553 // Don't attempt to schedule around any instruction that defines 1554 // a stack-oriented pointer, as it's unlikely to be profitable. This 1555 // saves compile time, because it doesn't require every single 1556 // stack slot reference to depend on the instruction that does the 1557 // modification. 1558 // Calls don't actually change the stack pointer, even if they have imp-defs. 1559 // No ARM calling conventions change the stack pointer. (X86 calling 1560 // conventions sometimes do). 1561 if (!MI->isCall() && MI->definesRegister(ARM::SP)) 1562 return true; 1563 1564 return false; 1565} 1566 1567bool ARMBaseInstrInfo:: 1568isProfitableToIfCvt(MachineBasicBlock &MBB, 1569 unsigned NumCycles, unsigned ExtraPredCycles, 1570 const BranchProbability &Probability) const { 1571 if (!NumCycles) 1572 return false; 1573 1574 // Attempt to estimate the relative costs of predication versus branching. 1575 unsigned UnpredCost = Probability.getNumerator() * NumCycles; 1576 UnpredCost /= Probability.getDenominator(); 1577 UnpredCost += 1; // The branch itself 1578 UnpredCost += Subtarget.getMispredictionPenalty() / 10; 1579 1580 return (NumCycles + ExtraPredCycles) <= UnpredCost; 1581} 1582 1583bool ARMBaseInstrInfo:: 1584isProfitableToIfCvt(MachineBasicBlock &TMBB, 1585 unsigned TCycles, unsigned TExtra, 1586 MachineBasicBlock &FMBB, 1587 unsigned FCycles, unsigned FExtra, 1588 const BranchProbability &Probability) const { 1589 if (!TCycles || !FCycles) 1590 return false; 1591 1592 // Attempt to estimate the relative costs of predication versus branching. 1593 unsigned TUnpredCost = Probability.getNumerator() * TCycles; 1594 TUnpredCost /= Probability.getDenominator(); 1595 1596 uint32_t Comp = Probability.getDenominator() - Probability.getNumerator(); 1597 unsigned FUnpredCost = Comp * FCycles; 1598 FUnpredCost /= Probability.getDenominator(); 1599 1600 unsigned UnpredCost = TUnpredCost + FUnpredCost; 1601 UnpredCost += 1; // The branch itself 1602 UnpredCost += Subtarget.getMispredictionPenalty() / 10; 1603 1604 return (TCycles + FCycles + TExtra + FExtra) <= UnpredCost; 1605} 1606 1607bool 1608ARMBaseInstrInfo::isProfitableToUnpredicate(MachineBasicBlock &TMBB, 1609 MachineBasicBlock &FMBB) const { 1610 // Reduce false anti-dependencies to let Swift's out-of-order execution 1611 // engine do its thing. 1612 return Subtarget.isSwift(); 1613} 1614 1615/// getInstrPredicate - If instruction is predicated, returns its predicate 1616/// condition, otherwise returns AL. It also returns the condition code 1617/// register by reference. 1618ARMCC::CondCodes 1619llvm::getInstrPredicate(const MachineInstr *MI, unsigned &PredReg) { 1620 int PIdx = MI->findFirstPredOperandIdx(); 1621 if (PIdx == -1) { 1622 PredReg = 0; 1623 return ARMCC::AL; 1624 } 1625 1626 PredReg = MI->getOperand(PIdx+1).getReg(); 1627 return (ARMCC::CondCodes)MI->getOperand(PIdx).getImm(); 1628} 1629 1630 1631int llvm::getMatchingCondBranchOpcode(int Opc) { 1632 if (Opc == ARM::B) 1633 return ARM::Bcc; 1634 if (Opc == ARM::tB) 1635 return ARM::tBcc; 1636 if (Opc == ARM::t2B) 1637 return ARM::t2Bcc; 1638 1639 llvm_unreachable("Unknown unconditional branch opcode!"); 1640} 1641 1642/// commuteInstruction - Handle commutable instructions. 1643MachineInstr * 1644ARMBaseInstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const { 1645 switch (MI->getOpcode()) { 1646 case ARM::MOVCCr: 1647 case ARM::t2MOVCCr: { 1648 // MOVCC can be commuted by inverting the condition. 1649 unsigned PredReg = 0; 1650 ARMCC::CondCodes CC = getInstrPredicate(MI, PredReg); 1651 // MOVCC AL can't be inverted. Shouldn't happen. 1652 if (CC == ARMCC::AL || PredReg != ARM::CPSR) 1653 return NULL; 1654 MI = TargetInstrInfo::commuteInstruction(MI, NewMI); 1655 if (!MI) 1656 return NULL; 1657 // After swapping the MOVCC operands, also invert the condition. 1658 MI->getOperand(MI->findFirstPredOperandIdx()) 1659 .setImm(ARMCC::getOppositeCondition(CC)); 1660 return MI; 1661 } 1662 } 1663 return TargetInstrInfo::commuteInstruction(MI, NewMI); 1664} 1665 1666/// Identify instructions that can be folded into a MOVCC instruction, and 1667/// return the defining instruction. 1668static MachineInstr *canFoldIntoMOVCC(unsigned Reg, 1669 const MachineRegisterInfo &MRI, 1670 const TargetInstrInfo *TII) { 1671 if (!TargetRegisterInfo::isVirtualRegister(Reg)) 1672 return 0; 1673 if (!MRI.hasOneNonDBGUse(Reg)) 1674 return 0; 1675 MachineInstr *MI = MRI.getVRegDef(Reg); 1676 if (!MI) 1677 return 0; 1678 // MI is folded into the MOVCC by predicating it. 1679 if (!MI->isPredicable()) 1680 return 0; 1681 // Check if MI has any non-dead defs or physreg uses. This also detects 1682 // predicated instructions which will be reading CPSR. 1683 for (unsigned i = 1, e = MI->getNumOperands(); i != e; ++i) { 1684 const MachineOperand &MO = MI->getOperand(i); 1685 // Reject frame index operands, PEI can't handle the predicated pseudos. 1686 if (MO.isFI() || MO.isCPI() || MO.isJTI()) 1687 return 0; 1688 if (!MO.isReg()) 1689 continue; 1690 // MI can't have any tied operands, that would conflict with predication. 1691 if (MO.isTied()) 1692 return 0; 1693 if (TargetRegisterInfo::isPhysicalRegister(MO.getReg())) 1694 return 0; 1695 if (MO.isDef() && !MO.isDead()) 1696 return 0; 1697 } 1698 bool DontMoveAcrossStores = true; 1699 if (!MI->isSafeToMove(TII, /* AliasAnalysis = */ 0, DontMoveAcrossStores)) 1700 return 0; 1701 return MI; 1702} 1703 1704bool ARMBaseInstrInfo::analyzeSelect(const MachineInstr *MI, 1705 SmallVectorImpl<MachineOperand> &Cond, 1706 unsigned &TrueOp, unsigned &FalseOp, 1707 bool &Optimizable) const { 1708 assert((MI->getOpcode() == ARM::MOVCCr || MI->getOpcode() == ARM::t2MOVCCr) && 1709 "Unknown select instruction"); 1710 // MOVCC operands: 1711 // 0: Def. 1712 // 1: True use. 1713 // 2: False use. 1714 // 3: Condition code. 1715 // 4: CPSR use. 1716 TrueOp = 1; 1717 FalseOp = 2; 1718 Cond.push_back(MI->getOperand(3)); 1719 Cond.push_back(MI->getOperand(4)); 1720 // We can always fold a def. 1721 Optimizable = true; 1722 return false; 1723} 1724 1725MachineInstr *ARMBaseInstrInfo::optimizeSelect(MachineInstr *MI, 1726 bool PreferFalse) const { 1727 assert((MI->getOpcode() == ARM::MOVCCr || MI->getOpcode() == ARM::t2MOVCCr) && 1728 "Unknown select instruction"); 1729 MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo(); 1730 MachineInstr *DefMI = canFoldIntoMOVCC(MI->getOperand(2).getReg(), MRI, this); 1731 bool Invert = !DefMI; 1732 if (!DefMI) 1733 DefMI = canFoldIntoMOVCC(MI->getOperand(1).getReg(), MRI, this); 1734 if (!DefMI) 1735 return 0; 1736 1737 // Find new register class to use. 1738 MachineOperand FalseReg = MI->getOperand(Invert ? 2 : 1); 1739 unsigned DestReg = MI->getOperand(0).getReg(); 1740 const TargetRegisterClass *PreviousClass = MRI.getRegClass(FalseReg.getReg()); 1741 if (!MRI.constrainRegClass(DestReg, PreviousClass)) 1742 return 0; 1743 1744 // Create a new predicated version of DefMI. 1745 // Rfalse is the first use. 1746 MachineInstrBuilder NewMI = BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), 1747 DefMI->getDesc(), DestReg); 1748 1749 // Copy all the DefMI operands, excluding its (null) predicate. 1750 const MCInstrDesc &DefDesc = DefMI->getDesc(); 1751 for (unsigned i = 1, e = DefDesc.getNumOperands(); 1752 i != e && !DefDesc.OpInfo[i].isPredicate(); ++i) 1753 NewMI.addOperand(DefMI->getOperand(i)); 1754 1755 unsigned CondCode = MI->getOperand(3).getImm(); 1756 if (Invert) 1757 NewMI.addImm(ARMCC::getOppositeCondition(ARMCC::CondCodes(CondCode))); 1758 else 1759 NewMI.addImm(CondCode); 1760 NewMI.addOperand(MI->getOperand(4)); 1761 1762 // DefMI is not the -S version that sets CPSR, so add an optional %noreg. 1763 if (NewMI->hasOptionalDef()) 1764 AddDefaultCC(NewMI); 1765 1766 // The output register value when the predicate is false is an implicit 1767 // register operand tied to the first def. 1768 // The tie makes the register allocator ensure the FalseReg is allocated the 1769 // same register as operand 0. 1770 FalseReg.setImplicit(); 1771 NewMI.addOperand(FalseReg); 1772 NewMI->tieOperands(0, NewMI->getNumOperands() - 1); 1773 1774 // The caller will erase MI, but not DefMI. 1775 DefMI->eraseFromParent(); 1776 return NewMI; 1777} 1778 1779/// Map pseudo instructions that imply an 'S' bit onto real opcodes. Whether the 1780/// instruction is encoded with an 'S' bit is determined by the optional CPSR 1781/// def operand. 1782/// 1783/// This will go away once we can teach tblgen how to set the optional CPSR def 1784/// operand itself. 1785struct AddSubFlagsOpcodePair { 1786 uint16_t PseudoOpc; 1787 uint16_t MachineOpc; 1788}; 1789 1790static const AddSubFlagsOpcodePair AddSubFlagsOpcodeMap[] = { 1791 {ARM::ADDSri, ARM::ADDri}, 1792 {ARM::ADDSrr, ARM::ADDrr}, 1793 {ARM::ADDSrsi, ARM::ADDrsi}, 1794 {ARM::ADDSrsr, ARM::ADDrsr}, 1795 1796 {ARM::SUBSri, ARM::SUBri}, 1797 {ARM::SUBSrr, ARM::SUBrr}, 1798 {ARM::SUBSrsi, ARM::SUBrsi}, 1799 {ARM::SUBSrsr, ARM::SUBrsr}, 1800 1801 {ARM::RSBSri, ARM::RSBri}, 1802 {ARM::RSBSrsi, ARM::RSBrsi}, 1803 {ARM::RSBSrsr, ARM::RSBrsr}, 1804 1805 {ARM::t2ADDSri, ARM::t2ADDri}, 1806 {ARM::t2ADDSrr, ARM::t2ADDrr}, 1807 {ARM::t2ADDSrs, ARM::t2ADDrs}, 1808 1809 {ARM::t2SUBSri, ARM::t2SUBri}, 1810 {ARM::t2SUBSrr, ARM::t2SUBrr}, 1811 {ARM::t2SUBSrs, ARM::t2SUBrs}, 1812 1813 {ARM::t2RSBSri, ARM::t2RSBri}, 1814 {ARM::t2RSBSrs, ARM::t2RSBrs}, 1815}; 1816 1817unsigned llvm::convertAddSubFlagsOpcode(unsigned OldOpc) { 1818 for (unsigned i = 0, e = array_lengthof(AddSubFlagsOpcodeMap); i != e; ++i) 1819 if (OldOpc == AddSubFlagsOpcodeMap[i].PseudoOpc) 1820 return AddSubFlagsOpcodeMap[i].MachineOpc; 1821 return 0; 1822} 1823 1824void llvm::emitARMRegPlusImmediate(MachineBasicBlock &MBB, 1825 MachineBasicBlock::iterator &MBBI, DebugLoc dl, 1826 unsigned DestReg, unsigned BaseReg, int NumBytes, 1827 ARMCC::CondCodes Pred, unsigned PredReg, 1828 const ARMBaseInstrInfo &TII, unsigned MIFlags) { 1829 if (NumBytes == 0 && DestReg != BaseReg) { 1830 BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), DestReg) 1831 .addReg(BaseReg, RegState::Kill) 1832 .addImm((unsigned)Pred).addReg(PredReg).addReg(0) 1833 .setMIFlags(MIFlags); 1834 return; 1835 } 1836 1837 bool isSub = NumBytes < 0; 1838 if (isSub) NumBytes = -NumBytes; 1839 1840 while (NumBytes) { 1841 unsigned RotAmt = ARM_AM::getSOImmValRotate(NumBytes); 1842 unsigned ThisVal = NumBytes & ARM_AM::rotr32(0xFF, RotAmt); 1843 assert(ThisVal && "Didn't extract field correctly"); 1844 1845 // We will handle these bits from offset, clear them. 1846 NumBytes &= ~ThisVal; 1847 1848 assert(ARM_AM::getSOImmVal(ThisVal) != -1 && "Bit extraction didn't work?"); 1849 1850 // Build the new ADD / SUB. 1851 unsigned Opc = isSub ? ARM::SUBri : ARM::ADDri; 1852 BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg) 1853 .addReg(BaseReg, RegState::Kill).addImm(ThisVal) 1854 .addImm((unsigned)Pred).addReg(PredReg).addReg(0) 1855 .setMIFlags(MIFlags); 1856 BaseReg = DestReg; 1857 } 1858} 1859 1860bool llvm::tryFoldSPUpdateIntoPushPop(MachineFunction &MF, 1861 MachineInstr *MI, 1862 unsigned NumBytes) { 1863 // This optimisation potentially adds lots of load and store 1864 // micro-operations, it's only really a great benefit to code-size. 1865 if (!MF.getFunction()->hasFnAttribute(Attribute::MinSize)) 1866 return false; 1867 1868 // If only one register is pushed/popped, LLVM can use an LDR/STR 1869 // instead. We can't modify those so make sure we're dealing with an 1870 // instruction we understand. 1871 bool IsPop = isPopOpcode(MI->getOpcode()); 1872 bool IsPush = isPushOpcode(MI->getOpcode()); 1873 if (!IsPush && !IsPop) 1874 return false; 1875 1876 bool IsVFPPushPop = MI->getOpcode() == ARM::VSTMDDB_UPD || 1877 MI->getOpcode() == ARM::VLDMDIA_UPD; 1878 bool IsT1PushPop = MI->getOpcode() == ARM::tPUSH || 1879 MI->getOpcode() == ARM::tPOP || 1880 MI->getOpcode() == ARM::tPOP_RET; 1881 1882 assert((IsT1PushPop || (MI->getOperand(0).getReg() == ARM::SP && 1883 MI->getOperand(1).getReg() == ARM::SP)) && 1884 "trying to fold sp update into non-sp-updating push/pop"); 1885 1886 // The VFP push & pop act on D-registers, so we can only fold an adjustment 1887 // by a multiple of 8 bytes in correctly. Similarly rN is 4-bytes. Don't try 1888 // if this is violated. 1889 if (NumBytes % (IsVFPPushPop ? 8 : 4) != 0) 1890 return false; 1891 1892 // ARM and Thumb2 push/pop insts have explicit "sp, sp" operands (+ 1893 // pred) so the list starts at 4. Thumb1 starts after the predicate. 1894 int RegListIdx = IsT1PushPop ? 2 : 4; 1895 1896 // Calculate the space we'll need in terms of registers. 1897 unsigned FirstReg = MI->getOperand(RegListIdx).getReg(); 1898 unsigned RD0Reg, RegsNeeded; 1899 if (IsVFPPushPop) { 1900 RD0Reg = ARM::D0; 1901 RegsNeeded = NumBytes / 8; 1902 } else { 1903 RD0Reg = ARM::R0; 1904 RegsNeeded = NumBytes / 4; 1905 } 1906 1907 // We're going to have to strip all list operands off before 1908 // re-adding them since the order matters, so save the existing ones 1909 // for later. 1910 SmallVector<MachineOperand, 4> RegList; 1911 for (int i = MI->getNumOperands() - 1; i >= RegListIdx; --i) 1912 RegList.push_back(MI->getOperand(i)); 1913 1914 MachineBasicBlock *MBB = MI->getParent(); 1915 const TargetRegisterInfo *TRI = MF.getRegInfo().getTargetRegisterInfo(); 1916 1917 // Now try to find enough space in the reglist to allocate NumBytes. 1918 for (unsigned CurReg = FirstReg - 1; CurReg >= RD0Reg && RegsNeeded; 1919 --CurReg, --RegsNeeded) { 1920 if (!IsPop) { 1921 // Pushing any register is completely harmless, mark the 1922 // register involved as undef since we don't care about it in 1923 // the slightest. 1924 RegList.push_back(MachineOperand::CreateReg(CurReg, false, false, 1925 false, false, true)); 1926 continue; 1927 } 1928 1929 // However, we can only pop an extra register if it's not live. Otherwise we 1930 // might clobber a return value register. We assume that once we find a live 1931 // return register all lower ones will be too so there's no use proceeding. 1932 if (MBB->computeRegisterLiveness(TRI, CurReg, MI) != 1933 MachineBasicBlock::LQR_Dead) 1934 return false; 1935 1936 // Mark the unimportant registers as <def,dead> in the POP. 1937 RegList.push_back(MachineOperand::CreateReg(CurReg, true, false, true)); 1938 } 1939 1940 if (RegsNeeded > 0) 1941 return false; 1942 1943 // Finally we know we can profitably perform the optimisation so go 1944 // ahead: strip all existing registers off and add them back again 1945 // in the right order. 1946 for (int i = MI->getNumOperands() - 1; i >= RegListIdx; --i) 1947 MI->RemoveOperand(i); 1948 1949 // Add the complete list back in. 1950 MachineInstrBuilder MIB(MF, &*MI); 1951 for (int i = RegList.size() - 1; i >= 0; --i) 1952 MIB.addOperand(RegList[i]); 1953 1954 return true; 1955} 1956 1957bool llvm::rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx, 1958 unsigned FrameReg, int &Offset, 1959 const ARMBaseInstrInfo &TII) { 1960 unsigned Opcode = MI.getOpcode(); 1961 const MCInstrDesc &Desc = MI.getDesc(); 1962 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask); 1963 bool isSub = false; 1964 1965 // Memory operands in inline assembly always use AddrMode2. 1966 if (Opcode == ARM::INLINEASM) 1967 AddrMode = ARMII::AddrMode2; 1968 1969 if (Opcode == ARM::ADDri) { 1970 Offset += MI.getOperand(FrameRegIdx+1).getImm(); 1971 if (Offset == 0) { 1972 // Turn it into a move. 1973 MI.setDesc(TII.get(ARM::MOVr)); 1974 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false); 1975 MI.RemoveOperand(FrameRegIdx+1); 1976 Offset = 0; 1977 return true; 1978 } else if (Offset < 0) { 1979 Offset = -Offset; 1980 isSub = true; 1981 MI.setDesc(TII.get(ARM::SUBri)); 1982 } 1983 1984 // Common case: small offset, fits into instruction. 1985 if (ARM_AM::getSOImmVal(Offset) != -1) { 1986 // Replace the FrameIndex with sp / fp 1987 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false); 1988 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset); 1989 Offset = 0; 1990 return true; 1991 } 1992 1993 // Otherwise, pull as much of the immedidate into this ADDri/SUBri 1994 // as possible. 1995 unsigned RotAmt = ARM_AM::getSOImmValRotate(Offset); 1996 unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xFF, RotAmt); 1997 1998 // We will handle these bits from offset, clear them. 1999 Offset &= ~ThisImmVal; 2000 2001 // Get the properly encoded SOImmVal field. 2002 assert(ARM_AM::getSOImmVal(ThisImmVal) != -1 && 2003 "Bit extraction didn't work?"); 2004 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(ThisImmVal); 2005 } else { 2006 unsigned ImmIdx = 0; 2007 int InstrOffs = 0; 2008 unsigned NumBits = 0; 2009 unsigned Scale = 1; 2010 switch (AddrMode) { 2011 case ARMII::AddrMode_i12: { 2012 ImmIdx = FrameRegIdx + 1; 2013 InstrOffs = MI.getOperand(ImmIdx).getImm(); 2014 NumBits = 12; 2015 break; 2016 } 2017 case ARMII::AddrMode2: { 2018 ImmIdx = FrameRegIdx+2; 2019 InstrOffs = ARM_AM::getAM2Offset(MI.getOperand(ImmIdx).getImm()); 2020 if (ARM_AM::getAM2Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub) 2021 InstrOffs *= -1; 2022 NumBits = 12; 2023 break; 2024 } 2025 case ARMII::AddrMode3: { 2026 ImmIdx = FrameRegIdx+2; 2027 InstrOffs = ARM_AM::getAM3Offset(MI.getOperand(ImmIdx).getImm()); 2028 if (ARM_AM::getAM3Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub) 2029 InstrOffs *= -1; 2030 NumBits = 8; 2031 break; 2032 } 2033 case ARMII::AddrMode4: 2034 case ARMII::AddrMode6: 2035 // Can't fold any offset even if it's zero. 2036 return false; 2037 case ARMII::AddrMode5: { 2038 ImmIdx = FrameRegIdx+1; 2039 InstrOffs = ARM_AM::getAM5Offset(MI.getOperand(ImmIdx).getImm()); 2040 if (ARM_AM::getAM5Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub) 2041 InstrOffs *= -1; 2042 NumBits = 8; 2043 Scale = 4; 2044 break; 2045 } 2046 default: 2047 llvm_unreachable("Unsupported addressing mode!"); 2048 } 2049 2050 Offset += InstrOffs * Scale; 2051 assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!"); 2052 if (Offset < 0) { 2053 Offset = -Offset; 2054 isSub = true; 2055 } 2056 2057 // Attempt to fold address comp. if opcode has offset bits 2058 if (NumBits > 0) { 2059 // Common case: small offset, fits into instruction. 2060 MachineOperand &ImmOp = MI.getOperand(ImmIdx); 2061 int ImmedOffset = Offset / Scale; 2062 unsigned Mask = (1 << NumBits) - 1; 2063 if ((unsigned)Offset <= Mask * Scale) { 2064 // Replace the FrameIndex with sp 2065 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false); 2066 // FIXME: When addrmode2 goes away, this will simplify (like the 2067 // T2 version), as the LDR.i12 versions don't need the encoding 2068 // tricks for the offset value. 2069 if (isSub) { 2070 if (AddrMode == ARMII::AddrMode_i12) 2071 ImmedOffset = -ImmedOffset; 2072 else 2073 ImmedOffset |= 1 << NumBits; 2074 } 2075 ImmOp.ChangeToImmediate(ImmedOffset); 2076 Offset = 0; 2077 return true; 2078 } 2079 2080 // Otherwise, it didn't fit. Pull in what we can to simplify the immed. 2081 ImmedOffset = ImmedOffset & Mask; 2082 if (isSub) { 2083 if (AddrMode == ARMII::AddrMode_i12) 2084 ImmedOffset = -ImmedOffset; 2085 else 2086 ImmedOffset |= 1 << NumBits; 2087 } 2088 ImmOp.ChangeToImmediate(ImmedOffset); 2089 Offset &= ~(Mask*Scale); 2090 } 2091 } 2092 2093 Offset = (isSub) ? -Offset : Offset; 2094 return Offset == 0; 2095} 2096 2097/// analyzeCompare - For a comparison instruction, return the source registers 2098/// in SrcReg and SrcReg2 if having two register operands, and the value it 2099/// compares against in CmpValue. Return true if the comparison instruction 2100/// can be analyzed. 2101bool ARMBaseInstrInfo:: 2102analyzeCompare(const MachineInstr *MI, unsigned &SrcReg, unsigned &SrcReg2, 2103 int &CmpMask, int &CmpValue) const { 2104 switch (MI->getOpcode()) { 2105 default: break; 2106 case ARM::CMPri: 2107 case ARM::t2CMPri: 2108 SrcReg = MI->getOperand(0).getReg(); 2109 SrcReg2 = 0; 2110 CmpMask = ~0; 2111 CmpValue = MI->getOperand(1).getImm(); 2112 return true; 2113 case ARM::CMPrr: 2114 case ARM::t2CMPrr: 2115 SrcReg = MI->getOperand(0).getReg(); 2116 SrcReg2 = MI->getOperand(1).getReg(); 2117 CmpMask = ~0; 2118 CmpValue = 0; 2119 return true; 2120 case ARM::TSTri: 2121 case ARM::t2TSTri: 2122 SrcReg = MI->getOperand(0).getReg(); 2123 SrcReg2 = 0; 2124 CmpMask = MI->getOperand(1).getImm(); 2125 CmpValue = 0; 2126 return true; 2127 } 2128 2129 return false; 2130} 2131 2132/// isSuitableForMask - Identify a suitable 'and' instruction that 2133/// operates on the given source register and applies the same mask 2134/// as a 'tst' instruction. Provide a limited look-through for copies. 2135/// When successful, MI will hold the found instruction. 2136static bool isSuitableForMask(MachineInstr *&MI, unsigned SrcReg, 2137 int CmpMask, bool CommonUse) { 2138 switch (MI->getOpcode()) { 2139 case ARM::ANDri: 2140 case ARM::t2ANDri: 2141 if (CmpMask != MI->getOperand(2).getImm()) 2142 return false; 2143 if (SrcReg == MI->getOperand(CommonUse ? 1 : 0).getReg()) 2144 return true; 2145 break; 2146 case ARM::COPY: { 2147 // Walk down one instruction which is potentially an 'and'. 2148 const MachineInstr &Copy = *MI; 2149 MachineBasicBlock::iterator AND( 2150 llvm::next(MachineBasicBlock::iterator(MI))); 2151 if (AND == MI->getParent()->end()) return false; 2152 MI = AND; 2153 return isSuitableForMask(MI, Copy.getOperand(0).getReg(), 2154 CmpMask, true); 2155 } 2156 } 2157 2158 return false; 2159} 2160 2161/// getSwappedCondition - assume the flags are set by MI(a,b), return 2162/// the condition code if we modify the instructions such that flags are 2163/// set by MI(b,a). 2164inline static ARMCC::CondCodes getSwappedCondition(ARMCC::CondCodes CC) { 2165 switch (CC) { 2166 default: return ARMCC::AL; 2167 case ARMCC::EQ: return ARMCC::EQ; 2168 case ARMCC::NE: return ARMCC::NE; 2169 case ARMCC::HS: return ARMCC::LS; 2170 case ARMCC::LO: return ARMCC::HI; 2171 case ARMCC::HI: return ARMCC::LO; 2172 case ARMCC::LS: return ARMCC::HS; 2173 case ARMCC::GE: return ARMCC::LE; 2174 case ARMCC::LT: return ARMCC::GT; 2175 case ARMCC::GT: return ARMCC::LT; 2176 case ARMCC::LE: return ARMCC::GE; 2177 } 2178} 2179 2180/// isRedundantFlagInstr - check whether the first instruction, whose only 2181/// purpose is to update flags, can be made redundant. 2182/// CMPrr can be made redundant by SUBrr if the operands are the same. 2183/// CMPri can be made redundant by SUBri if the operands are the same. 2184/// This function can be extended later on. 2185inline static bool isRedundantFlagInstr(MachineInstr *CmpI, unsigned SrcReg, 2186 unsigned SrcReg2, int ImmValue, 2187 MachineInstr *OI) { 2188 if ((CmpI->getOpcode() == ARM::CMPrr || 2189 CmpI->getOpcode() == ARM::t2CMPrr) && 2190 (OI->getOpcode() == ARM::SUBrr || 2191 OI->getOpcode() == ARM::t2SUBrr) && 2192 ((OI->getOperand(1).getReg() == SrcReg && 2193 OI->getOperand(2).getReg() == SrcReg2) || 2194 (OI->getOperand(1).getReg() == SrcReg2 && 2195 OI->getOperand(2).getReg() == SrcReg))) 2196 return true; 2197 2198 if ((CmpI->getOpcode() == ARM::CMPri || 2199 CmpI->getOpcode() == ARM::t2CMPri) && 2200 (OI->getOpcode() == ARM::SUBri || 2201 OI->getOpcode() == ARM::t2SUBri) && 2202 OI->getOperand(1).getReg() == SrcReg && 2203 OI->getOperand(2).getImm() == ImmValue) 2204 return true; 2205 return false; 2206} 2207 2208/// optimizeCompareInstr - Convert the instruction supplying the argument to the 2209/// comparison into one that sets the zero bit in the flags register; 2210/// Remove a redundant Compare instruction if an earlier instruction can set the 2211/// flags in the same way as Compare. 2212/// E.g. SUBrr(r1,r2) and CMPrr(r1,r2). We also handle the case where two 2213/// operands are swapped: SUBrr(r1,r2) and CMPrr(r2,r1), by updating the 2214/// condition code of instructions which use the flags. 2215bool ARMBaseInstrInfo:: 2216optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, unsigned SrcReg2, 2217 int CmpMask, int CmpValue, 2218 const MachineRegisterInfo *MRI) const { 2219 // Get the unique definition of SrcReg. 2220 MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg); 2221 if (!MI) return false; 2222 2223 // Masked compares sometimes use the same register as the corresponding 'and'. 2224 if (CmpMask != ~0) { 2225 if (!isSuitableForMask(MI, SrcReg, CmpMask, false) || isPredicated(MI)) { 2226 MI = 0; 2227 for (MachineRegisterInfo::use_iterator UI = MRI->use_begin(SrcReg), 2228 UE = MRI->use_end(); UI != UE; ++UI) { 2229 if (UI->getParent() != CmpInstr->getParent()) continue; 2230 MachineInstr *PotentialAND = &*UI; 2231 if (!isSuitableForMask(PotentialAND, SrcReg, CmpMask, true) || 2232 isPredicated(PotentialAND)) 2233 continue; 2234 MI = PotentialAND; 2235 break; 2236 } 2237 if (!MI) return false; 2238 } 2239 } 2240 2241 // Get ready to iterate backward from CmpInstr. 2242 MachineBasicBlock::iterator I = CmpInstr, E = MI, 2243 B = CmpInstr->getParent()->begin(); 2244 2245 // Early exit if CmpInstr is at the beginning of the BB. 2246 if (I == B) return false; 2247 2248 // There are two possible candidates which can be changed to set CPSR: 2249 // One is MI, the other is a SUB instruction. 2250 // For CMPrr(r1,r2), we are looking for SUB(r1,r2) or SUB(r2,r1). 2251 // For CMPri(r1, CmpValue), we are looking for SUBri(r1, CmpValue). 2252 MachineInstr *Sub = NULL; 2253 if (SrcReg2 != 0) 2254 // MI is not a candidate for CMPrr. 2255 MI = NULL; 2256 else if (MI->getParent() != CmpInstr->getParent() || CmpValue != 0) { 2257 // Conservatively refuse to convert an instruction which isn't in the same 2258 // BB as the comparison. 2259 // For CMPri, we need to check Sub, thus we can't return here. 2260 if (CmpInstr->getOpcode() == ARM::CMPri || 2261 CmpInstr->getOpcode() == ARM::t2CMPri) 2262 MI = NULL; 2263 else 2264 return false; 2265 } 2266 2267 // Check that CPSR isn't set between the comparison instruction and the one we 2268 // want to change. At the same time, search for Sub. 2269 const TargetRegisterInfo *TRI = &getRegisterInfo(); 2270 --I; 2271 for (; I != E; --I) { 2272 const MachineInstr &Instr = *I; 2273 2274 if (Instr.modifiesRegister(ARM::CPSR, TRI) || 2275 Instr.readsRegister(ARM::CPSR, TRI)) 2276 // This instruction modifies or uses CPSR after the one we want to 2277 // change. We can't do this transformation. 2278 return false; 2279 2280 // Check whether CmpInstr can be made redundant by the current instruction. 2281 if (isRedundantFlagInstr(CmpInstr, SrcReg, SrcReg2, CmpValue, &*I)) { 2282 Sub = &*I; 2283 break; 2284 } 2285 2286 if (I == B) 2287 // The 'and' is below the comparison instruction. 2288 return false; 2289 } 2290 2291 // Return false if no candidates exist. 2292 if (!MI && !Sub) 2293 return false; 2294 2295 // The single candidate is called MI. 2296 if (!MI) MI = Sub; 2297 2298 // We can't use a predicated instruction - it doesn't always write the flags. 2299 if (isPredicated(MI)) 2300 return false; 2301 2302 switch (MI->getOpcode()) { 2303 default: break; 2304 case ARM::RSBrr: 2305 case ARM::RSBri: 2306 case ARM::RSCrr: 2307 case ARM::RSCri: 2308 case ARM::ADDrr: 2309 case ARM::ADDri: 2310 case ARM::ADCrr: 2311 case ARM::ADCri: 2312 case ARM::SUBrr: 2313 case ARM::SUBri: 2314 case ARM::SBCrr: 2315 case ARM::SBCri: 2316 case ARM::t2RSBri: 2317 case ARM::t2ADDrr: 2318 case ARM::t2ADDri: 2319 case ARM::t2ADCrr: 2320 case ARM::t2ADCri: 2321 case ARM::t2SUBrr: 2322 case ARM::t2SUBri: 2323 case ARM::t2SBCrr: 2324 case ARM::t2SBCri: 2325 case ARM::ANDrr: 2326 case ARM::ANDri: 2327 case ARM::t2ANDrr: 2328 case ARM::t2ANDri: 2329 case ARM::ORRrr: 2330 case ARM::ORRri: 2331 case ARM::t2ORRrr: 2332 case ARM::t2ORRri: 2333 case ARM::EORrr: 2334 case ARM::EORri: 2335 case ARM::t2EORrr: 2336 case ARM::t2EORri: { 2337 // Scan forward for the use of CPSR 2338 // When checking against MI: if it's a conditional code requires 2339 // checking of V bit, then this is not safe to do. 2340 // It is safe to remove CmpInstr if CPSR is redefined or killed. 2341 // If we are done with the basic block, we need to check whether CPSR is 2342 // live-out. 2343 SmallVector<std::pair<MachineOperand*, ARMCC::CondCodes>, 4> 2344 OperandsToUpdate; 2345 bool isSafe = false; 2346 I = CmpInstr; 2347 E = CmpInstr->getParent()->end(); 2348 while (!isSafe && ++I != E) { 2349 const MachineInstr &Instr = *I; 2350 for (unsigned IO = 0, EO = Instr.getNumOperands(); 2351 !isSafe && IO != EO; ++IO) { 2352 const MachineOperand &MO = Instr.getOperand(IO); 2353 if (MO.isRegMask() && MO.clobbersPhysReg(ARM::CPSR)) { 2354 isSafe = true; 2355 break; 2356 } 2357 if (!MO.isReg() || MO.getReg() != ARM::CPSR) 2358 continue; 2359 if (MO.isDef()) { 2360 isSafe = true; 2361 break; 2362 } 2363 // Condition code is after the operand before CPSR. 2364 ARMCC::CondCodes CC = (ARMCC::CondCodes)Instr.getOperand(IO-1).getImm(); 2365 if (Sub) { 2366 ARMCC::CondCodes NewCC = getSwappedCondition(CC); 2367 if (NewCC == ARMCC::AL) 2368 return false; 2369 // If we have SUB(r1, r2) and CMP(r2, r1), the condition code based 2370 // on CMP needs to be updated to be based on SUB. 2371 // Push the condition code operands to OperandsToUpdate. 2372 // If it is safe to remove CmpInstr, the condition code of these 2373 // operands will be modified. 2374 if (SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 && 2375 Sub->getOperand(2).getReg() == SrcReg) 2376 OperandsToUpdate.push_back(std::make_pair(&((*I).getOperand(IO-1)), 2377 NewCC)); 2378 } 2379 else 2380 switch (CC) { 2381 default: 2382 // CPSR can be used multiple times, we should continue. 2383 break; 2384 case ARMCC::VS: 2385 case ARMCC::VC: 2386 case ARMCC::GE: 2387 case ARMCC::LT: 2388 case ARMCC::GT: 2389 case ARMCC::LE: 2390 return false; 2391 } 2392 } 2393 } 2394 2395 // If CPSR is not killed nor re-defined, we should check whether it is 2396 // live-out. If it is live-out, do not optimize. 2397 if (!isSafe) { 2398 MachineBasicBlock *MBB = CmpInstr->getParent(); 2399 for (MachineBasicBlock::succ_iterator SI = MBB->succ_begin(), 2400 SE = MBB->succ_end(); SI != SE; ++SI) 2401 if ((*SI)->isLiveIn(ARM::CPSR)) 2402 return false; 2403 } 2404 2405 // Toggle the optional operand to CPSR. 2406 MI->getOperand(5).setReg(ARM::CPSR); 2407 MI->getOperand(5).setIsDef(true); 2408 assert(!isPredicated(MI) && "Can't use flags from predicated instruction"); 2409 CmpInstr->eraseFromParent(); 2410 2411 // Modify the condition code of operands in OperandsToUpdate. 2412 // Since we have SUB(r1, r2) and CMP(r2, r1), the condition code needs to 2413 // be changed from r2 > r1 to r1 < r2, from r2 < r1 to r1 > r2, etc. 2414 for (unsigned i = 0, e = OperandsToUpdate.size(); i < e; i++) 2415 OperandsToUpdate[i].first->setImm(OperandsToUpdate[i].second); 2416 return true; 2417 } 2418 } 2419 2420 return false; 2421} 2422 2423bool ARMBaseInstrInfo::FoldImmediate(MachineInstr *UseMI, 2424 MachineInstr *DefMI, unsigned Reg, 2425 MachineRegisterInfo *MRI) const { 2426 // Fold large immediates into add, sub, or, xor. 2427 unsigned DefOpc = DefMI->getOpcode(); 2428 if (DefOpc != ARM::t2MOVi32imm && DefOpc != ARM::MOVi32imm) 2429 return false; 2430 if (!DefMI->getOperand(1).isImm()) 2431 // Could be t2MOVi32imm <ga:xx> 2432 return false; 2433 2434 if (!MRI->hasOneNonDBGUse(Reg)) 2435 return false; 2436 2437 const MCInstrDesc &DefMCID = DefMI->getDesc(); 2438 if (DefMCID.hasOptionalDef()) { 2439 unsigned NumOps = DefMCID.getNumOperands(); 2440 const MachineOperand &MO = DefMI->getOperand(NumOps-1); 2441 if (MO.getReg() == ARM::CPSR && !MO.isDead()) 2442 // If DefMI defines CPSR and it is not dead, it's obviously not safe 2443 // to delete DefMI. 2444 return false; 2445 } 2446 2447 const MCInstrDesc &UseMCID = UseMI->getDesc(); 2448 if (UseMCID.hasOptionalDef()) { 2449 unsigned NumOps = UseMCID.getNumOperands(); 2450 if (UseMI->getOperand(NumOps-1).getReg() == ARM::CPSR) 2451 // If the instruction sets the flag, do not attempt this optimization 2452 // since it may change the semantics of the code. 2453 return false; 2454 } 2455 2456 unsigned UseOpc = UseMI->getOpcode(); 2457 unsigned NewUseOpc = 0; 2458 uint32_t ImmVal = (uint32_t)DefMI->getOperand(1).getImm(); 2459 uint32_t SOImmValV1 = 0, SOImmValV2 = 0; 2460 bool Commute = false; 2461 switch (UseOpc) { 2462 default: return false; 2463 case ARM::SUBrr: 2464 case ARM::ADDrr: 2465 case ARM::ORRrr: 2466 case ARM::EORrr: 2467 case ARM::t2SUBrr: 2468 case ARM::t2ADDrr: 2469 case ARM::t2ORRrr: 2470 case ARM::t2EORrr: { 2471 Commute = UseMI->getOperand(2).getReg() != Reg; 2472 switch (UseOpc) { 2473 default: break; 2474 case ARM::SUBrr: { 2475 if (Commute) 2476 return false; 2477 ImmVal = -ImmVal; 2478 NewUseOpc = ARM::SUBri; 2479 // Fallthrough 2480 } 2481 case ARM::ADDrr: 2482 case ARM::ORRrr: 2483 case ARM::EORrr: { 2484 if (!ARM_AM::isSOImmTwoPartVal(ImmVal)) 2485 return false; 2486 SOImmValV1 = (uint32_t)ARM_AM::getSOImmTwoPartFirst(ImmVal); 2487 SOImmValV2 = (uint32_t)ARM_AM::getSOImmTwoPartSecond(ImmVal); 2488 switch (UseOpc) { 2489 default: break; 2490 case ARM::ADDrr: NewUseOpc = ARM::ADDri; break; 2491 case ARM::ORRrr: NewUseOpc = ARM::ORRri; break; 2492 case ARM::EORrr: NewUseOpc = ARM::EORri; break; 2493 } 2494 break; 2495 } 2496 case ARM::t2SUBrr: { 2497 if (Commute) 2498 return false; 2499 ImmVal = -ImmVal; 2500 NewUseOpc = ARM::t2SUBri; 2501 // Fallthrough 2502 } 2503 case ARM::t2ADDrr: 2504 case ARM::t2ORRrr: 2505 case ARM::t2EORrr: { 2506 if (!ARM_AM::isT2SOImmTwoPartVal(ImmVal)) 2507 return false; 2508 SOImmValV1 = (uint32_t)ARM_AM::getT2SOImmTwoPartFirst(ImmVal); 2509 SOImmValV2 = (uint32_t)ARM_AM::getT2SOImmTwoPartSecond(ImmVal); 2510 switch (UseOpc) { 2511 default: break; 2512 case ARM::t2ADDrr: NewUseOpc = ARM::t2ADDri; break; 2513 case ARM::t2ORRrr: NewUseOpc = ARM::t2ORRri; break; 2514 case ARM::t2EORrr: NewUseOpc = ARM::t2EORri; break; 2515 } 2516 break; 2517 } 2518 } 2519 } 2520 } 2521 2522 unsigned OpIdx = Commute ? 2 : 1; 2523 unsigned Reg1 = UseMI->getOperand(OpIdx).getReg(); 2524 bool isKill = UseMI->getOperand(OpIdx).isKill(); 2525 unsigned NewReg = MRI->createVirtualRegister(MRI->getRegClass(Reg)); 2526 AddDefaultCC(AddDefaultPred(BuildMI(*UseMI->getParent(), 2527 UseMI, UseMI->getDebugLoc(), 2528 get(NewUseOpc), NewReg) 2529 .addReg(Reg1, getKillRegState(isKill)) 2530 .addImm(SOImmValV1))); 2531 UseMI->setDesc(get(NewUseOpc)); 2532 UseMI->getOperand(1).setReg(NewReg); 2533 UseMI->getOperand(1).setIsKill(); 2534 UseMI->getOperand(2).ChangeToImmediate(SOImmValV2); 2535 DefMI->eraseFromParent(); 2536 return true; 2537} 2538 2539static unsigned getNumMicroOpsSwiftLdSt(const InstrItineraryData *ItinData, 2540 const MachineInstr *MI) { 2541 switch (MI->getOpcode()) { 2542 default: { 2543 const MCInstrDesc &Desc = MI->getDesc(); 2544 int UOps = ItinData->getNumMicroOps(Desc.getSchedClass()); 2545 assert(UOps >= 0 && "bad # UOps"); 2546 return UOps; 2547 } 2548 2549 case ARM::LDRrs: 2550 case ARM::LDRBrs: 2551 case ARM::STRrs: 2552 case ARM::STRBrs: { 2553 unsigned ShOpVal = MI->getOperand(3).getImm(); 2554 bool isSub = ARM_AM::getAM2Op(ShOpVal) == ARM_AM::sub; 2555 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal); 2556 if (!isSub && 2557 (ShImm == 0 || 2558 ((ShImm == 1 || ShImm == 2 || ShImm == 3) && 2559 ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl))) 2560 return 1; 2561 return 2; 2562 } 2563 2564 case ARM::LDRH: 2565 case ARM::STRH: { 2566 if (!MI->getOperand(2).getReg()) 2567 return 1; 2568 2569 unsigned ShOpVal = MI->getOperand(3).getImm(); 2570 bool isSub = ARM_AM::getAM2Op(ShOpVal) == ARM_AM::sub; 2571 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal); 2572 if (!isSub && 2573 (ShImm == 0 || 2574 ((ShImm == 1 || ShImm == 2 || ShImm == 3) && 2575 ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl))) 2576 return 1; 2577 return 2; 2578 } 2579 2580 case ARM::LDRSB: 2581 case ARM::LDRSH: 2582 return (ARM_AM::getAM3Op(MI->getOperand(3).getImm()) == ARM_AM::sub) ? 3:2; 2583 2584 case ARM::LDRSB_POST: 2585 case ARM::LDRSH_POST: { 2586 unsigned Rt = MI->getOperand(0).getReg(); 2587 unsigned Rm = MI->getOperand(3).getReg(); 2588 return (Rt == Rm) ? 4 : 3; 2589 } 2590 2591 case ARM::LDR_PRE_REG: 2592 case ARM::LDRB_PRE_REG: { 2593 unsigned Rt = MI->getOperand(0).getReg(); 2594 unsigned Rm = MI->getOperand(3).getReg(); 2595 if (Rt == Rm) 2596 return 3; 2597 unsigned ShOpVal = MI->getOperand(4).getImm(); 2598 bool isSub = ARM_AM::getAM2Op(ShOpVal) == ARM_AM::sub; 2599 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal); 2600 if (!isSub && 2601 (ShImm == 0 || 2602 ((ShImm == 1 || ShImm == 2 || ShImm == 3) && 2603 ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl))) 2604 return 2; 2605 return 3; 2606 } 2607 2608 case ARM::STR_PRE_REG: 2609 case ARM::STRB_PRE_REG: { 2610 unsigned ShOpVal = MI->getOperand(4).getImm(); 2611 bool isSub = ARM_AM::getAM2Op(ShOpVal) == ARM_AM::sub; 2612 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal); 2613 if (!isSub && 2614 (ShImm == 0 || 2615 ((ShImm == 1 || ShImm == 2 || ShImm == 3) && 2616 ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl))) 2617 return 2; 2618 return 3; 2619 } 2620 2621 case ARM::LDRH_PRE: 2622 case ARM::STRH_PRE: { 2623 unsigned Rt = MI->getOperand(0).getReg(); 2624 unsigned Rm = MI->getOperand(3).getReg(); 2625 if (!Rm) 2626 return 2; 2627 if (Rt == Rm) 2628 return 3; 2629 return (ARM_AM::getAM3Op(MI->getOperand(4).getImm()) == ARM_AM::sub) 2630 ? 3 : 2; 2631 } 2632 2633 case ARM::LDR_POST_REG: 2634 case ARM::LDRB_POST_REG: 2635 case ARM::LDRH_POST: { 2636 unsigned Rt = MI->getOperand(0).getReg(); 2637 unsigned Rm = MI->getOperand(3).getReg(); 2638 return (Rt == Rm) ? 3 : 2; 2639 } 2640 2641 case ARM::LDR_PRE_IMM: 2642 case ARM::LDRB_PRE_IMM: 2643 case ARM::LDR_POST_IMM: 2644 case ARM::LDRB_POST_IMM: 2645 case ARM::STRB_POST_IMM: 2646 case ARM::STRB_POST_REG: 2647 case ARM::STRB_PRE_IMM: 2648 case ARM::STRH_POST: 2649 case ARM::STR_POST_IMM: 2650 case ARM::STR_POST_REG: 2651 case ARM::STR_PRE_IMM: 2652 return 2; 2653 2654 case ARM::LDRSB_PRE: 2655 case ARM::LDRSH_PRE: { 2656 unsigned Rm = MI->getOperand(3).getReg(); 2657 if (Rm == 0) 2658 return 3; 2659 unsigned Rt = MI->getOperand(0).getReg(); 2660 if (Rt == Rm) 2661 return 4; 2662 unsigned ShOpVal = MI->getOperand(4).getImm(); 2663 bool isSub = ARM_AM::getAM2Op(ShOpVal) == ARM_AM::sub; 2664 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal); 2665 if (!isSub && 2666 (ShImm == 0 || 2667 ((ShImm == 1 || ShImm == 2 || ShImm == 3) && 2668 ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl))) 2669 return 3; 2670 return 4; 2671 } 2672 2673 case ARM::LDRD: { 2674 unsigned Rt = MI->getOperand(0).getReg(); 2675 unsigned Rn = MI->getOperand(2).getReg(); 2676 unsigned Rm = MI->getOperand(3).getReg(); 2677 if (Rm) 2678 return (ARM_AM::getAM3Op(MI->getOperand(4).getImm()) == ARM_AM::sub) ?4:3; 2679 return (Rt == Rn) ? 3 : 2; 2680 } 2681 2682 case ARM::STRD: { 2683 unsigned Rm = MI->getOperand(3).getReg(); 2684 if (Rm) 2685 return (ARM_AM::getAM3Op(MI->getOperand(4).getImm()) == ARM_AM::sub) ?4:3; 2686 return 2; 2687 } 2688 2689 case ARM::LDRD_POST: 2690 case ARM::t2LDRD_POST: 2691 return 3; 2692 2693 case ARM::STRD_POST: 2694 case ARM::t2STRD_POST: 2695 return 4; 2696 2697 case ARM::LDRD_PRE: { 2698 unsigned Rt = MI->getOperand(0).getReg(); 2699 unsigned Rn = MI->getOperand(3).getReg(); 2700 unsigned Rm = MI->getOperand(4).getReg(); 2701 if (Rm) 2702 return (ARM_AM::getAM3Op(MI->getOperand(5).getImm()) == ARM_AM::sub) ?5:4; 2703 return (Rt == Rn) ? 4 : 3; 2704 } 2705 2706 case ARM::t2LDRD_PRE: { 2707 unsigned Rt = MI->getOperand(0).getReg(); 2708 unsigned Rn = MI->getOperand(3).getReg(); 2709 return (Rt == Rn) ? 4 : 3; 2710 } 2711 2712 case ARM::STRD_PRE: { 2713 unsigned Rm = MI->getOperand(4).getReg(); 2714 if (Rm) 2715 return (ARM_AM::getAM3Op(MI->getOperand(5).getImm()) == ARM_AM::sub) ?5:4; 2716 return 3; 2717 } 2718 2719 case ARM::t2STRD_PRE: 2720 return 3; 2721 2722 case ARM::t2LDR_POST: 2723 case ARM::t2LDRB_POST: 2724 case ARM::t2LDRB_PRE: 2725 case ARM::t2LDRSBi12: 2726 case ARM::t2LDRSBi8: 2727 case ARM::t2LDRSBpci: 2728 case ARM::t2LDRSBs: 2729 case ARM::t2LDRH_POST: 2730 case ARM::t2LDRH_PRE: 2731 case ARM::t2LDRSBT: 2732 case ARM::t2LDRSB_POST: 2733 case ARM::t2LDRSB_PRE: 2734 case ARM::t2LDRSH_POST: 2735 case ARM::t2LDRSH_PRE: 2736 case ARM::t2LDRSHi12: 2737 case ARM::t2LDRSHi8: 2738 case ARM::t2LDRSHpci: 2739 case ARM::t2LDRSHs: 2740 return 2; 2741 2742 case ARM::t2LDRDi8: { 2743 unsigned Rt = MI->getOperand(0).getReg(); 2744 unsigned Rn = MI->getOperand(2).getReg(); 2745 return (Rt == Rn) ? 3 : 2; 2746 } 2747 2748 case ARM::t2STRB_POST: 2749 case ARM::t2STRB_PRE: 2750 case ARM::t2STRBs: 2751 case ARM::t2STRDi8: 2752 case ARM::t2STRH_POST: 2753 case ARM::t2STRH_PRE: 2754 case ARM::t2STRHs: 2755 case ARM::t2STR_POST: 2756 case ARM::t2STR_PRE: 2757 case ARM::t2STRs: 2758 return 2; 2759 } 2760} 2761 2762// Return the number of 32-bit words loaded by LDM or stored by STM. If this 2763// can't be easily determined return 0 (missing MachineMemOperand). 2764// 2765// FIXME: The current MachineInstr design does not support relying on machine 2766// mem operands to determine the width of a memory access. Instead, we expect 2767// the target to provide this information based on the instruction opcode and 2768// operands. However, using MachineMemOperand is a the best solution now for 2769// two reasons: 2770// 2771// 1) getNumMicroOps tries to infer LDM memory width from the total number of MI 2772// operands. This is much more dangerous than using the MachineMemOperand 2773// sizes because CodeGen passes can insert/remove optional machine operands. In 2774// fact, it's totally incorrect for preRA passes and appears to be wrong for 2775// postRA passes as well. 2776// 2777// 2) getNumLDMAddresses is only used by the scheduling machine model and any 2778// machine model that calls this should handle the unknown (zero size) case. 2779// 2780// Long term, we should require a target hook that verifies MachineMemOperand 2781// sizes during MC lowering. That target hook should be local to MC lowering 2782// because we can't ensure that it is aware of other MI forms. Doing this will 2783// ensure that MachineMemOperands are correctly propagated through all passes. 2784unsigned ARMBaseInstrInfo::getNumLDMAddresses(const MachineInstr *MI) const { 2785 unsigned Size = 0; 2786 for (MachineInstr::mmo_iterator I = MI->memoperands_begin(), 2787 E = MI->memoperands_end(); I != E; ++I) { 2788 Size += (*I)->getSize(); 2789 } 2790 return Size / 4; 2791} 2792 2793unsigned 2794ARMBaseInstrInfo::getNumMicroOps(const InstrItineraryData *ItinData, 2795 const MachineInstr *MI) const { 2796 if (!ItinData || ItinData->isEmpty()) 2797 return 1; 2798 2799 const MCInstrDesc &Desc = MI->getDesc(); 2800 unsigned Class = Desc.getSchedClass(); 2801 int ItinUOps = ItinData->getNumMicroOps(Class); 2802 if (ItinUOps >= 0) { 2803 if (Subtarget.isSwift() && (Desc.mayLoad() || Desc.mayStore())) 2804 return getNumMicroOpsSwiftLdSt(ItinData, MI); 2805 2806 return ItinUOps; 2807 } 2808 2809 unsigned Opc = MI->getOpcode(); 2810 switch (Opc) { 2811 default: 2812 llvm_unreachable("Unexpected multi-uops instruction!"); 2813 case ARM::VLDMQIA: 2814 case ARM::VSTMQIA: 2815 return 2; 2816 2817 // The number of uOps for load / store multiple are determined by the number 2818 // registers. 2819 // 2820 // On Cortex-A8, each pair of register loads / stores can be scheduled on the 2821 // same cycle. The scheduling for the first load / store must be done 2822 // separately by assuming the address is not 64-bit aligned. 2823 // 2824 // On Cortex-A9, the formula is simply (#reg / 2) + (#reg % 2). If the address 2825 // is not 64-bit aligned, then AGU would take an extra cycle. For VFP / NEON 2826 // load / store multiple, the formula is (#reg / 2) + (#reg % 2) + 1. 2827 case ARM::VLDMDIA: 2828 case ARM::VLDMDIA_UPD: 2829 case ARM::VLDMDDB_UPD: 2830 case ARM::VLDMSIA: 2831 case ARM::VLDMSIA_UPD: 2832 case ARM::VLDMSDB_UPD: 2833 case ARM::VSTMDIA: 2834 case ARM::VSTMDIA_UPD: 2835 case ARM::VSTMDDB_UPD: 2836 case ARM::VSTMSIA: 2837 case ARM::VSTMSIA_UPD: 2838 case ARM::VSTMSDB_UPD: { 2839 unsigned NumRegs = MI->getNumOperands() - Desc.getNumOperands(); 2840 return (NumRegs / 2) + (NumRegs % 2) + 1; 2841 } 2842 2843 case ARM::LDMIA_RET: 2844 case ARM::LDMIA: 2845 case ARM::LDMDA: 2846 case ARM::LDMDB: 2847 case ARM::LDMIB: 2848 case ARM::LDMIA_UPD: 2849 case ARM::LDMDA_UPD: 2850 case ARM::LDMDB_UPD: 2851 case ARM::LDMIB_UPD: 2852 case ARM::STMIA: 2853 case ARM::STMDA: 2854 case ARM::STMDB: 2855 case ARM::STMIB: 2856 case ARM::STMIA_UPD: 2857 case ARM::STMDA_UPD: 2858 case ARM::STMDB_UPD: 2859 case ARM::STMIB_UPD: 2860 case ARM::tLDMIA: 2861 case ARM::tLDMIA_UPD: 2862 case ARM::tSTMIA_UPD: 2863 case ARM::tPOP_RET: 2864 case ARM::tPOP: 2865 case ARM::tPUSH: 2866 case ARM::t2LDMIA_RET: 2867 case ARM::t2LDMIA: 2868 case ARM::t2LDMDB: 2869 case ARM::t2LDMIA_UPD: 2870 case ARM::t2LDMDB_UPD: 2871 case ARM::t2STMIA: 2872 case ARM::t2STMDB: 2873 case ARM::t2STMIA_UPD: 2874 case ARM::t2STMDB_UPD: { 2875 unsigned NumRegs = MI->getNumOperands() - Desc.getNumOperands() + 1; 2876 if (Subtarget.isSwift()) { 2877 int UOps = 1 + NumRegs; // One for address computation, one for each ld / st. 2878 switch (Opc) { 2879 default: break; 2880 case ARM::VLDMDIA_UPD: 2881 case ARM::VLDMDDB_UPD: 2882 case ARM::VLDMSIA_UPD: 2883 case ARM::VLDMSDB_UPD: 2884 case ARM::VSTMDIA_UPD: 2885 case ARM::VSTMDDB_UPD: 2886 case ARM::VSTMSIA_UPD: 2887 case ARM::VSTMSDB_UPD: 2888 case ARM::LDMIA_UPD: 2889 case ARM::LDMDA_UPD: 2890 case ARM::LDMDB_UPD: 2891 case ARM::LDMIB_UPD: 2892 case ARM::STMIA_UPD: 2893 case ARM::STMDA_UPD: 2894 case ARM::STMDB_UPD: 2895 case ARM::STMIB_UPD: 2896 case ARM::tLDMIA_UPD: 2897 case ARM::tSTMIA_UPD: 2898 case ARM::t2LDMIA_UPD: 2899 case ARM::t2LDMDB_UPD: 2900 case ARM::t2STMIA_UPD: 2901 case ARM::t2STMDB_UPD: 2902 ++UOps; // One for base register writeback. 2903 break; 2904 case ARM::LDMIA_RET: 2905 case ARM::tPOP_RET: 2906 case ARM::t2LDMIA_RET: 2907 UOps += 2; // One for base reg wb, one for write to pc. 2908 break; 2909 } 2910 return UOps; 2911 } else if (Subtarget.isCortexA8()) { 2912 if (NumRegs < 4) 2913 return 2; 2914 // 4 registers would be issued: 2, 2. 2915 // 5 registers would be issued: 2, 2, 1. 2916 int A8UOps = (NumRegs / 2); 2917 if (NumRegs % 2) 2918 ++A8UOps; 2919 return A8UOps; 2920 } else if (Subtarget.isLikeA9() || Subtarget.isSwift()) { 2921 int A9UOps = (NumRegs / 2); 2922 // If there are odd number of registers or if it's not 64-bit aligned, 2923 // then it takes an extra AGU (Address Generation Unit) cycle. 2924 if ((NumRegs % 2) || 2925 !MI->hasOneMemOperand() || 2926 (*MI->memoperands_begin())->getAlignment() < 8) 2927 ++A9UOps; 2928 return A9UOps; 2929 } else { 2930 // Assume the worst. 2931 return NumRegs; 2932 } 2933 } 2934 } 2935} 2936 2937int 2938ARMBaseInstrInfo::getVLDMDefCycle(const InstrItineraryData *ItinData, 2939 const MCInstrDesc &DefMCID, 2940 unsigned DefClass, 2941 unsigned DefIdx, unsigned DefAlign) const { 2942 int RegNo = (int)(DefIdx+1) - DefMCID.getNumOperands() + 1; 2943 if (RegNo <= 0) 2944 // Def is the address writeback. 2945 return ItinData->getOperandCycle(DefClass, DefIdx); 2946 2947 int DefCycle; 2948 if (Subtarget.isCortexA8()) { 2949 // (regno / 2) + (regno % 2) + 1 2950 DefCycle = RegNo / 2 + 1; 2951 if (RegNo % 2) 2952 ++DefCycle; 2953 } else if (Subtarget.isLikeA9() || Subtarget.isSwift()) { 2954 DefCycle = RegNo; 2955 bool isSLoad = false; 2956 2957 switch (DefMCID.getOpcode()) { 2958 default: break; 2959 case ARM::VLDMSIA: 2960 case ARM::VLDMSIA_UPD: 2961 case ARM::VLDMSDB_UPD: 2962 isSLoad = true; 2963 break; 2964 } 2965 2966 // If there are odd number of 'S' registers or if it's not 64-bit aligned, 2967 // then it takes an extra cycle. 2968 if ((isSLoad && (RegNo % 2)) || DefAlign < 8) 2969 ++DefCycle; 2970 } else { 2971 // Assume the worst. 2972 DefCycle = RegNo + 2; 2973 } 2974 2975 return DefCycle; 2976} 2977 2978int 2979ARMBaseInstrInfo::getLDMDefCycle(const InstrItineraryData *ItinData, 2980 const MCInstrDesc &DefMCID, 2981 unsigned DefClass, 2982 unsigned DefIdx, unsigned DefAlign) const { 2983 int RegNo = (int)(DefIdx+1) - DefMCID.getNumOperands() + 1; 2984 if (RegNo <= 0) 2985 // Def is the address writeback. 2986 return ItinData->getOperandCycle(DefClass, DefIdx); 2987 2988 int DefCycle; 2989 if (Subtarget.isCortexA8()) { 2990 // 4 registers would be issued: 1, 2, 1. 2991 // 5 registers would be issued: 1, 2, 2. 2992 DefCycle = RegNo / 2; 2993 if (DefCycle < 1) 2994 DefCycle = 1; 2995 // Result latency is issue cycle + 2: E2. 2996 DefCycle += 2; 2997 } else if (Subtarget.isLikeA9() || Subtarget.isSwift()) { 2998 DefCycle = (RegNo / 2); 2999 // If there are odd number of registers or if it's not 64-bit aligned, 3000 // then it takes an extra AGU (Address Generation Unit) cycle. 3001 if ((RegNo % 2) || DefAlign < 8) 3002 ++DefCycle; 3003 // Result latency is AGU cycles + 2. 3004 DefCycle += 2; 3005 } else { 3006 // Assume the worst. 3007 DefCycle = RegNo + 2; 3008 } 3009 3010 return DefCycle; 3011} 3012 3013int 3014ARMBaseInstrInfo::getVSTMUseCycle(const InstrItineraryData *ItinData, 3015 const MCInstrDesc &UseMCID, 3016 unsigned UseClass, 3017 unsigned UseIdx, unsigned UseAlign) const { 3018 int RegNo = (int)(UseIdx+1) - UseMCID.getNumOperands() + 1; 3019 if (RegNo <= 0) 3020 return ItinData->getOperandCycle(UseClass, UseIdx); 3021 3022 int UseCycle; 3023 if (Subtarget.isCortexA8()) { 3024 // (regno / 2) + (regno % 2) + 1 3025 UseCycle = RegNo / 2 + 1; 3026 if (RegNo % 2) 3027 ++UseCycle; 3028 } else if (Subtarget.isLikeA9() || Subtarget.isSwift()) { 3029 UseCycle = RegNo; 3030 bool isSStore = false; 3031 3032 switch (UseMCID.getOpcode()) { 3033 default: break; 3034 case ARM::VSTMSIA: 3035 case ARM::VSTMSIA_UPD: 3036 case ARM::VSTMSDB_UPD: 3037 isSStore = true; 3038 break; 3039 } 3040 3041 // If there are odd number of 'S' registers or if it's not 64-bit aligned, 3042 // then it takes an extra cycle. 3043 if ((isSStore && (RegNo % 2)) || UseAlign < 8) 3044 ++UseCycle; 3045 } else { 3046 // Assume the worst. 3047 UseCycle = RegNo + 2; 3048 } 3049 3050 return UseCycle; 3051} 3052 3053int 3054ARMBaseInstrInfo::getSTMUseCycle(const InstrItineraryData *ItinData, 3055 const MCInstrDesc &UseMCID, 3056 unsigned UseClass, 3057 unsigned UseIdx, unsigned UseAlign) const { 3058 int RegNo = (int)(UseIdx+1) - UseMCID.getNumOperands() + 1; 3059 if (RegNo <= 0) 3060 return ItinData->getOperandCycle(UseClass, UseIdx); 3061 3062 int UseCycle; 3063 if (Subtarget.isCortexA8()) { 3064 UseCycle = RegNo / 2; 3065 if (UseCycle < 2) 3066 UseCycle = 2; 3067 // Read in E3. 3068 UseCycle += 2; 3069 } else if (Subtarget.isLikeA9() || Subtarget.isSwift()) { 3070 UseCycle = (RegNo / 2); 3071 // If there are odd number of registers or if it's not 64-bit aligned, 3072 // then it takes an extra AGU (Address Generation Unit) cycle. 3073 if ((RegNo % 2) || UseAlign < 8) 3074 ++UseCycle; 3075 } else { 3076 // Assume the worst. 3077 UseCycle = 1; 3078 } 3079 return UseCycle; 3080} 3081 3082int 3083ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData, 3084 const MCInstrDesc &DefMCID, 3085 unsigned DefIdx, unsigned DefAlign, 3086 const MCInstrDesc &UseMCID, 3087 unsigned UseIdx, unsigned UseAlign) const { 3088 unsigned DefClass = DefMCID.getSchedClass(); 3089 unsigned UseClass = UseMCID.getSchedClass(); 3090 3091 if (DefIdx < DefMCID.getNumDefs() && UseIdx < UseMCID.getNumOperands()) 3092 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx); 3093 3094 // This may be a def / use of a variable_ops instruction, the operand 3095 // latency might be determinable dynamically. Let the target try to 3096 // figure it out. 3097 int DefCycle = -1; 3098 bool LdmBypass = false; 3099 switch (DefMCID.getOpcode()) { 3100 default: 3101 DefCycle = ItinData->getOperandCycle(DefClass, DefIdx); 3102 break; 3103 3104 case ARM::VLDMDIA: 3105 case ARM::VLDMDIA_UPD: 3106 case ARM::VLDMDDB_UPD: 3107 case ARM::VLDMSIA: 3108 case ARM::VLDMSIA_UPD: 3109 case ARM::VLDMSDB_UPD: 3110 DefCycle = getVLDMDefCycle(ItinData, DefMCID, DefClass, DefIdx, DefAlign); 3111 break; 3112 3113 case ARM::LDMIA_RET: 3114 case ARM::LDMIA: 3115 case ARM::LDMDA: 3116 case ARM::LDMDB: 3117 case ARM::LDMIB: 3118 case ARM::LDMIA_UPD: 3119 case ARM::LDMDA_UPD: 3120 case ARM::LDMDB_UPD: 3121 case ARM::LDMIB_UPD: 3122 case ARM::tLDMIA: 3123 case ARM::tLDMIA_UPD: 3124 case ARM::tPUSH: 3125 case ARM::t2LDMIA_RET: 3126 case ARM::t2LDMIA: 3127 case ARM::t2LDMDB: 3128 case ARM::t2LDMIA_UPD: 3129 case ARM::t2LDMDB_UPD: 3130 LdmBypass = 1; 3131 DefCycle = getLDMDefCycle(ItinData, DefMCID, DefClass, DefIdx, DefAlign); 3132 break; 3133 } 3134 3135 if (DefCycle == -1) 3136 // We can't seem to determine the result latency of the def, assume it's 2. 3137 DefCycle = 2; 3138 3139 int UseCycle = -1; 3140 switch (UseMCID.getOpcode()) { 3141 default: 3142 UseCycle = ItinData->getOperandCycle(UseClass, UseIdx); 3143 break; 3144 3145 case ARM::VSTMDIA: 3146 case ARM::VSTMDIA_UPD: 3147 case ARM::VSTMDDB_UPD: 3148 case ARM::VSTMSIA: 3149 case ARM::VSTMSIA_UPD: 3150 case ARM::VSTMSDB_UPD: 3151 UseCycle = getVSTMUseCycle(ItinData, UseMCID, UseClass, UseIdx, UseAlign); 3152 break; 3153 3154 case ARM::STMIA: 3155 case ARM::STMDA: 3156 case ARM::STMDB: 3157 case ARM::STMIB: 3158 case ARM::STMIA_UPD: 3159 case ARM::STMDA_UPD: 3160 case ARM::STMDB_UPD: 3161 case ARM::STMIB_UPD: 3162 case ARM::tSTMIA_UPD: 3163 case ARM::tPOP_RET: 3164 case ARM::tPOP: 3165 case ARM::t2STMIA: 3166 case ARM::t2STMDB: 3167 case ARM::t2STMIA_UPD: 3168 case ARM::t2STMDB_UPD: 3169 UseCycle = getSTMUseCycle(ItinData, UseMCID, UseClass, UseIdx, UseAlign); 3170 break; 3171 } 3172 3173 if (UseCycle == -1) 3174 // Assume it's read in the first stage. 3175 UseCycle = 1; 3176 3177 UseCycle = DefCycle - UseCycle + 1; 3178 if (UseCycle > 0) { 3179 if (LdmBypass) { 3180 // It's a variable_ops instruction so we can't use DefIdx here. Just use 3181 // first def operand. 3182 if (ItinData->hasPipelineForwarding(DefClass, DefMCID.getNumOperands()-1, 3183 UseClass, UseIdx)) 3184 --UseCycle; 3185 } else if (ItinData->hasPipelineForwarding(DefClass, DefIdx, 3186 UseClass, UseIdx)) { 3187 --UseCycle; 3188 } 3189 } 3190 3191 return UseCycle; 3192} 3193 3194static const MachineInstr *getBundledDefMI(const TargetRegisterInfo *TRI, 3195 const MachineInstr *MI, unsigned Reg, 3196 unsigned &DefIdx, unsigned &Dist) { 3197 Dist = 0; 3198 3199 MachineBasicBlock::const_iterator I = MI; ++I; 3200 MachineBasicBlock::const_instr_iterator II = 3201 llvm::prior(I.getInstrIterator()); 3202 assert(II->isInsideBundle() && "Empty bundle?"); 3203 3204 int Idx = -1; 3205 while (II->isInsideBundle()) { 3206 Idx = II->findRegisterDefOperandIdx(Reg, false, true, TRI); 3207 if (Idx != -1) 3208 break; 3209 --II; 3210 ++Dist; 3211 } 3212 3213 assert(Idx != -1 && "Cannot find bundled definition!"); 3214 DefIdx = Idx; 3215 return II; 3216} 3217 3218static const MachineInstr *getBundledUseMI(const TargetRegisterInfo *TRI, 3219 const MachineInstr *MI, unsigned Reg, 3220 unsigned &UseIdx, unsigned &Dist) { 3221 Dist = 0; 3222 3223 MachineBasicBlock::const_instr_iterator II = MI; ++II; 3224 assert(II->isInsideBundle() && "Empty bundle?"); 3225 MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end(); 3226 3227 // FIXME: This doesn't properly handle multiple uses. 3228 int Idx = -1; 3229 while (II != E && II->isInsideBundle()) { 3230 Idx = II->findRegisterUseOperandIdx(Reg, false, TRI); 3231 if (Idx != -1) 3232 break; 3233 if (II->getOpcode() != ARM::t2IT) 3234 ++Dist; 3235 ++II; 3236 } 3237 3238 if (Idx == -1) { 3239 Dist = 0; 3240 return 0; 3241 } 3242 3243 UseIdx = Idx; 3244 return II; 3245} 3246 3247/// Return the number of cycles to add to (or subtract from) the static 3248/// itinerary based on the def opcode and alignment. The caller will ensure that 3249/// adjusted latency is at least one cycle. 3250static int adjustDefLatency(const ARMSubtarget &Subtarget, 3251 const MachineInstr *DefMI, 3252 const MCInstrDesc *DefMCID, unsigned DefAlign) { 3253 int Adjust = 0; 3254 if (Subtarget.isCortexA8() || Subtarget.isLikeA9()) { 3255 // FIXME: Shifter op hack: no shift (i.e. [r +/- r]) or [r + r << 2] 3256 // variants are one cycle cheaper. 3257 switch (DefMCID->getOpcode()) { 3258 default: break; 3259 case ARM::LDRrs: 3260 case ARM::LDRBrs: { 3261 unsigned ShOpVal = DefMI->getOperand(3).getImm(); 3262 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal); 3263 if (ShImm == 0 || 3264 (ShImm == 2 && ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl)) 3265 --Adjust; 3266 break; 3267 } 3268 case ARM::t2LDRs: 3269 case ARM::t2LDRBs: 3270 case ARM::t2LDRHs: 3271 case ARM::t2LDRSHs: { 3272 // Thumb2 mode: lsl only. 3273 unsigned ShAmt = DefMI->getOperand(3).getImm(); 3274 if (ShAmt == 0 || ShAmt == 2) 3275 --Adjust; 3276 break; 3277 } 3278 } 3279 } else if (Subtarget.isSwift()) { 3280 // FIXME: Properly handle all of the latency adjustments for address 3281 // writeback. 3282 switch (DefMCID->getOpcode()) { 3283 default: break; 3284 case ARM::LDRrs: 3285 case ARM::LDRBrs: { 3286 unsigned ShOpVal = DefMI->getOperand(3).getImm(); 3287 bool isSub = ARM_AM::getAM2Op(ShOpVal) == ARM_AM::sub; 3288 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal); 3289 if (!isSub && 3290 (ShImm == 0 || 3291 ((ShImm == 1 || ShImm == 2 || ShImm == 3) && 3292 ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl))) 3293 Adjust -= 2; 3294 else if (!isSub && 3295 ShImm == 1 && ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsr) 3296 --Adjust; 3297 break; 3298 } 3299 case ARM::t2LDRs: 3300 case ARM::t2LDRBs: 3301 case ARM::t2LDRHs: 3302 case ARM::t2LDRSHs: { 3303 // Thumb2 mode: lsl only. 3304 unsigned ShAmt = DefMI->getOperand(3).getImm(); 3305 if (ShAmt == 0 || ShAmt == 1 || ShAmt == 2 || ShAmt == 3) 3306 Adjust -= 2; 3307 break; 3308 } 3309 } 3310 } 3311 3312 if (DefAlign < 8 && Subtarget.isLikeA9()) { 3313 switch (DefMCID->getOpcode()) { 3314 default: break; 3315 case ARM::VLD1q8: 3316 case ARM::VLD1q16: 3317 case ARM::VLD1q32: 3318 case ARM::VLD1q64: 3319 case ARM::VLD1q8wb_fixed: 3320 case ARM::VLD1q16wb_fixed: 3321 case ARM::VLD1q32wb_fixed: 3322 case ARM::VLD1q64wb_fixed: 3323 case ARM::VLD1q8wb_register: 3324 case ARM::VLD1q16wb_register: 3325 case ARM::VLD1q32wb_register: 3326 case ARM::VLD1q64wb_register: 3327 case ARM::VLD2d8: 3328 case ARM::VLD2d16: 3329 case ARM::VLD2d32: 3330 case ARM::VLD2q8: 3331 case ARM::VLD2q16: 3332 case ARM::VLD2q32: 3333 case ARM::VLD2d8wb_fixed: 3334 case ARM::VLD2d16wb_fixed: 3335 case ARM::VLD2d32wb_fixed: 3336 case ARM::VLD2q8wb_fixed: 3337 case ARM::VLD2q16wb_fixed: 3338 case ARM::VLD2q32wb_fixed: 3339 case ARM::VLD2d8wb_register: 3340 case ARM::VLD2d16wb_register: 3341 case ARM::VLD2d32wb_register: 3342 case ARM::VLD2q8wb_register: 3343 case ARM::VLD2q16wb_register: 3344 case ARM::VLD2q32wb_register: 3345 case ARM::VLD3d8: 3346 case ARM::VLD3d16: 3347 case ARM::VLD3d32: 3348 case ARM::VLD1d64T: 3349 case ARM::VLD3d8_UPD: 3350 case ARM::VLD3d16_UPD: 3351 case ARM::VLD3d32_UPD: 3352 case ARM::VLD1d64Twb_fixed: 3353 case ARM::VLD1d64Twb_register: 3354 case ARM::VLD3q8_UPD: 3355 case ARM::VLD3q16_UPD: 3356 case ARM::VLD3q32_UPD: 3357 case ARM::VLD4d8: 3358 case ARM::VLD4d16: 3359 case ARM::VLD4d32: 3360 case ARM::VLD1d64Q: 3361 case ARM::VLD4d8_UPD: 3362 case ARM::VLD4d16_UPD: 3363 case ARM::VLD4d32_UPD: 3364 case ARM::VLD1d64Qwb_fixed: 3365 case ARM::VLD1d64Qwb_register: 3366 case ARM::VLD4q8_UPD: 3367 case ARM::VLD4q16_UPD: 3368 case ARM::VLD4q32_UPD: 3369 case ARM::VLD1DUPq8: 3370 case ARM::VLD1DUPq16: 3371 case ARM::VLD1DUPq32: 3372 case ARM::VLD1DUPq8wb_fixed: 3373 case ARM::VLD1DUPq16wb_fixed: 3374 case ARM::VLD1DUPq32wb_fixed: 3375 case ARM::VLD1DUPq8wb_register: 3376 case ARM::VLD1DUPq16wb_register: 3377 case ARM::VLD1DUPq32wb_register: 3378 case ARM::VLD2DUPd8: 3379 case ARM::VLD2DUPd16: 3380 case ARM::VLD2DUPd32: 3381 case ARM::VLD2DUPd8wb_fixed: 3382 case ARM::VLD2DUPd16wb_fixed: 3383 case ARM::VLD2DUPd32wb_fixed: 3384 case ARM::VLD2DUPd8wb_register: 3385 case ARM::VLD2DUPd16wb_register: 3386 case ARM::VLD2DUPd32wb_register: 3387 case ARM::VLD4DUPd8: 3388 case ARM::VLD4DUPd16: 3389 case ARM::VLD4DUPd32: 3390 case ARM::VLD4DUPd8_UPD: 3391 case ARM::VLD4DUPd16_UPD: 3392 case ARM::VLD4DUPd32_UPD: 3393 case ARM::VLD1LNd8: 3394 case ARM::VLD1LNd16: 3395 case ARM::VLD1LNd32: 3396 case ARM::VLD1LNd8_UPD: 3397 case ARM::VLD1LNd16_UPD: 3398 case ARM::VLD1LNd32_UPD: 3399 case ARM::VLD2LNd8: 3400 case ARM::VLD2LNd16: 3401 case ARM::VLD2LNd32: 3402 case ARM::VLD2LNq16: 3403 case ARM::VLD2LNq32: 3404 case ARM::VLD2LNd8_UPD: 3405 case ARM::VLD2LNd16_UPD: 3406 case ARM::VLD2LNd32_UPD: 3407 case ARM::VLD2LNq16_UPD: 3408 case ARM::VLD2LNq32_UPD: 3409 case ARM::VLD4LNd8: 3410 case ARM::VLD4LNd16: 3411 case ARM::VLD4LNd32: 3412 case ARM::VLD4LNq16: 3413 case ARM::VLD4LNq32: 3414 case ARM::VLD4LNd8_UPD: 3415 case ARM::VLD4LNd16_UPD: 3416 case ARM::VLD4LNd32_UPD: 3417 case ARM::VLD4LNq16_UPD: 3418 case ARM::VLD4LNq32_UPD: 3419 // If the address is not 64-bit aligned, the latencies of these 3420 // instructions increases by one. 3421 ++Adjust; 3422 break; 3423 } 3424 } 3425 return Adjust; 3426} 3427 3428 3429 3430int 3431ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData, 3432 const MachineInstr *DefMI, unsigned DefIdx, 3433 const MachineInstr *UseMI, 3434 unsigned UseIdx) const { 3435 // No operand latency. The caller may fall back to getInstrLatency. 3436 if (!ItinData || ItinData->isEmpty()) 3437 return -1; 3438 3439 const MachineOperand &DefMO = DefMI->getOperand(DefIdx); 3440 unsigned Reg = DefMO.getReg(); 3441 const MCInstrDesc *DefMCID = &DefMI->getDesc(); 3442 const MCInstrDesc *UseMCID = &UseMI->getDesc(); 3443 3444 unsigned DefAdj = 0; 3445 if (DefMI->isBundle()) { 3446 DefMI = getBundledDefMI(&getRegisterInfo(), DefMI, Reg, DefIdx, DefAdj); 3447 DefMCID = &DefMI->getDesc(); 3448 } 3449 if (DefMI->isCopyLike() || DefMI->isInsertSubreg() || 3450 DefMI->isRegSequence() || DefMI->isImplicitDef()) { 3451 return 1; 3452 } 3453 3454 unsigned UseAdj = 0; 3455 if (UseMI->isBundle()) { 3456 unsigned NewUseIdx; 3457 const MachineInstr *NewUseMI = getBundledUseMI(&getRegisterInfo(), UseMI, 3458 Reg, NewUseIdx, UseAdj); 3459 if (!NewUseMI) 3460 return -1; 3461 3462 UseMI = NewUseMI; 3463 UseIdx = NewUseIdx; 3464 UseMCID = &UseMI->getDesc(); 3465 } 3466 3467 if (Reg == ARM::CPSR) { 3468 if (DefMI->getOpcode() == ARM::FMSTAT) { 3469 // fpscr -> cpsr stalls over 20 cycles on A8 (and earlier?) 3470 return Subtarget.isLikeA9() ? 1 : 20; 3471 } 3472 3473 // CPSR set and branch can be paired in the same cycle. 3474 if (UseMI->isBranch()) 3475 return 0; 3476 3477 // Otherwise it takes the instruction latency (generally one). 3478 unsigned Latency = getInstrLatency(ItinData, DefMI); 3479 3480 // For Thumb2 and -Os, prefer scheduling CPSR setting instruction close to 3481 // its uses. Instructions which are otherwise scheduled between them may 3482 // incur a code size penalty (not able to use the CPSR setting 16-bit 3483 // instructions). 3484 if (Latency > 0 && Subtarget.isThumb2()) { 3485 const MachineFunction *MF = DefMI->getParent()->getParent(); 3486 if (MF->getFunction()->getAttributes(). 3487 hasAttribute(AttributeSet::FunctionIndex, 3488 Attribute::OptimizeForSize)) 3489 --Latency; 3490 } 3491 return Latency; 3492 } 3493 3494 if (DefMO.isImplicit() || UseMI->getOperand(UseIdx).isImplicit()) 3495 return -1; 3496 3497 unsigned DefAlign = DefMI->hasOneMemOperand() 3498 ? (*DefMI->memoperands_begin())->getAlignment() : 0; 3499 unsigned UseAlign = UseMI->hasOneMemOperand() 3500 ? (*UseMI->memoperands_begin())->getAlignment() : 0; 3501 3502 // Get the itinerary's latency if possible, and handle variable_ops. 3503 int Latency = getOperandLatency(ItinData, *DefMCID, DefIdx, DefAlign, 3504 *UseMCID, UseIdx, UseAlign); 3505 // Unable to find operand latency. The caller may resort to getInstrLatency. 3506 if (Latency < 0) 3507 return Latency; 3508 3509 // Adjust for IT block position. 3510 int Adj = DefAdj + UseAdj; 3511 3512 // Adjust for dynamic def-side opcode variants not captured by the itinerary. 3513 Adj += adjustDefLatency(Subtarget, DefMI, DefMCID, DefAlign); 3514 if (Adj >= 0 || (int)Latency > -Adj) { 3515 return Latency + Adj; 3516 } 3517 // Return the itinerary latency, which may be zero but not less than zero. 3518 return Latency; 3519} 3520 3521int 3522ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData, 3523 SDNode *DefNode, unsigned DefIdx, 3524 SDNode *UseNode, unsigned UseIdx) const { 3525 if (!DefNode->isMachineOpcode()) 3526 return 1; 3527 3528 const MCInstrDesc &DefMCID = get(DefNode->getMachineOpcode()); 3529 3530 if (isZeroCost(DefMCID.Opcode)) 3531 return 0; 3532 3533 if (!ItinData || ItinData->isEmpty()) 3534 return DefMCID.mayLoad() ? 3 : 1; 3535 3536 if (!UseNode->isMachineOpcode()) { 3537 int Latency = ItinData->getOperandCycle(DefMCID.getSchedClass(), DefIdx); 3538 if (Subtarget.isLikeA9() || Subtarget.isSwift()) 3539 return Latency <= 2 ? 1 : Latency - 1; 3540 else 3541 return Latency <= 3 ? 1 : Latency - 2; 3542 } 3543 3544 const MCInstrDesc &UseMCID = get(UseNode->getMachineOpcode()); 3545 const MachineSDNode *DefMN = dyn_cast<MachineSDNode>(DefNode); 3546 unsigned DefAlign = !DefMN->memoperands_empty() 3547 ? (*DefMN->memoperands_begin())->getAlignment() : 0; 3548 const MachineSDNode *UseMN = dyn_cast<MachineSDNode>(UseNode); 3549 unsigned UseAlign = !UseMN->memoperands_empty() 3550 ? (*UseMN->memoperands_begin())->getAlignment() : 0; 3551 int Latency = getOperandLatency(ItinData, DefMCID, DefIdx, DefAlign, 3552 UseMCID, UseIdx, UseAlign); 3553 3554 if (Latency > 1 && 3555 (Subtarget.isCortexA8() || Subtarget.isLikeA9())) { 3556 // FIXME: Shifter op hack: no shift (i.e. [r +/- r]) or [r + r << 2] 3557 // variants are one cycle cheaper. 3558 switch (DefMCID.getOpcode()) { 3559 default: break; 3560 case ARM::LDRrs: 3561 case ARM::LDRBrs: { 3562 unsigned ShOpVal = 3563 cast<ConstantSDNode>(DefNode->getOperand(2))->getZExtValue(); 3564 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal); 3565 if (ShImm == 0 || 3566 (ShImm == 2 && ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl)) 3567 --Latency; 3568 break; 3569 } 3570 case ARM::t2LDRs: 3571 case ARM::t2LDRBs: 3572 case ARM::t2LDRHs: 3573 case ARM::t2LDRSHs: { 3574 // Thumb2 mode: lsl only. 3575 unsigned ShAmt = 3576 cast<ConstantSDNode>(DefNode->getOperand(2))->getZExtValue(); 3577 if (ShAmt == 0 || ShAmt == 2) 3578 --Latency; 3579 break; 3580 } 3581 } 3582 } else if (DefIdx == 0 && Latency > 2 && Subtarget.isSwift()) { 3583 // FIXME: Properly handle all of the latency adjustments for address 3584 // writeback. 3585 switch (DefMCID.getOpcode()) { 3586 default: break; 3587 case ARM::LDRrs: 3588 case ARM::LDRBrs: { 3589 unsigned ShOpVal = 3590 cast<ConstantSDNode>(DefNode->getOperand(2))->getZExtValue(); 3591 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal); 3592 if (ShImm == 0 || 3593 ((ShImm == 1 || ShImm == 2 || ShImm == 3) && 3594 ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl)) 3595 Latency -= 2; 3596 else if (ShImm == 1 && ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsr) 3597 --Latency; 3598 break; 3599 } 3600 case ARM::t2LDRs: 3601 case ARM::t2LDRBs: 3602 case ARM::t2LDRHs: 3603 case ARM::t2LDRSHs: { 3604 // Thumb2 mode: lsl 0-3 only. 3605 Latency -= 2; 3606 break; 3607 } 3608 } 3609 } 3610 3611 if (DefAlign < 8 && Subtarget.isLikeA9()) 3612 switch (DefMCID.getOpcode()) { 3613 default: break; 3614 case ARM::VLD1q8: 3615 case ARM::VLD1q16: 3616 case ARM::VLD1q32: 3617 case ARM::VLD1q64: 3618 case ARM::VLD1q8wb_register: 3619 case ARM::VLD1q16wb_register: 3620 case ARM::VLD1q32wb_register: 3621 case ARM::VLD1q64wb_register: 3622 case ARM::VLD1q8wb_fixed: 3623 case ARM::VLD1q16wb_fixed: 3624 case ARM::VLD1q32wb_fixed: 3625 case ARM::VLD1q64wb_fixed: 3626 case ARM::VLD2d8: 3627 case ARM::VLD2d16: 3628 case ARM::VLD2d32: 3629 case ARM::VLD2q8Pseudo: 3630 case ARM::VLD2q16Pseudo: 3631 case ARM::VLD2q32Pseudo: 3632 case ARM::VLD2d8wb_fixed: 3633 case ARM::VLD2d16wb_fixed: 3634 case ARM::VLD2d32wb_fixed: 3635 case ARM::VLD2q8PseudoWB_fixed: 3636 case ARM::VLD2q16PseudoWB_fixed: 3637 case ARM::VLD2q32PseudoWB_fixed: 3638 case ARM::VLD2d8wb_register: 3639 case ARM::VLD2d16wb_register: 3640 case ARM::VLD2d32wb_register: 3641 case ARM::VLD2q8PseudoWB_register: 3642 case ARM::VLD2q16PseudoWB_register: 3643 case ARM::VLD2q32PseudoWB_register: 3644 case ARM::VLD3d8Pseudo: 3645 case ARM::VLD3d16Pseudo: 3646 case ARM::VLD3d32Pseudo: 3647 case ARM::VLD1d64TPseudo: 3648 case ARM::VLD3d8Pseudo_UPD: 3649 case ARM::VLD3d16Pseudo_UPD: 3650 case ARM::VLD3d32Pseudo_UPD: 3651 case ARM::VLD3q8Pseudo_UPD: 3652 case ARM::VLD3q16Pseudo_UPD: 3653 case ARM::VLD3q32Pseudo_UPD: 3654 case ARM::VLD3q8oddPseudo: 3655 case ARM::VLD3q16oddPseudo: 3656 case ARM::VLD3q32oddPseudo: 3657 case ARM::VLD3q8oddPseudo_UPD: 3658 case ARM::VLD3q16oddPseudo_UPD: 3659 case ARM::VLD3q32oddPseudo_UPD: 3660 case ARM::VLD4d8Pseudo: 3661 case ARM::VLD4d16Pseudo: 3662 case ARM::VLD4d32Pseudo: 3663 case ARM::VLD1d64QPseudo: 3664 case ARM::VLD4d8Pseudo_UPD: 3665 case ARM::VLD4d16Pseudo_UPD: 3666 case ARM::VLD4d32Pseudo_UPD: 3667 case ARM::VLD4q8Pseudo_UPD: 3668 case ARM::VLD4q16Pseudo_UPD: 3669 case ARM::VLD4q32Pseudo_UPD: 3670 case ARM::VLD4q8oddPseudo: 3671 case ARM::VLD4q16oddPseudo: 3672 case ARM::VLD4q32oddPseudo: 3673 case ARM::VLD4q8oddPseudo_UPD: 3674 case ARM::VLD4q16oddPseudo_UPD: 3675 case ARM::VLD4q32oddPseudo_UPD: 3676 case ARM::VLD1DUPq8: 3677 case ARM::VLD1DUPq16: 3678 case ARM::VLD1DUPq32: 3679 case ARM::VLD1DUPq8wb_fixed: 3680 case ARM::VLD1DUPq16wb_fixed: 3681 case ARM::VLD1DUPq32wb_fixed: 3682 case ARM::VLD1DUPq8wb_register: 3683 case ARM::VLD1DUPq16wb_register: 3684 case ARM::VLD1DUPq32wb_register: 3685 case ARM::VLD2DUPd8: 3686 case ARM::VLD2DUPd16: 3687 case ARM::VLD2DUPd32: 3688 case ARM::VLD2DUPd8wb_fixed: 3689 case ARM::VLD2DUPd16wb_fixed: 3690 case ARM::VLD2DUPd32wb_fixed: 3691 case ARM::VLD2DUPd8wb_register: 3692 case ARM::VLD2DUPd16wb_register: 3693 case ARM::VLD2DUPd32wb_register: 3694 case ARM::VLD4DUPd8Pseudo: 3695 case ARM::VLD4DUPd16Pseudo: 3696 case ARM::VLD4DUPd32Pseudo: 3697 case ARM::VLD4DUPd8Pseudo_UPD: 3698 case ARM::VLD4DUPd16Pseudo_UPD: 3699 case ARM::VLD4DUPd32Pseudo_UPD: 3700 case ARM::VLD1LNq8Pseudo: 3701 case ARM::VLD1LNq16Pseudo: 3702 case ARM::VLD1LNq32Pseudo: 3703 case ARM::VLD1LNq8Pseudo_UPD: 3704 case ARM::VLD1LNq16Pseudo_UPD: 3705 case ARM::VLD1LNq32Pseudo_UPD: 3706 case ARM::VLD2LNd8Pseudo: 3707 case ARM::VLD2LNd16Pseudo: 3708 case ARM::VLD2LNd32Pseudo: 3709 case ARM::VLD2LNq16Pseudo: 3710 case ARM::VLD2LNq32Pseudo: 3711 case ARM::VLD2LNd8Pseudo_UPD: 3712 case ARM::VLD2LNd16Pseudo_UPD: 3713 case ARM::VLD2LNd32Pseudo_UPD: 3714 case ARM::VLD2LNq16Pseudo_UPD: 3715 case ARM::VLD2LNq32Pseudo_UPD: 3716 case ARM::VLD4LNd8Pseudo: 3717 case ARM::VLD4LNd16Pseudo: 3718 case ARM::VLD4LNd32Pseudo: 3719 case ARM::VLD4LNq16Pseudo: 3720 case ARM::VLD4LNq32Pseudo: 3721 case ARM::VLD4LNd8Pseudo_UPD: 3722 case ARM::VLD4LNd16Pseudo_UPD: 3723 case ARM::VLD4LNd32Pseudo_UPD: 3724 case ARM::VLD4LNq16Pseudo_UPD: 3725 case ARM::VLD4LNq32Pseudo_UPD: 3726 // If the address is not 64-bit aligned, the latencies of these 3727 // instructions increases by one. 3728 ++Latency; 3729 break; 3730 } 3731 3732 return Latency; 3733} 3734 3735unsigned ARMBaseInstrInfo::getPredicationCost(const MachineInstr *MI) const { 3736 if (MI->isCopyLike() || MI->isInsertSubreg() || 3737 MI->isRegSequence() || MI->isImplicitDef()) 3738 return 0; 3739 3740 if (MI->isBundle()) 3741 return 0; 3742 3743 const MCInstrDesc &MCID = MI->getDesc(); 3744 3745 if (MCID.isCall() || MCID.hasImplicitDefOfPhysReg(ARM::CPSR)) { 3746 // When predicated, CPSR is an additional source operand for CPSR updating 3747 // instructions, this apparently increases their latencies. 3748 return 1; 3749 } 3750 return 0; 3751} 3752 3753unsigned ARMBaseInstrInfo::getInstrLatency(const InstrItineraryData *ItinData, 3754 const MachineInstr *MI, 3755 unsigned *PredCost) const { 3756 if (MI->isCopyLike() || MI->isInsertSubreg() || 3757 MI->isRegSequence() || MI->isImplicitDef()) 3758 return 1; 3759 3760 // An instruction scheduler typically runs on unbundled instructions, however 3761 // other passes may query the latency of a bundled instruction. 3762 if (MI->isBundle()) { 3763 unsigned Latency = 0; 3764 MachineBasicBlock::const_instr_iterator I = MI; 3765 MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end(); 3766 while (++I != E && I->isInsideBundle()) { 3767 if (I->getOpcode() != ARM::t2IT) 3768 Latency += getInstrLatency(ItinData, I, PredCost); 3769 } 3770 return Latency; 3771 } 3772 3773 const MCInstrDesc &MCID = MI->getDesc(); 3774 if (PredCost && (MCID.isCall() || MCID.hasImplicitDefOfPhysReg(ARM::CPSR))) { 3775 // When predicated, CPSR is an additional source operand for CPSR updating 3776 // instructions, this apparently increases their latencies. 3777 *PredCost = 1; 3778 } 3779 // Be sure to call getStageLatency for an empty itinerary in case it has a 3780 // valid MinLatency property. 3781 if (!ItinData) 3782 return MI->mayLoad() ? 3 : 1; 3783 3784 unsigned Class = MCID.getSchedClass(); 3785 3786 // For instructions with variable uops, use uops as latency. 3787 if (!ItinData->isEmpty() && ItinData->getNumMicroOps(Class) < 0) 3788 return getNumMicroOps(ItinData, MI); 3789 3790 // For the common case, fall back on the itinerary's latency. 3791 unsigned Latency = ItinData->getStageLatency(Class); 3792 3793 // Adjust for dynamic def-side opcode variants not captured by the itinerary. 3794 unsigned DefAlign = MI->hasOneMemOperand() 3795 ? (*MI->memoperands_begin())->getAlignment() : 0; 3796 int Adj = adjustDefLatency(Subtarget, MI, &MCID, DefAlign); 3797 if (Adj >= 0 || (int)Latency > -Adj) { 3798 return Latency + Adj; 3799 } 3800 return Latency; 3801} 3802 3803int ARMBaseInstrInfo::getInstrLatency(const InstrItineraryData *ItinData, 3804 SDNode *Node) const { 3805 if (!Node->isMachineOpcode()) 3806 return 1; 3807 3808 if (!ItinData || ItinData->isEmpty()) 3809 return 1; 3810 3811 unsigned Opcode = Node->getMachineOpcode(); 3812 switch (Opcode) { 3813 default: 3814 return ItinData->getStageLatency(get(Opcode).getSchedClass()); 3815 case ARM::VLDMQIA: 3816 case ARM::VSTMQIA: 3817 return 2; 3818 } 3819} 3820 3821bool ARMBaseInstrInfo:: 3822hasHighOperandLatency(const InstrItineraryData *ItinData, 3823 const MachineRegisterInfo *MRI, 3824 const MachineInstr *DefMI, unsigned DefIdx, 3825 const MachineInstr *UseMI, unsigned UseIdx) const { 3826 unsigned DDomain = DefMI->getDesc().TSFlags & ARMII::DomainMask; 3827 unsigned UDomain = UseMI->getDesc().TSFlags & ARMII::DomainMask; 3828 if (Subtarget.isCortexA8() && 3829 (DDomain == ARMII::DomainVFP || UDomain == ARMII::DomainVFP)) 3830 // CortexA8 VFP instructions are not pipelined. 3831 return true; 3832 3833 // Hoist VFP / NEON instructions with 4 or higher latency. 3834 int Latency = computeOperandLatency(ItinData, DefMI, DefIdx, UseMI, UseIdx); 3835 if (Latency < 0) 3836 Latency = getInstrLatency(ItinData, DefMI); 3837 if (Latency <= 3) 3838 return false; 3839 return DDomain == ARMII::DomainVFP || DDomain == ARMII::DomainNEON || 3840 UDomain == ARMII::DomainVFP || UDomain == ARMII::DomainNEON; 3841} 3842 3843bool ARMBaseInstrInfo:: 3844hasLowDefLatency(const InstrItineraryData *ItinData, 3845 const MachineInstr *DefMI, unsigned DefIdx) const { 3846 if (!ItinData || ItinData->isEmpty()) 3847 return false; 3848 3849 unsigned DDomain = DefMI->getDesc().TSFlags & ARMII::DomainMask; 3850 if (DDomain == ARMII::DomainGeneral) { 3851 unsigned DefClass = DefMI->getDesc().getSchedClass(); 3852 int DefCycle = ItinData->getOperandCycle(DefClass, DefIdx); 3853 return (DefCycle != -1 && DefCycle <= 2); 3854 } 3855 return false; 3856} 3857 3858bool ARMBaseInstrInfo::verifyInstruction(const MachineInstr *MI, 3859 StringRef &ErrInfo) const { 3860 if (convertAddSubFlagsOpcode(MI->getOpcode())) { 3861 ErrInfo = "Pseudo flag setting opcodes only exist in Selection DAG"; 3862 return false; 3863 } 3864 return true; 3865} 3866 3867bool 3868ARMBaseInstrInfo::isFpMLxInstruction(unsigned Opcode, unsigned &MulOpc, 3869 unsigned &AddSubOpc, 3870 bool &NegAcc, bool &HasLane) const { 3871 DenseMap<unsigned, unsigned>::const_iterator I = MLxEntryMap.find(Opcode); 3872 if (I == MLxEntryMap.end()) 3873 return false; 3874 3875 const ARM_MLxEntry &Entry = ARM_MLxTable[I->second]; 3876 MulOpc = Entry.MulOpc; 3877 AddSubOpc = Entry.AddSubOpc; 3878 NegAcc = Entry.NegAcc; 3879 HasLane = Entry.HasLane; 3880 return true; 3881} 3882 3883//===----------------------------------------------------------------------===// 3884// Execution domains. 3885//===----------------------------------------------------------------------===// 3886// 3887// Some instructions go down the NEON pipeline, some go down the VFP pipeline, 3888// and some can go down both. The vmov instructions go down the VFP pipeline, 3889// but they can be changed to vorr equivalents that are executed by the NEON 3890// pipeline. 3891// 3892// We use the following execution domain numbering: 3893// 3894enum ARMExeDomain { 3895 ExeGeneric = 0, 3896 ExeVFP = 1, 3897 ExeNEON = 2 3898}; 3899// 3900// Also see ARMInstrFormats.td and Domain* enums in ARMBaseInfo.h 3901// 3902std::pair<uint16_t, uint16_t> 3903ARMBaseInstrInfo::getExecutionDomain(const MachineInstr *MI) const { 3904 // VMOVD, VMOVRS and VMOVSR are VFP instructions, but can be changed to NEON 3905 // if they are not predicated. 3906 if (MI->getOpcode() == ARM::VMOVD && !isPredicated(MI)) 3907 return std::make_pair(ExeVFP, (1<<ExeVFP) | (1<<ExeNEON)); 3908 3909 // CortexA9 is particularly picky about mixing the two and wants these 3910 // converted. 3911 if (Subtarget.isCortexA9() && !isPredicated(MI) && 3912 (MI->getOpcode() == ARM::VMOVRS || 3913 MI->getOpcode() == ARM::VMOVSR || 3914 MI->getOpcode() == ARM::VMOVS)) 3915 return std::make_pair(ExeVFP, (1<<ExeVFP) | (1<<ExeNEON)); 3916 3917 // No other instructions can be swizzled, so just determine their domain. 3918 unsigned Domain = MI->getDesc().TSFlags & ARMII::DomainMask; 3919 3920 if (Domain & ARMII::DomainNEON) 3921 return std::make_pair(ExeNEON, 0); 3922 3923 // Certain instructions can go either way on Cortex-A8. 3924 // Treat them as NEON instructions. 3925 if ((Domain & ARMII::DomainNEONA8) && Subtarget.isCortexA8()) 3926 return std::make_pair(ExeNEON, 0); 3927 3928 if (Domain & ARMII::DomainVFP) 3929 return std::make_pair(ExeVFP, 0); 3930 3931 return std::make_pair(ExeGeneric, 0); 3932} 3933 3934static unsigned getCorrespondingDRegAndLane(const TargetRegisterInfo *TRI, 3935 unsigned SReg, unsigned &Lane) { 3936 unsigned DReg = TRI->getMatchingSuperReg(SReg, ARM::ssub_0, &ARM::DPRRegClass); 3937 Lane = 0; 3938 3939 if (DReg != ARM::NoRegister) 3940 return DReg; 3941 3942 Lane = 1; 3943 DReg = TRI->getMatchingSuperReg(SReg, ARM::ssub_1, &ARM::DPRRegClass); 3944 3945 assert(DReg && "S-register with no D super-register?"); 3946 return DReg; 3947} 3948 3949/// getImplicitSPRUseForDPRUse - Given a use of a DPR register and lane, 3950/// set ImplicitSReg to a register number that must be marked as implicit-use or 3951/// zero if no register needs to be defined as implicit-use. 3952/// 3953/// If the function cannot determine if an SPR should be marked implicit use or 3954/// not, it returns false. 3955/// 3956/// This function handles cases where an instruction is being modified from taking 3957/// an SPR to a DPR[Lane]. A use of the DPR is being added, which may conflict 3958/// with an earlier def of an SPR corresponding to DPR[Lane^1] (i.e. the other 3959/// lane of the DPR). 3960/// 3961/// If the other SPR is defined, an implicit-use of it should be added. Else, 3962/// (including the case where the DPR itself is defined), it should not. 3963/// 3964static bool getImplicitSPRUseForDPRUse(const TargetRegisterInfo *TRI, 3965 MachineInstr *MI, 3966 unsigned DReg, unsigned Lane, 3967 unsigned &ImplicitSReg) { 3968 // If the DPR is defined or used already, the other SPR lane will be chained 3969 // correctly, so there is nothing to be done. 3970 if (MI->definesRegister(DReg, TRI) || MI->readsRegister(DReg, TRI)) { 3971 ImplicitSReg = 0; 3972 return true; 3973 } 3974 3975 // Otherwise we need to go searching to see if the SPR is set explicitly. 3976 ImplicitSReg = TRI->getSubReg(DReg, 3977 (Lane & 1) ? ARM::ssub_0 : ARM::ssub_1); 3978 MachineBasicBlock::LivenessQueryResult LQR = 3979 MI->getParent()->computeRegisterLiveness(TRI, ImplicitSReg, MI); 3980 3981 if (LQR == MachineBasicBlock::LQR_Live) 3982 return true; 3983 else if (LQR == MachineBasicBlock::LQR_Unknown) 3984 return false; 3985 3986 // If the register is known not to be live, there is no need to add an 3987 // implicit-use. 3988 ImplicitSReg = 0; 3989 return true; 3990} 3991 3992void 3993ARMBaseInstrInfo::setExecutionDomain(MachineInstr *MI, unsigned Domain) const { 3994 unsigned DstReg, SrcReg, DReg; 3995 unsigned Lane; 3996 MachineInstrBuilder MIB(*MI->getParent()->getParent(), MI); 3997 const TargetRegisterInfo *TRI = &getRegisterInfo(); 3998 switch (MI->getOpcode()) { 3999 default: 4000 llvm_unreachable("cannot handle opcode!"); 4001 break; 4002 case ARM::VMOVD: 4003 if (Domain != ExeNEON) 4004 break; 4005 4006 // Zap the predicate operands. 4007 assert(!isPredicated(MI) && "Cannot predicate a VORRd"); 4008 4009 // Source instruction is %DDst = VMOVD %DSrc, 14, %noreg (; implicits) 4010 DstReg = MI->getOperand(0).getReg(); 4011 SrcReg = MI->getOperand(1).getReg(); 4012 4013 for (unsigned i = MI->getDesc().getNumOperands(); i; --i) 4014 MI->RemoveOperand(i-1); 4015 4016 // Change to a %DDst = VORRd %DSrc, %DSrc, 14, %noreg (; implicits) 4017 MI->setDesc(get(ARM::VORRd)); 4018 AddDefaultPred(MIB.addReg(DstReg, RegState::Define) 4019 .addReg(SrcReg) 4020 .addReg(SrcReg)); 4021 break; 4022 case ARM::VMOVRS: 4023 if (Domain != ExeNEON) 4024 break; 4025 assert(!isPredicated(MI) && "Cannot predicate a VGETLN"); 4026 4027 // Source instruction is %RDst = VMOVRS %SSrc, 14, %noreg (; implicits) 4028 DstReg = MI->getOperand(0).getReg(); 4029 SrcReg = MI->getOperand(1).getReg(); 4030 4031 for (unsigned i = MI->getDesc().getNumOperands(); i; --i) 4032 MI->RemoveOperand(i-1); 4033 4034 DReg = getCorrespondingDRegAndLane(TRI, SrcReg, Lane); 4035 4036 // Convert to %RDst = VGETLNi32 %DSrc, Lane, 14, %noreg (; imps) 4037 // Note that DSrc has been widened and the other lane may be undef, which 4038 // contaminates the entire register. 4039 MI->setDesc(get(ARM::VGETLNi32)); 4040 AddDefaultPred(MIB.addReg(DstReg, RegState::Define) 4041 .addReg(DReg, RegState::Undef) 4042 .addImm(Lane)); 4043 4044 // The old source should be an implicit use, otherwise we might think it 4045 // was dead before here. 4046 MIB.addReg(SrcReg, RegState::Implicit); 4047 break; 4048 case ARM::VMOVSR: { 4049 if (Domain != ExeNEON) 4050 break; 4051 assert(!isPredicated(MI) && "Cannot predicate a VSETLN"); 4052 4053 // Source instruction is %SDst = VMOVSR %RSrc, 14, %noreg (; implicits) 4054 DstReg = MI->getOperand(0).getReg(); 4055 SrcReg = MI->getOperand(1).getReg(); 4056 4057 DReg = getCorrespondingDRegAndLane(TRI, DstReg, Lane); 4058 4059 unsigned ImplicitSReg; 4060 if (!getImplicitSPRUseForDPRUse(TRI, MI, DReg, Lane, ImplicitSReg)) 4061 break; 4062 4063 for (unsigned i = MI->getDesc().getNumOperands(); i; --i) 4064 MI->RemoveOperand(i-1); 4065 4066 // Convert to %DDst = VSETLNi32 %DDst, %RSrc, Lane, 14, %noreg (; imps) 4067 // Again DDst may be undefined at the beginning of this instruction. 4068 MI->setDesc(get(ARM::VSETLNi32)); 4069 MIB.addReg(DReg, RegState::Define) 4070 .addReg(DReg, getUndefRegState(!MI->readsRegister(DReg, TRI))) 4071 .addReg(SrcReg) 4072 .addImm(Lane); 4073 AddDefaultPred(MIB); 4074 4075 // The narrower destination must be marked as set to keep previous chains 4076 // in place. 4077 MIB.addReg(DstReg, RegState::Define | RegState::Implicit); 4078 if (ImplicitSReg != 0) 4079 MIB.addReg(ImplicitSReg, RegState::Implicit); 4080 break; 4081 } 4082 case ARM::VMOVS: { 4083 if (Domain != ExeNEON) 4084 break; 4085 4086 // Source instruction is %SDst = VMOVS %SSrc, 14, %noreg (; implicits) 4087 DstReg = MI->getOperand(0).getReg(); 4088 SrcReg = MI->getOperand(1).getReg(); 4089 4090 unsigned DstLane = 0, SrcLane = 0, DDst, DSrc; 4091 DDst = getCorrespondingDRegAndLane(TRI, DstReg, DstLane); 4092 DSrc = getCorrespondingDRegAndLane(TRI, SrcReg, SrcLane); 4093 4094 unsigned ImplicitSReg; 4095 if (!getImplicitSPRUseForDPRUse(TRI, MI, DSrc, SrcLane, ImplicitSReg)) 4096 break; 4097 4098 for (unsigned i = MI->getDesc().getNumOperands(); i; --i) 4099 MI->RemoveOperand(i-1); 4100 4101 if (DSrc == DDst) { 4102 // Destination can be: 4103 // %DDst = VDUPLN32d %DDst, Lane, 14, %noreg (; implicits) 4104 MI->setDesc(get(ARM::VDUPLN32d)); 4105 MIB.addReg(DDst, RegState::Define) 4106 .addReg(DDst, getUndefRegState(!MI->readsRegister(DDst, TRI))) 4107 .addImm(SrcLane); 4108 AddDefaultPred(MIB); 4109 4110 // Neither the source or the destination are naturally represented any 4111 // more, so add them in manually. 4112 MIB.addReg(DstReg, RegState::Implicit | RegState::Define); 4113 MIB.addReg(SrcReg, RegState::Implicit); 4114 if (ImplicitSReg != 0) 4115 MIB.addReg(ImplicitSReg, RegState::Implicit); 4116 break; 4117 } 4118 4119 // In general there's no single instruction that can perform an S <-> S 4120 // move in NEON space, but a pair of VEXT instructions *can* do the 4121 // job. It turns out that the VEXTs needed will only use DSrc once, with 4122 // the position based purely on the combination of lane-0 and lane-1 4123 // involved. For example 4124 // vmov s0, s2 -> vext.32 d0, d0, d1, #1 vext.32 d0, d0, d0, #1 4125 // vmov s1, s3 -> vext.32 d0, d1, d0, #1 vext.32 d0, d0, d0, #1 4126 // vmov s0, s3 -> vext.32 d0, d0, d0, #1 vext.32 d0, d1, d0, #1 4127 // vmov s1, s2 -> vext.32 d0, d0, d0, #1 vext.32 d0, d0, d1, #1 4128 // 4129 // Pattern of the MachineInstrs is: 4130 // %DDst = VEXTd32 %DSrc1, %DSrc2, Lane, 14, %noreg (;implicits) 4131 MachineInstrBuilder NewMIB; 4132 NewMIB = BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), 4133 get(ARM::VEXTd32), DDst); 4134 4135 // On the first instruction, both DSrc and DDst may be <undef> if present. 4136 // Specifically when the original instruction didn't have them as an 4137 // <imp-use>. 4138 unsigned CurReg = SrcLane == 1 && DstLane == 1 ? DSrc : DDst; 4139 bool CurUndef = !MI->readsRegister(CurReg, TRI); 4140 NewMIB.addReg(CurReg, getUndefRegState(CurUndef)); 4141 4142 CurReg = SrcLane == 0 && DstLane == 0 ? DSrc : DDst; 4143 CurUndef = !MI->readsRegister(CurReg, TRI); 4144 NewMIB.addReg(CurReg, getUndefRegState(CurUndef)); 4145 4146 NewMIB.addImm(1); 4147 AddDefaultPred(NewMIB); 4148 4149 if (SrcLane == DstLane) 4150 NewMIB.addReg(SrcReg, RegState::Implicit); 4151 4152 MI->setDesc(get(ARM::VEXTd32)); 4153 MIB.addReg(DDst, RegState::Define); 4154 4155 // On the second instruction, DDst has definitely been defined above, so 4156 // it is not <undef>. DSrc, if present, can be <undef> as above. 4157 CurReg = SrcLane == 1 && DstLane == 0 ? DSrc : DDst; 4158 CurUndef = CurReg == DSrc && !MI->readsRegister(CurReg, TRI); 4159 MIB.addReg(CurReg, getUndefRegState(CurUndef)); 4160 4161 CurReg = SrcLane == 0 && DstLane == 1 ? DSrc : DDst; 4162 CurUndef = CurReg == DSrc && !MI->readsRegister(CurReg, TRI); 4163 MIB.addReg(CurReg, getUndefRegState(CurUndef)); 4164 4165 MIB.addImm(1); 4166 AddDefaultPred(MIB); 4167 4168 if (SrcLane != DstLane) 4169 MIB.addReg(SrcReg, RegState::Implicit); 4170 4171 // As before, the original destination is no longer represented, add it 4172 // implicitly. 4173 MIB.addReg(DstReg, RegState::Define | RegState::Implicit); 4174 if (ImplicitSReg != 0) 4175 MIB.addReg(ImplicitSReg, RegState::Implicit); 4176 break; 4177 } 4178 } 4179 4180} 4181 4182//===----------------------------------------------------------------------===// 4183// Partial register updates 4184//===----------------------------------------------------------------------===// 4185// 4186// Swift renames NEON registers with 64-bit granularity. That means any 4187// instruction writing an S-reg implicitly reads the containing D-reg. The 4188// problem is mostly avoided by translating f32 operations to v2f32 operations 4189// on D-registers, but f32 loads are still a problem. 4190// 4191// These instructions can load an f32 into a NEON register: 4192// 4193// VLDRS - Only writes S, partial D update. 4194// VLD1LNd32 - Writes all D-regs, explicit partial D update, 2 uops. 4195// VLD1DUPd32 - Writes all D-regs, no partial reg update, 2 uops. 4196// 4197// FCONSTD can be used as a dependency-breaking instruction. 4198unsigned ARMBaseInstrInfo:: 4199getPartialRegUpdateClearance(const MachineInstr *MI, 4200 unsigned OpNum, 4201 const TargetRegisterInfo *TRI) const { 4202 if (!SwiftPartialUpdateClearance || 4203 !(Subtarget.isSwift() || Subtarget.isCortexA15())) 4204 return 0; 4205 4206 assert(TRI && "Need TRI instance"); 4207 4208 const MachineOperand &MO = MI->getOperand(OpNum); 4209 if (MO.readsReg()) 4210 return 0; 4211 unsigned Reg = MO.getReg(); 4212 int UseOp = -1; 4213 4214 switch(MI->getOpcode()) { 4215 // Normal instructions writing only an S-register. 4216 case ARM::VLDRS: 4217 case ARM::FCONSTS: 4218 case ARM::VMOVSR: 4219 case ARM::VMOVv8i8: 4220 case ARM::VMOVv4i16: 4221 case ARM::VMOVv2i32: 4222 case ARM::VMOVv2f32: 4223 case ARM::VMOVv1i64: 4224 UseOp = MI->findRegisterUseOperandIdx(Reg, false, TRI); 4225 break; 4226 4227 // Explicitly reads the dependency. 4228 case ARM::VLD1LNd32: 4229 UseOp = 3; 4230 break; 4231 default: 4232 return 0; 4233 } 4234 4235 // If this instruction actually reads a value from Reg, there is no unwanted 4236 // dependency. 4237 if (UseOp != -1 && MI->getOperand(UseOp).readsReg()) 4238 return 0; 4239 4240 // We must be able to clobber the whole D-reg. 4241 if (TargetRegisterInfo::isVirtualRegister(Reg)) { 4242 // Virtual register must be a foo:ssub_0<def,undef> operand. 4243 if (!MO.getSubReg() || MI->readsVirtualRegister(Reg)) 4244 return 0; 4245 } else if (ARM::SPRRegClass.contains(Reg)) { 4246 // Physical register: MI must define the full D-reg. 4247 unsigned DReg = TRI->getMatchingSuperReg(Reg, ARM::ssub_0, 4248 &ARM::DPRRegClass); 4249 if (!DReg || !MI->definesRegister(DReg, TRI)) 4250 return 0; 4251 } 4252 4253 // MI has an unwanted D-register dependency. 4254 // Avoid defs in the previous N instructrions. 4255 return SwiftPartialUpdateClearance; 4256} 4257 4258// Break a partial register dependency after getPartialRegUpdateClearance 4259// returned non-zero. 4260void ARMBaseInstrInfo:: 4261breakPartialRegDependency(MachineBasicBlock::iterator MI, 4262 unsigned OpNum, 4263 const TargetRegisterInfo *TRI) const { 4264 assert(MI && OpNum < MI->getDesc().getNumDefs() && "OpNum is not a def"); 4265 assert(TRI && "Need TRI instance"); 4266 4267 const MachineOperand &MO = MI->getOperand(OpNum); 4268 unsigned Reg = MO.getReg(); 4269 assert(TargetRegisterInfo::isPhysicalRegister(Reg) && 4270 "Can't break virtual register dependencies."); 4271 unsigned DReg = Reg; 4272 4273 // If MI defines an S-reg, find the corresponding D super-register. 4274 if (ARM::SPRRegClass.contains(Reg)) { 4275 DReg = ARM::D0 + (Reg - ARM::S0) / 2; 4276 assert(TRI->isSuperRegister(Reg, DReg) && "Register enums broken"); 4277 } 4278 4279 assert(ARM::DPRRegClass.contains(DReg) && "Can only break D-reg deps"); 4280 assert(MI->definesRegister(DReg, TRI) && "MI doesn't clobber full D-reg"); 4281 4282 // FIXME: In some cases, VLDRS can be changed to a VLD1DUPd32 which defines 4283 // the full D-register by loading the same value to both lanes. The 4284 // instruction is micro-coded with 2 uops, so don't do this until we can 4285 // properly schedule micro-coded instructions. The dispatcher stalls cause 4286 // too big regressions. 4287 4288 // Insert the dependency-breaking FCONSTD before MI. 4289 // 96 is the encoding of 0.5, but the actual value doesn't matter here. 4290 AddDefaultPred(BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), 4291 get(ARM::FCONSTD), DReg).addImm(96)); 4292 MI->addRegisterKilled(DReg, TRI, true); 4293} 4294 4295bool ARMBaseInstrInfo::hasNOP() const { 4296 return (Subtarget.getFeatureBits() & ARM::HasV6T2Ops) != 0; 4297} 4298 4299bool ARMBaseInstrInfo::isSwiftFastImmShift(const MachineInstr *MI) const { 4300 if (MI->getNumOperands() < 4) 4301 return true; 4302 unsigned ShOpVal = MI->getOperand(3).getImm(); 4303 unsigned ShImm = ARM_AM::getSORegOffset(ShOpVal); 4304 // Swift supports faster shifts for: lsl 2, lsl 1, and lsr 1. 4305 if ((ShImm == 1 && ARM_AM::getSORegShOp(ShOpVal) == ARM_AM::lsr) || 4306 ((ShImm == 1 || ShImm == 2) && 4307 ARM_AM::getSORegShOp(ShOpVal) == ARM_AM::lsl)) 4308 return true; 4309 4310 return false; 4311} 4312