ARMBaseInstrInfo.h revision dce4a407a24b04eebc6a376f8e62b41aaa7b071f 
1//===-- ARMBaseInstrInfo.h - ARM Base Instruction Information ---*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the Base ARM implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef ARMBASEINSTRUCTIONINFO_H
15#define ARMBASEINSTRUCTIONINFO_H
16
17#include "MCTargetDesc/ARMBaseInfo.h"
18#include "llvm/ADT/DenseMap.h"
19#include "llvm/ADT/SmallSet.h"
20#include "llvm/CodeGen/MachineInstrBuilder.h"
21#include "llvm/Target/TargetInstrInfo.h"
22
23#define GET_INSTRINFO_HEADER
24#include "ARMGenInstrInfo.inc"
25
26namespace llvm {
27  class ARMSubtarget;
28  class ARMBaseRegisterInfo;
29
30class ARMBaseInstrInfo : public ARMGenInstrInfo {
31  const ARMSubtarget &Subtarget;
32
33protected:
34  // Can be only subclassed.
35  explicit ARMBaseInstrInfo(const ARMSubtarget &STI);
36
37public:
38  // Return whether the target has an explicit NOP encoding.
39  bool hasNOP() const;
40
41  // Return the non-pre/post incrementing version of 'Opc'. Return 0
42  // if there is not such an opcode.
43  virtual unsigned getUnindexedOpcode(unsigned Opc) const =0;
44
45  MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI,
46                                      MachineBasicBlock::iterator &MBBI,
47                                      LiveVariables *LV) const override;
48
49  virtual const ARMBaseRegisterInfo &getRegisterInfo() const = 0;
50  const ARMSubtarget &getSubtarget() const { return Subtarget; }
51
52  ScheduleHazardRecognizer *
53  CreateTargetHazardRecognizer(const TargetMachine *TM,
54                               const ScheduleDAG *DAG) const override;
55
56  ScheduleHazardRecognizer *
57  CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II,
58                                     const ScheduleDAG *DAG) const override;
59
60  // Branch analysis.
61  bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
62                     MachineBasicBlock *&FBB,
63                     SmallVectorImpl<MachineOperand> &Cond,
64                     bool AllowModify = false) const override;
65  unsigned RemoveBranch(MachineBasicBlock &MBB) const override;
66  unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
67                        MachineBasicBlock *FBB,
68                        const SmallVectorImpl<MachineOperand> &Cond,
69                        DebugLoc DL) const override;
70
71  bool
72  ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
73
74  // Predication support.
75  bool isPredicated(const MachineInstr *MI) const override;
76
77  ARMCC::CondCodes getPredicate(const MachineInstr *MI) const {
78    int PIdx = MI->findFirstPredOperandIdx();
79    return PIdx != -1 ? (ARMCC::CondCodes)MI->getOperand(PIdx).getImm()
80                      : ARMCC::AL;
81  }
82
83  bool PredicateInstruction(MachineInstr *MI,
84                    const SmallVectorImpl<MachineOperand> &Pred) const override;
85
86  bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
87                   const SmallVectorImpl<MachineOperand> &Pred2) const override;
88
89  bool DefinesPredicate(MachineInstr *MI,
90                        std::vector<MachineOperand> &Pred) const override;
91
92  bool isPredicable(MachineInstr *MI) const override;
93
94  /// GetInstSize - Returns the size of the specified MachineInstr.
95  ///
96  virtual unsigned GetInstSizeInBytes(const MachineInstr* MI) const;
97
98  unsigned isLoadFromStackSlot(const MachineInstr *MI,
99                               int &FrameIndex) const override;
100  unsigned isStoreToStackSlot(const MachineInstr *MI,
101                              int &FrameIndex) const override;
102  unsigned isLoadFromStackSlotPostFE(const MachineInstr *MI,
103                                     int &FrameIndex) const override;
104  unsigned isStoreToStackSlotPostFE(const MachineInstr *MI,
105                                    int &FrameIndex) const override;
106
107  void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
108                   DebugLoc DL, unsigned DestReg, unsigned SrcReg,
109                   bool KillSrc) const override;
110
111  void storeRegToStackSlot(MachineBasicBlock &MBB,
112                           MachineBasicBlock::iterator MBBI,
113                           unsigned SrcReg, bool isKill, int FrameIndex,
114                           const TargetRegisterClass *RC,
115                           const TargetRegisterInfo *TRI) const override;
116
117  void loadRegFromStackSlot(MachineBasicBlock &MBB,
118                            MachineBasicBlock::iterator MBBI,
119                            unsigned DestReg, int FrameIndex,
120                            const TargetRegisterClass *RC,
121                            const TargetRegisterInfo *TRI) const override;
122
123  bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const override;
124
125  void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
126                     unsigned DestReg, unsigned SubIdx,
127                     const MachineInstr *Orig,
128                     const TargetRegisterInfo &TRI) const override;
129
130  MachineInstr *duplicate(MachineInstr *Orig,
131                          MachineFunction &MF) const override;
132
133  MachineInstr *commuteInstruction(MachineInstr*,
134                                   bool=false) const override;
135
136  const MachineInstrBuilder &AddDReg(MachineInstrBuilder &MIB, unsigned Reg,
137                                     unsigned SubIdx, unsigned State,
138                                     const TargetRegisterInfo *TRI) const;
139
140  bool produceSameValue(const MachineInstr *MI0, const MachineInstr *MI1,
141                        const MachineRegisterInfo *MRI) const override;
142
143  /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to
144  /// determine if two loads are loading from the same base address. It should
145  /// only return true if the base pointers are the same and the only
146  /// differences between the two addresses is the offset. It also returns the
147  /// offsets by reference.
148  bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, int64_t &Offset1,
149                               int64_t &Offset2) const override;
150
151  /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to
152  /// determine (in conjunction with areLoadsFromSameBasePtr) if two loads
153  /// should be scheduled togther. On some targets if two loads are loading from
154  /// addresses in the same cache line, it's better if they are scheduled
155  /// together. This function takes two integers that represent the load offsets
156  /// from the common base address. It returns true if it decides it's desirable
157  /// to schedule the two loads together. "NumLoads" is the number of loads that
158  /// have already been scheduled after Load1.
159  bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
160                               int64_t Offset1, int64_t Offset2,
161                               unsigned NumLoads) const override;
162
163  bool isSchedulingBoundary(const MachineInstr *MI,
164                            const MachineBasicBlock *MBB,
165                            const MachineFunction &MF) const override;
166
167  bool isProfitableToIfCvt(MachineBasicBlock &MBB,
168                           unsigned NumCycles, unsigned ExtraPredCycles,
169                           const BranchProbability &Probability) const override;
170
171  bool isProfitableToIfCvt(MachineBasicBlock &TMBB, unsigned NumT,
172                           unsigned ExtraT, MachineBasicBlock &FMBB,
173                           unsigned NumF, unsigned ExtraF,
174                           const BranchProbability &Probability) const override;
175
176  bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
177                          const BranchProbability &Probability) const override {
178    return NumCycles == 1;
179  }
180
181  bool isProfitableToUnpredicate(MachineBasicBlock &TMBB,
182                                 MachineBasicBlock &FMBB) const override;
183
184  /// analyzeCompare - For a comparison instruction, return the source registers
185  /// in SrcReg and SrcReg2 if having two register operands, and the value it
186  /// compares against in CmpValue. Return true if the comparison instruction
187  /// can be analyzed.
188  bool analyzeCompare(const MachineInstr *MI, unsigned &SrcReg,
189                      unsigned &SrcReg2, int &CmpMask,
190                      int &CmpValue) const override;
191
192  /// optimizeCompareInstr - Convert the instruction to set the zero flag so
193  /// that we can remove a "comparison with zero"; Remove a redundant CMP
194  /// instruction if the flags can be updated in the same way by an earlier
195  /// instruction such as SUB.
196  bool optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg,
197                            unsigned SrcReg2, int CmpMask, int CmpValue,
198                            const MachineRegisterInfo *MRI) const override;
199
200  bool analyzeSelect(const MachineInstr *MI,
201                     SmallVectorImpl<MachineOperand> &Cond,
202                     unsigned &TrueOp, unsigned &FalseOp,
203                     bool &Optimizable) const override;
204
205  MachineInstr *optimizeSelect(MachineInstr *MI, bool) const override;
206
207  /// FoldImmediate - 'Reg' is known to be defined by a move immediate
208  /// instruction, try to fold the immediate into the use instruction.
209  bool FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI,
210                     unsigned Reg, MachineRegisterInfo *MRI) const override;
211
212  unsigned getNumMicroOps(const InstrItineraryData *ItinData,
213                          const MachineInstr *MI) const override;
214
215  int getOperandLatency(const InstrItineraryData *ItinData,
216                        const MachineInstr *DefMI, unsigned DefIdx,
217                        const MachineInstr *UseMI,
218                        unsigned UseIdx) const override;
219  int getOperandLatency(const InstrItineraryData *ItinData,
220                        SDNode *DefNode, unsigned DefIdx,
221                        SDNode *UseNode, unsigned UseIdx) const override;
222
223  /// VFP/NEON execution domains.
224  std::pair<uint16_t, uint16_t>
225  getExecutionDomain(const MachineInstr *MI) const override;
226  void setExecutionDomain(MachineInstr *MI, unsigned Domain) const override;
227
228  unsigned getPartialRegUpdateClearance(const MachineInstr*, unsigned,
229                                      const TargetRegisterInfo*) const override;
230  void breakPartialRegDependency(MachineBasicBlock::iterator, unsigned,
231                                 const TargetRegisterInfo *TRI) const override;
232  /// Get the number of addresses by LDM or VLDM or zero for unknown.
233  unsigned getNumLDMAddresses(const MachineInstr *MI) const;
234
235private:
236  unsigned getInstBundleLength(const MachineInstr *MI) const;
237
238  int getVLDMDefCycle(const InstrItineraryData *ItinData,
239                      const MCInstrDesc &DefMCID,
240                      unsigned DefClass,
241                      unsigned DefIdx, unsigned DefAlign) const;
242  int getLDMDefCycle(const InstrItineraryData *ItinData,
243                     const MCInstrDesc &DefMCID,
244                     unsigned DefClass,
245                     unsigned DefIdx, unsigned DefAlign) const;
246  int getVSTMUseCycle(const InstrItineraryData *ItinData,
247                      const MCInstrDesc &UseMCID,
248                      unsigned UseClass,
249                      unsigned UseIdx, unsigned UseAlign) const;
250  int getSTMUseCycle(const InstrItineraryData *ItinData,
251                     const MCInstrDesc &UseMCID,
252                     unsigned UseClass,
253                     unsigned UseIdx, unsigned UseAlign) const;
254  int getOperandLatency(const InstrItineraryData *ItinData,
255                        const MCInstrDesc &DefMCID,
256                        unsigned DefIdx, unsigned DefAlign,
257                        const MCInstrDesc &UseMCID,
258                        unsigned UseIdx, unsigned UseAlign) const;
259
260  unsigned getPredicationCost(const MachineInstr *MI) const override;
261
262  unsigned getInstrLatency(const InstrItineraryData *ItinData,
263                           const MachineInstr *MI,
264                           unsigned *PredCost = nullptr) const override;
265
266  int getInstrLatency(const InstrItineraryData *ItinData,
267                      SDNode *Node) const override;
268
269  bool hasHighOperandLatency(const InstrItineraryData *ItinData,
270                             const MachineRegisterInfo *MRI,
271                             const MachineInstr *DefMI, unsigned DefIdx,
272                             const MachineInstr *UseMI,
273                             unsigned UseIdx) const override;
274  bool hasLowDefLatency(const InstrItineraryData *ItinData,
275                        const MachineInstr *DefMI,
276                        unsigned DefIdx) const override;
277
278  /// verifyInstruction - Perform target specific instruction verification.
279  bool verifyInstruction(const MachineInstr *MI,
280                         StringRef &ErrInfo) const override;
281
282private:
283  /// Modeling special VFP / NEON fp MLA / MLS hazards.
284
285  /// MLxEntryMap - Map fp MLA / MLS to the corresponding entry in the internal
286  /// MLx table.
287  DenseMap<unsigned, unsigned> MLxEntryMap;
288
289  /// MLxHazardOpcodes - Set of add / sub and multiply opcodes that would cause
290  /// stalls when scheduled together with fp MLA / MLS opcodes.
291  SmallSet<unsigned, 16> MLxHazardOpcodes;
292
293public:
294  /// isFpMLxInstruction - Return true if the specified opcode is a fp MLA / MLS
295  /// instruction.
296  bool isFpMLxInstruction(unsigned Opcode) const {
297    return MLxEntryMap.count(Opcode);
298  }
299
300  /// isFpMLxInstruction - This version also returns the multiply opcode and the
301  /// addition / subtraction opcode to expand to. Return true for 'HasLane' for
302  /// the MLX instructions with an extra lane operand.
303  bool isFpMLxInstruction(unsigned Opcode, unsigned &MulOpc,
304                          unsigned &AddSubOpc, bool &NegAcc,
305                          bool &HasLane) const;
306
307  /// canCauseFpMLxStall - Return true if an instruction of the specified opcode
308  /// will cause stalls when scheduled after (within 4-cycle window) a fp
309  /// MLA / MLS instruction.
310  bool canCauseFpMLxStall(unsigned Opcode) const {
311    return MLxHazardOpcodes.count(Opcode);
312  }
313
314  /// Returns true if the instruction has a shift by immediate that can be
315  /// executed in one cycle less.
316  bool isSwiftFastImmShift(const MachineInstr *MI) const;
317};
318
319static inline
320const MachineInstrBuilder &AddDefaultPred(const MachineInstrBuilder &MIB) {
321  return MIB.addImm((int64_t)ARMCC::AL).addReg(0);
322}
323
324static inline
325const MachineInstrBuilder &AddDefaultCC(const MachineInstrBuilder &MIB) {
326  return MIB.addReg(0);
327}
328
329static inline
330const MachineInstrBuilder &AddDefaultT1CC(const MachineInstrBuilder &MIB,
331                                          bool isDead = false) {
332  return MIB.addReg(ARM::CPSR, getDefRegState(true) | getDeadRegState(isDead));
333}
334
335static inline
336const MachineInstrBuilder &AddNoT1CC(const MachineInstrBuilder &MIB) {
337  return MIB.addReg(0);
338}
339
340static inline
341bool isUncondBranchOpcode(int Opc) {
342  return Opc == ARM::B || Opc == ARM::tB || Opc == ARM::t2B;
343}
344
345static inline
346bool isCondBranchOpcode(int Opc) {
347  return Opc == ARM::Bcc || Opc == ARM::tBcc || Opc == ARM::t2Bcc;
348}
349
350static inline
351bool isJumpTableBranchOpcode(int Opc) {
352  return Opc == ARM::BR_JTr || Opc == ARM::BR_JTm || Opc == ARM::BR_JTadd ||
353    Opc == ARM::tBR_JTr || Opc == ARM::t2BR_JT;
354}
355
356static inline
357bool isIndirectBranchOpcode(int Opc) {
358  return Opc == ARM::BX || Opc == ARM::MOVPCRX || Opc == ARM::tBRIND;
359}
360
361static inline bool isPopOpcode(int Opc) {
362  return Opc == ARM::tPOP_RET || Opc == ARM::LDMIA_RET ||
363         Opc == ARM::t2LDMIA_RET || Opc == ARM::tPOP || Opc == ARM::LDMIA_UPD ||
364         Opc == ARM::t2LDMIA_UPD || Opc == ARM::VLDMDIA_UPD;
365}
366
367static inline bool isPushOpcode(int Opc) {
368  return Opc == ARM::tPUSH || Opc == ARM::t2STMDB_UPD ||
369         Opc == ARM::STMDB_UPD || Opc == ARM::VSTMDDB_UPD;
370}
371
372/// getInstrPredicate - If instruction is predicated, returns its predicate
373/// condition, otherwise returns AL. It also returns the condition code
374/// register by reference.
375ARMCC::CondCodes getInstrPredicate(const MachineInstr *MI, unsigned &PredReg);
376
377int getMatchingCondBranchOpcode(int Opc);
378
379/// Determine if MI can be folded into an ARM MOVCC instruction, and return the
380/// opcode of the SSA instruction representing the conditional MI.
381unsigned canFoldARMInstrIntoMOVCC(unsigned Reg,
382                                  MachineInstr *&MI,
383                                  const MachineRegisterInfo &MRI);
384
385/// Map pseudo instructions that imply an 'S' bit onto real opcodes. Whether
386/// the instruction is encoded with an 'S' bit is determined by the optional
387/// CPSR def operand.
388unsigned convertAddSubFlagsOpcode(unsigned OldOpc);
389
390/// emitARMRegPlusImmediate / emitT2RegPlusImmediate - Emits a series of
391/// instructions to materializea destreg = basereg + immediate in ARM / Thumb2
392/// code.
393void emitARMRegPlusImmediate(MachineBasicBlock &MBB,
394                             MachineBasicBlock::iterator &MBBI, DebugLoc dl,
395                             unsigned DestReg, unsigned BaseReg, int NumBytes,
396                             ARMCC::CondCodes Pred, unsigned PredReg,
397                             const ARMBaseInstrInfo &TII, unsigned MIFlags = 0);
398
399void emitT2RegPlusImmediate(MachineBasicBlock &MBB,
400                            MachineBasicBlock::iterator &MBBI, DebugLoc dl,
401                            unsigned DestReg, unsigned BaseReg, int NumBytes,
402                            ARMCC::CondCodes Pred, unsigned PredReg,
403                            const ARMBaseInstrInfo &TII, unsigned MIFlags = 0);
404void emitThumbRegPlusImmediate(MachineBasicBlock &MBB,
405                               MachineBasicBlock::iterator &MBBI, DebugLoc dl,
406                               unsigned DestReg, unsigned BaseReg,
407                               int NumBytes, const TargetInstrInfo &TII,
408                               const ARMBaseRegisterInfo& MRI,
409                               unsigned MIFlags = 0);
410
411/// Tries to add registers to the reglist of a given base-updating
412/// push/pop instruction to adjust the stack by an additional
413/// NumBytes. This can save a few bytes per function in code-size, but
414/// obviously generates more memory traffic. As such, it only takes
415/// effect in functions being optimised for size.
416bool tryFoldSPUpdateIntoPushPop(const ARMSubtarget &Subtarget,
417                                MachineFunction &MF, MachineInstr *MI,
418                                unsigned NumBytes);
419
420/// rewriteARMFrameIndex / rewriteT2FrameIndex -
421/// Rewrite MI to access 'Offset' bytes from the FP. Return false if the
422/// offset could not be handled directly in MI, and return the left-over
423/// portion by reference.
424bool rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
425                          unsigned FrameReg, int &Offset,
426                          const ARMBaseInstrInfo &TII);
427
428bool rewriteT2FrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
429                         unsigned FrameReg, int &Offset,
430                         const ARMBaseInstrInfo &TII);
431
432} // End llvm namespace
433
434#endif
435