ARMBaseInstrInfo.h revision fc17fb0aeed584b8560461ab2843d0676a243f29 
1//===- ARMBaseInstrInfo.h - ARM Base Instruction Information -------------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the Base ARM implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef ARMBASEINSTRUCTIONINFO_H
15#define ARMBASEINSTRUCTIONINFO_H
16
17#include "ARM.h"
18#include "ARMRegisterInfo.h"
19#include "llvm/CodeGen/MachineInstrBuilder.h"
20#include "llvm/Target/TargetInstrInfo.h"
21
22namespace llvm {
23  class ARMSubtarget;
24
25/// ARMII - This namespace holds all of the target specific flags that
26/// instruction info tracks.
27///
28namespace ARMII {
29  enum {
30    //===------------------------------------------------------------------===//
31    // Instruction Flags.
32
33    //===------------------------------------------------------------------===//
34    // This four-bit field describes the addressing mode used.
35
36    AddrModeMask  = 0xf,
37    AddrModeNone    = 0,
38    AddrMode1       = 1,
39    AddrMode2       = 2,
40    AddrMode3       = 3,
41    AddrMode4       = 4,
42    AddrMode5       = 5,
43    AddrMode6       = 6,
44    AddrModeT1_1    = 7,
45    AddrModeT1_2    = 8,
46    AddrModeT1_4    = 9,
47    AddrModeT1_s    = 10, // i8 * 4 for pc and sp relative data
48    AddrModeT2_i12  = 11,
49    AddrModeT2_i8   = 12,
50    AddrModeT2_so   = 13,
51    AddrModeT2_pc   = 14, // +/- i12 for pc relative data
52    AddrModeT2_i8s4 = 15, // i8 * 4
53
54    // Size* - Flags to keep track of the size of an instruction.
55    SizeShift     = 4,
56    SizeMask      = 7 << SizeShift,
57    SizeSpecial   = 1,   // 0 byte pseudo or special case.
58    Size8Bytes    = 2,
59    Size4Bytes    = 3,
60    Size2Bytes    = 4,
61
62    // IndexMode - Unindex, pre-indexed, or post-indexed. Only valid for load
63    // and store ops
64    IndexModeShift = 7,
65    IndexModeMask  = 3 << IndexModeShift,
66    IndexModePre   = 1,
67    IndexModePost  = 2,
68
69    //===------------------------------------------------------------------===//
70    // Instruction encoding formats.
71    //
72    FormShift     = 9,
73    FormMask      = 0x3f << FormShift,
74
75    // Pseudo instructions
76    Pseudo        = 0  << FormShift,
77
78    // Multiply instructions
79    MulFrm        = 1  << FormShift,
80
81    // Branch instructions
82    BrFrm         = 2  << FormShift,
83    BrMiscFrm     = 3  << FormShift,
84
85    // Data Processing instructions
86    DPFrm         = 4  << FormShift,
87    DPSoRegFrm    = 5  << FormShift,
88
89    // Load and Store
90    LdFrm         = 6  << FormShift,
91    StFrm         = 7  << FormShift,
92    LdMiscFrm     = 8  << FormShift,
93    StMiscFrm     = 9  << FormShift,
94    LdStMulFrm    = 10 << FormShift,
95
96    // Miscellaneous arithmetic instructions
97    ArithMiscFrm  = 11 << FormShift,
98
99    // Extend instructions
100    ExtFrm        = 12 << FormShift,
101
102    // VFP formats
103    VFPUnaryFrm   = 13 << FormShift,
104    VFPBinaryFrm  = 14 << FormShift,
105    VFPConv1Frm   = 15 << FormShift,
106    VFPConv2Frm   = 16 << FormShift,
107    VFPConv3Frm   = 17 << FormShift,
108    VFPConv4Frm   = 18 << FormShift,
109    VFPConv5Frm   = 19 << FormShift,
110    VFPLdStFrm    = 20 << FormShift,
111    VFPLdStMulFrm = 21 << FormShift,
112    VFPMiscFrm    = 22 << FormShift,
113
114    // Thumb format
115    ThumbFrm      = 23 << FormShift,
116
117    // NEON format
118    NEONFrm       = 24 << FormShift,
119    NEONGetLnFrm  = 25 << FormShift,
120    NEONSetLnFrm  = 26 << FormShift,
121    NEONDupFrm    = 27 << FormShift,
122
123    //===------------------------------------------------------------------===//
124    // Misc flags.
125
126    // UnaryDP - Indicates this is a unary data processing instruction, i.e.
127    // it doesn't have a Rn operand.
128    UnaryDP       = 1 << 15,
129
130    // Xform16Bit - Indicates this Thumb2 instruction may be transformed into
131    // a 16-bit Thumb instruction if certain conditions are met.
132    Xform16Bit    = 1 << 16,
133
134    //===------------------------------------------------------------------===//
135    // Field shifts - such shifts are used to set field while generating
136    // machine instructions.
137    M_BitShift     = 5,
138    ShiftImmShift  = 5,
139    ShiftShift     = 7,
140    N_BitShift     = 7,
141    ImmHiShift     = 8,
142    SoRotImmShift  = 8,
143    RegRsShift     = 8,
144    ExtRotImmShift = 10,
145    RegRdLoShift   = 12,
146    RegRdShift     = 12,
147    RegRdHiShift   = 16,
148    RegRnShift     = 16,
149    S_BitShift     = 20,
150    W_BitShift     = 21,
151    AM3_I_BitShift = 22,
152    D_BitShift     = 22,
153    U_BitShift     = 23,
154    P_BitShift     = 24,
155    I_BitShift     = 25,
156    CondShift      = 28
157  };
158
159  /// ARMII::Op - Holds all of the instruction types required by
160  /// target specific instruction and register code.  ARMBaseInstrInfo
161  /// and subclasses should return a specific opcode that implements
162  /// the instruction type.
163  ///
164  enum Op {
165    ADDri,
166    ADDrs,
167    ADDrr,
168    MOVr,
169    SUBri,
170    SUBrs,
171    SUBrr
172  };
173}
174
175static inline
176const MachineInstrBuilder &AddDefaultPred(const MachineInstrBuilder &MIB) {
177  return MIB.addImm((int64_t)ARMCC::AL).addReg(0);
178}
179
180static inline
181const MachineInstrBuilder &AddDefaultCC(const MachineInstrBuilder &MIB) {
182  return MIB.addReg(0);
183}
184
185static inline
186const MachineInstrBuilder &AddDefaultT1CC(const MachineInstrBuilder &MIB) {
187  return MIB.addReg(ARM::CPSR);
188}
189
190class ARMBaseInstrInfo : public TargetInstrInfoImpl {
191  const ARMSubtarget &STI;
192
193protected:
194  // Can be only subclassed.
195  explicit ARMBaseInstrInfo(const ARMSubtarget &sti);
196public:
197  // Return the non-pre/post incrementing version of 'Opc'. Return 0
198  // if there is not such an opcode.
199  virtual unsigned getUnindexedOpcode(unsigned Opc) const =0;
200
201  // Return the opcode that implements 'Op', or 0 if no opcode
202  virtual unsigned getOpcode(ARMII::Op Op) const =0;
203
204  // Return true if the block does not fall through.
205  virtual bool BlockHasNoFallThrough(const MachineBasicBlock &MBB) const =0;
206
207  virtual MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI,
208                                              MachineBasicBlock::iterator &MBBI,
209                                              LiveVariables *LV) const;
210
211  virtual const ARMBaseRegisterInfo &getRegisterInfo() const =0;
212
213  // Branch analysis.
214  virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
215                             MachineBasicBlock *&FBB,
216                             SmallVectorImpl<MachineOperand> &Cond,
217                             bool AllowModify) const;
218  virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
219  virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
220                                MachineBasicBlock *FBB,
221                            const SmallVectorImpl<MachineOperand> &Cond) const;
222
223  virtual
224  bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
225
226  // Predication support.
227  bool isPredicated(const MachineInstr *MI) const {
228    int PIdx = MI->findFirstPredOperandIdx();
229    return PIdx != -1 && MI->getOperand(PIdx).getImm() != ARMCC::AL;
230  }
231
232  ARMCC::CondCodes getPredicate(const MachineInstr *MI) const {
233    int PIdx = MI->findFirstPredOperandIdx();
234    return PIdx != -1 ? (ARMCC::CondCodes)MI->getOperand(PIdx).getImm()
235                      : ARMCC::AL;
236  }
237
238  virtual
239  bool PredicateInstruction(MachineInstr *MI,
240                            const SmallVectorImpl<MachineOperand> &Pred) const;
241
242  virtual
243  bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
244                         const SmallVectorImpl<MachineOperand> &Pred2) const;
245
246  virtual bool DefinesPredicate(MachineInstr *MI,
247                                std::vector<MachineOperand> &Pred) const;
248
249  /// GetInstSize - Returns the size of the specified MachineInstr.
250  ///
251  virtual unsigned GetInstSizeInBytes(const MachineInstr* MI) const;
252
253  /// Return true if the instruction is a register to register move and return
254  /// the source and dest operands and their sub-register indices by reference.
255  virtual bool isMoveInstr(const MachineInstr &MI,
256                           unsigned &SrcReg, unsigned &DstReg,
257                           unsigned &SrcSubIdx, unsigned &DstSubIdx) const;
258
259  virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
260                                       int &FrameIndex) const;
261  virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
262                                      int &FrameIndex) const;
263
264  virtual bool copyRegToReg(MachineBasicBlock &MBB,
265                            MachineBasicBlock::iterator I,
266                            unsigned DestReg, unsigned SrcReg,
267                            const TargetRegisterClass *DestRC,
268                            const TargetRegisterClass *SrcRC) const;
269
270  virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
271                                   MachineBasicBlock::iterator MBBI,
272                                   unsigned SrcReg, bool isKill, int FrameIndex,
273                                   const TargetRegisterClass *RC) const;
274
275  virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
276                                    MachineBasicBlock::iterator MBBI,
277                                    unsigned DestReg, int FrameIndex,
278                                    const TargetRegisterClass *RC) const;
279
280  virtual bool canFoldMemoryOperand(const MachineInstr *MI,
281                                    const SmallVectorImpl<unsigned> &Ops) const;
282
283  virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
284                                              MachineInstr* MI,
285                                              const SmallVectorImpl<unsigned> &Ops,
286                                              int FrameIndex) const;
287
288  virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
289                                              MachineInstr* MI,
290                                              const SmallVectorImpl<unsigned> &Ops,
291                                              MachineInstr* LoadMI) const;
292
293private:
294  bool isUncondBranchOpcode(int Opc) const {
295    return Opc == ARM::B || Opc == ARM::tB || Opc == ARM::t2B;
296  }
297
298  bool isCondBranchOpcode(int Opc) const {
299    return Opc == ARM::Bcc || Opc == ARM::tBcc || Opc == ARM::t2Bcc;
300  }
301
302  bool isJumpTableBranchOpcode(int Opc) const {
303    return Opc == ARM::BR_JTr || Opc == ARM::BR_JTm || Opc == ARM::BR_JTadd ||
304      Opc == ARM::tBR_JTr || Opc == ARM::t2BR_JT;
305  }
306
307  int getMatchingCondBranchOpcode(int Opc) const;
308};
309}
310
311#endif
312