ARMCallingConv.td revision c73158730d43e7c8bdef32b2107566a6e78a8538 
1//===- ARMCallingConv.td - Calling Conventions for ARM -----*- tablegen -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9// This describes the calling conventions for ARM architecture.
10//===----------------------------------------------------------------------===//
11
12/// CCIfSubtarget - Match if the current subtarget has a feature F.
13class CCIfSubtarget<string F, CCAction A>:
14  CCIf<!strconcat("State.getTarget().getSubtarget<ARMSubtarget>().", F), A>;
15
16/// CCIfAlign - Match of the original alignment of the arg
17class CCIfAlign<string Align, CCAction A>:
18  CCIf<!strconcat("ArgFlags.getOrigAlign() == ", Align), A>;
19
20//===----------------------------------------------------------------------===//
21// ARM APCS Calling Convention
22//===----------------------------------------------------------------------===//
23def CC_ARM_APCS : CallingConv<[
24
25  // Handles byval parameters.
26  CCIfByVal<CCPassByVal<4, 4>>,
27    
28  CCIfType<[i8, i16], CCPromoteToType<i32>>,
29
30  // Handle all vector types as either f64 or v2f64.
31  CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>,
32  CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
33
34  // f64 and v2f64 are passed in adjacent GPRs, possibly split onto the stack
35  CCIfType<[f64, v2f64], CCCustom<"CC_ARM_APCS_Custom_f64">>,
36
37  CCIfType<[f32], CCBitConvertToType<i32>>,
38  CCIfType<[i32], CCAssignToReg<[R0, R1, R2, R3]>>,
39
40  CCIfType<[i32], CCAssignToStack<4, 4>>,
41  CCIfType<[f64], CCAssignToStack<8, 4>>,
42  CCIfType<[v2f64], CCAssignToStack<16, 4>>
43]>;
44
45def RetCC_ARM_APCS : CallingConv<[
46  CCIfType<[f32], CCBitConvertToType<i32>>,
47
48  // Handle all vector types as either f64 or v2f64.
49  CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>,
50  CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
51
52  CCIfType<[f64, v2f64], CCCustom<"RetCC_ARM_APCS_Custom_f64">>,
53
54  CCIfType<[i32], CCAssignToReg<[R0, R1, R2, R3]>>,
55  CCIfType<[i64], CCAssignToRegWithShadow<[R0, R2], [R1, R3]>>
56]>;
57
58//===----------------------------------------------------------------------===//
59// ARM APCS Calling Convention for FastCC (when VFP2 or later is available)
60//===----------------------------------------------------------------------===//
61def FastCC_ARM_APCS : CallingConv<[
62  // Handle all vector types as either f64 or v2f64.
63  CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>,
64  CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
65
66  CCIfType<[v2f64], CCAssignToReg<[Q0, Q1, Q2, Q3]>>,
67  CCIfType<[f64], CCAssignToReg<[D0, D1, D2, D3, D4, D5, D6, D7]>>,
68  CCIfType<[f32], CCAssignToReg<[S0, S1, S2, S3, S4, S5, S6, S7, S8,
69                                 S9, S10, S11, S12, S13, S14, S15]>>,
70  CCDelegateTo<CC_ARM_APCS>
71]>;
72
73def RetFastCC_ARM_APCS : CallingConv<[
74  // Handle all vector types as either f64 or v2f64.
75  CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>,
76  CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
77
78  CCIfType<[v2f64], CCAssignToReg<[Q0, Q1, Q2, Q3]>>,
79  CCIfType<[f64], CCAssignToReg<[D0, D1, D2, D3, D4, D5, D6, D7]>>,
80  CCIfType<[f32], CCAssignToReg<[S0, S1, S2, S3, S4, S5, S6, S7, S8,
81                                 S9, S10, S11, S12, S13, S14, S15]>>,
82  CCDelegateTo<RetCC_ARM_APCS>
83]>;
84
85
86//===----------------------------------------------------------------------===//
87// ARM AAPCS (EABI) Calling Convention, common parts
88//===----------------------------------------------------------------------===//
89
90def CC_ARM_AAPCS_Common : CallingConv<[
91
92  CCIfType<[i8, i16], CCPromoteToType<i32>>,
93
94  // i64/f64 is passed in even pairs of GPRs
95  // i64 is 8-aligned i32 here, so we may need to eat R1 as a pad register
96  // (and the same is true for f64 if VFP is not enabled)
97  CCIfType<[i32], CCIfAlign<"8", CCAssignToRegWithShadow<[R0, R2], [R0, R1]>>>,
98  CCIfType<[i32], CCIf<"State.getNextStackOffset() == 0 &&"
99                       "ArgFlags.getOrigAlign() != 8",
100                       CCAssignToReg<[R0, R1, R2, R3]>>>,
101
102  CCIfType<[i32], CCIfAlign<"8", CCAssignToStackWithShadow<4, 8, R3>>>,
103  CCIfType<[i32, f32], CCAssignToStack<4, 4>>,
104  CCIfType<[f64], CCAssignToStack<8, 8>>,
105  CCIfType<[v2f64], CCAssignToStack<16, 8>>
106]>;
107
108def RetCC_ARM_AAPCS_Common : CallingConv<[
109  CCIfType<[i32], CCAssignToReg<[R0, R1, R2, R3]>>,
110  CCIfType<[i64], CCAssignToRegWithShadow<[R0, R2], [R1, R3]>>
111]>;
112
113//===----------------------------------------------------------------------===//
114// ARM AAPCS (EABI) Calling Convention
115//===----------------------------------------------------------------------===//
116
117def CC_ARM_AAPCS : CallingConv<[
118  // Handle all vector types as either f64 or v2f64.
119  CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>,
120  CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
121
122  CCIfType<[f64, v2f64], CCCustom<"CC_ARM_AAPCS_Custom_f64">>,
123  CCIfType<[f32], CCBitConvertToType<i32>>,
124  CCDelegateTo<CC_ARM_AAPCS_Common>
125]>;
126
127def RetCC_ARM_AAPCS : CallingConv<[
128  // Handle all vector types as either f64 or v2f64.
129  CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>,
130  CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
131
132  CCIfType<[f64, v2f64], CCCustom<"RetCC_ARM_AAPCS_Custom_f64">>,
133  CCIfType<[f32], CCBitConvertToType<i32>>,
134  CCDelegateTo<RetCC_ARM_AAPCS_Common>
135]>;
136
137//===----------------------------------------------------------------------===//
138// ARM AAPCS-VFP (EABI) Calling Convention
139// Also used for FastCC (when VFP2 or later is available)
140//===----------------------------------------------------------------------===//
141
142def CC_ARM_AAPCS_VFP : CallingConv<[
143  // Handle all vector types as either f64 or v2f64.
144  CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>,
145  CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
146
147  CCIfType<[v2f64], CCAssignToReg<[Q0, Q1, Q2, Q3]>>,
148  CCIfType<[f64], CCAssignToReg<[D0, D1, D2, D3, D4, D5, D6, D7]>>,
149  CCIfType<[f32], CCAssignToReg<[S0, S1, S2, S3, S4, S5, S6, S7, S8,
150                                 S9, S10, S11, S12, S13, S14, S15]>>,
151  CCDelegateTo<CC_ARM_AAPCS_Common>
152]>;
153
154def RetCC_ARM_AAPCS_VFP : CallingConv<[
155  // Handle all vector types as either f64 or v2f64.
156  CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>,
157  CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
158
159  CCIfType<[v2f64], CCAssignToReg<[Q0, Q1, Q2, Q3]>>,
160  CCIfType<[f64], CCAssignToReg<[D0, D1, D2, D3, D4, D5, D6, D7]>>,
161  CCIfType<[f32], CCAssignToReg<[S0, S1, S2, S3, S4, S5, S6, S7, S8,
162                                 S9, S10, S11, S12, S13, S14, S15]>>,
163  CCDelegateTo<RetCC_ARM_AAPCS_Common>
164]>;
165