ARMCodeEmitter.cpp revision 08baddbc0708d6965b72b40aa3c1f40b56a31835 
1//===-- ARM/ARMCodeEmitter.cpp - Convert ARM code to machine code ---------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the pass that transforms the ARM machine instructions into
11// relocatable machine code.
12//
13//===----------------------------------------------------------------------===//
14
15#define DEBUG_TYPE "jit"
16#include "ARM.h"
17#include "ARMAddressingModes.h"
18#include "ARMConstantPoolValue.h"
19#include "ARMInstrInfo.h"
20#include "ARMRelocations.h"
21#include "ARMSubtarget.h"
22#include "ARMTargetMachine.h"
23#include "llvm/Constants.h"
24#include "llvm/DerivedTypes.h"
25#include "llvm/Function.h"
26#include "llvm/PassManager.h"
27#include "llvm/CodeGen/JITCodeEmitter.h"
28#include "llvm/CodeGen/MachineConstantPool.h"
29#include "llvm/CodeGen/MachineFunctionPass.h"
30#include "llvm/CodeGen/MachineInstr.h"
31#include "llvm/CodeGen/MachineJumpTableInfo.h"
32#include "llvm/CodeGen/MachineModuleInfo.h"
33#include "llvm/CodeGen/Passes.h"
34#include "llvm/ADT/Statistic.h"
35#include "llvm/Support/Debug.h"
36#include "llvm/Support/ErrorHandling.h"
37#include "llvm/Support/raw_ostream.h"
38#ifndef NDEBUG
39#include <iomanip>
40#endif
41using namespace llvm;
42
43STATISTIC(NumEmitted, "Number of machine instructions emitted");
44
45namespace {
46
47  class ARMCodeEmitter : public MachineFunctionPass {
48    ARMJITInfo                *JTI;
49    const ARMInstrInfo        *II;
50    const TargetData          *TD;
51    const ARMSubtarget        *Subtarget;
52    TargetMachine             &TM;
53    JITCodeEmitter            &MCE;
54    MachineModuleInfo *MMI;
55    const std::vector<MachineConstantPoolEntry> *MCPEs;
56    const std::vector<MachineJumpTableEntry> *MJTEs;
57    bool IsPIC;
58
59    void getAnalysisUsage(AnalysisUsage &AU) const {
60      AU.addRequired<MachineModuleInfo>();
61      MachineFunctionPass::getAnalysisUsage(AU);
62    }
63
64    static char ID;
65  public:
66    ARMCodeEmitter(TargetMachine &tm, JITCodeEmitter &mce)
67      : MachineFunctionPass(&ID), JTI(0),
68        II((const ARMInstrInfo *)tm.getInstrInfo()),
69        TD(tm.getTargetData()), TM(tm),
70    MCE(mce), MCPEs(0), MJTEs(0),
71    IsPIC(TM.getRelocationModel() == Reloc::PIC_) {}
72
73    /// getBinaryCodeForInstr - This function, generated by the
74    /// CodeEmitterGenerator using TableGen, produces the binary encoding for
75    /// machine instructions.
76    unsigned getBinaryCodeForInstr(const MachineInstr &MI);
77
78    bool runOnMachineFunction(MachineFunction &MF);
79
80    virtual const char *getPassName() const {
81      return "ARM Machine Code Emitter";
82    }
83
84    void emitInstruction(const MachineInstr &MI);
85
86  private:
87
88    void emitWordLE(unsigned Binary);
89    void emitDWordLE(uint64_t Binary);
90    void emitConstPoolInstruction(const MachineInstr &MI);
91    void emitMOVi32immInstruction(const MachineInstr &MI);
92    void emitMOVi2piecesInstruction(const MachineInstr &MI);
93    void emitLEApcrelJTInstruction(const MachineInstr &MI);
94    void emitPseudoMoveInstruction(const MachineInstr &MI);
95    void addPCLabel(unsigned LabelID);
96    void emitPseudoInstruction(const MachineInstr &MI);
97    unsigned getMachineSoRegOpValue(const MachineInstr &MI,
98                                    const TargetInstrDesc &TID,
99                                    const MachineOperand &MO,
100                                    unsigned OpIdx);
101
102    unsigned getMachineSoImmOpValue(unsigned SoImm);
103
104    unsigned getAddrModeSBit(const MachineInstr &MI,
105                             const TargetInstrDesc &TID) const;
106
107    void emitDataProcessingInstruction(const MachineInstr &MI,
108                                       unsigned ImplicitRd = 0,
109                                       unsigned ImplicitRn = 0);
110
111    void emitLoadStoreInstruction(const MachineInstr &MI,
112                                  unsigned ImplicitRd = 0,
113                                  unsigned ImplicitRn = 0);
114
115    void emitMiscLoadStoreInstruction(const MachineInstr &MI,
116                                      unsigned ImplicitRn = 0);
117
118    void emitLoadStoreMultipleInstruction(const MachineInstr &MI);
119
120    void emitMulFrmInstruction(const MachineInstr &MI);
121
122    void emitExtendInstruction(const MachineInstr &MI);
123
124    void emitMiscArithInstruction(const MachineInstr &MI);
125
126    void emitBranchInstruction(const MachineInstr &MI);
127
128    void emitInlineJumpTable(unsigned JTIndex);
129
130    void emitMiscBranchInstruction(const MachineInstr &MI);
131
132    void emitVFPArithInstruction(const MachineInstr &MI);
133
134    void emitVFPConversionInstruction(const MachineInstr &MI);
135
136    void emitVFPLoadStoreInstruction(const MachineInstr &MI);
137
138    void emitVFPLoadStoreMultipleInstruction(const MachineInstr &MI);
139
140    void emitMiscInstruction(const MachineInstr &MI);
141
142    void emitNEONGetLaneInstruction(const MachineInstr &MI);
143    void emitNEON1RegModImmInstruction(const MachineInstr &MI);
144    void emitNEON2RegInstruction(const MachineInstr &MI);
145    void emitNEON3RegInstruction(const MachineInstr &MI);
146
147    /// getMachineOpValue - Return binary encoding of operand. If the machine
148    /// operand requires relocation, record the relocation and return zero.
149    unsigned getMachineOpValue(const MachineInstr &MI,const MachineOperand &MO);
150    unsigned getMachineOpValue(const MachineInstr &MI, unsigned OpIdx) {
151      return getMachineOpValue(MI, MI.getOperand(OpIdx));
152    }
153
154    /// getMovi32Value - Return binary encoding of operand for movw/movt. If the
155    /// machine operand requires relocation, record the relocation and return
156    /// zero.
157    unsigned getMovi32Value(const MachineInstr &MI,const MachineOperand &MO,
158                            unsigned Reloc);
159    unsigned getMovi32Value(const MachineInstr &MI, unsigned OpIdx,
160                            unsigned Reloc) {
161      return getMovi32Value(MI, MI.getOperand(OpIdx), Reloc);
162    }
163
164    /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
165    ///
166    unsigned getShiftOp(unsigned Imm) const ;
167
168    /// Routines that handle operands which add machine relocations which are
169    /// fixed up by the relocation stage.
170    void emitGlobalAddress(const GlobalValue *GV, unsigned Reloc,
171                           bool MayNeedFarStub,  bool Indirect,
172                           intptr_t ACPV = 0);
173    void emitExternalSymbolAddress(const char *ES, unsigned Reloc);
174    void emitConstPoolAddress(unsigned CPI, unsigned Reloc);
175    void emitJumpTableAddress(unsigned JTIndex, unsigned Reloc);
176    void emitMachineBasicBlock(MachineBasicBlock *BB, unsigned Reloc,
177                               intptr_t JTBase = 0);
178  };
179}
180
181char ARMCodeEmitter::ID = 0;
182
183/// createARMJITCodeEmitterPass - Return a pass that emits the collected ARM
184/// code to the specified MCE object.
185FunctionPass *llvm::createARMJITCodeEmitterPass(ARMBaseTargetMachine &TM,
186                                                JITCodeEmitter &JCE) {
187  return new ARMCodeEmitter(TM, JCE);
188}
189
190bool ARMCodeEmitter::runOnMachineFunction(MachineFunction &MF) {
191  assert((MF.getTarget().getRelocationModel() != Reloc::Default ||
192          MF.getTarget().getRelocationModel() != Reloc::Static) &&
193         "JIT relocation model must be set to static or default!");
194  JTI = ((ARMTargetMachine &)MF.getTarget()).getJITInfo();
195  II = ((const ARMTargetMachine &)MF.getTarget()).getInstrInfo();
196  TD = ((const ARMTargetMachine &)MF.getTarget()).getTargetData();
197  Subtarget = &TM.getSubtarget<ARMSubtarget>();
198  MCPEs = &MF.getConstantPool()->getConstants();
199  MJTEs = 0;
200  if (MF.getJumpTableInfo()) MJTEs = &MF.getJumpTableInfo()->getJumpTables();
201  IsPIC = TM.getRelocationModel() == Reloc::PIC_;
202  JTI->Initialize(MF, IsPIC);
203  MMI = &getAnalysis<MachineModuleInfo>();
204  MCE.setModuleInfo(MMI);
205
206  do {
207    DEBUG(errs() << "JITTing function '"
208          << MF.getFunction()->getName() << "'\n");
209    MCE.startFunction(MF);
210    for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();
211         MBB != E; ++MBB) {
212      MCE.StartMachineBasicBlock(MBB);
213      for (MachineBasicBlock::const_iterator I = MBB->begin(), E = MBB->end();
214           I != E; ++I)
215        emitInstruction(*I);
216    }
217  } while (MCE.finishFunction(MF));
218
219  return false;
220}
221
222/// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
223///
224unsigned ARMCodeEmitter::getShiftOp(unsigned Imm) const {
225  switch (ARM_AM::getAM2ShiftOpc(Imm)) {
226  default: llvm_unreachable("Unknown shift opc!");
227  case ARM_AM::asr: return 2;
228  case ARM_AM::lsl: return 0;
229  case ARM_AM::lsr: return 1;
230  case ARM_AM::ror:
231  case ARM_AM::rrx: return 3;
232  }
233  return 0;
234}
235
236/// getMovi32Value - Return binary encoding of operand for movw/movt. If the
237/// machine operand requires relocation, record the relocation and return zero.
238unsigned ARMCodeEmitter::getMovi32Value(const MachineInstr &MI,
239                                        const MachineOperand &MO,
240                                        unsigned Reloc) {
241  assert(((Reloc == ARM::reloc_arm_movt) || (Reloc == ARM::reloc_arm_movw))
242      && "Relocation to this function should be for movt or movw");
243
244  if (MO.isImm())
245    return static_cast<unsigned>(MO.getImm());
246  else if (MO.isGlobal())
247    emitGlobalAddress(MO.getGlobal(), Reloc, true, false);
248  else if (MO.isSymbol())
249    emitExternalSymbolAddress(MO.getSymbolName(), Reloc);
250  else if (MO.isMBB())
251    emitMachineBasicBlock(MO.getMBB(), Reloc);
252  else {
253#ifndef NDEBUG
254    errs() << MO;
255#endif
256    llvm_unreachable("Unsupported operand type for movw/movt");
257  }
258  return 0;
259}
260
261/// getMachineOpValue - Return binary encoding of operand. If the machine
262/// operand requires relocation, record the relocation and return zero.
263unsigned ARMCodeEmitter::getMachineOpValue(const MachineInstr &MI,
264                                           const MachineOperand &MO) {
265  if (MO.isReg())
266    return ARMRegisterInfo::getRegisterNumbering(MO.getReg());
267  else if (MO.isImm())
268    return static_cast<unsigned>(MO.getImm());
269  else if (MO.isGlobal())
270    emitGlobalAddress(MO.getGlobal(), ARM::reloc_arm_branch, true, false);
271  else if (MO.isSymbol())
272    emitExternalSymbolAddress(MO.getSymbolName(), ARM::reloc_arm_branch);
273  else if (MO.isCPI()) {
274    const TargetInstrDesc &TID = MI.getDesc();
275    // For VFP load, the immediate offset is multiplied by 4.
276    unsigned Reloc =  ((TID.TSFlags & ARMII::FormMask) == ARMII::VFPLdStFrm)
277      ? ARM::reloc_arm_vfp_cp_entry : ARM::reloc_arm_cp_entry;
278    emitConstPoolAddress(MO.getIndex(), Reloc);
279  } else if (MO.isJTI())
280    emitJumpTableAddress(MO.getIndex(), ARM::reloc_arm_relative);
281  else if (MO.isMBB())
282    emitMachineBasicBlock(MO.getMBB(), ARM::reloc_arm_branch);
283  else {
284#ifndef NDEBUG
285    errs() << MO;
286#endif
287    llvm_unreachable(0);
288  }
289  return 0;
290}
291
292/// emitGlobalAddress - Emit the specified address to the code stream.
293///
294void ARMCodeEmitter::emitGlobalAddress(const GlobalValue *GV, unsigned Reloc,
295                                       bool MayNeedFarStub, bool Indirect,
296                                       intptr_t ACPV) {
297  MachineRelocation MR = Indirect
298    ? MachineRelocation::getIndirectSymbol(MCE.getCurrentPCOffset(), Reloc,
299                                           const_cast<GlobalValue *>(GV),
300                                           ACPV, MayNeedFarStub)
301    : MachineRelocation::getGV(MCE.getCurrentPCOffset(), Reloc,
302                               const_cast<GlobalValue *>(GV), ACPV,
303                               MayNeedFarStub);
304  MCE.addRelocation(MR);
305}
306
307/// emitExternalSymbolAddress - Arrange for the address of an external symbol to
308/// be emitted to the current location in the function, and allow it to be PC
309/// relative.
310void ARMCodeEmitter::emitExternalSymbolAddress(const char *ES, unsigned Reloc) {
311  MCE.addRelocation(MachineRelocation::getExtSym(MCE.getCurrentPCOffset(),
312                                                 Reloc, ES));
313}
314
315/// emitConstPoolAddress - Arrange for the address of an constant pool
316/// to be emitted to the current location in the function, and allow it to be PC
317/// relative.
318void ARMCodeEmitter::emitConstPoolAddress(unsigned CPI, unsigned Reloc) {
319  // Tell JIT emitter we'll resolve the address.
320  MCE.addRelocation(MachineRelocation::getConstPool(MCE.getCurrentPCOffset(),
321                                                    Reloc, CPI, 0, true));
322}
323
324/// emitJumpTableAddress - Arrange for the address of a jump table to
325/// be emitted to the current location in the function, and allow it to be PC
326/// relative.
327void ARMCodeEmitter::emitJumpTableAddress(unsigned JTIndex, unsigned Reloc) {
328  MCE.addRelocation(MachineRelocation::getJumpTable(MCE.getCurrentPCOffset(),
329                                                    Reloc, JTIndex, 0, true));
330}
331
332/// emitMachineBasicBlock - Emit the specified address basic block.
333void ARMCodeEmitter::emitMachineBasicBlock(MachineBasicBlock *BB,
334                                           unsigned Reloc, intptr_t JTBase) {
335  MCE.addRelocation(MachineRelocation::getBB(MCE.getCurrentPCOffset(),
336                                             Reloc, BB, JTBase));
337}
338
339void ARMCodeEmitter::emitWordLE(unsigned Binary) {
340  DEBUG(errs() << "  0x";
341        errs().write_hex(Binary) << "\n");
342  MCE.emitWordLE(Binary);
343}
344
345void ARMCodeEmitter::emitDWordLE(uint64_t Binary) {
346  DEBUG(errs() << "  0x";
347        errs().write_hex(Binary) << "\n");
348  MCE.emitDWordLE(Binary);
349}
350
351void ARMCodeEmitter::emitInstruction(const MachineInstr &MI) {
352  DEBUG(errs() << "JIT: " << (void*)MCE.getCurrentPCValue() << ":\t" << MI);
353
354  MCE.processDebugLoc(MI.getDebugLoc(), true);
355
356  ++NumEmitted;  // Keep track of the # of mi's emitted
357  switch (MI.getDesc().TSFlags & ARMII::FormMask) {
358  default: {
359    llvm_unreachable("Unhandled instruction encoding format!");
360    break;
361  }
362  case ARMII::Pseudo:
363    emitPseudoInstruction(MI);
364    break;
365  case ARMII::DPFrm:
366  case ARMII::DPSoRegFrm:
367    emitDataProcessingInstruction(MI);
368    break;
369  case ARMII::LdFrm:
370  case ARMII::StFrm:
371    emitLoadStoreInstruction(MI);
372    break;
373  case ARMII::LdMiscFrm:
374  case ARMII::StMiscFrm:
375    emitMiscLoadStoreInstruction(MI);
376    break;
377  case ARMII::LdStMulFrm:
378    emitLoadStoreMultipleInstruction(MI);
379    break;
380  case ARMII::MulFrm:
381    emitMulFrmInstruction(MI);
382    break;
383  case ARMII::ExtFrm:
384    emitExtendInstruction(MI);
385    break;
386  case ARMII::ArithMiscFrm:
387    emitMiscArithInstruction(MI);
388    break;
389  case ARMII::BrFrm:
390    emitBranchInstruction(MI);
391    break;
392  case ARMII::BrMiscFrm:
393    emitMiscBranchInstruction(MI);
394    break;
395  // VFP instructions.
396  case ARMII::VFPUnaryFrm:
397  case ARMII::VFPBinaryFrm:
398    emitVFPArithInstruction(MI);
399    break;
400  case ARMII::VFPConv1Frm:
401  case ARMII::VFPConv2Frm:
402  case ARMII::VFPConv3Frm:
403  case ARMII::VFPConv4Frm:
404  case ARMII::VFPConv5Frm:
405    emitVFPConversionInstruction(MI);
406    break;
407  case ARMII::VFPLdStFrm:
408    emitVFPLoadStoreInstruction(MI);
409    break;
410  case ARMII::VFPLdStMulFrm:
411    emitVFPLoadStoreMultipleInstruction(MI);
412    break;
413  case ARMII::VFPMiscFrm:
414    emitMiscInstruction(MI);
415    break;
416  // NEON instructions.
417  case ARMII::NGetLnFrm:
418    emitNEONGetLaneInstruction(MI);
419    break;
420  case ARMII::N1RegModImmFrm:
421    emitNEON1RegModImmInstruction(MI);
422    break;
423  case ARMII::N2RegFrm:
424    emitNEON2RegInstruction(MI);
425    break;
426  case ARMII::N3RegFrm:
427    emitNEON3RegInstruction(MI);
428    break;
429  }
430  MCE.processDebugLoc(MI.getDebugLoc(), false);
431}
432
433void ARMCodeEmitter::emitConstPoolInstruction(const MachineInstr &MI) {
434  unsigned CPI = MI.getOperand(0).getImm();       // CP instruction index.
435  unsigned CPIndex = MI.getOperand(1).getIndex(); // Actual cp entry index.
436  const MachineConstantPoolEntry &MCPE = (*MCPEs)[CPIndex];
437
438  // Remember the CONSTPOOL_ENTRY address for later relocation.
439  JTI->addConstantPoolEntryAddr(CPI, MCE.getCurrentPCValue());
440
441  // Emit constpool island entry. In most cases, the actual values will be
442  // resolved and relocated after code emission.
443  if (MCPE.isMachineConstantPoolEntry()) {
444    ARMConstantPoolValue *ACPV =
445      static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal);
446
447    DEBUG(errs() << "  ** ARM constant pool #" << CPI << " @ "
448          << (void*)MCE.getCurrentPCValue() << " " << *ACPV << '\n');
449
450    assert(ACPV->isGlobalValue() && "unsupported constant pool value");
451    const GlobalValue *GV = ACPV->getGV();
452    if (GV) {
453      Reloc::Model RelocM = TM.getRelocationModel();
454      emitGlobalAddress(GV, ARM::reloc_arm_machine_cp_entry,
455                        isa<Function>(GV),
456                        Subtarget->GVIsIndirectSymbol(GV, RelocM),
457                        (intptr_t)ACPV);
458     } else  {
459      emitExternalSymbolAddress(ACPV->getSymbol(), ARM::reloc_arm_absolute);
460    }
461    emitWordLE(0);
462  } else {
463    const Constant *CV = MCPE.Val.ConstVal;
464
465    DEBUG({
466        errs() << "  ** Constant pool #" << CPI << " @ "
467               << (void*)MCE.getCurrentPCValue() << " ";
468        if (const Function *F = dyn_cast<Function>(CV))
469          errs() << F->getName();
470        else
471          errs() << *CV;
472        errs() << '\n';
473      });
474
475    if (const GlobalValue *GV = dyn_cast<GlobalValue>(CV)) {
476      emitGlobalAddress(GV, ARM::reloc_arm_absolute, isa<Function>(GV), false);
477      emitWordLE(0);
478    } else if (const ConstantInt *CI = dyn_cast<ConstantInt>(CV)) {
479      uint32_t Val = *(uint32_t*)CI->getValue().getRawData();
480      emitWordLE(Val);
481    } else if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CV)) {
482      if (CFP->getType()->isFloatTy())
483        emitWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue());
484      else if (CFP->getType()->isDoubleTy())
485        emitDWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue());
486      else {
487        llvm_unreachable("Unable to handle this constantpool entry!");
488      }
489    } else {
490      llvm_unreachable("Unable to handle this constantpool entry!");
491    }
492  }
493}
494
495void ARMCodeEmitter::emitMOVi32immInstruction(const MachineInstr &MI) {
496  const MachineOperand &MO0 = MI.getOperand(0);
497  const MachineOperand &MO1 = MI.getOperand(1);
498
499  // Emit the 'movw' instruction.
500  unsigned Binary = 0x30 << 20;  // mov: Insts{27-20} = 0b00110000
501
502  unsigned Lo16 = getMovi32Value(MI, MO1, ARM::reloc_arm_movw) & 0xFFFF;
503
504  // Set the conditional execution predicate.
505  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
506
507  // Encode Rd.
508  Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
509
510  // Encode imm16 as imm4:imm12
511  Binary |= Lo16 & 0xFFF; // Insts{11-0} = imm12
512  Binary |= ((Lo16 >> 12) & 0xF) << 16; // Insts{19-16} = imm4
513  emitWordLE(Binary);
514
515  unsigned Hi16 = getMovi32Value(MI, MO1, ARM::reloc_arm_movt) >> 16;
516  // Emit the 'movt' instruction.
517  Binary = 0x34 << 20; // movt: Insts{27-20} = 0b00110100
518
519  // Set the conditional execution predicate.
520  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
521
522  // Encode Rd.
523  Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
524
525  // Encode imm16 as imm4:imm1, same as movw above.
526  Binary |= Hi16 & 0xFFF;
527  Binary |= ((Hi16 >> 12) & 0xF) << 16;
528  emitWordLE(Binary);
529}
530
531void ARMCodeEmitter::emitMOVi2piecesInstruction(const MachineInstr &MI) {
532  const MachineOperand &MO0 = MI.getOperand(0);
533  const MachineOperand &MO1 = MI.getOperand(1);
534  assert(MO1.isImm() && ARM_AM::isSOImmTwoPartVal(MO1.getImm()) &&
535                                                  "Not a valid so_imm value!");
536  unsigned V1 = ARM_AM::getSOImmTwoPartFirst(MO1.getImm());
537  unsigned V2 = ARM_AM::getSOImmTwoPartSecond(MO1.getImm());
538
539  // Emit the 'mov' instruction.
540  unsigned Binary = 0xd << 21;  // mov: Insts{24-21} = 0b1101
541
542  // Set the conditional execution predicate.
543  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
544
545  // Encode Rd.
546  Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
547
548  // Encode so_imm.
549  // Set bit I(25) to identify this is the immediate form of <shifter_op>
550  Binary |= 1 << ARMII::I_BitShift;
551  Binary |= getMachineSoImmOpValue(V1);
552  emitWordLE(Binary);
553
554  // Now the 'orr' instruction.
555  Binary = 0xc << 21;  // orr: Insts{24-21} = 0b1100
556
557  // Set the conditional execution predicate.
558  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
559
560  // Encode Rd.
561  Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
562
563  // Encode Rn.
564  Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRnShift;
565
566  // Encode so_imm.
567  // Set bit I(25) to identify this is the immediate form of <shifter_op>
568  Binary |= 1 << ARMII::I_BitShift;
569  Binary |= getMachineSoImmOpValue(V2);
570  emitWordLE(Binary);
571}
572
573void ARMCodeEmitter::emitLEApcrelJTInstruction(const MachineInstr &MI) {
574  // It's basically add r, pc, (LJTI - $+8)
575
576  const TargetInstrDesc &TID = MI.getDesc();
577
578  // Emit the 'add' instruction.
579  unsigned Binary = 0x4 << 21;  // add: Insts{24-31} = 0b0100
580
581  // Set the conditional execution predicate
582  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
583
584  // Encode S bit if MI modifies CPSR.
585  Binary |= getAddrModeSBit(MI, TID);
586
587  // Encode Rd.
588  Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
589
590  // Encode Rn which is PC.
591  Binary |= ARMRegisterInfo::getRegisterNumbering(ARM::PC) << ARMII::RegRnShift;
592
593  // Encode the displacement.
594  Binary |= 1 << ARMII::I_BitShift;
595  emitJumpTableAddress(MI.getOperand(1).getIndex(), ARM::reloc_arm_jt_base);
596
597  emitWordLE(Binary);
598}
599
600void ARMCodeEmitter::emitPseudoMoveInstruction(const MachineInstr &MI) {
601  unsigned Opcode = MI.getDesc().Opcode;
602
603  // Part of binary is determined by TableGn.
604  unsigned Binary = getBinaryCodeForInstr(MI);
605
606  // Set the conditional execution predicate
607  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
608
609  // Encode S bit if MI modifies CPSR.
610  if (Opcode == ARM::MOVsrl_flag || Opcode == ARM::MOVsra_flag)
611    Binary |= 1 << ARMII::S_BitShift;
612
613  // Encode register def if there is one.
614  Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
615
616  // Encode the shift operation.
617  switch (Opcode) {
618  default: break;
619  case ARM::MOVrx:
620    // rrx
621    Binary |= 0x6 << 4;
622    break;
623  case ARM::MOVsrl_flag:
624    // lsr #1
625    Binary |= (0x2 << 4) | (1 << 7);
626    break;
627  case ARM::MOVsra_flag:
628    // asr #1
629    Binary |= (0x4 << 4) | (1 << 7);
630    break;
631  }
632
633  // Encode register Rm.
634  Binary |= getMachineOpValue(MI, 1);
635
636  emitWordLE(Binary);
637}
638
639void ARMCodeEmitter::addPCLabel(unsigned LabelID) {
640  DEBUG(errs() << "  ** LPC" << LabelID << " @ "
641        << (void*)MCE.getCurrentPCValue() << '\n');
642  JTI->addPCLabelAddr(LabelID, MCE.getCurrentPCValue());
643}
644
645void ARMCodeEmitter::emitPseudoInstruction(const MachineInstr &MI) {
646  unsigned Opcode = MI.getDesc().Opcode;
647  switch (Opcode) {
648  default:
649    llvm_unreachable("ARMCodeEmitter::emitPseudoInstruction");
650  case TargetOpcode::INLINEASM: {
651    // We allow inline assembler nodes with empty bodies - they can
652    // implicitly define registers, which is ok for JIT.
653    if (MI.getOperand(0).getSymbolName()[0]) {
654      report_fatal_error("JIT does not support inline asm!");
655    }
656    break;
657  }
658  case TargetOpcode::DBG_LABEL:
659  case TargetOpcode::EH_LABEL:
660    MCE.emitLabel(MI.getOperand(0).getMCSymbol());
661    break;
662  case TargetOpcode::IMPLICIT_DEF:
663  case TargetOpcode::KILL:
664    // Do nothing.
665    break;
666  case ARM::CONSTPOOL_ENTRY:
667    emitConstPoolInstruction(MI);
668    break;
669  case ARM::PICADD: {
670    // Remember of the address of the PC label for relocation later.
671    addPCLabel(MI.getOperand(2).getImm());
672    // PICADD is just an add instruction that implicitly read pc.
673    emitDataProcessingInstruction(MI, 0, ARM::PC);
674    break;
675  }
676  case ARM::PICLDR:
677  case ARM::PICLDRB:
678  case ARM::PICSTR:
679  case ARM::PICSTRB: {
680    // Remember of the address of the PC label for relocation later.
681    addPCLabel(MI.getOperand(2).getImm());
682    // These are just load / store instructions that implicitly read pc.
683    emitLoadStoreInstruction(MI, 0, ARM::PC);
684    break;
685  }
686  case ARM::PICLDRH:
687  case ARM::PICLDRSH:
688  case ARM::PICLDRSB:
689  case ARM::PICSTRH: {
690    // Remember of the address of the PC label for relocation later.
691    addPCLabel(MI.getOperand(2).getImm());
692    // These are just load / store instructions that implicitly read pc.
693    emitMiscLoadStoreInstruction(MI, ARM::PC);
694    break;
695  }
696
697  case ARM::MOVi32imm:
698    emitMOVi32immInstruction(MI);
699    break;
700
701  case ARM::MOVi2pieces:
702    // Two instructions to materialize a constant.
703    emitMOVi2piecesInstruction(MI);
704    break;
705  case ARM::LEApcrelJT:
706    // Materialize jumptable address.
707    emitLEApcrelJTInstruction(MI);
708    break;
709  case ARM::MOVrx:
710  case ARM::MOVsrl_flag:
711  case ARM::MOVsra_flag:
712    emitPseudoMoveInstruction(MI);
713    break;
714  }
715}
716
717unsigned ARMCodeEmitter::getMachineSoRegOpValue(const MachineInstr &MI,
718                                                const TargetInstrDesc &TID,
719                                                const MachineOperand &MO,
720                                                unsigned OpIdx) {
721  unsigned Binary = getMachineOpValue(MI, MO);
722
723  const MachineOperand &MO1 = MI.getOperand(OpIdx + 1);
724  const MachineOperand &MO2 = MI.getOperand(OpIdx + 2);
725  ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm());
726
727  // Encode the shift opcode.
728  unsigned SBits = 0;
729  unsigned Rs = MO1.getReg();
730  if (Rs) {
731    // Set shift operand (bit[7:4]).
732    // LSL - 0001
733    // LSR - 0011
734    // ASR - 0101
735    // ROR - 0111
736    // RRX - 0110 and bit[11:8] clear.
737    switch (SOpc) {
738    default: llvm_unreachable("Unknown shift opc!");
739    case ARM_AM::lsl: SBits = 0x1; break;
740    case ARM_AM::lsr: SBits = 0x3; break;
741    case ARM_AM::asr: SBits = 0x5; break;
742    case ARM_AM::ror: SBits = 0x7; break;
743    case ARM_AM::rrx: SBits = 0x6; break;
744    }
745  } else {
746    // Set shift operand (bit[6:4]).
747    // LSL - 000
748    // LSR - 010
749    // ASR - 100
750    // ROR - 110
751    switch (SOpc) {
752    default: llvm_unreachable("Unknown shift opc!");
753    case ARM_AM::lsl: SBits = 0x0; break;
754    case ARM_AM::lsr: SBits = 0x2; break;
755    case ARM_AM::asr: SBits = 0x4; break;
756    case ARM_AM::ror: SBits = 0x6; break;
757    }
758  }
759  Binary |= SBits << 4;
760  if (SOpc == ARM_AM::rrx)
761    return Binary;
762
763  // Encode the shift operation Rs or shift_imm (except rrx).
764  if (Rs) {
765    // Encode Rs bit[11:8].
766    assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0);
767    return Binary |
768      (ARMRegisterInfo::getRegisterNumbering(Rs) << ARMII::RegRsShift);
769  }
770
771  // Encode shift_imm bit[11:7].
772  return Binary | ARM_AM::getSORegOffset(MO2.getImm()) << 7;
773}
774
775unsigned ARMCodeEmitter::getMachineSoImmOpValue(unsigned SoImm) {
776  int SoImmVal = ARM_AM::getSOImmVal(SoImm);
777  assert(SoImmVal != -1 && "Not a valid so_imm value!");
778
779  // Encode rotate_imm.
780  unsigned Binary = (ARM_AM::getSOImmValRot((unsigned)SoImmVal) >> 1)
781    << ARMII::SoRotImmShift;
782
783  // Encode immed_8.
784  Binary |= ARM_AM::getSOImmValImm((unsigned)SoImmVal);
785  return Binary;
786}
787
788unsigned ARMCodeEmitter::getAddrModeSBit(const MachineInstr &MI,
789                                         const TargetInstrDesc &TID) const {
790  for (unsigned i = MI.getNumOperands(), e = TID.getNumOperands(); i != e; --i){
791    const MachineOperand &MO = MI.getOperand(i-1);
792    if (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR)
793      return 1 << ARMII::S_BitShift;
794  }
795  return 0;
796}
797
798void ARMCodeEmitter::emitDataProcessingInstruction(const MachineInstr &MI,
799                                                   unsigned ImplicitRd,
800                                                   unsigned ImplicitRn) {
801  const TargetInstrDesc &TID = MI.getDesc();
802
803  // Part of binary is determined by TableGn.
804  unsigned Binary = getBinaryCodeForInstr(MI);
805
806  // Set the conditional execution predicate
807  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
808
809  // Encode S bit if MI modifies CPSR.
810  Binary |= getAddrModeSBit(MI, TID);
811
812  // Encode register def if there is one.
813  unsigned NumDefs = TID.getNumDefs();
814  unsigned OpIdx = 0;
815  if (NumDefs)
816    Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
817  else if (ImplicitRd)
818    // Special handling for implicit use (e.g. PC).
819    Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRd)
820               << ARMII::RegRdShift);
821
822  if (TID.Opcode == ARM::MOVi16) {
823      // Get immediate from MI.
824      unsigned Lo16 = getMovi32Value(MI, MI.getOperand(OpIdx),
825                      ARM::reloc_arm_movw);
826      // Encode imm which is the same as in emitMOVi32immInstruction().
827      Binary |= Lo16 & 0xFFF;
828      Binary |= ((Lo16 >> 12) & 0xF) << 16;
829      emitWordLE(Binary);
830      return;
831  } else if(TID.Opcode == ARM::MOVTi16) {
832      unsigned Hi16 = (getMovi32Value(MI, MI.getOperand(OpIdx),
833                       ARM::reloc_arm_movt) >> 16);
834      Binary |= Hi16 & 0xFFF;
835      Binary |= ((Hi16 >> 12) & 0xF) << 16;
836      emitWordLE(Binary);
837      return;
838  } else if ((TID.Opcode == ARM::BFC) || (TID.Opcode == ARM::BFI)) {
839      uint32_t v = ~MI.getOperand(2).getImm();
840      int32_t lsb = CountTrailingZeros_32(v);
841      int32_t msb = (32 - CountLeadingZeros_32(v)) - 1;
842      // Instr{20-16} = msb, Instr{11-7} = lsb
843      Binary |= (msb & 0x1F) << 16;
844      Binary |= (lsb & 0x1F) << 7;
845      emitWordLE(Binary);
846      return;
847  } else if ((TID.Opcode == ARM::UBFX) || (TID.Opcode == ARM::SBFX)) {
848      // Encode Rn in Instr{0-3}
849      Binary |= getMachineOpValue(MI, OpIdx++);
850
851      uint32_t lsb = MI.getOperand(OpIdx++).getImm();
852      uint32_t widthm1 = MI.getOperand(OpIdx++).getImm() - 1;
853
854      // Instr{20-16} = widthm1, Instr{11-7} = lsb
855      Binary |= (widthm1 & 0x1F) << 16;
856      Binary |= (lsb & 0x1F) << 7;
857      emitWordLE(Binary);
858      return;
859  }
860
861  // If this is a two-address operand, skip it. e.g. MOVCCr operand 1.
862  if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
863    ++OpIdx;
864
865  // Encode first non-shifter register operand if there is one.
866  bool isUnary = TID.TSFlags & ARMII::UnaryDP;
867  if (!isUnary) {
868    if (ImplicitRn)
869      // Special handling for implicit use (e.g. PC).
870      Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRn)
871                 << ARMII::RegRnShift);
872    else {
873      Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRnShift;
874      ++OpIdx;
875    }
876  }
877
878  // Encode shifter operand.
879  const MachineOperand &MO = MI.getOperand(OpIdx);
880  if ((TID.TSFlags & ARMII::FormMask) == ARMII::DPSoRegFrm) {
881    // Encode SoReg.
882    emitWordLE(Binary | getMachineSoRegOpValue(MI, TID, MO, OpIdx));
883    return;
884  }
885
886  if (MO.isReg()) {
887    // Encode register Rm.
888    emitWordLE(Binary | ARMRegisterInfo::getRegisterNumbering(MO.getReg()));
889    return;
890  }
891
892  // Encode so_imm.
893  Binary |= getMachineSoImmOpValue((unsigned)MO.getImm());
894
895  emitWordLE(Binary);
896}
897
898void ARMCodeEmitter::emitLoadStoreInstruction(const MachineInstr &MI,
899                                              unsigned ImplicitRd,
900                                              unsigned ImplicitRn) {
901  const TargetInstrDesc &TID = MI.getDesc();
902  unsigned Form = TID.TSFlags & ARMII::FormMask;
903  bool IsPrePost = (TID.TSFlags & ARMII::IndexModeMask) != 0;
904
905  // Part of binary is determined by TableGn.
906  unsigned Binary = getBinaryCodeForInstr(MI);
907
908  // Set the conditional execution predicate
909  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
910
911  unsigned OpIdx = 0;
912
913  // Operand 0 of a pre- and post-indexed store is the address base
914  // writeback. Skip it.
915  bool Skipped = false;
916  if (IsPrePost && Form == ARMII::StFrm) {
917    ++OpIdx;
918    Skipped = true;
919  }
920
921  // Set first operand
922  if (ImplicitRd)
923    // Special handling for implicit use (e.g. PC).
924    Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRd)
925               << ARMII::RegRdShift);
926  else
927    Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
928
929  // Set second operand
930  if (ImplicitRn)
931    // Special handling for implicit use (e.g. PC).
932    Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRn)
933               << ARMII::RegRnShift);
934  else
935    Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
936
937  // If this is a two-address operand, skip it. e.g. LDR_PRE.
938  if (!Skipped && TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
939    ++OpIdx;
940
941  const MachineOperand &MO2 = MI.getOperand(OpIdx);
942  unsigned AM2Opc = (ImplicitRn == ARM::PC)
943    ? 0 : MI.getOperand(OpIdx+1).getImm();
944
945  // Set bit U(23) according to sign of immed value (positive or negative).
946  Binary |= ((ARM_AM::getAM2Op(AM2Opc) == ARM_AM::add ? 1 : 0) <<
947             ARMII::U_BitShift);
948  if (!MO2.getReg()) { // is immediate
949    if (ARM_AM::getAM2Offset(AM2Opc))
950      // Set the value of offset_12 field
951      Binary |= ARM_AM::getAM2Offset(AM2Opc);
952    emitWordLE(Binary);
953    return;
954  }
955
956  // Set bit I(25), because this is not in immediate enconding.
957  Binary |= 1 << ARMII::I_BitShift;
958  assert(TargetRegisterInfo::isPhysicalRegister(MO2.getReg()));
959  // Set bit[3:0] to the corresponding Rm register
960  Binary |= ARMRegisterInfo::getRegisterNumbering(MO2.getReg());
961
962  // If this instr is in scaled register offset/index instruction, set
963  // shift_immed(bit[11:7]) and shift(bit[6:5]) fields.
964  if (unsigned ShImm = ARM_AM::getAM2Offset(AM2Opc)) {
965    Binary |= getShiftOp(AM2Opc) << ARMII::ShiftImmShift;  // shift
966    Binary |= ShImm              << ARMII::ShiftShift;     // shift_immed
967  }
968
969  emitWordLE(Binary);
970}
971
972void ARMCodeEmitter::emitMiscLoadStoreInstruction(const MachineInstr &MI,
973                                                  unsigned ImplicitRn) {
974  const TargetInstrDesc &TID = MI.getDesc();
975  unsigned Form = TID.TSFlags & ARMII::FormMask;
976  bool IsPrePost = (TID.TSFlags & ARMII::IndexModeMask) != 0;
977
978  // Part of binary is determined by TableGn.
979  unsigned Binary = getBinaryCodeForInstr(MI);
980
981  // Set the conditional execution predicate
982  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
983
984  unsigned OpIdx = 0;
985
986  // Operand 0 of a pre- and post-indexed store is the address base
987  // writeback. Skip it.
988  bool Skipped = false;
989  if (IsPrePost && Form == ARMII::StMiscFrm) {
990    ++OpIdx;
991    Skipped = true;
992  }
993
994  // Set first operand
995  Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
996
997  // Skip LDRD and STRD's second operand.
998  if (TID.Opcode == ARM::LDRD || TID.Opcode == ARM::STRD)
999    ++OpIdx;
1000
1001  // Set second operand
1002  if (ImplicitRn)
1003    // Special handling for implicit use (e.g. PC).
1004    Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRn)
1005               << ARMII::RegRnShift);
1006  else
1007    Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
1008
1009  // If this is a two-address operand, skip it. e.g. LDRH_POST.
1010  if (!Skipped && TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1011    ++OpIdx;
1012
1013  const MachineOperand &MO2 = MI.getOperand(OpIdx);
1014  unsigned AM3Opc = (ImplicitRn == ARM::PC)
1015    ? 0 : MI.getOperand(OpIdx+1).getImm();
1016
1017  // Set bit U(23) according to sign of immed value (positive or negative)
1018  Binary |= ((ARM_AM::getAM3Op(AM3Opc) == ARM_AM::add ? 1 : 0) <<
1019             ARMII::U_BitShift);
1020
1021  // If this instr is in register offset/index encoding, set bit[3:0]
1022  // to the corresponding Rm register.
1023  if (MO2.getReg()) {
1024    Binary |= ARMRegisterInfo::getRegisterNumbering(MO2.getReg());
1025    emitWordLE(Binary);
1026    return;
1027  }
1028
1029  // This instr is in immediate offset/index encoding, set bit 22 to 1.
1030  Binary |= 1 << ARMII::AM3_I_BitShift;
1031  if (unsigned ImmOffs = ARM_AM::getAM3Offset(AM3Opc)) {
1032    // Set operands
1033    Binary |= (ImmOffs >> 4) << ARMII::ImmHiShift;  // immedH
1034    Binary |= (ImmOffs & 0xF);                      // immedL
1035  }
1036
1037  emitWordLE(Binary);
1038}
1039
1040static unsigned getAddrModeUPBits(unsigned Mode) {
1041  unsigned Binary = 0;
1042
1043  // Set addressing mode by modifying bits U(23) and P(24)
1044  // IA - Increment after  - bit U = 1 and bit P = 0
1045  // IB - Increment before - bit U = 1 and bit P = 1
1046  // DA - Decrement after  - bit U = 0 and bit P = 0
1047  // DB - Decrement before - bit U = 0 and bit P = 1
1048  switch (Mode) {
1049  default: llvm_unreachable("Unknown addressing sub-mode!");
1050  case ARM_AM::da:                                     break;
1051  case ARM_AM::db: Binary |= 0x1 << ARMII::P_BitShift; break;
1052  case ARM_AM::ia: Binary |= 0x1 << ARMII::U_BitShift; break;
1053  case ARM_AM::ib: Binary |= 0x3 << ARMII::U_BitShift; break;
1054  }
1055
1056  return Binary;
1057}
1058
1059void ARMCodeEmitter::emitLoadStoreMultipleInstruction(const MachineInstr &MI) {
1060  const TargetInstrDesc &TID = MI.getDesc();
1061  bool IsUpdating = (TID.TSFlags & ARMII::IndexModeMask) != 0;
1062
1063  // Part of binary is determined by TableGn.
1064  unsigned Binary = getBinaryCodeForInstr(MI);
1065
1066  // Set the conditional execution predicate
1067  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1068
1069  // Skip operand 0 of an instruction with base register update.
1070  unsigned OpIdx = 0;
1071  if (IsUpdating)
1072    ++OpIdx;
1073
1074  // Set base address operand
1075  Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
1076
1077  // Set addressing mode by modifying bits U(23) and P(24)
1078  const MachineOperand &MO = MI.getOperand(OpIdx++);
1079  Binary |= getAddrModeUPBits(ARM_AM::getAM4SubMode(MO.getImm()));
1080
1081  // Set bit W(21)
1082  if (IsUpdating)
1083    Binary |= 0x1 << ARMII::W_BitShift;
1084
1085  // Set registers
1086  for (unsigned i = OpIdx+2, e = MI.getNumOperands(); i != e; ++i) {
1087    const MachineOperand &MO = MI.getOperand(i);
1088    if (!MO.isReg() || MO.isImplicit())
1089      break;
1090    unsigned RegNum = ARMRegisterInfo::getRegisterNumbering(MO.getReg());
1091    assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()) &&
1092           RegNum < 16);
1093    Binary |= 0x1 << RegNum;
1094  }
1095
1096  emitWordLE(Binary);
1097}
1098
1099void ARMCodeEmitter::emitMulFrmInstruction(const MachineInstr &MI) {
1100  const TargetInstrDesc &TID = MI.getDesc();
1101
1102  // Part of binary is determined by TableGn.
1103  unsigned Binary = getBinaryCodeForInstr(MI);
1104
1105  // Set the conditional execution predicate
1106  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1107
1108  // Encode S bit if MI modifies CPSR.
1109  Binary |= getAddrModeSBit(MI, TID);
1110
1111  // 32x32->64bit operations have two destination registers. The number
1112  // of register definitions will tell us if that's what we're dealing with.
1113  unsigned OpIdx = 0;
1114  if (TID.getNumDefs() == 2)
1115    Binary |= getMachineOpValue (MI, OpIdx++) << ARMII::RegRdLoShift;
1116
1117  // Encode Rd
1118  Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdHiShift;
1119
1120  // Encode Rm
1121  Binary |= getMachineOpValue(MI, OpIdx++);
1122
1123  // Encode Rs
1124  Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRsShift;
1125
1126  // Many multiple instructions (e.g. MLA) have three src operands. Encode
1127  // it as Rn (for multiply, that's in the same offset as RdLo.
1128  if (TID.getNumOperands() > OpIdx &&
1129      !TID.OpInfo[OpIdx].isPredicate() &&
1130      !TID.OpInfo[OpIdx].isOptionalDef())
1131    Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRdLoShift;
1132
1133  emitWordLE(Binary);
1134}
1135
1136void ARMCodeEmitter::emitExtendInstruction(const MachineInstr &MI) {
1137  const TargetInstrDesc &TID = MI.getDesc();
1138
1139  // Part of binary is determined by TableGn.
1140  unsigned Binary = getBinaryCodeForInstr(MI);
1141
1142  // Set the conditional execution predicate
1143  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1144
1145  unsigned OpIdx = 0;
1146
1147  // Encode Rd
1148  Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1149
1150  const MachineOperand &MO1 = MI.getOperand(OpIdx++);
1151  const MachineOperand &MO2 = MI.getOperand(OpIdx);
1152  if (MO2.isReg()) {
1153    // Two register operand form.
1154    // Encode Rn.
1155    Binary |= getMachineOpValue(MI, MO1) << ARMII::RegRnShift;
1156
1157    // Encode Rm.
1158    Binary |= getMachineOpValue(MI, MO2);
1159    ++OpIdx;
1160  } else {
1161    Binary |= getMachineOpValue(MI, MO1);
1162  }
1163
1164  // Encode rot imm (0, 8, 16, or 24) if it has a rotate immediate operand.
1165  if (MI.getOperand(OpIdx).isImm() &&
1166      !TID.OpInfo[OpIdx].isPredicate() &&
1167      !TID.OpInfo[OpIdx].isOptionalDef())
1168    Binary |= (getMachineOpValue(MI, OpIdx) / 8) << ARMII::ExtRotImmShift;
1169
1170  emitWordLE(Binary);
1171}
1172
1173void ARMCodeEmitter::emitMiscArithInstruction(const MachineInstr &MI) {
1174  const TargetInstrDesc &TID = MI.getDesc();
1175
1176  // Part of binary is determined by TableGn.
1177  unsigned Binary = getBinaryCodeForInstr(MI);
1178
1179  // Set the conditional execution predicate
1180  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1181
1182  unsigned OpIdx = 0;
1183
1184  // Encode Rd
1185  Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1186
1187  const MachineOperand &MO = MI.getOperand(OpIdx++);
1188  if (OpIdx == TID.getNumOperands() ||
1189      TID.OpInfo[OpIdx].isPredicate() ||
1190      TID.OpInfo[OpIdx].isOptionalDef()) {
1191    // Encode Rm and it's done.
1192    Binary |= getMachineOpValue(MI, MO);
1193    emitWordLE(Binary);
1194    return;
1195  }
1196
1197  // Encode Rn.
1198  Binary |= getMachineOpValue(MI, MO) << ARMII::RegRnShift;
1199
1200  // Encode Rm.
1201  Binary |= getMachineOpValue(MI, OpIdx++);
1202
1203  // Encode shift_imm.
1204  unsigned ShiftAmt = MI.getOperand(OpIdx).getImm();
1205  assert(ShiftAmt < 32 && "shift_imm range is 0 to 31!");
1206  Binary |= ShiftAmt << ARMII::ShiftShift;
1207
1208  emitWordLE(Binary);
1209}
1210
1211void ARMCodeEmitter::emitBranchInstruction(const MachineInstr &MI) {
1212  const TargetInstrDesc &TID = MI.getDesc();
1213
1214  if (TID.Opcode == ARM::TPsoft) {
1215    llvm_unreachable("ARM::TPsoft FIXME"); // FIXME
1216  }
1217
1218  // Part of binary is determined by TableGn.
1219  unsigned Binary = getBinaryCodeForInstr(MI);
1220
1221  // Set the conditional execution predicate
1222  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1223
1224  // Set signed_immed_24 field
1225  Binary |= getMachineOpValue(MI, 0);
1226
1227  emitWordLE(Binary);
1228}
1229
1230void ARMCodeEmitter::emitInlineJumpTable(unsigned JTIndex) {
1231  // Remember the base address of the inline jump table.
1232  uintptr_t JTBase = MCE.getCurrentPCValue();
1233  JTI->addJumpTableBaseAddr(JTIndex, JTBase);
1234  DEBUG(errs() << "  ** Jump Table #" << JTIndex << " @ " << (void*)JTBase
1235               << '\n');
1236
1237  // Now emit the jump table entries.
1238  const std::vector<MachineBasicBlock*> &MBBs = (*MJTEs)[JTIndex].MBBs;
1239  for (unsigned i = 0, e = MBBs.size(); i != e; ++i) {
1240    if (IsPIC)
1241      // DestBB address - JT base.
1242      emitMachineBasicBlock(MBBs[i], ARM::reloc_arm_pic_jt, JTBase);
1243    else
1244      // Absolute DestBB address.
1245      emitMachineBasicBlock(MBBs[i], ARM::reloc_arm_absolute);
1246    emitWordLE(0);
1247  }
1248}
1249
1250void ARMCodeEmitter::emitMiscBranchInstruction(const MachineInstr &MI) {
1251  const TargetInstrDesc &TID = MI.getDesc();
1252
1253  // Handle jump tables.
1254  if (TID.Opcode == ARM::BR_JTr || TID.Opcode == ARM::BR_JTadd) {
1255    // First emit a ldr pc, [] instruction.
1256    emitDataProcessingInstruction(MI, ARM::PC);
1257
1258    // Then emit the inline jump table.
1259    unsigned JTIndex =
1260      (TID.Opcode == ARM::BR_JTr)
1261      ? MI.getOperand(1).getIndex() : MI.getOperand(2).getIndex();
1262    emitInlineJumpTable(JTIndex);
1263    return;
1264  } else if (TID.Opcode == ARM::BR_JTm) {
1265    // First emit a ldr pc, [] instruction.
1266    emitLoadStoreInstruction(MI, ARM::PC);
1267
1268    // Then emit the inline jump table.
1269    emitInlineJumpTable(MI.getOperand(3).getIndex());
1270    return;
1271  }
1272
1273  // Part of binary is determined by TableGn.
1274  unsigned Binary = getBinaryCodeForInstr(MI);
1275
1276  // Set the conditional execution predicate
1277  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1278
1279  if (TID.Opcode == ARM::BX_RET || TID.Opcode == ARM::MOVPCLR)
1280    // The return register is LR.
1281    Binary |= ARMRegisterInfo::getRegisterNumbering(ARM::LR);
1282  else
1283    // otherwise, set the return register
1284    Binary |= getMachineOpValue(MI, 0);
1285
1286  emitWordLE(Binary);
1287}
1288
1289static unsigned encodeVFPRd(const MachineInstr &MI, unsigned OpIdx) {
1290  unsigned RegD = MI.getOperand(OpIdx).getReg();
1291  unsigned Binary = 0;
1292  bool isSPVFP = false;
1293  RegD = ARMRegisterInfo::getRegisterNumbering(RegD, &isSPVFP);
1294  if (!isSPVFP)
1295    Binary |=   RegD               << ARMII::RegRdShift;
1296  else {
1297    Binary |= ((RegD & 0x1E) >> 1) << ARMII::RegRdShift;
1298    Binary |=  (RegD & 0x01)       << ARMII::D_BitShift;
1299  }
1300  return Binary;
1301}
1302
1303static unsigned encodeVFPRn(const MachineInstr &MI, unsigned OpIdx) {
1304  unsigned RegN = MI.getOperand(OpIdx).getReg();
1305  unsigned Binary = 0;
1306  bool isSPVFP = false;
1307  RegN = ARMRegisterInfo::getRegisterNumbering(RegN, &isSPVFP);
1308  if (!isSPVFP)
1309    Binary |=   RegN               << ARMII::RegRnShift;
1310  else {
1311    Binary |= ((RegN & 0x1E) >> 1) << ARMII::RegRnShift;
1312    Binary |=  (RegN & 0x01)       << ARMII::N_BitShift;
1313  }
1314  return Binary;
1315}
1316
1317static unsigned encodeVFPRm(const MachineInstr &MI, unsigned OpIdx) {
1318  unsigned RegM = MI.getOperand(OpIdx).getReg();
1319  unsigned Binary = 0;
1320  bool isSPVFP = false;
1321  RegM = ARMRegisterInfo::getRegisterNumbering(RegM, &isSPVFP);
1322  if (!isSPVFP)
1323    Binary |=   RegM;
1324  else {
1325    Binary |= ((RegM & 0x1E) >> 1);
1326    Binary |=  (RegM & 0x01)       << ARMII::M_BitShift;
1327  }
1328  return Binary;
1329}
1330
1331void ARMCodeEmitter::emitVFPArithInstruction(const MachineInstr &MI) {
1332  const TargetInstrDesc &TID = MI.getDesc();
1333
1334  // Part of binary is determined by TableGn.
1335  unsigned Binary = getBinaryCodeForInstr(MI);
1336
1337  // Set the conditional execution predicate
1338  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1339
1340  unsigned OpIdx = 0;
1341  assert((Binary & ARMII::D_BitShift) == 0 &&
1342         (Binary & ARMII::N_BitShift) == 0 &&
1343         (Binary & ARMII::M_BitShift) == 0 && "VFP encoding bug!");
1344
1345  // Encode Dd / Sd.
1346  Binary |= encodeVFPRd(MI, OpIdx++);
1347
1348  // If this is a two-address operand, skip it, e.g. FMACD.
1349  if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1350    ++OpIdx;
1351
1352  // Encode Dn / Sn.
1353  if ((TID.TSFlags & ARMII::FormMask) == ARMII::VFPBinaryFrm)
1354    Binary |= encodeVFPRn(MI, OpIdx++);
1355
1356  if (OpIdx == TID.getNumOperands() ||
1357      TID.OpInfo[OpIdx].isPredicate() ||
1358      TID.OpInfo[OpIdx].isOptionalDef()) {
1359    // FCMPEZD etc. has only one operand.
1360    emitWordLE(Binary);
1361    return;
1362  }
1363
1364  // Encode Dm / Sm.
1365  Binary |= encodeVFPRm(MI, OpIdx);
1366
1367  emitWordLE(Binary);
1368}
1369
1370void ARMCodeEmitter::emitVFPConversionInstruction(const MachineInstr &MI) {
1371  const TargetInstrDesc &TID = MI.getDesc();
1372  unsigned Form = TID.TSFlags & ARMII::FormMask;
1373
1374  // Part of binary is determined by TableGn.
1375  unsigned Binary = getBinaryCodeForInstr(MI);
1376
1377  // Set the conditional execution predicate
1378  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1379
1380  switch (Form) {
1381  default: break;
1382  case ARMII::VFPConv1Frm:
1383  case ARMII::VFPConv2Frm:
1384  case ARMII::VFPConv3Frm:
1385    // Encode Dd / Sd.
1386    Binary |= encodeVFPRd(MI, 0);
1387    break;
1388  case ARMII::VFPConv4Frm:
1389    // Encode Dn / Sn.
1390    Binary |= encodeVFPRn(MI, 0);
1391    break;
1392  case ARMII::VFPConv5Frm:
1393    // Encode Dm / Sm.
1394    Binary |= encodeVFPRm(MI, 0);
1395    break;
1396  }
1397
1398  switch (Form) {
1399  default: break;
1400  case ARMII::VFPConv1Frm:
1401    // Encode Dm / Sm.
1402    Binary |= encodeVFPRm(MI, 1);
1403    break;
1404  case ARMII::VFPConv2Frm:
1405  case ARMII::VFPConv3Frm:
1406    // Encode Dn / Sn.
1407    Binary |= encodeVFPRn(MI, 1);
1408    break;
1409  case ARMII::VFPConv4Frm:
1410  case ARMII::VFPConv5Frm:
1411    // Encode Dd / Sd.
1412    Binary |= encodeVFPRd(MI, 1);
1413    break;
1414  }
1415
1416  if (Form == ARMII::VFPConv5Frm)
1417    // Encode Dn / Sn.
1418    Binary |= encodeVFPRn(MI, 2);
1419  else if (Form == ARMII::VFPConv3Frm)
1420    // Encode Dm / Sm.
1421    Binary |= encodeVFPRm(MI, 2);
1422
1423  emitWordLE(Binary);
1424}
1425
1426void ARMCodeEmitter::emitVFPLoadStoreInstruction(const MachineInstr &MI) {
1427  // Part of binary is determined by TableGn.
1428  unsigned Binary = getBinaryCodeForInstr(MI);
1429
1430  // Set the conditional execution predicate
1431  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1432
1433  unsigned OpIdx = 0;
1434
1435  // Encode Dd / Sd.
1436  Binary |= encodeVFPRd(MI, OpIdx++);
1437
1438  // Encode address base.
1439  const MachineOperand &Base = MI.getOperand(OpIdx++);
1440  Binary |= getMachineOpValue(MI, Base) << ARMII::RegRnShift;
1441
1442  // If there is a non-zero immediate offset, encode it.
1443  if (Base.isReg()) {
1444    const MachineOperand &Offset = MI.getOperand(OpIdx);
1445    if (unsigned ImmOffs = ARM_AM::getAM5Offset(Offset.getImm())) {
1446      if (ARM_AM::getAM5Op(Offset.getImm()) == ARM_AM::add)
1447        Binary |= 1 << ARMII::U_BitShift;
1448      Binary |= ImmOffs;
1449      emitWordLE(Binary);
1450      return;
1451    }
1452  }
1453
1454  // If immediate offset is omitted, default to +0.
1455  Binary |= 1 << ARMII::U_BitShift;
1456
1457  emitWordLE(Binary);
1458}
1459
1460void
1461ARMCodeEmitter::emitVFPLoadStoreMultipleInstruction(const MachineInstr &MI) {
1462  const TargetInstrDesc &TID = MI.getDesc();
1463  bool IsUpdating = (TID.TSFlags & ARMII::IndexModeMask) != 0;
1464
1465  // Part of binary is determined by TableGn.
1466  unsigned Binary = getBinaryCodeForInstr(MI);
1467
1468  // Set the conditional execution predicate
1469  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1470
1471  // Skip operand 0 of an instruction with base register update.
1472  unsigned OpIdx = 0;
1473  if (IsUpdating)
1474    ++OpIdx;
1475
1476  // Set base address operand
1477  Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
1478
1479  // Set addressing mode by modifying bits U(23) and P(24)
1480  const MachineOperand &MO = MI.getOperand(OpIdx++);
1481  Binary |= getAddrModeUPBits(ARM_AM::getAM5SubMode(MO.getImm()));
1482
1483  // Set bit W(21)
1484  if (IsUpdating)
1485    Binary |= 0x1 << ARMII::W_BitShift;
1486
1487  // First register is encoded in Dd.
1488  Binary |= encodeVFPRd(MI, OpIdx+2);
1489
1490  // Number of registers are encoded in offset field.
1491  unsigned NumRegs = 1;
1492  for (unsigned i = OpIdx+3, e = MI.getNumOperands(); i != e; ++i) {
1493    const MachineOperand &MO = MI.getOperand(i);
1494    if (!MO.isReg() || MO.isImplicit())
1495      break;
1496    ++NumRegs;
1497  }
1498  // Bit 8 will be set if <list> is consecutive 64-bit registers (e.g., D0)
1499  // Otherwise, it will be 0, in the case of 32-bit registers.
1500  if(Binary & 0x100)
1501    Binary |= NumRegs * 2;
1502  else
1503    Binary |= NumRegs;
1504
1505  emitWordLE(Binary);
1506}
1507
1508void ARMCodeEmitter::emitMiscInstruction(const MachineInstr &MI) {
1509  unsigned Opcode = MI.getDesc().Opcode;
1510  // Part of binary is determined by TableGn.
1511  unsigned Binary = getBinaryCodeForInstr(MI);
1512
1513  // Set the conditional execution predicate
1514  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1515
1516  switch(Opcode) {
1517  default:
1518    llvm_unreachable("ARMCodeEmitter::emitMiscInstruction");
1519
1520  case ARM::FMSTAT:
1521    // No further encoding needed.
1522    break;
1523
1524  case ARM::VMRS:
1525  case ARM::VMSR: {
1526    const MachineOperand &MO0 = MI.getOperand(0);
1527    // Encode Rt.
1528    Binary |= ARMRegisterInfo::getRegisterNumbering(MO0.getReg())
1529                << ARMII::RegRdShift;
1530    break;
1531  }
1532
1533  case ARM::FCONSTD:
1534  case ARM::FCONSTS: {
1535    // Encode Dd / Sd.
1536    Binary |= encodeVFPRd(MI, 0);
1537
1538    // Encode imm., Table A7-18 VFP modified immediate constants
1539    const MachineOperand &MO1 = MI.getOperand(1);
1540    unsigned Imm = static_cast<unsigned>(MO1.getFPImm()->getValueAPF()
1541                      .bitcastToAPInt().getHiBits(32).getLimitedValue());
1542    unsigned ModifiedImm;
1543
1544    if(Opcode == ARM::FCONSTS)
1545      ModifiedImm = (Imm & 0x80000000) >> 24 | // a
1546                    (Imm & 0x03F80000) >> 19;  // bcdefgh
1547    else // Opcode == ARM::FCONSTD
1548      ModifiedImm = (Imm & 0x80000000) >> 24 | // a
1549                    (Imm & 0x007F0000) >> 16;  // bcdefgh
1550
1551    // Insts{19-16} = abcd, Insts{3-0} = efgh
1552    Binary |= ((ModifiedImm & 0xF0) >> 4) << 16;
1553    Binary |= (ModifiedImm & 0xF);
1554    break;
1555  }
1556  }
1557
1558  emitWordLE(Binary);
1559}
1560
1561static unsigned encodeNEONRd(const MachineInstr &MI, unsigned OpIdx) {
1562  unsigned RegD = MI.getOperand(OpIdx).getReg();
1563  unsigned Binary = 0;
1564  RegD = ARMRegisterInfo::getRegisterNumbering(RegD);
1565  Binary |= (RegD & 0xf) << ARMII::RegRdShift;
1566  Binary |= ((RegD >> 4) & 1) << ARMII::D_BitShift;
1567  return Binary;
1568}
1569
1570static unsigned encodeNEONRn(const MachineInstr &MI, unsigned OpIdx) {
1571  unsigned RegN = MI.getOperand(OpIdx).getReg();
1572  unsigned Binary = 0;
1573  RegN = ARMRegisterInfo::getRegisterNumbering(RegN);
1574  Binary |= (RegN & 0xf) << ARMII::RegRnShift;
1575  Binary |= ((RegN >> 4) & 1) << ARMII::N_BitShift;
1576  return Binary;
1577}
1578
1579static unsigned encodeNEONRm(const MachineInstr &MI, unsigned OpIdx) {
1580  unsigned RegM = MI.getOperand(OpIdx).getReg();
1581  unsigned Binary = 0;
1582  RegM = ARMRegisterInfo::getRegisterNumbering(RegM);
1583  Binary |= (RegM & 0xf);
1584  Binary |= ((RegM >> 4) & 1) << ARMII::M_BitShift;
1585  return Binary;
1586}
1587
1588/// convertNEONDataProcToThumb - Convert the ARM mode encoding for a NEON
1589/// data-processing instruction to the corresponding Thumb encoding.
1590static unsigned convertNEONDataProcToThumb(unsigned Binary) {
1591  assert((Binary & 0xfe000000) == 0xf2000000 &&
1592         "not an ARM NEON data-processing instruction");
1593  unsigned UBit = (Binary >> 24) & 1;
1594  return 0xef000000 | (UBit << 28) | (Binary & 0xffffff);
1595}
1596
1597void ARMCodeEmitter::emitNEONGetLaneInstruction(const MachineInstr &MI) {
1598  unsigned Binary = getBinaryCodeForInstr(MI);
1599
1600  // Set the conditional execution predicate
1601  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1602
1603  unsigned RegT = MI.getOperand(0).getReg();
1604  RegT = ARMRegisterInfo::getRegisterNumbering(RegT);
1605  Binary |= (RegT << ARMII::RegRdShift);
1606  Binary |= encodeNEONRn(MI, 1);
1607
1608  unsigned LaneShift;
1609  if ((Binary & (1 << 22)) != 0)
1610    LaneShift = 0; // 8-bit elements
1611  else if ((Binary & (1 << 5)) != 0)
1612    LaneShift = 1; // 16-bit elements
1613  else
1614    LaneShift = 2; // 32-bit elements
1615
1616  unsigned Lane = MI.getOperand(2).getImm() << LaneShift;
1617  unsigned Opc1 = Lane >> 2;
1618  unsigned Opc2 = Lane & 3;
1619  assert((Opc1 & 3) == 0 && "out-of-range lane number operand");
1620  Binary |= (Opc1 << 21);
1621  Binary |= (Opc2 << 5);
1622
1623  emitWordLE(Binary);
1624}
1625
1626void ARMCodeEmitter::emitNEON1RegModImmInstruction(const MachineInstr &MI) {
1627  unsigned Binary = getBinaryCodeForInstr(MI);
1628  // Destination register is encoded in Dd.
1629  Binary |= encodeNEONRd(MI, 0);
1630  // Immediate fields: Op, Cmode, I, Imm3, Imm4
1631  unsigned Imm = MI.getOperand(1).getImm();
1632  unsigned Op = (Imm >> 12) & 1;
1633  unsigned Cmode = (Imm >> 8) & 0xf;
1634  unsigned I = (Imm >> 7) & 1;
1635  unsigned Imm3 = (Imm >> 4) & 0x7;
1636  unsigned Imm4 = Imm & 0xf;
1637  Binary |= (I << 24) | (Imm3 << 16) | (Cmode << 8) | (Op << 5) | Imm4;
1638  if (Subtarget->isThumb())
1639    Binary = convertNEONDataProcToThumb(Binary);
1640  emitWordLE(Binary);
1641}
1642
1643void ARMCodeEmitter::emitNEON2RegInstruction(const MachineInstr &MI) {
1644  const TargetInstrDesc &TID = MI.getDesc();
1645  unsigned Binary = getBinaryCodeForInstr(MI);
1646  // Destination register is encoded in Dd; source register in Dm.
1647  unsigned OpIdx = 0;
1648  Binary |= encodeNEONRd(MI, OpIdx++);
1649  if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1650    ++OpIdx;
1651  Binary |= encodeNEONRm(MI, OpIdx);
1652  if (Subtarget->isThumb())
1653    Binary = convertNEONDataProcToThumb(Binary);
1654  // FIXME: This does not handle VDUPfdf or VDUPfqf.
1655  emitWordLE(Binary);
1656}
1657
1658void ARMCodeEmitter::emitNEON3RegInstruction(const MachineInstr &MI) {
1659  const TargetInstrDesc &TID = MI.getDesc();
1660  unsigned Binary = getBinaryCodeForInstr(MI);
1661  // Destination register is encoded in Dd; source registers in Dn and Dm.
1662  unsigned OpIdx = 0;
1663  Binary |= encodeNEONRd(MI, OpIdx++);
1664  if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1665    ++OpIdx;
1666  Binary |= encodeNEONRn(MI, OpIdx++);
1667  if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1668    ++OpIdx;
1669  Binary |= encodeNEONRm(MI, OpIdx);
1670  if (Subtarget->isThumb())
1671    Binary = convertNEONDataProcToThumb(Binary);
1672  // FIXME: This does not handle VMOVDneon or VMOVQ.
1673  emitWordLE(Binary);
1674}
1675
1676#include "ARMGenCodeEmitter.inc"
1677