ARMCodeEmitter.cpp revision 0e1bcdf4f7547bb5f47ed5ff5f2409a8f72f3609
1//===-- ARM/ARMCodeEmitter.cpp - Convert ARM code to machine code ---------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the pass that transforms the ARM machine instructions into 11// relocatable machine code. 12// 13//===----------------------------------------------------------------------===// 14 15#define DEBUG_TYPE "jit" 16#include "ARM.h" 17#include "ARMAddressingModes.h" 18#include "ARMConstantPoolValue.h" 19#include "ARMInstrInfo.h" 20#include "ARMRelocations.h" 21#include "ARMSubtarget.h" 22#include "ARMTargetMachine.h" 23#include "llvm/Constants.h" 24#include "llvm/DerivedTypes.h" 25#include "llvm/Function.h" 26#include "llvm/PassManager.h" 27#include "llvm/CodeGen/JITCodeEmitter.h" 28#include "llvm/CodeGen/MachineConstantPool.h" 29#include "llvm/CodeGen/MachineFunctionPass.h" 30#include "llvm/CodeGen/MachineInstr.h" 31#include "llvm/CodeGen/MachineJumpTableInfo.h" 32#include "llvm/CodeGen/MachineModuleInfo.h" 33#include "llvm/CodeGen/Passes.h" 34#include "llvm/ADT/Statistic.h" 35#include "llvm/Support/Debug.h" 36#include "llvm/Support/ErrorHandling.h" 37#include "llvm/Support/raw_ostream.h" 38#ifndef NDEBUG 39#include <iomanip> 40#endif 41using namespace llvm; 42 43STATISTIC(NumEmitted, "Number of machine instructions emitted"); 44 45namespace { 46 47 class ARMCodeEmitter : public MachineFunctionPass { 48 ARMJITInfo *JTI; 49 const ARMInstrInfo *II; 50 const TargetData *TD; 51 const ARMSubtarget *Subtarget; 52 TargetMachine &TM; 53 JITCodeEmitter &MCE; 54 MachineModuleInfo *MMI; 55 const std::vector<MachineConstantPoolEntry> *MCPEs; 56 const std::vector<MachineJumpTableEntry> *MJTEs; 57 bool IsPIC; 58 bool IsThumb; 59 60 void getAnalysisUsage(AnalysisUsage &AU) const { 61 AU.addRequired<MachineModuleInfo>(); 62 MachineFunctionPass::getAnalysisUsage(AU); 63 } 64 65 static char ID; 66 public: 67 ARMCodeEmitter(TargetMachine &tm, JITCodeEmitter &mce) 68 : MachineFunctionPass(ID), JTI(0), 69 II((const ARMInstrInfo *)tm.getInstrInfo()), 70 TD(tm.getTargetData()), TM(tm), 71 MCE(mce), MCPEs(0), MJTEs(0), 72 IsPIC(TM.getRelocationModel() == Reloc::PIC_), IsThumb(false) {} 73 74 /// getBinaryCodeForInstr - This function, generated by the 75 /// CodeEmitterGenerator using TableGen, produces the binary encoding for 76 /// machine instructions. 77 unsigned getBinaryCodeForInstr(const MachineInstr &MI) const; 78 79 bool runOnMachineFunction(MachineFunction &MF); 80 81 virtual const char *getPassName() const { 82 return "ARM Machine Code Emitter"; 83 } 84 85 void emitInstruction(const MachineInstr &MI); 86 87 private: 88 89 void emitWordLE(unsigned Binary); 90 void emitDWordLE(uint64_t Binary); 91 void emitConstPoolInstruction(const MachineInstr &MI); 92 void emitMOVi32immInstruction(const MachineInstr &MI); 93 void emitMOVi2piecesInstruction(const MachineInstr &MI); 94 void emitLEApcrelJTInstruction(const MachineInstr &MI); 95 void emitPseudoMoveInstruction(const MachineInstr &MI); 96 void addPCLabel(unsigned LabelID); 97 void emitPseudoInstruction(const MachineInstr &MI); 98 unsigned getMachineSoRegOpValue(const MachineInstr &MI, 99 const TargetInstrDesc &TID, 100 const MachineOperand &MO, 101 unsigned OpIdx); 102 103 unsigned getMachineSoImmOpValue(unsigned SoImm); 104 unsigned getAddrModeSBit(const MachineInstr &MI, 105 const TargetInstrDesc &TID) const; 106 107 void emitDataProcessingInstruction(const MachineInstr &MI, 108 unsigned ImplicitRd = 0, 109 unsigned ImplicitRn = 0); 110 111 void emitLoadStoreInstruction(const MachineInstr &MI, 112 unsigned ImplicitRd = 0, 113 unsigned ImplicitRn = 0); 114 115 void emitMiscLoadStoreInstruction(const MachineInstr &MI, 116 unsigned ImplicitRn = 0); 117 118 void emitLoadStoreMultipleInstruction(const MachineInstr &MI); 119 120 void emitMulFrmInstruction(const MachineInstr &MI); 121 122 void emitExtendInstruction(const MachineInstr &MI); 123 124 void emitMiscArithInstruction(const MachineInstr &MI); 125 126 void emitSaturateInstruction(const MachineInstr &MI); 127 128 void emitBranchInstruction(const MachineInstr &MI); 129 130 void emitInlineJumpTable(unsigned JTIndex); 131 132 void emitMiscBranchInstruction(const MachineInstr &MI); 133 134 void emitVFPArithInstruction(const MachineInstr &MI); 135 136 void emitVFPConversionInstruction(const MachineInstr &MI); 137 138 void emitVFPLoadStoreInstruction(const MachineInstr &MI); 139 140 void emitVFPLoadStoreMultipleInstruction(const MachineInstr &MI); 141 142 void emitNEONLaneInstruction(const MachineInstr &MI); 143 void emitNEONDupInstruction(const MachineInstr &MI); 144 void emitNEON1RegModImmInstruction(const MachineInstr &MI); 145 void emitNEON2RegInstruction(const MachineInstr &MI); 146 void emitNEON3RegInstruction(const MachineInstr &MI); 147 148 /// getMachineOpValue - Return binary encoding of operand. If the machine 149 /// operand requires relocation, record the relocation and return zero. 150 unsigned getMachineOpValue(const MachineInstr &MI, 151 const MachineOperand &MO) const; 152 unsigned getMachineOpValue(const MachineInstr &MI, unsigned OpIdx) const { 153 return getMachineOpValue(MI, MI.getOperand(OpIdx)); 154 } 155 156 // FIXME: The legacy JIT ARMCodeEmitter doesn't rely on the the 157 // TableGen'erated getBinaryCodeForInstr() function to encode any 158 // operand values, instead querying getMachineOpValue() directly for 159 // each operand it needs to encode. Thus, any of the new encoder 160 // helper functions can simply return 0 as the values the return 161 // are already handled elsewhere. They are placeholders to allow this 162 // encoder to continue to function until the MC encoder is sufficiently 163 // far along that this one can be eliminated entirely. 164 unsigned NEONThumb2DataIPostEncoder(const MachineInstr &MI, unsigned Val) 165 const { return 0; } 166 unsigned NEONThumb2LoadStorePostEncoder(const MachineInstr &MI,unsigned Val) 167 const { return 0; } 168 unsigned NEONThumb2DupPostEncoder(const MachineInstr &MI,unsigned Val) 169 const { return 0; } 170 unsigned getBranchTargetOpValue(const MachineInstr &MI, unsigned Op) 171 const { return 0; } 172 unsigned getCCOutOpValue(const MachineInstr &MI, unsigned Op) 173 const { return 0; } 174 unsigned getSOImmOpValue(const MachineInstr &MI, unsigned Op) 175 const { return 0; } 176 unsigned getT2SOImmOpValue(const MachineInstr &MI, unsigned Op) 177 const { return 0; } 178 unsigned getSORegOpValue(const MachineInstr &MI, unsigned Op) 179 const { return 0; } 180 unsigned getT2AddrModeImm12OpValue(const MachineInstr &MI, unsigned Op) 181 const { return 0; } 182 unsigned getT2AddrModeImm8OpValue(const MachineInstr &MI, unsigned Op) 183 const { return 0; } 184 unsigned getT2AddrModeImm8OffsetOpValue(const MachineInstr &MI, unsigned Op) 185 const { return 0; } 186 unsigned getT2AddrModeImm12OffsetOpValue(const MachineInstr &MI,unsigned Op) 187 const { return 0; } 188 unsigned getT2AddrModeSORegOpValue(const MachineInstr &MI, unsigned Op) 189 const { return 0; } 190 unsigned getT2SORegOpValue(const MachineInstr &MI, unsigned Op) 191 const { return 0; } 192 unsigned getRotImmOpValue(const MachineInstr &MI, unsigned Op) 193 const { return 0; } 194 unsigned getImmMinusOneOpValue(const MachineInstr &MI, unsigned Op) 195 const { return 0; } 196 unsigned getAddrMode6AddressOpValue(const MachineInstr &MI, unsigned Op) 197 const { return 0; } 198 unsigned getAddrMode6DupAddressOpValue(const MachineInstr &MI, unsigned Op) 199 const { return 0; } 200 unsigned getAddrMode6OffsetOpValue(const MachineInstr &MI, unsigned Op) 201 const { return 0; } 202 unsigned getBitfieldInvertedMaskOpValue(const MachineInstr &MI, 203 unsigned Op) const { return 0; } 204 uint32_t getLdStmModeOpValue(const MachineInstr &MI, unsigned OpIdx) 205 const {return 0; } 206 uint32_t getLdStSORegOpValue(const MachineInstr &MI, unsigned OpIdx) 207 const { return 0; } 208 209 unsigned getAddrModeImm12OpValue(const MachineInstr &MI, unsigned Op) 210 const { 211 // {17-13} = reg 212 // {12} = (U)nsigned (add == '1', sub == '0') 213 // {11-0} = imm12 214 const MachineOperand &MO = MI.getOperand(Op); 215 const MachineOperand &MO1 = MI.getOperand(Op + 1); 216 if (!MO.isReg()) { 217 emitConstPoolAddress(MO.getIndex(), ARM::reloc_arm_cp_entry); 218 return 0; 219 } 220 unsigned Reg = getARMRegisterNumbering(MO.getReg()); 221 int32_t Imm12 = MO1.getImm(); 222 uint32_t Binary; 223 Binary = Imm12 & 0xfff; 224 if (Imm12 >= 0) 225 Binary |= (1 << 12); 226 Binary |= (Reg << 13); 227 return Binary; 228 } 229 230 unsigned getMovtImmOpValue(const MachineInstr &MI, unsigned Op) const { 231 return 0; 232 } 233 234 uint32_t getAddrMode2OpValue(const MachineInstr &MI, unsigned OpIdx) 235 const { return 0;} 236 uint32_t getAddrMode2OffsetOpValue(const MachineInstr &MI, unsigned OpIdx) 237 const { return 0;} 238 uint32_t getAddrMode3OffsetOpValue(const MachineInstr &MI, unsigned OpIdx) 239 const { return 0;} 240 uint32_t getAddrMode3OpValue(const MachineInstr &MI, unsigned Op) 241 const { return 0; } 242 uint32_t getAddrModeS4OpValue(const MachineInstr &MI, unsigned Op) 243 const { return 0; } 244 uint32_t getAddrMode5OpValue(const MachineInstr &MI, unsigned Op) const { 245 // {17-13} = reg 246 // {12} = (U)nsigned (add == '1', sub == '0') 247 // {11-0} = imm12 248 const MachineOperand &MO = MI.getOperand(Op); 249 const MachineOperand &MO1 = MI.getOperand(Op + 1); 250 if (!MO.isReg()) { 251 emitConstPoolAddress(MO.getIndex(), ARM::reloc_arm_cp_entry); 252 return 0; 253 } 254 unsigned Reg = getARMRegisterNumbering(MO.getReg()); 255 int32_t Imm12 = MO1.getImm(); 256 257 // Special value for #-0 258 if (Imm12 == INT32_MIN) 259 Imm12 = 0; 260 261 // Immediate is always encoded as positive. The 'U' bit controls add vs 262 // sub. 263 bool isAdd = true; 264 if (Imm12 < 0) { 265 Imm12 = -Imm12; 266 isAdd = false; 267 } 268 269 uint32_t Binary = Imm12 & 0xfff; 270 if (isAdd) 271 Binary |= (1 << 12); 272 Binary |= (Reg << 13); 273 return Binary; 274 } 275 unsigned getNEONVcvtImm32OpValue(const MachineInstr &MI, unsigned Op) 276 const { return 0; } 277 278 unsigned getRegisterListOpValue(const MachineInstr &MI, unsigned Op) 279 const { return 0; } 280 281 /// getMovi32Value - Return binary encoding of operand for movw/movt. If the 282 /// machine operand requires relocation, record the relocation and return 283 /// zero. 284 unsigned getMovi32Value(const MachineInstr &MI,const MachineOperand &MO, 285 unsigned Reloc); 286 287 /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value. 288 /// 289 unsigned getShiftOp(unsigned Imm) const ; 290 291 /// Routines that handle operands which add machine relocations which are 292 /// fixed up by the relocation stage. 293 void emitGlobalAddress(const GlobalValue *GV, unsigned Reloc, 294 bool MayNeedFarStub, bool Indirect, 295 intptr_t ACPV = 0) const; 296 void emitExternalSymbolAddress(const char *ES, unsigned Reloc) const; 297 void emitConstPoolAddress(unsigned CPI, unsigned Reloc) const; 298 void emitJumpTableAddress(unsigned JTIndex, unsigned Reloc) const; 299 void emitMachineBasicBlock(MachineBasicBlock *BB, unsigned Reloc, 300 intptr_t JTBase = 0) const; 301 }; 302} 303 304char ARMCodeEmitter::ID = 0; 305 306/// createARMJITCodeEmitterPass - Return a pass that emits the collected ARM 307/// code to the specified MCE object. 308FunctionPass *llvm::createARMJITCodeEmitterPass(ARMBaseTargetMachine &TM, 309 JITCodeEmitter &JCE) { 310 return new ARMCodeEmitter(TM, JCE); 311} 312 313bool ARMCodeEmitter::runOnMachineFunction(MachineFunction &MF) { 314 assert((MF.getTarget().getRelocationModel() != Reloc::Default || 315 MF.getTarget().getRelocationModel() != Reloc::Static) && 316 "JIT relocation model must be set to static or default!"); 317 JTI = ((ARMTargetMachine &)MF.getTarget()).getJITInfo(); 318 II = ((const ARMTargetMachine &)MF.getTarget()).getInstrInfo(); 319 TD = ((const ARMTargetMachine &)MF.getTarget()).getTargetData(); 320 Subtarget = &TM.getSubtarget<ARMSubtarget>(); 321 MCPEs = &MF.getConstantPool()->getConstants(); 322 MJTEs = 0; 323 if (MF.getJumpTableInfo()) MJTEs = &MF.getJumpTableInfo()->getJumpTables(); 324 IsPIC = TM.getRelocationModel() == Reloc::PIC_; 325 IsThumb = MF.getInfo<ARMFunctionInfo>()->isThumbFunction(); 326 JTI->Initialize(MF, IsPIC); 327 MMI = &getAnalysis<MachineModuleInfo>(); 328 MCE.setModuleInfo(MMI); 329 330 do { 331 DEBUG(errs() << "JITTing function '" 332 << MF.getFunction()->getName() << "'\n"); 333 MCE.startFunction(MF); 334 for (MachineFunction::iterator MBB = MF.begin(), E = MF.end(); 335 MBB != E; ++MBB) { 336 MCE.StartMachineBasicBlock(MBB); 337 for (MachineBasicBlock::const_iterator I = MBB->begin(), E = MBB->end(); 338 I != E; ++I) 339 emitInstruction(*I); 340 } 341 } while (MCE.finishFunction(MF)); 342 343 return false; 344} 345 346/// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value. 347/// 348unsigned ARMCodeEmitter::getShiftOp(unsigned Imm) const { 349 switch (ARM_AM::getAM2ShiftOpc(Imm)) { 350 default: llvm_unreachable("Unknown shift opc!"); 351 case ARM_AM::asr: return 2; 352 case ARM_AM::lsl: return 0; 353 case ARM_AM::lsr: return 1; 354 case ARM_AM::ror: 355 case ARM_AM::rrx: return 3; 356 } 357 return 0; 358} 359 360/// getMovi32Value - Return binary encoding of operand for movw/movt. If the 361/// machine operand requires relocation, record the relocation and return zero. 362unsigned ARMCodeEmitter::getMovi32Value(const MachineInstr &MI, 363 const MachineOperand &MO, 364 unsigned Reloc) { 365 assert(((Reloc == ARM::reloc_arm_movt) || (Reloc == ARM::reloc_arm_movw)) 366 && "Relocation to this function should be for movt or movw"); 367 368 if (MO.isImm()) 369 return static_cast<unsigned>(MO.getImm()); 370 else if (MO.isGlobal()) 371 emitGlobalAddress(MO.getGlobal(), Reloc, true, false); 372 else if (MO.isSymbol()) 373 emitExternalSymbolAddress(MO.getSymbolName(), Reloc); 374 else if (MO.isMBB()) 375 emitMachineBasicBlock(MO.getMBB(), Reloc); 376 else { 377#ifndef NDEBUG 378 errs() << MO; 379#endif 380 llvm_unreachable("Unsupported operand type for movw/movt"); 381 } 382 return 0; 383} 384 385/// getMachineOpValue - Return binary encoding of operand. If the machine 386/// operand requires relocation, record the relocation and return zero. 387unsigned ARMCodeEmitter::getMachineOpValue(const MachineInstr &MI, 388 const MachineOperand &MO) const { 389 if (MO.isReg()) 390 return getARMRegisterNumbering(MO.getReg()); 391 else if (MO.isImm()) 392 return static_cast<unsigned>(MO.getImm()); 393 else if (MO.isGlobal()) 394 emitGlobalAddress(MO.getGlobal(), ARM::reloc_arm_branch, true, false); 395 else if (MO.isSymbol()) 396 emitExternalSymbolAddress(MO.getSymbolName(), ARM::reloc_arm_branch); 397 else if (MO.isCPI()) { 398 const TargetInstrDesc &TID = MI.getDesc(); 399 // For VFP load, the immediate offset is multiplied by 4. 400 unsigned Reloc = ((TID.TSFlags & ARMII::FormMask) == ARMII::VFPLdStFrm) 401 ? ARM::reloc_arm_vfp_cp_entry : ARM::reloc_arm_cp_entry; 402 emitConstPoolAddress(MO.getIndex(), Reloc); 403 } else if (MO.isJTI()) 404 emitJumpTableAddress(MO.getIndex(), ARM::reloc_arm_relative); 405 else if (MO.isMBB()) 406 emitMachineBasicBlock(MO.getMBB(), ARM::reloc_arm_branch); 407 else 408 llvm_unreachable("Unable to encode MachineOperand!"); 409 return 0; 410} 411 412/// emitGlobalAddress - Emit the specified address to the code stream. 413/// 414void ARMCodeEmitter::emitGlobalAddress(const GlobalValue *GV, unsigned Reloc, 415 bool MayNeedFarStub, bool Indirect, 416 intptr_t ACPV) const { 417 MachineRelocation MR = Indirect 418 ? MachineRelocation::getIndirectSymbol(MCE.getCurrentPCOffset(), Reloc, 419 const_cast<GlobalValue *>(GV), 420 ACPV, MayNeedFarStub) 421 : MachineRelocation::getGV(MCE.getCurrentPCOffset(), Reloc, 422 const_cast<GlobalValue *>(GV), ACPV, 423 MayNeedFarStub); 424 MCE.addRelocation(MR); 425} 426 427/// emitExternalSymbolAddress - Arrange for the address of an external symbol to 428/// be emitted to the current location in the function, and allow it to be PC 429/// relative. 430void ARMCodeEmitter:: 431emitExternalSymbolAddress(const char *ES, unsigned Reloc) const { 432 MCE.addRelocation(MachineRelocation::getExtSym(MCE.getCurrentPCOffset(), 433 Reloc, ES)); 434} 435 436/// emitConstPoolAddress - Arrange for the address of an constant pool 437/// to be emitted to the current location in the function, and allow it to be PC 438/// relative. 439void ARMCodeEmitter::emitConstPoolAddress(unsigned CPI, unsigned Reloc) const { 440 // Tell JIT emitter we'll resolve the address. 441 MCE.addRelocation(MachineRelocation::getConstPool(MCE.getCurrentPCOffset(), 442 Reloc, CPI, 0, true)); 443} 444 445/// emitJumpTableAddress - Arrange for the address of a jump table to 446/// be emitted to the current location in the function, and allow it to be PC 447/// relative. 448void ARMCodeEmitter:: 449emitJumpTableAddress(unsigned JTIndex, unsigned Reloc) const { 450 MCE.addRelocation(MachineRelocation::getJumpTable(MCE.getCurrentPCOffset(), 451 Reloc, JTIndex, 0, true)); 452} 453 454/// emitMachineBasicBlock - Emit the specified address basic block. 455void ARMCodeEmitter::emitMachineBasicBlock(MachineBasicBlock *BB, 456 unsigned Reloc, 457 intptr_t JTBase) const { 458 MCE.addRelocation(MachineRelocation::getBB(MCE.getCurrentPCOffset(), 459 Reloc, BB, JTBase)); 460} 461 462void ARMCodeEmitter::emitWordLE(unsigned Binary) { 463 DEBUG(errs() << " 0x"; 464 errs().write_hex(Binary) << "\n"); 465 MCE.emitWordLE(Binary); 466} 467 468void ARMCodeEmitter::emitDWordLE(uint64_t Binary) { 469 DEBUG(errs() << " 0x"; 470 errs().write_hex(Binary) << "\n"); 471 MCE.emitDWordLE(Binary); 472} 473 474void ARMCodeEmitter::emitInstruction(const MachineInstr &MI) { 475 DEBUG(errs() << "JIT: " << (void*)MCE.getCurrentPCValue() << ":\t" << MI); 476 477 MCE.processDebugLoc(MI.getDebugLoc(), true); 478 479 ++NumEmitted; // Keep track of the # of mi's emitted 480 switch (MI.getDesc().TSFlags & ARMII::FormMask) { 481 default: { 482 llvm_unreachable("Unhandled instruction encoding format!"); 483 break; 484 } 485 case ARMII::MiscFrm: 486 if (MI.getOpcode() == ARM::LEApcrelJT) { 487 // Materialize jumptable address. 488 emitLEApcrelJTInstruction(MI); 489 break; 490 } 491 llvm_unreachable("Unhandled instruction encoding!"); 492 break; 493 case ARMII::Pseudo: 494 emitPseudoInstruction(MI); 495 break; 496 case ARMII::DPFrm: 497 case ARMII::DPSoRegFrm: 498 emitDataProcessingInstruction(MI); 499 break; 500 case ARMII::LdFrm: 501 case ARMII::StFrm: 502 emitLoadStoreInstruction(MI); 503 break; 504 case ARMII::LdMiscFrm: 505 case ARMII::StMiscFrm: 506 emitMiscLoadStoreInstruction(MI); 507 break; 508 case ARMII::LdStMulFrm: 509 emitLoadStoreMultipleInstruction(MI); 510 break; 511 case ARMII::MulFrm: 512 emitMulFrmInstruction(MI); 513 break; 514 case ARMII::ExtFrm: 515 emitExtendInstruction(MI); 516 break; 517 case ARMII::ArithMiscFrm: 518 emitMiscArithInstruction(MI); 519 break; 520 case ARMII::SatFrm: 521 emitSaturateInstruction(MI); 522 break; 523 case ARMII::BrFrm: 524 emitBranchInstruction(MI); 525 break; 526 case ARMII::BrMiscFrm: 527 emitMiscBranchInstruction(MI); 528 break; 529 // VFP instructions. 530 case ARMII::VFPUnaryFrm: 531 case ARMII::VFPBinaryFrm: 532 emitVFPArithInstruction(MI); 533 break; 534 case ARMII::VFPConv1Frm: 535 case ARMII::VFPConv2Frm: 536 case ARMII::VFPConv3Frm: 537 case ARMII::VFPConv4Frm: 538 case ARMII::VFPConv5Frm: 539 emitVFPConversionInstruction(MI); 540 break; 541 case ARMII::VFPLdStFrm: 542 emitVFPLoadStoreInstruction(MI); 543 break; 544 case ARMII::VFPLdStMulFrm: 545 emitVFPLoadStoreMultipleInstruction(MI); 546 break; 547 548 // NEON instructions. 549 case ARMII::NGetLnFrm: 550 case ARMII::NSetLnFrm: 551 emitNEONLaneInstruction(MI); 552 break; 553 case ARMII::NDupFrm: 554 emitNEONDupInstruction(MI); 555 break; 556 case ARMII::N1RegModImmFrm: 557 emitNEON1RegModImmInstruction(MI); 558 break; 559 case ARMII::N2RegFrm: 560 emitNEON2RegInstruction(MI); 561 break; 562 case ARMII::N3RegFrm: 563 emitNEON3RegInstruction(MI); 564 break; 565 } 566 MCE.processDebugLoc(MI.getDebugLoc(), false); 567} 568 569void ARMCodeEmitter::emitConstPoolInstruction(const MachineInstr &MI) { 570 unsigned CPI = MI.getOperand(0).getImm(); // CP instruction index. 571 unsigned CPIndex = MI.getOperand(1).getIndex(); // Actual cp entry index. 572 const MachineConstantPoolEntry &MCPE = (*MCPEs)[CPIndex]; 573 574 // Remember the CONSTPOOL_ENTRY address for later relocation. 575 JTI->addConstantPoolEntryAddr(CPI, MCE.getCurrentPCValue()); 576 577 // Emit constpool island entry. In most cases, the actual values will be 578 // resolved and relocated after code emission. 579 if (MCPE.isMachineConstantPoolEntry()) { 580 ARMConstantPoolValue *ACPV = 581 static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal); 582 583 DEBUG(errs() << " ** ARM constant pool #" << CPI << " @ " 584 << (void*)MCE.getCurrentPCValue() << " " << *ACPV << '\n'); 585 586 assert(ACPV->isGlobalValue() && "unsupported constant pool value"); 587 const GlobalValue *GV = ACPV->getGV(); 588 if (GV) { 589 Reloc::Model RelocM = TM.getRelocationModel(); 590 emitGlobalAddress(GV, ARM::reloc_arm_machine_cp_entry, 591 isa<Function>(GV), 592 Subtarget->GVIsIndirectSymbol(GV, RelocM), 593 (intptr_t)ACPV); 594 } else { 595 emitExternalSymbolAddress(ACPV->getSymbol(), ARM::reloc_arm_absolute); 596 } 597 emitWordLE(0); 598 } else { 599 const Constant *CV = MCPE.Val.ConstVal; 600 601 DEBUG({ 602 errs() << " ** Constant pool #" << CPI << " @ " 603 << (void*)MCE.getCurrentPCValue() << " "; 604 if (const Function *F = dyn_cast<Function>(CV)) 605 errs() << F->getName(); 606 else 607 errs() << *CV; 608 errs() << '\n'; 609 }); 610 611 if (const GlobalValue *GV = dyn_cast<GlobalValue>(CV)) { 612 emitGlobalAddress(GV, ARM::reloc_arm_absolute, isa<Function>(GV), false); 613 emitWordLE(0); 614 } else if (const ConstantInt *CI = dyn_cast<ConstantInt>(CV)) { 615 uint32_t Val = uint32_t(*CI->getValue().getRawData()); 616 emitWordLE(Val); 617 } else if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CV)) { 618 if (CFP->getType()->isFloatTy()) 619 emitWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue()); 620 else if (CFP->getType()->isDoubleTy()) 621 emitDWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue()); 622 else { 623 llvm_unreachable("Unable to handle this constantpool entry!"); 624 } 625 } else { 626 llvm_unreachable("Unable to handle this constantpool entry!"); 627 } 628 } 629} 630 631void ARMCodeEmitter::emitMOVi32immInstruction(const MachineInstr &MI) { 632 const MachineOperand &MO0 = MI.getOperand(0); 633 const MachineOperand &MO1 = MI.getOperand(1); 634 635 // Emit the 'movw' instruction. 636 unsigned Binary = 0x30 << 20; // mov: Insts{27-20} = 0b00110000 637 638 unsigned Lo16 = getMovi32Value(MI, MO1, ARM::reloc_arm_movw) & 0xFFFF; 639 640 // Set the conditional execution predicate. 641 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 642 643 // Encode Rd. 644 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift; 645 646 // Encode imm16 as imm4:imm12 647 Binary |= Lo16 & 0xFFF; // Insts{11-0} = imm12 648 Binary |= ((Lo16 >> 12) & 0xF) << 16; // Insts{19-16} = imm4 649 emitWordLE(Binary); 650 651 unsigned Hi16 = getMovi32Value(MI, MO1, ARM::reloc_arm_movt) >> 16; 652 // Emit the 'movt' instruction. 653 Binary = 0x34 << 20; // movt: Insts{27-20} = 0b00110100 654 655 // Set the conditional execution predicate. 656 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 657 658 // Encode Rd. 659 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift; 660 661 // Encode imm16 as imm4:imm1, same as movw above. 662 Binary |= Hi16 & 0xFFF; 663 Binary |= ((Hi16 >> 12) & 0xF) << 16; 664 emitWordLE(Binary); 665} 666 667void ARMCodeEmitter::emitMOVi2piecesInstruction(const MachineInstr &MI) { 668 const MachineOperand &MO0 = MI.getOperand(0); 669 const MachineOperand &MO1 = MI.getOperand(1); 670 assert(MO1.isImm() && ARM_AM::isSOImmTwoPartVal(MO1.getImm()) && 671 "Not a valid so_imm value!"); 672 unsigned V1 = ARM_AM::getSOImmTwoPartFirst(MO1.getImm()); 673 unsigned V2 = ARM_AM::getSOImmTwoPartSecond(MO1.getImm()); 674 675 // Emit the 'mov' instruction. 676 unsigned Binary = 0xd << 21; // mov: Insts{24-21} = 0b1101 677 678 // Set the conditional execution predicate. 679 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 680 681 // Encode Rd. 682 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift; 683 684 // Encode so_imm. 685 // Set bit I(25) to identify this is the immediate form of <shifter_op> 686 Binary |= 1 << ARMII::I_BitShift; 687 Binary |= getMachineSoImmOpValue(V1); 688 emitWordLE(Binary); 689 690 // Now the 'orr' instruction. 691 Binary = 0xc << 21; // orr: Insts{24-21} = 0b1100 692 693 // Set the conditional execution predicate. 694 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 695 696 // Encode Rd. 697 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift; 698 699 // Encode Rn. 700 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRnShift; 701 702 // Encode so_imm. 703 // Set bit I(25) to identify this is the immediate form of <shifter_op> 704 Binary |= 1 << ARMII::I_BitShift; 705 Binary |= getMachineSoImmOpValue(V2); 706 emitWordLE(Binary); 707} 708 709void ARMCodeEmitter::emitLEApcrelJTInstruction(const MachineInstr &MI) { 710 // It's basically add r, pc, (LJTI - $+8) 711 712 const TargetInstrDesc &TID = MI.getDesc(); 713 714 // Emit the 'add' instruction. 715 unsigned Binary = 0x4 << 21; // add: Insts{24-21} = 0b0100 716 717 // Set the conditional execution predicate 718 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 719 720 // Encode S bit if MI modifies CPSR. 721 Binary |= getAddrModeSBit(MI, TID); 722 723 // Encode Rd. 724 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift; 725 726 // Encode Rn which is PC. 727 Binary |= getARMRegisterNumbering(ARM::PC) << ARMII::RegRnShift; 728 729 // Encode the displacement. 730 Binary |= 1 << ARMII::I_BitShift; 731 emitJumpTableAddress(MI.getOperand(1).getIndex(), ARM::reloc_arm_jt_base); 732 733 emitWordLE(Binary); 734} 735 736void ARMCodeEmitter::emitPseudoMoveInstruction(const MachineInstr &MI) { 737 unsigned Opcode = MI.getDesc().Opcode; 738 739 // Part of binary is determined by TableGn. 740 unsigned Binary = getBinaryCodeForInstr(MI); 741 742 // Set the conditional execution predicate 743 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 744 745 // Encode S bit if MI modifies CPSR. 746 if (Opcode == ARM::MOVsrl_flag || Opcode == ARM::MOVsra_flag) 747 Binary |= 1 << ARMII::S_BitShift; 748 749 // Encode register def if there is one. 750 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift; 751 752 // Encode the shift operation. 753 switch (Opcode) { 754 default: break; 755 case ARM::RRX: 756 // rrx 757 Binary |= 0x6 << 4; 758 break; 759 case ARM::MOVsrl_flag: 760 // lsr #1 761 Binary |= (0x2 << 4) | (1 << 7); 762 break; 763 case ARM::MOVsra_flag: 764 // asr #1 765 Binary |= (0x4 << 4) | (1 << 7); 766 break; 767 } 768 769 // Encode register Rm. 770 Binary |= getMachineOpValue(MI, 1); 771 772 emitWordLE(Binary); 773} 774 775void ARMCodeEmitter::addPCLabel(unsigned LabelID) { 776 DEBUG(errs() << " ** LPC" << LabelID << " @ " 777 << (void*)MCE.getCurrentPCValue() << '\n'); 778 JTI->addPCLabelAddr(LabelID, MCE.getCurrentPCValue()); 779} 780 781void ARMCodeEmitter::emitPseudoInstruction(const MachineInstr &MI) { 782 unsigned Opcode = MI.getDesc().Opcode; 783 switch (Opcode) { 784 default: 785 llvm_unreachable("ARMCodeEmitter::emitPseudoInstruction"); 786 case ARM::BX_CALL: 787 case ARM::BMOVPCRX_CALL: 788 case ARM::BXr9_CALL: 789 case ARM::BMOVPCRXr9_CALL: { 790 // First emit mov lr, pc 791 unsigned Binary = 0x01a0e00f; 792 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 793 emitWordLE(Binary); 794 795 // and then emit the branch. 796 emitMiscBranchInstruction(MI); 797 break; 798 } 799 case TargetOpcode::INLINEASM: { 800 // We allow inline assembler nodes with empty bodies - they can 801 // implicitly define registers, which is ok for JIT. 802 if (MI.getOperand(0).getSymbolName()[0]) { 803 report_fatal_error("JIT does not support inline asm!"); 804 } 805 break; 806 } 807 case TargetOpcode::PROLOG_LABEL: 808 case TargetOpcode::EH_LABEL: 809 MCE.emitLabel(MI.getOperand(0).getMCSymbol()); 810 break; 811 case TargetOpcode::IMPLICIT_DEF: 812 case TargetOpcode::KILL: 813 // Do nothing. 814 break; 815 case ARM::CONSTPOOL_ENTRY: 816 emitConstPoolInstruction(MI); 817 break; 818 case ARM::PICADD: { 819 // Remember of the address of the PC label for relocation later. 820 addPCLabel(MI.getOperand(2).getImm()); 821 // PICADD is just an add instruction that implicitly read pc. 822 emitDataProcessingInstruction(MI, 0, ARM::PC); 823 break; 824 } 825 case ARM::PICLDR: 826 case ARM::PICLDRB: 827 case ARM::PICSTR: 828 case ARM::PICSTRB: { 829 // Remember of the address of the PC label for relocation later. 830 addPCLabel(MI.getOperand(2).getImm()); 831 // These are just load / store instructions that implicitly read pc. 832 emitLoadStoreInstruction(MI, 0, ARM::PC); 833 break; 834 } 835 case ARM::PICLDRH: 836 case ARM::PICLDRSH: 837 case ARM::PICLDRSB: 838 case ARM::PICSTRH: { 839 // Remember of the address of the PC label for relocation later. 840 addPCLabel(MI.getOperand(2).getImm()); 841 // These are just load / store instructions that implicitly read pc. 842 emitMiscLoadStoreInstruction(MI, ARM::PC); 843 break; 844 } 845 846 case ARM::MOVi32imm: 847 // Two instructions to materialize a constant. 848 if (Subtarget->hasV6T2Ops()) 849 emitMOVi32immInstruction(MI); 850 else 851 emitMOVi2piecesInstruction(MI); 852 break; 853 854 case ARM::LEApcrelJT: 855 // Materialize jumptable address. 856 emitLEApcrelJTInstruction(MI); 857 break; 858 case ARM::RRX: 859 case ARM::MOVsrl_flag: 860 case ARM::MOVsra_flag: 861 emitPseudoMoveInstruction(MI); 862 break; 863 } 864} 865 866unsigned ARMCodeEmitter::getMachineSoRegOpValue(const MachineInstr &MI, 867 const TargetInstrDesc &TID, 868 const MachineOperand &MO, 869 unsigned OpIdx) { 870 unsigned Binary = getMachineOpValue(MI, MO); 871 872 const MachineOperand &MO1 = MI.getOperand(OpIdx + 1); 873 const MachineOperand &MO2 = MI.getOperand(OpIdx + 2); 874 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm()); 875 876 // Encode the shift opcode. 877 unsigned SBits = 0; 878 unsigned Rs = MO1.getReg(); 879 if (Rs) { 880 // Set shift operand (bit[7:4]). 881 // LSL - 0001 882 // LSR - 0011 883 // ASR - 0101 884 // ROR - 0111 885 // RRX - 0110 and bit[11:8] clear. 886 switch (SOpc) { 887 default: llvm_unreachable("Unknown shift opc!"); 888 case ARM_AM::lsl: SBits = 0x1; break; 889 case ARM_AM::lsr: SBits = 0x3; break; 890 case ARM_AM::asr: SBits = 0x5; break; 891 case ARM_AM::ror: SBits = 0x7; break; 892 case ARM_AM::rrx: SBits = 0x6; break; 893 } 894 } else { 895 // Set shift operand (bit[6:4]). 896 // LSL - 000 897 // LSR - 010 898 // ASR - 100 899 // ROR - 110 900 switch (SOpc) { 901 default: llvm_unreachable("Unknown shift opc!"); 902 case ARM_AM::lsl: SBits = 0x0; break; 903 case ARM_AM::lsr: SBits = 0x2; break; 904 case ARM_AM::asr: SBits = 0x4; break; 905 case ARM_AM::ror: SBits = 0x6; break; 906 } 907 } 908 Binary |= SBits << 4; 909 if (SOpc == ARM_AM::rrx) 910 return Binary; 911 912 // Encode the shift operation Rs or shift_imm (except rrx). 913 if (Rs) { 914 // Encode Rs bit[11:8]. 915 assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0); 916 return Binary | (getARMRegisterNumbering(Rs) << ARMII::RegRsShift); 917 } 918 919 // Encode shift_imm bit[11:7]. 920 return Binary | ARM_AM::getSORegOffset(MO2.getImm()) << 7; 921} 922 923unsigned ARMCodeEmitter::getMachineSoImmOpValue(unsigned SoImm) { 924 int SoImmVal = ARM_AM::getSOImmVal(SoImm); 925 assert(SoImmVal != -1 && "Not a valid so_imm value!"); 926 927 // Encode rotate_imm. 928 unsigned Binary = (ARM_AM::getSOImmValRot((unsigned)SoImmVal) >> 1) 929 << ARMII::SoRotImmShift; 930 931 // Encode immed_8. 932 Binary |= ARM_AM::getSOImmValImm((unsigned)SoImmVal); 933 return Binary; 934} 935 936unsigned ARMCodeEmitter::getAddrModeSBit(const MachineInstr &MI, 937 const TargetInstrDesc &TID) const { 938 for (unsigned i = MI.getNumOperands(), e = TID.getNumOperands(); i != e; --i){ 939 const MachineOperand &MO = MI.getOperand(i-1); 940 if (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR) 941 return 1 << ARMII::S_BitShift; 942 } 943 return 0; 944} 945 946void ARMCodeEmitter::emitDataProcessingInstruction(const MachineInstr &MI, 947 unsigned ImplicitRd, 948 unsigned ImplicitRn) { 949 const TargetInstrDesc &TID = MI.getDesc(); 950 951 // Part of binary is determined by TableGn. 952 unsigned Binary = getBinaryCodeForInstr(MI); 953 954 // Set the conditional execution predicate 955 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 956 957 // Encode S bit if MI modifies CPSR. 958 Binary |= getAddrModeSBit(MI, TID); 959 960 // Encode register def if there is one. 961 unsigned NumDefs = TID.getNumDefs(); 962 unsigned OpIdx = 0; 963 if (NumDefs) 964 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift; 965 else if (ImplicitRd) 966 // Special handling for implicit use (e.g. PC). 967 Binary |= (getARMRegisterNumbering(ImplicitRd) << ARMII::RegRdShift); 968 969 if (TID.Opcode == ARM::MOVi16) { 970 // Get immediate from MI. 971 unsigned Lo16 = getMovi32Value(MI, MI.getOperand(OpIdx), 972 ARM::reloc_arm_movw); 973 // Encode imm which is the same as in emitMOVi32immInstruction(). 974 Binary |= Lo16 & 0xFFF; 975 Binary |= ((Lo16 >> 12) & 0xF) << 16; 976 emitWordLE(Binary); 977 return; 978 } else if(TID.Opcode == ARM::MOVTi16) { 979 unsigned Hi16 = (getMovi32Value(MI, MI.getOperand(OpIdx), 980 ARM::reloc_arm_movt) >> 16); 981 Binary |= Hi16 & 0xFFF; 982 Binary |= ((Hi16 >> 12) & 0xF) << 16; 983 emitWordLE(Binary); 984 return; 985 } else if ((TID.Opcode == ARM::BFC) || (TID.Opcode == ARM::BFI)) { 986 uint32_t v = ~MI.getOperand(2).getImm(); 987 int32_t lsb = CountTrailingZeros_32(v); 988 int32_t msb = (32 - CountLeadingZeros_32(v)) - 1; 989 // Instr{20-16} = msb, Instr{11-7} = lsb 990 Binary |= (msb & 0x1F) << 16; 991 Binary |= (lsb & 0x1F) << 7; 992 emitWordLE(Binary); 993 return; 994 } else if ((TID.Opcode == ARM::UBFX) || (TID.Opcode == ARM::SBFX)) { 995 // Encode Rn in Instr{0-3} 996 Binary |= getMachineOpValue(MI, OpIdx++); 997 998 uint32_t lsb = MI.getOperand(OpIdx++).getImm(); 999 uint32_t widthm1 = MI.getOperand(OpIdx++).getImm() - 1; 1000 1001 // Instr{20-16} = widthm1, Instr{11-7} = lsb 1002 Binary |= (widthm1 & 0x1F) << 16; 1003 Binary |= (lsb & 0x1F) << 7; 1004 emitWordLE(Binary); 1005 return; 1006 } 1007 1008 // If this is a two-address operand, skip it. e.g. MOVCCr operand 1. 1009 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1) 1010 ++OpIdx; 1011 1012 // Encode first non-shifter register operand if there is one. 1013 bool isUnary = TID.TSFlags & ARMII::UnaryDP; 1014 if (!isUnary) { 1015 if (ImplicitRn) 1016 // Special handling for implicit use (e.g. PC). 1017 Binary |= (getARMRegisterNumbering(ImplicitRn) << ARMII::RegRnShift); 1018 else { 1019 Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRnShift; 1020 ++OpIdx; 1021 } 1022 } 1023 1024 // Encode shifter operand. 1025 const MachineOperand &MO = MI.getOperand(OpIdx); 1026 if ((TID.TSFlags & ARMII::FormMask) == ARMII::DPSoRegFrm) { 1027 // Encode SoReg. 1028 emitWordLE(Binary | getMachineSoRegOpValue(MI, TID, MO, OpIdx)); 1029 return; 1030 } 1031 1032 if (MO.isReg()) { 1033 // Encode register Rm. 1034 emitWordLE(Binary | getARMRegisterNumbering(MO.getReg())); 1035 return; 1036 } 1037 1038 // Encode so_imm. 1039 Binary |= getMachineSoImmOpValue((unsigned)MO.getImm()); 1040 1041 emitWordLE(Binary); 1042} 1043 1044void ARMCodeEmitter::emitLoadStoreInstruction(const MachineInstr &MI, 1045 unsigned ImplicitRd, 1046 unsigned ImplicitRn) { 1047 const TargetInstrDesc &TID = MI.getDesc(); 1048 unsigned Form = TID.TSFlags & ARMII::FormMask; 1049 bool IsPrePost = (TID.TSFlags & ARMII::IndexModeMask) != 0; 1050 1051 // Part of binary is determined by TableGn. 1052 unsigned Binary = getBinaryCodeForInstr(MI); 1053 1054 // If this is an LDRi12, STRi12 or LDRcp, nothing more needs be done. 1055 if (MI.getOpcode() == ARM::LDRi12 || MI.getOpcode() == ARM::LDRcp || 1056 MI.getOpcode() == ARM::STRi12) { 1057 emitWordLE(Binary); 1058 return; 1059 } 1060 1061 // Set the conditional execution predicate 1062 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1063 1064 unsigned OpIdx = 0; 1065 1066 // Operand 0 of a pre- and post-indexed store is the address base 1067 // writeback. Skip it. 1068 bool Skipped = false; 1069 if (IsPrePost && Form == ARMII::StFrm) { 1070 ++OpIdx; 1071 Skipped = true; 1072 } 1073 1074 // Set first operand 1075 if (ImplicitRd) 1076 // Special handling for implicit use (e.g. PC). 1077 Binary |= (getARMRegisterNumbering(ImplicitRd) << ARMII::RegRdShift); 1078 else 1079 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift; 1080 1081 // Set second operand 1082 if (ImplicitRn) 1083 // Special handling for implicit use (e.g. PC). 1084 Binary |= (getARMRegisterNumbering(ImplicitRn) << ARMII::RegRnShift); 1085 else 1086 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift; 1087 1088 // If this is a two-address operand, skip it. e.g. LDR_PRE. 1089 if (!Skipped && TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1) 1090 ++OpIdx; 1091 1092 const MachineOperand &MO2 = MI.getOperand(OpIdx); 1093 unsigned AM2Opc = (ImplicitRn == ARM::PC) 1094 ? 0 : MI.getOperand(OpIdx+1).getImm(); 1095 1096 // Set bit U(23) according to sign of immed value (positive or negative). 1097 Binary |= ((ARM_AM::getAM2Op(AM2Opc) == ARM_AM::add ? 1 : 0) << 1098 ARMII::U_BitShift); 1099 if (!MO2.getReg()) { // is immediate 1100 if (ARM_AM::getAM2Offset(AM2Opc)) 1101 // Set the value of offset_12 field 1102 Binary |= ARM_AM::getAM2Offset(AM2Opc); 1103 emitWordLE(Binary); 1104 return; 1105 } 1106 1107 // Set bit I(25), because this is not in immediate encoding. 1108 Binary |= 1 << ARMII::I_BitShift; 1109 assert(TargetRegisterInfo::isPhysicalRegister(MO2.getReg())); 1110 // Set bit[3:0] to the corresponding Rm register 1111 Binary |= getARMRegisterNumbering(MO2.getReg()); 1112 1113 // If this instr is in scaled register offset/index instruction, set 1114 // shift_immed(bit[11:7]) and shift(bit[6:5]) fields. 1115 if (unsigned ShImm = ARM_AM::getAM2Offset(AM2Opc)) { 1116 Binary |= getShiftOp(AM2Opc) << ARMII::ShiftImmShift; // shift 1117 Binary |= ShImm << ARMII::ShiftShift; // shift_immed 1118 } 1119 1120 emitWordLE(Binary); 1121} 1122 1123void ARMCodeEmitter::emitMiscLoadStoreInstruction(const MachineInstr &MI, 1124 unsigned ImplicitRn) { 1125 const TargetInstrDesc &TID = MI.getDesc(); 1126 unsigned Form = TID.TSFlags & ARMII::FormMask; 1127 bool IsPrePost = (TID.TSFlags & ARMII::IndexModeMask) != 0; 1128 1129 // Part of binary is determined by TableGn. 1130 unsigned Binary = getBinaryCodeForInstr(MI); 1131 1132 // Set the conditional execution predicate 1133 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1134 1135 unsigned OpIdx = 0; 1136 1137 // Operand 0 of a pre- and post-indexed store is the address base 1138 // writeback. Skip it. 1139 bool Skipped = false; 1140 if (IsPrePost && Form == ARMII::StMiscFrm) { 1141 ++OpIdx; 1142 Skipped = true; 1143 } 1144 1145 // Set first operand 1146 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift; 1147 1148 // Skip LDRD and STRD's second operand. 1149 if (TID.Opcode == ARM::LDRD || TID.Opcode == ARM::STRD) 1150 ++OpIdx; 1151 1152 // Set second operand 1153 if (ImplicitRn) 1154 // Special handling for implicit use (e.g. PC). 1155 Binary |= (getARMRegisterNumbering(ImplicitRn) << ARMII::RegRnShift); 1156 else 1157 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift; 1158 1159 // If this is a two-address operand, skip it. e.g. LDRH_POST. 1160 if (!Skipped && TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1) 1161 ++OpIdx; 1162 1163 const MachineOperand &MO2 = MI.getOperand(OpIdx); 1164 unsigned AM3Opc = (ImplicitRn == ARM::PC) 1165 ? 0 : MI.getOperand(OpIdx+1).getImm(); 1166 1167 // Set bit U(23) according to sign of immed value (positive or negative) 1168 Binary |= ((ARM_AM::getAM3Op(AM3Opc) == ARM_AM::add ? 1 : 0) << 1169 ARMII::U_BitShift); 1170 1171 // If this instr is in register offset/index encoding, set bit[3:0] 1172 // to the corresponding Rm register. 1173 if (MO2.getReg()) { 1174 Binary |= getARMRegisterNumbering(MO2.getReg()); 1175 emitWordLE(Binary); 1176 return; 1177 } 1178 1179 // This instr is in immediate offset/index encoding, set bit 22 to 1. 1180 Binary |= 1 << ARMII::AM3_I_BitShift; 1181 if (unsigned ImmOffs = ARM_AM::getAM3Offset(AM3Opc)) { 1182 // Set operands 1183 Binary |= (ImmOffs >> 4) << ARMII::ImmHiShift; // immedH 1184 Binary |= (ImmOffs & 0xF); // immedL 1185 } 1186 1187 emitWordLE(Binary); 1188} 1189 1190static unsigned getAddrModeUPBits(unsigned Mode) { 1191 unsigned Binary = 0; 1192 1193 // Set addressing mode by modifying bits U(23) and P(24) 1194 // IA - Increment after - bit U = 1 and bit P = 0 1195 // IB - Increment before - bit U = 1 and bit P = 1 1196 // DA - Decrement after - bit U = 0 and bit P = 0 1197 // DB - Decrement before - bit U = 0 and bit P = 1 1198 switch (Mode) { 1199 default: llvm_unreachable("Unknown addressing sub-mode!"); 1200 case ARM_AM::da: break; 1201 case ARM_AM::db: Binary |= 0x1 << ARMII::P_BitShift; break; 1202 case ARM_AM::ia: Binary |= 0x1 << ARMII::U_BitShift; break; 1203 case ARM_AM::ib: Binary |= 0x3 << ARMII::U_BitShift; break; 1204 } 1205 1206 return Binary; 1207} 1208 1209void ARMCodeEmitter::emitLoadStoreMultipleInstruction(const MachineInstr &MI) { 1210 const TargetInstrDesc &TID = MI.getDesc(); 1211 bool IsUpdating = (TID.TSFlags & ARMII::IndexModeMask) != 0; 1212 1213 // Part of binary is determined by TableGn. 1214 unsigned Binary = getBinaryCodeForInstr(MI); 1215 1216 // Set the conditional execution predicate 1217 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1218 1219 // Skip operand 0 of an instruction with base register update. 1220 unsigned OpIdx = 0; 1221 if (IsUpdating) 1222 ++OpIdx; 1223 1224 // Set base address operand 1225 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift; 1226 1227 // Set addressing mode by modifying bits U(23) and P(24) 1228 ARM_AM::AMSubMode Mode = ARM_AM::getLoadStoreMultipleSubMode(MI.getOpcode()); 1229 Binary |= getAddrModeUPBits(ARM_AM::getAM4SubMode(Mode)); 1230 1231 // Set bit W(21) 1232 if (IsUpdating) 1233 Binary |= 0x1 << ARMII::W_BitShift; 1234 1235 // Set registers 1236 for (unsigned i = OpIdx+2, e = MI.getNumOperands(); i != e; ++i) { 1237 const MachineOperand &MO = MI.getOperand(i); 1238 if (!MO.isReg() || MO.isImplicit()) 1239 break; 1240 unsigned RegNum = getARMRegisterNumbering(MO.getReg()); 1241 assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()) && 1242 RegNum < 16); 1243 Binary |= 0x1 << RegNum; 1244 } 1245 1246 emitWordLE(Binary); 1247} 1248 1249void ARMCodeEmitter::emitMulFrmInstruction(const MachineInstr &MI) { 1250 const TargetInstrDesc &TID = MI.getDesc(); 1251 1252 // Part of binary is determined by TableGn. 1253 unsigned Binary = getBinaryCodeForInstr(MI); 1254 1255 // Set the conditional execution predicate 1256 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1257 1258 // Encode S bit if MI modifies CPSR. 1259 Binary |= getAddrModeSBit(MI, TID); 1260 1261 // 32x32->64bit operations have two destination registers. The number 1262 // of register definitions will tell us if that's what we're dealing with. 1263 unsigned OpIdx = 0; 1264 if (TID.getNumDefs() == 2) 1265 Binary |= getMachineOpValue (MI, OpIdx++) << ARMII::RegRdLoShift; 1266 1267 // Encode Rd 1268 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdHiShift; 1269 1270 // Encode Rm 1271 Binary |= getMachineOpValue(MI, OpIdx++); 1272 1273 // Encode Rs 1274 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRsShift; 1275 1276 // Many multiple instructions (e.g. MLA) have three src operands. Encode 1277 // it as Rn (for multiply, that's in the same offset as RdLo. 1278 if (TID.getNumOperands() > OpIdx && 1279 !TID.OpInfo[OpIdx].isPredicate() && 1280 !TID.OpInfo[OpIdx].isOptionalDef()) 1281 Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRdLoShift; 1282 1283 emitWordLE(Binary); 1284} 1285 1286void ARMCodeEmitter::emitExtendInstruction(const MachineInstr &MI) { 1287 const TargetInstrDesc &TID = MI.getDesc(); 1288 1289 // Part of binary is determined by TableGn. 1290 unsigned Binary = getBinaryCodeForInstr(MI); 1291 1292 // Set the conditional execution predicate 1293 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1294 1295 unsigned OpIdx = 0; 1296 1297 // Encode Rd 1298 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift; 1299 1300 const MachineOperand &MO1 = MI.getOperand(OpIdx++); 1301 const MachineOperand &MO2 = MI.getOperand(OpIdx); 1302 if (MO2.isReg()) { 1303 // Two register operand form. 1304 // Encode Rn. 1305 Binary |= getMachineOpValue(MI, MO1) << ARMII::RegRnShift; 1306 1307 // Encode Rm. 1308 Binary |= getMachineOpValue(MI, MO2); 1309 ++OpIdx; 1310 } else { 1311 Binary |= getMachineOpValue(MI, MO1); 1312 } 1313 1314 // Encode rot imm (0, 8, 16, or 24) if it has a rotate immediate operand. 1315 if (MI.getOperand(OpIdx).isImm() && 1316 !TID.OpInfo[OpIdx].isPredicate() && 1317 !TID.OpInfo[OpIdx].isOptionalDef()) 1318 Binary |= (getMachineOpValue(MI, OpIdx) / 8) << ARMII::ExtRotImmShift; 1319 1320 emitWordLE(Binary); 1321} 1322 1323void ARMCodeEmitter::emitMiscArithInstruction(const MachineInstr &MI) { 1324 const TargetInstrDesc &TID = MI.getDesc(); 1325 1326 // Part of binary is determined by TableGn. 1327 unsigned Binary = getBinaryCodeForInstr(MI); 1328 1329 // Set the conditional execution predicate 1330 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1331 1332 unsigned OpIdx = 0; 1333 1334 // Encode Rd 1335 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift; 1336 1337 const MachineOperand &MO = MI.getOperand(OpIdx++); 1338 if (OpIdx == TID.getNumOperands() || 1339 TID.OpInfo[OpIdx].isPredicate() || 1340 TID.OpInfo[OpIdx].isOptionalDef()) { 1341 // Encode Rm and it's done. 1342 Binary |= getMachineOpValue(MI, MO); 1343 emitWordLE(Binary); 1344 return; 1345 } 1346 1347 // Encode Rn. 1348 Binary |= getMachineOpValue(MI, MO) << ARMII::RegRnShift; 1349 1350 // Encode Rm. 1351 Binary |= getMachineOpValue(MI, OpIdx++); 1352 1353 // Encode shift_imm. 1354 unsigned ShiftAmt = MI.getOperand(OpIdx).getImm(); 1355 if (TID.Opcode == ARM::PKHTB) { 1356 assert(ShiftAmt != 0 && "PKHTB shift_imm is 0!"); 1357 if (ShiftAmt == 32) 1358 ShiftAmt = 0; 1359 } 1360 assert(ShiftAmt < 32 && "shift_imm range is 0 to 31!"); 1361 Binary |= ShiftAmt << ARMII::ShiftShift; 1362 1363 emitWordLE(Binary); 1364} 1365 1366void ARMCodeEmitter::emitSaturateInstruction(const MachineInstr &MI) { 1367 const TargetInstrDesc &TID = MI.getDesc(); 1368 1369 // Part of binary is determined by TableGen. 1370 unsigned Binary = getBinaryCodeForInstr(MI); 1371 1372 // Set the conditional execution predicate 1373 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1374 1375 // Encode Rd 1376 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift; 1377 1378 // Encode saturate bit position. 1379 unsigned Pos = MI.getOperand(1).getImm(); 1380 if (TID.Opcode == ARM::SSAT || TID.Opcode == ARM::SSAT16) 1381 Pos -= 1; 1382 assert((Pos < 16 || (Pos < 32 && 1383 TID.Opcode != ARM::SSAT16 && 1384 TID.Opcode != ARM::USAT16)) && 1385 "saturate bit position out of range"); 1386 Binary |= Pos << 16; 1387 1388 // Encode Rm 1389 Binary |= getMachineOpValue(MI, 2); 1390 1391 // Encode shift_imm. 1392 if (TID.getNumOperands() == 4) { 1393 unsigned ShiftOp = MI.getOperand(3).getImm(); 1394 ARM_AM::ShiftOpc Opc = ARM_AM::getSORegShOp(ShiftOp); 1395 if (Opc == ARM_AM::asr) 1396 Binary |= (1 << 6); 1397 unsigned ShiftAmt = MI.getOperand(3).getImm(); 1398 if (ShiftAmt == 32 && Opc == ARM_AM::asr) 1399 ShiftAmt = 0; 1400 assert(ShiftAmt < 32 && "shift_imm range is 0 to 31!"); 1401 Binary |= ShiftAmt << ARMII::ShiftShift; 1402 } 1403 1404 emitWordLE(Binary); 1405} 1406 1407void ARMCodeEmitter::emitBranchInstruction(const MachineInstr &MI) { 1408 const TargetInstrDesc &TID = MI.getDesc(); 1409 1410 if (TID.Opcode == ARM::TPsoft) { 1411 llvm_unreachable("ARM::TPsoft FIXME"); // FIXME 1412 } 1413 1414 // Part of binary is determined by TableGn. 1415 unsigned Binary = getBinaryCodeForInstr(MI); 1416 1417 // Set the conditional execution predicate 1418 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1419 1420 // Set signed_immed_24 field 1421 Binary |= getMachineOpValue(MI, 0); 1422 1423 emitWordLE(Binary); 1424} 1425 1426void ARMCodeEmitter::emitInlineJumpTable(unsigned JTIndex) { 1427 // Remember the base address of the inline jump table. 1428 uintptr_t JTBase = MCE.getCurrentPCValue(); 1429 JTI->addJumpTableBaseAddr(JTIndex, JTBase); 1430 DEBUG(errs() << " ** Jump Table #" << JTIndex << " @ " << (void*)JTBase 1431 << '\n'); 1432 1433 // Now emit the jump table entries. 1434 const std::vector<MachineBasicBlock*> &MBBs = (*MJTEs)[JTIndex].MBBs; 1435 for (unsigned i = 0, e = MBBs.size(); i != e; ++i) { 1436 if (IsPIC) 1437 // DestBB address - JT base. 1438 emitMachineBasicBlock(MBBs[i], ARM::reloc_arm_pic_jt, JTBase); 1439 else 1440 // Absolute DestBB address. 1441 emitMachineBasicBlock(MBBs[i], ARM::reloc_arm_absolute); 1442 emitWordLE(0); 1443 } 1444} 1445 1446void ARMCodeEmitter::emitMiscBranchInstruction(const MachineInstr &MI) { 1447 const TargetInstrDesc &TID = MI.getDesc(); 1448 1449 // Handle jump tables. 1450 if (TID.Opcode == ARM::BR_JTr || TID.Opcode == ARM::BR_JTadd) { 1451 // First emit a ldr pc, [] instruction. 1452 emitDataProcessingInstruction(MI, ARM::PC); 1453 1454 // Then emit the inline jump table. 1455 unsigned JTIndex = 1456 (TID.Opcode == ARM::BR_JTr) 1457 ? MI.getOperand(1).getIndex() : MI.getOperand(2).getIndex(); 1458 emitInlineJumpTable(JTIndex); 1459 return; 1460 } else if (TID.Opcode == ARM::BR_JTm) { 1461 // First emit a ldr pc, [] instruction. 1462 emitLoadStoreInstruction(MI, ARM::PC); 1463 1464 // Then emit the inline jump table. 1465 emitInlineJumpTable(MI.getOperand(3).getIndex()); 1466 return; 1467 } 1468 1469 // Part of binary is determined by TableGn. 1470 unsigned Binary = getBinaryCodeForInstr(MI); 1471 1472 // Set the conditional execution predicate 1473 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1474 1475 if (TID.Opcode == ARM::BX_RET || TID.Opcode == ARM::MOVPCLR) 1476 // The return register is LR. 1477 Binary |= getARMRegisterNumbering(ARM::LR); 1478 else 1479 // otherwise, set the return register 1480 Binary |= getMachineOpValue(MI, 0); 1481 1482 emitWordLE(Binary); 1483} 1484 1485static unsigned encodeVFPRd(const MachineInstr &MI, unsigned OpIdx) { 1486 unsigned RegD = MI.getOperand(OpIdx).getReg(); 1487 unsigned Binary = 0; 1488 bool isSPVFP = ARM::SPRRegisterClass->contains(RegD); 1489 RegD = getARMRegisterNumbering(RegD); 1490 if (!isSPVFP) 1491 Binary |= RegD << ARMII::RegRdShift; 1492 else { 1493 Binary |= ((RegD & 0x1E) >> 1) << ARMII::RegRdShift; 1494 Binary |= (RegD & 0x01) << ARMII::D_BitShift; 1495 } 1496 return Binary; 1497} 1498 1499static unsigned encodeVFPRn(const MachineInstr &MI, unsigned OpIdx) { 1500 unsigned RegN = MI.getOperand(OpIdx).getReg(); 1501 unsigned Binary = 0; 1502 bool isSPVFP = ARM::SPRRegisterClass->contains(RegN); 1503 RegN = getARMRegisterNumbering(RegN); 1504 if (!isSPVFP) 1505 Binary |= RegN << ARMII::RegRnShift; 1506 else { 1507 Binary |= ((RegN & 0x1E) >> 1) << ARMII::RegRnShift; 1508 Binary |= (RegN & 0x01) << ARMII::N_BitShift; 1509 } 1510 return Binary; 1511} 1512 1513static unsigned encodeVFPRm(const MachineInstr &MI, unsigned OpIdx) { 1514 unsigned RegM = MI.getOperand(OpIdx).getReg(); 1515 unsigned Binary = 0; 1516 bool isSPVFP = ARM::SPRRegisterClass->contains(RegM); 1517 RegM = getARMRegisterNumbering(RegM); 1518 if (!isSPVFP) 1519 Binary |= RegM; 1520 else { 1521 Binary |= ((RegM & 0x1E) >> 1); 1522 Binary |= (RegM & 0x01) << ARMII::M_BitShift; 1523 } 1524 return Binary; 1525} 1526 1527void ARMCodeEmitter::emitVFPArithInstruction(const MachineInstr &MI) { 1528 const TargetInstrDesc &TID = MI.getDesc(); 1529 1530 // Part of binary is determined by TableGn. 1531 unsigned Binary = getBinaryCodeForInstr(MI); 1532 1533 // Set the conditional execution predicate 1534 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1535 1536 unsigned OpIdx = 0; 1537 assert((Binary & ARMII::D_BitShift) == 0 && 1538 (Binary & ARMII::N_BitShift) == 0 && 1539 (Binary & ARMII::M_BitShift) == 0 && "VFP encoding bug!"); 1540 1541 // Encode Dd / Sd. 1542 Binary |= encodeVFPRd(MI, OpIdx++); 1543 1544 // If this is a two-address operand, skip it, e.g. FMACD. 1545 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1) 1546 ++OpIdx; 1547 1548 // Encode Dn / Sn. 1549 if ((TID.TSFlags & ARMII::FormMask) == ARMII::VFPBinaryFrm) 1550 Binary |= encodeVFPRn(MI, OpIdx++); 1551 1552 if (OpIdx == TID.getNumOperands() || 1553 TID.OpInfo[OpIdx].isPredicate() || 1554 TID.OpInfo[OpIdx].isOptionalDef()) { 1555 // FCMPEZD etc. has only one operand. 1556 emitWordLE(Binary); 1557 return; 1558 } 1559 1560 // Encode Dm / Sm. 1561 Binary |= encodeVFPRm(MI, OpIdx); 1562 1563 emitWordLE(Binary); 1564} 1565 1566void ARMCodeEmitter::emitVFPConversionInstruction(const MachineInstr &MI) { 1567 const TargetInstrDesc &TID = MI.getDesc(); 1568 unsigned Form = TID.TSFlags & ARMII::FormMask; 1569 1570 // Part of binary is determined by TableGn. 1571 unsigned Binary = getBinaryCodeForInstr(MI); 1572 1573 // Set the conditional execution predicate 1574 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1575 1576 switch (Form) { 1577 default: break; 1578 case ARMII::VFPConv1Frm: 1579 case ARMII::VFPConv2Frm: 1580 case ARMII::VFPConv3Frm: 1581 // Encode Dd / Sd. 1582 Binary |= encodeVFPRd(MI, 0); 1583 break; 1584 case ARMII::VFPConv4Frm: 1585 // Encode Dn / Sn. 1586 Binary |= encodeVFPRn(MI, 0); 1587 break; 1588 case ARMII::VFPConv5Frm: 1589 // Encode Dm / Sm. 1590 Binary |= encodeVFPRm(MI, 0); 1591 break; 1592 } 1593 1594 switch (Form) { 1595 default: break; 1596 case ARMII::VFPConv1Frm: 1597 // Encode Dm / Sm. 1598 Binary |= encodeVFPRm(MI, 1); 1599 break; 1600 case ARMII::VFPConv2Frm: 1601 case ARMII::VFPConv3Frm: 1602 // Encode Dn / Sn. 1603 Binary |= encodeVFPRn(MI, 1); 1604 break; 1605 case ARMII::VFPConv4Frm: 1606 case ARMII::VFPConv5Frm: 1607 // Encode Dd / Sd. 1608 Binary |= encodeVFPRd(MI, 1); 1609 break; 1610 } 1611 1612 if (Form == ARMII::VFPConv5Frm) 1613 // Encode Dn / Sn. 1614 Binary |= encodeVFPRn(MI, 2); 1615 else if (Form == ARMII::VFPConv3Frm) 1616 // Encode Dm / Sm. 1617 Binary |= encodeVFPRm(MI, 2); 1618 1619 emitWordLE(Binary); 1620} 1621 1622void ARMCodeEmitter::emitVFPLoadStoreInstruction(const MachineInstr &MI) { 1623 // Part of binary is determined by TableGn. 1624 unsigned Binary = getBinaryCodeForInstr(MI); 1625 1626 // Set the conditional execution predicate 1627 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1628 1629 unsigned OpIdx = 0; 1630 1631 // Encode Dd / Sd. 1632 Binary |= encodeVFPRd(MI, OpIdx++); 1633 1634 // Encode address base. 1635 const MachineOperand &Base = MI.getOperand(OpIdx++); 1636 Binary |= getMachineOpValue(MI, Base) << ARMII::RegRnShift; 1637 1638 // If there is a non-zero immediate offset, encode it. 1639 if (Base.isReg()) { 1640 const MachineOperand &Offset = MI.getOperand(OpIdx); 1641 if (unsigned ImmOffs = ARM_AM::getAM5Offset(Offset.getImm())) { 1642 if (ARM_AM::getAM5Op(Offset.getImm()) == ARM_AM::add) 1643 Binary |= 1 << ARMII::U_BitShift; 1644 Binary |= ImmOffs; 1645 emitWordLE(Binary); 1646 return; 1647 } 1648 } 1649 1650 // If immediate offset is omitted, default to +0. 1651 Binary |= 1 << ARMII::U_BitShift; 1652 1653 emitWordLE(Binary); 1654} 1655 1656void 1657ARMCodeEmitter::emitVFPLoadStoreMultipleInstruction(const MachineInstr &MI) { 1658 const TargetInstrDesc &TID = MI.getDesc(); 1659 bool IsUpdating = (TID.TSFlags & ARMII::IndexModeMask) != 0; 1660 1661 // Part of binary is determined by TableGn. 1662 unsigned Binary = getBinaryCodeForInstr(MI); 1663 1664 // Set the conditional execution predicate 1665 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1666 1667 // Skip operand 0 of an instruction with base register update. 1668 unsigned OpIdx = 0; 1669 if (IsUpdating) 1670 ++OpIdx; 1671 1672 // Set base address operand 1673 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift; 1674 1675 // Set addressing mode by modifying bits U(23) and P(24) 1676 ARM_AM::AMSubMode Mode = ARM_AM::getLoadStoreMultipleSubMode(MI.getOpcode()); 1677 Binary |= getAddrModeUPBits(ARM_AM::getAM4SubMode(Mode)); 1678 1679 // Set bit W(21) 1680 if (IsUpdating) 1681 Binary |= 0x1 << ARMII::W_BitShift; 1682 1683 // First register is encoded in Dd. 1684 Binary |= encodeVFPRd(MI, OpIdx+2); 1685 1686 // Count the number of registers. 1687 unsigned NumRegs = 1; 1688 for (unsigned i = OpIdx+3, e = MI.getNumOperands(); i != e; ++i) { 1689 const MachineOperand &MO = MI.getOperand(i); 1690 if (!MO.isReg() || MO.isImplicit()) 1691 break; 1692 ++NumRegs; 1693 } 1694 // Bit 8 will be set if <list> is consecutive 64-bit registers (e.g., D0) 1695 // Otherwise, it will be 0, in the case of 32-bit registers. 1696 if(Binary & 0x100) 1697 Binary |= NumRegs * 2; 1698 else 1699 Binary |= NumRegs; 1700 1701 emitWordLE(Binary); 1702} 1703 1704static unsigned encodeNEONRd(const MachineInstr &MI, unsigned OpIdx) { 1705 unsigned RegD = MI.getOperand(OpIdx).getReg(); 1706 unsigned Binary = 0; 1707 RegD = getARMRegisterNumbering(RegD); 1708 Binary |= (RegD & 0xf) << ARMII::RegRdShift; 1709 Binary |= ((RegD >> 4) & 1) << ARMII::D_BitShift; 1710 return Binary; 1711} 1712 1713static unsigned encodeNEONRn(const MachineInstr &MI, unsigned OpIdx) { 1714 unsigned RegN = MI.getOperand(OpIdx).getReg(); 1715 unsigned Binary = 0; 1716 RegN = getARMRegisterNumbering(RegN); 1717 Binary |= (RegN & 0xf) << ARMII::RegRnShift; 1718 Binary |= ((RegN >> 4) & 1) << ARMII::N_BitShift; 1719 return Binary; 1720} 1721 1722static unsigned encodeNEONRm(const MachineInstr &MI, unsigned OpIdx) { 1723 unsigned RegM = MI.getOperand(OpIdx).getReg(); 1724 unsigned Binary = 0; 1725 RegM = getARMRegisterNumbering(RegM); 1726 Binary |= (RegM & 0xf); 1727 Binary |= ((RegM >> 4) & 1) << ARMII::M_BitShift; 1728 return Binary; 1729} 1730 1731/// convertNEONDataProcToThumb - Convert the ARM mode encoding for a NEON 1732/// data-processing instruction to the corresponding Thumb encoding. 1733static unsigned convertNEONDataProcToThumb(unsigned Binary) { 1734 assert((Binary & 0xfe000000) == 0xf2000000 && 1735 "not an ARM NEON data-processing instruction"); 1736 unsigned UBit = (Binary >> 24) & 1; 1737 return 0xef000000 | (UBit << 28) | (Binary & 0xffffff); 1738} 1739 1740void ARMCodeEmitter::emitNEONLaneInstruction(const MachineInstr &MI) { 1741 unsigned Binary = getBinaryCodeForInstr(MI); 1742 1743 unsigned RegTOpIdx, RegNOpIdx, LnOpIdx; 1744 const TargetInstrDesc &TID = MI.getDesc(); 1745 if ((TID.TSFlags & ARMII::FormMask) == ARMII::NGetLnFrm) { 1746 RegTOpIdx = 0; 1747 RegNOpIdx = 1; 1748 LnOpIdx = 2; 1749 } else { // ARMII::NSetLnFrm 1750 RegTOpIdx = 2; 1751 RegNOpIdx = 0; 1752 LnOpIdx = 3; 1753 } 1754 1755 // Set the conditional execution predicate 1756 Binary |= (IsThumb ? ARMCC::AL : II->getPredicate(&MI)) << ARMII::CondShift; 1757 1758 unsigned RegT = MI.getOperand(RegTOpIdx).getReg(); 1759 RegT = getARMRegisterNumbering(RegT); 1760 Binary |= (RegT << ARMII::RegRdShift); 1761 Binary |= encodeNEONRn(MI, RegNOpIdx); 1762 1763 unsigned LaneShift; 1764 if ((Binary & (1 << 22)) != 0) 1765 LaneShift = 0; // 8-bit elements 1766 else if ((Binary & (1 << 5)) != 0) 1767 LaneShift = 1; // 16-bit elements 1768 else 1769 LaneShift = 2; // 32-bit elements 1770 1771 unsigned Lane = MI.getOperand(LnOpIdx).getImm() << LaneShift; 1772 unsigned Opc1 = Lane >> 2; 1773 unsigned Opc2 = Lane & 3; 1774 assert((Opc1 & 3) == 0 && "out-of-range lane number operand"); 1775 Binary |= (Opc1 << 21); 1776 Binary |= (Opc2 << 5); 1777 1778 emitWordLE(Binary); 1779} 1780 1781void ARMCodeEmitter::emitNEONDupInstruction(const MachineInstr &MI) { 1782 unsigned Binary = getBinaryCodeForInstr(MI); 1783 1784 // Set the conditional execution predicate 1785 Binary |= (IsThumb ? ARMCC::AL : II->getPredicate(&MI)) << ARMII::CondShift; 1786 1787 unsigned RegT = MI.getOperand(1).getReg(); 1788 RegT = getARMRegisterNumbering(RegT); 1789 Binary |= (RegT << ARMII::RegRdShift); 1790 Binary |= encodeNEONRn(MI, 0); 1791 emitWordLE(Binary); 1792} 1793 1794void ARMCodeEmitter::emitNEON1RegModImmInstruction(const MachineInstr &MI) { 1795 unsigned Binary = getBinaryCodeForInstr(MI); 1796 // Destination register is encoded in Dd. 1797 Binary |= encodeNEONRd(MI, 0); 1798 // Immediate fields: Op, Cmode, I, Imm3, Imm4 1799 unsigned Imm = MI.getOperand(1).getImm(); 1800 unsigned Op = (Imm >> 12) & 1; 1801 unsigned Cmode = (Imm >> 8) & 0xf; 1802 unsigned I = (Imm >> 7) & 1; 1803 unsigned Imm3 = (Imm >> 4) & 0x7; 1804 unsigned Imm4 = Imm & 0xf; 1805 Binary |= (I << 24) | (Imm3 << 16) | (Cmode << 8) | (Op << 5) | Imm4; 1806 if (IsThumb) 1807 Binary = convertNEONDataProcToThumb(Binary); 1808 emitWordLE(Binary); 1809} 1810 1811void ARMCodeEmitter::emitNEON2RegInstruction(const MachineInstr &MI) { 1812 const TargetInstrDesc &TID = MI.getDesc(); 1813 unsigned Binary = getBinaryCodeForInstr(MI); 1814 // Destination register is encoded in Dd; source register in Dm. 1815 unsigned OpIdx = 0; 1816 Binary |= encodeNEONRd(MI, OpIdx++); 1817 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1) 1818 ++OpIdx; 1819 Binary |= encodeNEONRm(MI, OpIdx); 1820 if (IsThumb) 1821 Binary = convertNEONDataProcToThumb(Binary); 1822 // FIXME: This does not handle VDUPfdf or VDUPfqf. 1823 emitWordLE(Binary); 1824} 1825 1826void ARMCodeEmitter::emitNEON3RegInstruction(const MachineInstr &MI) { 1827 const TargetInstrDesc &TID = MI.getDesc(); 1828 unsigned Binary = getBinaryCodeForInstr(MI); 1829 // Destination register is encoded in Dd; source registers in Dn and Dm. 1830 unsigned OpIdx = 0; 1831 Binary |= encodeNEONRd(MI, OpIdx++); 1832 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1) 1833 ++OpIdx; 1834 Binary |= encodeNEONRn(MI, OpIdx++); 1835 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1) 1836 ++OpIdx; 1837 Binary |= encodeNEONRm(MI, OpIdx); 1838 if (IsThumb) 1839 Binary = convertNEONDataProcToThumb(Binary); 1840 // FIXME: This does not handle VMOVDneon or VMOVQ. 1841 emitWordLE(Binary); 1842} 1843 1844#include "ARMGenCodeEmitter.inc" 1845