ARMCodeEmitter.cpp revision 0f282439be688babbbf6d54151ddf9a7ebbf3637 
1//===-- ARM/ARMCodeEmitter.cpp - Convert ARM code to machine code ---------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the pass that transforms the ARM machine instructions into
11// relocatable machine code.
12//
13//===----------------------------------------------------------------------===//
14
15#define DEBUG_TYPE "jit"
16#include "ARM.h"
17#include "ARMAddressingModes.h"
18#include "ARMConstantPoolValue.h"
19#include "ARMInstrInfo.h"
20#include "ARMRelocations.h"
21#include "ARMSubtarget.h"
22#include "ARMTargetMachine.h"
23#include "llvm/Constants.h"
24#include "llvm/DerivedTypes.h"
25#include "llvm/Function.h"
26#include "llvm/PassManager.h"
27#include "llvm/CodeGen/MachineCodeEmitter.h"
28#include "llvm/CodeGen/MachineConstantPool.h"
29#include "llvm/CodeGen/MachineFunctionPass.h"
30#include "llvm/CodeGen/MachineInstr.h"
31#include "llvm/CodeGen/Passes.h"
32#include "llvm/ADT/Statistic.h"
33#include "llvm/Support/Compiler.h"
34#include "llvm/Support/Debug.h"
35using namespace llvm;
36
37STATISTIC(NumEmitted, "Number of machine instructions emitted");
38
39namespace {
40  class VISIBILITY_HIDDEN ARMCodeEmitter : public MachineFunctionPass {
41    ARMJITInfo                *JTI;
42    const ARMInstrInfo        *II;
43    const TargetData          *TD;
44    TargetMachine             &TM;
45    MachineCodeEmitter        &MCE;
46    const MachineConstantPool *MCP;
47  public:
48    static char ID;
49    explicit ARMCodeEmitter(TargetMachine &tm, MachineCodeEmitter &mce)
50      : MachineFunctionPass(&ID), JTI(0), II(0), TD(0), TM(tm),
51      MCE(mce), MCP(0) {}
52    ARMCodeEmitter(TargetMachine &tm, MachineCodeEmitter &mce,
53            const ARMInstrInfo &ii, const TargetData &td)
54      : MachineFunctionPass(&ID), JTI(0), II(&ii), TD(&td), TM(tm),
55      MCE(mce), MCP(0) {}
56
57    bool runOnMachineFunction(MachineFunction &MF);
58
59    virtual const char *getPassName() const {
60      return "ARM Machine Code Emitter";
61    }
62
63    void emitInstruction(const MachineInstr &MI);
64
65  private:
66
67    void emitConstPoolInstruction(const MachineInstr &MI);
68
69    void emitPseudoInstruction(const MachineInstr &MI);
70
71    unsigned getAddrModeNoneInstrBinary(const MachineInstr &MI,
72                                        const TargetInstrDesc &TID,
73                                        unsigned Binary);
74
75    unsigned getMachineSoRegOpValue(const MachineInstr &MI,
76                                    const TargetInstrDesc &TID,
77                                    unsigned OpIdx);
78
79    unsigned getAddrMode1SBit(const MachineInstr &MI,
80                              const TargetInstrDesc &TID) const;
81
82    unsigned getAddrMode1InstrBinary(const MachineInstr &MI,
83                                     const TargetInstrDesc &TID,
84                                     unsigned Binary);
85    unsigned getAddrMode2InstrBinary(const MachineInstr &MI,
86                                     const TargetInstrDesc &TID,
87                                     unsigned Binary);
88    unsigned getAddrMode3InstrBinary(const MachineInstr &MI,
89                                     const TargetInstrDesc &TID,
90                                     unsigned Binary);
91    unsigned getAddrMode4InstrBinary(const MachineInstr &MI,
92                                     const TargetInstrDesc &TID,
93                                     unsigned Binary);
94
95    /// getInstrBinary - Return binary encoding for the specified
96    /// machine instruction.
97    unsigned getInstrBinary(const MachineInstr &MI);
98
99    /// getBinaryCodeForInstr - This function, generated by the
100    /// CodeEmitterGenerator using TableGen, produces the binary encoding for
101    /// machine instructions.
102    ///
103    unsigned getBinaryCodeForInstr(const MachineInstr &MI);
104
105    /// getMachineOpValue - Return binary encoding of operand. If the machine
106    /// operand requires relocation, record the relocation and return zero.
107    unsigned getMachineOpValue(const MachineInstr &MI, unsigned OpIdx) {
108      return getMachineOpValue(MI, MI.getOperand(OpIdx));
109    }
110    unsigned getMachineOpValue(const MachineInstr &MI,
111                               const MachineOperand &MO);
112
113    /// getBaseOpcodeFor - Return the opcode value.
114    ///
115    unsigned getBaseOpcodeFor(const TargetInstrDesc &TID) const {
116      return (TID.TSFlags & ARMII::OpcodeMask) >> ARMII::OpcodeShift;
117    }
118
119    /// getShiftOp - Return the shift opcode (bit[6:5]) of the machine operand.
120    ///
121    unsigned getShiftOp(const MachineOperand &MO) const ;
122
123    /// Routines that handle operands which add machine relocations which are
124    /// fixed up by the JIT fixup stage.
125    void emitGlobalAddress(GlobalValue *GV, unsigned Reloc,
126                           bool NeedStub);
127    void emitExternalSymbolAddress(const char *ES, unsigned Reloc);
128    void emitConstPoolAddress(unsigned CPI, unsigned Reloc,
129                              int Disp = 0, unsigned PCAdj = 0 );
130    void emitJumpTableAddress(unsigned JTIndex, unsigned Reloc,
131                              unsigned PCAdj = 0);
132    void emitGlobalConstant(const Constant *CV);
133    void emitMachineBasicBlock(MachineBasicBlock *BB);
134  };
135  char ARMCodeEmitter::ID = 0;
136}
137
138/// createARMCodeEmitterPass - Return a pass that emits the collected ARM code
139/// to the specified MCE object.
140FunctionPass *llvm::createARMCodeEmitterPass(ARMTargetMachine &TM,
141                                             MachineCodeEmitter &MCE) {
142  return new ARMCodeEmitter(TM, MCE);
143}
144
145bool ARMCodeEmitter::runOnMachineFunction(MachineFunction &MF) {
146  assert((MF.getTarget().getRelocationModel() != Reloc::Default ||
147          MF.getTarget().getRelocationModel() != Reloc::Static) &&
148         "JIT relocation model must be set to static or default!");
149  II = ((ARMTargetMachine&)MF.getTarget()).getInstrInfo();
150  TD = ((ARMTargetMachine&)MF.getTarget()).getTargetData();
151  JTI = ((ARMTargetMachine&)MF.getTarget()).getJITInfo();
152  MCP = MF.getConstantPool();
153
154  do {
155    DOUT << "JITTing function '" << MF.getFunction()->getName() << "'\n";
156    MCE.startFunction(MF);
157    for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();
158         MBB != E; ++MBB) {
159      MCE.StartMachineBasicBlock(MBB);
160      for (MachineBasicBlock::const_iterator I = MBB->begin(), E = MBB->end();
161           I != E; ++I)
162        emitInstruction(*I);
163    }
164  } while (MCE.finishFunction(MF));
165
166  return false;
167}
168
169/// getShiftOp - Return the shift opcode (bit[6:5]) of the machine operand.
170///
171unsigned ARMCodeEmitter::getShiftOp(const MachineOperand &MO) const {
172  switch (ARM_AM::getAM2ShiftOpc(MO.getImm())) {
173  default: assert(0 && "Unknown shift opc!");
174  case ARM_AM::asr: return 2;
175  case ARM_AM::lsl: return 0;
176  case ARM_AM::lsr: return 1;
177  case ARM_AM::ror:
178  case ARM_AM::rrx: return 3;
179  }
180  return 0;
181}
182
183/// getMachineOpValue - Return binary encoding of operand. If the machine
184/// operand requires relocation, record the relocation and return zero.
185unsigned ARMCodeEmitter::getMachineOpValue(const MachineInstr &MI,
186                                           const MachineOperand &MO) {
187  if (MO.isReg())
188    return ARMRegisterInfo::getRegisterNumbering(MO.getReg());
189  else if (MO.isImm())
190    return static_cast<unsigned>(MO.getImm());
191  else if (MO.isGlobal())
192    emitGlobalAddress(MO.getGlobal(), ARM::reloc_arm_branch, true);
193  else if (MO.isSymbol())
194    emitExternalSymbolAddress(MO.getSymbolName(), ARM::reloc_arm_relative);
195  else if (MO.isCPI())
196    emitConstPoolAddress(MO.getIndex(), ARM::reloc_arm_cp_entry);
197  else if (MO.isJTI())
198    emitJumpTableAddress(MO.getIndex(), ARM::reloc_arm_relative);
199  else if (MO.isMBB())
200    emitMachineBasicBlock(MO.getMBB());
201  else {
202    cerr << "ERROR: Unknown type of MachineOperand: " << MO << "\n";
203    abort();
204  }
205  return 0;
206}
207
208/// emitGlobalAddress - Emit the specified address to the code stream.
209///
210void ARMCodeEmitter::emitGlobalAddress(GlobalValue *GV,
211                                       unsigned Reloc, bool NeedStub) {
212  MCE.addRelocation(MachineRelocation::getGV(MCE.getCurrentPCOffset(),
213                                             Reloc, GV, 0, NeedStub));
214}
215
216/// emitExternalSymbolAddress - Arrange for the address of an external symbol to
217/// be emitted to the current location in the function, and allow it to be PC
218/// relative.
219void ARMCodeEmitter::emitExternalSymbolAddress(const char *ES, unsigned Reloc) {
220  MCE.addRelocation(MachineRelocation::getExtSym(MCE.getCurrentPCOffset(),
221                                                 Reloc, ES));
222}
223
224/// emitConstPoolAddress - Arrange for the address of an constant pool
225/// to be emitted to the current location in the function, and allow it to be PC
226/// relative.
227void ARMCodeEmitter::emitConstPoolAddress(unsigned CPI, unsigned Reloc,
228                                          int Disp /* = 0 */,
229                                          unsigned PCAdj /* = 0 */) {
230  // Tell JIT emitter we'll resolve the address.
231  MCE.addRelocation(MachineRelocation::getConstPool(MCE.getCurrentPCOffset(),
232                                                    Reloc, CPI, PCAdj, true));
233}
234
235/// emitJumpTableAddress - Arrange for the address of a jump table to
236/// be emitted to the current location in the function, and allow it to be PC
237/// relative.
238void ARMCodeEmitter::emitJumpTableAddress(unsigned JTIndex, unsigned Reloc,
239                                          unsigned PCAdj /* = 0 */) {
240  MCE.addRelocation(MachineRelocation::getJumpTable(MCE.getCurrentPCOffset(),
241                                                    Reloc, JTIndex, PCAdj));
242}
243
244/// emitMachineBasicBlock - Emit the specified address basic block.
245void ARMCodeEmitter::emitMachineBasicBlock(MachineBasicBlock *BB) {
246  MCE.addRelocation(MachineRelocation::getBB(MCE.getCurrentPCOffset(),
247                                             ARM::reloc_arm_branch, BB));
248}
249
250void ARMCodeEmitter::emitInstruction(const MachineInstr &MI) {
251  DOUT << "JIT: " << "0x" << MCE.getCurrentPCValue() << ":\t" << MI;
252
253  NumEmitted++;  // Keep track of the # of mi's emitted
254  if ((MI.getDesc().TSFlags & ARMII::FormMask) == ARMII::Pseudo)
255    emitPseudoInstruction(MI);
256  else
257    MCE.emitWordLE(getInstrBinary(MI));
258}
259
260unsigned ARMCodeEmitter::getAddrModeNoneInstrBinary(const MachineInstr &MI,
261                                                    const TargetInstrDesc &TID,
262                                                    unsigned Binary) {
263  // Set the conditional execution predicate
264  Binary |= II->getPredicate(&MI) << 28;
265
266  switch (TID.TSFlags & ARMII::FormMask) {
267  default:
268    assert(0 && "Unknown instruction subtype!");
269    break;
270  case ARMII::Branch: {
271    // Set signed_immed_24 field
272    Binary |= getMachineOpValue(MI, 0);
273
274    // if it is a conditional branch, set cond field
275    if (TID.Opcode == ARM::Bcc) {
276      Binary &= 0x0FFFFFFF;                      // clear conditional field
277      Binary |= getMachineOpValue(MI, 1) << 28;  // set conditional field
278    }
279    break;
280  }
281  case ARMII::BranchMisc: {
282    if (TID.Opcode == ARM::BX)
283      abort(); // FIXME
284    if (TID.Opcode == ARM::BX_RET)
285      Binary |= 0xe; // the return register is LR
286    else
287      // otherwise, set the return register
288      Binary |= getMachineOpValue(MI, 0);
289    break;
290  }
291  }
292
293  return Binary;
294}
295
296unsigned ARMCodeEmitter::getMachineSoRegOpValue(const MachineInstr &MI,
297                                                const TargetInstrDesc &TID,
298                                                unsigned OpIdx) {
299  // Set last operand (register Rm)
300  unsigned Binary = getMachineOpValue(MI, OpIdx);
301
302  const MachineOperand &MO1 = MI.getOperand(OpIdx + 1);
303  const MachineOperand &MO2 = MI.getOperand(OpIdx + 2);
304  ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm());
305
306  // Encode the shift opcode.
307  unsigned SBits = 0;
308  unsigned Rs = MO1.getReg();
309  if (Rs) {
310    // Set shift operand (bit[7:4]).
311    // LSL - 0001
312    // LSR - 0011
313    // ASR - 0101
314    // ROR - 0111
315    // RRX - 0110 and bit[11:8] clear.
316    switch (SOpc) {
317    default: assert(0 && "Unknown shift opc!");
318    case ARM_AM::lsl: SBits = 0x1; break;
319    case ARM_AM::lsr: SBits = 0x3; break;
320    case ARM_AM::asr: SBits = 0x5; break;
321    case ARM_AM::ror: SBits = 0x7; break;
322    case ARM_AM::rrx: SBits = 0x6; break;
323    }
324  } else {
325    // Set shift operand (bit[6:4]).
326    // LSL - 000
327    // LSR - 010
328    // ASR - 100
329    // ROR - 110
330    switch (SOpc) {
331    default: assert(0 && "Unknown shift opc!");
332    case ARM_AM::lsl: SBits = 0x0; break;
333    case ARM_AM::lsr: SBits = 0x2; break;
334    case ARM_AM::asr: SBits = 0x4; break;
335    case ARM_AM::ror: SBits = 0x6; break;
336    }
337  }
338  Binary |= SBits << 4;
339  if (SOpc == ARM_AM::rrx)
340    return Binary;
341
342  // Encode the shift operation Rs or shift_imm (except rrx).
343  if (Rs) {
344    // Encode Rs bit[11:8].
345    assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0);
346    return Binary |
347      (ARMRegisterInfo::getRegisterNumbering(Rs) << ARMII::RegRsShift);
348  }
349
350  // Encode shift_imm bit[11:7].
351  return Binary | ARM_AM::getSORegOffset(MO2.getImm()) << 7;
352}
353
354unsigned ARMCodeEmitter::getAddrMode1SBit(const MachineInstr &MI,
355                                          const TargetInstrDesc &TID) const {
356  for (unsigned i = MI.getNumOperands(), e = TID.getNumOperands(); i != e; --i){
357    const MachineOperand &MO = MI.getOperand(i-1);
358    if (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR)
359      return 1 << ARMII::S_BitShift;
360  }
361  return 0;
362}
363
364void ARMCodeEmitter::emitConstPoolInstruction(const MachineInstr &MI) {
365  unsigned CPI = MI.getOperand(0).getImm();
366  unsigned CPIndex = MI.getOperand(1).getIndex();
367  const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPIndex];
368
369  // Remember the CONSTPOOL_ENTRY address for later relocation.
370  JTI->addConstantPoolEntryAddr(CPI, MCE.getCurrentPCValue());
371
372  // Emit constpool island entry. In most cases, the actual values will be
373  // resolved and relocated after code emission.
374  if (MCPE.isMachineConstantPoolEntry()) {
375    ARMConstantPoolValue *ACPV =
376      static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal);
377
378    DOUT << "\t** ARM constant pool #" << CPI << ", ' @ "
379         << (void*)MCE.getCurrentPCValue() << *ACPV << '\n';
380
381    GlobalValue *GV = ACPV->getGV();
382    if (GV) {
383      assert(!ACPV->isStub() && "Don't know how to deal this yet!");
384      emitGlobalAddress(GV, ARM::reloc_arm_absolute, false);
385    } else  {
386      assert(!ACPV->isNonLazyPointer() && "Don't know how to deal this yet!");
387      emitExternalSymbolAddress(ACPV->getSymbol(), ARM::reloc_arm_absolute);
388    }
389    MCE.emitWordLE(0);
390  } else {
391    Constant *CV = MCPE.Val.ConstVal;
392
393    DOUT << "\t** Constant pool #" << CPI << ", ' @ "
394         << (void*)MCE.getCurrentPCValue() << *CV << '\n';
395
396    if (GlobalValue *GV = dyn_cast<GlobalValue>(CV)) {
397      emitGlobalAddress(GV, ARM::reloc_arm_absolute, false);
398      MCE.emitWordLE(0);
399    } else {
400      abort(); // FIXME: Is this right?
401      const ConstantInt *CI = dyn_cast<ConstantInt>(CV);
402      uint32_t Val = *(uint32_t*)CI->getValue().getRawData();
403      MCE.emitWordLE(Val);
404    }
405  }
406}
407
408void ARMCodeEmitter::emitPseudoInstruction(const MachineInstr &MI) {
409  unsigned Opcode = MI.getDesc().Opcode;
410  switch (Opcode) {
411  default:
412    abort(); // FIXME:
413  case ARM::CONSTPOOL_ENTRY: {
414    emitConstPoolInstruction(MI);
415    break;
416  }
417  }
418}
419
420unsigned ARMCodeEmitter::getAddrMode1InstrBinary(const MachineInstr &MI,
421                                                 const TargetInstrDesc &TID,
422                                                 unsigned Binary) {
423  // Set the conditional execution predicate
424  Binary |= II->getPredicate(&MI) << 28;
425
426  // Encode S bit if MI modifies CPSR.
427  Binary |= getAddrMode1SBit(MI, TID);
428
429  // Encode register def if there is one.
430  unsigned NumDefs = TID.getNumDefs();
431  unsigned OpIdx = 0;
432  if (NumDefs) {
433    Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRdShift;
434    ++OpIdx;
435  }
436
437  // Encode first non-shifter register operand if there is one.
438  unsigned Format = TID.TSFlags & ARMII::FormMask;
439  bool hasRnOperand= !(Format == ARMII::DPRdMisc  ||
440                       Format == ARMII::DPRdIm    ||
441                       Format == ARMII::DPRdReg   ||
442                       Format == ARMII::DPRdSoReg);
443  if (hasRnOperand) {
444    Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRnShift;
445    ++OpIdx;
446  }
447
448  // Encode shifter operand.
449  bool HasSoReg = (Format == ARMII::DPRdSoReg ||
450                   Format == ARMII::DPRnSoReg ||
451                   Format == ARMII::DPRSoReg  ||
452                   Format == ARMII::DPRSoRegS);
453  if (HasSoReg)
454    // Encode SoReg.
455    return Binary | getMachineSoRegOpValue(MI, TID, OpIdx);
456
457  const MachineOperand &MO = MI.getOperand(OpIdx);
458  if (MO.isReg())
459    // Encode register Rm.
460    return Binary | getMachineOpValue(MI, NumDefs);
461
462  // Encode so_imm.
463  // Set bit I(25) to identify this is the immediate form of <shifter_op>
464  Binary |= 1 << ARMII::I_BitShift;
465  unsigned SoImm = MO.getImm();
466  // Encode rotate_imm.
467  Binary |= ARM_AM::getSOImmValRot(SoImm) << ARMII::RotImmShift;
468  // Encode immed_8.
469  Binary |= ARM_AM::getSOImmVal(SoImm);
470  return Binary;
471}
472
473unsigned ARMCodeEmitter::getAddrMode2InstrBinary(const MachineInstr &MI,
474                                                 const TargetInstrDesc &TID,
475                                                 unsigned Binary) {
476  // Set the conditional execution predicate
477  Binary |= II->getPredicate(&MI) << 28;
478
479  // Set first operand
480  Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
481
482  // Set second operand
483  Binary |= getMachineOpValue(MI, 1) << ARMII::RegRnShift;
484
485  const MachineOperand &MO2 = MI.getOperand(2);
486  const MachineOperand &MO3 = MI.getOperand(3);
487
488  // Set bit U(23) according to sign of immed value (positive or negative).
489  Binary |= ((ARM_AM::getAM2Op(MO3.getImm()) == ARM_AM::add ? 1 : 0) <<
490             ARMII::U_BitShift);
491  if (!MO2.getReg()) { // is immediate
492    if (ARM_AM::getAM2Offset(MO3.getImm()))
493      // Set the value of offset_12 field
494      Binary |= ARM_AM::getAM2Offset(MO3.getImm());
495    return Binary;
496  }
497
498  // Set bit I(25), because this is not in immediate enconding.
499  Binary |= 1 << ARMII::I_BitShift;
500  assert(TargetRegisterInfo::isPhysicalRegister(MO2.getReg()));
501  // Set bit[3:0] to the corresponding Rm register
502  Binary |= ARMRegisterInfo::getRegisterNumbering(MO2.getReg());
503
504  // if this instr is in scaled register offset/index instruction, set
505  // shift_immed(bit[11:7]) and shift(bit[6:5]) fields.
506  if (unsigned ShImm = ARM_AM::getAM2Offset(MO3.getImm())) {
507    Binary |= getShiftOp(MO3) << 5;  // shift
508    Binary |= ShImm           << 7;  // shift_immed
509  }
510
511  return Binary;
512}
513
514unsigned ARMCodeEmitter::getAddrMode3InstrBinary(const MachineInstr &MI,
515                                                 const TargetInstrDesc &TID,
516                                                 unsigned Binary) {
517  // Set the conditional execution predicate
518  Binary |= II->getPredicate(&MI) << 28;
519
520  // Set first operand
521  Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
522
523  // Set second operand
524  Binary |= getMachineOpValue(MI, 1) << ARMII::RegRnShift;
525
526  const MachineOperand &MO2 = MI.getOperand(2);
527  const MachineOperand &MO3 = MI.getOperand(3);
528
529  // Set bit U(23) according to sign of immed value (positive or negative)
530  Binary |= ((ARM_AM::getAM2Op(MO3.getImm()) == ARM_AM::add ? 1 : 0) <<
531             ARMII::U_BitShift);
532
533  // If this instr is in register offset/index encoding, set bit[3:0]
534  // to the corresponding Rm register.
535  if (MO2.getReg()) {
536    Binary |= ARMRegisterInfo::getRegisterNumbering(MO2.getReg());
537    return Binary;
538  }
539
540  // if this instr is in immediate offset/index encoding, set bit 22 to 1
541  if (unsigned ImmOffs = ARM_AM::getAM3Offset(MO3.getImm())) {
542    Binary |= 1 << 22;
543    // Set operands
544    Binary |= (ImmOffs >> 4) << 8;  // immedH
545    Binary |= (ImmOffs & ~0xF);     // immedL
546  }
547
548  return Binary;
549}
550
551unsigned ARMCodeEmitter::getAddrMode4InstrBinary(const MachineInstr &MI,
552                                                 const TargetInstrDesc &TID,
553                                                 unsigned Binary) {
554  // Set the conditional execution predicate
555  Binary |= II->getPredicate(&MI) << 28;
556
557  // Set first operand
558  Binary |= getMachineOpValue(MI, 0) << ARMII::RegRnShift;
559
560  // Set addressing mode by modifying bits U(23) and P(24)
561  // IA - Increment after  - bit U = 1 and bit P = 0
562  // IB - Increment before - bit U = 1 and bit P = 1
563  // DA - Decrement after  - bit U = 0 and bit P = 0
564  // DB - Decrement before - bit U = 0 and bit P = 1
565  const MachineOperand &MO = MI.getOperand(1);
566  ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MO.getImm());
567  switch (Mode) {
568  default: assert(0 && "Unknown addressing sub-mode!");
569  case ARM_AM::da:                      break;
570  case ARM_AM::db: Binary |= 0x1 << 24; break;
571  case ARM_AM::ia: Binary |= 0x1 << 23; break;
572  case ARM_AM::ib: Binary |= 0x3 << 23; break;
573  }
574
575  // Set bit W(21)
576  if (ARM_AM::getAM4WBFlag(MO.getImm()))
577    Binary |= 0x1 << 21;
578
579  // Set registers
580  for (unsigned i = 4, e = MI.getNumOperands(); i != e; ++i) {
581    const MachineOperand &MO = MI.getOperand(i);
582    if (MO.isReg() && MO.isImplicit())
583      continue;
584    unsigned RegNum = ARMRegisterInfo::getRegisterNumbering(MO.getReg());
585    assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()) &&
586           RegNum < 16);
587    Binary |= 0x1 << RegNum;
588  }
589
590  return Binary;
591}
592
593/// getInstrBinary - Return binary encoding for the specified
594/// machine instruction.
595unsigned ARMCodeEmitter::getInstrBinary(const MachineInstr &MI) {
596  // Part of binary is determined by TableGn.
597  unsigned Binary = getBinaryCodeForInstr(MI);
598
599  const TargetInstrDesc &TID = MI.getDesc();
600  switch (TID.TSFlags & ARMII::AddrModeMask) {
601  case ARMII::AddrModeNone:
602    return getAddrModeNoneInstrBinary(MI, TID, Binary);
603  case ARMII::AddrMode1:
604    return getAddrMode1InstrBinary(MI, TID, Binary);
605  case ARMII::AddrMode2:
606    return getAddrMode2InstrBinary(MI, TID, Binary);
607  case ARMII::AddrMode3:
608    return getAddrMode3InstrBinary(MI, TID, Binary);
609  case ARMII::AddrMode4:
610    return getAddrMode4InstrBinary(MI, TID, Binary);
611  }
612
613  abort();
614  return 0;
615}
616
617#include "ARMGenCodeEmitter.inc"
618