ARMCodeEmitter.cpp revision 13d2f4e87ae6b295ce49d6fba72237b351f59de6 
1//===-- ARM/ARMCodeEmitter.cpp - Convert ARM code to machine code ---------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the pass that transforms the ARM machine instructions into
11// relocatable machine code.
12//
13//===----------------------------------------------------------------------===//
14
15#define DEBUG_TYPE "jit"
16#include "ARM.h"
17#include "ARMAddressingModes.h"
18#include "ARMConstantPoolValue.h"
19#include "ARMInstrInfo.h"
20#include "ARMRelocations.h"
21#include "ARMSubtarget.h"
22#include "ARMTargetMachine.h"
23#include "llvm/Constants.h"
24#include "llvm/DerivedTypes.h"
25#include "llvm/Function.h"
26#include "llvm/PassManager.h"
27#include "llvm/CodeGen/MachineCodeEmitter.h"
28#include "llvm/CodeGen/JITCodeEmitter.h"
29#include "llvm/CodeGen/MachineConstantPool.h"
30#include "llvm/CodeGen/MachineFunctionPass.h"
31#include "llvm/CodeGen/MachineInstr.h"
32#include "llvm/CodeGen/MachineJumpTableInfo.h"
33#include "llvm/CodeGen/Passes.h"
34#include "llvm/ADT/Statistic.h"
35#include "llvm/Support/Compiler.h"
36#include "llvm/Support/Debug.h"
37#ifndef NDEBUG
38#include <iomanip>
39#endif
40using namespace llvm;
41
42STATISTIC(NumEmitted, "Number of machine instructions emitted");
43
44namespace {
45
46  class ARMCodeEmitter {
47  public:
48    /// getBinaryCodeForInstr - This function, generated by the
49    /// CodeEmitterGenerator using TableGen, produces the binary encoding for
50    /// machine instructions.
51    unsigned getBinaryCodeForInstr(const MachineInstr &MI);
52  };
53
54  template<class CodeEmitter>
55  class VISIBILITY_HIDDEN Emitter : public MachineFunctionPass,
56                                    public ARMCodeEmitter {
57    ARMJITInfo                *JTI;
58    const ARMInstrInfo        *II;
59    const TargetData          *TD;
60    TargetMachine             &TM;
61    CodeEmitter               &MCE;
62    const std::vector<MachineConstantPoolEntry> *MCPEs;
63    const std::vector<MachineJumpTableEntry> *MJTEs;
64    bool IsPIC;
65
66  public:
67    static char ID;
68    explicit Emitter(TargetMachine &tm, CodeEmitter &mce)
69      : MachineFunctionPass(&ID), JTI(0), II(0), TD(0), TM(tm),
70      MCE(mce), MCPEs(0), MJTEs(0),
71      IsPIC(TM.getRelocationModel() == Reloc::PIC_) {}
72    Emitter(TargetMachine &tm, CodeEmitter &mce,
73            const ARMInstrInfo &ii, const TargetData &td)
74      : MachineFunctionPass(&ID), JTI(0), II(&ii), TD(&td), TM(tm),
75      MCE(mce), MCPEs(0), MJTEs(0),
76      IsPIC(TM.getRelocationModel() == Reloc::PIC_) {}
77
78    bool runOnMachineFunction(MachineFunction &MF);
79
80    virtual const char *getPassName() const {
81      return "ARM Machine Code Emitter";
82    }
83
84    void emitInstruction(const MachineInstr &MI);
85
86  private:
87
88    void emitWordLE(unsigned Binary);
89
90    void emitDWordLE(uint64_t Binary);
91
92    void emitConstPoolInstruction(const MachineInstr &MI);
93
94    void emitMOVi2piecesInstruction(const MachineInstr &MI);
95
96    void emitLEApcrelJTInstruction(const MachineInstr &MI);
97
98    void emitPseudoMoveInstruction(const MachineInstr &MI);
99
100    void addPCLabel(unsigned LabelID);
101
102    void emitPseudoInstruction(const MachineInstr &MI);
103
104    unsigned getMachineSoRegOpValue(const MachineInstr &MI,
105                                    const TargetInstrDesc &TID,
106                                    const MachineOperand &MO,
107                                    unsigned OpIdx);
108
109    unsigned getMachineSoImmOpValue(unsigned SoImm);
110
111    unsigned getAddrModeSBit(const MachineInstr &MI,
112                             const TargetInstrDesc &TID) const;
113
114    void emitDataProcessingInstruction(const MachineInstr &MI,
115                                       unsigned ImplicitRd = 0,
116                                       unsigned ImplicitRn = 0);
117
118    void emitLoadStoreInstruction(const MachineInstr &MI,
119                                  unsigned ImplicitRd = 0,
120                                  unsigned ImplicitRn = 0);
121
122    void emitMiscLoadStoreInstruction(const MachineInstr &MI,
123                                      unsigned ImplicitRn = 0);
124
125    void emitLoadStoreMultipleInstruction(const MachineInstr &MI);
126
127    void emitMulFrmInstruction(const MachineInstr &MI);
128
129    void emitExtendInstruction(const MachineInstr &MI);
130
131    void emitMiscArithInstruction(const MachineInstr &MI);
132
133    void emitBranchInstruction(const MachineInstr &MI);
134
135    void emitInlineJumpTable(unsigned JTIndex);
136
137    void emitMiscBranchInstruction(const MachineInstr &MI);
138
139    void emitVFPArithInstruction(const MachineInstr &MI);
140
141    void emitVFPConversionInstruction(const MachineInstr &MI);
142
143    void emitVFPLoadStoreInstruction(const MachineInstr &MI);
144
145    void emitVFPLoadStoreMultipleInstruction(const MachineInstr &MI);
146
147    void emitMiscInstruction(const MachineInstr &MI);
148
149    /// getMachineOpValue - Return binary encoding of operand. If the machine
150    /// operand requires relocation, record the relocation and return zero.
151    unsigned getMachineOpValue(const MachineInstr &MI,const MachineOperand &MO);
152    unsigned getMachineOpValue(const MachineInstr &MI, unsigned OpIdx) {
153      return getMachineOpValue(MI, MI.getOperand(OpIdx));
154    }
155
156    /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
157    ///
158    unsigned getShiftOp(unsigned Imm) const ;
159
160    /// Routines that handle operands which add machine relocations which are
161    /// fixed up by the relocation stage.
162    void emitGlobalAddress(GlobalValue *GV, unsigned Reloc,
163                           bool NeedStub, intptr_t ACPV = 0);
164    void emitExternalSymbolAddress(const char *ES, unsigned Reloc);
165    void emitConstPoolAddress(unsigned CPI, unsigned Reloc);
166    void emitJumpTableAddress(unsigned JTIndex, unsigned Reloc);
167    void emitMachineBasicBlock(MachineBasicBlock *BB, unsigned Reloc,
168                               intptr_t JTBase = 0);
169  };
170  template <class CodeEmitter>
171  char Emitter<CodeEmitter>::ID = 0;
172}
173
174/// createARMCodeEmitterPass - Return a pass that emits the collected ARM code
175/// to the specified MCE object.
176
177namespace llvm {
178
179FunctionPass *createARMCodeEmitterPass(ARMBaseTargetMachine &TM,
180                                       MachineCodeEmitter &MCE) {
181  return new Emitter<MachineCodeEmitter>(TM, MCE);
182}
183FunctionPass *createARMJITCodeEmitterPass(ARMBaseTargetMachine &TM,
184                                          JITCodeEmitter &JCE) {
185  return new Emitter<JITCodeEmitter>(TM, JCE);
186}
187
188} // end namespace llvm
189
190template<class CodeEmitter>
191bool Emitter<CodeEmitter>::runOnMachineFunction(MachineFunction &MF) {
192  assert((MF.getTarget().getRelocationModel() != Reloc::Default ||
193          MF.getTarget().getRelocationModel() != Reloc::Static) &&
194         "JIT relocation model must be set to static or default!");
195  II = ((ARMTargetMachine&)MF.getTarget()).getInstrInfo();
196  TD = ((ARMTargetMachine&)MF.getTarget()).getTargetData();
197  JTI = ((ARMTargetMachine&)MF.getTarget()).getJITInfo();
198  MCPEs = &MF.getConstantPool()->getConstants();
199  MJTEs = &MF.getJumpTableInfo()->getJumpTables();
200  IsPIC = TM.getRelocationModel() == Reloc::PIC_;
201  JTI->Initialize(MF, IsPIC);
202
203  do {
204    DOUT << "JITTing function '" << MF.getFunction()->getName() << "'\n";
205    MCE.startFunction(MF);
206    for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();
207         MBB != E; ++MBB) {
208      MCE.StartMachineBasicBlock(MBB);
209      for (MachineBasicBlock::const_iterator I = MBB->begin(), E = MBB->end();
210           I != E; ++I)
211        emitInstruction(*I);
212    }
213  } while (MCE.finishFunction(MF));
214
215  return false;
216}
217
218/// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
219///
220template<class CodeEmitter>
221unsigned Emitter<CodeEmitter>::getShiftOp(unsigned Imm) const {
222  switch (ARM_AM::getAM2ShiftOpc(Imm)) {
223  default: assert(0 && "Unknown shift opc!");
224  case ARM_AM::asr: return 2;
225  case ARM_AM::lsl: return 0;
226  case ARM_AM::lsr: return 1;
227  case ARM_AM::ror:
228  case ARM_AM::rrx: return 3;
229  }
230  return 0;
231}
232
233/// getMachineOpValue - Return binary encoding of operand. If the machine
234/// operand requires relocation, record the relocation and return zero.
235template<class CodeEmitter>
236unsigned Emitter<CodeEmitter>::getMachineOpValue(const MachineInstr &MI,
237                                                 const MachineOperand &MO) {
238  if (MO.isReg())
239    return ARMRegisterInfo::getRegisterNumbering(MO.getReg());
240  else if (MO.isImm())
241    return static_cast<unsigned>(MO.getImm());
242  else if (MO.isGlobal())
243    emitGlobalAddress(MO.getGlobal(), ARM::reloc_arm_branch, true);
244  else if (MO.isSymbol())
245    emitExternalSymbolAddress(MO.getSymbolName(), ARM::reloc_arm_branch);
246  else if (MO.isCPI()) {
247    const TargetInstrDesc &TID = MI.getDesc();
248    // For VFP load, the immediate offset is multiplied by 4.
249    unsigned Reloc =  ((TID.TSFlags & ARMII::FormMask) == ARMII::VFPLdStFrm)
250      ? ARM::reloc_arm_vfp_cp_entry : ARM::reloc_arm_cp_entry;
251    emitConstPoolAddress(MO.getIndex(), Reloc);
252  } else if (MO.isJTI())
253    emitJumpTableAddress(MO.getIndex(), ARM::reloc_arm_relative);
254  else if (MO.isMBB())
255    emitMachineBasicBlock(MO.getMBB(), ARM::reloc_arm_branch);
256  else {
257    cerr << "ERROR: Unknown type of MachineOperand: " << MO << "\n";
258    abort();
259  }
260  return 0;
261}
262
263/// emitGlobalAddress - Emit the specified address to the code stream.
264///
265template<class CodeEmitter>
266void Emitter<CodeEmitter>::emitGlobalAddress(GlobalValue *GV, unsigned Reloc,
267                                             bool NeedStub, intptr_t ACPV) {
268  MCE.addRelocation(MachineRelocation::getGV(MCE.getCurrentPCOffset(), Reloc,
269                                             GV, ACPV, NeedStub));
270}
271
272/// emitExternalSymbolAddress - Arrange for the address of an external symbol to
273/// be emitted to the current location in the function, and allow it to be PC
274/// relative.
275template<class CodeEmitter>
276void Emitter<CodeEmitter>::emitExternalSymbolAddress(const char *ES,
277                                                     unsigned Reloc) {
278  MCE.addRelocation(MachineRelocation::getExtSym(MCE.getCurrentPCOffset(),
279                                                 Reloc, ES));
280}
281
282/// emitConstPoolAddress - Arrange for the address of an constant pool
283/// to be emitted to the current location in the function, and allow it to be PC
284/// relative.
285template<class CodeEmitter>
286void Emitter<CodeEmitter>::emitConstPoolAddress(unsigned CPI,
287                                                unsigned Reloc) {
288  // Tell JIT emitter we'll resolve the address.
289  MCE.addRelocation(MachineRelocation::getConstPool(MCE.getCurrentPCOffset(),
290                                                    Reloc, CPI, 0, true));
291}
292
293/// emitJumpTableAddress - Arrange for the address of a jump table to
294/// be emitted to the current location in the function, and allow it to be PC
295/// relative.
296template<class CodeEmitter>
297void Emitter<CodeEmitter>::emitJumpTableAddress(unsigned JTIndex,
298                                                unsigned Reloc) {
299  MCE.addRelocation(MachineRelocation::getJumpTable(MCE.getCurrentPCOffset(),
300                                                    Reloc, JTIndex, 0, true));
301}
302
303/// emitMachineBasicBlock - Emit the specified address basic block.
304template<class CodeEmitter>
305void Emitter<CodeEmitter>::emitMachineBasicBlock(MachineBasicBlock *BB,
306                                              unsigned Reloc, intptr_t JTBase) {
307  MCE.addRelocation(MachineRelocation::getBB(MCE.getCurrentPCOffset(),
308                                             Reloc, BB, JTBase));
309}
310
311template<class CodeEmitter>
312void Emitter<CodeEmitter>::emitWordLE(unsigned Binary) {
313#ifndef NDEBUG
314  DOUT << "  0x" << std::hex << std::setw(8) << std::setfill('0')
315       << Binary << std::dec << "\n";
316#endif
317  MCE.emitWordLE(Binary);
318}
319
320template<class CodeEmitter>
321void Emitter<CodeEmitter>::emitDWordLE(uint64_t Binary) {
322#ifndef NDEBUG
323  DOUT << "  0x" << std::hex << std::setw(8) << std::setfill('0')
324       << (unsigned)Binary << std::dec << "\n";
325  DOUT << "  0x" << std::hex << std::setw(8) << std::setfill('0')
326       << (unsigned)(Binary >> 32) << std::dec << "\n";
327#endif
328  MCE.emitDWordLE(Binary);
329}
330
331template<class CodeEmitter>
332void Emitter<CodeEmitter>::emitInstruction(const MachineInstr &MI) {
333  DOUT << "JIT: " << (void*)MCE.getCurrentPCValue() << ":\t" << MI;
334
335  NumEmitted++;  // Keep track of the # of mi's emitted
336  switch (MI.getDesc().TSFlags & ARMII::FormMask) {
337  default: {
338    assert(0 && "Unhandled instruction encoding format!");
339    break;
340  }
341  case ARMII::Pseudo:
342    emitPseudoInstruction(MI);
343    break;
344  case ARMII::DPFrm:
345  case ARMII::DPSoRegFrm:
346    emitDataProcessingInstruction(MI);
347    break;
348  case ARMII::LdFrm:
349  case ARMII::StFrm:
350    emitLoadStoreInstruction(MI);
351    break;
352  case ARMII::LdMiscFrm:
353  case ARMII::StMiscFrm:
354    emitMiscLoadStoreInstruction(MI);
355    break;
356  case ARMII::LdStMulFrm:
357    emitLoadStoreMultipleInstruction(MI);
358    break;
359  case ARMII::MulFrm:
360    emitMulFrmInstruction(MI);
361    break;
362  case ARMII::ExtFrm:
363    emitExtendInstruction(MI);
364    break;
365  case ARMII::ArithMiscFrm:
366    emitMiscArithInstruction(MI);
367    break;
368  case ARMII::BrFrm:
369    emitBranchInstruction(MI);
370    break;
371  case ARMII::BrMiscFrm:
372    emitMiscBranchInstruction(MI);
373    break;
374  // VFP instructions.
375  case ARMII::VFPUnaryFrm:
376  case ARMII::VFPBinaryFrm:
377    emitVFPArithInstruction(MI);
378    break;
379  case ARMII::VFPConv1Frm:
380  case ARMII::VFPConv2Frm:
381  case ARMII::VFPConv3Frm:
382  case ARMII::VFPConv4Frm:
383  case ARMII::VFPConv5Frm:
384    emitVFPConversionInstruction(MI);
385    break;
386  case ARMII::VFPLdStFrm:
387    emitVFPLoadStoreInstruction(MI);
388    break;
389  case ARMII::VFPLdStMulFrm:
390    emitVFPLoadStoreMultipleInstruction(MI);
391    break;
392  case ARMII::VFPMiscFrm:
393    emitMiscInstruction(MI);
394    break;
395  }
396}
397
398template<class CodeEmitter>
399void Emitter<CodeEmitter>::emitConstPoolInstruction(const MachineInstr &MI) {
400  unsigned CPI = MI.getOperand(0).getImm();       // CP instruction index.
401  unsigned CPIndex = MI.getOperand(1).getIndex(); // Actual cp entry index.
402  const MachineConstantPoolEntry &MCPE = (*MCPEs)[CPIndex];
403
404  // Remember the CONSTPOOL_ENTRY address for later relocation.
405  JTI->addConstantPoolEntryAddr(CPI, MCE.getCurrentPCValue());
406
407  // Emit constpool island entry. In most cases, the actual values will be
408  // resolved and relocated after code emission.
409  if (MCPE.isMachineConstantPoolEntry()) {
410    ARMConstantPoolValue *ACPV =
411      static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal);
412
413    DOUT << "  ** ARM constant pool #" << CPI << " @ "
414         << (void*)MCE.getCurrentPCValue() << " " << *ACPV << '\n';
415
416    GlobalValue *GV = ACPV->getGV();
417    if (GV) {
418      assert(!ACPV->isStub() && "Don't know how to deal this yet!");
419      if (ACPV->isNonLazyPointer())
420        MCE.addRelocation(MachineRelocation::getIndirectSymbol(
421                  MCE.getCurrentPCOffset(), ARM::reloc_arm_machine_cp_entry, GV,
422                  (intptr_t)ACPV, false));
423      else
424        emitGlobalAddress(GV, ARM::reloc_arm_machine_cp_entry,
425                          ACPV->isStub() || isa<Function>(GV), (intptr_t)ACPV);
426     } else  {
427      assert(!ACPV->isNonLazyPointer() && "Don't know how to deal this yet!");
428      emitExternalSymbolAddress(ACPV->getSymbol(), ARM::reloc_arm_absolute);
429    }
430    emitWordLE(0);
431  } else {
432    Constant *CV = MCPE.Val.ConstVal;
433
434#ifndef NDEBUG
435    DOUT << "  ** Constant pool #" << CPI << " @ "
436         << (void*)MCE.getCurrentPCValue() << " ";
437    if (const Function *F = dyn_cast<Function>(CV))
438      DOUT << F->getName();
439    else
440      DOUT << *CV;
441    DOUT << '\n';
442#endif
443
444    if (GlobalValue *GV = dyn_cast<GlobalValue>(CV)) {
445      emitGlobalAddress(GV, ARM::reloc_arm_absolute, isa<Function>(GV));
446      emitWordLE(0);
447    } else if (const ConstantInt *CI = dyn_cast<ConstantInt>(CV)) {
448      uint32_t Val = *(uint32_t*)CI->getValue().getRawData();
449      emitWordLE(Val);
450    } else if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CV)) {
451      if (CFP->getType() == Type::FloatTy)
452        emitWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue());
453      else if (CFP->getType() == Type::DoubleTy)
454        emitDWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue());
455      else {
456        assert(0 && "Unable to handle this constantpool entry!");
457        abort();
458      }
459    } else {
460      assert(0 && "Unable to handle this constantpool entry!");
461      abort();
462    }
463  }
464}
465
466template<class CodeEmitter>
467void Emitter<CodeEmitter>::emitMOVi2piecesInstruction(const MachineInstr &MI) {
468  const MachineOperand &MO0 = MI.getOperand(0);
469  const MachineOperand &MO1 = MI.getOperand(1);
470  assert(MO1.isImm() && "Not a valid so_imm value!");
471  unsigned V1 = ARM_AM::getSOImmTwoPartFirst(MO1.getImm());
472  unsigned V2 = ARM_AM::getSOImmTwoPartSecond(MO1.getImm());
473
474  // Emit the 'mov' instruction.
475  unsigned Binary = 0xd << 21;  // mov: Insts{24-21} = 0b1101
476
477  // Set the conditional execution predicate.
478  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
479
480  // Encode Rd.
481  Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
482
483  // Encode so_imm.
484  // Set bit I(25) to identify this is the immediate form of <shifter_op>
485  Binary |= 1 << ARMII::I_BitShift;
486  Binary |= getMachineSoImmOpValue(ARM_AM::getSOImmVal(V1));
487  emitWordLE(Binary);
488
489  // Now the 'orr' instruction.
490  Binary = 0xc << 21;  // orr: Insts{24-21} = 0b1100
491
492  // Set the conditional execution predicate.
493  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
494
495  // Encode Rd.
496  Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
497
498  // Encode Rn.
499  Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRnShift;
500
501  // Encode so_imm.
502  // Set bit I(25) to identify this is the immediate form of <shifter_op>
503  Binary |= 1 << ARMII::I_BitShift;
504  Binary |= getMachineSoImmOpValue(ARM_AM::getSOImmVal(V2));
505  emitWordLE(Binary);
506}
507
508template<class CodeEmitter>
509void Emitter<CodeEmitter>::emitLEApcrelJTInstruction(const MachineInstr &MI) {
510  // It's basically add r, pc, (LJTI - $+8)
511
512  const TargetInstrDesc &TID = MI.getDesc();
513
514  // Emit the 'add' instruction.
515  unsigned Binary = 0x4 << 21;  // add: Insts{24-31} = 0b0100
516
517  // Set the conditional execution predicate
518  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
519
520  // Encode S bit if MI modifies CPSR.
521  Binary |= getAddrModeSBit(MI, TID);
522
523  // Encode Rd.
524  Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
525
526  // Encode Rn which is PC.
527  Binary |= ARMRegisterInfo::getRegisterNumbering(ARM::PC) << ARMII::RegRnShift;
528
529  // Encode the displacement.
530  // Set bit I(25) to identify this is the immediate form of <shifter_op>.
531  Binary |= 1 << ARMII::I_BitShift;
532  emitJumpTableAddress(MI.getOperand(1).getIndex(), ARM::reloc_arm_jt_base);
533
534  emitWordLE(Binary);
535}
536
537template<class CodeEmitter>
538void Emitter<CodeEmitter>::emitPseudoMoveInstruction(const MachineInstr &MI) {
539  unsigned Opcode = MI.getDesc().Opcode;
540
541  // Part of binary is determined by TableGn.
542  unsigned Binary = getBinaryCodeForInstr(MI);
543
544  // Set the conditional execution predicate
545  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
546
547  // Encode S bit if MI modifies CPSR.
548  if (Opcode == ARM::MOVsrl_flag || Opcode == ARM::MOVsra_flag)
549    Binary |= 1 << ARMII::S_BitShift;
550
551  // Encode register def if there is one.
552  Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
553
554  // Encode the shift operation.
555  switch (Opcode) {
556  default: break;
557  case ARM::MOVrx:
558    // rrx
559    Binary |= 0x6 << 4;
560    break;
561  case ARM::MOVsrl_flag:
562    // lsr #1
563    Binary |= (0x2 << 4) | (1 << 7);
564    break;
565  case ARM::MOVsra_flag:
566    // asr #1
567    Binary |= (0x4 << 4) | (1 << 7);
568    break;
569  }
570
571  // Encode register Rm.
572  Binary |= getMachineOpValue(MI, 1);
573
574  emitWordLE(Binary);
575}
576
577template<class CodeEmitter>
578void Emitter<CodeEmitter>::addPCLabel(unsigned LabelID) {
579  DOUT << "  ** LPC" << LabelID << " @ "
580       << (void*)MCE.getCurrentPCValue() << '\n';
581  JTI->addPCLabelAddr(LabelID, MCE.getCurrentPCValue());
582}
583
584template<class CodeEmitter>
585void Emitter<CodeEmitter>::emitPseudoInstruction(const MachineInstr &MI) {
586  unsigned Opcode = MI.getDesc().Opcode;
587  switch (Opcode) {
588  default:
589    abort(); // FIXME:
590  case TargetInstrInfo::INLINEASM: {
591    // We allow inline assembler nodes with empty bodies - they can
592    // implicitly define registers, which is ok for JIT.
593    if (MI.getOperand(0).getSymbolName()[0]) {
594      assert(0 && "JIT does not support inline asm!\n");
595      abort();
596    }
597    break;
598  }
599  case TargetInstrInfo::DBG_LABEL:
600  case TargetInstrInfo::EH_LABEL:
601    MCE.emitLabel(MI.getOperand(0).getImm());
602    break;
603  case TargetInstrInfo::IMPLICIT_DEF:
604  case TargetInstrInfo::DECLARE:
605  case ARM::DWARF_LOC:
606    // Do nothing.
607    break;
608  case ARM::CONSTPOOL_ENTRY:
609    emitConstPoolInstruction(MI);
610    break;
611  case ARM::PICADD: {
612    // Remember of the address of the PC label for relocation later.
613    addPCLabel(MI.getOperand(2).getImm());
614    // PICADD is just an add instruction that implicitly read pc.
615    emitDataProcessingInstruction(MI, 0, ARM::PC);
616    break;
617  }
618  case ARM::PICLDR:
619  case ARM::PICLDRB:
620  case ARM::PICSTR:
621  case ARM::PICSTRB: {
622    // Remember of the address of the PC label for relocation later.
623    addPCLabel(MI.getOperand(2).getImm());
624    // These are just load / store instructions that implicitly read pc.
625    emitLoadStoreInstruction(MI, 0, ARM::PC);
626    break;
627  }
628  case ARM::PICLDRH:
629  case ARM::PICLDRSH:
630  case ARM::PICLDRSB:
631  case ARM::PICSTRH: {
632    // Remember of the address of the PC label for relocation later.
633    addPCLabel(MI.getOperand(2).getImm());
634    // These are just load / store instructions that implicitly read pc.
635    emitMiscLoadStoreInstruction(MI, ARM::PC);
636    break;
637  }
638  case ARM::MOVi2pieces:
639    // Two instructions to materialize a constant.
640    emitMOVi2piecesInstruction(MI);
641    break;
642  case ARM::LEApcrelJT:
643    // Materialize jumptable address.
644    emitLEApcrelJTInstruction(MI);
645    break;
646  case ARM::MOVrx:
647  case ARM::MOVsrl_flag:
648  case ARM::MOVsra_flag:
649    emitPseudoMoveInstruction(MI);
650    break;
651  }
652}
653
654template<class CodeEmitter>
655unsigned Emitter<CodeEmitter>::getMachineSoRegOpValue(
656                                                const MachineInstr &MI,
657                                                const TargetInstrDesc &TID,
658                                                const MachineOperand &MO,
659                                                unsigned OpIdx) {
660  unsigned Binary = getMachineOpValue(MI, MO);
661
662  const MachineOperand &MO1 = MI.getOperand(OpIdx + 1);
663  const MachineOperand &MO2 = MI.getOperand(OpIdx + 2);
664  ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm());
665
666  // Encode the shift opcode.
667  unsigned SBits = 0;
668  unsigned Rs = MO1.getReg();
669  if (Rs) {
670    // Set shift operand (bit[7:4]).
671    // LSL - 0001
672    // LSR - 0011
673    // ASR - 0101
674    // ROR - 0111
675    // RRX - 0110 and bit[11:8] clear.
676    switch (SOpc) {
677    default: assert(0 && "Unknown shift opc!");
678    case ARM_AM::lsl: SBits = 0x1; break;
679    case ARM_AM::lsr: SBits = 0x3; break;
680    case ARM_AM::asr: SBits = 0x5; break;
681    case ARM_AM::ror: SBits = 0x7; break;
682    case ARM_AM::rrx: SBits = 0x6; break;
683    }
684  } else {
685    // Set shift operand (bit[6:4]).
686    // LSL - 000
687    // LSR - 010
688    // ASR - 100
689    // ROR - 110
690    switch (SOpc) {
691    default: assert(0 && "Unknown shift opc!");
692    case ARM_AM::lsl: SBits = 0x0; break;
693    case ARM_AM::lsr: SBits = 0x2; break;
694    case ARM_AM::asr: SBits = 0x4; break;
695    case ARM_AM::ror: SBits = 0x6; break;
696    }
697  }
698  Binary |= SBits << 4;
699  if (SOpc == ARM_AM::rrx)
700    return Binary;
701
702  // Encode the shift operation Rs or shift_imm (except rrx).
703  if (Rs) {
704    // Encode Rs bit[11:8].
705    assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0);
706    return Binary |
707      (ARMRegisterInfo::getRegisterNumbering(Rs) << ARMII::RegRsShift);
708  }
709
710  // Encode shift_imm bit[11:7].
711  return Binary | ARM_AM::getSORegOffset(MO2.getImm()) << 7;
712}
713
714template<class CodeEmitter>
715unsigned Emitter<CodeEmitter>::getMachineSoImmOpValue(unsigned SoImm) {
716  // Encode rotate_imm.
717  unsigned Binary = (ARM_AM::getSOImmValRot(SoImm) >> 1)
718    << ARMII::SoRotImmShift;
719
720  // Encode immed_8.
721  Binary |= ARM_AM::getSOImmValImm(SoImm);
722  return Binary;
723}
724
725template<class CodeEmitter>
726unsigned Emitter<CodeEmitter>::getAddrModeSBit(const MachineInstr &MI,
727                                             const TargetInstrDesc &TID) const {
728  for (unsigned i = MI.getNumOperands(), e = TID.getNumOperands(); i != e; --i){
729    const MachineOperand &MO = MI.getOperand(i-1);
730    if (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR)
731      return 1 << ARMII::S_BitShift;
732  }
733  return 0;
734}
735
736template<class CodeEmitter>
737void Emitter<CodeEmitter>::emitDataProcessingInstruction(
738                                                   const MachineInstr &MI,
739                                                   unsigned ImplicitRd,
740                                                   unsigned ImplicitRn) {
741  const TargetInstrDesc &TID = MI.getDesc();
742
743  // Part of binary is determined by TableGn.
744  unsigned Binary = getBinaryCodeForInstr(MI);
745
746  // Set the conditional execution predicate
747  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
748
749  // Encode S bit if MI modifies CPSR.
750  Binary |= getAddrModeSBit(MI, TID);
751
752  // Encode register def if there is one.
753  unsigned NumDefs = TID.getNumDefs();
754  unsigned OpIdx = 0;
755  if (NumDefs)
756    Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
757  else if (ImplicitRd)
758    // Special handling for implicit use (e.g. PC).
759    Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRd)
760               << ARMII::RegRdShift);
761
762  // If this is a two-address operand, skip it. e.g. MOVCCr operand 1.
763  if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
764    ++OpIdx;
765
766  // Encode first non-shifter register operand if there is one.
767  bool isUnary = TID.TSFlags & ARMII::UnaryDP;
768  if (!isUnary) {
769    if (ImplicitRn)
770      // Special handling for implicit use (e.g. PC).
771      Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRn)
772                 << ARMII::RegRnShift);
773    else {
774      Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRnShift;
775      ++OpIdx;
776    }
777  }
778
779  // Encode shifter operand.
780  const MachineOperand &MO = MI.getOperand(OpIdx);
781  if ((TID.TSFlags & ARMII::FormMask) == ARMII::DPSoRegFrm) {
782    // Encode SoReg.
783    emitWordLE(Binary | getMachineSoRegOpValue(MI, TID, MO, OpIdx));
784    return;
785  }
786
787  if (MO.isReg()) {
788    // Encode register Rm.
789    emitWordLE(Binary | ARMRegisterInfo::getRegisterNumbering(MO.getReg()));
790    return;
791  }
792
793  // Encode so_imm.
794  // Set bit I(25) to identify this is the immediate form of <shifter_op>.
795  Binary |= 1 << ARMII::I_BitShift;
796  Binary |= getMachineSoImmOpValue(MO.getImm());
797
798  emitWordLE(Binary);
799}
800
801template<class CodeEmitter>
802void Emitter<CodeEmitter>::emitLoadStoreInstruction(
803                                              const MachineInstr &MI,
804                                              unsigned ImplicitRd,
805                                              unsigned ImplicitRn) {
806  const TargetInstrDesc &TID = MI.getDesc();
807  unsigned Form = TID.TSFlags & ARMII::FormMask;
808  bool IsPrePost = (TID.TSFlags & ARMII::IndexModeMask) != 0;
809
810  // Part of binary is determined by TableGn.
811  unsigned Binary = getBinaryCodeForInstr(MI);
812
813  // Set the conditional execution predicate
814  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
815
816  unsigned OpIdx = 0;
817
818  // Operand 0 of a pre- and post-indexed store is the address base
819  // writeback. Skip it.
820  bool Skipped = false;
821  if (IsPrePost && Form == ARMII::StFrm) {
822    ++OpIdx;
823    Skipped = true;
824  }
825
826  // Set first operand
827  if (ImplicitRd)
828    // Special handling for implicit use (e.g. PC).
829    Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRd)
830               << ARMII::RegRdShift);
831  else
832    Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
833
834  // Set second operand
835  if (ImplicitRn)
836    // Special handling for implicit use (e.g. PC).
837    Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRn)
838               << ARMII::RegRnShift);
839  else
840    Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
841
842  // If this is a two-address operand, skip it. e.g. LDR_PRE.
843  if (!Skipped && TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
844    ++OpIdx;
845
846  const MachineOperand &MO2 = MI.getOperand(OpIdx);
847  unsigned AM2Opc = (ImplicitRn == ARM::PC)
848    ? 0 : MI.getOperand(OpIdx+1).getImm();
849
850  // Set bit U(23) according to sign of immed value (positive or negative).
851  Binary |= ((ARM_AM::getAM2Op(AM2Opc) == ARM_AM::add ? 1 : 0) <<
852             ARMII::U_BitShift);
853  if (!MO2.getReg()) { // is immediate
854    if (ARM_AM::getAM2Offset(AM2Opc))
855      // Set the value of offset_12 field
856      Binary |= ARM_AM::getAM2Offset(AM2Opc);
857    emitWordLE(Binary);
858    return;
859  }
860
861  // Set bit I(25), because this is not in immediate enconding.
862  Binary |= 1 << ARMII::I_BitShift;
863  assert(TargetRegisterInfo::isPhysicalRegister(MO2.getReg()));
864  // Set bit[3:0] to the corresponding Rm register
865  Binary |= ARMRegisterInfo::getRegisterNumbering(MO2.getReg());
866
867  // If this instr is in scaled register offset/index instruction, set
868  // shift_immed(bit[11:7]) and shift(bit[6:5]) fields.
869  if (unsigned ShImm = ARM_AM::getAM2Offset(AM2Opc)) {
870    Binary |= getShiftOp(AM2Opc) << ARMII::ShiftImmShift;  // shift
871    Binary |= ShImm              << ARMII::ShiftShift;     // shift_immed
872  }
873
874  emitWordLE(Binary);
875}
876
877template<class CodeEmitter>
878void Emitter<CodeEmitter>::emitMiscLoadStoreInstruction(const MachineInstr &MI,
879                                                        unsigned ImplicitRn) {
880  const TargetInstrDesc &TID = MI.getDesc();
881  unsigned Form = TID.TSFlags & ARMII::FormMask;
882  bool IsPrePost = (TID.TSFlags & ARMII::IndexModeMask) != 0;
883
884  // Part of binary is determined by TableGn.
885  unsigned Binary = getBinaryCodeForInstr(MI);
886
887  // Set the conditional execution predicate
888  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
889
890  unsigned OpIdx = 0;
891
892  // Operand 0 of a pre- and post-indexed store is the address base
893  // writeback. Skip it.
894  bool Skipped = false;
895  if (IsPrePost && Form == ARMII::StMiscFrm) {
896    ++OpIdx;
897    Skipped = true;
898  }
899
900  // Set first operand
901  Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
902
903  // Skip LDRD and STRD's second operand.
904  if (TID.Opcode == ARM::LDRD || TID.Opcode == ARM::STRD)
905    ++OpIdx;
906
907  // Set second operand
908  if (ImplicitRn)
909    // Special handling for implicit use (e.g. PC).
910    Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRn)
911               << ARMII::RegRnShift);
912  else
913    Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
914
915  // If this is a two-address operand, skip it. e.g. LDRH_POST.
916  if (!Skipped && TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
917    ++OpIdx;
918
919  const MachineOperand &MO2 = MI.getOperand(OpIdx);
920  unsigned AM3Opc = (ImplicitRn == ARM::PC)
921    ? 0 : MI.getOperand(OpIdx+1).getImm();
922
923  // Set bit U(23) according to sign of immed value (positive or negative)
924  Binary |= ((ARM_AM::getAM3Op(AM3Opc) == ARM_AM::add ? 1 : 0) <<
925             ARMII::U_BitShift);
926
927  // If this instr is in register offset/index encoding, set bit[3:0]
928  // to the corresponding Rm register.
929  if (MO2.getReg()) {
930    Binary |= ARMRegisterInfo::getRegisterNumbering(MO2.getReg());
931    emitWordLE(Binary);
932    return;
933  }
934
935  // This instr is in immediate offset/index encoding, set bit 22 to 1.
936  Binary |= 1 << ARMII::AM3_I_BitShift;
937  if (unsigned ImmOffs = ARM_AM::getAM3Offset(AM3Opc)) {
938    // Set operands
939    Binary |= (ImmOffs >> 4) << ARMII::ImmHiShift;  // immedH
940    Binary |= (ImmOffs & 0xF);                      // immedL
941  }
942
943  emitWordLE(Binary);
944}
945
946static unsigned getAddrModeUPBits(unsigned Mode) {
947  unsigned Binary = 0;
948
949  // Set addressing mode by modifying bits U(23) and P(24)
950  // IA - Increment after  - bit U = 1 and bit P = 0
951  // IB - Increment before - bit U = 1 and bit P = 1
952  // DA - Decrement after  - bit U = 0 and bit P = 0
953  // DB - Decrement before - bit U = 0 and bit P = 1
954  switch (Mode) {
955  default: assert(0 && "Unknown addressing sub-mode!");
956  case ARM_AM::da:                      break;
957  case ARM_AM::db: Binary |= 0x1 << ARMII::P_BitShift; break;
958  case ARM_AM::ia: Binary |= 0x1 << ARMII::U_BitShift; break;
959  case ARM_AM::ib: Binary |= 0x3 << ARMII::U_BitShift; break;
960  }
961
962  return Binary;
963}
964
965template<class CodeEmitter>
966void Emitter<CodeEmitter>::emitLoadStoreMultipleInstruction(
967                                                       const MachineInstr &MI) {
968  // Part of binary is determined by TableGn.
969  unsigned Binary = getBinaryCodeForInstr(MI);
970
971  // Set the conditional execution predicate
972  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
973
974  // Set base address operand
975  Binary |= getMachineOpValue(MI, 0) << ARMII::RegRnShift;
976
977  // Set addressing mode by modifying bits U(23) and P(24)
978  const MachineOperand &MO = MI.getOperand(1);
979  Binary |= getAddrModeUPBits(ARM_AM::getAM4SubMode(MO.getImm()));
980
981  // Set bit W(21)
982  if (ARM_AM::getAM4WBFlag(MO.getImm()))
983    Binary |= 0x1 << ARMII::W_BitShift;
984
985  // Set registers
986  for (unsigned i = 4, e = MI.getNumOperands(); i != e; ++i) {
987    const MachineOperand &MO = MI.getOperand(i);
988    if (!MO.isReg() || MO.isImplicit())
989      break;
990    unsigned RegNum = ARMRegisterInfo::getRegisterNumbering(MO.getReg());
991    assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()) &&
992           RegNum < 16);
993    Binary |= 0x1 << RegNum;
994  }
995
996  emitWordLE(Binary);
997}
998
999template<class CodeEmitter>
1000void Emitter<CodeEmitter>::emitMulFrmInstruction(const MachineInstr &MI) {
1001  const TargetInstrDesc &TID = MI.getDesc();
1002
1003  // Part of binary is determined by TableGn.
1004  unsigned Binary = getBinaryCodeForInstr(MI);
1005
1006  // Set the conditional execution predicate
1007  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1008
1009  // Encode S bit if MI modifies CPSR.
1010  Binary |= getAddrModeSBit(MI, TID);
1011
1012  // 32x32->64bit operations have two destination registers. The number
1013  // of register definitions will tell us if that's what we're dealing with.
1014  unsigned OpIdx = 0;
1015  if (TID.getNumDefs() == 2)
1016    Binary |= getMachineOpValue (MI, OpIdx++) << ARMII::RegRdLoShift;
1017
1018  // Encode Rd
1019  Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdHiShift;
1020
1021  // Encode Rm
1022  Binary |= getMachineOpValue(MI, OpIdx++);
1023
1024  // Encode Rs
1025  Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRsShift;
1026
1027  // Many multiple instructions (e.g. MLA) have three src operands. Encode
1028  // it as Rn (for multiply, that's in the same offset as RdLo.
1029  if (TID.getNumOperands() > OpIdx &&
1030      !TID.OpInfo[OpIdx].isPredicate() &&
1031      !TID.OpInfo[OpIdx].isOptionalDef())
1032    Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRdLoShift;
1033
1034  emitWordLE(Binary);
1035}
1036
1037template<class CodeEmitter>
1038void Emitter<CodeEmitter>::emitExtendInstruction(const MachineInstr &MI) {
1039  const TargetInstrDesc &TID = MI.getDesc();
1040
1041  // Part of binary is determined by TableGn.
1042  unsigned Binary = getBinaryCodeForInstr(MI);
1043
1044  // Set the conditional execution predicate
1045  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1046
1047  unsigned OpIdx = 0;
1048
1049  // Encode Rd
1050  Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1051
1052  const MachineOperand &MO1 = MI.getOperand(OpIdx++);
1053  const MachineOperand &MO2 = MI.getOperand(OpIdx);
1054  if (MO2.isReg()) {
1055    // Two register operand form.
1056    // Encode Rn.
1057    Binary |= getMachineOpValue(MI, MO1) << ARMII::RegRnShift;
1058
1059    // Encode Rm.
1060    Binary |= getMachineOpValue(MI, MO2);
1061    ++OpIdx;
1062  } else {
1063    Binary |= getMachineOpValue(MI, MO1);
1064  }
1065
1066  // Encode rot imm (0, 8, 16, or 24) if it has a rotate immediate operand.
1067  if (MI.getOperand(OpIdx).isImm() &&
1068      !TID.OpInfo[OpIdx].isPredicate() &&
1069      !TID.OpInfo[OpIdx].isOptionalDef())
1070    Binary |= (getMachineOpValue(MI, OpIdx) / 8) << ARMII::ExtRotImmShift;
1071
1072  emitWordLE(Binary);
1073}
1074
1075template<class CodeEmitter>
1076void Emitter<CodeEmitter>::emitMiscArithInstruction(const MachineInstr &MI) {
1077  const TargetInstrDesc &TID = MI.getDesc();
1078
1079  // Part of binary is determined by TableGn.
1080  unsigned Binary = getBinaryCodeForInstr(MI);
1081
1082  // Set the conditional execution predicate
1083  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1084
1085  unsigned OpIdx = 0;
1086
1087  // Encode Rd
1088  Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1089
1090  const MachineOperand &MO = MI.getOperand(OpIdx++);
1091  if (OpIdx == TID.getNumOperands() ||
1092      TID.OpInfo[OpIdx].isPredicate() ||
1093      TID.OpInfo[OpIdx].isOptionalDef()) {
1094    // Encode Rm and it's done.
1095    Binary |= getMachineOpValue(MI, MO);
1096    emitWordLE(Binary);
1097    return;
1098  }
1099
1100  // Encode Rn.
1101  Binary |= getMachineOpValue(MI, MO) << ARMII::RegRnShift;
1102
1103  // Encode Rm.
1104  Binary |= getMachineOpValue(MI, OpIdx++);
1105
1106  // Encode shift_imm.
1107  unsigned ShiftAmt = MI.getOperand(OpIdx).getImm();
1108  assert(ShiftAmt < 32 && "shift_imm range is 0 to 31!");
1109  Binary |= ShiftAmt << ARMII::ShiftShift;
1110
1111  emitWordLE(Binary);
1112}
1113
1114template<class CodeEmitter>
1115void Emitter<CodeEmitter>::emitBranchInstruction(const MachineInstr &MI) {
1116  const TargetInstrDesc &TID = MI.getDesc();
1117
1118  if (TID.Opcode == ARM::TPsoft)
1119    abort(); // FIXME
1120
1121  // Part of binary is determined by TableGn.
1122  unsigned Binary = getBinaryCodeForInstr(MI);
1123
1124  // Set the conditional execution predicate
1125  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1126
1127  // Set signed_immed_24 field
1128  Binary |= getMachineOpValue(MI, 0);
1129
1130  emitWordLE(Binary);
1131}
1132
1133template<class CodeEmitter>
1134void Emitter<CodeEmitter>::emitInlineJumpTable(unsigned JTIndex) {
1135  // Remember the base address of the inline jump table.
1136  uintptr_t JTBase = MCE.getCurrentPCValue();
1137  JTI->addJumpTableBaseAddr(JTIndex, JTBase);
1138  DOUT << "  ** Jump Table #" << JTIndex << " @ " << (void*)JTBase << '\n';
1139
1140  // Now emit the jump table entries.
1141  const std::vector<MachineBasicBlock*> &MBBs = (*MJTEs)[JTIndex].MBBs;
1142  for (unsigned i = 0, e = MBBs.size(); i != e; ++i) {
1143    if (IsPIC)
1144      // DestBB address - JT base.
1145      emitMachineBasicBlock(MBBs[i], ARM::reloc_arm_pic_jt, JTBase);
1146    else
1147      // Absolute DestBB address.
1148      emitMachineBasicBlock(MBBs[i], ARM::reloc_arm_absolute);
1149    emitWordLE(0);
1150  }
1151}
1152
1153template<class CodeEmitter>
1154void Emitter<CodeEmitter>::emitMiscBranchInstruction(const MachineInstr &MI) {
1155  const TargetInstrDesc &TID = MI.getDesc();
1156
1157  // Handle jump tables.
1158  if (TID.Opcode == ARM::BR_JTr || TID.Opcode == ARM::BR_JTadd ||
1159      TID.Opcode == ARM::t2BR_JTr || TID.Opcode == ARM::t2BR_JTadd) {
1160    // First emit a ldr pc, [] instruction.
1161    emitDataProcessingInstruction(MI, ARM::PC);
1162
1163    // Then emit the inline jump table.
1164    unsigned JTIndex = (TID.Opcode == ARM::BR_JTr || TID.Opcode == ARM::t2BR_JTr)
1165      ? MI.getOperand(1).getIndex() : MI.getOperand(2).getIndex();
1166    emitInlineJumpTable(JTIndex);
1167    return;
1168  } else if (TID.Opcode == ARM::BR_JTm || TID.Opcode == ARM::t2BR_JTm) {
1169    // First emit a ldr pc, [] instruction.
1170    emitLoadStoreInstruction(MI, ARM::PC);
1171
1172    // Then emit the inline jump table.
1173    emitInlineJumpTable(MI.getOperand(3).getIndex());
1174    return;
1175  }
1176
1177  // Part of binary is determined by TableGn.
1178  unsigned Binary = getBinaryCodeForInstr(MI);
1179
1180  // Set the conditional execution predicate
1181  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1182
1183  if (TID.Opcode == ARM::BX_RET)
1184    // The return register is LR.
1185    Binary |= ARMRegisterInfo::getRegisterNumbering(ARM::LR);
1186  else
1187    // otherwise, set the return register
1188    Binary |= getMachineOpValue(MI, 0);
1189
1190  emitWordLE(Binary);
1191}
1192
1193static unsigned encodeVFPRd(const MachineInstr &MI, unsigned OpIdx) {
1194  unsigned RegD = MI.getOperand(OpIdx).getReg();
1195  unsigned Binary = 0;
1196  bool isSPVFP = false;
1197  RegD = ARMRegisterInfo::getRegisterNumbering(RegD, isSPVFP);
1198  if (!isSPVFP)
1199    Binary |=   RegD               << ARMII::RegRdShift;
1200  else {
1201    Binary |= ((RegD & 0x1E) >> 1) << ARMII::RegRdShift;
1202    Binary |=  (RegD & 0x01)       << ARMII::D_BitShift;
1203  }
1204  return Binary;
1205}
1206
1207static unsigned encodeVFPRn(const MachineInstr &MI, unsigned OpIdx) {
1208  unsigned RegN = MI.getOperand(OpIdx).getReg();
1209  unsigned Binary = 0;
1210  bool isSPVFP = false;
1211  RegN = ARMRegisterInfo::getRegisterNumbering(RegN, isSPVFP);
1212  if (!isSPVFP)
1213    Binary |=   RegN               << ARMII::RegRnShift;
1214  else {
1215    Binary |= ((RegN & 0x1E) >> 1) << ARMII::RegRnShift;
1216    Binary |=  (RegN & 0x01)       << ARMII::N_BitShift;
1217  }
1218  return Binary;
1219}
1220
1221static unsigned encodeVFPRm(const MachineInstr &MI, unsigned OpIdx) {
1222  unsigned RegM = MI.getOperand(OpIdx).getReg();
1223  unsigned Binary = 0;
1224  bool isSPVFP = false;
1225  RegM = ARMRegisterInfo::getRegisterNumbering(RegM, isSPVFP);
1226  if (!isSPVFP)
1227    Binary |=   RegM;
1228  else {
1229    Binary |= ((RegM & 0x1E) >> 1);
1230    Binary |=  (RegM & 0x01)       << ARMII::M_BitShift;
1231  }
1232  return Binary;
1233}
1234
1235template<class CodeEmitter>
1236void Emitter<CodeEmitter>::emitVFPArithInstruction(const MachineInstr &MI) {
1237  const TargetInstrDesc &TID = MI.getDesc();
1238
1239  // Part of binary is determined by TableGn.
1240  unsigned Binary = getBinaryCodeForInstr(MI);
1241
1242  // Set the conditional execution predicate
1243  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1244
1245  unsigned OpIdx = 0;
1246  assert((Binary & ARMII::D_BitShift) == 0 &&
1247         (Binary & ARMII::N_BitShift) == 0 &&
1248         (Binary & ARMII::M_BitShift) == 0 && "VFP encoding bug!");
1249
1250  // Encode Dd / Sd.
1251  Binary |= encodeVFPRd(MI, OpIdx++);
1252
1253  // If this is a two-address operand, skip it, e.g. FMACD.
1254  if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1255    ++OpIdx;
1256
1257  // Encode Dn / Sn.
1258  if ((TID.TSFlags & ARMII::FormMask) == ARMII::VFPBinaryFrm)
1259    Binary |= encodeVFPRn(MI, OpIdx++);
1260
1261  if (OpIdx == TID.getNumOperands() ||
1262      TID.OpInfo[OpIdx].isPredicate() ||
1263      TID.OpInfo[OpIdx].isOptionalDef()) {
1264    // FCMPEZD etc. has only one operand.
1265    emitWordLE(Binary);
1266    return;
1267  }
1268
1269  // Encode Dm / Sm.
1270  Binary |= encodeVFPRm(MI, OpIdx);
1271
1272  emitWordLE(Binary);
1273}
1274
1275template<class CodeEmitter>
1276void Emitter<CodeEmitter>::emitVFPConversionInstruction(
1277      const MachineInstr &MI) {
1278  const TargetInstrDesc &TID = MI.getDesc();
1279  unsigned Form = TID.TSFlags & ARMII::FormMask;
1280
1281  // Part of binary is determined by TableGn.
1282  unsigned Binary = getBinaryCodeForInstr(MI);
1283
1284  // Set the conditional execution predicate
1285  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1286
1287  switch (Form) {
1288  default: break;
1289  case ARMII::VFPConv1Frm:
1290  case ARMII::VFPConv2Frm:
1291  case ARMII::VFPConv3Frm:
1292    // Encode Dd / Sd.
1293    Binary |= encodeVFPRd(MI, 0);
1294    break;
1295  case ARMII::VFPConv4Frm:
1296    // Encode Dn / Sn.
1297    Binary |= encodeVFPRn(MI, 0);
1298    break;
1299  case ARMII::VFPConv5Frm:
1300    // Encode Dm / Sm.
1301    Binary |= encodeVFPRm(MI, 0);
1302    break;
1303  }
1304
1305  switch (Form) {
1306  default: break;
1307  case ARMII::VFPConv1Frm:
1308    // Encode Dm / Sm.
1309    Binary |= encodeVFPRm(MI, 1);
1310    break;
1311  case ARMII::VFPConv2Frm:
1312  case ARMII::VFPConv3Frm:
1313    // Encode Dn / Sn.
1314    Binary |= encodeVFPRn(MI, 1);
1315    break;
1316  case ARMII::VFPConv4Frm:
1317  case ARMII::VFPConv5Frm:
1318    // Encode Dd / Sd.
1319    Binary |= encodeVFPRd(MI, 1);
1320    break;
1321  }
1322
1323  if (Form == ARMII::VFPConv5Frm)
1324    // Encode Dn / Sn.
1325    Binary |= encodeVFPRn(MI, 2);
1326  else if (Form == ARMII::VFPConv3Frm)
1327    // Encode Dm / Sm.
1328    Binary |= encodeVFPRm(MI, 2);
1329
1330  emitWordLE(Binary);
1331}
1332
1333template<class CodeEmitter>
1334void Emitter<CodeEmitter>::emitVFPLoadStoreInstruction(const MachineInstr &MI) {
1335  // Part of binary is determined by TableGn.
1336  unsigned Binary = getBinaryCodeForInstr(MI);
1337
1338  // Set the conditional execution predicate
1339  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1340
1341  unsigned OpIdx = 0;
1342
1343  // Encode Dd / Sd.
1344  Binary |= encodeVFPRd(MI, OpIdx++);
1345
1346  // Encode address base.
1347  const MachineOperand &Base = MI.getOperand(OpIdx++);
1348  Binary |= getMachineOpValue(MI, Base) << ARMII::RegRnShift;
1349
1350  // If there is a non-zero immediate offset, encode it.
1351  if (Base.isReg()) {
1352    const MachineOperand &Offset = MI.getOperand(OpIdx);
1353    if (unsigned ImmOffs = ARM_AM::getAM5Offset(Offset.getImm())) {
1354      if (ARM_AM::getAM5Op(Offset.getImm()) == ARM_AM::add)
1355        Binary |= 1 << ARMII::U_BitShift;
1356      Binary |= ImmOffs;
1357      emitWordLE(Binary);
1358      return;
1359    }
1360  }
1361
1362  // If immediate offset is omitted, default to +0.
1363  Binary |= 1 << ARMII::U_BitShift;
1364
1365  emitWordLE(Binary);
1366}
1367
1368template<class CodeEmitter>
1369void Emitter<CodeEmitter>::emitVFPLoadStoreMultipleInstruction(
1370                                                       const MachineInstr &MI) {
1371  // Part of binary is determined by TableGn.
1372  unsigned Binary = getBinaryCodeForInstr(MI);
1373
1374  // Set the conditional execution predicate
1375  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1376
1377  // Set base address operand
1378  Binary |= getMachineOpValue(MI, 0) << ARMII::RegRnShift;
1379
1380  // Set addressing mode by modifying bits U(23) and P(24)
1381  const MachineOperand &MO = MI.getOperand(1);
1382  Binary |= getAddrModeUPBits(ARM_AM::getAM5SubMode(MO.getImm()));
1383
1384  // Set bit W(21)
1385  if (ARM_AM::getAM5WBFlag(MO.getImm()))
1386    Binary |= 0x1 << ARMII::W_BitShift;
1387
1388  // First register is encoded in Dd.
1389  Binary |= encodeVFPRd(MI, 4);
1390
1391  // Number of registers are encoded in offset field.
1392  unsigned NumRegs = 1;
1393  for (unsigned i = 5, e = MI.getNumOperands(); i != e; ++i) {
1394    const MachineOperand &MO = MI.getOperand(i);
1395    if (!MO.isReg() || MO.isImplicit())
1396      break;
1397    ++NumRegs;
1398  }
1399  Binary |= NumRegs * 2;
1400
1401  emitWordLE(Binary);
1402}
1403
1404template<class CodeEmitter>
1405void Emitter<CodeEmitter>::emitMiscInstruction(const MachineInstr &MI) {
1406  // Part of binary is determined by TableGn.
1407  unsigned Binary = getBinaryCodeForInstr(MI);
1408
1409  // Set the conditional execution predicate
1410  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1411
1412  emitWordLE(Binary);
1413}
1414
1415#include "ARMGenCodeEmitter.inc"
1416
1417