ARMCodeEmitter.cpp revision 1611273351d75b5cbe2a67485bb9831d5916fe26
1//===-- ARM/ARMCodeEmitter.cpp - Convert ARM code to machine code ---------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the pass that transforms the ARM machine instructions into 11// relocatable machine code. 12// 13//===----------------------------------------------------------------------===// 14 15#define DEBUG_TYPE "jit" 16#include "ARM.h" 17#include "ARMAddressingModes.h" 18#include "ARMConstantPoolValue.h" 19#include "ARMInstrInfo.h" 20#include "ARMRelocations.h" 21#include "ARMSubtarget.h" 22#include "ARMTargetMachine.h" 23#include "llvm/Constants.h" 24#include "llvm/DerivedTypes.h" 25#include "llvm/Function.h" 26#include "llvm/PassManager.h" 27#include "llvm/CodeGen/JITCodeEmitter.h" 28#include "llvm/CodeGen/MachineConstantPool.h" 29#include "llvm/CodeGen/MachineFunctionPass.h" 30#include "llvm/CodeGen/MachineInstr.h" 31#include "llvm/CodeGen/MachineJumpTableInfo.h" 32#include "llvm/CodeGen/MachineModuleInfo.h" 33#include "llvm/CodeGen/Passes.h" 34#include "llvm/ADT/Statistic.h" 35#include "llvm/Support/Debug.h" 36#include "llvm/Support/ErrorHandling.h" 37#include "llvm/Support/raw_ostream.h" 38#ifndef NDEBUG 39#include <iomanip> 40#endif 41using namespace llvm; 42 43STATISTIC(NumEmitted, "Number of machine instructions emitted"); 44 45namespace { 46 47 class ARMCodeEmitter : public MachineFunctionPass { 48 ARMJITInfo *JTI; 49 const ARMInstrInfo *II; 50 const TargetData *TD; 51 const ARMSubtarget *Subtarget; 52 TargetMachine &TM; 53 JITCodeEmitter &MCE; 54 MachineModuleInfo *MMI; 55 const std::vector<MachineConstantPoolEntry> *MCPEs; 56 const std::vector<MachineJumpTableEntry> *MJTEs; 57 bool IsPIC; 58 59 void getAnalysisUsage(AnalysisUsage &AU) const { 60 AU.addRequired<MachineModuleInfo>(); 61 MachineFunctionPass::getAnalysisUsage(AU); 62 } 63 64 static char ID; 65 public: 66 ARMCodeEmitter(TargetMachine &tm, JITCodeEmitter &mce) 67 : MachineFunctionPass(&ID), JTI(0), II((ARMInstrInfo*)tm.getInstrInfo()), 68 TD(tm.getTargetData()), TM(tm), 69 MCE(mce), MCPEs(0), MJTEs(0), 70 IsPIC(TM.getRelocationModel() == Reloc::PIC_) {} 71 72 /// getBinaryCodeForInstr - This function, generated by the 73 /// CodeEmitterGenerator using TableGen, produces the binary encoding for 74 /// machine instructions. 75 unsigned getBinaryCodeForInstr(const MachineInstr &MI); 76 77 bool runOnMachineFunction(MachineFunction &MF); 78 79 virtual const char *getPassName() const { 80 return "ARM Machine Code Emitter"; 81 } 82 83 void emitInstruction(const MachineInstr &MI); 84 85 private: 86 87 void emitWordLE(unsigned Binary); 88 void emitDWordLE(uint64_t Binary); 89 void emitConstPoolInstruction(const MachineInstr &MI); 90 void emitMOVi2piecesInstruction(const MachineInstr &MI); 91 void emitLEApcrelJTInstruction(const MachineInstr &MI); 92 void emitPseudoMoveInstruction(const MachineInstr &MI); 93 void addPCLabel(unsigned LabelID); 94 void emitPseudoInstruction(const MachineInstr &MI); 95 unsigned getMachineSoRegOpValue(const MachineInstr &MI, 96 const TargetInstrDesc &TID, 97 const MachineOperand &MO, 98 unsigned OpIdx); 99 100 unsigned getMachineSoImmOpValue(unsigned SoImm); 101 102 unsigned getAddrModeSBit(const MachineInstr &MI, 103 const TargetInstrDesc &TID) const; 104 105 void emitDataProcessingInstruction(const MachineInstr &MI, 106 unsigned ImplicitRd = 0, 107 unsigned ImplicitRn = 0); 108 109 void emitLoadStoreInstruction(const MachineInstr &MI, 110 unsigned ImplicitRd = 0, 111 unsigned ImplicitRn = 0); 112 113 void emitMiscLoadStoreInstruction(const MachineInstr &MI, 114 unsigned ImplicitRn = 0); 115 116 void emitLoadStoreMultipleInstruction(const MachineInstr &MI); 117 118 void emitMulFrmInstruction(const MachineInstr &MI); 119 120 void emitExtendInstruction(const MachineInstr &MI); 121 122 void emitMiscArithInstruction(const MachineInstr &MI); 123 124 void emitBranchInstruction(const MachineInstr &MI); 125 126 void emitInlineJumpTable(unsigned JTIndex); 127 128 void emitMiscBranchInstruction(const MachineInstr &MI); 129 130 void emitVFPArithInstruction(const MachineInstr &MI); 131 132 void emitVFPConversionInstruction(const MachineInstr &MI); 133 134 void emitVFPLoadStoreInstruction(const MachineInstr &MI); 135 136 void emitVFPLoadStoreMultipleInstruction(const MachineInstr &MI); 137 138 void emitMiscInstruction(const MachineInstr &MI); 139 140 /// getMachineOpValue - Return binary encoding of operand. If the machine 141 /// operand requires relocation, record the relocation and return zero. 142 unsigned getMachineOpValue(const MachineInstr &MI,const MachineOperand &MO); 143 unsigned getMachineOpValue(const MachineInstr &MI, unsigned OpIdx) { 144 return getMachineOpValue(MI, MI.getOperand(OpIdx)); 145 } 146 147 /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value. 148 /// 149 unsigned getShiftOp(unsigned Imm) const ; 150 151 /// Routines that handle operands which add machine relocations which are 152 /// fixed up by the relocation stage. 153 void emitGlobalAddress(GlobalValue *GV, unsigned Reloc, 154 bool MayNeedFarStub, bool Indirect, 155 intptr_t ACPV = 0); 156 void emitExternalSymbolAddress(const char *ES, unsigned Reloc); 157 void emitConstPoolAddress(unsigned CPI, unsigned Reloc); 158 void emitJumpTableAddress(unsigned JTIndex, unsigned Reloc); 159 void emitMachineBasicBlock(MachineBasicBlock *BB, unsigned Reloc, 160 intptr_t JTBase = 0); 161 }; 162} 163 164char ARMCodeEmitter::ID = 0; 165 166/// createARMJITCodeEmitterPass - Return a pass that emits the collected ARM 167/// code to the specified MCE object. 168FunctionPass *llvm::createARMJITCodeEmitterPass(ARMBaseTargetMachine &TM, 169 JITCodeEmitter &JCE) { 170 return new ARMCodeEmitter(TM, JCE); 171} 172 173bool ARMCodeEmitter::runOnMachineFunction(MachineFunction &MF) { 174 assert((MF.getTarget().getRelocationModel() != Reloc::Default || 175 MF.getTarget().getRelocationModel() != Reloc::Static) && 176 "JIT relocation model must be set to static or default!"); 177 JTI = ((ARMTargetMachine&)MF.getTarget()).getJITInfo(); 178 II = ((ARMTargetMachine&)MF.getTarget()).getInstrInfo(); 179 TD = ((ARMTargetMachine&)MF.getTarget()).getTargetData(); 180 Subtarget = &TM.getSubtarget<ARMSubtarget>(); 181 MCPEs = &MF.getConstantPool()->getConstants(); 182 MJTEs = 0; 183 if (MF.getJumpTableInfo()) MJTEs = &MF.getJumpTableInfo()->getJumpTables(); 184 IsPIC = TM.getRelocationModel() == Reloc::PIC_; 185 JTI->Initialize(MF, IsPIC); 186 MMI = &getAnalysis<MachineModuleInfo>(); 187 MCE.setModuleInfo(MMI); 188 189 do { 190 DEBUG(errs() << "JITTing function '" 191 << MF.getFunction()->getName() << "'\n"); 192 MCE.startFunction(MF); 193 for (MachineFunction::iterator MBB = MF.begin(), E = MF.end(); 194 MBB != E; ++MBB) { 195 MCE.StartMachineBasicBlock(MBB); 196 for (MachineBasicBlock::const_iterator I = MBB->begin(), E = MBB->end(); 197 I != E; ++I) 198 emitInstruction(*I); 199 } 200 } while (MCE.finishFunction(MF)); 201 202 return false; 203} 204 205/// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value. 206/// 207unsigned ARMCodeEmitter::getShiftOp(unsigned Imm) const { 208 switch (ARM_AM::getAM2ShiftOpc(Imm)) { 209 default: llvm_unreachable("Unknown shift opc!"); 210 case ARM_AM::asr: return 2; 211 case ARM_AM::lsl: return 0; 212 case ARM_AM::lsr: return 1; 213 case ARM_AM::ror: 214 case ARM_AM::rrx: return 3; 215 } 216 return 0; 217} 218 219/// getMachineOpValue - Return binary encoding of operand. If the machine 220/// operand requires relocation, record the relocation and return zero. 221unsigned ARMCodeEmitter::getMachineOpValue(const MachineInstr &MI, 222 const MachineOperand &MO) { 223 if (MO.isReg()) 224 return ARMRegisterInfo::getRegisterNumbering(MO.getReg()); 225 else if (MO.isImm()) 226 return static_cast<unsigned>(MO.getImm()); 227 else if (MO.isGlobal()) 228 emitGlobalAddress(MO.getGlobal(), ARM::reloc_arm_branch, true, false); 229 else if (MO.isSymbol()) 230 emitExternalSymbolAddress(MO.getSymbolName(), ARM::reloc_arm_branch); 231 else if (MO.isCPI()) { 232 const TargetInstrDesc &TID = MI.getDesc(); 233 // For VFP load, the immediate offset is multiplied by 4. 234 unsigned Reloc = ((TID.TSFlags & ARMII::FormMask) == ARMII::VFPLdStFrm) 235 ? ARM::reloc_arm_vfp_cp_entry : ARM::reloc_arm_cp_entry; 236 emitConstPoolAddress(MO.getIndex(), Reloc); 237 } else if (MO.isJTI()) 238 emitJumpTableAddress(MO.getIndex(), ARM::reloc_arm_relative); 239 else if (MO.isMBB()) 240 emitMachineBasicBlock(MO.getMBB(), ARM::reloc_arm_branch); 241 else { 242#ifndef NDEBUG 243 errs() << MO; 244#endif 245 llvm_unreachable(0); 246 } 247 return 0; 248} 249 250/// emitGlobalAddress - Emit the specified address to the code stream. 251/// 252void ARMCodeEmitter::emitGlobalAddress(GlobalValue *GV, unsigned Reloc, 253 bool MayNeedFarStub, bool Indirect, 254 intptr_t ACPV) { 255 MachineRelocation MR = Indirect 256 ? MachineRelocation::getIndirectSymbol(MCE.getCurrentPCOffset(), Reloc, 257 GV, ACPV, MayNeedFarStub) 258 : MachineRelocation::getGV(MCE.getCurrentPCOffset(), Reloc, 259 GV, ACPV, MayNeedFarStub); 260 MCE.addRelocation(MR); 261} 262 263/// emitExternalSymbolAddress - Arrange for the address of an external symbol to 264/// be emitted to the current location in the function, and allow it to be PC 265/// relative. 266void ARMCodeEmitter::emitExternalSymbolAddress(const char *ES, unsigned Reloc) { 267 MCE.addRelocation(MachineRelocation::getExtSym(MCE.getCurrentPCOffset(), 268 Reloc, ES)); 269} 270 271/// emitConstPoolAddress - Arrange for the address of an constant pool 272/// to be emitted to the current location in the function, and allow it to be PC 273/// relative. 274void ARMCodeEmitter::emitConstPoolAddress(unsigned CPI, unsigned Reloc) { 275 // Tell JIT emitter we'll resolve the address. 276 MCE.addRelocation(MachineRelocation::getConstPool(MCE.getCurrentPCOffset(), 277 Reloc, CPI, 0, true)); 278} 279 280/// emitJumpTableAddress - Arrange for the address of a jump table to 281/// be emitted to the current location in the function, and allow it to be PC 282/// relative. 283void ARMCodeEmitter::emitJumpTableAddress(unsigned JTIndex, unsigned Reloc) { 284 MCE.addRelocation(MachineRelocation::getJumpTable(MCE.getCurrentPCOffset(), 285 Reloc, JTIndex, 0, true)); 286} 287 288/// emitMachineBasicBlock - Emit the specified address basic block. 289void ARMCodeEmitter::emitMachineBasicBlock(MachineBasicBlock *BB, 290 unsigned Reloc, intptr_t JTBase) { 291 MCE.addRelocation(MachineRelocation::getBB(MCE.getCurrentPCOffset(), 292 Reloc, BB, JTBase)); 293} 294 295void ARMCodeEmitter::emitWordLE(unsigned Binary) { 296 DEBUG(errs() << " 0x"; 297 errs().write_hex(Binary) << "\n"); 298 MCE.emitWordLE(Binary); 299} 300 301void ARMCodeEmitter::emitDWordLE(uint64_t Binary) { 302 DEBUG(errs() << " 0x"; 303 errs().write_hex(Binary) << "\n"); 304 MCE.emitDWordLE(Binary); 305} 306 307void ARMCodeEmitter::emitInstruction(const MachineInstr &MI) { 308 DEBUG(errs() << "JIT: " << (void*)MCE.getCurrentPCValue() << ":\t" << MI); 309 310 MCE.processDebugLoc(MI.getDebugLoc(), true); 311 312 NumEmitted++; // Keep track of the # of mi's emitted 313 switch (MI.getDesc().TSFlags & ARMII::FormMask) { 314 default: { 315 llvm_unreachable("Unhandled instruction encoding format!"); 316 break; 317 } 318 case ARMII::Pseudo: 319 emitPseudoInstruction(MI); 320 break; 321 case ARMII::DPFrm: 322 case ARMII::DPSoRegFrm: 323 emitDataProcessingInstruction(MI); 324 break; 325 case ARMII::LdFrm: 326 case ARMII::StFrm: 327 emitLoadStoreInstruction(MI); 328 break; 329 case ARMII::LdMiscFrm: 330 case ARMII::StMiscFrm: 331 emitMiscLoadStoreInstruction(MI); 332 break; 333 case ARMII::LdStMulFrm: 334 emitLoadStoreMultipleInstruction(MI); 335 break; 336 case ARMII::MulFrm: 337 emitMulFrmInstruction(MI); 338 break; 339 case ARMII::ExtFrm: 340 emitExtendInstruction(MI); 341 break; 342 case ARMII::ArithMiscFrm: 343 emitMiscArithInstruction(MI); 344 break; 345 case ARMII::BrFrm: 346 emitBranchInstruction(MI); 347 break; 348 case ARMII::BrMiscFrm: 349 emitMiscBranchInstruction(MI); 350 break; 351 // VFP instructions. 352 case ARMII::VFPUnaryFrm: 353 case ARMII::VFPBinaryFrm: 354 emitVFPArithInstruction(MI); 355 break; 356 case ARMII::VFPConv1Frm: 357 case ARMII::VFPConv2Frm: 358 case ARMII::VFPConv3Frm: 359 case ARMII::VFPConv4Frm: 360 case ARMII::VFPConv5Frm: 361 emitVFPConversionInstruction(MI); 362 break; 363 case ARMII::VFPLdStFrm: 364 emitVFPLoadStoreInstruction(MI); 365 break; 366 case ARMII::VFPLdStMulFrm: 367 emitVFPLoadStoreMultipleInstruction(MI); 368 break; 369 case ARMII::VFPMiscFrm: 370 emitMiscInstruction(MI); 371 break; 372 } 373 MCE.processDebugLoc(MI.getDebugLoc(), false); 374} 375 376void ARMCodeEmitter::emitConstPoolInstruction(const MachineInstr &MI) { 377 unsigned CPI = MI.getOperand(0).getImm(); // CP instruction index. 378 unsigned CPIndex = MI.getOperand(1).getIndex(); // Actual cp entry index. 379 const MachineConstantPoolEntry &MCPE = (*MCPEs)[CPIndex]; 380 381 // Remember the CONSTPOOL_ENTRY address for later relocation. 382 JTI->addConstantPoolEntryAddr(CPI, MCE.getCurrentPCValue()); 383 384 // Emit constpool island entry. In most cases, the actual values will be 385 // resolved and relocated after code emission. 386 if (MCPE.isMachineConstantPoolEntry()) { 387 ARMConstantPoolValue *ACPV = 388 static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal); 389 390 DEBUG(errs() << " ** ARM constant pool #" << CPI << " @ " 391 << (void*)MCE.getCurrentPCValue() << " " << *ACPV << '\n'); 392 393 assert(ACPV->isGlobalValue() && "unsupported constant pool value"); 394 GlobalValue *GV = ACPV->getGV(); 395 if (GV) { 396 Reloc::Model RelocM = TM.getRelocationModel(); 397 emitGlobalAddress(GV, ARM::reloc_arm_machine_cp_entry, 398 isa<Function>(GV), 399 Subtarget->GVIsIndirectSymbol(GV, RelocM), 400 (intptr_t)ACPV); 401 } else { 402 emitExternalSymbolAddress(ACPV->getSymbol(), ARM::reloc_arm_absolute); 403 } 404 emitWordLE(0); 405 } else { 406 Constant *CV = MCPE.Val.ConstVal; 407 408 DEBUG({ 409 errs() << " ** Constant pool #" << CPI << " @ " 410 << (void*)MCE.getCurrentPCValue() << " "; 411 if (const Function *F = dyn_cast<Function>(CV)) 412 errs() << F->getName(); 413 else 414 errs() << *CV; 415 errs() << '\n'; 416 }); 417 418 if (GlobalValue *GV = dyn_cast<GlobalValue>(CV)) { 419 emitGlobalAddress(GV, ARM::reloc_arm_absolute, isa<Function>(GV), false); 420 emitWordLE(0); 421 } else if (const ConstantInt *CI = dyn_cast<ConstantInt>(CV)) { 422 uint32_t Val = *(uint32_t*)CI->getValue().getRawData(); 423 emitWordLE(Val); 424 } else if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CV)) { 425 if (CFP->getType()->isFloatTy()) 426 emitWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue()); 427 else if (CFP->getType()->isDoubleTy()) 428 emitDWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue()); 429 else { 430 llvm_unreachable("Unable to handle this constantpool entry!"); 431 } 432 } else { 433 llvm_unreachable("Unable to handle this constantpool entry!"); 434 } 435 } 436} 437 438void ARMCodeEmitter::emitMOVi2piecesInstruction(const MachineInstr &MI) { 439 const MachineOperand &MO0 = MI.getOperand(0); 440 const MachineOperand &MO1 = MI.getOperand(1); 441 assert(MO1.isImm() && ARM_AM::isSOImmTwoPartVal(MO1.getImm()) && 442 "Not a valid so_imm value!"); 443 unsigned V1 = ARM_AM::getSOImmTwoPartFirst(MO1.getImm()); 444 unsigned V2 = ARM_AM::getSOImmTwoPartSecond(MO1.getImm()); 445 446 // Emit the 'mov' instruction. 447 unsigned Binary = 0xd << 21; // mov: Insts{24-21} = 0b1101 448 449 // Set the conditional execution predicate. 450 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 451 452 // Encode Rd. 453 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift; 454 455 // Encode so_imm. 456 // Set bit I(25) to identify this is the immediate form of <shifter_op> 457 Binary |= 1 << ARMII::I_BitShift; 458 Binary |= getMachineSoImmOpValue(V1); 459 emitWordLE(Binary); 460 461 // Now the 'orr' instruction. 462 Binary = 0xc << 21; // orr: Insts{24-21} = 0b1100 463 464 // Set the conditional execution predicate. 465 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 466 467 // Encode Rd. 468 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift; 469 470 // Encode Rn. 471 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRnShift; 472 473 // Encode so_imm. 474 // Set bit I(25) to identify this is the immediate form of <shifter_op> 475 Binary |= 1 << ARMII::I_BitShift; 476 Binary |= getMachineSoImmOpValue(V2); 477 emitWordLE(Binary); 478} 479 480void ARMCodeEmitter::emitLEApcrelJTInstruction(const MachineInstr &MI) { 481 // It's basically add r, pc, (LJTI - $+8) 482 483 const TargetInstrDesc &TID = MI.getDesc(); 484 485 // Emit the 'add' instruction. 486 unsigned Binary = 0x4 << 21; // add: Insts{24-31} = 0b0100 487 488 // Set the conditional execution predicate 489 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 490 491 // Encode S bit if MI modifies CPSR. 492 Binary |= getAddrModeSBit(MI, TID); 493 494 // Encode Rd. 495 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift; 496 497 // Encode Rn which is PC. 498 Binary |= ARMRegisterInfo::getRegisterNumbering(ARM::PC) << ARMII::RegRnShift; 499 500 // Encode the displacement. 501 Binary |= 1 << ARMII::I_BitShift; 502 emitJumpTableAddress(MI.getOperand(1).getIndex(), ARM::reloc_arm_jt_base); 503 504 emitWordLE(Binary); 505} 506 507void ARMCodeEmitter::emitPseudoMoveInstruction(const MachineInstr &MI) { 508 unsigned Opcode = MI.getDesc().Opcode; 509 510 // Part of binary is determined by TableGn. 511 unsigned Binary = getBinaryCodeForInstr(MI); 512 513 // Set the conditional execution predicate 514 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 515 516 // Encode S bit if MI modifies CPSR. 517 if (Opcode == ARM::MOVsrl_flag || Opcode == ARM::MOVsra_flag) 518 Binary |= 1 << ARMII::S_BitShift; 519 520 // Encode register def if there is one. 521 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift; 522 523 // Encode the shift operation. 524 switch (Opcode) { 525 default: break; 526 case ARM::MOVrx: 527 // rrx 528 Binary |= 0x6 << 4; 529 break; 530 case ARM::MOVsrl_flag: 531 // lsr #1 532 Binary |= (0x2 << 4) | (1 << 7); 533 break; 534 case ARM::MOVsra_flag: 535 // asr #1 536 Binary |= (0x4 << 4) | (1 << 7); 537 break; 538 } 539 540 // Encode register Rm. 541 Binary |= getMachineOpValue(MI, 1); 542 543 emitWordLE(Binary); 544} 545 546void ARMCodeEmitter::addPCLabel(unsigned LabelID) { 547 DEBUG(errs() << " ** LPC" << LabelID << " @ " 548 << (void*)MCE.getCurrentPCValue() << '\n'); 549 JTI->addPCLabelAddr(LabelID, MCE.getCurrentPCValue()); 550} 551 552void ARMCodeEmitter::emitPseudoInstruction(const MachineInstr &MI) { 553 unsigned Opcode = MI.getDesc().Opcode; 554 switch (Opcode) { 555 default: 556 llvm_unreachable("ARMCodeEmitter::emitPseudoInstruction"); 557 // FIXME: Add support for MOVimm32. 558 case TargetOpcode::INLINEASM: { 559 // We allow inline assembler nodes with empty bodies - they can 560 // implicitly define registers, which is ok for JIT. 561 if (MI.getOperand(0).getSymbolName()[0]) { 562 llvm_report_error("JIT does not support inline asm!"); 563 } 564 break; 565 } 566 case TargetOpcode::DBG_LABEL: 567 case TargetOpcode::EH_LABEL: 568 MCE.emitLabel(MMI->getLabelSym(MI.getOperand(0).getImm())); 569 break; 570 case TargetOpcode::IMPLICIT_DEF: 571 case TargetOpcode::KILL: 572 // Do nothing. 573 break; 574 case ARM::CONSTPOOL_ENTRY: 575 emitConstPoolInstruction(MI); 576 break; 577 case ARM::PICADD: { 578 // Remember of the address of the PC label for relocation later. 579 addPCLabel(MI.getOperand(2).getImm()); 580 // PICADD is just an add instruction that implicitly read pc. 581 emitDataProcessingInstruction(MI, 0, ARM::PC); 582 break; 583 } 584 case ARM::PICLDR: 585 case ARM::PICLDRB: 586 case ARM::PICSTR: 587 case ARM::PICSTRB: { 588 // Remember of the address of the PC label for relocation later. 589 addPCLabel(MI.getOperand(2).getImm()); 590 // These are just load / store instructions that implicitly read pc. 591 emitLoadStoreInstruction(MI, 0, ARM::PC); 592 break; 593 } 594 case ARM::PICLDRH: 595 case ARM::PICLDRSH: 596 case ARM::PICLDRSB: 597 case ARM::PICSTRH: { 598 // Remember of the address of the PC label for relocation later. 599 addPCLabel(MI.getOperand(2).getImm()); 600 // These are just load / store instructions that implicitly read pc. 601 emitMiscLoadStoreInstruction(MI, ARM::PC); 602 break; 603 } 604 case ARM::MOVi2pieces: 605 // Two instructions to materialize a constant. 606 emitMOVi2piecesInstruction(MI); 607 break; 608 case ARM::LEApcrelJT: 609 // Materialize jumptable address. 610 emitLEApcrelJTInstruction(MI); 611 break; 612 case ARM::MOVrx: 613 case ARM::MOVsrl_flag: 614 case ARM::MOVsra_flag: 615 emitPseudoMoveInstruction(MI); 616 break; 617 } 618} 619 620unsigned ARMCodeEmitter::getMachineSoRegOpValue( 621 const MachineInstr &MI, 622 const TargetInstrDesc &TID, 623 const MachineOperand &MO, 624 unsigned OpIdx) { 625 unsigned Binary = getMachineOpValue(MI, MO); 626 627 const MachineOperand &MO1 = MI.getOperand(OpIdx + 1); 628 const MachineOperand &MO2 = MI.getOperand(OpIdx + 2); 629 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm()); 630 631 // Encode the shift opcode. 632 unsigned SBits = 0; 633 unsigned Rs = MO1.getReg(); 634 if (Rs) { 635 // Set shift operand (bit[7:4]). 636 // LSL - 0001 637 // LSR - 0011 638 // ASR - 0101 639 // ROR - 0111 640 // RRX - 0110 and bit[11:8] clear. 641 switch (SOpc) { 642 default: llvm_unreachable("Unknown shift opc!"); 643 case ARM_AM::lsl: SBits = 0x1; break; 644 case ARM_AM::lsr: SBits = 0x3; break; 645 case ARM_AM::asr: SBits = 0x5; break; 646 case ARM_AM::ror: SBits = 0x7; break; 647 case ARM_AM::rrx: SBits = 0x6; break; 648 } 649 } else { 650 // Set shift operand (bit[6:4]). 651 // LSL - 000 652 // LSR - 010 653 // ASR - 100 654 // ROR - 110 655 switch (SOpc) { 656 default: llvm_unreachable("Unknown shift opc!"); 657 case ARM_AM::lsl: SBits = 0x0; break; 658 case ARM_AM::lsr: SBits = 0x2; break; 659 case ARM_AM::asr: SBits = 0x4; break; 660 case ARM_AM::ror: SBits = 0x6; break; 661 } 662 } 663 Binary |= SBits << 4; 664 if (SOpc == ARM_AM::rrx) 665 return Binary; 666 667 // Encode the shift operation Rs or shift_imm (except rrx). 668 if (Rs) { 669 // Encode Rs bit[11:8]. 670 assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0); 671 return Binary | 672 (ARMRegisterInfo::getRegisterNumbering(Rs) << ARMII::RegRsShift); 673 } 674 675 // Encode shift_imm bit[11:7]. 676 return Binary | ARM_AM::getSORegOffset(MO2.getImm()) << 7; 677} 678 679unsigned ARMCodeEmitter::getMachineSoImmOpValue(unsigned SoImm) { 680 int SoImmVal = ARM_AM::getSOImmVal(SoImm); 681 assert(SoImmVal != -1 && "Not a valid so_imm value!"); 682 683 // Encode rotate_imm. 684 unsigned Binary = (ARM_AM::getSOImmValRot((unsigned)SoImmVal) >> 1) 685 << ARMII::SoRotImmShift; 686 687 // Encode immed_8. 688 Binary |= ARM_AM::getSOImmValImm((unsigned)SoImmVal); 689 return Binary; 690} 691 692unsigned ARMCodeEmitter::getAddrModeSBit(const MachineInstr &MI, 693 const TargetInstrDesc &TID) const { 694 for (unsigned i = MI.getNumOperands(), e = TID.getNumOperands(); i != e; --i){ 695 const MachineOperand &MO = MI.getOperand(i-1); 696 if (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR) 697 return 1 << ARMII::S_BitShift; 698 } 699 return 0; 700} 701 702void ARMCodeEmitter::emitDataProcessingInstruction( 703 const MachineInstr &MI, 704 unsigned ImplicitRd, 705 unsigned ImplicitRn) { 706 const TargetInstrDesc &TID = MI.getDesc(); 707 708 if (TID.Opcode == ARM::BFC) { 709 llvm_report_error("ARMv6t2 JIT is not yet supported."); 710 } 711 712 // Part of binary is determined by TableGn. 713 unsigned Binary = getBinaryCodeForInstr(MI); 714 715 // Set the conditional execution predicate 716 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 717 718 // Encode S bit if MI modifies CPSR. 719 Binary |= getAddrModeSBit(MI, TID); 720 721 // Encode register def if there is one. 722 unsigned NumDefs = TID.getNumDefs(); 723 unsigned OpIdx = 0; 724 if (NumDefs) 725 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift; 726 else if (ImplicitRd) 727 // Special handling for implicit use (e.g. PC). 728 Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRd) 729 << ARMII::RegRdShift); 730 731 // If this is a two-address operand, skip it. e.g. MOVCCr operand 1. 732 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1) 733 ++OpIdx; 734 735 // Encode first non-shifter register operand if there is one. 736 bool isUnary = TID.TSFlags & ARMII::UnaryDP; 737 if (!isUnary) { 738 if (ImplicitRn) 739 // Special handling for implicit use (e.g. PC). 740 Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRn) 741 << ARMII::RegRnShift); 742 else { 743 Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRnShift; 744 ++OpIdx; 745 } 746 } 747 748 // Encode shifter operand. 749 const MachineOperand &MO = MI.getOperand(OpIdx); 750 if ((TID.TSFlags & ARMII::FormMask) == ARMII::DPSoRegFrm) { 751 // Encode SoReg. 752 emitWordLE(Binary | getMachineSoRegOpValue(MI, TID, MO, OpIdx)); 753 return; 754 } 755 756 if (MO.isReg()) { 757 // Encode register Rm. 758 emitWordLE(Binary | ARMRegisterInfo::getRegisterNumbering(MO.getReg())); 759 return; 760 } 761 762 // Encode so_imm. 763 Binary |= getMachineSoImmOpValue((unsigned)MO.getImm()); 764 765 emitWordLE(Binary); 766} 767 768void ARMCodeEmitter::emitLoadStoreInstruction( 769 const MachineInstr &MI, 770 unsigned ImplicitRd, 771 unsigned ImplicitRn) { 772 const TargetInstrDesc &TID = MI.getDesc(); 773 unsigned Form = TID.TSFlags & ARMII::FormMask; 774 bool IsPrePost = (TID.TSFlags & ARMII::IndexModeMask) != 0; 775 776 // Part of binary is determined by TableGn. 777 unsigned Binary = getBinaryCodeForInstr(MI); 778 779 // Set the conditional execution predicate 780 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 781 782 unsigned OpIdx = 0; 783 784 // Operand 0 of a pre- and post-indexed store is the address base 785 // writeback. Skip it. 786 bool Skipped = false; 787 if (IsPrePost && Form == ARMII::StFrm) { 788 ++OpIdx; 789 Skipped = true; 790 } 791 792 // Set first operand 793 if (ImplicitRd) 794 // Special handling for implicit use (e.g. PC). 795 Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRd) 796 << ARMII::RegRdShift); 797 else 798 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift; 799 800 // Set second operand 801 if (ImplicitRn) 802 // Special handling for implicit use (e.g. PC). 803 Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRn) 804 << ARMII::RegRnShift); 805 else 806 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift; 807 808 // If this is a two-address operand, skip it. e.g. LDR_PRE. 809 if (!Skipped && TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1) 810 ++OpIdx; 811 812 const MachineOperand &MO2 = MI.getOperand(OpIdx); 813 unsigned AM2Opc = (ImplicitRn == ARM::PC) 814 ? 0 : MI.getOperand(OpIdx+1).getImm(); 815 816 // Set bit U(23) according to sign of immed value (positive or negative). 817 Binary |= ((ARM_AM::getAM2Op(AM2Opc) == ARM_AM::add ? 1 : 0) << 818 ARMII::U_BitShift); 819 if (!MO2.getReg()) { // is immediate 820 if (ARM_AM::getAM2Offset(AM2Opc)) 821 // Set the value of offset_12 field 822 Binary |= ARM_AM::getAM2Offset(AM2Opc); 823 emitWordLE(Binary); 824 return; 825 } 826 827 // Set bit I(25), because this is not in immediate enconding. 828 Binary |= 1 << ARMII::I_BitShift; 829 assert(TargetRegisterInfo::isPhysicalRegister(MO2.getReg())); 830 // Set bit[3:0] to the corresponding Rm register 831 Binary |= ARMRegisterInfo::getRegisterNumbering(MO2.getReg()); 832 833 // If this instr is in scaled register offset/index instruction, set 834 // shift_immed(bit[11:7]) and shift(bit[6:5]) fields. 835 if (unsigned ShImm = ARM_AM::getAM2Offset(AM2Opc)) { 836 Binary |= getShiftOp(AM2Opc) << ARMII::ShiftImmShift; // shift 837 Binary |= ShImm << ARMII::ShiftShift; // shift_immed 838 } 839 840 emitWordLE(Binary); 841} 842 843void ARMCodeEmitter::emitMiscLoadStoreInstruction(const MachineInstr &MI, 844 unsigned ImplicitRn) { 845 const TargetInstrDesc &TID = MI.getDesc(); 846 unsigned Form = TID.TSFlags & ARMII::FormMask; 847 bool IsPrePost = (TID.TSFlags & ARMII::IndexModeMask) != 0; 848 849 // Part of binary is determined by TableGn. 850 unsigned Binary = getBinaryCodeForInstr(MI); 851 852 // Set the conditional execution predicate 853 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 854 855 unsigned OpIdx = 0; 856 857 // Operand 0 of a pre- and post-indexed store is the address base 858 // writeback. Skip it. 859 bool Skipped = false; 860 if (IsPrePost && Form == ARMII::StMiscFrm) { 861 ++OpIdx; 862 Skipped = true; 863 } 864 865 // Set first operand 866 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift; 867 868 // Skip LDRD and STRD's second operand. 869 if (TID.Opcode == ARM::LDRD || TID.Opcode == ARM::STRD) 870 ++OpIdx; 871 872 // Set second operand 873 if (ImplicitRn) 874 // Special handling for implicit use (e.g. PC). 875 Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRn) 876 << ARMII::RegRnShift); 877 else 878 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift; 879 880 // If this is a two-address operand, skip it. e.g. LDRH_POST. 881 if (!Skipped && TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1) 882 ++OpIdx; 883 884 const MachineOperand &MO2 = MI.getOperand(OpIdx); 885 unsigned AM3Opc = (ImplicitRn == ARM::PC) 886 ? 0 : MI.getOperand(OpIdx+1).getImm(); 887 888 // Set bit U(23) according to sign of immed value (positive or negative) 889 Binary |= ((ARM_AM::getAM3Op(AM3Opc) == ARM_AM::add ? 1 : 0) << 890 ARMII::U_BitShift); 891 892 // If this instr is in register offset/index encoding, set bit[3:0] 893 // to the corresponding Rm register. 894 if (MO2.getReg()) { 895 Binary |= ARMRegisterInfo::getRegisterNumbering(MO2.getReg()); 896 emitWordLE(Binary); 897 return; 898 } 899 900 // This instr is in immediate offset/index encoding, set bit 22 to 1. 901 Binary |= 1 << ARMII::AM3_I_BitShift; 902 if (unsigned ImmOffs = ARM_AM::getAM3Offset(AM3Opc)) { 903 // Set operands 904 Binary |= (ImmOffs >> 4) << ARMII::ImmHiShift; // immedH 905 Binary |= (ImmOffs & 0xF); // immedL 906 } 907 908 emitWordLE(Binary); 909} 910 911static unsigned getAddrModeUPBits(unsigned Mode) { 912 unsigned Binary = 0; 913 914 // Set addressing mode by modifying bits U(23) and P(24) 915 // IA - Increment after - bit U = 1 and bit P = 0 916 // IB - Increment before - bit U = 1 and bit P = 1 917 // DA - Decrement after - bit U = 0 and bit P = 0 918 // DB - Decrement before - bit U = 0 and bit P = 1 919 switch (Mode) { 920 default: llvm_unreachable("Unknown addressing sub-mode!"); 921 case ARM_AM::da: break; 922 case ARM_AM::db: Binary |= 0x1 << ARMII::P_BitShift; break; 923 case ARM_AM::ia: Binary |= 0x1 << ARMII::U_BitShift; break; 924 case ARM_AM::ib: Binary |= 0x3 << ARMII::U_BitShift; break; 925 } 926 927 return Binary; 928} 929 930void ARMCodeEmitter::emitLoadStoreMultipleInstruction(const MachineInstr &MI) { 931 const TargetInstrDesc &TID = MI.getDesc(); 932 bool IsUpdating = (TID.TSFlags & ARMII::IndexModeMask) != 0; 933 934 // Part of binary is determined by TableGn. 935 unsigned Binary = getBinaryCodeForInstr(MI); 936 937 // Set the conditional execution predicate 938 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 939 940 // Skip operand 0 of an instruction with base register update. 941 unsigned OpIdx = 0; 942 if (IsUpdating) 943 ++OpIdx; 944 945 // Set base address operand 946 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift; 947 948 // Set addressing mode by modifying bits U(23) and P(24) 949 const MachineOperand &MO = MI.getOperand(OpIdx++); 950 Binary |= getAddrModeUPBits(ARM_AM::getAM4SubMode(MO.getImm())); 951 952 // Set bit W(21) 953 if (ARM_AM::getAM4WBFlag(MO.getImm())) 954 Binary |= 0x1 << ARMII::W_BitShift; 955 956 // Set registers 957 for (unsigned i = OpIdx+2, e = MI.getNumOperands(); i != e; ++i) { 958 const MachineOperand &MO = MI.getOperand(i); 959 if (!MO.isReg() || MO.isImplicit()) 960 break; 961 unsigned RegNum = ARMRegisterInfo::getRegisterNumbering(MO.getReg()); 962 assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()) && 963 RegNum < 16); 964 Binary |= 0x1 << RegNum; 965 } 966 967 emitWordLE(Binary); 968} 969 970void ARMCodeEmitter::emitMulFrmInstruction(const MachineInstr &MI) { 971 const TargetInstrDesc &TID = MI.getDesc(); 972 973 // Part of binary is determined by TableGn. 974 unsigned Binary = getBinaryCodeForInstr(MI); 975 976 // Set the conditional execution predicate 977 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 978 979 // Encode S bit if MI modifies CPSR. 980 Binary |= getAddrModeSBit(MI, TID); 981 982 // 32x32->64bit operations have two destination registers. The number 983 // of register definitions will tell us if that's what we're dealing with. 984 unsigned OpIdx = 0; 985 if (TID.getNumDefs() == 2) 986 Binary |= getMachineOpValue (MI, OpIdx++) << ARMII::RegRdLoShift; 987 988 // Encode Rd 989 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdHiShift; 990 991 // Encode Rm 992 Binary |= getMachineOpValue(MI, OpIdx++); 993 994 // Encode Rs 995 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRsShift; 996 997 // Many multiple instructions (e.g. MLA) have three src operands. Encode 998 // it as Rn (for multiply, that's in the same offset as RdLo. 999 if (TID.getNumOperands() > OpIdx && 1000 !TID.OpInfo[OpIdx].isPredicate() && 1001 !TID.OpInfo[OpIdx].isOptionalDef()) 1002 Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRdLoShift; 1003 1004 emitWordLE(Binary); 1005} 1006 1007void ARMCodeEmitter::emitExtendInstruction(const MachineInstr &MI) { 1008 const TargetInstrDesc &TID = MI.getDesc(); 1009 1010 // Part of binary is determined by TableGn. 1011 unsigned Binary = getBinaryCodeForInstr(MI); 1012 1013 // Set the conditional execution predicate 1014 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1015 1016 unsigned OpIdx = 0; 1017 1018 // Encode Rd 1019 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift; 1020 1021 const MachineOperand &MO1 = MI.getOperand(OpIdx++); 1022 const MachineOperand &MO2 = MI.getOperand(OpIdx); 1023 if (MO2.isReg()) { 1024 // Two register operand form. 1025 // Encode Rn. 1026 Binary |= getMachineOpValue(MI, MO1) << ARMII::RegRnShift; 1027 1028 // Encode Rm. 1029 Binary |= getMachineOpValue(MI, MO2); 1030 ++OpIdx; 1031 } else { 1032 Binary |= getMachineOpValue(MI, MO1); 1033 } 1034 1035 // Encode rot imm (0, 8, 16, or 24) if it has a rotate immediate operand. 1036 if (MI.getOperand(OpIdx).isImm() && 1037 !TID.OpInfo[OpIdx].isPredicate() && 1038 !TID.OpInfo[OpIdx].isOptionalDef()) 1039 Binary |= (getMachineOpValue(MI, OpIdx) / 8) << ARMII::ExtRotImmShift; 1040 1041 emitWordLE(Binary); 1042} 1043 1044void ARMCodeEmitter::emitMiscArithInstruction(const MachineInstr &MI) { 1045 const TargetInstrDesc &TID = MI.getDesc(); 1046 1047 // Part of binary is determined by TableGn. 1048 unsigned Binary = getBinaryCodeForInstr(MI); 1049 1050 // Set the conditional execution predicate 1051 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1052 1053 unsigned OpIdx = 0; 1054 1055 // Encode Rd 1056 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift; 1057 1058 const MachineOperand &MO = MI.getOperand(OpIdx++); 1059 if (OpIdx == TID.getNumOperands() || 1060 TID.OpInfo[OpIdx].isPredicate() || 1061 TID.OpInfo[OpIdx].isOptionalDef()) { 1062 // Encode Rm and it's done. 1063 Binary |= getMachineOpValue(MI, MO); 1064 emitWordLE(Binary); 1065 return; 1066 } 1067 1068 // Encode Rn. 1069 Binary |= getMachineOpValue(MI, MO) << ARMII::RegRnShift; 1070 1071 // Encode Rm. 1072 Binary |= getMachineOpValue(MI, OpIdx++); 1073 1074 // Encode shift_imm. 1075 unsigned ShiftAmt = MI.getOperand(OpIdx).getImm(); 1076 assert(ShiftAmt < 32 && "shift_imm range is 0 to 31!"); 1077 Binary |= ShiftAmt << ARMII::ShiftShift; 1078 1079 emitWordLE(Binary); 1080} 1081 1082void ARMCodeEmitter::emitBranchInstruction(const MachineInstr &MI) { 1083 const TargetInstrDesc &TID = MI.getDesc(); 1084 1085 if (TID.Opcode == ARM::TPsoft) { 1086 llvm_unreachable("ARM::TPsoft FIXME"); // FIXME 1087 } 1088 1089 // Part of binary is determined by TableGn. 1090 unsigned Binary = getBinaryCodeForInstr(MI); 1091 1092 // Set the conditional execution predicate 1093 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1094 1095 // Set signed_immed_24 field 1096 Binary |= getMachineOpValue(MI, 0); 1097 1098 emitWordLE(Binary); 1099} 1100 1101void ARMCodeEmitter::emitInlineJumpTable(unsigned JTIndex) { 1102 // Remember the base address of the inline jump table. 1103 uintptr_t JTBase = MCE.getCurrentPCValue(); 1104 JTI->addJumpTableBaseAddr(JTIndex, JTBase); 1105 DEBUG(errs() << " ** Jump Table #" << JTIndex << " @ " << (void*)JTBase 1106 << '\n'); 1107 1108 // Now emit the jump table entries. 1109 const std::vector<MachineBasicBlock*> &MBBs = (*MJTEs)[JTIndex].MBBs; 1110 for (unsigned i = 0, e = MBBs.size(); i != e; ++i) { 1111 if (IsPIC) 1112 // DestBB address - JT base. 1113 emitMachineBasicBlock(MBBs[i], ARM::reloc_arm_pic_jt, JTBase); 1114 else 1115 // Absolute DestBB address. 1116 emitMachineBasicBlock(MBBs[i], ARM::reloc_arm_absolute); 1117 emitWordLE(0); 1118 } 1119} 1120 1121void ARMCodeEmitter::emitMiscBranchInstruction(const MachineInstr &MI) { 1122 const TargetInstrDesc &TID = MI.getDesc(); 1123 1124 // Handle jump tables. 1125 if (TID.Opcode == ARM::BR_JTr || TID.Opcode == ARM::BR_JTadd) { 1126 // First emit a ldr pc, [] instruction. 1127 emitDataProcessingInstruction(MI, ARM::PC); 1128 1129 // Then emit the inline jump table. 1130 unsigned JTIndex = 1131 (TID.Opcode == ARM::BR_JTr) 1132 ? MI.getOperand(1).getIndex() : MI.getOperand(2).getIndex(); 1133 emitInlineJumpTable(JTIndex); 1134 return; 1135 } else if (TID.Opcode == ARM::BR_JTm) { 1136 // First emit a ldr pc, [] instruction. 1137 emitLoadStoreInstruction(MI, ARM::PC); 1138 1139 // Then emit the inline jump table. 1140 emitInlineJumpTable(MI.getOperand(3).getIndex()); 1141 return; 1142 } 1143 1144 // Part of binary is determined by TableGn. 1145 unsigned Binary = getBinaryCodeForInstr(MI); 1146 1147 // Set the conditional execution predicate 1148 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1149 1150 if (TID.Opcode == ARM::BX_RET || TID.Opcode == ARM::MOVPCLR) 1151 // The return register is LR. 1152 Binary |= ARMRegisterInfo::getRegisterNumbering(ARM::LR); 1153 else 1154 // otherwise, set the return register 1155 Binary |= getMachineOpValue(MI, 0); 1156 1157 emitWordLE(Binary); 1158} 1159 1160static unsigned encodeVFPRd(const MachineInstr &MI, unsigned OpIdx) { 1161 unsigned RegD = MI.getOperand(OpIdx).getReg(); 1162 unsigned Binary = 0; 1163 bool isSPVFP = false; 1164 RegD = ARMRegisterInfo::getRegisterNumbering(RegD, &isSPVFP); 1165 if (!isSPVFP) 1166 Binary |= RegD << ARMII::RegRdShift; 1167 else { 1168 Binary |= ((RegD & 0x1E) >> 1) << ARMII::RegRdShift; 1169 Binary |= (RegD & 0x01) << ARMII::D_BitShift; 1170 } 1171 return Binary; 1172} 1173 1174static unsigned encodeVFPRn(const MachineInstr &MI, unsigned OpIdx) { 1175 unsigned RegN = MI.getOperand(OpIdx).getReg(); 1176 unsigned Binary = 0; 1177 bool isSPVFP = false; 1178 RegN = ARMRegisterInfo::getRegisterNumbering(RegN, &isSPVFP); 1179 if (!isSPVFP) 1180 Binary |= RegN << ARMII::RegRnShift; 1181 else { 1182 Binary |= ((RegN & 0x1E) >> 1) << ARMII::RegRnShift; 1183 Binary |= (RegN & 0x01) << ARMII::N_BitShift; 1184 } 1185 return Binary; 1186} 1187 1188static unsigned encodeVFPRm(const MachineInstr &MI, unsigned OpIdx) { 1189 unsigned RegM = MI.getOperand(OpIdx).getReg(); 1190 unsigned Binary = 0; 1191 bool isSPVFP = false; 1192 RegM = ARMRegisterInfo::getRegisterNumbering(RegM, &isSPVFP); 1193 if (!isSPVFP) 1194 Binary |= RegM; 1195 else { 1196 Binary |= ((RegM & 0x1E) >> 1); 1197 Binary |= (RegM & 0x01) << ARMII::M_BitShift; 1198 } 1199 return Binary; 1200} 1201 1202void ARMCodeEmitter::emitVFPArithInstruction(const MachineInstr &MI) { 1203 const TargetInstrDesc &TID = MI.getDesc(); 1204 1205 // Part of binary is determined by TableGn. 1206 unsigned Binary = getBinaryCodeForInstr(MI); 1207 1208 // Set the conditional execution predicate 1209 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1210 1211 unsigned OpIdx = 0; 1212 assert((Binary & ARMII::D_BitShift) == 0 && 1213 (Binary & ARMII::N_BitShift) == 0 && 1214 (Binary & ARMII::M_BitShift) == 0 && "VFP encoding bug!"); 1215 1216 // Encode Dd / Sd. 1217 Binary |= encodeVFPRd(MI, OpIdx++); 1218 1219 // If this is a two-address operand, skip it, e.g. FMACD. 1220 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1) 1221 ++OpIdx; 1222 1223 // Encode Dn / Sn. 1224 if ((TID.TSFlags & ARMII::FormMask) == ARMII::VFPBinaryFrm) 1225 Binary |= encodeVFPRn(MI, OpIdx++); 1226 1227 if (OpIdx == TID.getNumOperands() || 1228 TID.OpInfo[OpIdx].isPredicate() || 1229 TID.OpInfo[OpIdx].isOptionalDef()) { 1230 // FCMPEZD etc. has only one operand. 1231 emitWordLE(Binary); 1232 return; 1233 } 1234 1235 // Encode Dm / Sm. 1236 Binary |= encodeVFPRm(MI, OpIdx); 1237 1238 emitWordLE(Binary); 1239} 1240 1241void ARMCodeEmitter::emitVFPConversionInstruction( 1242 const MachineInstr &MI) { 1243 const TargetInstrDesc &TID = MI.getDesc(); 1244 unsigned Form = TID.TSFlags & ARMII::FormMask; 1245 1246 // Part of binary is determined by TableGn. 1247 unsigned Binary = getBinaryCodeForInstr(MI); 1248 1249 // Set the conditional execution predicate 1250 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1251 1252 switch (Form) { 1253 default: break; 1254 case ARMII::VFPConv1Frm: 1255 case ARMII::VFPConv2Frm: 1256 case ARMII::VFPConv3Frm: 1257 // Encode Dd / Sd. 1258 Binary |= encodeVFPRd(MI, 0); 1259 break; 1260 case ARMII::VFPConv4Frm: 1261 // Encode Dn / Sn. 1262 Binary |= encodeVFPRn(MI, 0); 1263 break; 1264 case ARMII::VFPConv5Frm: 1265 // Encode Dm / Sm. 1266 Binary |= encodeVFPRm(MI, 0); 1267 break; 1268 } 1269 1270 switch (Form) { 1271 default: break; 1272 case ARMII::VFPConv1Frm: 1273 // Encode Dm / Sm. 1274 Binary |= encodeVFPRm(MI, 1); 1275 break; 1276 case ARMII::VFPConv2Frm: 1277 case ARMII::VFPConv3Frm: 1278 // Encode Dn / Sn. 1279 Binary |= encodeVFPRn(MI, 1); 1280 break; 1281 case ARMII::VFPConv4Frm: 1282 case ARMII::VFPConv5Frm: 1283 // Encode Dd / Sd. 1284 Binary |= encodeVFPRd(MI, 1); 1285 break; 1286 } 1287 1288 if (Form == ARMII::VFPConv5Frm) 1289 // Encode Dn / Sn. 1290 Binary |= encodeVFPRn(MI, 2); 1291 else if (Form == ARMII::VFPConv3Frm) 1292 // Encode Dm / Sm. 1293 Binary |= encodeVFPRm(MI, 2); 1294 1295 emitWordLE(Binary); 1296} 1297 1298void ARMCodeEmitter::emitVFPLoadStoreInstruction(const MachineInstr &MI) { 1299 // Part of binary is determined by TableGn. 1300 unsigned Binary = getBinaryCodeForInstr(MI); 1301 1302 // Set the conditional execution predicate 1303 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1304 1305 unsigned OpIdx = 0; 1306 1307 // Encode Dd / Sd. 1308 Binary |= encodeVFPRd(MI, OpIdx++); 1309 1310 // Encode address base. 1311 const MachineOperand &Base = MI.getOperand(OpIdx++); 1312 Binary |= getMachineOpValue(MI, Base) << ARMII::RegRnShift; 1313 1314 // If there is a non-zero immediate offset, encode it. 1315 if (Base.isReg()) { 1316 const MachineOperand &Offset = MI.getOperand(OpIdx); 1317 if (unsigned ImmOffs = ARM_AM::getAM5Offset(Offset.getImm())) { 1318 if (ARM_AM::getAM5Op(Offset.getImm()) == ARM_AM::add) 1319 Binary |= 1 << ARMII::U_BitShift; 1320 Binary |= ImmOffs; 1321 emitWordLE(Binary); 1322 return; 1323 } 1324 } 1325 1326 // If immediate offset is omitted, default to +0. 1327 Binary |= 1 << ARMII::U_BitShift; 1328 1329 emitWordLE(Binary); 1330} 1331 1332void ARMCodeEmitter::emitVFPLoadStoreMultipleInstruction( 1333 const MachineInstr &MI) { 1334 const TargetInstrDesc &TID = MI.getDesc(); 1335 bool IsUpdating = (TID.TSFlags & ARMII::IndexModeMask) != 0; 1336 1337 // Part of binary is determined by TableGn. 1338 unsigned Binary = getBinaryCodeForInstr(MI); 1339 1340 // Set the conditional execution predicate 1341 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1342 1343 // Skip operand 0 of an instruction with base register update. 1344 unsigned OpIdx = 0; 1345 if (IsUpdating) 1346 ++OpIdx; 1347 1348 // Set base address operand 1349 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift; 1350 1351 // Set addressing mode by modifying bits U(23) and P(24) 1352 const MachineOperand &MO = MI.getOperand(OpIdx++); 1353 Binary |= getAddrModeUPBits(ARM_AM::getAM5SubMode(MO.getImm())); 1354 1355 // Set bit W(21) 1356 if (ARM_AM::getAM5WBFlag(MO.getImm())) 1357 Binary |= 0x1 << ARMII::W_BitShift; 1358 1359 // First register is encoded in Dd. 1360 Binary |= encodeVFPRd(MI, OpIdx+2); 1361 1362 // Number of registers are encoded in offset field. 1363 unsigned NumRegs = 1; 1364 for (unsigned i = OpIdx+3, e = MI.getNumOperands(); i != e; ++i) { 1365 const MachineOperand &MO = MI.getOperand(i); 1366 if (!MO.isReg() || MO.isImplicit()) 1367 break; 1368 ++NumRegs; 1369 } 1370 Binary |= NumRegs * 2; 1371 1372 emitWordLE(Binary); 1373} 1374 1375void ARMCodeEmitter::emitMiscInstruction(const MachineInstr &MI) { 1376 // Part of binary is determined by TableGn. 1377 unsigned Binary = getBinaryCodeForInstr(MI); 1378 1379 // Set the conditional execution predicate 1380 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1381 1382 emitWordLE(Binary); 1383} 1384 1385#include "ARMGenCodeEmitter.inc" 1386