ARMCodeEmitter.cpp revision 30a4c49153cb859d72f6507ba361dd78bdfc2a01 
1//===-- ARM/ARMCodeEmitter.cpp - Convert ARM code to machine code ---------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the pass that transforms the ARM machine instructions into
11// relocatable machine code.
12//
13//===----------------------------------------------------------------------===//
14
15#define DEBUG_TYPE "jit"
16#include "ARM.h"
17#include "ARMAddressingModes.h"
18#include "ARMConstantPoolValue.h"
19#include "ARMInstrInfo.h"
20#include "ARMRelocations.h"
21#include "ARMSubtarget.h"
22#include "ARMTargetMachine.h"
23#include "llvm/Constants.h"
24#include "llvm/DerivedTypes.h"
25#include "llvm/Function.h"
26#include "llvm/PassManager.h"
27#include "llvm/CodeGen/JITCodeEmitter.h"
28#include "llvm/CodeGen/MachineConstantPool.h"
29#include "llvm/CodeGen/MachineFunctionPass.h"
30#include "llvm/CodeGen/MachineInstr.h"
31#include "llvm/CodeGen/MachineJumpTableInfo.h"
32#include "llvm/CodeGen/MachineModuleInfo.h"
33#include "llvm/CodeGen/Passes.h"
34#include "llvm/ADT/Statistic.h"
35#include "llvm/Support/Debug.h"
36#include "llvm/Support/ErrorHandling.h"
37#include "llvm/Support/raw_ostream.h"
38#ifndef NDEBUG
39#include <iomanip>
40#endif
41using namespace llvm;
42
43STATISTIC(NumEmitted, "Number of machine instructions emitted");
44
45namespace {
46
47  class ARMCodeEmitter : public MachineFunctionPass {
48    ARMJITInfo                *JTI;
49    const ARMInstrInfo        *II;
50    const TargetData          *TD;
51    const ARMSubtarget        *Subtarget;
52    TargetMachine             &TM;
53    JITCodeEmitter            &MCE;
54    MachineModuleInfo *MMI;
55    const std::vector<MachineConstantPoolEntry> *MCPEs;
56    const std::vector<MachineJumpTableEntry> *MJTEs;
57    bool IsPIC;
58    bool IsThumb;
59
60    void getAnalysisUsage(AnalysisUsage &AU) const {
61      AU.addRequired<MachineModuleInfo>();
62      MachineFunctionPass::getAnalysisUsage(AU);
63    }
64
65    static char ID;
66  public:
67    ARMCodeEmitter(TargetMachine &tm, JITCodeEmitter &mce)
68      : MachineFunctionPass(ID), JTI(0),
69        II((const ARMInstrInfo *)tm.getInstrInfo()),
70        TD(tm.getTargetData()), TM(tm),
71        MCE(mce), MCPEs(0), MJTEs(0),
72        IsPIC(TM.getRelocationModel() == Reloc::PIC_), IsThumb(false) {}
73
74    /// getBinaryCodeForInstr - This function, generated by the
75    /// CodeEmitterGenerator using TableGen, produces the binary encoding for
76    /// machine instructions.
77    unsigned getBinaryCodeForInstr(const MachineInstr &MI) const;
78
79    bool runOnMachineFunction(MachineFunction &MF);
80
81    virtual const char *getPassName() const {
82      return "ARM Machine Code Emitter";
83    }
84
85    void emitInstruction(const MachineInstr &MI);
86
87  private:
88
89    void emitWordLE(unsigned Binary);
90    void emitDWordLE(uint64_t Binary);
91    void emitConstantToMemory(unsigned CPI, const Constant *CV);
92    void emitConstPoolInstruction(const MachineInstr &MI);
93    void emitMOVi32immInstruction(const MachineInstr &MI);
94    void emitMOVi2piecesInstruction(const MachineInstr &MI);
95    void emitLEApcrelInstruction(const MachineInstr &MI);
96    void emitLEApcrelJTInstruction(const MachineInstr &MI);
97    void emitPseudoMoveInstruction(const MachineInstr &MI);
98    void addPCLabel(unsigned LabelID);
99    void emitPseudoInstruction(const MachineInstr &MI);
100    unsigned getMachineSoRegOpValue(const MachineInstr &MI,
101                                    const TargetInstrDesc &TID,
102                                    const MachineOperand &MO,
103                                    unsigned OpIdx);
104
105    unsigned getMachineSoImmOpValue(unsigned SoImm);
106    unsigned getAddrModeSBit(const MachineInstr &MI,
107                             const TargetInstrDesc &TID) const;
108
109    void emitDataProcessingInstruction(const MachineInstr &MI,
110                                       unsigned ImplicitRd = 0,
111                                       unsigned ImplicitRn = 0);
112
113    void emitLoadStoreInstruction(const MachineInstr &MI,
114                                  unsigned ImplicitRd = 0,
115                                  unsigned ImplicitRn = 0);
116
117    void emitMiscLoadStoreInstruction(const MachineInstr &MI,
118                                      unsigned ImplicitRn = 0);
119
120    void emitLoadStoreMultipleInstruction(const MachineInstr &MI);
121
122    void emitMulFrmInstruction(const MachineInstr &MI);
123
124    void emitExtendInstruction(const MachineInstr &MI);
125
126    void emitMiscArithInstruction(const MachineInstr &MI);
127
128    void emitSaturateInstruction(const MachineInstr &MI);
129
130    void emitBranchInstruction(const MachineInstr &MI);
131
132    void emitInlineJumpTable(unsigned JTIndex);
133
134    void emitMiscBranchInstruction(const MachineInstr &MI);
135
136    void emitVFPArithInstruction(const MachineInstr &MI);
137
138    void emitVFPConversionInstruction(const MachineInstr &MI);
139
140    void emitVFPLoadStoreInstruction(const MachineInstr &MI);
141
142    void emitVFPLoadStoreMultipleInstruction(const MachineInstr &MI);
143
144    void emitMiscInstruction(const MachineInstr &MI);
145
146    void emitNEONLaneInstruction(const MachineInstr &MI);
147    void emitNEONDupInstruction(const MachineInstr &MI);
148    void emitNEON1RegModImmInstruction(const MachineInstr &MI);
149    void emitNEON2RegInstruction(const MachineInstr &MI);
150    void emitNEON3RegInstruction(const MachineInstr &MI);
151
152    /// getMachineOpValue - Return binary encoding of operand. If the machine
153    /// operand requires relocation, record the relocation and return zero.
154    unsigned getMachineOpValue(const MachineInstr &MI,
155                               const MachineOperand &MO) const;
156    unsigned getMachineOpValue(const MachineInstr &MI, unsigned OpIdx) const {
157      return getMachineOpValue(MI, MI.getOperand(OpIdx));
158    }
159
160    // FIXME: The legacy JIT ARMCodeEmitter doesn't rely on the the
161    //  TableGen'erated getBinaryCodeForInstr() function to encode any
162    //  operand values, instead querying getMachineOpValue() directly for
163    //  each operand it needs to encode. Thus, any of the new encoder
164    //  helper functions can simply return 0 as the values the return
165    //  are already handled elsewhere. They are placeholders to allow this
166    //  encoder to continue to function until the MC encoder is sufficiently
167    //  far along that this one can be eliminated entirely.
168    unsigned NEONThumb2DataIPostEncoder(const MachineInstr &MI, unsigned Val)
169      const { return 0; }
170    unsigned NEONThumb2LoadStorePostEncoder(const MachineInstr &MI,unsigned Val)
171      const { return 0; }
172    unsigned NEONThumb2DupPostEncoder(const MachineInstr &MI,unsigned Val)
173      const { return 0; }
174    unsigned getBranchTargetOpValue(const MachineInstr &MI, unsigned Op)
175      const { return 0; }
176    unsigned getCCOutOpValue(const MachineInstr &MI, unsigned Op)
177      const { return 0; }
178    unsigned getSOImmOpValue(const MachineInstr &MI, unsigned Op)
179      const { return 0; }
180    unsigned getT2SOImmOpValue(const MachineInstr &MI, unsigned Op)
181      const { return 0; }
182    unsigned getSORegOpValue(const MachineInstr &MI, unsigned Op)
183      const { return 0; }
184    unsigned getT2SORegOpValue(const MachineInstr &MI, unsigned Op)
185      const { return 0; }
186    unsigned getRotImmOpValue(const MachineInstr &MI, unsigned Op)
187      const { return 0; }
188    unsigned getImmMinusOneOpValue(const MachineInstr &MI, unsigned Op)
189      const { return 0; }
190    unsigned getAddrMode6AddressOpValue(const MachineInstr &MI, unsigned Op)
191      const { return 0; }
192    unsigned getAddrMode6OffsetOpValue(const MachineInstr &MI, unsigned Op)
193      const { return 0; }
194    unsigned getBitfieldInvertedMaskOpValue(const MachineInstr &MI,
195                                            unsigned Op) const { return 0; }
196    uint32_t getLdStmModeOpValue(const MachineInstr &MI, unsigned OpIdx)
197      const {return 0; }
198    uint32_t getLdStSORegOpValue(const MachineInstr &MI, unsigned OpIdx)
199      const { return 0; }
200
201    unsigned getAddrModeImm12OpValue(const MachineInstr &MI, unsigned Op)
202      const {
203      // {17-13} = reg
204      // {12}    = (U)nsigned (add == '1', sub == '0')
205      // {11-0}  = imm12
206      const MachineOperand &MO  = MI.getOperand(Op);
207      const MachineOperand &MO1 = MI.getOperand(Op + 1);
208      if (!MO.isReg()) {
209        emitConstPoolAddress(MO.getIndex(), ARM::reloc_arm_cp_entry);
210        return 0;
211      }
212      unsigned Reg = getARMRegisterNumbering(MO.getReg());
213      int32_t Imm12 = MO1.getImm();
214      uint32_t Binary;
215      Binary = Imm12 & 0xfff;
216      if (Imm12 >= 0)
217        Binary |= (1 << 12);
218      Binary |= (Reg << 13);
219      return Binary;
220    }
221    uint32_t getAddrMode2OpValue(const MachineInstr &MI, unsigned OpIdx)
222      const { return 0;}
223    uint32_t getAddrMode2OffsetOpValue(const MachineInstr &MI, unsigned OpIdx)
224      const { return 0;}
225    uint32_t getAddrMode3OffsetOpValue(const MachineInstr &MI, unsigned OpIdx)
226      const { return 0;}
227    uint32_t getAddrMode3OpValue(const MachineInstr &MI, unsigned Op) const
228      { return 0; }
229    uint32_t getAddrMode5OpValue(const MachineInstr &MI, unsigned Op) const {
230      // {12-9}  = reg
231      // {8}     = (U)nsigned (add == '1', sub == '0')
232      // {7-0}   = imm8
233      uint32_t Binary;
234      const MachineOperand &MO  = MI.getOperand(Op);
235      uint32_t Reg = getMachineOpValue(MI, MO);
236      Binary |= (Reg << 9);
237
238      // If there is a non-zero immediate offset, encode it.
239      if (MO.isReg()) {
240          const MachineOperand &MO1 = MI.getOperand(Op + 1);
241        if (uint32_t ImmOffs = ARM_AM::getAM5Offset(MO1.getImm())) {
242          if (ARM_AM::getAM5Op(MO1.getImm()) == ARM_AM::add)
243            Binary |= 1 << 8;
244          Binary |= ImmOffs & 0xff;
245          return Binary;
246        }
247      }
248
249      // If immediate offset is omitted, default to +0.
250      Binary |= 1 << 8;
251      return Binary;
252    }
253    unsigned getNEONVcvtImm32OpValue(const MachineInstr &MI, unsigned Op)
254      const { return 0; }
255
256    unsigned getRegisterListOpValue(const MachineInstr &MI, unsigned Op)
257      const { return 0; }
258
259    /// getMovi32Value - Return binary encoding of operand for movw/movt. If the
260    /// machine operand requires relocation, record the relocation and return
261    /// zero.
262    unsigned getMovi32Value(const MachineInstr &MI,const MachineOperand &MO,
263                            unsigned Reloc);
264
265    /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
266    ///
267    unsigned getShiftOp(unsigned Imm) const ;
268
269    /// Routines that handle operands which add machine relocations which are
270    /// fixed up by the relocation stage.
271    void emitGlobalAddress(const GlobalValue *GV, unsigned Reloc,
272                           bool MayNeedFarStub,  bool Indirect,
273                           intptr_t ACPV = 0) const;
274    void emitExternalSymbolAddress(const char *ES, unsigned Reloc) const;
275    void emitConstPoolAddress(unsigned CPI, unsigned Reloc) const;
276    void emitJumpTableAddress(unsigned JTIndex, unsigned Reloc) const;
277    void emitMachineBasicBlock(MachineBasicBlock *BB, unsigned Reloc,
278                               intptr_t JTBase = 0) const;
279  };
280}
281
282char ARMCodeEmitter::ID = 0;
283
284/// createARMJITCodeEmitterPass - Return a pass that emits the collected ARM
285/// code to the specified MCE object.
286FunctionPass *llvm::createARMJITCodeEmitterPass(ARMBaseTargetMachine &TM,
287                                                JITCodeEmitter &JCE) {
288  return new ARMCodeEmitter(TM, JCE);
289}
290
291bool ARMCodeEmitter::runOnMachineFunction(MachineFunction &MF) {
292  assert((MF.getTarget().getRelocationModel() != Reloc::Default ||
293          MF.getTarget().getRelocationModel() != Reloc::Static) &&
294         "JIT relocation model must be set to static or default!");
295  JTI = ((ARMTargetMachine &)MF.getTarget()).getJITInfo();
296  II = ((const ARMTargetMachine &)MF.getTarget()).getInstrInfo();
297  TD = ((const ARMTargetMachine &)MF.getTarget()).getTargetData();
298  Subtarget = &TM.getSubtarget<ARMSubtarget>();
299  MCPEs = &MF.getConstantPool()->getConstants();
300  MJTEs = 0;
301  if (MF.getJumpTableInfo()) MJTEs = &MF.getJumpTableInfo()->getJumpTables();
302  IsPIC = TM.getRelocationModel() == Reloc::PIC_;
303  IsThumb = MF.getInfo<ARMFunctionInfo>()->isThumbFunction();
304  JTI->Initialize(MF, IsPIC);
305  MMI = &getAnalysis<MachineModuleInfo>();
306  MCE.setModuleInfo(MMI);
307
308  do {
309    DEBUG(errs() << "JITTing function '"
310          << MF.getFunction()->getName() << "'\n");
311    MCE.startFunction(MF);
312    for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();
313         MBB != E; ++MBB) {
314      MCE.StartMachineBasicBlock(MBB);
315      for (MachineBasicBlock::const_iterator I = MBB->begin(), E = MBB->end();
316           I != E; ++I)
317        emitInstruction(*I);
318    }
319  } while (MCE.finishFunction(MF));
320
321  return false;
322}
323
324/// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
325///
326unsigned ARMCodeEmitter::getShiftOp(unsigned Imm) const {
327  switch (ARM_AM::getAM2ShiftOpc(Imm)) {
328  default: llvm_unreachable("Unknown shift opc!");
329  case ARM_AM::asr: return 2;
330  case ARM_AM::lsl: return 0;
331  case ARM_AM::lsr: return 1;
332  case ARM_AM::ror:
333  case ARM_AM::rrx: return 3;
334  }
335  return 0;
336}
337
338/// getMovi32Value - Return binary encoding of operand for movw/movt. If the
339/// machine operand requires relocation, record the relocation and return zero.
340unsigned ARMCodeEmitter::getMovi32Value(const MachineInstr &MI,
341                                        const MachineOperand &MO,
342                                        unsigned Reloc) {
343  assert(((Reloc == ARM::reloc_arm_movt) || (Reloc == ARM::reloc_arm_movw))
344      && "Relocation to this function should be for movt or movw");
345
346  if (MO.isImm())
347    return static_cast<unsigned>(MO.getImm());
348  else if (MO.isGlobal())
349    emitGlobalAddress(MO.getGlobal(), Reloc, true, false);
350  else if (MO.isSymbol())
351    emitExternalSymbolAddress(MO.getSymbolName(), Reloc);
352  else if (MO.isMBB())
353    emitMachineBasicBlock(MO.getMBB(), Reloc);
354  else {
355#ifndef NDEBUG
356    errs() << MO;
357#endif
358    llvm_unreachable("Unsupported operand type for movw/movt");
359  }
360  return 0;
361}
362
363/// getMachineOpValue - Return binary encoding of operand. If the machine
364/// operand requires relocation, record the relocation and return zero.
365unsigned ARMCodeEmitter::getMachineOpValue(const MachineInstr &MI,
366                                           const MachineOperand &MO) const {
367  if (MO.isReg())
368    return getARMRegisterNumbering(MO.getReg());
369  else if (MO.isImm())
370    return static_cast<unsigned>(MO.getImm());
371  else if (MO.isFPImm())
372    return static_cast<unsigned>(MO.getFPImm()->getValueAPF()
373                      .bitcastToAPInt().getHiBits(32).getLimitedValue());
374  else if (MO.isGlobal())
375    emitGlobalAddress(MO.getGlobal(), ARM::reloc_arm_branch, true, false);
376  else if (MO.isSymbol())
377    emitExternalSymbolAddress(MO.getSymbolName(), ARM::reloc_arm_branch);
378  else if (MO.isCPI()) {
379    const TargetInstrDesc &TID = MI.getDesc();
380    // For VFP load, the immediate offset is multiplied by 4.
381    unsigned Reloc =  ((TID.TSFlags & ARMII::FormMask) == ARMII::VFPLdStFrm)
382      ? ARM::reloc_arm_vfp_cp_entry : ARM::reloc_arm_cp_entry;
383    emitConstPoolAddress(MO.getIndex(), Reloc);
384  } else if (MO.isJTI())
385    emitJumpTableAddress(MO.getIndex(), ARM::reloc_arm_relative);
386  else if (MO.isMBB())
387    emitMachineBasicBlock(MO.getMBB(), ARM::reloc_arm_branch);
388  else {
389#ifndef NDEBUG
390    errs() << MO;
391#endif
392    llvm_unreachable(0);
393  }
394  return 0;
395}
396
397/// emitGlobalAddress - Emit the specified address to the code stream.
398///
399void ARMCodeEmitter::emitGlobalAddress(const GlobalValue *GV, unsigned Reloc,
400                                       bool MayNeedFarStub, bool Indirect,
401                                       intptr_t ACPV) const {
402  MachineRelocation MR = Indirect
403    ? MachineRelocation::getIndirectSymbol(MCE.getCurrentPCOffset(), Reloc,
404                                           const_cast<GlobalValue *>(GV),
405                                           ACPV, MayNeedFarStub)
406    : MachineRelocation::getGV(MCE.getCurrentPCOffset(), Reloc,
407                               const_cast<GlobalValue *>(GV), ACPV,
408                               MayNeedFarStub);
409  MCE.addRelocation(MR);
410}
411
412/// emitExternalSymbolAddress - Arrange for the address of an external symbol to
413/// be emitted to the current location in the function, and allow it to be PC
414/// relative.
415void ARMCodeEmitter::
416emitExternalSymbolAddress(const char *ES, unsigned Reloc) const {
417  MCE.addRelocation(MachineRelocation::getExtSym(MCE.getCurrentPCOffset(),
418                                                 Reloc, ES));
419}
420
421/// emitConstPoolAddress - Arrange for the address of an constant pool
422/// to be emitted to the current location in the function, and allow it to be PC
423/// relative.
424void ARMCodeEmitter::emitConstPoolAddress(unsigned CPI, unsigned Reloc) const {
425  // Tell JIT emitter we'll resolve the address.
426  MCE.addRelocation(MachineRelocation::getConstPool(MCE.getCurrentPCOffset(),
427                                                    Reloc, CPI, 0, true));
428}
429
430/// emitJumpTableAddress - Arrange for the address of a jump table to
431/// be emitted to the current location in the function, and allow it to be PC
432/// relative.
433void ARMCodeEmitter::
434emitJumpTableAddress(unsigned JTIndex, unsigned Reloc) const {
435  MCE.addRelocation(MachineRelocation::getJumpTable(MCE.getCurrentPCOffset(),
436                                                    Reloc, JTIndex, 0, true));
437}
438
439/// emitMachineBasicBlock - Emit the specified address basic block.
440void ARMCodeEmitter::emitMachineBasicBlock(MachineBasicBlock *BB,
441                                           unsigned Reloc,
442                                           intptr_t JTBase) const {
443  MCE.addRelocation(MachineRelocation::getBB(MCE.getCurrentPCOffset(),
444                                             Reloc, BB, JTBase));
445}
446
447void ARMCodeEmitter::emitWordLE(unsigned Binary) {
448  DEBUG(errs() << "  0x";
449        errs().write_hex(Binary) << "\n");
450  MCE.emitWordLE(Binary);
451}
452
453void ARMCodeEmitter::emitDWordLE(uint64_t Binary) {
454  DEBUG(errs() << "  0x";
455        errs().write_hex(Binary) << "\n");
456  MCE.emitDWordLE(Binary);
457}
458
459void ARMCodeEmitter::emitInstruction(const MachineInstr &MI) {
460  DEBUG(errs() << "JIT: " << (void*)MCE.getCurrentPCValue() << ":\t" << MI);
461
462  MCE.processDebugLoc(MI.getDebugLoc(), true);
463
464  ++NumEmitted;  // Keep track of the # of mi's emitted
465  switch (MI.getDesc().TSFlags & ARMII::FormMask) {
466  default: {
467    llvm_unreachable("Unhandled instruction encoding format!");
468    break;
469  }
470  case ARMII::Pseudo:
471    emitPseudoInstruction(MI);
472    break;
473  case ARMII::DPFrm:
474  case ARMII::DPSoRegFrm:
475    emitDataProcessingInstruction(MI);
476    break;
477  case ARMII::LdFrm:
478  case ARMII::StFrm:
479    emitLoadStoreInstruction(MI);
480    break;
481  case ARMII::LdMiscFrm:
482  case ARMII::StMiscFrm:
483    emitMiscLoadStoreInstruction(MI);
484    break;
485  case ARMII::LdStMulFrm:
486    emitLoadStoreMultipleInstruction(MI);
487    break;
488  case ARMII::MulFrm:
489    emitMulFrmInstruction(MI);
490    break;
491  case ARMII::ExtFrm:
492    emitExtendInstruction(MI);
493    break;
494  case ARMII::ArithMiscFrm:
495    emitMiscArithInstruction(MI);
496    break;
497  case ARMII::SatFrm:
498    emitSaturateInstruction(MI);
499    break;
500  case ARMII::BrFrm:
501    emitBranchInstruction(MI);
502    break;
503  case ARMII::BrMiscFrm:
504    emitMiscBranchInstruction(MI);
505    break;
506  // VFP instructions.
507  case ARMII::VFPUnaryFrm:
508  case ARMII::VFPBinaryFrm:
509    emitVFPArithInstruction(MI);
510    break;
511  case ARMII::VFPConv1Frm:
512  case ARMII::VFPConv2Frm:
513  case ARMII::VFPConv3Frm:
514  case ARMII::VFPConv4Frm:
515  case ARMII::VFPConv5Frm:
516    emitVFPConversionInstruction(MI);
517    break;
518  case ARMII::VFPLdStFrm:
519    emitVFPLoadStoreInstruction(MI);
520    break;
521  case ARMII::VFPLdStMulFrm:
522    emitVFPLoadStoreMultipleInstruction(MI);
523    break;
524  case ARMII::VFPMiscFrm:
525    emitMiscInstruction(MI);
526    break;
527  // NEON instructions.
528  case ARMII::NGetLnFrm:
529  case ARMII::NSetLnFrm:
530    emitNEONLaneInstruction(MI);
531    break;
532  case ARMII::NDupFrm:
533    emitNEONDupInstruction(MI);
534    break;
535  case ARMII::N1RegModImmFrm:
536    emitNEON1RegModImmInstruction(MI);
537    break;
538  case ARMII::N2RegFrm:
539    emitNEON2RegInstruction(MI);
540    break;
541  case ARMII::N3RegFrm:
542    emitNEON3RegInstruction(MI);
543    break;
544  }
545  MCE.processDebugLoc(MI.getDebugLoc(), false);
546}
547
548void ARMCodeEmitter::emitConstantToMemory(unsigned CPI, const Constant *C) {
549  DEBUG({
550      errs() << "  ** Constant pool #" << CPI << " @ "
551             << (void*)MCE.getCurrentPCValue() << " ";
552      if (const Function *F = dyn_cast<Function>(C))
553        errs() << F->getName();
554      else
555        errs() << *C;
556      errs() << '\n';
557    });
558
559  switch (C->getValueID()) {
560  default: {
561    llvm_unreachable("Unable to handle this constantpool entry!");
562    break;
563  }
564  case Value::GlobalVariableVal: {
565    emitGlobalAddress(static_cast<const GlobalValue*>(C),
566                      ARM::reloc_arm_absolute, isa<Function>(C), false);
567    emitWordLE(0);
568    break;
569  }
570  case Value::ConstantIntVal: {
571    const ConstantInt *CI = static_cast<const ConstantInt*>(C);
572    uint32_t Val = *(uint32_t*)CI->getValue().getRawData();
573    emitWordLE(Val);
574    break;
575  }
576  case Value::ConstantFPVal: {
577    const ConstantFP *CFP = static_cast<const ConstantFP*>(C);
578    if (CFP->getType()->isFloatTy())
579      emitWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue());
580    else if (CFP->getType()->isDoubleTy())
581      emitDWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue());
582    else {
583      llvm_unreachable("Unable to handle this constantpool entry!");
584    }
585    break;
586  }
587  case Value::ConstantArrayVal: {
588    const ConstantArray *CA = static_cast<const ConstantArray*>(C);
589    for (unsigned i = 0, e = CA->getNumOperands(); i != e; ++i)
590      emitConstantToMemory(CPI, CA->getOperand(i));
591    break;
592  }
593  }
594
595  return;
596}
597
598void ARMCodeEmitter::emitConstPoolInstruction(const MachineInstr &MI) {
599  unsigned CPI = MI.getOperand(0).getImm();       // CP instruction index.
600  unsigned CPIndex = MI.getOperand(1).getIndex(); // Actual cp entry index.
601  const MachineConstantPoolEntry &MCPE = (*MCPEs)[CPIndex];
602
603  // Remember the CONSTPOOL_ENTRY address for later relocation.
604  JTI->addConstantPoolEntryAddr(CPI, MCE.getCurrentPCValue());
605
606  // Emit constpool island entry. In most cases, the actual values will be
607  // resolved and relocated after code emission.
608  if (MCPE.isMachineConstantPoolEntry()) {
609    ARMConstantPoolValue *ACPV =
610      static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal);
611
612    DEBUG(errs() << "  ** ARM constant pool #" << CPI << " @ "
613          << (void*)MCE.getCurrentPCValue() << " " << *ACPV << '\n');
614
615    assert(ACPV->isGlobalValue() && "unsupported constant pool value");
616    const GlobalValue *GV = ACPV->getGV();
617    if (GV) {
618      Reloc::Model RelocM = TM.getRelocationModel();
619      emitGlobalAddress(GV, ARM::reloc_arm_machine_cp_entry,
620                        isa<Function>(GV),
621                        Subtarget->GVIsIndirectSymbol(GV, RelocM),
622                        (intptr_t)ACPV);
623     } else  {
624      emitExternalSymbolAddress(ACPV->getSymbol(), ARM::reloc_arm_absolute);
625    }
626    emitWordLE(0);
627  } else {
628    emitConstantToMemory(CPI, MCPE.Val.ConstVal);
629  }
630}
631
632void ARMCodeEmitter::emitMOVi32immInstruction(const MachineInstr &MI) {
633  const MachineOperand &MO0 = MI.getOperand(0);
634  const MachineOperand &MO1 = MI.getOperand(1);
635
636  // Emit the 'movw' instruction.
637  unsigned Binary = 0x30 << 20;  // mov: Insts{27-20} = 0b00110000
638
639  unsigned Lo16 = getMovi32Value(MI, MO1, ARM::reloc_arm_movw) & 0xFFFF;
640
641  // Set the conditional execution predicate.
642  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
643
644  // Encode Rd.
645  Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
646
647  // Encode imm16 as imm4:imm12
648  Binary |= Lo16 & 0xFFF; // Insts{11-0} = imm12
649  Binary |= ((Lo16 >> 12) & 0xF) << 16; // Insts{19-16} = imm4
650  emitWordLE(Binary);
651
652  unsigned Hi16 = getMovi32Value(MI, MO1, ARM::reloc_arm_movt) >> 16;
653  // Emit the 'movt' instruction.
654  Binary = 0x34 << 20; // movt: Insts{27-20} = 0b00110100
655
656  // Set the conditional execution predicate.
657  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
658
659  // Encode Rd.
660  Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
661
662  // Encode imm16 as imm4:imm1, same as movw above.
663  Binary |= Hi16 & 0xFFF;
664  Binary |= ((Hi16 >> 12) & 0xF) << 16;
665  emitWordLE(Binary);
666}
667
668void ARMCodeEmitter::emitMOVi2piecesInstruction(const MachineInstr &MI) {
669  const MachineOperand &MO0 = MI.getOperand(0);
670  const MachineOperand &MO1 = MI.getOperand(1);
671  assert(MO1.isImm() && ARM_AM::isSOImmTwoPartVal(MO1.getImm()) &&
672                                                  "Not a valid so_imm value!");
673  unsigned V1 = ARM_AM::getSOImmTwoPartFirst(MO1.getImm());
674  unsigned V2 = ARM_AM::getSOImmTwoPartSecond(MO1.getImm());
675
676  // Emit the 'mov' instruction.
677  unsigned Binary = 0xd << 21;  // mov: Insts{24-21} = 0b1101
678
679  // Set the conditional execution predicate.
680  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
681
682  // Encode Rd.
683  Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
684
685  // Encode so_imm.
686  // Set bit I(25) to identify this is the immediate form of <shifter_op>
687  Binary |= 1 << ARMII::I_BitShift;
688  Binary |= getMachineSoImmOpValue(V1);
689  emitWordLE(Binary);
690
691  // Now the 'orr' instruction.
692  Binary = 0xc << 21;  // orr: Insts{24-21} = 0b1100
693
694  // Set the conditional execution predicate.
695  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
696
697  // Encode Rd.
698  Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
699
700  // Encode Rn.
701  Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRnShift;
702
703  // Encode so_imm.
704  // Set bit I(25) to identify this is the immediate form of <shifter_op>
705  Binary |= 1 << ARMII::I_BitShift;
706  Binary |= getMachineSoImmOpValue(V2);
707  emitWordLE(Binary);
708}
709
710void ARMCodeEmitter::emitLEApcrelInstruction(const MachineInstr &MI) {
711  // It's basically add r, pc, (LCPI - $+8)
712  const TargetInstrDesc &TID = MI.getDesc();
713
714  unsigned Binary = 0;
715
716  // Set the conditional execution predicate
717  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
718
719  // Encode S bit if MI modifies CPSR.
720  Binary |= getAddrModeSBit(MI, TID);
721
722  // Encode Rd.
723  Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
724
725  // Encode Rn which is PC.
726  Binary |= getARMRegisterNumbering(ARM::PC) << ARMII::RegRnShift;
727
728  // Encode the displacement which is a so_imm.
729  // Set bit I(25) to identify this is the immediate form of <shifter_op>
730  Binary |= 1 << ARMII::I_BitShift;
731  emitConstPoolAddress(MI.getOperand(1).getIndex(), ARM::reloc_arm_so_imm_cp_entry);
732
733  emitWordLE(Binary);
734}
735
736void ARMCodeEmitter::emitLEApcrelJTInstruction(const MachineInstr &MI) {
737  // It's basically add r, pc, (LJTI - $+8)
738
739  const TargetInstrDesc &TID = MI.getDesc();
740
741  // Emit the 'add' instruction.
742  unsigned Binary = 0x4 << 21;  // add: Insts{21-24} = 0b0100
743
744  // Set the conditional execution predicate
745  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
746
747  // Encode S bit if MI modifies CPSR.
748  Binary |= getAddrModeSBit(MI, TID);
749
750  // Encode Rd.
751  Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
752
753  // Encode Rn which is PC.
754  Binary |= getARMRegisterNumbering(ARM::PC) << ARMII::RegRnShift;
755
756  // Encode the displacement.
757  Binary |= 1 << ARMII::I_BitShift;
758  emitJumpTableAddress(MI.getOperand(1).getIndex(), ARM::reloc_arm_jt_base);
759
760  emitWordLE(Binary);
761}
762
763void ARMCodeEmitter::emitPseudoMoveInstruction(const MachineInstr &MI) {
764  unsigned Opcode = MI.getDesc().Opcode;
765
766  // Part of binary is determined by TableGn.
767  unsigned Binary = getBinaryCodeForInstr(MI);
768
769  // Set the conditional execution predicate
770  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
771
772  // Encode S bit if MI modifies CPSR.
773  if (Opcode == ARM::MOVsrl_flag || Opcode == ARM::MOVsra_flag)
774    Binary |= 1 << ARMII::S_BitShift;
775
776  // Encode register def if there is one.
777  Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
778
779  // Encode the shift operation.
780  switch (Opcode) {
781  default: break;
782  case ARM::RRX:
783    // rrx
784    Binary |= 0x6 << 4;
785    break;
786  case ARM::MOVsrl_flag:
787    // lsr #1
788    Binary |= (0x2 << 4) | (1 << 7);
789    break;
790  case ARM::MOVsra_flag:
791    // asr #1
792    Binary |= (0x4 << 4) | (1 << 7);
793    break;
794  }
795
796  // Encode register Rm.
797  Binary |= getMachineOpValue(MI, 1);
798
799  emitWordLE(Binary);
800}
801
802void ARMCodeEmitter::addPCLabel(unsigned LabelID) {
803  DEBUG(errs() << "  ** LPC" << LabelID << " @ "
804        << (void*)MCE.getCurrentPCValue() << '\n');
805  JTI->addPCLabelAddr(LabelID, MCE.getCurrentPCValue());
806}
807
808void ARMCodeEmitter::emitPseudoInstruction(const MachineInstr &MI) {
809  unsigned Opcode = MI.getDesc().Opcode;
810  switch (Opcode) {
811  default:
812    llvm_unreachable("ARMCodeEmitter::emitPseudoInstruction");
813  case ARM::BX:
814  case ARM::BMOVPCRX:
815  case ARM::BXr9:
816  case ARM::BMOVPCRXr9: {
817    // First emit mov lr, pc
818    unsigned Binary = 0x01a0e00f;
819    Binary |= II->getPredicate(&MI) << ARMII::CondShift;
820    emitWordLE(Binary);
821
822    // and then emit the branch.
823    emitMiscBranchInstruction(MI);
824    break;
825  }
826  case TargetOpcode::INLINEASM: {
827    // We allow inline assembler nodes with empty bodies - they can
828    // implicitly define registers, which is ok for JIT.
829    if (MI.getOperand(0).getSymbolName()[0]) {
830      report_fatal_error("JIT does not support inline asm!");
831    }
832    break;
833  }
834  case TargetOpcode::PROLOG_LABEL:
835  case TargetOpcode::EH_LABEL:
836    MCE.emitLabel(MI.getOperand(0).getMCSymbol());
837    break;
838  case TargetOpcode::IMPLICIT_DEF:
839  case TargetOpcode::KILL:
840    // Do nothing.
841    break;
842  case ARM::CONSTPOOL_ENTRY:
843    emitConstPoolInstruction(MI);
844    break;
845  case ARM::PICADD: {
846    // Remember of the address of the PC label for relocation later.
847    addPCLabel(MI.getOperand(2).getImm());
848    // PICADD is just an add instruction that implicitly read pc.
849    emitDataProcessingInstruction(MI, 0, ARM::PC);
850    break;
851  }
852  case ARM::PICLDR:
853  case ARM::PICLDRB:
854  case ARM::PICSTR:
855  case ARM::PICSTRB: {
856    // Remember of the address of the PC label for relocation later.
857    addPCLabel(MI.getOperand(2).getImm());
858    // These are just load / store instructions that implicitly read pc.
859    emitLoadStoreInstruction(MI, 0, ARM::PC);
860    break;
861  }
862  case ARM::PICLDRH:
863  case ARM::PICLDRSH:
864  case ARM::PICLDRSB:
865  case ARM::PICSTRH: {
866    // Remember of the address of the PC label for relocation later.
867    addPCLabel(MI.getOperand(2).getImm());
868    // These are just load / store instructions that implicitly read pc.
869    emitMiscLoadStoreInstruction(MI, ARM::PC);
870    break;
871  }
872
873  case ARM::MOVi32imm:
874    // Two instructions to materialize a constant.
875    if (Subtarget->hasV6T2Ops())
876      emitMOVi32immInstruction(MI);
877    else
878      emitMOVi2piecesInstruction(MI);
879    break;
880  case ARM::LEApcrel:
881    // Materialize constantpool index address.
882    emitLEApcrelInstruction(MI);
883    break;
884  case ARM::LEApcrelJT:
885    // Materialize jumptable address.
886    emitLEApcrelJTInstruction(MI);
887    break;
888  case ARM::RRX:
889  case ARM::MOVsrl_flag:
890  case ARM::MOVsra_flag:
891    emitPseudoMoveInstruction(MI);
892    break;
893  }
894}
895
896unsigned ARMCodeEmitter::getMachineSoRegOpValue(const MachineInstr &MI,
897                                                const TargetInstrDesc &TID,
898                                                const MachineOperand &MO,
899                                                unsigned OpIdx) {
900  unsigned Binary = getMachineOpValue(MI, MO);
901
902  const MachineOperand &MO1 = MI.getOperand(OpIdx + 1);
903  const MachineOperand &MO2 = MI.getOperand(OpIdx + 2);
904  ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm());
905
906  // Encode the shift opcode.
907  unsigned SBits = 0;
908  unsigned Rs = MO1.getReg();
909  if (Rs) {
910    // Set shift operand (bit[7:4]).
911    // LSL - 0001
912    // LSR - 0011
913    // ASR - 0101
914    // ROR - 0111
915    // RRX - 0110 and bit[11:8] clear.
916    switch (SOpc) {
917    default: llvm_unreachable("Unknown shift opc!");
918    case ARM_AM::lsl: SBits = 0x1; break;
919    case ARM_AM::lsr: SBits = 0x3; break;
920    case ARM_AM::asr: SBits = 0x5; break;
921    case ARM_AM::ror: SBits = 0x7; break;
922    case ARM_AM::rrx: SBits = 0x6; break;
923    }
924  } else {
925    // Set shift operand (bit[6:4]).
926    // LSL - 000
927    // LSR - 010
928    // ASR - 100
929    // ROR - 110
930    switch (SOpc) {
931    default: llvm_unreachable("Unknown shift opc!");
932    case ARM_AM::lsl: SBits = 0x0; break;
933    case ARM_AM::lsr: SBits = 0x2; break;
934    case ARM_AM::asr: SBits = 0x4; break;
935    case ARM_AM::ror: SBits = 0x6; break;
936    }
937  }
938  Binary |= SBits << 4;
939  if (SOpc == ARM_AM::rrx)
940    return Binary;
941
942  // Encode the shift operation Rs or shift_imm (except rrx).
943  if (Rs) {
944    // Encode Rs bit[11:8].
945    assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0);
946    return Binary | (getARMRegisterNumbering(Rs) << ARMII::RegRsShift);
947  }
948
949  // Encode shift_imm bit[11:7].
950  return Binary | ARM_AM::getSORegOffset(MO2.getImm()) << 7;
951}
952
953unsigned ARMCodeEmitter::getMachineSoImmOpValue(unsigned SoImm) {
954  int SoImmVal = ARM_AM::getSOImmVal(SoImm);
955  assert(SoImmVal != -1 && "Not a valid so_imm value!");
956
957  // Encode rotate_imm.
958  unsigned Binary = (ARM_AM::getSOImmValRot((unsigned)SoImmVal) >> 1)
959    << ARMII::SoRotImmShift;
960
961  // Encode immed_8.
962  Binary |= ARM_AM::getSOImmValImm((unsigned)SoImmVal);
963  return Binary;
964}
965
966unsigned ARMCodeEmitter::getAddrModeSBit(const MachineInstr &MI,
967                                         const TargetInstrDesc &TID) const {
968  for (unsigned i = MI.getNumOperands(), e = TID.getNumOperands(); i >= e; --i){
969    const MachineOperand &MO = MI.getOperand(i-1);
970    if (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR)
971      return 1 << ARMII::S_BitShift;
972  }
973  return 0;
974}
975
976void ARMCodeEmitter::emitDataProcessingInstruction(const MachineInstr &MI,
977                                                   unsigned ImplicitRd,
978                                                   unsigned ImplicitRn) {
979  const TargetInstrDesc &TID = MI.getDesc();
980
981  // Part of binary is determined by TableGn.
982  unsigned Binary = getBinaryCodeForInstr(MI);
983
984  // Set the conditional execution predicate
985  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
986
987  // Encode S bit if MI modifies CPSR.
988  Binary |= getAddrModeSBit(MI, TID);
989
990  // Encode register def if there is one.
991  unsigned NumDefs = TID.getNumDefs();
992  unsigned OpIdx = 0;
993  if (NumDefs)
994    Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
995  else if (ImplicitRd)
996    // Special handling for implicit use (e.g. PC).
997    Binary |= (getARMRegisterNumbering(ImplicitRd) << ARMII::RegRdShift);
998
999  if (TID.Opcode == ARM::MOVi16) {
1000      // Get immediate from MI.
1001      unsigned Lo16 = getMovi32Value(MI, MI.getOperand(OpIdx),
1002                      ARM::reloc_arm_movw);
1003      // Encode imm which is the same as in emitMOVi32immInstruction().
1004      Binary |= Lo16 & 0xFFF;
1005      Binary |= ((Lo16 >> 12) & 0xF) << 16;
1006      emitWordLE(Binary);
1007      return;
1008  } else if(TID.Opcode == ARM::MOVTi16) {
1009      unsigned Hi16 = (getMovi32Value(MI, MI.getOperand(OpIdx),
1010                       ARM::reloc_arm_movt) >> 16);
1011      Binary |= Hi16 & 0xFFF;
1012      Binary |= ((Hi16 >> 12) & 0xF) << 16;
1013      emitWordLE(Binary);
1014      return;
1015  } else if ((TID.Opcode == ARM::BFC) || (TID.Opcode == ARM::BFI)) {
1016      uint32_t v = ~MI.getOperand(2).getImm();
1017      int32_t lsb = CountTrailingZeros_32(v);
1018      int32_t msb = (32 - CountLeadingZeros_32(v)) - 1;
1019      // Instr{20-16} = msb, Instr{11-7} = lsb
1020      Binary |= (msb & 0x1F) << 16;
1021      Binary |= (lsb & 0x1F) << 7;
1022      emitWordLE(Binary);
1023      return;
1024  } else if ((TID.Opcode == ARM::UBFX) || (TID.Opcode == ARM::SBFX)) {
1025      // Encode Rn in Instr{0-3}
1026      Binary |= getMachineOpValue(MI, OpIdx++);
1027
1028      uint32_t lsb = MI.getOperand(OpIdx++).getImm();
1029      uint32_t widthm1 = MI.getOperand(OpIdx++).getImm() - 1;
1030
1031      // Instr{20-16} = widthm1, Instr{11-7} = lsb
1032      Binary |= (widthm1 & 0x1F) << 16;
1033      Binary |= (lsb & 0x1F) << 7;
1034      emitWordLE(Binary);
1035      return;
1036  }
1037
1038  // If this is a two-address operand, skip it. e.g. MOVCCr operand 1.
1039  if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1040    ++OpIdx;
1041
1042  // Encode first non-shifter register operand if there is one.
1043  bool isUnary = TID.TSFlags & ARMII::UnaryDP;
1044  if (!isUnary) {
1045    if (ImplicitRn)
1046      // Special handling for implicit use (e.g. PC).
1047      Binary |= (getARMRegisterNumbering(ImplicitRn) << ARMII::RegRnShift);
1048    else {
1049      Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRnShift;
1050      ++OpIdx;
1051    }
1052  }
1053
1054  // Encode shifter operand.
1055  const MachineOperand &MO = MI.getOperand(OpIdx);
1056  if ((TID.TSFlags & ARMII::FormMask) == ARMII::DPSoRegFrm) {
1057    // Encode SoReg.
1058    emitWordLE(Binary | getMachineSoRegOpValue(MI, TID, MO, OpIdx));
1059    return;
1060  }
1061
1062  if (MO.isReg()) {
1063    // Encode register Rm.
1064    emitWordLE(Binary | getARMRegisterNumbering(MO.getReg()));
1065    return;
1066  }
1067
1068  // Encode so_imm.
1069  Binary |= getMachineSoImmOpValue((unsigned)MO.getImm());
1070
1071  emitWordLE(Binary);
1072}
1073
1074void ARMCodeEmitter::emitLoadStoreInstruction(const MachineInstr &MI,
1075                                              unsigned ImplicitRd,
1076                                              unsigned ImplicitRn) {
1077  const TargetInstrDesc &TID = MI.getDesc();
1078  unsigned Form = TID.TSFlags & ARMII::FormMask;
1079  bool IsPrePost = (TID.TSFlags & ARMII::IndexModeMask) != 0;
1080
1081  // Part of binary is determined by TableGn.
1082  unsigned Binary = getBinaryCodeForInstr(MI);
1083
1084  // If this is an LDRi12, STRi12 or LDRcp, nothing more needs be done.
1085  if (MI.getOpcode() == ARM::LDRi12 || MI.getOpcode() == ARM::LDRcp ||
1086      MI.getOpcode() == ARM::STRi12) {
1087    emitWordLE(Binary);
1088    return;
1089  }
1090
1091  // Set the conditional execution predicate
1092  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1093
1094  unsigned OpIdx = 0;
1095
1096  // Operand 0 of a pre- and post-indexed store is the address base
1097  // writeback. Skip it.
1098  bool Skipped = false;
1099  if (IsPrePost && Form == ARMII::StFrm) {
1100    ++OpIdx;
1101    Skipped = true;
1102  }
1103
1104  // Set first operand
1105  if (ImplicitRd)
1106    // Special handling for implicit use (e.g. PC).
1107    Binary |= (getARMRegisterNumbering(ImplicitRd) << ARMII::RegRdShift);
1108  else
1109    Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1110
1111  // Set second operand
1112  if (ImplicitRn)
1113    // Special handling for implicit use (e.g. PC).
1114    Binary |= (getARMRegisterNumbering(ImplicitRn) << ARMII::RegRnShift);
1115  else
1116    Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
1117
1118  // If this is a two-address operand, skip it. e.g. LDR_PRE.
1119  if (!Skipped && TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1120    ++OpIdx;
1121
1122  const MachineOperand &MO2 = MI.getOperand(OpIdx);
1123  unsigned AM2Opc = (ImplicitRn == ARM::PC)
1124    ? 0 : MI.getOperand(OpIdx+1).getImm();
1125
1126  // Set bit U(23) according to sign of immed value (positive or negative).
1127  Binary |= ((ARM_AM::getAM2Op(AM2Opc) == ARM_AM::add ? 1 : 0) <<
1128             ARMII::U_BitShift);
1129  if (!MO2.getReg()) { // is immediate
1130    if (ARM_AM::getAM2Offset(AM2Opc))
1131      // Set the value of offset_12 field
1132      Binary |= ARM_AM::getAM2Offset(AM2Opc);
1133    emitWordLE(Binary);
1134    return;
1135  }
1136
1137  // Set bit I(25), because this is not in immediate encoding.
1138  Binary |= 1 << ARMII::I_BitShift;
1139  assert(TargetRegisterInfo::isPhysicalRegister(MO2.getReg()));
1140  // Set bit[3:0] to the corresponding Rm register
1141  Binary |= getARMRegisterNumbering(MO2.getReg());
1142
1143  // If this instr is in scaled register offset/index instruction, set
1144  // shift_immed(bit[11:7]) and shift(bit[6:5]) fields.
1145  if (unsigned ShImm = ARM_AM::getAM2Offset(AM2Opc)) {
1146    Binary |= getShiftOp(AM2Opc) << ARMII::ShiftImmShift;  // shift
1147    Binary |= ShImm              << ARMII::ShiftShift;     // shift_immed
1148  }
1149
1150  emitWordLE(Binary);
1151}
1152
1153void ARMCodeEmitter::emitMiscLoadStoreInstruction(const MachineInstr &MI,
1154                                                  unsigned ImplicitRn) {
1155  const TargetInstrDesc &TID = MI.getDesc();
1156  unsigned Form = TID.TSFlags & ARMII::FormMask;
1157  bool IsPrePost = (TID.TSFlags & ARMII::IndexModeMask) != 0;
1158
1159  // Part of binary is determined by TableGn.
1160  unsigned Binary = getBinaryCodeForInstr(MI);
1161
1162  // Set the conditional execution predicate
1163  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1164
1165  unsigned OpIdx = 0;
1166
1167  // Operand 0 of a pre- and post-indexed store is the address base
1168  // writeback. Skip it.
1169  bool Skipped = false;
1170  if (IsPrePost && Form == ARMII::StMiscFrm) {
1171    ++OpIdx;
1172    Skipped = true;
1173  }
1174
1175  // Set first operand
1176  Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1177
1178  // Skip LDRD and STRD's second operand.
1179  if (TID.Opcode == ARM::LDRD || TID.Opcode == ARM::STRD)
1180    ++OpIdx;
1181
1182  // Set second operand
1183  if (ImplicitRn)
1184    // Special handling for implicit use (e.g. PC).
1185    Binary |= (getARMRegisterNumbering(ImplicitRn) << ARMII::RegRnShift);
1186  else
1187    Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
1188
1189  // If this is a two-address operand, skip it. e.g. LDRH_POST.
1190  if (!Skipped && TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1191    ++OpIdx;
1192
1193  const MachineOperand &MO2 = MI.getOperand(OpIdx);
1194  unsigned AM3Opc = (ImplicitRn == ARM::PC)
1195    ? 0 : MI.getOperand(OpIdx+1).getImm();
1196
1197  // Set bit U(23) according to sign of immed value (positive or negative)
1198  Binary |= ((ARM_AM::getAM3Op(AM3Opc) == ARM_AM::add ? 1 : 0) <<
1199             ARMII::U_BitShift);
1200
1201  // If this instr is in register offset/index encoding, set bit[3:0]
1202  // to the corresponding Rm register.
1203  if (MO2.getReg()) {
1204    Binary |= getARMRegisterNumbering(MO2.getReg());
1205    emitWordLE(Binary);
1206    return;
1207  }
1208
1209  // This instr is in immediate offset/index encoding, set bit 22 to 1.
1210  Binary |= 1 << ARMII::AM3_I_BitShift;
1211  if (unsigned ImmOffs = ARM_AM::getAM3Offset(AM3Opc)) {
1212    // Set operands
1213    Binary |= (ImmOffs >> 4) << ARMII::ImmHiShift;  // immedH
1214    Binary |= (ImmOffs & 0xF);                      // immedL
1215  }
1216
1217  emitWordLE(Binary);
1218}
1219
1220static unsigned getAddrModeUPBits(unsigned Mode) {
1221  unsigned Binary = 0;
1222
1223  // Set addressing mode by modifying bits U(23) and P(24)
1224  // IA - Increment after  - bit U = 1 and bit P = 0
1225  // IB - Increment before - bit U = 1 and bit P = 1
1226  // DA - Decrement after  - bit U = 0 and bit P = 0
1227  // DB - Decrement before - bit U = 0 and bit P = 1
1228  switch (Mode) {
1229  default: llvm_unreachable("Unknown addressing sub-mode!");
1230  case ARM_AM::da:                                     break;
1231  case ARM_AM::db: Binary |= 0x1 << ARMII::P_BitShift; break;
1232  case ARM_AM::ia: Binary |= 0x1 << ARMII::U_BitShift; break;
1233  case ARM_AM::ib: Binary |= 0x3 << ARMII::U_BitShift; break;
1234  }
1235
1236  return Binary;
1237}
1238
1239void ARMCodeEmitter::emitLoadStoreMultipleInstruction(const MachineInstr &MI) {
1240  const TargetInstrDesc &TID = MI.getDesc();
1241  bool IsUpdating = (TID.TSFlags & ARMII::IndexModeMask) != 0;
1242
1243  // Part of binary is determined by TableGn.
1244  unsigned Binary = getBinaryCodeForInstr(MI);
1245
1246  // Set the conditional execution predicate
1247  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1248
1249  // Skip operand 0 of an instruction with base register update.
1250  unsigned OpIdx = 0;
1251  if (IsUpdating)
1252    ++OpIdx;
1253
1254  // Set base address operand
1255  Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
1256
1257  // Set addressing mode by modifying bits U(23) and P(24)
1258  const MachineOperand &MO = MI.getOperand(OpIdx++);
1259  Binary |= getAddrModeUPBits(ARM_AM::getAM4SubMode(MO.getImm()));
1260
1261  // Set bit W(21)
1262  if (IsUpdating)
1263    Binary |= 0x1 << ARMII::W_BitShift;
1264
1265  // Set registers
1266  for (unsigned i = OpIdx+2, e = MI.getNumOperands(); i != e; ++i) {
1267    const MachineOperand &MO = MI.getOperand(i);
1268    if (!MO.isReg() || MO.isImplicit())
1269      break;
1270    unsigned RegNum = getARMRegisterNumbering(MO.getReg());
1271    assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()) &&
1272           RegNum < 16);
1273    Binary |= 0x1 << RegNum;
1274  }
1275
1276  emitWordLE(Binary);
1277}
1278
1279void ARMCodeEmitter::emitMulFrmInstruction(const MachineInstr &MI) {
1280  const TargetInstrDesc &TID = MI.getDesc();
1281
1282  // Part of binary is determined by TableGn.
1283  unsigned Binary = getBinaryCodeForInstr(MI);
1284
1285  // Set the conditional execution predicate
1286  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1287
1288  // Encode S bit if MI modifies CPSR.
1289  Binary |= getAddrModeSBit(MI, TID);
1290
1291  // 32x32->64bit operations have two destination registers. The number
1292  // of register definitions will tell us if that's what we're dealing with.
1293  unsigned OpIdx = 0;
1294  if (TID.getNumDefs() == 2)
1295    Binary |= getMachineOpValue (MI, OpIdx++) << ARMII::RegRdLoShift;
1296
1297  // Encode Rd
1298  Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdHiShift;
1299
1300  // Encode Rm
1301  Binary |= getMachineOpValue(MI, OpIdx++);
1302
1303  // Encode Rs
1304  Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRsShift;
1305
1306  // Many multiple instructions (e.g. MLA) have three src operands. Encode
1307  // it as Rn (for multiply, that's in the same offset as RdLo.
1308  if (TID.getNumOperands() > OpIdx &&
1309      !TID.OpInfo[OpIdx].isPredicate() &&
1310      !TID.OpInfo[OpIdx].isOptionalDef())
1311    Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRdLoShift;
1312
1313  emitWordLE(Binary);
1314}
1315
1316void ARMCodeEmitter::emitExtendInstruction(const MachineInstr &MI) {
1317  const TargetInstrDesc &TID = MI.getDesc();
1318
1319  // Part of binary is determined by TableGn.
1320  unsigned Binary = getBinaryCodeForInstr(MI);
1321
1322  // Set the conditional execution predicate
1323  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1324
1325  unsigned OpIdx = 0;
1326
1327  // Encode Rd
1328  Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1329
1330  const MachineOperand &MO1 = MI.getOperand(OpIdx++);
1331  const MachineOperand &MO2 = MI.getOperand(OpIdx);
1332  if (MO2.isReg()) {
1333    // Two register operand form.
1334    // Encode Rn.
1335    Binary |= getMachineOpValue(MI, MO1) << ARMII::RegRnShift;
1336
1337    // Encode Rm.
1338    Binary |= getMachineOpValue(MI, MO2);
1339    ++OpIdx;
1340  } else {
1341    Binary |= getMachineOpValue(MI, MO1);
1342  }
1343
1344  // Encode rot imm (0, 8, 16, or 24) if it has a rotate immediate operand.
1345  if (MI.getOperand(OpIdx).isImm() &&
1346      !TID.OpInfo[OpIdx].isPredicate() &&
1347      !TID.OpInfo[OpIdx].isOptionalDef())
1348    Binary |= (getMachineOpValue(MI, OpIdx) / 8) << ARMII::ExtRotImmShift;
1349
1350  emitWordLE(Binary);
1351}
1352
1353void ARMCodeEmitter::emitMiscArithInstruction(const MachineInstr &MI) {
1354  const TargetInstrDesc &TID = MI.getDesc();
1355
1356  // Part of binary is determined by TableGn.
1357  unsigned Binary = getBinaryCodeForInstr(MI);
1358
1359  // Set the conditional execution predicate
1360  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1361
1362  unsigned OpIdx = 0;
1363
1364  // Encode Rd
1365  Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1366
1367  const MachineOperand &MO = MI.getOperand(OpIdx++);
1368  if (OpIdx == TID.getNumOperands() ||
1369      TID.OpInfo[OpIdx].isPredicate() ||
1370      TID.OpInfo[OpIdx].isOptionalDef()) {
1371    // Encode Rm and it's done.
1372    Binary |= getMachineOpValue(MI, MO);
1373    emitWordLE(Binary);
1374    return;
1375  }
1376
1377  // Encode Rn.
1378  Binary |= getMachineOpValue(MI, MO) << ARMII::RegRnShift;
1379
1380  // Encode Rm.
1381  Binary |= getMachineOpValue(MI, OpIdx++);
1382
1383  // Encode shift_imm.
1384  unsigned ShiftAmt = MI.getOperand(OpIdx).getImm();
1385  if (TID.Opcode == ARM::PKHTB) {
1386    assert(ShiftAmt != 0 && "PKHTB shift_imm is 0!");
1387    if (ShiftAmt == 32)
1388      ShiftAmt = 0;
1389  }
1390  assert(ShiftAmt < 32 && "shift_imm range is 0 to 31!");
1391  Binary |= ShiftAmt << ARMII::ShiftShift;
1392
1393  emitWordLE(Binary);
1394}
1395
1396void ARMCodeEmitter::emitSaturateInstruction(const MachineInstr &MI) {
1397  const TargetInstrDesc &TID = MI.getDesc();
1398
1399  // Part of binary is determined by TableGen.
1400  unsigned Binary = getBinaryCodeForInstr(MI);
1401
1402  // Set the conditional execution predicate
1403  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1404
1405  // Encode Rd
1406  Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
1407
1408  // Encode saturate bit position.
1409  unsigned Pos = MI.getOperand(1).getImm();
1410  if (TID.Opcode == ARM::SSAT || TID.Opcode == ARM::SSAT16)
1411    Pos -= 1;
1412  assert((Pos < 16 || (Pos < 32 &&
1413                       TID.Opcode != ARM::SSAT16 &&
1414                       TID.Opcode != ARM::USAT16)) &&
1415         "saturate bit position out of range");
1416  Binary |= Pos << 16;
1417
1418  // Encode Rm
1419  Binary |= getMachineOpValue(MI, 2);
1420
1421  // Encode shift_imm.
1422  if (TID.getNumOperands() == 4) {
1423    unsigned ShiftOp = MI.getOperand(3).getImm();
1424    ARM_AM::ShiftOpc Opc = ARM_AM::getSORegShOp(ShiftOp);
1425    if (Opc == ARM_AM::asr)
1426      Binary |= (1 << 6);
1427    unsigned ShiftAmt = MI.getOperand(3).getImm();
1428    if (ShiftAmt == 32 && Opc == ARM_AM::asr)
1429      ShiftAmt = 0;
1430    assert(ShiftAmt < 32 && "shift_imm range is 0 to 31!");
1431    Binary |= ShiftAmt << ARMII::ShiftShift;
1432  }
1433
1434  emitWordLE(Binary);
1435}
1436
1437void ARMCodeEmitter::emitBranchInstruction(const MachineInstr &MI) {
1438  const TargetInstrDesc &TID = MI.getDesc();
1439
1440  if (TID.Opcode == ARM::TPsoft) {
1441    llvm_unreachable("ARM::TPsoft FIXME"); // FIXME
1442  }
1443
1444  // Part of binary is determined by TableGn.
1445  unsigned Binary = getBinaryCodeForInstr(MI);
1446
1447  // Set the conditional execution predicate
1448  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1449
1450  // Set signed_immed_24 field
1451  Binary |= getMachineOpValue(MI, 0);
1452
1453  emitWordLE(Binary);
1454}
1455
1456void ARMCodeEmitter::emitInlineJumpTable(unsigned JTIndex) {
1457  // Remember the base address of the inline jump table.
1458  uintptr_t JTBase = MCE.getCurrentPCValue();
1459  JTI->addJumpTableBaseAddr(JTIndex, JTBase);
1460  DEBUG(errs() << "  ** Jump Table #" << JTIndex << " @ " << (void*)JTBase
1461               << '\n');
1462
1463  // Now emit the jump table entries.
1464  const std::vector<MachineBasicBlock*> &MBBs = (*MJTEs)[JTIndex].MBBs;
1465  for (unsigned i = 0, e = MBBs.size(); i != e; ++i) {
1466    if (IsPIC)
1467      // DestBB address - JT base.
1468      emitMachineBasicBlock(MBBs[i], ARM::reloc_arm_pic_jt, JTBase);
1469    else
1470      // Absolute DestBB address.
1471      emitMachineBasicBlock(MBBs[i], ARM::reloc_arm_absolute);
1472    emitWordLE(0);
1473  }
1474}
1475
1476void ARMCodeEmitter::emitMiscBranchInstruction(const MachineInstr &MI) {
1477  const TargetInstrDesc &TID = MI.getDesc();
1478
1479  // Handle jump tables.
1480  if (TID.Opcode == ARM::BR_JTr || TID.Opcode == ARM::BR_JTadd) {
1481    // First emit a ldr pc, [] instruction.
1482    emitDataProcessingInstruction(MI, ARM::PC);
1483
1484    // Then emit the inline jump table.
1485    unsigned JTIndex =
1486      (TID.Opcode == ARM::BR_JTr)
1487      ? MI.getOperand(1).getIndex() : MI.getOperand(2).getIndex();
1488    emitInlineJumpTable(JTIndex);
1489    return;
1490  } else if (TID.Opcode == ARM::BR_JTm) {
1491    // First emit a ldr pc, [] instruction.
1492    emitLoadStoreInstruction(MI, ARM::PC);
1493
1494    // Then emit the inline jump table.
1495    emitInlineJumpTable(MI.getOperand(3).getIndex());
1496    return;
1497  }
1498
1499  // Part of binary is determined by TableGn.
1500  unsigned Binary = getBinaryCodeForInstr(MI);
1501
1502  // Set the conditional execution predicate
1503  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1504
1505  if (TID.Opcode == ARM::BX_RET || TID.Opcode == ARM::MOVPCLR)
1506    // The return register is LR.
1507    Binary |= getARMRegisterNumbering(ARM::LR);
1508  else
1509    // otherwise, set the return register
1510    Binary |= getMachineOpValue(MI, 0);
1511
1512  emitWordLE(Binary);
1513}
1514
1515static unsigned encodeVFPRd(const MachineInstr &MI, unsigned OpIdx) {
1516  unsigned RegD = MI.getOperand(OpIdx).getReg();
1517  unsigned Binary = 0;
1518  bool isSPVFP = ARM::SPRRegisterClass->contains(RegD);
1519  RegD = getARMRegisterNumbering(RegD);
1520  if (!isSPVFP) {
1521    Binary |=  (RegD & 0x0F)       << ARMII::RegRdShift;
1522    Binary |= ((RegD & 0x10) >> 4) << ARMII::D_BitShift;
1523  } else {
1524    Binary |= ((RegD & 0x1E) >> 1) << ARMII::RegRdShift;
1525    Binary |=  (RegD & 0x01)       << ARMII::D_BitShift;
1526  }
1527  return Binary;
1528}
1529
1530static unsigned encodeVFPRn(const MachineInstr &MI, unsigned OpIdx) {
1531  unsigned RegN = MI.getOperand(OpIdx).getReg();
1532  unsigned Binary = 0;
1533  bool isSPVFP = ARM::SPRRegisterClass->contains(RegN);
1534  RegN = getARMRegisterNumbering(RegN);
1535  if (!isSPVFP) {
1536    Binary |=  (RegN & 0x0F)       << ARMII::RegRnShift;
1537    Binary |= ((RegN & 0x10) >> 4) << ARMII::N_BitShift;
1538  } else {
1539    Binary |= ((RegN & 0x1E) >> 1) << ARMII::RegRnShift;
1540    Binary |=  (RegN & 0x01)       << ARMII::N_BitShift;
1541  }
1542  return Binary;
1543}
1544
1545static unsigned encodeVFPRm(const MachineInstr &MI, unsigned OpIdx) {
1546  unsigned RegM = MI.getOperand(OpIdx).getReg();
1547  unsigned Binary = 0;
1548  bool isSPVFP = ARM::SPRRegisterClass->contains(RegM);
1549  RegM = getARMRegisterNumbering(RegM);
1550  if (!isSPVFP) {
1551    Binary |=  (RegM & 0x0F);
1552    Binary |= ((RegM & 0x10) >> 4) << ARMII::M_BitShift;
1553  } else {
1554    Binary |= ((RegM & 0x1E) >> 1);
1555    Binary |=  (RegM & 0x01)       << ARMII::M_BitShift;
1556  }
1557  return Binary;
1558}
1559
1560void ARMCodeEmitter::emitVFPArithInstruction(const MachineInstr &MI) {
1561  const TargetInstrDesc &TID = MI.getDesc();
1562
1563  // Part of binary is determined by TableGn.
1564  unsigned Binary = getBinaryCodeForInstr(MI);
1565
1566  // Set the conditional execution predicate
1567  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1568
1569  unsigned OpIdx = 0;
1570
1571  // Encode Dd / Sd.
1572  Binary |= encodeVFPRd(MI, OpIdx++);
1573
1574  // If this is a two-address operand, skip it, e.g. FMACD.
1575  if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1576    ++OpIdx;
1577
1578  // Encode Dn / Sn.
1579  if ((TID.TSFlags & ARMII::FormMask) == ARMII::VFPBinaryFrm)
1580    Binary |= encodeVFPRn(MI, OpIdx++);
1581
1582  if (OpIdx == TID.getNumOperands() ||
1583      TID.OpInfo[OpIdx].isPredicate() ||
1584      TID.OpInfo[OpIdx].isOptionalDef()) {
1585    // FCMPEZD etc. has only one operand.
1586    emitWordLE(Binary);
1587    return;
1588  }
1589
1590  // Encode Dm / Sm.
1591  Binary |= encodeVFPRm(MI, OpIdx);
1592
1593  emitWordLE(Binary);
1594}
1595
1596void ARMCodeEmitter::emitVFPConversionInstruction(const MachineInstr &MI) {
1597  const TargetInstrDesc &TID = MI.getDesc();
1598  unsigned Form = TID.TSFlags & ARMII::FormMask;
1599
1600  // Part of binary is determined by TableGn.
1601  unsigned Binary = getBinaryCodeForInstr(MI);
1602
1603  // Set the conditional execution predicate
1604  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1605
1606  switch (Form) {
1607  default: break;
1608  case ARMII::VFPConv1Frm:
1609  case ARMII::VFPConv2Frm:
1610  case ARMII::VFPConv3Frm:
1611    // Encode Dd / Sd.
1612    Binary |= encodeVFPRd(MI, 0);
1613    break;
1614  case ARMII::VFPConv4Frm:
1615    // Encode Dn / Sn.
1616    Binary |= encodeVFPRn(MI, 0);
1617    break;
1618  case ARMII::VFPConv5Frm:
1619    // Encode Dm / Sm.
1620    Binary |= encodeVFPRm(MI, 0);
1621    break;
1622  }
1623
1624  switch (Form) {
1625  default: break;
1626  case ARMII::VFPConv1Frm:
1627    // Encode Dm / Sm.
1628    Binary |= encodeVFPRm(MI, 1);
1629    break;
1630  case ARMII::VFPConv2Frm:
1631  case ARMII::VFPConv3Frm:
1632    // Encode Dn / Sn.
1633    Binary |= encodeVFPRn(MI, 1);
1634    break;
1635  case ARMII::VFPConv4Frm:
1636  case ARMII::VFPConv5Frm:
1637    // Encode Dd / Sd.
1638    Binary |= encodeVFPRd(MI, 1);
1639    break;
1640  }
1641
1642  if (Form == ARMII::VFPConv5Frm)
1643    // Encode Dn / Sn.
1644    Binary |= encodeVFPRn(MI, 2);
1645  else if (Form == ARMII::VFPConv3Frm)
1646    // Encode Dm / Sm.
1647    Binary |= encodeVFPRm(MI, 2);
1648
1649  emitWordLE(Binary);
1650}
1651
1652void ARMCodeEmitter::emitVFPLoadStoreInstruction(const MachineInstr &MI) {
1653  // Part of binary is determined by TableGn.
1654  unsigned Binary = getBinaryCodeForInstr(MI);
1655
1656  // Set the conditional execution predicate
1657  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1658
1659  if (MI.getOpcode() == ARM::VLDRS || MI.getOpcode() == ARM::VLDRD ||
1660      MI.getOpcode() == ARM::VSTRS || MI.getOpcode() == ARM::VSTRD){
1661    emitWordLE(Binary);
1662    return;
1663  }
1664
1665  unsigned OpIdx = 0;
1666
1667  // Encode Dd / Sd.
1668  Binary |= encodeVFPRd(MI, OpIdx++);
1669
1670  // Encode address base.
1671  const MachineOperand &Base = MI.getOperand(OpIdx++);
1672  Binary |= getMachineOpValue(MI, Base) << ARMII::RegRnShift;
1673
1674  // If there is a non-zero immediate offset, encode it.
1675  if (Base.isReg()) {
1676    const MachineOperand &Offset = MI.getOperand(OpIdx);
1677    if (unsigned ImmOffs = ARM_AM::getAM5Offset(Offset.getImm())) {
1678      if (ARM_AM::getAM5Op(Offset.getImm()) == ARM_AM::add)
1679        Binary |= 1 << ARMII::U_BitShift;
1680      Binary |= ImmOffs;
1681      emitWordLE(Binary);
1682      return;
1683    }
1684  }
1685
1686  // If immediate offset is omitted, default to +0.
1687  Binary |= 1 << ARMII::U_BitShift;
1688
1689  emitWordLE(Binary);
1690}
1691
1692void
1693ARMCodeEmitter::emitVFPLoadStoreMultipleInstruction(const MachineInstr &MI) {
1694  const TargetInstrDesc &TID = MI.getDesc();
1695  bool IsUpdating = (TID.TSFlags & ARMII::IndexModeMask) != 0;
1696
1697  // Part of binary is determined by TableGn.
1698  unsigned Binary = getBinaryCodeForInstr(MI);
1699
1700  // Set the conditional execution predicate
1701  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1702
1703  // Skip operand 0 of an instruction with base register update.
1704  unsigned OpIdx = 0;
1705  if (IsUpdating)
1706    ++OpIdx;
1707
1708  // Set base address operand
1709  Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
1710
1711  // Set addressing mode by modifying bits U(23) and P(24)
1712  const MachineOperand &MO = MI.getOperand(OpIdx++);
1713  Binary |= getAddrModeUPBits(ARM_AM::getAM4SubMode(MO.getImm()));
1714
1715  // Set bit W(21)
1716  if (IsUpdating)
1717    Binary |= 0x1 << ARMII::W_BitShift;
1718
1719  // First register is encoded in Dd.
1720  Binary |= encodeVFPRd(MI, OpIdx+2);
1721
1722  // Count the number of registers.
1723  unsigned NumRegs = 1;
1724  for (unsigned i = OpIdx+3, e = MI.getNumOperands(); i != e; ++i) {
1725    const MachineOperand &MO = MI.getOperand(i);
1726    if (!MO.isReg() || MO.isImplicit())
1727      break;
1728    ++NumRegs;
1729  }
1730  // Bit 8 will be set if <list> is consecutive 64-bit registers (e.g., D0)
1731  // Otherwise, it will be 0, in the case of 32-bit registers.
1732  if(Binary & 0x100)
1733    Binary |= NumRegs * 2;
1734  else
1735    Binary |= NumRegs;
1736
1737  emitWordLE(Binary);
1738}
1739
1740void ARMCodeEmitter::emitMiscInstruction(const MachineInstr &MI) {
1741  unsigned Opcode = MI.getDesc().Opcode;
1742  // Part of binary is determined by TableGn.
1743  unsigned Binary = getBinaryCodeForInstr(MI);
1744
1745  // Set the conditional execution predicate
1746  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1747
1748  emitWordLE(Binary);
1749}
1750
1751static unsigned encodeNEONRd(const MachineInstr &MI, unsigned OpIdx) {
1752  unsigned RegD = MI.getOperand(OpIdx).getReg();
1753  unsigned Binary = 0;
1754  RegD = getARMRegisterNumbering(RegD);
1755  Binary |= (RegD & 0xf) << ARMII::RegRdShift;
1756  Binary |= ((RegD >> 4) & 1) << ARMII::D_BitShift;
1757  return Binary;
1758}
1759
1760static unsigned encodeNEONRn(const MachineInstr &MI, unsigned OpIdx) {
1761  unsigned RegN = MI.getOperand(OpIdx).getReg();
1762  unsigned Binary = 0;
1763  RegN = getARMRegisterNumbering(RegN);
1764  Binary |= (RegN & 0xf) << ARMII::RegRnShift;
1765  Binary |= ((RegN >> 4) & 1) << ARMII::N_BitShift;
1766  return Binary;
1767}
1768
1769static unsigned encodeNEONRm(const MachineInstr &MI, unsigned OpIdx) {
1770  unsigned RegM = MI.getOperand(OpIdx).getReg();
1771  unsigned Binary = 0;
1772  RegM = getARMRegisterNumbering(RegM);
1773  Binary |= (RegM & 0xf);
1774  Binary |= ((RegM >> 4) & 1) << ARMII::M_BitShift;
1775  return Binary;
1776}
1777
1778/// convertNEONDataProcToThumb - Convert the ARM mode encoding for a NEON
1779/// data-processing instruction to the corresponding Thumb encoding.
1780static unsigned convertNEONDataProcToThumb(unsigned Binary) {
1781  assert((Binary & 0xfe000000) == 0xf2000000 &&
1782         "not an ARM NEON data-processing instruction");
1783  unsigned UBit = (Binary >> 24) & 1;
1784  return 0xef000000 | (UBit << 28) | (Binary & 0xffffff);
1785}
1786
1787void ARMCodeEmitter::emitNEONLaneInstruction(const MachineInstr &MI) {
1788  unsigned Binary = getBinaryCodeForInstr(MI);
1789
1790  unsigned RegTOpIdx, RegNOpIdx, LnOpIdx;
1791  const TargetInstrDesc &TID = MI.getDesc();
1792  if ((TID.TSFlags & ARMII::FormMask) == ARMII::NGetLnFrm) {
1793    RegTOpIdx = 0;
1794    RegNOpIdx = 1;
1795    LnOpIdx = 2;
1796  } else { // ARMII::NSetLnFrm
1797    RegTOpIdx = 2;
1798    RegNOpIdx = 0;
1799    LnOpIdx = 3;
1800  }
1801
1802  // Set the conditional execution predicate
1803  Binary |= (IsThumb ? ARMCC::AL : II->getPredicate(&MI)) << ARMII::CondShift;
1804
1805  unsigned RegT = MI.getOperand(RegTOpIdx).getReg();
1806  RegT = getARMRegisterNumbering(RegT);
1807  Binary |= (RegT << ARMII::RegRdShift);
1808  Binary |= encodeNEONRn(MI, RegNOpIdx);
1809
1810  unsigned LaneShift;
1811  if ((Binary & (1 << 22)) != 0)
1812    LaneShift = 0; // 8-bit elements
1813  else if ((Binary & (1 << 5)) != 0)
1814    LaneShift = 1; // 16-bit elements
1815  else
1816    LaneShift = 2; // 32-bit elements
1817
1818  unsigned Lane = MI.getOperand(LnOpIdx).getImm() << LaneShift;
1819  unsigned Opc1 = Lane >> 2;
1820  unsigned Opc2 = Lane & 3;
1821  assert((Opc1 & 3) == 0 && "out-of-range lane number operand");
1822  Binary |= (Opc1 << 21);
1823  Binary |= (Opc2 << 5);
1824
1825  emitWordLE(Binary);
1826}
1827
1828void ARMCodeEmitter::emitNEONDupInstruction(const MachineInstr &MI) {
1829  unsigned Binary = getBinaryCodeForInstr(MI);
1830
1831  // Set the conditional execution predicate
1832  Binary |= (IsThumb ? ARMCC::AL : II->getPredicate(&MI)) << ARMII::CondShift;
1833
1834  unsigned RegT = MI.getOperand(1).getReg();
1835  RegT = getARMRegisterNumbering(RegT);
1836  Binary |= (RegT << ARMII::RegRdShift);
1837  Binary |= encodeNEONRn(MI, 0);
1838  emitWordLE(Binary);
1839}
1840
1841void ARMCodeEmitter::emitNEON1RegModImmInstruction(const MachineInstr &MI) {
1842  unsigned Binary = getBinaryCodeForInstr(MI);
1843  // Destination register is encoded in Dd.
1844  Binary |= encodeNEONRd(MI, 0);
1845  // Immediate fields: Op, Cmode, I, Imm3, Imm4
1846  unsigned Imm = MI.getOperand(1).getImm();
1847  unsigned Op = (Imm >> 12) & 1;
1848  unsigned Cmode = (Imm >> 8) & 0xf;
1849  unsigned I = (Imm >> 7) & 1;
1850  unsigned Imm3 = (Imm >> 4) & 0x7;
1851  unsigned Imm4 = Imm & 0xf;
1852  Binary |= (I << 24) | (Imm3 << 16) | (Cmode << 8) | (Op << 5) | Imm4;
1853  if (IsThumb)
1854    Binary = convertNEONDataProcToThumb(Binary);
1855  emitWordLE(Binary);
1856}
1857
1858void ARMCodeEmitter::emitNEON2RegInstruction(const MachineInstr &MI) {
1859  const TargetInstrDesc &TID = MI.getDesc();
1860  unsigned Binary = getBinaryCodeForInstr(MI);
1861  // Destination register is encoded in Dd; source register in Dm.
1862  unsigned OpIdx = 0;
1863  Binary |= encodeNEONRd(MI, OpIdx++);
1864  if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1865    ++OpIdx;
1866  Binary |= encodeNEONRm(MI, OpIdx);
1867  if (IsThumb)
1868    Binary = convertNEONDataProcToThumb(Binary);
1869  // FIXME: This does not handle VDUPfdf or VDUPfqf.
1870  emitWordLE(Binary);
1871}
1872
1873void ARMCodeEmitter::emitNEON3RegInstruction(const MachineInstr &MI) {
1874  const TargetInstrDesc &TID = MI.getDesc();
1875  unsigned Binary = getBinaryCodeForInstr(MI);
1876  // Destination register is encoded in Dd; source registers in Dn and Dm.
1877  unsigned OpIdx = 0;
1878  Binary |= encodeNEONRd(MI, OpIdx++);
1879  if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1880    ++OpIdx;
1881  Binary |= encodeNEONRn(MI, OpIdx++);
1882  if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1883    ++OpIdx;
1884  Binary |= encodeNEONRm(MI, OpIdx);
1885  if (IsThumb)
1886    Binary = convertNEONDataProcToThumb(Binary);
1887  // FIXME: This does not handle VMOVDneon or VMOVQ.
1888  emitWordLE(Binary);
1889}
1890
1891#include "ARMGenCodeEmitter.inc"
1892