ARMCodeEmitter.cpp revision 3341262de27dad5e1f983fe072a749356a8f3c78 
1//===-- ARM/ARMCodeEmitter.cpp - Convert ARM code to machine code ---------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the pass that transforms the ARM machine instructions into
11// relocatable machine code.
12//
13//===----------------------------------------------------------------------===//
14
15#define DEBUG_TYPE "arm-emitter"
16#include "ARM.h"
17#include "ARMAddressingModes.h"
18#include "ARMInstrInfo.h"
19#include "ARMRelocations.h"
20#include "ARMSubtarget.h"
21#include "ARMTargetMachine.h"
22#include "llvm/Function.h"
23#include "llvm/PassManager.h"
24#include "llvm/CodeGen/MachineCodeEmitter.h"
25#include "llvm/CodeGen/MachineConstantPool.h"
26#include "llvm/CodeGen/MachineFunctionPass.h"
27#include "llvm/CodeGen/MachineInstr.h"
28#include "llvm/CodeGen/Passes.h"
29#include "llvm/ADT/Statistic.h"
30#include "llvm/Support/Compiler.h"
31#include "llvm/Support/Debug.h"
32using namespace llvm;
33
34STATISTIC(NumEmitted, "Number of machine instructions emitted");
35
36namespace {
37  class VISIBILITY_HIDDEN ARMCodeEmitter : public MachineFunctionPass {
38    ARMJITInfo                *JTI;
39    const ARMInstrInfo        *II;
40    const TargetData          *TD;
41    TargetMachine             &TM;
42    MachineCodeEmitter        &MCE;
43    const MachineConstantPool *MCP;
44  public:
45    static char ID;
46    explicit ARMCodeEmitter(TargetMachine &tm, MachineCodeEmitter &mce)
47      : MachineFunctionPass(&ID), JTI(0), II(0), TD(0), TM(tm),
48      MCE(mce), MCP(0) {}
49    ARMCodeEmitter(TargetMachine &tm, MachineCodeEmitter &mce,
50            const ARMInstrInfo &ii, const TargetData &td)
51      : MachineFunctionPass(&ID), JTI(0), II(&ii), TD(&td), TM(tm),
52      MCE(mce), MCP(0) {}
53
54    bool runOnMachineFunction(MachineFunction &MF);
55
56    virtual const char *getPassName() const {
57      return "ARM Machine Code Emitter";
58    }
59
60    void emitInstruction(const MachineInstr &MI);
61
62  private:
63
64    void emitConstPoolInstruction(const MachineInstr &MI);
65
66    void emitPseudoInstruction(const MachineInstr &MI);
67
68    unsigned getAddrModeNoneInstrBinary(const MachineInstr &MI,
69                                        const TargetInstrDesc &TID,
70                                        unsigned Binary);
71
72    unsigned getMachineSoRegOpValue(const MachineInstr &MI,
73                                    const TargetInstrDesc &TID,
74                                    unsigned OpIdx);
75
76    unsigned getAddrMode1SBit(const MachineInstr &MI,
77                              const TargetInstrDesc &TID) const;
78
79    unsigned getAddrMode1InstrBinary(const MachineInstr &MI,
80                                     const TargetInstrDesc &TID,
81                                     unsigned Binary);
82    unsigned getAddrMode2InstrBinary(const MachineInstr &MI,
83                                     const TargetInstrDesc &TID,
84                                     unsigned Binary);
85    unsigned getAddrMode3InstrBinary(const MachineInstr &MI,
86                                     const TargetInstrDesc &TID,
87                                     unsigned Binary);
88    unsigned getAddrMode4InstrBinary(const MachineInstr &MI,
89                                     const TargetInstrDesc &TID,
90                                     unsigned Binary);
91
92    /// getInstrBinary - Return binary encoding for the specified
93    /// machine instruction.
94    unsigned getInstrBinary(const MachineInstr &MI);
95
96    /// getBinaryCodeForInstr - This function, generated by the
97    /// CodeEmitterGenerator using TableGen, produces the binary encoding for
98    /// machine instructions.
99    ///
100    unsigned getBinaryCodeForInstr(const MachineInstr &MI);
101
102    /// getMachineOpValue - Return binary encoding of operand. If the machine
103    /// operand requires relocation, record the relocation and return zero.
104    unsigned getMachineOpValue(const MachineInstr &MI, unsigned OpIdx) {
105      return getMachineOpValue(MI, MI.getOperand(OpIdx));
106    }
107    unsigned getMachineOpValue(const MachineInstr &MI,
108                               const MachineOperand &MO);
109
110    /// getBaseOpcodeFor - Return the opcode value.
111    ///
112    unsigned getBaseOpcodeFor(const TargetInstrDesc &TID) const {
113      return (TID.TSFlags & ARMII::OpcodeMask) >> ARMII::OpcodeShift;
114    }
115
116    /// getShiftOp - Return the shift opcode (bit[6:5]) of the machine operand.
117    ///
118    unsigned getShiftOp(const MachineOperand &MO) const ;
119
120    /// Routines that handle operands which add machine relocations which are
121    /// fixed up by the JIT fixup stage.
122    void emitGlobalAddress(GlobalValue *GV, unsigned Reloc,
123                           bool NeedStub);
124    void emitExternalSymbolAddress(const char *ES, unsigned Reloc);
125    void emitConstPoolAddress(unsigned CPI, unsigned Reloc,
126                              int Disp = 0, unsigned PCAdj = 0 );
127    void emitJumpTableAddress(unsigned JTIndex, unsigned Reloc,
128                              unsigned PCAdj = 0);
129    void emitGlobalConstant(const Constant *CV);
130    void emitMachineBasicBlock(MachineBasicBlock *BB);
131  };
132  char ARMCodeEmitter::ID = 0;
133}
134
135/// createARMCodeEmitterPass - Return a pass that emits the collected ARM code
136/// to the specified MCE object.
137FunctionPass *llvm::createARMCodeEmitterPass(ARMTargetMachine &TM,
138                                             MachineCodeEmitter &MCE) {
139  return new ARMCodeEmitter(TM, MCE);
140}
141
142bool ARMCodeEmitter::runOnMachineFunction(MachineFunction &MF) {
143  assert((MF.getTarget().getRelocationModel() != Reloc::Default ||
144          MF.getTarget().getRelocationModel() != Reloc::Static) &&
145         "JIT relocation model must be set to static or default!");
146  II = ((ARMTargetMachine&)MF.getTarget()).getInstrInfo();
147  TD = ((ARMTargetMachine&)MF.getTarget()).getTargetData();
148  JTI = ((ARMTargetMachine&)MF.getTarget()).getJITInfo();
149  MCP = MF.getConstantPool();
150
151  do {
152    DOUT << "JITTing function '" << MF.getFunction()->getName() << "'\n";
153    MCE.startFunction(MF);
154    for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();
155         MBB != E; ++MBB) {
156      MCE.StartMachineBasicBlock(MBB);
157      for (MachineBasicBlock::const_iterator I = MBB->begin(), E = MBB->end();
158           I != E; ++I)
159        emitInstruction(*I);
160    }
161  } while (MCE.finishFunction(MF));
162
163  return false;
164}
165
166/// getShiftOp - Return the shift opcode (bit[6:5]) of the machine operand.
167///
168unsigned ARMCodeEmitter::getShiftOp(const MachineOperand &MO) const {
169  switch (ARM_AM::getAM2ShiftOpc(MO.getImm())) {
170  default: assert(0 && "Unknown shift opc!");
171  case ARM_AM::asr: return 2;
172  case ARM_AM::lsl: return 0;
173  case ARM_AM::lsr: return 1;
174  case ARM_AM::ror:
175  case ARM_AM::rrx: return 3;
176  }
177  return 0;
178}
179
180/// getMachineOpValue - Return binary encoding of operand. If the machine
181/// operand requires relocation, record the relocation and return zero.
182unsigned ARMCodeEmitter::getMachineOpValue(const MachineInstr &MI,
183                                           const MachineOperand &MO) {
184  if (MO.isReg())
185    return ARMRegisterInfo::getRegisterNumbering(MO.getReg());
186  else if (MO.isImm())
187    return static_cast<unsigned>(MO.getImm());
188  else if (MO.isGlobal())
189    emitGlobalAddress(MO.getGlobal(), ARM::reloc_arm_branch, true);
190  else if (MO.isSymbol())
191    emitExternalSymbolAddress(MO.getSymbolName(), ARM::reloc_arm_relative);
192  else if (MO.isCPI())
193    emitConstPoolAddress(MO.getIndex(), ARM::reloc_arm_relative);
194  else if (MO.isJTI())
195    emitJumpTableAddress(MO.getIndex(), ARM::reloc_arm_relative);
196  else if (MO.isMBB())
197    emitMachineBasicBlock(MO.getMBB());
198  else {
199    cerr << "ERROR: Unknown type of MachineOperand: " << MO << "\n";
200    abort();
201  }
202  return 0;
203}
204
205/// emitGlobalAddress - Emit the specified address to the code stream.
206///
207void ARMCodeEmitter::emitGlobalAddress(GlobalValue *GV,
208                                       unsigned Reloc, bool NeedStub) {
209  MCE.addRelocation(MachineRelocation::getGV(MCE.getCurrentPCOffset(),
210                                             Reloc, GV, 0, NeedStub));
211}
212
213/// emitExternalSymbolAddress - Arrange for the address of an external symbol to
214/// be emitted to the current location in the function, and allow it to be PC
215/// relative.
216void ARMCodeEmitter::emitExternalSymbolAddress(const char *ES, unsigned Reloc) {
217  MCE.addRelocation(MachineRelocation::getExtSym(MCE.getCurrentPCOffset(),
218                                                 Reloc, ES));
219}
220
221/// emitConstPoolAddress - Arrange for the address of an constant pool
222/// to be emitted to the current location in the function, and allow it to be PC
223/// relative.
224void ARMCodeEmitter::emitConstPoolAddress(unsigned CPI, unsigned Reloc,
225                                          int Disp /* = 0 */,
226                                          unsigned PCAdj /* = 0 */) {
227  MCE.addRelocation(MachineRelocation::getConstPool(MCE.getCurrentPCOffset(),
228                                                    Reloc, CPI, PCAdj));
229}
230
231/// emitJumpTableAddress - Arrange for the address of a jump table to
232/// be emitted to the current location in the function, and allow it to be PC
233/// relative.
234void ARMCodeEmitter::emitJumpTableAddress(unsigned JTIndex, unsigned Reloc,
235                                          unsigned PCAdj /* = 0 */) {
236  MCE.addRelocation(MachineRelocation::getJumpTable(MCE.getCurrentPCOffset(),
237                                                    Reloc, JTIndex, PCAdj));
238}
239
240/// emitMachineBasicBlock - Emit the specified address basic block.
241void ARMCodeEmitter::emitMachineBasicBlock(MachineBasicBlock *BB) {
242  MCE.addRelocation(MachineRelocation::getBB(MCE.getCurrentPCOffset(),
243                                             ARM::reloc_arm_branch, BB));
244}
245
246void ARMCodeEmitter::emitInstruction(const MachineInstr &MI) {
247  DOUT << MI;
248
249  NumEmitted++;  // Keep track of the # of mi's emitted
250  if ((MI.getDesc().TSFlags & ARMII::FormMask) == ARMII::Pseudo)
251    emitPseudoInstruction(MI);
252  else
253    MCE.emitWordLE(getInstrBinary(MI));
254}
255
256unsigned ARMCodeEmitter::getAddrModeNoneInstrBinary(const MachineInstr &MI,
257                                                    const TargetInstrDesc &TID,
258                                                    unsigned Binary) {
259  // Set the conditional execution predicate
260  Binary |= II->getPredicate(&MI) << 28;
261
262  switch (TID.TSFlags & ARMII::FormMask) {
263  default:
264    assert(0 && "Unknown instruction subtype!");
265    break;
266  case ARMII::Branch: {
267    // Set signed_immed_24 field
268    Binary |= getMachineOpValue(MI, 0);
269
270    // if it is a conditional branch, set cond field
271    if (TID.Opcode == ARM::Bcc) {
272      Binary &= 0x0FFFFFFF;                      // clear conditional field
273      Binary |= getMachineOpValue(MI, 1) << 28;  // set conditional field
274    }
275    break;
276  }
277  case ARMII::BranchMisc: {
278    if (TID.Opcode == ARM::BX)
279      abort(); // FIXME
280    if (TID.Opcode == ARM::BX_RET)
281      Binary |= 0xe; // the return register is LR
282    else
283      // otherwise, set the return register
284      Binary |= getMachineOpValue(MI, 0);
285    break;
286  }
287  }
288
289  return Binary;
290}
291
292unsigned ARMCodeEmitter::getMachineSoRegOpValue(const MachineInstr &MI,
293                                                const TargetInstrDesc &TID,
294                                                unsigned OpIdx) {
295  // Set last operand (register Rm)
296  unsigned Binary = getMachineOpValue(MI, OpIdx);
297
298  const MachineOperand &MO1 = MI.getOperand(OpIdx + 1);
299  const MachineOperand &MO2 = MI.getOperand(OpIdx + 2);
300  ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm());
301
302  // Encode the shift opcode.
303  unsigned SBits = 0;
304  unsigned Rs = MO1.getReg();
305  if (Rs) {
306    // Set shift operand (bit[7:4]).
307    // LSL - 0001
308    // LSR - 0011
309    // ASR - 0101
310    // ROR - 0111
311    // RRX - 0110 and bit[11:8] clear.
312    switch (SOpc) {
313    default: assert(0 && "Unknown shift opc!");
314    case ARM_AM::lsl: SBits = 0x1; break;
315    case ARM_AM::lsr: SBits = 0x3; break;
316    case ARM_AM::asr: SBits = 0x5; break;
317    case ARM_AM::ror: SBits = 0x7; break;
318    case ARM_AM::rrx: SBits = 0x6; break;
319    }
320  } else {
321    // Set shift operand (bit[6:4]).
322    // LSL - 000
323    // LSR - 010
324    // ASR - 100
325    // ROR - 110
326    switch (SOpc) {
327    default: assert(0 && "Unknown shift opc!");
328    case ARM_AM::lsl: SBits = 0x0; break;
329    case ARM_AM::lsr: SBits = 0x2; break;
330    case ARM_AM::asr: SBits = 0x4; break;
331    case ARM_AM::ror: SBits = 0x6; break;
332    }
333  }
334  Binary |= SBits << 4;
335  if (SOpc == ARM_AM::rrx)
336    return Binary;
337
338  // Encode the shift operation Rs or shift_imm (except rrx).
339  if (Rs) {
340    // Encode Rs bit[11:8].
341    assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0);
342    return Binary |
343      (ARMRegisterInfo::getRegisterNumbering(Rs) << ARMII::RegRsShift);
344  }
345
346  // Encode shift_imm bit[11:7].
347  return Binary | ARM_AM::getSORegOffset(MO2.getImm()) << 7;
348}
349
350unsigned ARMCodeEmitter::getAddrMode1SBit(const MachineInstr &MI,
351                                          const TargetInstrDesc &TID) const {
352  for (unsigned i = MI.getNumOperands(), e = TID.getNumOperands(); i != e; --i){
353    const MachineOperand &MO = MI.getOperand(i-1);
354    if (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR)
355      return 1 << ARMII::S_BitShift;
356  }
357  return 0;
358}
359
360void ARMCodeEmitter::emitConstPoolInstruction(const MachineInstr &MI) {
361  // FIXME
362}
363
364void ARMCodeEmitter::emitPseudoInstruction(const MachineInstr &MI) {
365  unsigned Opcode = MI.getDesc().Opcode;
366  switch (Opcode) {
367  default:
368    abort(); // FIXME:
369  case ARM::CONSTPOOL_ENTRY: {
370    emitConstPoolInstruction(MI);
371    break;
372  }
373  }
374}
375
376unsigned ARMCodeEmitter::getAddrMode1InstrBinary(const MachineInstr &MI,
377                                                 const TargetInstrDesc &TID,
378                                                 unsigned Binary) {
379  // Set the conditional execution predicate
380  Binary |= II->getPredicate(&MI) << 28;
381
382  // Encode S bit if MI modifies CPSR.
383  Binary |= getAddrMode1SBit(MI, TID);
384
385  // Encode register def if there is one.
386  unsigned NumDefs = TID.getNumDefs();
387  unsigned OpIdx = 0;
388  if (NumDefs) {
389    Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRdShift;
390    ++OpIdx;
391  }
392
393  // Encode first non-shifter register operand if there is one.
394  unsigned Format = TID.TSFlags & ARMII::FormMask;
395  bool hasRnOperand= !(Format == ARMII::DPRdMisc  ||
396                       Format == ARMII::DPRdIm    ||
397                       Format == ARMII::DPRdReg   ||
398                       Format == ARMII::DPRdSoReg);
399  if (hasRnOperand) {
400    Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRnShift;
401    ++OpIdx;
402  }
403
404  // Encode shifter operand.
405  bool HasSoReg = (Format == ARMII::DPRdSoReg ||
406                   Format == ARMII::DPRnSoReg ||
407                   Format == ARMII::DPRSoReg  ||
408                   Format == ARMII::DPRSoRegS);
409  if (HasSoReg)
410    // Encode SoReg.
411    return Binary | getMachineSoRegOpValue(MI, TID, OpIdx);
412
413  const MachineOperand &MO = MI.getOperand(OpIdx);
414  if (MO.isReg())
415    // Encode register Rm.
416    return Binary | getMachineOpValue(MI, NumDefs);
417
418  // Encode so_imm.
419  // Set bit I(25) to identify this is the immediate form of <shifter_op>
420  Binary |= 1 << ARMII::I_BitShift;
421  unsigned SoImm = MO.getImm();
422  // Encode rotate_imm.
423  Binary |= ARM_AM::getSOImmValRot(SoImm) << ARMII::RotImmShift;
424  // Encode immed_8.
425  Binary |= ARM_AM::getSOImmVal(SoImm);
426  return Binary;
427}
428
429unsigned ARMCodeEmitter::getAddrMode2InstrBinary(const MachineInstr &MI,
430                                                 const TargetInstrDesc &TID,
431                                                 unsigned Binary) {
432  // Set the conditional execution predicate
433  Binary |= II->getPredicate(&MI) << 28;
434
435  // Set first operand
436  Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
437
438  // Set second operand
439  Binary |= getMachineOpValue(MI, 1) << ARMII::RegRnShift;
440
441  const MachineOperand &MO2 = MI.getOperand(2);
442  const MachineOperand &MO3 = MI.getOperand(3);
443
444  // Set bit U(23) according to sign of immed value (positive or negative).
445  Binary |= ((ARM_AM::getAM2Op(MO3.getImm()) == ARM_AM::add ? 1 : 0) <<
446             ARMII::U_BitShift);
447  if (!MO2.getReg()) { // is immediate
448    if (ARM_AM::getAM2Offset(MO3.getImm()))
449      // Set the value of offset_12 field
450      Binary |= ARM_AM::getAM2Offset(MO3.getImm());
451    return Binary;
452  }
453
454  // Set bit I(25), because this is not in immediate enconding.
455  Binary |= 1 << ARMII::I_BitShift;
456  assert(TargetRegisterInfo::isPhysicalRegister(MO2.getReg()));
457  // Set bit[3:0] to the corresponding Rm register
458  Binary |= ARMRegisterInfo::getRegisterNumbering(MO2.getReg());
459
460  // if this instr is in scaled register offset/index instruction, set
461  // shift_immed(bit[11:7]) and shift(bit[6:5]) fields.
462  if (unsigned ShImm = ARM_AM::getAM2Offset(MO3.getImm())) {
463    Binary |= getShiftOp(MO3) << 5;  // shift
464    Binary |= ShImm           << 7;  // shift_immed
465  }
466
467  return Binary;
468}
469
470unsigned ARMCodeEmitter::getAddrMode3InstrBinary(const MachineInstr &MI,
471                                                 const TargetInstrDesc &TID,
472                                                 unsigned Binary) {
473  // Set the conditional execution predicate
474  Binary |= II->getPredicate(&MI) << 28;
475
476  // Set first operand
477  Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
478
479  // Set second operand
480  Binary |= getMachineOpValue(MI, 1) << ARMII::RegRnShift;
481
482  const MachineOperand &MO2 = MI.getOperand(2);
483  const MachineOperand &MO3 = MI.getOperand(3);
484
485  // Set bit U(23) according to sign of immed value (positive or negative)
486  Binary |= ((ARM_AM::getAM2Op(MO3.getImm()) == ARM_AM::add ? 1 : 0) <<
487             ARMII::U_BitShift);
488
489  // If this instr is in register offset/index encoding, set bit[3:0]
490  // to the corresponding Rm register.
491  if (MO2.getReg()) {
492    Binary |= ARMRegisterInfo::getRegisterNumbering(MO2.getReg());
493    return Binary;
494  }
495
496  // if this instr is in immediate offset/index encoding, set bit 22 to 1
497  if (unsigned ImmOffs = ARM_AM::getAM3Offset(MO3.getImm())) {
498    Binary |= 1 << 22;
499    // Set operands
500    Binary |= (ImmOffs >> 4) << 8;  // immedH
501    Binary |= (ImmOffs & ~0xF);     // immedL
502  }
503
504  return Binary;
505}
506
507unsigned ARMCodeEmitter::getAddrMode4InstrBinary(const MachineInstr &MI,
508                                                 const TargetInstrDesc &TID,
509                                                 unsigned Binary) {
510  // Set the conditional execution predicate
511  Binary |= II->getPredicate(&MI) << 28;
512
513  // Set first operand
514  Binary |= getMachineOpValue(MI, 0) << ARMII::RegRnShift;
515
516  // Set addressing mode by modifying bits U(23) and P(24)
517  // IA - Increment after  - bit U = 1 and bit P = 0
518  // IB - Increment before - bit U = 1 and bit P = 1
519  // DA - Decrement after  - bit U = 0 and bit P = 0
520  // DB - Decrement before - bit U = 0 and bit P = 1
521  const MachineOperand &MO = MI.getOperand(1);
522  ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MO.getImm());
523  switch (Mode) {
524  default: assert(0 && "Unknown addressing sub-mode!");
525  case ARM_AM::da:                      break;
526  case ARM_AM::db: Binary |= 0x1 << 24; break;
527  case ARM_AM::ia: Binary |= 0x1 << 23; break;
528  case ARM_AM::ib: Binary |= 0x3 << 23; break;
529  }
530
531  // Set bit W(21)
532  if (ARM_AM::getAM4WBFlag(MO.getImm()))
533    Binary |= 0x1 << 21;
534
535  // Set registers
536  for (unsigned i = 4, e = MI.getNumOperands(); i != e; ++i) {
537    const MachineOperand &MO = MI.getOperand(i);
538    if (MO.isReg() && MO.isImplicit())
539      continue;
540    unsigned RegNum = ARMRegisterInfo::getRegisterNumbering(MO.getReg());
541    assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()) &&
542           RegNum < 16);
543    Binary |= 0x1 << RegNum;
544  }
545
546  return Binary;
547}
548
549/// getInstrBinary - Return binary encoding for the specified
550/// machine instruction.
551unsigned ARMCodeEmitter::getInstrBinary(const MachineInstr &MI) {
552  // Part of binary is determined by TableGn.
553  unsigned Binary = getBinaryCodeForInstr(MI);
554
555  const TargetInstrDesc &TID = MI.getDesc();
556  switch (TID.TSFlags & ARMII::AddrModeMask) {
557  case ARMII::AddrModeNone:
558    return getAddrModeNoneInstrBinary(MI, TID, Binary);
559  case ARMII::AddrMode1:
560    return getAddrMode1InstrBinary(MI, TID, Binary);
561  case ARMII::AddrMode2:
562    return getAddrMode2InstrBinary(MI, TID, Binary);
563  case ARMII::AddrMode3:
564    return getAddrMode3InstrBinary(MI, TID, Binary);
565  case ARMII::AddrMode4:
566    return getAddrMode4InstrBinary(MI, TID, Binary);
567  }
568
569  abort();
570  return 0;
571}
572
573#include "ARMGenCodeEmitter.inc"
574