ARMCodeEmitter.cpp revision 33fabd7cc17c60a066c2891244a376684d774fc9 
1//===-- ARM/ARMCodeEmitter.cpp - Convert ARM code to machine code ---------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the pass that transforms the ARM machine instructions into
11// relocatable machine code.
12//
13//===----------------------------------------------------------------------===//
14
15#define DEBUG_TYPE "jit"
16#include "ARM.h"
17#include "ARMAddressingModes.h"
18#include "ARMConstantPoolValue.h"
19#include "ARMInstrInfo.h"
20#include "ARMRelocations.h"
21#include "ARMSubtarget.h"
22#include "ARMTargetMachine.h"
23#include "llvm/Constants.h"
24#include "llvm/DerivedTypes.h"
25#include "llvm/Function.h"
26#include "llvm/PassManager.h"
27#include "llvm/CodeGen/MachineCodeEmitter.h"
28#include "llvm/CodeGen/JITCodeEmitter.h"
29#include "llvm/CodeGen/ObjectCodeEmitter.h"
30#include "llvm/CodeGen/MachineConstantPool.h"
31#include "llvm/CodeGen/MachineFunctionPass.h"
32#include "llvm/CodeGen/MachineInstr.h"
33#include "llvm/CodeGen/MachineJumpTableInfo.h"
34#include "llvm/CodeGen/MachineModuleInfo.h"
35#include "llvm/CodeGen/Passes.h"
36#include "llvm/ADT/Statistic.h"
37#include "llvm/Support/Debug.h"
38#include "llvm/Support/ErrorHandling.h"
39#include "llvm/Support/raw_ostream.h"
40#ifndef NDEBUG
41#include <iomanip>
42#endif
43using namespace llvm;
44
45STATISTIC(NumEmitted, "Number of machine instructions emitted");
46
47namespace {
48
49  class ARMCodeEmitter : public MachineFunctionPass {
50    ARMJITInfo                *JTI;
51    const ARMInstrInfo        *II;
52    const TargetData          *TD;
53    const ARMSubtarget        *Subtarget;
54    TargetMachine             &TM;
55    JITCodeEmitter            &MCE;
56    const std::vector<MachineConstantPoolEntry> *MCPEs;
57    const std::vector<MachineJumpTableEntry> *MJTEs;
58    bool IsPIC;
59
60    void getAnalysisUsage(AnalysisUsage &AU) const {
61      AU.addRequired<MachineModuleInfo>();
62      MachineFunctionPass::getAnalysisUsage(AU);
63    }
64
65    static char ID;
66  public:
67    ARMCodeEmitter(TargetMachine &tm, JITCodeEmitter &mce)
68      : MachineFunctionPass(&ID), JTI(0), II((ARMInstrInfo*)tm.getInstrInfo()),
69        TD(tm.getTargetData()), TM(tm),
70    MCE(mce), MCPEs(0), MJTEs(0),
71    IsPIC(TM.getRelocationModel() == Reloc::PIC_) {}
72
73    /// getBinaryCodeForInstr - This function, generated by the
74    /// CodeEmitterGenerator using TableGen, produces the binary encoding for
75    /// machine instructions.
76    unsigned getBinaryCodeForInstr(const MachineInstr &MI);
77
78    bool runOnMachineFunction(MachineFunction &MF);
79
80    virtual const char *getPassName() const {
81      return "ARM Machine Code Emitter";
82    }
83
84    void emitInstruction(const MachineInstr &MI);
85
86  private:
87
88    void emitWordLE(unsigned Binary);
89    void emitDWordLE(uint64_t Binary);
90    void emitConstPoolInstruction(const MachineInstr &MI);
91    void emitMOVi2piecesInstruction(const MachineInstr &MI);
92    void emitLEApcrelJTInstruction(const MachineInstr &MI);
93    void emitPseudoMoveInstruction(const MachineInstr &MI);
94    void addPCLabel(unsigned LabelID);
95    void emitPseudoInstruction(const MachineInstr &MI);
96    unsigned getMachineSoRegOpValue(const MachineInstr &MI,
97                                    const TargetInstrDesc &TID,
98                                    const MachineOperand &MO,
99                                    unsigned OpIdx);
100
101    unsigned getMachineSoImmOpValue(unsigned SoImm);
102
103    unsigned getAddrModeSBit(const MachineInstr &MI,
104                             const TargetInstrDesc &TID) const;
105
106    void emitDataProcessingInstruction(const MachineInstr &MI,
107                                       unsigned ImplicitRd = 0,
108                                       unsigned ImplicitRn = 0);
109
110    void emitLoadStoreInstruction(const MachineInstr &MI,
111                                  unsigned ImplicitRd = 0,
112                                  unsigned ImplicitRn = 0);
113
114    void emitMiscLoadStoreInstruction(const MachineInstr &MI,
115                                      unsigned ImplicitRn = 0);
116
117    void emitLoadStoreMultipleInstruction(const MachineInstr &MI);
118
119    void emitMulFrmInstruction(const MachineInstr &MI);
120
121    void emitExtendInstruction(const MachineInstr &MI);
122
123    void emitMiscArithInstruction(const MachineInstr &MI);
124
125    void emitBranchInstruction(const MachineInstr &MI);
126
127    void emitInlineJumpTable(unsigned JTIndex);
128
129    void emitMiscBranchInstruction(const MachineInstr &MI);
130
131    void emitVFPArithInstruction(const MachineInstr &MI);
132
133    void emitVFPConversionInstruction(const MachineInstr &MI);
134
135    void emitVFPLoadStoreInstruction(const MachineInstr &MI);
136
137    void emitVFPLoadStoreMultipleInstruction(const MachineInstr &MI);
138
139    void emitMiscInstruction(const MachineInstr &MI);
140
141    /// getMachineOpValue - Return binary encoding of operand. If the machine
142    /// operand requires relocation, record the relocation and return zero.
143    unsigned getMachineOpValue(const MachineInstr &MI,const MachineOperand &MO);
144    unsigned getMachineOpValue(const MachineInstr &MI, unsigned OpIdx) {
145      return getMachineOpValue(MI, MI.getOperand(OpIdx));
146    }
147
148    /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
149    ///
150    unsigned getShiftOp(unsigned Imm) const ;
151
152    /// Routines that handle operands which add machine relocations which are
153    /// fixed up by the relocation stage.
154    void emitGlobalAddress(GlobalValue *GV, unsigned Reloc,
155                           bool MayNeedFarStub,  bool Indirect,
156                           intptr_t ACPV = 0);
157    void emitExternalSymbolAddress(const char *ES, unsigned Reloc);
158    void emitConstPoolAddress(unsigned CPI, unsigned Reloc);
159    void emitJumpTableAddress(unsigned JTIndex, unsigned Reloc);
160    void emitMachineBasicBlock(MachineBasicBlock *BB, unsigned Reloc,
161                               intptr_t JTBase = 0);
162  };
163}
164
165char ARMCodeEmitter::ID = 0;
166
167/// createARMJITCodeEmitterPass - Return a pass that emits the collected ARM
168/// code to the specified MCE object.
169FunctionPass *llvm::createARMJITCodeEmitterPass(ARMBaseTargetMachine &TM,
170                                                JITCodeEmitter &JCE) {
171  return new ARMCodeEmitter(TM, JCE);
172}
173
174bool ARMCodeEmitter::runOnMachineFunction(MachineFunction &MF) {
175  assert((MF.getTarget().getRelocationModel() != Reloc::Default ||
176          MF.getTarget().getRelocationModel() != Reloc::Static) &&
177         "JIT relocation model must be set to static or default!");
178  JTI = ((ARMTargetMachine&)MF.getTarget()).getJITInfo();
179  II = ((ARMTargetMachine&)MF.getTarget()).getInstrInfo();
180  TD = ((ARMTargetMachine&)MF.getTarget()).getTargetData();
181  Subtarget = &TM.getSubtarget<ARMSubtarget>();
182  MCPEs = &MF.getConstantPool()->getConstants();
183  MJTEs = 0;
184  if (MF.getJumpTableInfo()) MJTEs = &MF.getJumpTableInfo()->getJumpTables();
185  IsPIC = TM.getRelocationModel() == Reloc::PIC_;
186  JTI->Initialize(MF, IsPIC);
187  MCE.setModuleInfo(&getAnalysis<MachineModuleInfo>());
188
189  do {
190    DEBUG(errs() << "JITTing function '"
191          << MF.getFunction()->getName() << "'\n");
192    MCE.startFunction(MF);
193    for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();
194         MBB != E; ++MBB) {
195      MCE.StartMachineBasicBlock(MBB);
196      for (MachineBasicBlock::const_iterator I = MBB->begin(), E = MBB->end();
197           I != E; ++I)
198        emitInstruction(*I);
199    }
200  } while (MCE.finishFunction(MF));
201
202  return false;
203}
204
205/// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
206///
207unsigned ARMCodeEmitter::getShiftOp(unsigned Imm) const {
208  switch (ARM_AM::getAM2ShiftOpc(Imm)) {
209  default: llvm_unreachable("Unknown shift opc!");
210  case ARM_AM::asr: return 2;
211  case ARM_AM::lsl: return 0;
212  case ARM_AM::lsr: return 1;
213  case ARM_AM::ror:
214  case ARM_AM::rrx: return 3;
215  }
216  return 0;
217}
218
219/// getMachineOpValue - Return binary encoding of operand. If the machine
220/// operand requires relocation, record the relocation and return zero.
221unsigned ARMCodeEmitter::getMachineOpValue(const MachineInstr &MI,
222                                           const MachineOperand &MO) {
223  if (MO.isReg())
224    return ARMRegisterInfo::getRegisterNumbering(MO.getReg());
225  else if (MO.isImm())
226    return static_cast<unsigned>(MO.getImm());
227  else if (MO.isGlobal())
228    emitGlobalAddress(MO.getGlobal(), ARM::reloc_arm_branch, true, false);
229  else if (MO.isSymbol())
230    emitExternalSymbolAddress(MO.getSymbolName(), ARM::reloc_arm_branch);
231  else if (MO.isCPI()) {
232    const TargetInstrDesc &TID = MI.getDesc();
233    // For VFP load, the immediate offset is multiplied by 4.
234    unsigned Reloc =  ((TID.TSFlags & ARMII::FormMask) == ARMII::VFPLdStFrm)
235      ? ARM::reloc_arm_vfp_cp_entry : ARM::reloc_arm_cp_entry;
236    emitConstPoolAddress(MO.getIndex(), Reloc);
237  } else if (MO.isJTI())
238    emitJumpTableAddress(MO.getIndex(), ARM::reloc_arm_relative);
239  else if (MO.isMBB())
240    emitMachineBasicBlock(MO.getMBB(), ARM::reloc_arm_branch);
241  else {
242#ifndef NDEBUG
243    errs() << MO;
244#endif
245    llvm_unreachable(0);
246  }
247  return 0;
248}
249
250/// emitGlobalAddress - Emit the specified address to the code stream.
251///
252void ARMCodeEmitter::emitGlobalAddress(GlobalValue *GV, unsigned Reloc,
253                                       bool MayNeedFarStub, bool Indirect,
254                                       intptr_t ACPV) {
255  MachineRelocation MR = Indirect
256    ? MachineRelocation::getIndirectSymbol(MCE.getCurrentPCOffset(), Reloc,
257                                           GV, ACPV, MayNeedFarStub)
258    : MachineRelocation::getGV(MCE.getCurrentPCOffset(), Reloc,
259                               GV, ACPV, MayNeedFarStub);
260  MCE.addRelocation(MR);
261}
262
263/// emitExternalSymbolAddress - Arrange for the address of an external symbol to
264/// be emitted to the current location in the function, and allow it to be PC
265/// relative.
266void ARMCodeEmitter::emitExternalSymbolAddress(const char *ES, unsigned Reloc) {
267  MCE.addRelocation(MachineRelocation::getExtSym(MCE.getCurrentPCOffset(),
268                                                 Reloc, ES));
269}
270
271/// emitConstPoolAddress - Arrange for the address of an constant pool
272/// to be emitted to the current location in the function, and allow it to be PC
273/// relative.
274void ARMCodeEmitter::emitConstPoolAddress(unsigned CPI, unsigned Reloc) {
275  // Tell JIT emitter we'll resolve the address.
276  MCE.addRelocation(MachineRelocation::getConstPool(MCE.getCurrentPCOffset(),
277                                                    Reloc, CPI, 0, true));
278}
279
280/// emitJumpTableAddress - Arrange for the address of a jump table to
281/// be emitted to the current location in the function, and allow it to be PC
282/// relative.
283void ARMCodeEmitter::emitJumpTableAddress(unsigned JTIndex, unsigned Reloc) {
284  MCE.addRelocation(MachineRelocation::getJumpTable(MCE.getCurrentPCOffset(),
285                                                    Reloc, JTIndex, 0, true));
286}
287
288/// emitMachineBasicBlock - Emit the specified address basic block.
289void ARMCodeEmitter::emitMachineBasicBlock(MachineBasicBlock *BB,
290                                           unsigned Reloc, intptr_t JTBase) {
291  MCE.addRelocation(MachineRelocation::getBB(MCE.getCurrentPCOffset(),
292                                             Reloc, BB, JTBase));
293}
294
295void ARMCodeEmitter::emitWordLE(unsigned Binary) {
296  DEBUG(errs() << "  0x";
297        errs().write_hex(Binary) << "\n");
298  MCE.emitWordLE(Binary);
299}
300
301void ARMCodeEmitter::emitDWordLE(uint64_t Binary) {
302  DEBUG(errs() << "  0x";
303        errs().write_hex(Binary) << "\n");
304  MCE.emitDWordLE(Binary);
305}
306
307void ARMCodeEmitter::emitInstruction(const MachineInstr &MI) {
308  DEBUG(errs() << "JIT: " << (void*)MCE.getCurrentPCValue() << ":\t" << MI);
309
310  MCE.processDebugLoc(MI.getDebugLoc(), true);
311
312  NumEmitted++;  // Keep track of the # of mi's emitted
313  switch (MI.getDesc().TSFlags & ARMII::FormMask) {
314  default: {
315    llvm_unreachable("Unhandled instruction encoding format!");
316    break;
317  }
318  case ARMII::Pseudo:
319    emitPseudoInstruction(MI);
320    break;
321  case ARMII::DPFrm:
322  case ARMII::DPSoRegFrm:
323    emitDataProcessingInstruction(MI);
324    break;
325  case ARMII::LdFrm:
326  case ARMII::StFrm:
327    emitLoadStoreInstruction(MI);
328    break;
329  case ARMII::LdMiscFrm:
330  case ARMII::StMiscFrm:
331    emitMiscLoadStoreInstruction(MI);
332    break;
333  case ARMII::LdStMulFrm:
334    emitLoadStoreMultipleInstruction(MI);
335    break;
336  case ARMII::MulFrm:
337    emitMulFrmInstruction(MI);
338    break;
339  case ARMII::ExtFrm:
340    emitExtendInstruction(MI);
341    break;
342  case ARMII::ArithMiscFrm:
343    emitMiscArithInstruction(MI);
344    break;
345  case ARMII::BrFrm:
346    emitBranchInstruction(MI);
347    break;
348  case ARMII::BrMiscFrm:
349    emitMiscBranchInstruction(MI);
350    break;
351  // VFP instructions.
352  case ARMII::VFPUnaryFrm:
353  case ARMII::VFPBinaryFrm:
354    emitVFPArithInstruction(MI);
355    break;
356  case ARMII::VFPConv1Frm:
357  case ARMII::VFPConv2Frm:
358  case ARMII::VFPConv3Frm:
359  case ARMII::VFPConv4Frm:
360  case ARMII::VFPConv5Frm:
361    emitVFPConversionInstruction(MI);
362    break;
363  case ARMII::VFPLdStFrm:
364    emitVFPLoadStoreInstruction(MI);
365    break;
366  case ARMII::VFPLdStMulFrm:
367    emitVFPLoadStoreMultipleInstruction(MI);
368    break;
369  case ARMII::VFPMiscFrm:
370    emitMiscInstruction(MI);
371    break;
372  }
373  MCE.processDebugLoc(MI.getDebugLoc(), false);
374}
375
376void ARMCodeEmitter::emitConstPoolInstruction(const MachineInstr &MI) {
377  unsigned CPI = MI.getOperand(0).getImm();       // CP instruction index.
378  unsigned CPIndex = MI.getOperand(1).getIndex(); // Actual cp entry index.
379  const MachineConstantPoolEntry &MCPE = (*MCPEs)[CPIndex];
380
381  // Remember the CONSTPOOL_ENTRY address for later relocation.
382  JTI->addConstantPoolEntryAddr(CPI, MCE.getCurrentPCValue());
383
384  // Emit constpool island entry. In most cases, the actual values will be
385  // resolved and relocated after code emission.
386  if (MCPE.isMachineConstantPoolEntry()) {
387    ARMConstantPoolValue *ACPV =
388      static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal);
389
390    DEBUG(errs() << "  ** ARM constant pool #" << CPI << " @ "
391          << (void*)MCE.getCurrentPCValue() << " " << *ACPV << '\n');
392
393    assert(ACPV->isGlobalValue() && "unsupported constant pool value");
394    GlobalValue *GV = ACPV->getGV();
395    if (GV) {
396      Reloc::Model RelocM = TM.getRelocationModel();
397      emitGlobalAddress(GV, ARM::reloc_arm_machine_cp_entry,
398                        isa<Function>(GV),
399                        Subtarget->GVIsIndirectSymbol(GV, RelocM),
400                        (intptr_t)ACPV);
401     } else  {
402      emitExternalSymbolAddress(ACPV->getSymbol(), ARM::reloc_arm_absolute);
403    }
404    emitWordLE(0);
405  } else {
406    Constant *CV = MCPE.Val.ConstVal;
407
408    DEBUG({
409        errs() << "  ** Constant pool #" << CPI << " @ "
410               << (void*)MCE.getCurrentPCValue() << " ";
411        if (const Function *F = dyn_cast<Function>(CV))
412          errs() << F->getName();
413        else
414          errs() << *CV;
415        errs() << '\n';
416      });
417
418    if (GlobalValue *GV = dyn_cast<GlobalValue>(CV)) {
419      emitGlobalAddress(GV, ARM::reloc_arm_absolute, isa<Function>(GV), false);
420      emitWordLE(0);
421    } else if (const ConstantInt *CI = dyn_cast<ConstantInt>(CV)) {
422      uint32_t Val = *(uint32_t*)CI->getValue().getRawData();
423      emitWordLE(Val);
424    } else if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CV)) {
425      if (CFP->getType()->isFloatTy())
426        emitWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue());
427      else if (CFP->getType()->isDoubleTy())
428        emitDWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue());
429      else {
430        llvm_unreachable("Unable to handle this constantpool entry!");
431      }
432    } else {
433      llvm_unreachable("Unable to handle this constantpool entry!");
434    }
435  }
436}
437
438void ARMCodeEmitter::emitMOVi2piecesInstruction(const MachineInstr &MI) {
439  const MachineOperand &MO0 = MI.getOperand(0);
440  const MachineOperand &MO1 = MI.getOperand(1);
441  assert(MO1.isImm() && ARM_AM::getSOImmVal(MO1.isImm()) != -1 &&
442                                            "Not a valid so_imm value!");
443  unsigned V1 = ARM_AM::getSOImmTwoPartFirst(MO1.getImm());
444  unsigned V2 = ARM_AM::getSOImmTwoPartSecond(MO1.getImm());
445
446  // Emit the 'mov' instruction.
447  unsigned Binary = 0xd << 21;  // mov: Insts{24-21} = 0b1101
448
449  // Set the conditional execution predicate.
450  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
451
452  // Encode Rd.
453  Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
454
455  // Encode so_imm.
456  // Set bit I(25) to identify this is the immediate form of <shifter_op>
457  Binary |= 1 << ARMII::I_BitShift;
458  Binary |= getMachineSoImmOpValue(V1);
459  emitWordLE(Binary);
460
461  // Now the 'orr' instruction.
462  Binary = 0xc << 21;  // orr: Insts{24-21} = 0b1100
463
464  // Set the conditional execution predicate.
465  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
466
467  // Encode Rd.
468  Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
469
470  // Encode Rn.
471  Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRnShift;
472
473  // Encode so_imm.
474  // Set bit I(25) to identify this is the immediate form of <shifter_op>
475  Binary |= 1 << ARMII::I_BitShift;
476  Binary |= getMachineSoImmOpValue(V2);
477  emitWordLE(Binary);
478}
479
480void ARMCodeEmitter::emitLEApcrelJTInstruction(const MachineInstr &MI) {
481  // It's basically add r, pc, (LJTI - $+8)
482
483  const TargetInstrDesc &TID = MI.getDesc();
484
485  // Emit the 'add' instruction.
486  unsigned Binary = 0x4 << 21;  // add: Insts{24-31} = 0b0100
487
488  // Set the conditional execution predicate
489  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
490
491  // Encode S bit if MI modifies CPSR.
492  Binary |= getAddrModeSBit(MI, TID);
493
494  // Encode Rd.
495  Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
496
497  // Encode Rn which is PC.
498  Binary |= ARMRegisterInfo::getRegisterNumbering(ARM::PC) << ARMII::RegRnShift;
499
500  // Encode the displacement.
501  Binary |= 1 << ARMII::I_BitShift;
502  emitJumpTableAddress(MI.getOperand(1).getIndex(), ARM::reloc_arm_jt_base);
503
504  emitWordLE(Binary);
505}
506
507void ARMCodeEmitter::emitPseudoMoveInstruction(const MachineInstr &MI) {
508  unsigned Opcode = MI.getDesc().Opcode;
509
510  // Part of binary is determined by TableGn.
511  unsigned Binary = getBinaryCodeForInstr(MI);
512
513  // Set the conditional execution predicate
514  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
515
516  // Encode S bit if MI modifies CPSR.
517  if (Opcode == ARM::MOVsrl_flag || Opcode == ARM::MOVsra_flag)
518    Binary |= 1 << ARMII::S_BitShift;
519
520  // Encode register def if there is one.
521  Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
522
523  // Encode the shift operation.
524  switch (Opcode) {
525  default: break;
526  case ARM::MOVrx:
527    // rrx
528    Binary |= 0x6 << 4;
529    break;
530  case ARM::MOVsrl_flag:
531    // lsr #1
532    Binary |= (0x2 << 4) | (1 << 7);
533    break;
534  case ARM::MOVsra_flag:
535    // asr #1
536    Binary |= (0x4 << 4) | (1 << 7);
537    break;
538  }
539
540  // Encode register Rm.
541  Binary |= getMachineOpValue(MI, 1);
542
543  emitWordLE(Binary);
544}
545
546void ARMCodeEmitter::addPCLabel(unsigned LabelID) {
547  DEBUG(errs() << "  ** LPC" << LabelID << " @ "
548        << (void*)MCE.getCurrentPCValue() << '\n');
549  JTI->addPCLabelAddr(LabelID, MCE.getCurrentPCValue());
550}
551
552void ARMCodeEmitter::emitPseudoInstruction(const MachineInstr &MI) {
553  unsigned Opcode = MI.getDesc().Opcode;
554  switch (Opcode) {
555  default:
556    llvm_unreachable("ARMCodeEmitter::emitPseudoInstruction");
557  // FIXME: Add support for MOVimm32.
558  case TargetInstrInfo::INLINEASM: {
559    // We allow inline assembler nodes with empty bodies - they can
560    // implicitly define registers, which is ok for JIT.
561    if (MI.getOperand(0).getSymbolName()[0]) {
562      llvm_report_error("JIT does not support inline asm!");
563    }
564    break;
565  }
566  case TargetInstrInfo::DBG_LABEL:
567  case TargetInstrInfo::EH_LABEL:
568    MCE.emitLabel(MI.getOperand(0).getImm());
569    break;
570  case TargetInstrInfo::IMPLICIT_DEF:
571  case TargetInstrInfo::KILL:
572    // Do nothing.
573    break;
574  case ARM::CONSTPOOL_ENTRY:
575    emitConstPoolInstruction(MI);
576    break;
577  case ARM::PICADD: {
578    // Remember of the address of the PC label for relocation later.
579    addPCLabel(MI.getOperand(2).getImm());
580    // PICADD is just an add instruction that implicitly read pc.
581    emitDataProcessingInstruction(MI, 0, ARM::PC);
582    break;
583  }
584  case ARM::PICLDR:
585  case ARM::PICLDRB:
586  case ARM::PICSTR:
587  case ARM::PICSTRB: {
588    // Remember of the address of the PC label for relocation later.
589    addPCLabel(MI.getOperand(2).getImm());
590    // These are just load / store instructions that implicitly read pc.
591    emitLoadStoreInstruction(MI, 0, ARM::PC);
592    break;
593  }
594  case ARM::PICLDRH:
595  case ARM::PICLDRSH:
596  case ARM::PICLDRSB:
597  case ARM::PICSTRH: {
598    // Remember of the address of the PC label for relocation later.
599    addPCLabel(MI.getOperand(2).getImm());
600    // These are just load / store instructions that implicitly read pc.
601    emitMiscLoadStoreInstruction(MI, ARM::PC);
602    break;
603  }
604  case ARM::MOVi2pieces:
605    // Two instructions to materialize a constant.
606    emitMOVi2piecesInstruction(MI);
607    break;
608  case ARM::LEApcrelJT:
609    // Materialize jumptable address.
610    emitLEApcrelJTInstruction(MI);
611    break;
612  case ARM::MOVrx:
613  case ARM::MOVsrl_flag:
614  case ARM::MOVsra_flag:
615    emitPseudoMoveInstruction(MI);
616    break;
617  }
618}
619
620unsigned ARMCodeEmitter::getMachineSoRegOpValue(
621                                                const MachineInstr &MI,
622                                                const TargetInstrDesc &TID,
623                                                const MachineOperand &MO,
624                                                unsigned OpIdx) {
625  unsigned Binary = getMachineOpValue(MI, MO);
626
627  const MachineOperand &MO1 = MI.getOperand(OpIdx + 1);
628  const MachineOperand &MO2 = MI.getOperand(OpIdx + 2);
629  ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm());
630
631  // Encode the shift opcode.
632  unsigned SBits = 0;
633  unsigned Rs = MO1.getReg();
634  if (Rs) {
635    // Set shift operand (bit[7:4]).
636    // LSL - 0001
637    // LSR - 0011
638    // ASR - 0101
639    // ROR - 0111
640    // RRX - 0110 and bit[11:8] clear.
641    switch (SOpc) {
642    default: llvm_unreachable("Unknown shift opc!");
643    case ARM_AM::lsl: SBits = 0x1; break;
644    case ARM_AM::lsr: SBits = 0x3; break;
645    case ARM_AM::asr: SBits = 0x5; break;
646    case ARM_AM::ror: SBits = 0x7; break;
647    case ARM_AM::rrx: SBits = 0x6; break;
648    }
649  } else {
650    // Set shift operand (bit[6:4]).
651    // LSL - 000
652    // LSR - 010
653    // ASR - 100
654    // ROR - 110
655    switch (SOpc) {
656    default: llvm_unreachable("Unknown shift opc!");
657    case ARM_AM::lsl: SBits = 0x0; break;
658    case ARM_AM::lsr: SBits = 0x2; break;
659    case ARM_AM::asr: SBits = 0x4; break;
660    case ARM_AM::ror: SBits = 0x6; break;
661    }
662  }
663  Binary |= SBits << 4;
664  if (SOpc == ARM_AM::rrx)
665    return Binary;
666
667  // Encode the shift operation Rs or shift_imm (except rrx).
668  if (Rs) {
669    // Encode Rs bit[11:8].
670    assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0);
671    return Binary |
672      (ARMRegisterInfo::getRegisterNumbering(Rs) << ARMII::RegRsShift);
673  }
674
675  // Encode shift_imm bit[11:7].
676  return Binary | ARM_AM::getSORegOffset(MO2.getImm()) << 7;
677}
678
679unsigned ARMCodeEmitter::getMachineSoImmOpValue(unsigned SoImm) {
680  int SoImmVal = ARM_AM::getSOImmVal(SoImm);
681  assert(SoImmVal != -1 && "Not a valid so_imm value!");
682
683  // Encode rotate_imm.
684  unsigned Binary = (ARM_AM::getSOImmValRot((unsigned)SoImmVal) >> 1)
685    << ARMII::SoRotImmShift;
686
687  // Encode immed_8.
688  Binary |= ARM_AM::getSOImmValImm((unsigned)SoImmVal);
689  return Binary;
690}
691
692unsigned ARMCodeEmitter::getAddrModeSBit(const MachineInstr &MI,
693                                             const TargetInstrDesc &TID) const {
694  for (unsigned i = MI.getNumOperands(), e = TID.getNumOperands(); i != e; --i){
695    const MachineOperand &MO = MI.getOperand(i-1);
696    if (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR)
697      return 1 << ARMII::S_BitShift;
698  }
699  return 0;
700}
701
702void ARMCodeEmitter::emitDataProcessingInstruction(
703                                                   const MachineInstr &MI,
704                                                   unsigned ImplicitRd,
705                                                   unsigned ImplicitRn) {
706  const TargetInstrDesc &TID = MI.getDesc();
707
708  if (TID.Opcode == ARM::BFC) {
709    llvm_report_error("ARMv6t2 JIT is not yet supported.");
710  }
711
712  // Part of binary is determined by TableGn.
713  unsigned Binary = getBinaryCodeForInstr(MI);
714
715  // Set the conditional execution predicate
716  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
717
718  // Encode S bit if MI modifies CPSR.
719  Binary |= getAddrModeSBit(MI, TID);
720
721  // Encode register def if there is one.
722  unsigned NumDefs = TID.getNumDefs();
723  unsigned OpIdx = 0;
724  if (NumDefs)
725    Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
726  else if (ImplicitRd)
727    // Special handling for implicit use (e.g. PC).
728    Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRd)
729               << ARMII::RegRdShift);
730
731  // If this is a two-address operand, skip it. e.g. MOVCCr operand 1.
732  if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
733    ++OpIdx;
734
735  // Encode first non-shifter register operand if there is one.
736  bool isUnary = TID.TSFlags & ARMII::UnaryDP;
737  if (!isUnary) {
738    if (ImplicitRn)
739      // Special handling for implicit use (e.g. PC).
740      Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRn)
741                 << ARMII::RegRnShift);
742    else {
743      Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRnShift;
744      ++OpIdx;
745    }
746  }
747
748  // Encode shifter operand.
749  const MachineOperand &MO = MI.getOperand(OpIdx);
750  if ((TID.TSFlags & ARMII::FormMask) == ARMII::DPSoRegFrm) {
751    // Encode SoReg.
752    emitWordLE(Binary | getMachineSoRegOpValue(MI, TID, MO, OpIdx));
753    return;
754  }
755
756  if (MO.isReg()) {
757    // Encode register Rm.
758    emitWordLE(Binary | ARMRegisterInfo::getRegisterNumbering(MO.getReg()));
759    return;
760  }
761
762  // Encode so_imm.
763  Binary |= getMachineSoImmOpValue((unsigned)MO.getImm());
764
765  emitWordLE(Binary);
766}
767
768void ARMCodeEmitter::emitLoadStoreInstruction(
769                                              const MachineInstr &MI,
770                                              unsigned ImplicitRd,
771                                              unsigned ImplicitRn) {
772  const TargetInstrDesc &TID = MI.getDesc();
773  unsigned Form = TID.TSFlags & ARMII::FormMask;
774  bool IsPrePost = (TID.TSFlags & ARMII::IndexModeMask) != 0;
775
776  // Part of binary is determined by TableGn.
777  unsigned Binary = getBinaryCodeForInstr(MI);
778
779  // Set the conditional execution predicate
780  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
781
782  unsigned OpIdx = 0;
783
784  // Operand 0 of a pre- and post-indexed store is the address base
785  // writeback. Skip it.
786  bool Skipped = false;
787  if (IsPrePost && Form == ARMII::StFrm) {
788    ++OpIdx;
789    Skipped = true;
790  }
791
792  // Set first operand
793  if (ImplicitRd)
794    // Special handling for implicit use (e.g. PC).
795    Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRd)
796               << ARMII::RegRdShift);
797  else
798    Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
799
800  // Set second operand
801  if (ImplicitRn)
802    // Special handling for implicit use (e.g. PC).
803    Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRn)
804               << ARMII::RegRnShift);
805  else
806    Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
807
808  // If this is a two-address operand, skip it. e.g. LDR_PRE.
809  if (!Skipped && TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
810    ++OpIdx;
811
812  const MachineOperand &MO2 = MI.getOperand(OpIdx);
813  unsigned AM2Opc = (ImplicitRn == ARM::PC)
814    ? 0 : MI.getOperand(OpIdx+1).getImm();
815
816  // Set bit U(23) according to sign of immed value (positive or negative).
817  Binary |= ((ARM_AM::getAM2Op(AM2Opc) == ARM_AM::add ? 1 : 0) <<
818             ARMII::U_BitShift);
819  if (!MO2.getReg()) { // is immediate
820    if (ARM_AM::getAM2Offset(AM2Opc))
821      // Set the value of offset_12 field
822      Binary |= ARM_AM::getAM2Offset(AM2Opc);
823    emitWordLE(Binary);
824    return;
825  }
826
827  // Set bit I(25), because this is not in immediate enconding.
828  Binary |= 1 << ARMII::I_BitShift;
829  assert(TargetRegisterInfo::isPhysicalRegister(MO2.getReg()));
830  // Set bit[3:0] to the corresponding Rm register
831  Binary |= ARMRegisterInfo::getRegisterNumbering(MO2.getReg());
832
833  // If this instr is in scaled register offset/index instruction, set
834  // shift_immed(bit[11:7]) and shift(bit[6:5]) fields.
835  if (unsigned ShImm = ARM_AM::getAM2Offset(AM2Opc)) {
836    Binary |= getShiftOp(AM2Opc) << ARMII::ShiftImmShift;  // shift
837    Binary |= ShImm              << ARMII::ShiftShift;     // shift_immed
838  }
839
840  emitWordLE(Binary);
841}
842
843void ARMCodeEmitter::emitMiscLoadStoreInstruction(const MachineInstr &MI,
844                                                        unsigned ImplicitRn) {
845  const TargetInstrDesc &TID = MI.getDesc();
846  unsigned Form = TID.TSFlags & ARMII::FormMask;
847  bool IsPrePost = (TID.TSFlags & ARMII::IndexModeMask) != 0;
848
849  // Part of binary is determined by TableGn.
850  unsigned Binary = getBinaryCodeForInstr(MI);
851
852  // Set the conditional execution predicate
853  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
854
855  unsigned OpIdx = 0;
856
857  // Operand 0 of a pre- and post-indexed store is the address base
858  // writeback. Skip it.
859  bool Skipped = false;
860  if (IsPrePost && Form == ARMII::StMiscFrm) {
861    ++OpIdx;
862    Skipped = true;
863  }
864
865  // Set first operand
866  Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
867
868  // Skip LDRD and STRD's second operand.
869  if (TID.Opcode == ARM::LDRD || TID.Opcode == ARM::STRD)
870    ++OpIdx;
871
872  // Set second operand
873  if (ImplicitRn)
874    // Special handling for implicit use (e.g. PC).
875    Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRn)
876               << ARMII::RegRnShift);
877  else
878    Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
879
880  // If this is a two-address operand, skip it. e.g. LDRH_POST.
881  if (!Skipped && TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
882    ++OpIdx;
883
884  const MachineOperand &MO2 = MI.getOperand(OpIdx);
885  unsigned AM3Opc = (ImplicitRn == ARM::PC)
886    ? 0 : MI.getOperand(OpIdx+1).getImm();
887
888  // Set bit U(23) according to sign of immed value (positive or negative)
889  Binary |= ((ARM_AM::getAM3Op(AM3Opc) == ARM_AM::add ? 1 : 0) <<
890             ARMII::U_BitShift);
891
892  // If this instr is in register offset/index encoding, set bit[3:0]
893  // to the corresponding Rm register.
894  if (MO2.getReg()) {
895    Binary |= ARMRegisterInfo::getRegisterNumbering(MO2.getReg());
896    emitWordLE(Binary);
897    return;
898  }
899
900  // This instr is in immediate offset/index encoding, set bit 22 to 1.
901  Binary |= 1 << ARMII::AM3_I_BitShift;
902  if (unsigned ImmOffs = ARM_AM::getAM3Offset(AM3Opc)) {
903    // Set operands
904    Binary |= (ImmOffs >> 4) << ARMII::ImmHiShift;  // immedH
905    Binary |= (ImmOffs & 0xF);                      // immedL
906  }
907
908  emitWordLE(Binary);
909}
910
911static unsigned getAddrModeUPBits(unsigned Mode) {
912  unsigned Binary = 0;
913
914  // Set addressing mode by modifying bits U(23) and P(24)
915  // IA - Increment after  - bit U = 1 and bit P = 0
916  // IB - Increment before - bit U = 1 and bit P = 1
917  // DA - Decrement after  - bit U = 0 and bit P = 0
918  // DB - Decrement before - bit U = 0 and bit P = 1
919  switch (Mode) {
920  default: llvm_unreachable("Unknown addressing sub-mode!");
921  case ARM_AM::da:                                     break;
922  case ARM_AM::db: Binary |= 0x1 << ARMII::P_BitShift; break;
923  case ARM_AM::ia: Binary |= 0x1 << ARMII::U_BitShift; break;
924  case ARM_AM::ib: Binary |= 0x3 << ARMII::U_BitShift; break;
925  }
926
927  return Binary;
928}
929
930void ARMCodeEmitter::emitLoadStoreMultipleInstruction(
931                                                       const MachineInstr &MI) {
932  // Part of binary is determined by TableGn.
933  unsigned Binary = getBinaryCodeForInstr(MI);
934
935  // Set the conditional execution predicate
936  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
937
938  // Set base address operand
939  Binary |= getMachineOpValue(MI, 0) << ARMII::RegRnShift;
940
941  // Set addressing mode by modifying bits U(23) and P(24)
942  const MachineOperand &MO = MI.getOperand(1);
943  Binary |= getAddrModeUPBits(ARM_AM::getAM4SubMode(MO.getImm()));
944
945  // Set bit W(21)
946  if (ARM_AM::getAM4WBFlag(MO.getImm()))
947    Binary |= 0x1 << ARMII::W_BitShift;
948
949  // Set registers
950  for (unsigned i = 5, e = MI.getNumOperands(); i != e; ++i) {
951    const MachineOperand &MO = MI.getOperand(i);
952    if (!MO.isReg() || MO.isImplicit())
953      break;
954    unsigned RegNum = ARMRegisterInfo::getRegisterNumbering(MO.getReg());
955    assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()) &&
956           RegNum < 16);
957    Binary |= 0x1 << RegNum;
958  }
959
960  emitWordLE(Binary);
961}
962
963void ARMCodeEmitter::emitMulFrmInstruction(const MachineInstr &MI) {
964  const TargetInstrDesc &TID = MI.getDesc();
965
966  // Part of binary is determined by TableGn.
967  unsigned Binary = getBinaryCodeForInstr(MI);
968
969  // Set the conditional execution predicate
970  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
971
972  // Encode S bit if MI modifies CPSR.
973  Binary |= getAddrModeSBit(MI, TID);
974
975  // 32x32->64bit operations have two destination registers. The number
976  // of register definitions will tell us if that's what we're dealing with.
977  unsigned OpIdx = 0;
978  if (TID.getNumDefs() == 2)
979    Binary |= getMachineOpValue (MI, OpIdx++) << ARMII::RegRdLoShift;
980
981  // Encode Rd
982  Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdHiShift;
983
984  // Encode Rm
985  Binary |= getMachineOpValue(MI, OpIdx++);
986
987  // Encode Rs
988  Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRsShift;
989
990  // Many multiple instructions (e.g. MLA) have three src operands. Encode
991  // it as Rn (for multiply, that's in the same offset as RdLo.
992  if (TID.getNumOperands() > OpIdx &&
993      !TID.OpInfo[OpIdx].isPredicate() &&
994      !TID.OpInfo[OpIdx].isOptionalDef())
995    Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRdLoShift;
996
997  emitWordLE(Binary);
998}
999
1000void ARMCodeEmitter::emitExtendInstruction(const MachineInstr &MI) {
1001  const TargetInstrDesc &TID = MI.getDesc();
1002
1003  // Part of binary is determined by TableGn.
1004  unsigned Binary = getBinaryCodeForInstr(MI);
1005
1006  // Set the conditional execution predicate
1007  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1008
1009  unsigned OpIdx = 0;
1010
1011  // Encode Rd
1012  Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1013
1014  const MachineOperand &MO1 = MI.getOperand(OpIdx++);
1015  const MachineOperand &MO2 = MI.getOperand(OpIdx);
1016  if (MO2.isReg()) {
1017    // Two register operand form.
1018    // Encode Rn.
1019    Binary |= getMachineOpValue(MI, MO1) << ARMII::RegRnShift;
1020
1021    // Encode Rm.
1022    Binary |= getMachineOpValue(MI, MO2);
1023    ++OpIdx;
1024  } else {
1025    Binary |= getMachineOpValue(MI, MO1);
1026  }
1027
1028  // Encode rot imm (0, 8, 16, or 24) if it has a rotate immediate operand.
1029  if (MI.getOperand(OpIdx).isImm() &&
1030      !TID.OpInfo[OpIdx].isPredicate() &&
1031      !TID.OpInfo[OpIdx].isOptionalDef())
1032    Binary |= (getMachineOpValue(MI, OpIdx) / 8) << ARMII::ExtRotImmShift;
1033
1034  emitWordLE(Binary);
1035}
1036
1037void ARMCodeEmitter::emitMiscArithInstruction(const MachineInstr &MI) {
1038  const TargetInstrDesc &TID = MI.getDesc();
1039
1040  // Part of binary is determined by TableGn.
1041  unsigned Binary = getBinaryCodeForInstr(MI);
1042
1043  // Set the conditional execution predicate
1044  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1045
1046  unsigned OpIdx = 0;
1047
1048  // Encode Rd
1049  Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1050
1051  const MachineOperand &MO = MI.getOperand(OpIdx++);
1052  if (OpIdx == TID.getNumOperands() ||
1053      TID.OpInfo[OpIdx].isPredicate() ||
1054      TID.OpInfo[OpIdx].isOptionalDef()) {
1055    // Encode Rm and it's done.
1056    Binary |= getMachineOpValue(MI, MO);
1057    emitWordLE(Binary);
1058    return;
1059  }
1060
1061  // Encode Rn.
1062  Binary |= getMachineOpValue(MI, MO) << ARMII::RegRnShift;
1063
1064  // Encode Rm.
1065  Binary |= getMachineOpValue(MI, OpIdx++);
1066
1067  // Encode shift_imm.
1068  unsigned ShiftAmt = MI.getOperand(OpIdx).getImm();
1069  assert(ShiftAmt < 32 && "shift_imm range is 0 to 31!");
1070  Binary |= ShiftAmt << ARMII::ShiftShift;
1071
1072  emitWordLE(Binary);
1073}
1074
1075void ARMCodeEmitter::emitBranchInstruction(const MachineInstr &MI) {
1076  const TargetInstrDesc &TID = MI.getDesc();
1077
1078  if (TID.Opcode == ARM::TPsoft) {
1079    llvm_unreachable("ARM::TPsoft FIXME"); // FIXME
1080  }
1081
1082  // Part of binary is determined by TableGn.
1083  unsigned Binary = getBinaryCodeForInstr(MI);
1084
1085  // Set the conditional execution predicate
1086  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1087
1088  // Set signed_immed_24 field
1089  Binary |= getMachineOpValue(MI, 0);
1090
1091  emitWordLE(Binary);
1092}
1093
1094void ARMCodeEmitter::emitInlineJumpTable(unsigned JTIndex) {
1095  // Remember the base address of the inline jump table.
1096  uintptr_t JTBase = MCE.getCurrentPCValue();
1097  JTI->addJumpTableBaseAddr(JTIndex, JTBase);
1098  DEBUG(errs() << "  ** Jump Table #" << JTIndex << " @ " << (void*)JTBase
1099               << '\n');
1100
1101  // Now emit the jump table entries.
1102  const std::vector<MachineBasicBlock*> &MBBs = (*MJTEs)[JTIndex].MBBs;
1103  for (unsigned i = 0, e = MBBs.size(); i != e; ++i) {
1104    if (IsPIC)
1105      // DestBB address - JT base.
1106      emitMachineBasicBlock(MBBs[i], ARM::reloc_arm_pic_jt, JTBase);
1107    else
1108      // Absolute DestBB address.
1109      emitMachineBasicBlock(MBBs[i], ARM::reloc_arm_absolute);
1110    emitWordLE(0);
1111  }
1112}
1113
1114void ARMCodeEmitter::emitMiscBranchInstruction(const MachineInstr &MI) {
1115  const TargetInstrDesc &TID = MI.getDesc();
1116
1117  // Handle jump tables.
1118  if (TID.Opcode == ARM::BR_JTr || TID.Opcode == ARM::BR_JTadd) {
1119    // First emit a ldr pc, [] instruction.
1120    emitDataProcessingInstruction(MI, ARM::PC);
1121
1122    // Then emit the inline jump table.
1123    unsigned JTIndex =
1124      (TID.Opcode == ARM::BR_JTr)
1125      ? MI.getOperand(1).getIndex() : MI.getOperand(2).getIndex();
1126    emitInlineJumpTable(JTIndex);
1127    return;
1128  } else if (TID.Opcode == ARM::BR_JTm) {
1129    // First emit a ldr pc, [] instruction.
1130    emitLoadStoreInstruction(MI, ARM::PC);
1131
1132    // Then emit the inline jump table.
1133    emitInlineJumpTable(MI.getOperand(3).getIndex());
1134    return;
1135  }
1136
1137  // Part of binary is determined by TableGn.
1138  unsigned Binary = getBinaryCodeForInstr(MI);
1139
1140  // Set the conditional execution predicate
1141  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1142
1143  if (TID.Opcode == ARM::BX_RET)
1144    // The return register is LR.
1145    Binary |= ARMRegisterInfo::getRegisterNumbering(ARM::LR);
1146  else
1147    // otherwise, set the return register
1148    Binary |= getMachineOpValue(MI, 0);
1149
1150  emitWordLE(Binary);
1151}
1152
1153static unsigned encodeVFPRd(const MachineInstr &MI, unsigned OpIdx) {
1154  unsigned RegD = MI.getOperand(OpIdx).getReg();
1155  unsigned Binary = 0;
1156  bool isSPVFP = false;
1157  RegD = ARMRegisterInfo::getRegisterNumbering(RegD, &isSPVFP);
1158  if (!isSPVFP)
1159    Binary |=   RegD               << ARMII::RegRdShift;
1160  else {
1161    Binary |= ((RegD & 0x1E) >> 1) << ARMII::RegRdShift;
1162    Binary |=  (RegD & 0x01)       << ARMII::D_BitShift;
1163  }
1164  return Binary;
1165}
1166
1167static unsigned encodeVFPRn(const MachineInstr &MI, unsigned OpIdx) {
1168  unsigned RegN = MI.getOperand(OpIdx).getReg();
1169  unsigned Binary = 0;
1170  bool isSPVFP = false;
1171  RegN = ARMRegisterInfo::getRegisterNumbering(RegN, &isSPVFP);
1172  if (!isSPVFP)
1173    Binary |=   RegN               << ARMII::RegRnShift;
1174  else {
1175    Binary |= ((RegN & 0x1E) >> 1) << ARMII::RegRnShift;
1176    Binary |=  (RegN & 0x01)       << ARMII::N_BitShift;
1177  }
1178  return Binary;
1179}
1180
1181static unsigned encodeVFPRm(const MachineInstr &MI, unsigned OpIdx) {
1182  unsigned RegM = MI.getOperand(OpIdx).getReg();
1183  unsigned Binary = 0;
1184  bool isSPVFP = false;
1185  RegM = ARMRegisterInfo::getRegisterNumbering(RegM, &isSPVFP);
1186  if (!isSPVFP)
1187    Binary |=   RegM;
1188  else {
1189    Binary |= ((RegM & 0x1E) >> 1);
1190    Binary |=  (RegM & 0x01)       << ARMII::M_BitShift;
1191  }
1192  return Binary;
1193}
1194
1195void ARMCodeEmitter::emitVFPArithInstruction(const MachineInstr &MI) {
1196  const TargetInstrDesc &TID = MI.getDesc();
1197
1198  // Part of binary is determined by TableGn.
1199  unsigned Binary = getBinaryCodeForInstr(MI);
1200
1201  // Set the conditional execution predicate
1202  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1203
1204  unsigned OpIdx = 0;
1205  assert((Binary & ARMII::D_BitShift) == 0 &&
1206         (Binary & ARMII::N_BitShift) == 0 &&
1207         (Binary & ARMII::M_BitShift) == 0 && "VFP encoding bug!");
1208
1209  // Encode Dd / Sd.
1210  Binary |= encodeVFPRd(MI, OpIdx++);
1211
1212  // If this is a two-address operand, skip it, e.g. FMACD.
1213  if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1214    ++OpIdx;
1215
1216  // Encode Dn / Sn.
1217  if ((TID.TSFlags & ARMII::FormMask) == ARMII::VFPBinaryFrm)
1218    Binary |= encodeVFPRn(MI, OpIdx++);
1219
1220  if (OpIdx == TID.getNumOperands() ||
1221      TID.OpInfo[OpIdx].isPredicate() ||
1222      TID.OpInfo[OpIdx].isOptionalDef()) {
1223    // FCMPEZD etc. has only one operand.
1224    emitWordLE(Binary);
1225    return;
1226  }
1227
1228  // Encode Dm / Sm.
1229  Binary |= encodeVFPRm(MI, OpIdx);
1230
1231  emitWordLE(Binary);
1232}
1233
1234void ARMCodeEmitter::emitVFPConversionInstruction(
1235      const MachineInstr &MI) {
1236  const TargetInstrDesc &TID = MI.getDesc();
1237  unsigned Form = TID.TSFlags & ARMII::FormMask;
1238
1239  // Part of binary is determined by TableGn.
1240  unsigned Binary = getBinaryCodeForInstr(MI);
1241
1242  // Set the conditional execution predicate
1243  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1244
1245  switch (Form) {
1246  default: break;
1247  case ARMII::VFPConv1Frm:
1248  case ARMII::VFPConv2Frm:
1249  case ARMII::VFPConv3Frm:
1250    // Encode Dd / Sd.
1251    Binary |= encodeVFPRd(MI, 0);
1252    break;
1253  case ARMII::VFPConv4Frm:
1254    // Encode Dn / Sn.
1255    Binary |= encodeVFPRn(MI, 0);
1256    break;
1257  case ARMII::VFPConv5Frm:
1258    // Encode Dm / Sm.
1259    Binary |= encodeVFPRm(MI, 0);
1260    break;
1261  }
1262
1263  switch (Form) {
1264  default: break;
1265  case ARMII::VFPConv1Frm:
1266    // Encode Dm / Sm.
1267    Binary |= encodeVFPRm(MI, 1);
1268    break;
1269  case ARMII::VFPConv2Frm:
1270  case ARMII::VFPConv3Frm:
1271    // Encode Dn / Sn.
1272    Binary |= encodeVFPRn(MI, 1);
1273    break;
1274  case ARMII::VFPConv4Frm:
1275  case ARMII::VFPConv5Frm:
1276    // Encode Dd / Sd.
1277    Binary |= encodeVFPRd(MI, 1);
1278    break;
1279  }
1280
1281  if (Form == ARMII::VFPConv5Frm)
1282    // Encode Dn / Sn.
1283    Binary |= encodeVFPRn(MI, 2);
1284  else if (Form == ARMII::VFPConv3Frm)
1285    // Encode Dm / Sm.
1286    Binary |= encodeVFPRm(MI, 2);
1287
1288  emitWordLE(Binary);
1289}
1290
1291void ARMCodeEmitter::emitVFPLoadStoreInstruction(const MachineInstr &MI) {
1292  // Part of binary is determined by TableGn.
1293  unsigned Binary = getBinaryCodeForInstr(MI);
1294
1295  // Set the conditional execution predicate
1296  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1297
1298  unsigned OpIdx = 0;
1299
1300  // Encode Dd / Sd.
1301  Binary |= encodeVFPRd(MI, OpIdx++);
1302
1303  // Encode address base.
1304  const MachineOperand &Base = MI.getOperand(OpIdx++);
1305  Binary |= getMachineOpValue(MI, Base) << ARMII::RegRnShift;
1306
1307  // If there is a non-zero immediate offset, encode it.
1308  if (Base.isReg()) {
1309    const MachineOperand &Offset = MI.getOperand(OpIdx);
1310    if (unsigned ImmOffs = ARM_AM::getAM5Offset(Offset.getImm())) {
1311      if (ARM_AM::getAM5Op(Offset.getImm()) == ARM_AM::add)
1312        Binary |= 1 << ARMII::U_BitShift;
1313      Binary |= ImmOffs;
1314      emitWordLE(Binary);
1315      return;
1316    }
1317  }
1318
1319  // If immediate offset is omitted, default to +0.
1320  Binary |= 1 << ARMII::U_BitShift;
1321
1322  emitWordLE(Binary);
1323}
1324
1325void ARMCodeEmitter::emitVFPLoadStoreMultipleInstruction(
1326                                                       const MachineInstr &MI) {
1327  // Part of binary is determined by TableGn.
1328  unsigned Binary = getBinaryCodeForInstr(MI);
1329
1330  // Set the conditional execution predicate
1331  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1332
1333  // Set base address operand
1334  Binary |= getMachineOpValue(MI, 0) << ARMII::RegRnShift;
1335
1336  // Set addressing mode by modifying bits U(23) and P(24)
1337  const MachineOperand &MO = MI.getOperand(1);
1338  Binary |= getAddrModeUPBits(ARM_AM::getAM5SubMode(MO.getImm()));
1339
1340  // Set bit W(21)
1341  if (ARM_AM::getAM5WBFlag(MO.getImm()))
1342    Binary |= 0x1 << ARMII::W_BitShift;
1343
1344  // First register is encoded in Dd.
1345  Binary |= encodeVFPRd(MI, 5);
1346
1347  // Number of registers are encoded in offset field.
1348  unsigned NumRegs = 1;
1349  for (unsigned i = 6, e = MI.getNumOperands(); i != e; ++i) {
1350    const MachineOperand &MO = MI.getOperand(i);
1351    if (!MO.isReg() || MO.isImplicit())
1352      break;
1353    ++NumRegs;
1354  }
1355  Binary |= NumRegs * 2;
1356
1357  emitWordLE(Binary);
1358}
1359
1360void ARMCodeEmitter::emitMiscInstruction(const MachineInstr &MI) {
1361  // Part of binary is determined by TableGn.
1362  unsigned Binary = getBinaryCodeForInstr(MI);
1363
1364  // Set the conditional execution predicate
1365  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1366
1367  emitWordLE(Binary);
1368}
1369
1370#include "ARMGenCodeEmitter.inc"
1371