ARMCodeEmitter.cpp revision 3d89598f1f77b6592f04671cc5d356eb285b746f 
1//===-- ARM/ARMCodeEmitter.cpp - Convert ARM code to machine code ---------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the pass that transforms the ARM machine instructions into
11// relocatable machine code.
12//
13//===----------------------------------------------------------------------===//
14
15#define DEBUG_TYPE "jit"
16#include "ARM.h"
17#include "ARMAddressingModes.h"
18#include "ARMConstantPoolValue.h"
19#include "ARMInstrInfo.h"
20#include "ARMRelocations.h"
21#include "ARMSubtarget.h"
22#include "ARMTargetMachine.h"
23#include "llvm/Constants.h"
24#include "llvm/DerivedTypes.h"
25#include "llvm/Function.h"
26#include "llvm/PassManager.h"
27#include "llvm/CodeGen/MachineCodeEmitter.h"
28#include "llvm/CodeGen/MachineConstantPool.h"
29#include "llvm/CodeGen/MachineFunctionPass.h"
30#include "llvm/CodeGen/MachineInstr.h"
31#include "llvm/CodeGen/MachineJumpTableInfo.h"
32#include "llvm/CodeGen/Passes.h"
33#include "llvm/ADT/Statistic.h"
34#include "llvm/Support/Compiler.h"
35#include "llvm/Support/Debug.h"
36#ifndef NDEBUG
37#include <iomanip>
38#endif
39using namespace llvm;
40
41STATISTIC(NumEmitted, "Number of machine instructions emitted");
42
43namespace {
44  class VISIBILITY_HIDDEN ARMCodeEmitter : public MachineFunctionPass {
45    ARMJITInfo                *JTI;
46    const ARMInstrInfo        *II;
47    const TargetData          *TD;
48    TargetMachine             &TM;
49    MachineCodeEmitter        &MCE;
50    const std::vector<MachineConstantPoolEntry> *MCPEs;
51    const std::vector<MachineJumpTableEntry> *MJTEs;
52    bool IsPIC;
53
54  public:
55    static char ID;
56    explicit ARMCodeEmitter(TargetMachine &tm, MachineCodeEmitter &mce)
57      : MachineFunctionPass(&ID), JTI(0), II(0), TD(0), TM(tm),
58      MCE(mce), MCPEs(0), MJTEs(0),
59      IsPIC(TM.getRelocationModel() == Reloc::PIC_) {}
60    ARMCodeEmitter(TargetMachine &tm, MachineCodeEmitter &mce,
61            const ARMInstrInfo &ii, const TargetData &td)
62      : MachineFunctionPass(&ID), JTI(0), II(&ii), TD(&td), TM(tm),
63      MCE(mce), MCPEs(0), MJTEs(0),
64      IsPIC(TM.getRelocationModel() == Reloc::PIC_) {}
65
66    bool runOnMachineFunction(MachineFunction &MF);
67
68    virtual const char *getPassName() const {
69      return "ARM Machine Code Emitter";
70    }
71
72    void emitInstruction(const MachineInstr &MI);
73
74  private:
75
76    void emitWordLE(unsigned Binary);
77
78    void emitDWordLE(uint64_t Binary);
79
80    void emitConstPoolInstruction(const MachineInstr &MI);
81
82    void emitMOVi2piecesInstruction(const MachineInstr &MI);
83
84    void emitLEApcrelJTInstruction(const MachineInstr &MI);
85
86    void addPCLabel(unsigned LabelID);
87
88    void emitPseudoInstruction(const MachineInstr &MI);
89
90    unsigned getMachineSoRegOpValue(const MachineInstr &MI,
91                                    const TargetInstrDesc &TID,
92                                    const MachineOperand &MO,
93                                    unsigned OpIdx);
94
95    unsigned getMachineSoImmOpValue(unsigned SoImm);
96
97    unsigned getAddrModeSBit(const MachineInstr &MI,
98                             const TargetInstrDesc &TID) const;
99
100    void emitDataProcessingInstruction(const MachineInstr &MI,
101                                       unsigned ImplicitRd = 0,
102                                       unsigned ImplicitRn = 0);
103
104    void emitLoadStoreInstruction(const MachineInstr &MI,
105                                  unsigned ImplicitRd = 0,
106                                  unsigned ImplicitRn = 0);
107
108    void emitMiscLoadStoreInstruction(const MachineInstr &MI,
109                                      unsigned ImplicitRn = 0);
110
111    void emitLoadStoreMultipleInstruction(const MachineInstr &MI);
112
113    void emitMulFrmInstruction(const MachineInstr &MI);
114
115    void emitExtendInstruction(const MachineInstr &MI);
116
117    void emitMiscArithInstruction(const MachineInstr &MI);
118
119    void emitBranchInstruction(const MachineInstr &MI);
120
121    void emitInlineJumpTable(unsigned JTIndex);
122
123    void emitMiscBranchInstruction(const MachineInstr &MI);
124
125    void emitVFPArithInstruction(const MachineInstr &MI);
126
127    void emitVFPConversionInstruction(const MachineInstr &MI);
128
129    void emitVFPLoadStoreInstruction(const MachineInstr &MI);
130
131    void emitVFPLoadStoreMultipleInstruction(const MachineInstr &MI);
132
133    void emitMiscInstruction(const MachineInstr &MI);
134
135    /// getBinaryCodeForInstr - This function, generated by the
136    /// CodeEmitterGenerator using TableGen, produces the binary encoding for
137    /// machine instructions.
138    ///
139    unsigned getBinaryCodeForInstr(const MachineInstr &MI);
140
141    /// getMachineOpValue - Return binary encoding of operand. If the machine
142    /// operand requires relocation, record the relocation and return zero.
143    unsigned getMachineOpValue(const MachineInstr &MI,const MachineOperand &MO);
144    unsigned getMachineOpValue(const MachineInstr &MI, unsigned OpIdx) {
145      return getMachineOpValue(MI, MI.getOperand(OpIdx));
146    }
147
148    /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
149    ///
150    unsigned getShiftOp(unsigned Imm) const ;
151
152    /// Routines that handle operands which add machine relocations which are
153    /// fixed up by the relocation stage.
154    void emitGlobalAddress(GlobalValue *GV, unsigned Reloc,
155                           bool NeedStub, intptr_t ACPV = 0);
156    void emitExternalSymbolAddress(const char *ES, unsigned Reloc);
157    void emitConstPoolAddress(unsigned CPI, unsigned Reloc);
158    void emitJumpTableAddress(unsigned JTIndex, unsigned Reloc);
159    void emitMachineBasicBlock(MachineBasicBlock *BB, unsigned Reloc,
160                               intptr_t JTBase = 0);
161  };
162  char ARMCodeEmitter::ID = 0;
163}
164
165/// createARMCodeEmitterPass - Return a pass that emits the collected ARM code
166/// to the specified MCE object.
167FunctionPass *llvm::createARMCodeEmitterPass(ARMTargetMachine &TM,
168                                             MachineCodeEmitter &MCE) {
169  return new ARMCodeEmitter(TM, MCE);
170}
171
172bool ARMCodeEmitter::runOnMachineFunction(MachineFunction &MF) {
173  assert((MF.getTarget().getRelocationModel() != Reloc::Default ||
174          MF.getTarget().getRelocationModel() != Reloc::Static) &&
175         "JIT relocation model must be set to static or default!");
176  II = ((ARMTargetMachine&)MF.getTarget()).getInstrInfo();
177  TD = ((ARMTargetMachine&)MF.getTarget()).getTargetData();
178  JTI = ((ARMTargetMachine&)MF.getTarget()).getJITInfo();
179  MCPEs = &MF.getConstantPool()->getConstants();
180  MJTEs = &MF.getJumpTableInfo()->getJumpTables();
181  IsPIC = TM.getRelocationModel() == Reloc::PIC_;
182  JTI->Initialize(MF, IsPIC);
183
184  do {
185    DOUT << "JITTing function '" << MF.getFunction()->getName() << "'\n";
186    MCE.startFunction(MF);
187    for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();
188         MBB != E; ++MBB) {
189      MCE.StartMachineBasicBlock(MBB);
190      for (MachineBasicBlock::const_iterator I = MBB->begin(), E = MBB->end();
191           I != E; ++I)
192        emitInstruction(*I);
193    }
194  } while (MCE.finishFunction(MF));
195
196  return false;
197}
198
199/// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
200///
201unsigned ARMCodeEmitter::getShiftOp(unsigned Imm) const {
202  switch (ARM_AM::getAM2ShiftOpc(Imm)) {
203  default: assert(0 && "Unknown shift opc!");
204  case ARM_AM::asr: return 2;
205  case ARM_AM::lsl: return 0;
206  case ARM_AM::lsr: return 1;
207  case ARM_AM::ror:
208  case ARM_AM::rrx: return 3;
209  }
210  return 0;
211}
212
213/// getMachineOpValue - Return binary encoding of operand. If the machine
214/// operand requires relocation, record the relocation and return zero.
215unsigned ARMCodeEmitter::getMachineOpValue(const MachineInstr &MI,
216                                           const MachineOperand &MO) {
217  if (MO.isReg())
218    return ARMRegisterInfo::getRegisterNumbering(MO.getReg());
219  else if (MO.isImm())
220    return static_cast<unsigned>(MO.getImm());
221  else if (MO.isGlobal())
222    emitGlobalAddress(MO.getGlobal(), ARM::reloc_arm_branch, true);
223  else if (MO.isSymbol())
224    emitExternalSymbolAddress(MO.getSymbolName(), ARM::reloc_arm_branch);
225  else if (MO.isCPI()) {
226    const TargetInstrDesc &TID = MI.getDesc();
227    // For VFP load, the immediate offset is multiplied by 4.
228    unsigned Reloc =  ((TID.TSFlags & ARMII::FormMask) == ARMII::VFPLdStFrm)
229      ? ARM::reloc_arm_vfp_cp_entry : ARM::reloc_arm_cp_entry;
230    emitConstPoolAddress(MO.getIndex(), Reloc);
231  } else if (MO.isJTI())
232    emitJumpTableAddress(MO.getIndex(), ARM::reloc_arm_relative);
233  else if (MO.isMBB())
234    emitMachineBasicBlock(MO.getMBB(), ARM::reloc_arm_branch);
235  else {
236    cerr << "ERROR: Unknown type of MachineOperand: " << MO << "\n";
237    abort();
238  }
239  return 0;
240}
241
242/// emitGlobalAddress - Emit the specified address to the code stream.
243///
244void ARMCodeEmitter::emitGlobalAddress(GlobalValue *GV, unsigned Reloc,
245                                       bool NeedStub, intptr_t ACPV) {
246  MCE.addRelocation(MachineRelocation::getGV(MCE.getCurrentPCOffset(),
247                                             Reloc, GV, ACPV, NeedStub));
248}
249
250/// emitExternalSymbolAddress - Arrange for the address of an external symbol to
251/// be emitted to the current location in the function, and allow it to be PC
252/// relative.
253void ARMCodeEmitter::emitExternalSymbolAddress(const char *ES, unsigned Reloc) {
254  MCE.addRelocation(MachineRelocation::getExtSym(MCE.getCurrentPCOffset(),
255                                                 Reloc, ES));
256}
257
258/// emitConstPoolAddress - Arrange for the address of an constant pool
259/// to be emitted to the current location in the function, and allow it to be PC
260/// relative.
261void ARMCodeEmitter::emitConstPoolAddress(unsigned CPI, unsigned Reloc) {
262  // Tell JIT emitter we'll resolve the address.
263  MCE.addRelocation(MachineRelocation::getConstPool(MCE.getCurrentPCOffset(),
264                                                    Reloc, CPI, 0, true));
265}
266
267/// emitJumpTableAddress - Arrange for the address of a jump table to
268/// be emitted to the current location in the function, and allow it to be PC
269/// relative.
270void ARMCodeEmitter::emitJumpTableAddress(unsigned JTIndex, unsigned Reloc) {
271  MCE.addRelocation(MachineRelocation::getJumpTable(MCE.getCurrentPCOffset(),
272                                                    Reloc, JTIndex, 0, true));
273}
274
275/// emitMachineBasicBlock - Emit the specified address basic block.
276void ARMCodeEmitter::emitMachineBasicBlock(MachineBasicBlock *BB,
277                                           unsigned Reloc, intptr_t JTBase) {
278  MCE.addRelocation(MachineRelocation::getBB(MCE.getCurrentPCOffset(),
279                                             Reloc, BB, JTBase));
280}
281
282void ARMCodeEmitter::emitWordLE(unsigned Binary) {
283#ifndef NDEBUG
284  DOUT << "  0x" << std::hex << std::setw(8) << std::setfill('0')
285       << Binary << std::dec << "\n";
286#endif
287  MCE.emitWordLE(Binary);
288}
289
290void ARMCodeEmitter::emitDWordLE(uint64_t Binary) {
291#ifndef NDEBUG
292  DOUT << "  0x" << std::hex << std::setw(8) << std::setfill('0')
293       << (unsigned)Binary << std::dec << "\n";
294  DOUT << "  0x" << std::hex << std::setw(8) << std::setfill('0')
295       << (unsigned)(Binary >> 32) << std::dec << "\n";
296#endif
297  MCE.emitDWordLE(Binary);
298}
299
300void ARMCodeEmitter::emitInstruction(const MachineInstr &MI) {
301  DOUT << "JIT: " << (void*)MCE.getCurrentPCValue() << ":\t" << MI;
302
303  NumEmitted++;  // Keep track of the # of mi's emitted
304  switch (MI.getDesc().TSFlags & ARMII::FormMask) {
305  default:
306    assert(0 && "Unhandled instruction encoding format!");
307    break;
308  case ARMII::Pseudo:
309    emitPseudoInstruction(MI);
310    break;
311  case ARMII::DPFrm:
312  case ARMII::DPSoRegFrm:
313    emitDataProcessingInstruction(MI);
314    break;
315  case ARMII::LdFrm:
316  case ARMII::StFrm:
317    emitLoadStoreInstruction(MI);
318    break;
319  case ARMII::LdMiscFrm:
320  case ARMII::StMiscFrm:
321    emitMiscLoadStoreInstruction(MI);
322    break;
323  case ARMII::LdStMulFrm:
324    emitLoadStoreMultipleInstruction(MI);
325    break;
326  case ARMII::MulFrm:
327    emitMulFrmInstruction(MI);
328    break;
329  case ARMII::ExtFrm:
330    emitExtendInstruction(MI);
331    break;
332  case ARMII::ArithMiscFrm:
333    emitMiscArithInstruction(MI);
334    break;
335  case ARMII::BrFrm:
336    emitBranchInstruction(MI);
337    break;
338  case ARMII::BrMiscFrm:
339    emitMiscBranchInstruction(MI);
340    break;
341  // VFP instructions.
342  case ARMII::VFPUnaryFrm:
343  case ARMII::VFPBinaryFrm:
344    emitVFPArithInstruction(MI);
345    break;
346  case ARMII::VFPConv1Frm:
347  case ARMII::VFPConv2Frm:
348  case ARMII::VFPConv3Frm:
349  case ARMII::VFPConv4Frm:
350  case ARMII::VFPConv5Frm:
351    emitVFPConversionInstruction(MI);
352    break;
353  case ARMII::VFPLdStFrm:
354    emitVFPLoadStoreInstruction(MI);
355    break;
356  case ARMII::VFPLdStMulFrm:
357    emitVFPLoadStoreMultipleInstruction(MI);
358    break;
359  case ARMII::VFPMiscFrm:
360    emitMiscInstruction(MI);
361    break;
362  }
363}
364
365void ARMCodeEmitter::emitConstPoolInstruction(const MachineInstr &MI) {
366  unsigned CPI = MI.getOperand(0).getImm();       // CP instruction index.
367  unsigned CPIndex = MI.getOperand(1).getIndex(); // Actual cp entry index.
368  const MachineConstantPoolEntry &MCPE = (*MCPEs)[CPIndex];
369
370  // Remember the CONSTPOOL_ENTRY address for later relocation.
371  JTI->addConstantPoolEntryAddr(CPI, MCE.getCurrentPCValue());
372
373  // Emit constpool island entry. In most cases, the actual values will be
374  // resolved and relocated after code emission.
375  if (MCPE.isMachineConstantPoolEntry()) {
376    ARMConstantPoolValue *ACPV =
377      static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal);
378
379    DOUT << "  ** ARM constant pool #" << CPI << " @ "
380         << (void*)MCE.getCurrentPCValue() << " " << *ACPV << '\n';
381
382    GlobalValue *GV = ACPV->getGV();
383    if (GV) {
384      assert(!ACPV->isStub() && "Don't know how to deal this yet!");
385      if (ACPV->isNonLazyPointer())
386        MCE.addRelocation(MachineRelocation::getIndirectSymbol(
387                  MCE.getCurrentPCOffset(), ARM::reloc_arm_machine_cp_entry, GV,
388                  (intptr_t)ACPV, false));
389      else
390        emitGlobalAddress(GV, ARM::reloc_arm_machine_cp_entry,
391                          ACPV->isStub(), (intptr_t)ACPV);
392     } else  {
393      assert(!ACPV->isNonLazyPointer() && "Don't know how to deal this yet!");
394      emitExternalSymbolAddress(ACPV->getSymbol(), ARM::reloc_arm_absolute);
395    }
396    emitWordLE(0);
397  } else {
398    Constant *CV = MCPE.Val.ConstVal;
399
400    DOUT << "  ** Constant pool #" << CPI << " @ "
401         << (void*)MCE.getCurrentPCValue() << " " << *CV << '\n';
402
403    if (GlobalValue *GV = dyn_cast<GlobalValue>(CV)) {
404      emitGlobalAddress(GV, ARM::reloc_arm_absolute, false);
405      emitWordLE(0);
406    } else if (const ConstantInt *CI = dyn_cast<ConstantInt>(CV)) {
407      uint32_t Val = *(uint32_t*)CI->getValue().getRawData();
408      emitWordLE(Val);
409    } else if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CV)) {
410      if (CFP->getType() == Type::FloatTy)
411        emitWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue());
412      else if (CFP->getType() == Type::DoubleTy)
413        emitDWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue());
414      else {
415        assert(0 && "Unable to handle this constantpool entry!");
416        abort();
417      }
418    } else {
419      assert(0 && "Unable to handle this constantpool entry!");
420      abort();
421    }
422  }
423}
424
425void ARMCodeEmitter::emitMOVi2piecesInstruction(const MachineInstr &MI) {
426  const MachineOperand &MO0 = MI.getOperand(0);
427  const MachineOperand &MO1 = MI.getOperand(1);
428  assert(MO1.isImm() && "Not a valid so_imm value!");
429  unsigned V1 = ARM_AM::getSOImmTwoPartFirst(MO1.getImm());
430  unsigned V2 = ARM_AM::getSOImmTwoPartSecond(MO1.getImm());
431
432  // Emit the 'mov' instruction.
433  unsigned Binary = 0xd << 21;  // mov: Insts{24-21} = 0b1101
434
435  // Set the conditional execution predicate.
436  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
437
438  // Encode Rd.
439  Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
440
441  // Encode so_imm.
442  // Set bit I(25) to identify this is the immediate form of <shifter_op>
443  Binary |= 1 << ARMII::I_BitShift;
444  Binary |= getMachineSoImmOpValue(ARM_AM::getSOImmVal(V1));
445  emitWordLE(Binary);
446
447  // Now the 'orr' instruction.
448  Binary = 0xc << 21;  // orr: Insts{24-21} = 0b1100
449
450  // Set the conditional execution predicate.
451  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
452
453  // Encode Rd.
454  Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
455
456  // Encode Rn.
457  Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRnShift;
458
459  // Encode so_imm.
460  // Set bit I(25) to identify this is the immediate form of <shifter_op>
461  Binary |= 1 << ARMII::I_BitShift;
462  Binary |= getMachineSoImmOpValue(ARM_AM::getSOImmVal(V2));
463  emitWordLE(Binary);
464}
465
466void ARMCodeEmitter::emitLEApcrelJTInstruction(const MachineInstr &MI) {
467  // It's basically add r, pc, (LJTI - $+8)
468
469  const TargetInstrDesc &TID = MI.getDesc();
470
471  // Emit the 'add' instruction.
472  unsigned Binary = 0x4 << 21;  // add: Insts{24-31} = 0b0100
473
474  // Set the conditional execution predicate
475  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
476
477  // Encode S bit if MI modifies CPSR.
478  Binary |= getAddrModeSBit(MI, TID);
479
480  // Encode Rd.
481  Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
482
483  // Encode Rn which is PC.
484  Binary |= ARMRegisterInfo::getRegisterNumbering(ARM::PC) << ARMII::RegRnShift;
485
486  // Encode the displacement.
487  // Set bit I(25) to identify this is the immediate form of <shifter_op>.
488  Binary |= 1 << ARMII::I_BitShift;
489  emitJumpTableAddress(MI.getOperand(1).getIndex(), ARM::reloc_arm_jt_base);
490
491  emitWordLE(Binary);
492}
493
494void ARMCodeEmitter::addPCLabel(unsigned LabelID) {
495  DOUT << "  ** LPC" << LabelID << " @ "
496       << (void*)MCE.getCurrentPCValue() << '\n';
497  JTI->addPCLabelAddr(LabelID, MCE.getCurrentPCValue());
498}
499
500void ARMCodeEmitter::emitPseudoInstruction(const MachineInstr &MI) {
501  unsigned Opcode = MI.getDesc().Opcode;
502  switch (Opcode) {
503  default:
504    abort(); // FIXME:
505  case ARM::CONSTPOOL_ENTRY:
506    emitConstPoolInstruction(MI);
507    break;
508  case ARM::PICADD: {
509    // Remember of the address of the PC label for relocation later.
510    addPCLabel(MI.getOperand(2).getImm());
511    // PICADD is just an add instruction that implicitly read pc.
512    emitDataProcessingInstruction(MI, 0, ARM::PC);
513    break;
514  }
515  case ARM::PICLDR:
516  case ARM::PICLDRB:
517  case ARM::PICSTR:
518  case ARM::PICSTRB: {
519    // Remember of the address of the PC label for relocation later.
520    addPCLabel(MI.getOperand(2).getImm());
521    // These are just load / store instructions that implicitly read pc.
522    emitLoadStoreInstruction(MI, 0, ARM::PC);
523    break;
524  }
525  case ARM::PICLDRH:
526  case ARM::PICLDRSH:
527  case ARM::PICLDRSB:
528  case ARM::PICSTRH: {
529    // Remember of the address of the PC label for relocation later.
530    addPCLabel(MI.getOperand(2).getImm());
531    // These are just load / store instructions that implicitly read pc.
532    emitMiscLoadStoreInstruction(MI, ARM::PC);
533    break;
534  }
535  case ARM::MOVi2pieces:
536    // Two instructions to materialize a constant.
537    emitMOVi2piecesInstruction(MI);
538    break;
539  case ARM::LEApcrelJT:
540    // Materialize jumptable address.
541    emitLEApcrelJTInstruction(MI);
542    break;
543  }
544}
545
546
547unsigned ARMCodeEmitter::getMachineSoRegOpValue(const MachineInstr &MI,
548                                                const TargetInstrDesc &TID,
549                                                const MachineOperand &MO,
550                                                unsigned OpIdx) {
551  unsigned Binary = getMachineOpValue(MI, MO);
552
553  const MachineOperand &MO1 = MI.getOperand(OpIdx + 1);
554  const MachineOperand &MO2 = MI.getOperand(OpIdx + 2);
555  ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm());
556
557  // Encode the shift opcode.
558  unsigned SBits = 0;
559  unsigned Rs = MO1.getReg();
560  if (Rs) {
561    // Set shift operand (bit[7:4]).
562    // LSL - 0001
563    // LSR - 0011
564    // ASR - 0101
565    // ROR - 0111
566    // RRX - 0110 and bit[11:8] clear.
567    switch (SOpc) {
568    default: assert(0 && "Unknown shift opc!");
569    case ARM_AM::lsl: SBits = 0x1; break;
570    case ARM_AM::lsr: SBits = 0x3; break;
571    case ARM_AM::asr: SBits = 0x5; break;
572    case ARM_AM::ror: SBits = 0x7; break;
573    case ARM_AM::rrx: SBits = 0x6; break;
574    }
575  } else {
576    // Set shift operand (bit[6:4]).
577    // LSL - 000
578    // LSR - 010
579    // ASR - 100
580    // ROR - 110
581    switch (SOpc) {
582    default: assert(0 && "Unknown shift opc!");
583    case ARM_AM::lsl: SBits = 0x0; break;
584    case ARM_AM::lsr: SBits = 0x2; break;
585    case ARM_AM::asr: SBits = 0x4; break;
586    case ARM_AM::ror: SBits = 0x6; break;
587    }
588  }
589  Binary |= SBits << 4;
590  if (SOpc == ARM_AM::rrx)
591    return Binary;
592
593  // Encode the shift operation Rs or shift_imm (except rrx).
594  if (Rs) {
595    // Encode Rs bit[11:8].
596    assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0);
597    return Binary |
598      (ARMRegisterInfo::getRegisterNumbering(Rs) << ARMII::RegRsShift);
599  }
600
601  // Encode shift_imm bit[11:7].
602  return Binary | ARM_AM::getSORegOffset(MO2.getImm()) << 7;
603}
604
605unsigned ARMCodeEmitter::getMachineSoImmOpValue(unsigned SoImm) {
606  // Encode rotate_imm.
607  unsigned Binary = (ARM_AM::getSOImmValRot(SoImm) >> 1)
608    << ARMII::SoRotImmShift;
609
610  // Encode immed_8.
611  Binary |= ARM_AM::getSOImmValImm(SoImm);
612  return Binary;
613}
614
615unsigned ARMCodeEmitter::getAddrModeSBit(const MachineInstr &MI,
616                                         const TargetInstrDesc &TID) const {
617  for (unsigned i = MI.getNumOperands(), e = TID.getNumOperands(); i != e; --i){
618    const MachineOperand &MO = MI.getOperand(i-1);
619    if (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR)
620      return 1 << ARMII::S_BitShift;
621  }
622  return 0;
623}
624
625void ARMCodeEmitter::emitDataProcessingInstruction(const MachineInstr &MI,
626                                                   unsigned ImplicitRd,
627                                                   unsigned ImplicitRn) {
628  const TargetInstrDesc &TID = MI.getDesc();
629
630  // Part of binary is determined by TableGn.
631  unsigned Binary = getBinaryCodeForInstr(MI);
632
633  // Set the conditional execution predicate
634  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
635
636  // Encode S bit if MI modifies CPSR.
637  Binary |= getAddrModeSBit(MI, TID);
638
639  // Encode register def if there is one.
640  unsigned NumDefs = TID.getNumDefs();
641  unsigned OpIdx = 0;
642  if (NumDefs)
643    Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
644  else if (ImplicitRd)
645    // Special handling for implicit use (e.g. PC).
646    Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRd)
647               << ARMII::RegRdShift);
648
649  // If this is a two-address operand, skip it. e.g. MOVCCr operand 1.
650  if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
651    ++OpIdx;
652
653  // Encode first non-shifter register operand if there is one.
654  bool isUnary = TID.TSFlags & ARMII::UnaryDP;
655  if (!isUnary) {
656    if (ImplicitRn)
657      // Special handling for implicit use (e.g. PC).
658      Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRn)
659                 << ARMII::RegRnShift);
660    else {
661      Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRnShift;
662      ++OpIdx;
663    }
664  }
665
666  // Encode shifter operand.
667  const MachineOperand &MO = MI.getOperand(OpIdx);
668  if ((TID.TSFlags & ARMII::FormMask) == ARMII::DPSoRegFrm) {
669    // Encode SoReg.
670    emitWordLE(Binary | getMachineSoRegOpValue(MI, TID, MO, OpIdx));
671    return;
672  }
673
674  if (MO.isReg()) {
675    // Encode register Rm.
676    emitWordLE(Binary | ARMRegisterInfo::getRegisterNumbering(MO.getReg()));
677    return;
678  }
679
680  // Encode so_imm.
681  // Set bit I(25) to identify this is the immediate form of <shifter_op>.
682  Binary |= 1 << ARMII::I_BitShift;
683  Binary |= getMachineSoImmOpValue(MO.getImm());
684
685  emitWordLE(Binary);
686}
687
688void ARMCodeEmitter::emitLoadStoreInstruction(const MachineInstr &MI,
689                                              unsigned ImplicitRd,
690                                              unsigned ImplicitRn) {
691  const TargetInstrDesc &TID = MI.getDesc();
692  unsigned Form = TID.TSFlags & ARMII::FormMask;
693  bool IsPrePost = (TID.TSFlags & ARMII::IndexModeMask) != 0;
694
695  // Part of binary is determined by TableGn.
696  unsigned Binary = getBinaryCodeForInstr(MI);
697
698  // Set the conditional execution predicate
699  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
700
701  unsigned OpIdx = 0;
702
703  // Operand 0 of a pre- and post-indexed store is the address base
704  // writeback. Skip it.
705  bool Skipped = false;
706  if (IsPrePost && Form == ARMII::StFrm) {
707    ++OpIdx;
708    Skipped = true;
709  }
710
711  // Set first operand
712  if (ImplicitRd)
713    // Special handling for implicit use (e.g. PC).
714    Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRd)
715               << ARMII::RegRdShift);
716  else
717    Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
718
719  // Set second operand
720  if (ImplicitRn)
721    // Special handling for implicit use (e.g. PC).
722    Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRn)
723               << ARMII::RegRnShift);
724  else
725    Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
726
727  // If this is a two-address operand, skip it. e.g. LDR_PRE.
728  if (!Skipped && TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
729    ++OpIdx;
730
731  const MachineOperand &MO2 = MI.getOperand(OpIdx);
732  unsigned AM2Opc = (ImplicitRn == ARM::PC)
733    ? 0 : MI.getOperand(OpIdx+1).getImm();
734
735  // Set bit U(23) according to sign of immed value (positive or negative).
736  Binary |= ((ARM_AM::getAM2Op(AM2Opc) == ARM_AM::add ? 1 : 0) <<
737             ARMII::U_BitShift);
738  if (!MO2.getReg()) { // is immediate
739    if (ARM_AM::getAM2Offset(AM2Opc))
740      // Set the value of offset_12 field
741      Binary |= ARM_AM::getAM2Offset(AM2Opc);
742    emitWordLE(Binary);
743    return;
744  }
745
746  // Set bit I(25), because this is not in immediate enconding.
747  Binary |= 1 << ARMII::I_BitShift;
748  assert(TargetRegisterInfo::isPhysicalRegister(MO2.getReg()));
749  // Set bit[3:0] to the corresponding Rm register
750  Binary |= ARMRegisterInfo::getRegisterNumbering(MO2.getReg());
751
752  // If this instr is in scaled register offset/index instruction, set
753  // shift_immed(bit[11:7]) and shift(bit[6:5]) fields.
754  if (unsigned ShImm = ARM_AM::getAM2Offset(AM2Opc)) {
755    Binary |= getShiftOp(AM2Opc) << ARMII::ShiftImmShift;  // shift
756    Binary |= ShImm              << ARMII::ShiftShift;     // shift_immed
757  }
758
759  emitWordLE(Binary);
760}
761
762void ARMCodeEmitter::emitMiscLoadStoreInstruction(const MachineInstr &MI,
763                                                  unsigned ImplicitRn) {
764  const TargetInstrDesc &TID = MI.getDesc();
765  unsigned Form = TID.TSFlags & ARMII::FormMask;
766  bool IsPrePost = (TID.TSFlags & ARMII::IndexModeMask) != 0;
767
768  // Part of binary is determined by TableGn.
769  unsigned Binary = getBinaryCodeForInstr(MI);
770
771  // Set the conditional execution predicate
772  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
773
774  unsigned OpIdx = 0;
775
776  // Operand 0 of a pre- and post-indexed store is the address base
777  // writeback. Skip it.
778  bool Skipped = false;
779  if (IsPrePost && Form == ARMII::StMiscFrm) {
780    ++OpIdx;
781    Skipped = true;
782  }
783
784  // Set first operand
785  Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
786
787  // Set second operand
788  if (ImplicitRn)
789    // Special handling for implicit use (e.g. PC).
790    Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRn)
791               << ARMII::RegRnShift);
792  else
793    Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
794
795  // If this is a two-address operand, skip it. e.g. LDRH_POST.
796  if (!Skipped && TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
797    ++OpIdx;
798
799  const MachineOperand &MO2 = MI.getOperand(OpIdx);
800  unsigned AM3Opc = (ImplicitRn == ARM::PC)
801    ? 0 : MI.getOperand(OpIdx+1).getImm();
802
803  // Set bit U(23) according to sign of immed value (positive or negative)
804  Binary |= ((ARM_AM::getAM3Op(AM3Opc) == ARM_AM::add ? 1 : 0) <<
805             ARMII::U_BitShift);
806
807  // If this instr is in register offset/index encoding, set bit[3:0]
808  // to the corresponding Rm register.
809  if (MO2.getReg()) {
810    Binary |= ARMRegisterInfo::getRegisterNumbering(MO2.getReg());
811    emitWordLE(Binary);
812    return;
813  }
814
815  // This instr is in immediate offset/index encoding, set bit 22 to 1.
816  Binary |= 1 << ARMII::AM3_I_BitShift;
817  if (unsigned ImmOffs = ARM_AM::getAM3Offset(AM3Opc)) {
818    // Set operands
819    Binary |= (ImmOffs >> 4) << ARMII::ImmHiShift;  // immedH
820    Binary |= (ImmOffs & 0xF);                      // immedL
821  }
822
823  emitWordLE(Binary);
824}
825
826static unsigned getAddrModeUPBits(unsigned Mode) {
827  unsigned Binary = 0;
828
829  // Set addressing mode by modifying bits U(23) and P(24)
830  // IA - Increment after  - bit U = 1 and bit P = 0
831  // IB - Increment before - bit U = 1 and bit P = 1
832  // DA - Decrement after  - bit U = 0 and bit P = 0
833  // DB - Decrement before - bit U = 0 and bit P = 1
834  switch (Mode) {
835  default: assert(0 && "Unknown addressing sub-mode!");
836  case ARM_AM::da:                      break;
837  case ARM_AM::db: Binary |= 0x1 << ARMII::P_BitShift; break;
838  case ARM_AM::ia: Binary |= 0x1 << ARMII::U_BitShift; break;
839  case ARM_AM::ib: Binary |= 0x3 << ARMII::U_BitShift; break;
840  }
841
842  return Binary;
843}
844
845void ARMCodeEmitter::emitLoadStoreMultipleInstruction(const MachineInstr &MI) {
846  // Part of binary is determined by TableGn.
847  unsigned Binary = getBinaryCodeForInstr(MI);
848
849  // Set the conditional execution predicate
850  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
851
852  // Set base address operand
853  Binary |= getMachineOpValue(MI, 0) << ARMII::RegRnShift;
854
855  // Set addressing mode by modifying bits U(23) and P(24)
856  const MachineOperand &MO = MI.getOperand(1);
857  Binary |= getAddrModeUPBits(ARM_AM::getAM4SubMode(MO.getImm()));
858
859  // Set bit W(21)
860  if (ARM_AM::getAM4WBFlag(MO.getImm()))
861    Binary |= 0x1 << ARMII::W_BitShift;
862
863  // Set registers
864  for (unsigned i = 4, e = MI.getNumOperands(); i != e; ++i) {
865    const MachineOperand &MO = MI.getOperand(i);
866    if (!MO.isReg() || MO.isImplicit())
867      break;
868    unsigned RegNum = ARMRegisterInfo::getRegisterNumbering(MO.getReg());
869    assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()) &&
870           RegNum < 16);
871    Binary |= 0x1 << RegNum;
872  }
873
874  emitWordLE(Binary);
875}
876
877void ARMCodeEmitter::emitMulFrmInstruction(const MachineInstr &MI) {
878  const TargetInstrDesc &TID = MI.getDesc();
879
880  // Part of binary is determined by TableGn.
881  unsigned Binary = getBinaryCodeForInstr(MI);
882
883  // Set the conditional execution predicate
884  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
885
886  // Encode S bit if MI modifies CPSR.
887  Binary |= getAddrModeSBit(MI, TID);
888
889  // 32x32->64bit operations have two destination registers. The number
890  // of register definitions will tell us if that's what we're dealing with.
891  unsigned OpIdx = 0;
892  if (TID.getNumDefs() == 2)
893    Binary |= getMachineOpValue (MI, OpIdx++) << ARMII::RegRdLoShift;
894
895  // Encode Rd
896  Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdHiShift;
897
898  // Encode Rm
899  Binary |= getMachineOpValue(MI, OpIdx++);
900
901  // Encode Rs
902  Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRsShift;
903
904  // Many multiple instructions (e.g. MLA) have three src operands. Encode
905  // it as Rn (for multiply, that's in the same offset as RdLo.
906  if (TID.getNumOperands() > OpIdx &&
907      !TID.OpInfo[OpIdx].isPredicate() &&
908      !TID.OpInfo[OpIdx].isOptionalDef())
909    Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRdLoShift;
910
911  emitWordLE(Binary);
912}
913
914void ARMCodeEmitter::emitExtendInstruction(const MachineInstr &MI) {
915  const TargetInstrDesc &TID = MI.getDesc();
916
917  // Part of binary is determined by TableGn.
918  unsigned Binary = getBinaryCodeForInstr(MI);
919
920  // Set the conditional execution predicate
921  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
922
923  unsigned OpIdx = 0;
924
925  // Encode Rd
926  Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
927
928  const MachineOperand &MO1 = MI.getOperand(OpIdx++);
929  const MachineOperand &MO2 = MI.getOperand(OpIdx);
930  if (MO2.isReg()) {
931    // Two register operand form.
932    // Encode Rn.
933    Binary |= getMachineOpValue(MI, MO1) << ARMII::RegRnShift;
934
935    // Encode Rm.
936    Binary |= getMachineOpValue(MI, MO2);
937    ++OpIdx;
938  } else {
939    Binary |= getMachineOpValue(MI, MO1);
940  }
941
942  // Encode rot imm (0, 8, 16, or 24) if it has a rotate immediate operand.
943  if (MI.getOperand(OpIdx).isImm() &&
944      !TID.OpInfo[OpIdx].isPredicate() &&
945      !TID.OpInfo[OpIdx].isOptionalDef())
946    Binary |= (getMachineOpValue(MI, OpIdx) / 8) << ARMII::ExtRotImmShift;
947
948  emitWordLE(Binary);
949}
950
951void ARMCodeEmitter::emitMiscArithInstruction(const MachineInstr &MI) {
952  const TargetInstrDesc &TID = MI.getDesc();
953
954  // Part of binary is determined by TableGn.
955  unsigned Binary = getBinaryCodeForInstr(MI);
956
957  // Set the conditional execution predicate
958  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
959
960  unsigned OpIdx = 0;
961
962  // Encode Rd
963  Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
964
965  const MachineOperand &MO = MI.getOperand(OpIdx++);
966  if (OpIdx == TID.getNumOperands() ||
967      TID.OpInfo[OpIdx].isPredicate() ||
968      TID.OpInfo[OpIdx].isOptionalDef()) {
969    // Encode Rm and it's done.
970    Binary |= getMachineOpValue(MI, MO);
971    emitWordLE(Binary);
972    return;
973  }
974
975  // Encode Rn.
976  Binary |= getMachineOpValue(MI, MO) << ARMII::RegRnShift;
977
978  // Encode Rm.
979  Binary |= getMachineOpValue(MI, OpIdx++);
980
981  // Encode shift_imm.
982  unsigned ShiftAmt = MI.getOperand(OpIdx).getImm();
983  assert(ShiftAmt < 32 && "shift_imm range is 0 to 31!");
984  Binary |= ShiftAmt << ARMII::ShiftShift;
985
986  emitWordLE(Binary);
987}
988
989void ARMCodeEmitter::emitBranchInstruction(const MachineInstr &MI) {
990  const TargetInstrDesc &TID = MI.getDesc();
991
992  if (TID.Opcode == ARM::TPsoft)
993    abort(); // FIXME
994
995  // Part of binary is determined by TableGn.
996  unsigned Binary = getBinaryCodeForInstr(MI);
997
998  // Set the conditional execution predicate
999  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1000
1001  // Set signed_immed_24 field
1002  Binary |= getMachineOpValue(MI, 0);
1003
1004  emitWordLE(Binary);
1005}
1006
1007void ARMCodeEmitter::emitInlineJumpTable(unsigned JTIndex) {
1008  // Remember the base address of the inline jump table.
1009  intptr_t JTBase = MCE.getCurrentPCValue();
1010  JTI->addJumpTableBaseAddr(JTIndex, JTBase);
1011  DOUT << "  ** Jump Table #" << JTIndex << " @ " << (void*)JTBase << '\n';
1012
1013  // Now emit the jump table entries.
1014  const std::vector<MachineBasicBlock*> &MBBs = (*MJTEs)[JTIndex].MBBs;
1015  for (unsigned i = 0, e = MBBs.size(); i != e; ++i) {
1016    if (IsPIC)
1017      // DestBB address - JT base.
1018      emitMachineBasicBlock(MBBs[i], ARM::reloc_arm_pic_jt, JTBase);
1019    else
1020      // Absolute DestBB address.
1021      emitMachineBasicBlock(MBBs[i], ARM::reloc_arm_absolute);
1022    emitWordLE(0);
1023  }
1024}
1025
1026void ARMCodeEmitter::emitMiscBranchInstruction(const MachineInstr &MI) {
1027  const TargetInstrDesc &TID = MI.getDesc();
1028
1029  // Handle jump tables.
1030  if (TID.Opcode == ARM::BR_JTr || TID.Opcode == ARM::BR_JTadd) {
1031    // First emit a ldr pc, [] instruction.
1032    emitDataProcessingInstruction(MI, ARM::PC);
1033
1034    // Then emit the inline jump table.
1035    unsigned JTIndex = (TID.Opcode == ARM::BR_JTr)
1036      ? MI.getOperand(1).getIndex() : MI.getOperand(2).getIndex();
1037    emitInlineJumpTable(JTIndex);
1038    return;
1039  } else if (TID.Opcode == ARM::BR_JTm) {
1040    // First emit a ldr pc, [] instruction.
1041    emitLoadStoreInstruction(MI, ARM::PC);
1042
1043    // Then emit the inline jump table.
1044    emitInlineJumpTable(MI.getOperand(3).getIndex());
1045    return;
1046  }
1047
1048  // Part of binary is determined by TableGn.
1049  unsigned Binary = getBinaryCodeForInstr(MI);
1050
1051  // Set the conditional execution predicate
1052  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1053
1054  if (TID.Opcode == ARM::BX_RET)
1055    // The return register is LR.
1056    Binary |= ARMRegisterInfo::getRegisterNumbering(ARM::LR);
1057  else
1058    // otherwise, set the return register
1059    Binary |= getMachineOpValue(MI, 0);
1060
1061  emitWordLE(Binary);
1062}
1063
1064static unsigned encodeVFPRd(const MachineInstr &MI, unsigned OpIdx) {
1065  unsigned RegD = MI.getOperand(OpIdx).getReg();
1066  unsigned Binary = 0;
1067  bool isSPVFP = false;
1068  RegD = ARMRegisterInfo::getRegisterNumbering(RegD, isSPVFP);
1069  if (!isSPVFP)
1070    Binary |=   RegD               << ARMII::RegRdShift;
1071  else {
1072    Binary |= ((RegD & 0x1E) >> 1) << ARMII::RegRdShift;
1073    Binary |=  (RegD & 0x01)       << ARMII::D_BitShift;
1074  }
1075  return Binary;
1076}
1077
1078static unsigned encodeVFPRn(const MachineInstr &MI, unsigned OpIdx) {
1079  unsigned RegN = MI.getOperand(OpIdx).getReg();
1080  unsigned Binary = 0;
1081  bool isSPVFP = false;
1082  RegN = ARMRegisterInfo::getRegisterNumbering(RegN, isSPVFP);
1083  if (!isSPVFP)
1084    Binary |=   RegN               << ARMII::RegRnShift;
1085  else {
1086    Binary |= ((RegN & 0x1E) >> 1) << ARMII::RegRnShift;
1087    Binary |=  (RegN & 0x01)       << ARMII::N_BitShift;
1088  }
1089  return Binary;
1090}
1091
1092static unsigned encodeVFPRm(const MachineInstr &MI, unsigned OpIdx) {
1093  unsigned RegM = MI.getOperand(OpIdx).getReg();
1094  unsigned Binary = 0;
1095  bool isSPVFP = false;
1096  RegM = ARMRegisterInfo::getRegisterNumbering(RegM, isSPVFP);
1097  if (!isSPVFP)
1098    Binary |=   RegM;
1099  else {
1100    Binary |= ((RegM & 0x1E) >> 1);
1101    Binary |=  (RegM & 0x01)       << ARMII::M_BitShift;
1102  }
1103  return Binary;
1104}
1105
1106void ARMCodeEmitter::emitVFPArithInstruction(const MachineInstr &MI) {
1107  const TargetInstrDesc &TID = MI.getDesc();
1108
1109  // Part of binary is determined by TableGn.
1110  unsigned Binary = getBinaryCodeForInstr(MI);
1111
1112  // Set the conditional execution predicate
1113  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1114
1115  unsigned OpIdx = 0;
1116  assert((Binary & ARMII::D_BitShift) == 0 &&
1117         (Binary & ARMII::N_BitShift) == 0 &&
1118         (Binary & ARMII::M_BitShift) == 0 && "VFP encoding bug!");
1119
1120  // Encode Dd / Sd.
1121  Binary |= encodeVFPRd(MI, OpIdx++);
1122
1123  // If this is a two-address operand, skip it, e.g. FMACD.
1124  if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1125    ++OpIdx;
1126
1127  // Encode Dn / Sn.
1128  if ((TID.TSFlags & ARMII::FormMask) == ARMII::VFPBinaryFrm)
1129    Binary |= encodeVFPRn(MI, OpIdx++);
1130
1131  if (OpIdx == TID.getNumOperands() ||
1132      TID.OpInfo[OpIdx].isPredicate() ||
1133      TID.OpInfo[OpIdx].isOptionalDef()) {
1134    // FCMPEZD etc. has only one operand.
1135    emitWordLE(Binary);
1136    return;
1137  }
1138
1139  // Encode Dm / Sm.
1140  Binary |= encodeVFPRm(MI, OpIdx);
1141
1142  emitWordLE(Binary);
1143}
1144
1145void ARMCodeEmitter::emitVFPConversionInstruction(const MachineInstr &MI) {
1146  const TargetInstrDesc &TID = MI.getDesc();
1147  unsigned Form = TID.TSFlags & ARMII::FormMask;
1148
1149  // Part of binary is determined by TableGn.
1150  unsigned Binary = getBinaryCodeForInstr(MI);
1151
1152  // Set the conditional execution predicate
1153  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1154
1155  switch (Form) {
1156  default: break;
1157  case ARMII::VFPConv1Frm:
1158  case ARMII::VFPConv2Frm:
1159  case ARMII::VFPConv3Frm:
1160    // Encode Dd / Sd.
1161    Binary |= encodeVFPRd(MI, 0);
1162    break;
1163  case ARMII::VFPConv4Frm:
1164    // Encode Dn / Sn.
1165    Binary |= encodeVFPRn(MI, 0);
1166    break;
1167  case ARMII::VFPConv5Frm:
1168    // Encode Dm / Sm.
1169    Binary |= encodeVFPRm(MI, 0);
1170    break;
1171  }
1172
1173  switch (Form) {
1174  default: break;
1175  case ARMII::VFPConv1Frm:
1176    // Encode Dm / Sm.
1177    Binary |= encodeVFPRm(MI, 1);
1178    break;
1179  case ARMII::VFPConv2Frm:
1180  case ARMII::VFPConv3Frm:
1181    // Encode Dn / Sn.
1182    Binary |= encodeVFPRn(MI, 1);
1183    break;
1184  case ARMII::VFPConv4Frm:
1185  case ARMII::VFPConv5Frm:
1186    // Encode Dd / Sd.
1187    Binary |= encodeVFPRd(MI, 1);
1188    break;
1189  }
1190
1191  if (Form == ARMII::VFPConv5Frm)
1192    // Encode Dn / Sn.
1193    Binary |= encodeVFPRn(MI, 2);
1194  else if (Form == ARMII::VFPConv3Frm)
1195    // Encode Dm / Sm.
1196    Binary |= encodeVFPRm(MI, 2);
1197
1198  emitWordLE(Binary);
1199}
1200
1201void ARMCodeEmitter::emitVFPLoadStoreInstruction(const MachineInstr &MI) {
1202  // Part of binary is determined by TableGn.
1203  unsigned Binary = getBinaryCodeForInstr(MI);
1204
1205  // Set the conditional execution predicate
1206  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1207
1208  unsigned OpIdx = 0;
1209
1210  // Encode Dd / Sd.
1211  Binary |= encodeVFPRd(MI, OpIdx++);
1212
1213  // Encode address base.
1214  const MachineOperand &Base = MI.getOperand(OpIdx++);
1215  Binary |= getMachineOpValue(MI, Base) << ARMII::RegRnShift;
1216
1217  // If there is a non-zero immediate offset, encode it.
1218  if (Base.isReg()) {
1219    const MachineOperand &Offset = MI.getOperand(OpIdx);
1220    if (unsigned ImmOffs = ARM_AM::getAM5Offset(Offset.getImm())) {
1221      if (ARM_AM::getAM5Op(Offset.getImm()) == ARM_AM::add)
1222        Binary |= 1 << ARMII::U_BitShift;
1223      Binary |= ImmOffs;
1224      emitWordLE(Binary);
1225      return;
1226    }
1227  }
1228
1229  // If immediate offset is omitted, default to +0.
1230  Binary |= 1 << ARMII::U_BitShift;
1231
1232  emitWordLE(Binary);
1233}
1234
1235void
1236ARMCodeEmitter::emitVFPLoadStoreMultipleInstruction(const MachineInstr &MI) {
1237  // Part of binary is determined by TableGn.
1238  unsigned Binary = getBinaryCodeForInstr(MI);
1239
1240  // Set the conditional execution predicate
1241  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1242
1243  // Set base address operand
1244  Binary |= getMachineOpValue(MI, 0) << ARMII::RegRnShift;
1245
1246  // Set addressing mode by modifying bits U(23) and P(24)
1247  const MachineOperand &MO = MI.getOperand(1);
1248  Binary |= getAddrModeUPBits(ARM_AM::getAM5SubMode(MO.getImm()));
1249
1250  // Set bit W(21)
1251  if (ARM_AM::getAM5WBFlag(MO.getImm()))
1252    Binary |= 0x1 << ARMII::W_BitShift;
1253
1254  // First register is encoded in Dd.
1255  Binary |= encodeVFPRd(MI, 4);
1256
1257  // Number of registers are encoded in offset field.
1258  unsigned NumRegs = 1;
1259  for (unsigned i = 5, e = MI.getNumOperands(); i != e; ++i) {
1260    const MachineOperand &MO = MI.getOperand(i);
1261    if (!MO.isReg() || MO.isImplicit())
1262      break;
1263    ++NumRegs;
1264  }
1265  Binary |= NumRegs * 2;
1266
1267  emitWordLE(Binary);
1268}
1269
1270void ARMCodeEmitter::emitMiscInstruction(const MachineInstr &MI) {
1271  // Part of binary is determined by TableGn.
1272  unsigned Binary = getBinaryCodeForInstr(MI);
1273
1274  // Set the conditional execution predicate
1275  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1276
1277  emitWordLE(Binary);
1278}
1279
1280#include "ARMGenCodeEmitter.inc"
1281