ARMCodeEmitter.cpp revision 3f4924efffdb4bb7af408356df86bd8cb83ab89a 
1//===-- ARM/ARMCodeEmitter.cpp - Convert ARM code to machine code ---------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the pass that transforms the ARM machine instructions into
11// relocatable machine code.
12//
13//===----------------------------------------------------------------------===//
14
15#define DEBUG_TYPE "jit"
16#include "ARM.h"
17#include "ARMAddressingModes.h"
18#include "ARMConstantPoolValue.h"
19#include "ARMInstrInfo.h"
20#include "ARMRelocations.h"
21#include "ARMSubtarget.h"
22#include "ARMTargetMachine.h"
23#include "llvm/Constants.h"
24#include "llvm/DerivedTypes.h"
25#include "llvm/Function.h"
26#include "llvm/PassManager.h"
27#include "llvm/CodeGen/MachineCodeEmitter.h"
28#include "llvm/CodeGen/MachineConstantPool.h"
29#include "llvm/CodeGen/MachineFunctionPass.h"
30#include "llvm/CodeGen/MachineInstr.h"
31#include "llvm/CodeGen/MachineJumpTableInfo.h"
32#include "llvm/CodeGen/Passes.h"
33#include "llvm/ADT/Statistic.h"
34#include "llvm/Support/Compiler.h"
35#include "llvm/Support/Debug.h"
36#ifndef NDEBUG
37#include <iomanip>
38#endif
39using namespace llvm;
40
41STATISTIC(NumEmitted, "Number of machine instructions emitted");
42
43namespace {
44  class VISIBILITY_HIDDEN ARMCodeEmitter : public MachineFunctionPass {
45    ARMJITInfo                *JTI;
46    const ARMInstrInfo        *II;
47    const TargetData          *TD;
48    TargetMachine             &TM;
49    MachineCodeEmitter        &MCE;
50    const std::vector<MachineConstantPoolEntry> *MCPEs;
51    const std::vector<MachineJumpTableEntry> *MJTEs;
52    bool IsPIC;
53
54  public:
55    static char ID;
56    explicit ARMCodeEmitter(TargetMachine &tm, MachineCodeEmitter &mce)
57      : MachineFunctionPass(&ID), JTI(0), II(0), TD(0), TM(tm),
58      MCE(mce), MCPEs(0), MJTEs(0),
59      IsPIC(TM.getRelocationModel() == Reloc::PIC_) {}
60    ARMCodeEmitter(TargetMachine &tm, MachineCodeEmitter &mce,
61            const ARMInstrInfo &ii, const TargetData &td)
62      : MachineFunctionPass(&ID), JTI(0), II(&ii), TD(&td), TM(tm),
63      MCE(mce), MCPEs(0), MJTEs(0),
64      IsPIC(TM.getRelocationModel() == Reloc::PIC_) {}
65
66    bool runOnMachineFunction(MachineFunction &MF);
67
68    virtual const char *getPassName() const {
69      return "ARM Machine Code Emitter";
70    }
71
72    void emitInstruction(const MachineInstr &MI);
73
74  private:
75
76    void emitWordLE(unsigned Binary);
77
78    void emitDWordLE(uint64_t Binary);
79
80    void emitConstPoolInstruction(const MachineInstr &MI);
81
82    void emitMOVi2piecesInstruction(const MachineInstr &MI);
83
84    void emitLEApcrelJTInstruction(const MachineInstr &MI);
85
86    void addPCLabel(unsigned LabelID);
87
88    void emitPseudoInstruction(const MachineInstr &MI);
89
90    unsigned getMachineSoRegOpValue(const MachineInstr &MI,
91                                    const TargetInstrDesc &TID,
92                                    const MachineOperand &MO,
93                                    unsigned OpIdx);
94
95    unsigned getMachineSoImmOpValue(unsigned SoImm);
96
97    unsigned getAddrModeSBit(const MachineInstr &MI,
98                             const TargetInstrDesc &TID) const;
99
100    void emitDataProcessingInstruction(const MachineInstr &MI,
101                                       unsigned ImplicitRd = 0,
102                                       unsigned ImplicitRn = 0);
103
104    void emitLoadStoreInstruction(const MachineInstr &MI,
105                                  unsigned ImplicitRd = 0,
106                                  unsigned ImplicitRn = 0);
107
108    void emitMiscLoadStoreInstruction(const MachineInstr &MI,
109                                      unsigned ImplicitRn = 0);
110
111    void emitLoadStoreMultipleInstruction(const MachineInstr &MI);
112
113    void emitMulFrmInstruction(const MachineInstr &MI);
114
115    void emitExtendInstruction(const MachineInstr &MI);
116
117    void emitMiscArithInstruction(const MachineInstr &MI);
118
119    void emitBranchInstruction(const MachineInstr &MI);
120
121    void emitInlineJumpTable(unsigned JTIndex);
122
123    void emitMiscBranchInstruction(const MachineInstr &MI);
124
125    void emitVFPArithInstruction(const MachineInstr &MI);
126
127    void emitVFPConversionInstruction(const MachineInstr &MI);
128
129    void emitVFPLoadStoreInstruction(const MachineInstr &MI);
130
131    void emitVFPLoadStoreMultipleInstruction(const MachineInstr &MI);
132
133    void emitMiscInstruction(const MachineInstr &MI);
134
135    /// getBinaryCodeForInstr - This function, generated by the
136    /// CodeEmitterGenerator using TableGen, produces the binary encoding for
137    /// machine instructions.
138    ///
139    unsigned getBinaryCodeForInstr(const MachineInstr &MI);
140
141    /// getMachineOpValue - Return binary encoding of operand. If the machine
142    /// operand requires relocation, record the relocation and return zero.
143    unsigned getMachineOpValue(const MachineInstr &MI,const MachineOperand &MO);
144    unsigned getMachineOpValue(const MachineInstr &MI, unsigned OpIdx) {
145      return getMachineOpValue(MI, MI.getOperand(OpIdx));
146    }
147
148    /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
149    ///
150    unsigned getShiftOp(unsigned Imm) const ;
151
152    /// Routines that handle operands which add machine relocations which are
153    /// fixed up by the relocation stage.
154    void emitGlobalAddress(GlobalValue *GV, unsigned Reloc,
155                           bool NeedStub, intptr_t ACPV = 0);
156    void emitExternalSymbolAddress(const char *ES, unsigned Reloc);
157    void emitConstPoolAddress(unsigned CPI, unsigned Reloc);
158    void emitJumpTableAddress(unsigned JTIndex, unsigned Reloc);
159    void emitMachineBasicBlock(MachineBasicBlock *BB, unsigned Reloc,
160                               intptr_t JTBase = 0);
161  };
162  char ARMCodeEmitter::ID = 0;
163}
164
165/// createARMCodeEmitterPass - Return a pass that emits the collected ARM code
166/// to the specified MCE object.
167FunctionPass *llvm::createARMCodeEmitterPass(ARMTargetMachine &TM,
168                                             MachineCodeEmitter &MCE) {
169  return new ARMCodeEmitter(TM, MCE);
170}
171
172bool ARMCodeEmitter::runOnMachineFunction(MachineFunction &MF) {
173  assert((MF.getTarget().getRelocationModel() != Reloc::Default ||
174          MF.getTarget().getRelocationModel() != Reloc::Static) &&
175         "JIT relocation model must be set to static or default!");
176  II = ((ARMTargetMachine&)MF.getTarget()).getInstrInfo();
177  TD = ((ARMTargetMachine&)MF.getTarget()).getTargetData();
178  JTI = ((ARMTargetMachine&)MF.getTarget()).getJITInfo();
179  MCPEs = &MF.getConstantPool()->getConstants();
180  MJTEs = &MF.getJumpTableInfo()->getJumpTables();
181  IsPIC = TM.getRelocationModel() == Reloc::PIC_;
182  JTI->Initialize(MF, IsPIC);
183
184  do {
185    DOUT << "JITTing function '" << MF.getFunction()->getName() << "'\n";
186    MCE.startFunction(MF);
187    for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();
188         MBB != E; ++MBB) {
189      MCE.StartMachineBasicBlock(MBB);
190      for (MachineBasicBlock::const_iterator I = MBB->begin(), E = MBB->end();
191           I != E; ++I)
192        emitInstruction(*I);
193    }
194  } while (MCE.finishFunction(MF));
195
196  return false;
197}
198
199/// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
200///
201unsigned ARMCodeEmitter::getShiftOp(unsigned Imm) const {
202  switch (ARM_AM::getAM2ShiftOpc(Imm)) {
203  default: assert(0 && "Unknown shift opc!");
204  case ARM_AM::asr: return 2;
205  case ARM_AM::lsl: return 0;
206  case ARM_AM::lsr: return 1;
207  case ARM_AM::ror:
208  case ARM_AM::rrx: return 3;
209  }
210  return 0;
211}
212
213/// getMachineOpValue - Return binary encoding of operand. If the machine
214/// operand requires relocation, record the relocation and return zero.
215unsigned ARMCodeEmitter::getMachineOpValue(const MachineInstr &MI,
216                                           const MachineOperand &MO) {
217  if (MO.isReg())
218    return ARMRegisterInfo::getRegisterNumbering(MO.getReg());
219  else if (MO.isImm())
220    return static_cast<unsigned>(MO.getImm());
221  else if (MO.isGlobal())
222    emitGlobalAddress(MO.getGlobal(), ARM::reloc_arm_branch, true);
223  else if (MO.isSymbol())
224    emitExternalSymbolAddress(MO.getSymbolName(), ARM::reloc_arm_branch);
225  else if (MO.isCPI()) {
226    const TargetInstrDesc &TID = MI.getDesc();
227    // For VFP load, the immediate offset is multiplied by 4.
228    unsigned Reloc =  ((TID.TSFlags & ARMII::FormMask) == ARMII::VFPLdStFrm)
229      ? ARM::reloc_arm_vfp_cp_entry : ARM::reloc_arm_cp_entry;
230    emitConstPoolAddress(MO.getIndex(), Reloc);
231  } else if (MO.isJTI())
232    emitJumpTableAddress(MO.getIndex(), ARM::reloc_arm_relative);
233  else if (MO.isMBB())
234    emitMachineBasicBlock(MO.getMBB(), ARM::reloc_arm_branch);
235  else {
236    cerr << "ERROR: Unknown type of MachineOperand: " << MO << "\n";
237    abort();
238  }
239  return 0;
240}
241
242/// emitGlobalAddress - Emit the specified address to the code stream.
243///
244void ARMCodeEmitter::emitGlobalAddress(GlobalValue *GV, unsigned Reloc,
245                                       bool NeedStub, intptr_t ACPV) {
246  MCE.addRelocation(MachineRelocation::getGV(MCE.getCurrentPCOffset(),
247                                             Reloc, GV, ACPV, NeedStub));
248}
249
250/// emitExternalSymbolAddress - Arrange for the address of an external symbol to
251/// be emitted to the current location in the function, and allow it to be PC
252/// relative.
253void ARMCodeEmitter::emitExternalSymbolAddress(const char *ES, unsigned Reloc) {
254  MCE.addRelocation(MachineRelocation::getExtSym(MCE.getCurrentPCOffset(),
255                                                 Reloc, ES));
256}
257
258/// emitConstPoolAddress - Arrange for the address of an constant pool
259/// to be emitted to the current location in the function, and allow it to be PC
260/// relative.
261void ARMCodeEmitter::emitConstPoolAddress(unsigned CPI, unsigned Reloc) {
262  // Tell JIT emitter we'll resolve the address.
263  MCE.addRelocation(MachineRelocation::getConstPool(MCE.getCurrentPCOffset(),
264                                                    Reloc, CPI, 0, true));
265}
266
267/// emitJumpTableAddress - Arrange for the address of a jump table to
268/// be emitted to the current location in the function, and allow it to be PC
269/// relative.
270void ARMCodeEmitter::emitJumpTableAddress(unsigned JTIndex, unsigned Reloc) {
271  MCE.addRelocation(MachineRelocation::getJumpTable(MCE.getCurrentPCOffset(),
272                                                    Reloc, JTIndex, 0, true));
273}
274
275/// emitMachineBasicBlock - Emit the specified address basic block.
276void ARMCodeEmitter::emitMachineBasicBlock(MachineBasicBlock *BB,
277                                           unsigned Reloc, intptr_t JTBase) {
278  MCE.addRelocation(MachineRelocation::getBB(MCE.getCurrentPCOffset(),
279                                             Reloc, BB, JTBase));
280}
281
282void ARMCodeEmitter::emitWordLE(unsigned Binary) {
283#ifndef NDEBUG
284  DOUT << "  0x" << std::hex << std::setw(8) << std::setfill('0')
285       << Binary << std::dec << "\n";
286#endif
287  MCE.emitWordLE(Binary);
288}
289
290void ARMCodeEmitter::emitDWordLE(uint64_t Binary) {
291#ifndef NDEBUG
292  DOUT << "  0x" << std::hex << std::setw(8) << std::setfill('0')
293       << (unsigned)Binary << std::dec << "\n";
294  DOUT << "  0x" << std::hex << std::setw(8) << std::setfill('0')
295       << (unsigned)(Binary >> 32) << std::dec << "\n";
296#endif
297  MCE.emitDWordLE(Binary);
298}
299
300void ARMCodeEmitter::emitInstruction(const MachineInstr &MI) {
301  DOUT << "JIT: " << (void*)MCE.getCurrentPCValue() << ":\t" << MI;
302
303  NumEmitted++;  // Keep track of the # of mi's emitted
304  switch (MI.getDesc().TSFlags & ARMII::FormMask) {
305  default:
306    assert(0 && "Unhandled instruction encoding format!");
307    break;
308  case ARMII::Pseudo:
309    emitPseudoInstruction(MI);
310    break;
311  case ARMII::DPFrm:
312  case ARMII::DPSoRegFrm:
313    emitDataProcessingInstruction(MI);
314    break;
315  case ARMII::LdStFrm:
316    emitLoadStoreInstruction(MI);
317    break;
318  case ARMII::LdStMiscFrm:
319    emitMiscLoadStoreInstruction(MI);
320    break;
321  case ARMII::LdStMulFrm:
322    emitLoadStoreMultipleInstruction(MI);
323    break;
324  case ARMII::MulFrm:
325    emitMulFrmInstruction(MI);
326    break;
327  case ARMII::ExtFrm:
328    emitExtendInstruction(MI);
329    break;
330  case ARMII::ArithMiscFrm:
331    emitMiscArithInstruction(MI);
332    break;
333  case ARMII::BrFrm:
334    emitBranchInstruction(MI);
335    break;
336  case ARMII::BrMiscFrm:
337    emitMiscBranchInstruction(MI);
338    break;
339  // VFP instructions.
340  case ARMII::VFPUnaryFrm:
341  case ARMII::VFPBinaryFrm:
342    emitVFPArithInstruction(MI);
343    break;
344  case ARMII::VFPConv1Frm:
345  case ARMII::VFPConv2Frm:
346  case ARMII::VFPConv3Frm:
347  case ARMII::VFPConv4Frm:
348  case ARMII::VFPConv5Frm:
349    emitVFPConversionInstruction(MI);
350    break;
351  case ARMII::VFPLdStFrm:
352    emitVFPLoadStoreInstruction(MI);
353    break;
354  case ARMII::VFPLdStMulFrm:
355    emitVFPLoadStoreMultipleInstruction(MI);
356    break;
357  case ARMII::VFPMiscFrm:
358    emitMiscInstruction(MI);
359    break;
360  }
361}
362
363void ARMCodeEmitter::emitConstPoolInstruction(const MachineInstr &MI) {
364  unsigned CPI = MI.getOperand(0).getImm();       // CP instruction index.
365  unsigned CPIndex = MI.getOperand(1).getIndex(); // Actual cp entry index.
366  const MachineConstantPoolEntry &MCPE = (*MCPEs)[CPIndex];
367
368  // Remember the CONSTPOOL_ENTRY address for later relocation.
369  JTI->addConstantPoolEntryAddr(CPI, MCE.getCurrentPCValue());
370
371  // Emit constpool island entry. In most cases, the actual values will be
372  // resolved and relocated after code emission.
373  if (MCPE.isMachineConstantPoolEntry()) {
374    ARMConstantPoolValue *ACPV =
375      static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal);
376
377    DOUT << "  ** ARM constant pool #" << CPI << " @ "
378         << (void*)MCE.getCurrentPCValue() << " " << *ACPV << '\n';
379
380    GlobalValue *GV = ACPV->getGV();
381    if (GV) {
382      assert(!ACPV->isStub() && "Don't know how to deal this yet!");
383      if (ACPV->isNonLazyPointer())
384        MCE.addRelocation(MachineRelocation::getIndirectSymbol(
385                  MCE.getCurrentPCOffset(), ARM::reloc_arm_machine_cp_entry, GV,
386                  (intptr_t)ACPV, false));
387      else
388        emitGlobalAddress(GV, ARM::reloc_arm_machine_cp_entry,
389                          ACPV->isStub(), (intptr_t)ACPV);
390     } else  {
391      assert(!ACPV->isNonLazyPointer() && "Don't know how to deal this yet!");
392      emitExternalSymbolAddress(ACPV->getSymbol(), ARM::reloc_arm_absolute);
393    }
394    emitWordLE(0);
395  } else {
396    Constant *CV = MCPE.Val.ConstVal;
397
398    DOUT << "  ** Constant pool #" << CPI << " @ "
399         << (void*)MCE.getCurrentPCValue() << " " << *CV << '\n';
400
401    if (GlobalValue *GV = dyn_cast<GlobalValue>(CV)) {
402      emitGlobalAddress(GV, ARM::reloc_arm_absolute, false);
403      emitWordLE(0);
404    } else if (const ConstantInt *CI = dyn_cast<ConstantInt>(CV)) {
405      uint32_t Val = *(uint32_t*)CI->getValue().getRawData();
406      emitWordLE(Val);
407    } else if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CV)) {
408      if (CFP->getType() == Type::FloatTy)
409        emitWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue());
410      else if (CFP->getType() == Type::DoubleTy)
411        emitDWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue());
412      else {
413        assert(0 && "Unable to handle this constantpool entry!");
414        abort();
415      }
416    } else {
417      assert(0 && "Unable to handle this constantpool entry!");
418      abort();
419    }
420  }
421}
422
423void ARMCodeEmitter::emitMOVi2piecesInstruction(const MachineInstr &MI) {
424  const MachineOperand &MO0 = MI.getOperand(0);
425  const MachineOperand &MO1 = MI.getOperand(1);
426  assert(MO1.isImm() && "Not a valid so_imm value!");
427  unsigned V1 = ARM_AM::getSOImmTwoPartFirst(MO1.getImm());
428  unsigned V2 = ARM_AM::getSOImmTwoPartSecond(MO1.getImm());
429
430  // Emit the 'mov' instruction.
431  unsigned Binary = 0xd << 21;  // mov: Insts{24-21} = 0b1101
432
433  // Set the conditional execution predicate.
434  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
435
436  // Encode Rd.
437  Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
438
439  // Encode so_imm.
440  // Set bit I(25) to identify this is the immediate form of <shifter_op>
441  Binary |= 1 << ARMII::I_BitShift;
442  Binary |= getMachineSoImmOpValue(ARM_AM::getSOImmVal(V1));
443  emitWordLE(Binary);
444
445  // Now the 'orr' instruction.
446  Binary = 0xc << 21;  // orr: Insts{24-21} = 0b1100
447
448  // Set the conditional execution predicate.
449  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
450
451  // Encode Rd.
452  Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
453
454  // Encode Rn.
455  Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRnShift;
456
457  // Encode so_imm.
458  // Set bit I(25) to identify this is the immediate form of <shifter_op>
459  Binary |= 1 << ARMII::I_BitShift;
460  Binary |= getMachineSoImmOpValue(ARM_AM::getSOImmVal(V2));
461  emitWordLE(Binary);
462}
463
464void ARMCodeEmitter::emitLEApcrelJTInstruction(const MachineInstr &MI) {
465  // It's basically add r, pc, (LJTI - $+8)
466
467  const TargetInstrDesc &TID = MI.getDesc();
468
469  // Emit the 'add' instruction.
470  unsigned Binary = 0x4 << 21;  // add: Insts{24-31} = 0b0100
471
472  // Set the conditional execution predicate
473  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
474
475  // Encode S bit if MI modifies CPSR.
476  Binary |= getAddrModeSBit(MI, TID);
477
478  // Encode Rd.
479  Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
480
481  // Encode Rn which is PC.
482  Binary |= ARMRegisterInfo::getRegisterNumbering(ARM::PC) << ARMII::RegRnShift;
483
484  // Encode the displacement.
485  // Set bit I(25) to identify this is the immediate form of <shifter_op>.
486  Binary |= 1 << ARMII::I_BitShift;
487  emitJumpTableAddress(MI.getOperand(1).getIndex(), ARM::reloc_arm_jt_base);
488
489  emitWordLE(Binary);
490}
491
492void ARMCodeEmitter::addPCLabel(unsigned LabelID) {
493  DOUT << "  ** LPC" << LabelID << " @ "
494       << (void*)MCE.getCurrentPCValue() << '\n';
495  JTI->addPCLabelAddr(LabelID, MCE.getCurrentPCValue());
496}
497
498void ARMCodeEmitter::emitPseudoInstruction(const MachineInstr &MI) {
499  unsigned Opcode = MI.getDesc().Opcode;
500  switch (Opcode) {
501  default:
502    abort(); // FIXME:
503  case ARM::CONSTPOOL_ENTRY:
504    emitConstPoolInstruction(MI);
505    break;
506  case ARM::PICADD: {
507    // Remember of the address of the PC label for relocation later.
508    addPCLabel(MI.getOperand(2).getImm());
509    // PICADD is just an add instruction that implicitly read pc.
510    emitDataProcessingInstruction(MI, 0, ARM::PC);
511    break;
512  }
513  case ARM::PICLDR:
514  case ARM::PICLDRB:
515  case ARM::PICSTR:
516  case ARM::PICSTRB: {
517    // Remember of the address of the PC label for relocation later.
518    addPCLabel(MI.getOperand(2).getImm());
519    // These are just load / store instructions that implicitly read pc.
520    emitLoadStoreInstruction(MI, 0, ARM::PC);
521    break;
522  }
523  case ARM::PICLDRH:
524  case ARM::PICLDRSH:
525  case ARM::PICLDRSB:
526  case ARM::PICSTRH: {
527    // Remember of the address of the PC label for relocation later.
528    addPCLabel(MI.getOperand(2).getImm());
529    // These are just load / store instructions that implicitly read pc.
530    emitMiscLoadStoreInstruction(MI, ARM::PC);
531    break;
532  }
533  case ARM::MOVi2pieces:
534    // Two instructions to materialize a constant.
535    emitMOVi2piecesInstruction(MI);
536    break;
537  case ARM::LEApcrelJT:
538    // Materialize jumptable address.
539    emitLEApcrelJTInstruction(MI);
540    break;
541  }
542}
543
544
545unsigned ARMCodeEmitter::getMachineSoRegOpValue(const MachineInstr &MI,
546                                                const TargetInstrDesc &TID,
547                                                const MachineOperand &MO,
548                                                unsigned OpIdx) {
549  unsigned Binary = getMachineOpValue(MI, MO);
550
551  const MachineOperand &MO1 = MI.getOperand(OpIdx + 1);
552  const MachineOperand &MO2 = MI.getOperand(OpIdx + 2);
553  ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm());
554
555  // Encode the shift opcode.
556  unsigned SBits = 0;
557  unsigned Rs = MO1.getReg();
558  if (Rs) {
559    // Set shift operand (bit[7:4]).
560    // LSL - 0001
561    // LSR - 0011
562    // ASR - 0101
563    // ROR - 0111
564    // RRX - 0110 and bit[11:8] clear.
565    switch (SOpc) {
566    default: assert(0 && "Unknown shift opc!");
567    case ARM_AM::lsl: SBits = 0x1; break;
568    case ARM_AM::lsr: SBits = 0x3; break;
569    case ARM_AM::asr: SBits = 0x5; break;
570    case ARM_AM::ror: SBits = 0x7; break;
571    case ARM_AM::rrx: SBits = 0x6; break;
572    }
573  } else {
574    // Set shift operand (bit[6:4]).
575    // LSL - 000
576    // LSR - 010
577    // ASR - 100
578    // ROR - 110
579    switch (SOpc) {
580    default: assert(0 && "Unknown shift opc!");
581    case ARM_AM::lsl: SBits = 0x0; break;
582    case ARM_AM::lsr: SBits = 0x2; break;
583    case ARM_AM::asr: SBits = 0x4; break;
584    case ARM_AM::ror: SBits = 0x6; break;
585    }
586  }
587  Binary |= SBits << 4;
588  if (SOpc == ARM_AM::rrx)
589    return Binary;
590
591  // Encode the shift operation Rs or shift_imm (except rrx).
592  if (Rs) {
593    // Encode Rs bit[11:8].
594    assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0);
595    return Binary |
596      (ARMRegisterInfo::getRegisterNumbering(Rs) << ARMII::RegRsShift);
597  }
598
599  // Encode shift_imm bit[11:7].
600  return Binary | ARM_AM::getSORegOffset(MO2.getImm()) << 7;
601}
602
603unsigned ARMCodeEmitter::getMachineSoImmOpValue(unsigned SoImm) {
604  // Encode rotate_imm.
605  unsigned Binary = (ARM_AM::getSOImmValRot(SoImm) >> 1)
606    << ARMII::SoRotImmShift;
607
608  // Encode immed_8.
609  Binary |= ARM_AM::getSOImmValImm(SoImm);
610  return Binary;
611}
612
613unsigned ARMCodeEmitter::getAddrModeSBit(const MachineInstr &MI,
614                                         const TargetInstrDesc &TID) const {
615  for (unsigned i = MI.getNumOperands(), e = TID.getNumOperands(); i != e; --i){
616    const MachineOperand &MO = MI.getOperand(i-1);
617    if (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR)
618      return 1 << ARMII::S_BitShift;
619  }
620  return 0;
621}
622
623void ARMCodeEmitter::emitDataProcessingInstruction(const MachineInstr &MI,
624                                                   unsigned ImplicitRd,
625                                                   unsigned ImplicitRn) {
626  const TargetInstrDesc &TID = MI.getDesc();
627
628  // Part of binary is determined by TableGn.
629  unsigned Binary = getBinaryCodeForInstr(MI);
630
631  // Set the conditional execution predicate
632  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
633
634  // Encode S bit if MI modifies CPSR.
635  Binary |= getAddrModeSBit(MI, TID);
636
637  // Encode register def if there is one.
638  unsigned NumDefs = TID.getNumDefs();
639  unsigned OpIdx = 0;
640  if (NumDefs)
641    Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
642  else if (ImplicitRd)
643    // Special handling for implicit use (e.g. PC).
644    Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRd)
645               << ARMII::RegRdShift);
646
647  // If this is a two-address operand, skip it. e.g. MOVCCr operand 1.
648  if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
649    ++OpIdx;
650
651  // Encode first non-shifter register operand if there is one.
652  bool isUnary = TID.TSFlags & ARMII::UnaryDP;
653  if (!isUnary) {
654    if (ImplicitRn)
655      // Special handling for implicit use (e.g. PC).
656      Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRn)
657                 << ARMII::RegRnShift);
658    else {
659      Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRnShift;
660      ++OpIdx;
661    }
662  }
663
664  // Encode shifter operand.
665  const MachineOperand &MO = MI.getOperand(OpIdx);
666  if ((TID.TSFlags & ARMII::FormMask) == ARMII::DPSoRegFrm) {
667    // Encode SoReg.
668    emitWordLE(Binary | getMachineSoRegOpValue(MI, TID, MO, OpIdx));
669    return;
670  }
671
672  if (MO.isReg()) {
673    // Encode register Rm.
674    emitWordLE(Binary | ARMRegisterInfo::getRegisterNumbering(MO.getReg()));
675    return;
676  }
677
678  // Encode so_imm.
679  // Set bit I(25) to identify this is the immediate form of <shifter_op>.
680  Binary |= 1 << ARMII::I_BitShift;
681  Binary |= getMachineSoImmOpValue(MO.getImm());
682
683  emitWordLE(Binary);
684}
685
686void ARMCodeEmitter::emitLoadStoreInstruction(const MachineInstr &MI,
687                                              unsigned ImplicitRd,
688                                              unsigned ImplicitRn) {
689  const TargetInstrDesc &TID = MI.getDesc();
690
691  // Part of binary is determined by TableGn.
692  unsigned Binary = getBinaryCodeForInstr(MI);
693
694  // Set the conditional execution predicate
695  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
696
697  // Set first operand
698  unsigned OpIdx = 0;
699  if (ImplicitRd)
700    // Special handling for implicit use (e.g. PC).
701    Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRd)
702               << ARMII::RegRdShift);
703  else
704    Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
705
706  // Set second operand
707  if (ImplicitRn)
708    // Special handling for implicit use (e.g. PC).
709    Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRn)
710               << ARMII::RegRnShift);
711  else
712    Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
713
714  // If this is a two-address operand, skip it. e.g. LDR_PRE.
715  if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
716    ++OpIdx;
717
718  const MachineOperand &MO2 = MI.getOperand(OpIdx);
719  unsigned AM2Opc = (ImplicitRn == ARM::PC)
720    ? 0 : MI.getOperand(OpIdx+1).getImm();
721
722  // Set bit U(23) according to sign of immed value (positive or negative).
723  Binary |= ((ARM_AM::getAM2Op(AM2Opc) == ARM_AM::add ? 1 : 0) <<
724             ARMII::U_BitShift);
725  if (!MO2.getReg()) { // is immediate
726    if (ARM_AM::getAM2Offset(AM2Opc))
727      // Set the value of offset_12 field
728      Binary |= ARM_AM::getAM2Offset(AM2Opc);
729    emitWordLE(Binary);
730    return;
731  }
732
733  // Set bit I(25), because this is not in immediate enconding.
734  Binary |= 1 << ARMII::I_BitShift;
735  assert(TargetRegisterInfo::isPhysicalRegister(MO2.getReg()));
736  // Set bit[3:0] to the corresponding Rm register
737  Binary |= ARMRegisterInfo::getRegisterNumbering(MO2.getReg());
738
739  // If this instr is in scaled register offset/index instruction, set
740  // shift_immed(bit[11:7]) and shift(bit[6:5]) fields.
741  if (unsigned ShImm = ARM_AM::getAM2Offset(AM2Opc)) {
742    Binary |= getShiftOp(AM2Opc) << ARMII::ShiftImmShift;  // shift
743    Binary |= ShImm              << ARMII::ShiftShift;     // shift_immed
744  }
745
746  emitWordLE(Binary);
747}
748
749void ARMCodeEmitter::emitMiscLoadStoreInstruction(const MachineInstr &MI,
750                                                  unsigned ImplicitRn) {
751  const TargetInstrDesc &TID = MI.getDesc();
752
753  // Part of binary is determined by TableGn.
754  unsigned Binary = getBinaryCodeForInstr(MI);
755
756  // Set the conditional execution predicate
757  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
758
759  // Set first operand
760  Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
761
762  // Set second operand
763  unsigned OpIdx = 1;
764  if (ImplicitRn)
765    // Special handling for implicit use (e.g. PC).
766    Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRn)
767               << ARMII::RegRnShift);
768  else
769    Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
770
771  // If this is a two-address operand, skip it. e.g. LDRH_POST.
772  if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
773    ++OpIdx;
774
775  const MachineOperand &MO2 = MI.getOperand(OpIdx);
776  unsigned AM3Opc = (ImplicitRn == ARM::PC)
777    ? 0 : MI.getOperand(OpIdx+1).getImm();
778
779  // Set bit U(23) according to sign of immed value (positive or negative)
780  Binary |= ((ARM_AM::getAM3Op(AM3Opc) == ARM_AM::add ? 1 : 0) <<
781             ARMII::U_BitShift);
782
783  // If this instr is in register offset/index encoding, set bit[3:0]
784  // to the corresponding Rm register.
785  if (MO2.getReg()) {
786    Binary |= ARMRegisterInfo::getRegisterNumbering(MO2.getReg());
787    emitWordLE(Binary);
788    return;
789  }
790
791  // This instr is in immediate offset/index encoding, set bit 22 to 1.
792  Binary |= 1 << ARMII::AM3_I_BitShift;
793  if (unsigned ImmOffs = ARM_AM::getAM3Offset(AM3Opc)) {
794    // Set operands
795    Binary |= (ImmOffs >> 4) << ARMII::ImmHiShift;  // immedH
796    Binary |= (ImmOffs & 0xF);                      // immedL
797  }
798
799  emitWordLE(Binary);
800}
801
802static unsigned getAddrModeUPBits(unsigned Mode) {
803  unsigned Binary = 0;
804
805  // Set addressing mode by modifying bits U(23) and P(24)
806  // IA - Increment after  - bit U = 1 and bit P = 0
807  // IB - Increment before - bit U = 1 and bit P = 1
808  // DA - Decrement after  - bit U = 0 and bit P = 0
809  // DB - Decrement before - bit U = 0 and bit P = 1
810  switch (Mode) {
811  default: assert(0 && "Unknown addressing sub-mode!");
812  case ARM_AM::da:                      break;
813  case ARM_AM::db: Binary |= 0x1 << ARMII::P_BitShift; break;
814  case ARM_AM::ia: Binary |= 0x1 << ARMII::U_BitShift; break;
815  case ARM_AM::ib: Binary |= 0x3 << ARMII::U_BitShift; break;
816  }
817
818  return Binary;
819}
820
821void ARMCodeEmitter::emitLoadStoreMultipleInstruction(const MachineInstr &MI) {
822  // Part of binary is determined by TableGn.
823  unsigned Binary = getBinaryCodeForInstr(MI);
824
825  // Set the conditional execution predicate
826  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
827
828  // Set base address operand
829  Binary |= getMachineOpValue(MI, 0) << ARMII::RegRnShift;
830
831  // Set addressing mode by modifying bits U(23) and P(24)
832  const MachineOperand &MO = MI.getOperand(1);
833  Binary |= getAddrModeUPBits(ARM_AM::getAM4SubMode(MO.getImm()));
834
835  // Set bit W(21)
836  if (ARM_AM::getAM4WBFlag(MO.getImm()))
837    Binary |= 0x1 << ARMII::W_BitShift;
838
839  // Set registers
840  for (unsigned i = 4, e = MI.getNumOperands(); i != e; ++i) {
841    const MachineOperand &MO = MI.getOperand(i);
842    if (!MO.isReg() || MO.isImplicit())
843      break;
844    unsigned RegNum = ARMRegisterInfo::getRegisterNumbering(MO.getReg());
845    assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()) &&
846           RegNum < 16);
847    Binary |= 0x1 << RegNum;
848  }
849
850  emitWordLE(Binary);
851}
852
853void ARMCodeEmitter::emitMulFrmInstruction(const MachineInstr &MI) {
854  const TargetInstrDesc &TID = MI.getDesc();
855
856  // Part of binary is determined by TableGn.
857  unsigned Binary = getBinaryCodeForInstr(MI);
858
859  // Set the conditional execution predicate
860  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
861
862  // Encode S bit if MI modifies CPSR.
863  Binary |= getAddrModeSBit(MI, TID);
864
865  // 32x32->64bit operations have two destination registers. The number
866  // of register definitions will tell us if that's what we're dealing with.
867  unsigned OpIdx = 0;
868  if (TID.getNumDefs() == 2)
869    Binary |= getMachineOpValue (MI, OpIdx++) << ARMII::RegRdLoShift;
870
871  // Encode Rd
872  Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdHiShift;
873
874  // Encode Rm
875  Binary |= getMachineOpValue(MI, OpIdx++);
876
877  // Encode Rs
878  Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRsShift;
879
880  // Many multiple instructions (e.g. MLA) have three src operands. Encode
881  // it as Rn (for multiply, that's in the same offset as RdLo.
882  if (TID.getNumOperands() > OpIdx &&
883      !TID.OpInfo[OpIdx].isPredicate() &&
884      !TID.OpInfo[OpIdx].isOptionalDef())
885    Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRdLoShift;
886
887  emitWordLE(Binary);
888}
889
890void ARMCodeEmitter::emitExtendInstruction(const MachineInstr &MI) {
891  const TargetInstrDesc &TID = MI.getDesc();
892
893  // Part of binary is determined by TableGn.
894  unsigned Binary = getBinaryCodeForInstr(MI);
895
896  // Set the conditional execution predicate
897  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
898
899  unsigned OpIdx = 0;
900
901  // Encode Rd
902  Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
903
904  const MachineOperand &MO1 = MI.getOperand(OpIdx++);
905  const MachineOperand &MO2 = MI.getOperand(OpIdx);
906  if (MO2.isReg()) {
907    // Two register operand form.
908    // Encode Rn.
909    Binary |= getMachineOpValue(MI, MO1) << ARMII::RegRnShift;
910
911    // Encode Rm.
912    Binary |= getMachineOpValue(MI, MO2);
913    ++OpIdx;
914  } else {
915    Binary |= getMachineOpValue(MI, MO1);
916  }
917
918  // Encode rot imm (0, 8, 16, or 24) if it has a rotate immediate operand.
919  if (MI.getOperand(OpIdx).isImm() &&
920      !TID.OpInfo[OpIdx].isPredicate() &&
921      !TID.OpInfo[OpIdx].isOptionalDef())
922    Binary |= (getMachineOpValue(MI, OpIdx) / 8) << ARMII::ExtRotImmShift;
923
924  emitWordLE(Binary);
925}
926
927void ARMCodeEmitter::emitMiscArithInstruction(const MachineInstr &MI) {
928  const TargetInstrDesc &TID = MI.getDesc();
929
930  // Part of binary is determined by TableGn.
931  unsigned Binary = getBinaryCodeForInstr(MI);
932
933  // Set the conditional execution predicate
934  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
935
936  unsigned OpIdx = 0;
937
938  // Encode Rd
939  Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
940
941  const MachineOperand &MO = MI.getOperand(OpIdx++);
942  if (OpIdx == TID.getNumOperands() ||
943      TID.OpInfo[OpIdx].isPredicate() ||
944      TID.OpInfo[OpIdx].isOptionalDef()) {
945    // Encode Rm and it's done.
946    Binary |= getMachineOpValue(MI, MO);
947    emitWordLE(Binary);
948    return;
949  }
950
951  // Encode Rn.
952  Binary |= getMachineOpValue(MI, MO) << ARMII::RegRnShift;
953
954  // Encode Rm.
955  Binary |= getMachineOpValue(MI, OpIdx++);
956
957  // Encode shift_imm.
958  unsigned ShiftAmt = MI.getOperand(OpIdx).getImm();
959  assert(ShiftAmt < 32 && "shift_imm range is 0 to 31!");
960  Binary |= ShiftAmt << ARMII::ShiftShift;
961
962  emitWordLE(Binary);
963}
964
965void ARMCodeEmitter::emitBranchInstruction(const MachineInstr &MI) {
966  const TargetInstrDesc &TID = MI.getDesc();
967
968  if (TID.Opcode == ARM::TPsoft)
969    abort(); // FIXME
970
971  // Part of binary is determined by TableGn.
972  unsigned Binary = getBinaryCodeForInstr(MI);
973
974  // Set the conditional execution predicate
975  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
976
977  // Set signed_immed_24 field
978  Binary |= getMachineOpValue(MI, 0);
979
980  emitWordLE(Binary);
981}
982
983void ARMCodeEmitter::emitInlineJumpTable(unsigned JTIndex) {
984  // Remember the base address of the inline jump table.
985  intptr_t JTBase = MCE.getCurrentPCValue();
986  JTI->addJumpTableBaseAddr(JTIndex, JTBase);
987  DOUT << "  ** Jump Table #" << JTIndex << " @ " << (void*)JTBase << '\n';
988
989  // Now emit the jump table entries.
990  const std::vector<MachineBasicBlock*> &MBBs = (*MJTEs)[JTIndex].MBBs;
991  for (unsigned i = 0, e = MBBs.size(); i != e; ++i) {
992    if (IsPIC)
993      // DestBB address - JT base.
994      emitMachineBasicBlock(MBBs[i], ARM::reloc_arm_pic_jt, JTBase);
995    else
996      // Absolute DestBB address.
997      emitMachineBasicBlock(MBBs[i], ARM::reloc_arm_absolute);
998    emitWordLE(0);
999  }
1000}
1001
1002void ARMCodeEmitter::emitMiscBranchInstruction(const MachineInstr &MI) {
1003  const TargetInstrDesc &TID = MI.getDesc();
1004
1005  // Handle jump tables.
1006  if (TID.Opcode == ARM::BR_JTr || TID.Opcode == ARM::BR_JTadd) {
1007    // First emit a ldr pc, [] instruction.
1008    emitDataProcessingInstruction(MI, ARM::PC);
1009
1010    // Then emit the inline jump table.
1011    unsigned JTIndex = (TID.Opcode == ARM::BR_JTr)
1012      ? MI.getOperand(1).getIndex() : MI.getOperand(2).getIndex();
1013    emitInlineJumpTable(JTIndex);
1014    return;
1015  } else if (TID.Opcode == ARM::BR_JTm) {
1016    // First emit a ldr pc, [] instruction.
1017    emitLoadStoreInstruction(MI, ARM::PC);
1018
1019    // Then emit the inline jump table.
1020    emitInlineJumpTable(MI.getOperand(3).getIndex());
1021    return;
1022  }
1023
1024  // Part of binary is determined by TableGn.
1025  unsigned Binary = getBinaryCodeForInstr(MI);
1026
1027  // Set the conditional execution predicate
1028  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1029
1030  if (TID.Opcode == ARM::BX_RET)
1031    // The return register is LR.
1032    Binary |= ARMRegisterInfo::getRegisterNumbering(ARM::LR);
1033  else
1034    // otherwise, set the return register
1035    Binary |= getMachineOpValue(MI, 0);
1036
1037  emitWordLE(Binary);
1038}
1039
1040static unsigned encodeVFPRd(const MachineInstr &MI, unsigned OpIdx) {
1041  unsigned RegD = MI.getOperand(OpIdx).getReg();
1042  unsigned Binary = 0;
1043  bool isSPVFP = false;
1044  RegD = ARMRegisterInfo::getRegisterNumbering(RegD, isSPVFP);
1045  if (!isSPVFP)
1046    Binary |=   RegD               << ARMII::RegRdShift;
1047  else {
1048    Binary |= ((RegD & 0x1E) >> 1) << ARMII::RegRdShift;
1049    Binary |=  (RegD & 0x01)       << ARMII::D_BitShift;
1050  }
1051  return Binary;
1052}
1053
1054static unsigned encodeVFPRn(const MachineInstr &MI, unsigned OpIdx) {
1055  unsigned RegN = MI.getOperand(OpIdx).getReg();
1056  unsigned Binary = 0;
1057  bool isSPVFP = false;
1058  RegN = ARMRegisterInfo::getRegisterNumbering(RegN, isSPVFP);
1059  if (!isSPVFP)
1060    Binary |=   RegN               << ARMII::RegRnShift;
1061  else {
1062    Binary |= ((RegN & 0x1E) >> 1) << ARMII::RegRnShift;
1063    Binary |=  (RegN & 0x01)       << ARMII::N_BitShift;
1064  }
1065  return Binary;
1066}
1067
1068static unsigned encodeVFPRm(const MachineInstr &MI, unsigned OpIdx) {
1069  unsigned RegM = MI.getOperand(OpIdx).getReg();
1070  unsigned Binary = 0;
1071  bool isSPVFP = false;
1072  RegM = ARMRegisterInfo::getRegisterNumbering(RegM, isSPVFP);
1073  if (!isSPVFP)
1074    Binary |=   RegM;
1075  else {
1076    Binary |= ((RegM & 0x1E) >> 1);
1077    Binary |=  (RegM & 0x01)       << ARMII::M_BitShift;
1078  }
1079  return Binary;
1080}
1081
1082void ARMCodeEmitter::emitVFPArithInstruction(const MachineInstr &MI) {
1083  const TargetInstrDesc &TID = MI.getDesc();
1084
1085  // Part of binary is determined by TableGn.
1086  unsigned Binary = getBinaryCodeForInstr(MI);
1087
1088  // Set the conditional execution predicate
1089  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1090
1091  unsigned OpIdx = 0;
1092  assert((Binary & ARMII::D_BitShift) == 0 &&
1093         (Binary & ARMII::N_BitShift) == 0 &&
1094         (Binary & ARMII::M_BitShift) == 0 && "VFP encoding bug!");
1095
1096  // Encode Dd / Sd.
1097  Binary |= encodeVFPRd(MI, OpIdx++);
1098
1099  // If this is a two-address operand, skip it, e.g. FMACD.
1100  if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1101    ++OpIdx;
1102
1103  // Encode Dn / Sn.
1104  if ((TID.TSFlags & ARMII::FormMask) == ARMII::VFPBinaryFrm)
1105    Binary |= encodeVFPRn(MI, OpIdx++);
1106
1107  if (OpIdx == TID.getNumOperands() ||
1108      TID.OpInfo[OpIdx].isPredicate() ||
1109      TID.OpInfo[OpIdx].isOptionalDef()) {
1110    // FCMPEZD etc. has only one operand.
1111    emitWordLE(Binary);
1112    return;
1113  }
1114
1115  // Encode Dm / Sm.
1116  Binary |= encodeVFPRm(MI, OpIdx);
1117
1118  emitWordLE(Binary);
1119}
1120
1121void ARMCodeEmitter::emitVFPConversionInstruction(const MachineInstr &MI) {
1122  const TargetInstrDesc &TID = MI.getDesc();
1123  unsigned Form = TID.TSFlags & ARMII::FormMask;
1124
1125  // Part of binary is determined by TableGn.
1126  unsigned Binary = getBinaryCodeForInstr(MI);
1127
1128  // Set the conditional execution predicate
1129  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1130
1131  switch (Form) {
1132  default: break;
1133  case ARMII::VFPConv1Frm:
1134  case ARMII::VFPConv2Frm:
1135  case ARMII::VFPConv3Frm:
1136    // Encode Dd / Sd.
1137    Binary |= encodeVFPRd(MI, 0);
1138    break;
1139  case ARMII::VFPConv4Frm:
1140    // Encode Dn / Sn.
1141    Binary |= encodeVFPRn(MI, 0);
1142    break;
1143  case ARMII::VFPConv5Frm:
1144    // Encode Dm / Sm.
1145    Binary |= encodeVFPRm(MI, 0);
1146    break;
1147  }
1148
1149  switch (Form) {
1150  default: break;
1151  case ARMII::VFPConv1Frm:
1152    // Encode Dm / Sm.
1153    Binary |= encodeVFPRm(MI, 1);
1154  case ARMII::VFPConv2Frm:
1155  case ARMII::VFPConv3Frm:
1156    // Encode Dn / Sn.
1157    Binary |= encodeVFPRn(MI, 1);
1158    break;
1159  case ARMII::VFPConv4Frm:
1160  case ARMII::VFPConv5Frm:
1161    // Encode Dd / Sd.
1162    Binary |= encodeVFPRd(MI, 1);
1163    break;
1164  }
1165
1166  if (Form == ARMII::VFPConv5Frm)
1167    // Encode Dn / Sn.
1168    Binary |= encodeVFPRn(MI, 2);
1169  else if (Form == ARMII::VFPConv3Frm)
1170    // Encode Dm / Sm.
1171    Binary |= encodeVFPRm(MI, 2);
1172
1173  emitWordLE(Binary);
1174}
1175
1176void ARMCodeEmitter::emitVFPLoadStoreInstruction(const MachineInstr &MI) {
1177  // Part of binary is determined by TableGn.
1178  unsigned Binary = getBinaryCodeForInstr(MI);
1179
1180  // Set the conditional execution predicate
1181  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1182
1183  unsigned OpIdx = 0;
1184
1185  // Encode Dd / Sd.
1186  Binary |= encodeVFPRd(MI, OpIdx++);
1187
1188  // Encode address base.
1189  const MachineOperand &Base = MI.getOperand(OpIdx++);
1190  Binary |= getMachineOpValue(MI, Base) << ARMII::RegRnShift;
1191
1192  // If there is a non-zero immediate offset, encode it.
1193  if (Base.isReg()) {
1194    const MachineOperand &Offset = MI.getOperand(OpIdx);
1195    if (unsigned ImmOffs = ARM_AM::getAM5Offset(Offset.getImm())) {
1196      if (ARM_AM::getAM5Op(Offset.getImm()) == ARM_AM::add)
1197        Binary |= 1 << ARMII::U_BitShift;
1198      // Immediate offset is multiplied by 4.
1199      Binary |= ImmOffs >> 2;
1200      emitWordLE(Binary);
1201      return;
1202    }
1203  }
1204
1205  // If immediate offset is omitted, default to +0.
1206  Binary |= 1 << ARMII::U_BitShift;
1207
1208  emitWordLE(Binary);
1209}
1210
1211void
1212ARMCodeEmitter::emitVFPLoadStoreMultipleInstruction(const MachineInstr &MI) {
1213  // Part of binary is determined by TableGn.
1214  unsigned Binary = getBinaryCodeForInstr(MI);
1215
1216  // Set the conditional execution predicate
1217  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1218
1219  // Set base address operand
1220  Binary |= getMachineOpValue(MI, 0) << ARMII::RegRnShift;
1221
1222  // Set addressing mode by modifying bits U(23) and P(24)
1223  const MachineOperand &MO = MI.getOperand(1);
1224  Binary |= getAddrModeUPBits(ARM_AM::getAM5SubMode(MO.getImm()));
1225
1226  // Set bit W(21)
1227  if (ARM_AM::getAM5WBFlag(MO.getImm()))
1228    Binary |= 0x1 << ARMII::W_BitShift;
1229
1230  // First register is encoded in Dd.
1231  Binary |= encodeVFPRd(MI, 4);
1232
1233  // Number of registers are encoded in offset field.
1234  unsigned NumRegs = 1;
1235  for (unsigned i = 5, e = MI.getNumOperands(); i != e; ++i) {
1236    const MachineOperand &MO = MI.getOperand(i);
1237    if (!MO.isReg() || MO.isImplicit())
1238      break;
1239    ++NumRegs;
1240  }
1241  Binary |= NumRegs * 2;
1242
1243  emitWordLE(Binary);
1244}
1245
1246void ARMCodeEmitter::emitMiscInstruction(const MachineInstr &MI) {
1247  // Part of binary is determined by TableGn.
1248  unsigned Binary = getBinaryCodeForInstr(MI);
1249
1250  // Set the conditional execution predicate
1251  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1252
1253  emitWordLE(Binary);
1254}
1255
1256#include "ARMGenCodeEmitter.inc"
1257