ARMCodeEmitter.cpp revision 3fea19105d4929ad694f0b6272de31924c9f9f09 
1//===-- ARM/ARMCodeEmitter.cpp - Convert ARM code to machine code ---------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the pass that transforms the ARM machine instructions into
11// relocatable machine code.
12//
13//===----------------------------------------------------------------------===//
14
15#define DEBUG_TYPE "jit"
16#include "ARM.h"
17#include "ARMAddressingModes.h"
18#include "ARMConstantPoolValue.h"
19#include "ARMInstrInfo.h"
20#include "ARMRelocations.h"
21#include "ARMSubtarget.h"
22#include "ARMTargetMachine.h"
23#include "llvm/Constants.h"
24#include "llvm/DerivedTypes.h"
25#include "llvm/Function.h"
26#include "llvm/PassManager.h"
27#include "llvm/CodeGen/JITCodeEmitter.h"
28#include "llvm/CodeGen/MachineConstantPool.h"
29#include "llvm/CodeGen/MachineFunctionPass.h"
30#include "llvm/CodeGen/MachineInstr.h"
31#include "llvm/CodeGen/MachineJumpTableInfo.h"
32#include "llvm/CodeGen/MachineModuleInfo.h"
33#include "llvm/CodeGen/Passes.h"
34#include "llvm/ADT/Statistic.h"
35#include "llvm/Support/Debug.h"
36#include "llvm/Support/ErrorHandling.h"
37#include "llvm/Support/raw_ostream.h"
38#ifndef NDEBUG
39#include <iomanip>
40#endif
41using namespace llvm;
42
43STATISTIC(NumEmitted, "Number of machine instructions emitted");
44
45namespace {
46
47  class ARMCodeEmitter : public MachineFunctionPass {
48    ARMJITInfo                *JTI;
49    const ARMInstrInfo        *II;
50    const TargetData          *TD;
51    const ARMSubtarget        *Subtarget;
52    TargetMachine             &TM;
53    JITCodeEmitter            &MCE;
54    MachineModuleInfo *MMI;
55    const std::vector<MachineConstantPoolEntry> *MCPEs;
56    const std::vector<MachineJumpTableEntry> *MJTEs;
57    bool IsPIC;
58    bool IsThumb;
59
60    void getAnalysisUsage(AnalysisUsage &AU) const {
61      AU.addRequired<MachineModuleInfo>();
62      MachineFunctionPass::getAnalysisUsage(AU);
63    }
64
65    static char ID;
66  public:
67    ARMCodeEmitter(TargetMachine &tm, JITCodeEmitter &mce)
68      : MachineFunctionPass(ID), JTI(0),
69        II((const ARMInstrInfo *)tm.getInstrInfo()),
70        TD(tm.getTargetData()), TM(tm),
71        MCE(mce), MCPEs(0), MJTEs(0),
72        IsPIC(TM.getRelocationModel() == Reloc::PIC_), IsThumb(false) {}
73
74    /// getBinaryCodeForInstr - This function, generated by the
75    /// CodeEmitterGenerator using TableGen, produces the binary encoding for
76    /// machine instructions.
77    unsigned getBinaryCodeForInstr(const MachineInstr &MI) const;
78
79    bool runOnMachineFunction(MachineFunction &MF);
80
81    virtual const char *getPassName() const {
82      return "ARM Machine Code Emitter";
83    }
84
85    void emitInstruction(const MachineInstr &MI);
86
87  private:
88
89    void emitWordLE(unsigned Binary);
90    void emitDWordLE(uint64_t Binary);
91    void emitConstPoolInstruction(const MachineInstr &MI);
92    void emitMOVi32immInstruction(const MachineInstr &MI);
93    void emitMOVi2piecesInstruction(const MachineInstr &MI);
94    void emitLEApcrelJTInstruction(const MachineInstr &MI);
95    void emitPseudoMoveInstruction(const MachineInstr &MI);
96    void addPCLabel(unsigned LabelID);
97    void emitPseudoInstruction(const MachineInstr &MI);
98    unsigned getMachineSoRegOpValue(const MachineInstr &MI,
99                                    const TargetInstrDesc &TID,
100                                    const MachineOperand &MO,
101                                    unsigned OpIdx);
102
103    unsigned getMachineSoImmOpValue(unsigned SoImm);
104
105    unsigned getAddrModeSBit(const MachineInstr &MI,
106                             const TargetInstrDesc &TID) const;
107
108    void emitDataProcessingInstruction(const MachineInstr &MI,
109                                       unsigned ImplicitRd = 0,
110                                       unsigned ImplicitRn = 0);
111
112    void emitLoadStoreInstruction(const MachineInstr &MI,
113                                  unsigned ImplicitRd = 0,
114                                  unsigned ImplicitRn = 0);
115
116    void emitMiscLoadStoreInstruction(const MachineInstr &MI,
117                                      unsigned ImplicitRn = 0);
118
119    void emitLoadStoreMultipleInstruction(const MachineInstr &MI);
120
121    void emitMulFrmInstruction(const MachineInstr &MI);
122
123    void emitExtendInstruction(const MachineInstr &MI);
124
125    void emitMiscArithInstruction(const MachineInstr &MI);
126
127    void emitSaturateInstruction(const MachineInstr &MI);
128
129    void emitBranchInstruction(const MachineInstr &MI);
130
131    void emitInlineJumpTable(unsigned JTIndex);
132
133    void emitMiscBranchInstruction(const MachineInstr &MI);
134
135    void emitVFPArithInstruction(const MachineInstr &MI);
136
137    void emitVFPConversionInstruction(const MachineInstr &MI);
138
139    void emitVFPLoadStoreInstruction(const MachineInstr &MI);
140
141    void emitVFPLoadStoreMultipleInstruction(const MachineInstr &MI);
142
143    void emitNEONLaneInstruction(const MachineInstr &MI);
144    void emitNEONDupInstruction(const MachineInstr &MI);
145    void emitNEON1RegModImmInstruction(const MachineInstr &MI);
146    void emitNEON2RegInstruction(const MachineInstr &MI);
147    void emitNEON3RegInstruction(const MachineInstr &MI);
148
149    /// getMachineOpValue - Return binary encoding of operand. If the machine
150    /// operand requires relocation, record the relocation and return zero.
151    unsigned getMachineOpValue(const MachineInstr &MI,
152                               const MachineOperand &MO) const;
153    unsigned getMachineOpValue(const MachineInstr &MI, unsigned OpIdx) const {
154      return getMachineOpValue(MI, MI.getOperand(OpIdx));
155    }
156
157    // FIXME: The legacy JIT ARMCodeEmitter doesn't rely on the the
158    //  TableGen'erated getBinaryCodeForInstr() function to encode any
159    //  operand values, instead querying getMachineOpValue() directly for
160    //  each operand it needs to encode. Thus, any of the new encoder
161    //  helper functions can simply return 0 as the values the return
162    //  are already handled elsewhere. They are placeholders to allow this
163    //  encoder to continue to function until the MC encoder is sufficiently
164    //  far along that this one can be eliminated entirely.
165    unsigned getCCOutOpValue(const MachineInstr &MI, unsigned Op)
166      const { return 0; }
167    unsigned getSOImmOpValue(const MachineInstr &MI, unsigned Op)
168      const { return 0; }
169    unsigned getSORegOpValue(const MachineInstr &MI, unsigned Op)
170      const { return 0; }
171    unsigned getRotImmOpValue(const MachineInstr &MI, unsigned Op)
172      const { return 0; }
173    unsigned getImmMinusOneOpValue(const MachineInstr &MI, unsigned Op)
174      const { return 0; }
175    unsigned getBitfieldInvertedMaskOpValue(const MachineInstr &MI,
176                                            unsigned Op) const { return 0; }
177
178    /// getMovi32Value - Return binary encoding of operand for movw/movt. If the
179    /// machine operand requires relocation, record the relocation and return
180    /// zero.
181    unsigned getMovi32Value(const MachineInstr &MI,const MachineOperand &MO,
182                            unsigned Reloc);
183
184    /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
185    ///
186    unsigned getShiftOp(unsigned Imm) const ;
187
188    /// Routines that handle operands which add machine relocations which are
189    /// fixed up by the relocation stage.
190    void emitGlobalAddress(const GlobalValue *GV, unsigned Reloc,
191                           bool MayNeedFarStub,  bool Indirect,
192                           intptr_t ACPV = 0) const;
193    void emitExternalSymbolAddress(const char *ES, unsigned Reloc) const;
194    void emitConstPoolAddress(unsigned CPI, unsigned Reloc) const;
195    void emitJumpTableAddress(unsigned JTIndex, unsigned Reloc) const;
196    void emitMachineBasicBlock(MachineBasicBlock *BB, unsigned Reloc,
197                               intptr_t JTBase = 0) const;
198  };
199}
200
201char ARMCodeEmitter::ID = 0;
202
203/// createARMJITCodeEmitterPass - Return a pass that emits the collected ARM
204/// code to the specified MCE object.
205FunctionPass *llvm::createARMJITCodeEmitterPass(ARMBaseTargetMachine &TM,
206                                                JITCodeEmitter &JCE) {
207  return new ARMCodeEmitter(TM, JCE);
208}
209
210bool ARMCodeEmitter::runOnMachineFunction(MachineFunction &MF) {
211  assert((MF.getTarget().getRelocationModel() != Reloc::Default ||
212          MF.getTarget().getRelocationModel() != Reloc::Static) &&
213         "JIT relocation model must be set to static or default!");
214  JTI = ((ARMTargetMachine &)MF.getTarget()).getJITInfo();
215  II = ((const ARMTargetMachine &)MF.getTarget()).getInstrInfo();
216  TD = ((const ARMTargetMachine &)MF.getTarget()).getTargetData();
217  Subtarget = &TM.getSubtarget<ARMSubtarget>();
218  MCPEs = &MF.getConstantPool()->getConstants();
219  MJTEs = 0;
220  if (MF.getJumpTableInfo()) MJTEs = &MF.getJumpTableInfo()->getJumpTables();
221  IsPIC = TM.getRelocationModel() == Reloc::PIC_;
222  IsThumb = MF.getInfo<ARMFunctionInfo>()->isThumbFunction();
223  JTI->Initialize(MF, IsPIC);
224  MMI = &getAnalysis<MachineModuleInfo>();
225  MCE.setModuleInfo(MMI);
226
227  do {
228    DEBUG(errs() << "JITTing function '"
229          << MF.getFunction()->getName() << "'\n");
230    MCE.startFunction(MF);
231    for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();
232         MBB != E; ++MBB) {
233      MCE.StartMachineBasicBlock(MBB);
234      for (MachineBasicBlock::const_iterator I = MBB->begin(), E = MBB->end();
235           I != E; ++I)
236        emitInstruction(*I);
237    }
238  } while (MCE.finishFunction(MF));
239
240  return false;
241}
242
243/// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
244///
245unsigned ARMCodeEmitter::getShiftOp(unsigned Imm) const {
246  switch (ARM_AM::getAM2ShiftOpc(Imm)) {
247  default: llvm_unreachable("Unknown shift opc!");
248  case ARM_AM::asr: return 2;
249  case ARM_AM::lsl: return 0;
250  case ARM_AM::lsr: return 1;
251  case ARM_AM::ror:
252  case ARM_AM::rrx: return 3;
253  }
254  return 0;
255}
256
257/// getMovi32Value - Return binary encoding of operand for movw/movt. If the
258/// machine operand requires relocation, record the relocation and return zero.
259unsigned ARMCodeEmitter::getMovi32Value(const MachineInstr &MI,
260                                        const MachineOperand &MO,
261                                        unsigned Reloc) {
262  assert(((Reloc == ARM::reloc_arm_movt) || (Reloc == ARM::reloc_arm_movw))
263      && "Relocation to this function should be for movt or movw");
264
265  if (MO.isImm())
266    return static_cast<unsigned>(MO.getImm());
267  else if (MO.isGlobal())
268    emitGlobalAddress(MO.getGlobal(), Reloc, true, false);
269  else if (MO.isSymbol())
270    emitExternalSymbolAddress(MO.getSymbolName(), Reloc);
271  else if (MO.isMBB())
272    emitMachineBasicBlock(MO.getMBB(), Reloc);
273  else {
274#ifndef NDEBUG
275    errs() << MO;
276#endif
277    llvm_unreachable("Unsupported operand type for movw/movt");
278  }
279  return 0;
280}
281
282/// getMachineOpValue - Return binary encoding of operand. If the machine
283/// operand requires relocation, record the relocation and return zero.
284unsigned ARMCodeEmitter::getMachineOpValue(const MachineInstr &MI,
285                                           const MachineOperand &MO) const {
286  if (MO.isReg())
287    return getARMRegisterNumbering(MO.getReg());
288  else if (MO.isImm())
289    return static_cast<unsigned>(MO.getImm());
290  else if (MO.isGlobal())
291    emitGlobalAddress(MO.getGlobal(), ARM::reloc_arm_branch, true, false);
292  else if (MO.isSymbol())
293    emitExternalSymbolAddress(MO.getSymbolName(), ARM::reloc_arm_branch);
294  else if (MO.isCPI()) {
295    const TargetInstrDesc &TID = MI.getDesc();
296    // For VFP load, the immediate offset is multiplied by 4.
297    unsigned Reloc =  ((TID.TSFlags & ARMII::FormMask) == ARMII::VFPLdStFrm)
298      ? ARM::reloc_arm_vfp_cp_entry : ARM::reloc_arm_cp_entry;
299    emitConstPoolAddress(MO.getIndex(), Reloc);
300  } else if (MO.isJTI())
301    emitJumpTableAddress(MO.getIndex(), ARM::reloc_arm_relative);
302  else if (MO.isMBB())
303    emitMachineBasicBlock(MO.getMBB(), ARM::reloc_arm_branch);
304  else {
305#ifndef NDEBUG
306    errs() << MO;
307#endif
308    llvm_unreachable(0);
309  }
310  return 0;
311}
312
313/// emitGlobalAddress - Emit the specified address to the code stream.
314///
315void ARMCodeEmitter::emitGlobalAddress(const GlobalValue *GV, unsigned Reloc,
316                                       bool MayNeedFarStub, bool Indirect,
317                                       intptr_t ACPV) const {
318  MachineRelocation MR = Indirect
319    ? MachineRelocation::getIndirectSymbol(MCE.getCurrentPCOffset(), Reloc,
320                                           const_cast<GlobalValue *>(GV),
321                                           ACPV, MayNeedFarStub)
322    : MachineRelocation::getGV(MCE.getCurrentPCOffset(), Reloc,
323                               const_cast<GlobalValue *>(GV), ACPV,
324                               MayNeedFarStub);
325  MCE.addRelocation(MR);
326}
327
328/// emitExternalSymbolAddress - Arrange for the address of an external symbol to
329/// be emitted to the current location in the function, and allow it to be PC
330/// relative.
331void ARMCodeEmitter::
332emitExternalSymbolAddress(const char *ES, unsigned Reloc) const {
333  MCE.addRelocation(MachineRelocation::getExtSym(MCE.getCurrentPCOffset(),
334                                                 Reloc, ES));
335}
336
337/// emitConstPoolAddress - Arrange for the address of an constant pool
338/// to be emitted to the current location in the function, and allow it to be PC
339/// relative.
340void ARMCodeEmitter::emitConstPoolAddress(unsigned CPI, unsigned Reloc) const {
341  // Tell JIT emitter we'll resolve the address.
342  MCE.addRelocation(MachineRelocation::getConstPool(MCE.getCurrentPCOffset(),
343                                                    Reloc, CPI, 0, true));
344}
345
346/// emitJumpTableAddress - Arrange for the address of a jump table to
347/// be emitted to the current location in the function, and allow it to be PC
348/// relative.
349void ARMCodeEmitter::
350emitJumpTableAddress(unsigned JTIndex, unsigned Reloc) const {
351  MCE.addRelocation(MachineRelocation::getJumpTable(MCE.getCurrentPCOffset(),
352                                                    Reloc, JTIndex, 0, true));
353}
354
355/// emitMachineBasicBlock - Emit the specified address basic block.
356void ARMCodeEmitter::emitMachineBasicBlock(MachineBasicBlock *BB,
357                                           unsigned Reloc,
358                                           intptr_t JTBase) const {
359  MCE.addRelocation(MachineRelocation::getBB(MCE.getCurrentPCOffset(),
360                                             Reloc, BB, JTBase));
361}
362
363void ARMCodeEmitter::emitWordLE(unsigned Binary) {
364  DEBUG(errs() << "  0x";
365        errs().write_hex(Binary) << "\n");
366  MCE.emitWordLE(Binary);
367}
368
369void ARMCodeEmitter::emitDWordLE(uint64_t Binary) {
370  DEBUG(errs() << "  0x";
371        errs().write_hex(Binary) << "\n");
372  MCE.emitDWordLE(Binary);
373}
374
375void ARMCodeEmitter::emitInstruction(const MachineInstr &MI) {
376  DEBUG(errs() << "JIT: " << (void*)MCE.getCurrentPCValue() << ":\t" << MI);
377
378  MCE.processDebugLoc(MI.getDebugLoc(), true);
379
380  ++NumEmitted;  // Keep track of the # of mi's emitted
381  switch (MI.getDesc().TSFlags & ARMII::FormMask) {
382  default: {
383    llvm_unreachable("Unhandled instruction encoding format!");
384    break;
385  }
386  case ARMII::Pseudo:
387    emitPseudoInstruction(MI);
388    break;
389  case ARMII::DPFrm:
390  case ARMII::DPSoRegFrm:
391    emitDataProcessingInstruction(MI);
392    break;
393  case ARMII::LdFrm:
394  case ARMII::StFrm:
395    emitLoadStoreInstruction(MI);
396    break;
397  case ARMII::LdMiscFrm:
398  case ARMII::StMiscFrm:
399    emitMiscLoadStoreInstruction(MI);
400    break;
401  case ARMII::LdStMulFrm:
402    emitLoadStoreMultipleInstruction(MI);
403    break;
404  case ARMII::MulFrm:
405    emitMulFrmInstruction(MI);
406    break;
407  case ARMII::ExtFrm:
408    emitExtendInstruction(MI);
409    break;
410  case ARMII::ArithMiscFrm:
411    emitMiscArithInstruction(MI);
412    break;
413  case ARMII::SatFrm:
414    emitSaturateInstruction(MI);
415    break;
416  case ARMII::BrFrm:
417    emitBranchInstruction(MI);
418    break;
419  case ARMII::BrMiscFrm:
420    emitMiscBranchInstruction(MI);
421    break;
422  // VFP instructions.
423  case ARMII::VFPUnaryFrm:
424  case ARMII::VFPBinaryFrm:
425    emitVFPArithInstruction(MI);
426    break;
427  case ARMII::VFPConv1Frm:
428  case ARMII::VFPConv2Frm:
429  case ARMII::VFPConv3Frm:
430  case ARMII::VFPConv4Frm:
431  case ARMII::VFPConv5Frm:
432    emitVFPConversionInstruction(MI);
433    break;
434  case ARMII::VFPLdStFrm:
435    emitVFPLoadStoreInstruction(MI);
436    break;
437  case ARMII::VFPLdStMulFrm:
438    emitVFPLoadStoreMultipleInstruction(MI);
439    break;
440
441  // NEON instructions.
442  case ARMII::NGetLnFrm:
443  case ARMII::NSetLnFrm:
444    emitNEONLaneInstruction(MI);
445    break;
446  case ARMII::NDupFrm:
447    emitNEONDupInstruction(MI);
448    break;
449  case ARMII::N1RegModImmFrm:
450    emitNEON1RegModImmInstruction(MI);
451    break;
452  case ARMII::N2RegFrm:
453    emitNEON2RegInstruction(MI);
454    break;
455  case ARMII::N3RegFrm:
456    emitNEON3RegInstruction(MI);
457    break;
458  }
459  MCE.processDebugLoc(MI.getDebugLoc(), false);
460}
461
462void ARMCodeEmitter::emitConstPoolInstruction(const MachineInstr &MI) {
463  unsigned CPI = MI.getOperand(0).getImm();       // CP instruction index.
464  unsigned CPIndex = MI.getOperand(1).getIndex(); // Actual cp entry index.
465  const MachineConstantPoolEntry &MCPE = (*MCPEs)[CPIndex];
466
467  // Remember the CONSTPOOL_ENTRY address for later relocation.
468  JTI->addConstantPoolEntryAddr(CPI, MCE.getCurrentPCValue());
469
470  // Emit constpool island entry. In most cases, the actual values will be
471  // resolved and relocated after code emission.
472  if (MCPE.isMachineConstantPoolEntry()) {
473    ARMConstantPoolValue *ACPV =
474      static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal);
475
476    DEBUG(errs() << "  ** ARM constant pool #" << CPI << " @ "
477          << (void*)MCE.getCurrentPCValue() << " " << *ACPV << '\n');
478
479    assert(ACPV->isGlobalValue() && "unsupported constant pool value");
480    const GlobalValue *GV = ACPV->getGV();
481    if (GV) {
482      Reloc::Model RelocM = TM.getRelocationModel();
483      emitGlobalAddress(GV, ARM::reloc_arm_machine_cp_entry,
484                        isa<Function>(GV),
485                        Subtarget->GVIsIndirectSymbol(GV, RelocM),
486                        (intptr_t)ACPV);
487     } else  {
488      emitExternalSymbolAddress(ACPV->getSymbol(), ARM::reloc_arm_absolute);
489    }
490    emitWordLE(0);
491  } else {
492    const Constant *CV = MCPE.Val.ConstVal;
493
494    DEBUG({
495        errs() << "  ** Constant pool #" << CPI << " @ "
496               << (void*)MCE.getCurrentPCValue() << " ";
497        if (const Function *F = dyn_cast<Function>(CV))
498          errs() << F->getName();
499        else
500          errs() << *CV;
501        errs() << '\n';
502      });
503
504    if (const GlobalValue *GV = dyn_cast<GlobalValue>(CV)) {
505      emitGlobalAddress(GV, ARM::reloc_arm_absolute, isa<Function>(GV), false);
506      emitWordLE(0);
507    } else if (const ConstantInt *CI = dyn_cast<ConstantInt>(CV)) {
508      uint32_t Val = *(uint32_t*)CI->getValue().getRawData();
509      emitWordLE(Val);
510    } else if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CV)) {
511      if (CFP->getType()->isFloatTy())
512        emitWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue());
513      else if (CFP->getType()->isDoubleTy())
514        emitDWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue());
515      else {
516        llvm_unreachable("Unable to handle this constantpool entry!");
517      }
518    } else {
519      llvm_unreachable("Unable to handle this constantpool entry!");
520    }
521  }
522}
523
524void ARMCodeEmitter::emitMOVi32immInstruction(const MachineInstr &MI) {
525  const MachineOperand &MO0 = MI.getOperand(0);
526  const MachineOperand &MO1 = MI.getOperand(1);
527
528  // Emit the 'movw' instruction.
529  unsigned Binary = 0x30 << 20;  // mov: Insts{27-20} = 0b00110000
530
531  unsigned Lo16 = getMovi32Value(MI, MO1, ARM::reloc_arm_movw) & 0xFFFF;
532
533  // Set the conditional execution predicate.
534  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
535
536  // Encode Rd.
537  Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
538
539  // Encode imm16 as imm4:imm12
540  Binary |= Lo16 & 0xFFF; // Insts{11-0} = imm12
541  Binary |= ((Lo16 >> 12) & 0xF) << 16; // Insts{19-16} = imm4
542  emitWordLE(Binary);
543
544  unsigned Hi16 = getMovi32Value(MI, MO1, ARM::reloc_arm_movt) >> 16;
545  // Emit the 'movt' instruction.
546  Binary = 0x34 << 20; // movt: Insts{27-20} = 0b00110100
547
548  // Set the conditional execution predicate.
549  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
550
551  // Encode Rd.
552  Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
553
554  // Encode imm16 as imm4:imm1, same as movw above.
555  Binary |= Hi16 & 0xFFF;
556  Binary |= ((Hi16 >> 12) & 0xF) << 16;
557  emitWordLE(Binary);
558}
559
560void ARMCodeEmitter::emitMOVi2piecesInstruction(const MachineInstr &MI) {
561  const MachineOperand &MO0 = MI.getOperand(0);
562  const MachineOperand &MO1 = MI.getOperand(1);
563  assert(MO1.isImm() && ARM_AM::isSOImmTwoPartVal(MO1.getImm()) &&
564                                                  "Not a valid so_imm value!");
565  unsigned V1 = ARM_AM::getSOImmTwoPartFirst(MO1.getImm());
566  unsigned V2 = ARM_AM::getSOImmTwoPartSecond(MO1.getImm());
567
568  // Emit the 'mov' instruction.
569  unsigned Binary = 0xd << 21;  // mov: Insts{24-21} = 0b1101
570
571  // Set the conditional execution predicate.
572  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
573
574  // Encode Rd.
575  Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
576
577  // Encode so_imm.
578  // Set bit I(25) to identify this is the immediate form of <shifter_op>
579  Binary |= 1 << ARMII::I_BitShift;
580  Binary |= getMachineSoImmOpValue(V1);
581  emitWordLE(Binary);
582
583  // Now the 'orr' instruction.
584  Binary = 0xc << 21;  // orr: Insts{24-21} = 0b1100
585
586  // Set the conditional execution predicate.
587  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
588
589  // Encode Rd.
590  Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
591
592  // Encode Rn.
593  Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRnShift;
594
595  // Encode so_imm.
596  // Set bit I(25) to identify this is the immediate form of <shifter_op>
597  Binary |= 1 << ARMII::I_BitShift;
598  Binary |= getMachineSoImmOpValue(V2);
599  emitWordLE(Binary);
600}
601
602void ARMCodeEmitter::emitLEApcrelJTInstruction(const MachineInstr &MI) {
603  // It's basically add r, pc, (LJTI - $+8)
604
605  const TargetInstrDesc &TID = MI.getDesc();
606
607  // Emit the 'add' instruction.
608  unsigned Binary = 0x4 << 21;  // add: Insts{24-31} = 0b0100
609
610  // Set the conditional execution predicate
611  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
612
613  // Encode S bit if MI modifies CPSR.
614  Binary |= getAddrModeSBit(MI, TID);
615
616  // Encode Rd.
617  Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
618
619  // Encode Rn which is PC.
620  Binary |= getARMRegisterNumbering(ARM::PC) << ARMII::RegRnShift;
621
622  // Encode the displacement.
623  Binary |= 1 << ARMII::I_BitShift;
624  emitJumpTableAddress(MI.getOperand(1).getIndex(), ARM::reloc_arm_jt_base);
625
626  emitWordLE(Binary);
627}
628
629void ARMCodeEmitter::emitPseudoMoveInstruction(const MachineInstr &MI) {
630  unsigned Opcode = MI.getDesc().Opcode;
631
632  // Part of binary is determined by TableGn.
633  unsigned Binary = getBinaryCodeForInstr(MI);
634
635  // Set the conditional execution predicate
636  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
637
638  // Encode S bit if MI modifies CPSR.
639  if (Opcode == ARM::MOVsrl_flag || Opcode == ARM::MOVsra_flag)
640    Binary |= 1 << ARMII::S_BitShift;
641
642  // Encode register def if there is one.
643  Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
644
645  // Encode the shift operation.
646  switch (Opcode) {
647  default: break;
648  case ARM::RRX:
649    // rrx
650    Binary |= 0x6 << 4;
651    break;
652  case ARM::MOVsrl_flag:
653    // lsr #1
654    Binary |= (0x2 << 4) | (1 << 7);
655    break;
656  case ARM::MOVsra_flag:
657    // asr #1
658    Binary |= (0x4 << 4) | (1 << 7);
659    break;
660  }
661
662  // Encode register Rm.
663  Binary |= getMachineOpValue(MI, 1);
664
665  emitWordLE(Binary);
666}
667
668void ARMCodeEmitter::addPCLabel(unsigned LabelID) {
669  DEBUG(errs() << "  ** LPC" << LabelID << " @ "
670        << (void*)MCE.getCurrentPCValue() << '\n');
671  JTI->addPCLabelAddr(LabelID, MCE.getCurrentPCValue());
672}
673
674void ARMCodeEmitter::emitPseudoInstruction(const MachineInstr &MI) {
675  unsigned Opcode = MI.getDesc().Opcode;
676  switch (Opcode) {
677  default:
678    llvm_unreachable("ARMCodeEmitter::emitPseudoInstruction");
679  case ARM::BX:
680  case ARM::BMOVPCRX:
681  case ARM::BXr9:
682  case ARM::BMOVPCRXr9: {
683    // First emit mov lr, pc
684    unsigned Binary = 0x01a0e00f;
685    Binary |= II->getPredicate(&MI) << ARMII::CondShift;
686    emitWordLE(Binary);
687
688    // and then emit the branch.
689    emitMiscBranchInstruction(MI);
690    break;
691  }
692  case TargetOpcode::INLINEASM: {
693    // We allow inline assembler nodes with empty bodies - they can
694    // implicitly define registers, which is ok for JIT.
695    if (MI.getOperand(0).getSymbolName()[0]) {
696      report_fatal_error("JIT does not support inline asm!");
697    }
698    break;
699  }
700  case TargetOpcode::PROLOG_LABEL:
701  case TargetOpcode::EH_LABEL:
702    MCE.emitLabel(MI.getOperand(0).getMCSymbol());
703    break;
704  case TargetOpcode::IMPLICIT_DEF:
705  case TargetOpcode::KILL:
706    // Do nothing.
707    break;
708  case ARM::CONSTPOOL_ENTRY:
709    emitConstPoolInstruction(MI);
710    break;
711  case ARM::PICADD: {
712    // Remember of the address of the PC label for relocation later.
713    addPCLabel(MI.getOperand(2).getImm());
714    // PICADD is just an add instruction that implicitly read pc.
715    emitDataProcessingInstruction(MI, 0, ARM::PC);
716    break;
717  }
718  case ARM::PICLDR:
719  case ARM::PICLDRB:
720  case ARM::PICSTR:
721  case ARM::PICSTRB: {
722    // Remember of the address of the PC label for relocation later.
723    addPCLabel(MI.getOperand(2).getImm());
724    // These are just load / store instructions that implicitly read pc.
725    emitLoadStoreInstruction(MI, 0, ARM::PC);
726    break;
727  }
728  case ARM::PICLDRH:
729  case ARM::PICLDRSH:
730  case ARM::PICLDRSB:
731  case ARM::PICSTRH: {
732    // Remember of the address of the PC label for relocation later.
733    addPCLabel(MI.getOperand(2).getImm());
734    // These are just load / store instructions that implicitly read pc.
735    emitMiscLoadStoreInstruction(MI, ARM::PC);
736    break;
737  }
738
739  case ARM::MOVi32imm:
740    emitMOVi32immInstruction(MI);
741    break;
742
743  case ARM::MOVi2pieces:
744    // Two instructions to materialize a constant.
745    emitMOVi2piecesInstruction(MI);
746    break;
747  case ARM::LEApcrelJT:
748    // Materialize jumptable address.
749    emitLEApcrelJTInstruction(MI);
750    break;
751  case ARM::RRX:
752  case ARM::MOVsrl_flag:
753  case ARM::MOVsra_flag:
754    emitPseudoMoveInstruction(MI);
755    break;
756  }
757}
758
759unsigned ARMCodeEmitter::getMachineSoRegOpValue(const MachineInstr &MI,
760                                                const TargetInstrDesc &TID,
761                                                const MachineOperand &MO,
762                                                unsigned OpIdx) {
763  unsigned Binary = getMachineOpValue(MI, MO);
764
765  const MachineOperand &MO1 = MI.getOperand(OpIdx + 1);
766  const MachineOperand &MO2 = MI.getOperand(OpIdx + 2);
767  ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm());
768
769  // Encode the shift opcode.
770  unsigned SBits = 0;
771  unsigned Rs = MO1.getReg();
772  if (Rs) {
773    // Set shift operand (bit[7:4]).
774    // LSL - 0001
775    // LSR - 0011
776    // ASR - 0101
777    // ROR - 0111
778    // RRX - 0110 and bit[11:8] clear.
779    switch (SOpc) {
780    default: llvm_unreachable("Unknown shift opc!");
781    case ARM_AM::lsl: SBits = 0x1; break;
782    case ARM_AM::lsr: SBits = 0x3; break;
783    case ARM_AM::asr: SBits = 0x5; break;
784    case ARM_AM::ror: SBits = 0x7; break;
785    case ARM_AM::rrx: SBits = 0x6; break;
786    }
787  } else {
788    // Set shift operand (bit[6:4]).
789    // LSL - 000
790    // LSR - 010
791    // ASR - 100
792    // ROR - 110
793    switch (SOpc) {
794    default: llvm_unreachable("Unknown shift opc!");
795    case ARM_AM::lsl: SBits = 0x0; break;
796    case ARM_AM::lsr: SBits = 0x2; break;
797    case ARM_AM::asr: SBits = 0x4; break;
798    case ARM_AM::ror: SBits = 0x6; break;
799    }
800  }
801  Binary |= SBits << 4;
802  if (SOpc == ARM_AM::rrx)
803    return Binary;
804
805  // Encode the shift operation Rs or shift_imm (except rrx).
806  if (Rs) {
807    // Encode Rs bit[11:8].
808    assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0);
809    return Binary | (getARMRegisterNumbering(Rs) << ARMII::RegRsShift);
810  }
811
812  // Encode shift_imm bit[11:7].
813  return Binary | ARM_AM::getSORegOffset(MO2.getImm()) << 7;
814}
815
816unsigned ARMCodeEmitter::getMachineSoImmOpValue(unsigned SoImm) {
817  int SoImmVal = ARM_AM::getSOImmVal(SoImm);
818  assert(SoImmVal != -1 && "Not a valid so_imm value!");
819
820  // Encode rotate_imm.
821  unsigned Binary = (ARM_AM::getSOImmValRot((unsigned)SoImmVal) >> 1)
822    << ARMII::SoRotImmShift;
823
824  // Encode immed_8.
825  Binary |= ARM_AM::getSOImmValImm((unsigned)SoImmVal);
826  return Binary;
827}
828
829unsigned ARMCodeEmitter::getAddrModeSBit(const MachineInstr &MI,
830                                         const TargetInstrDesc &TID) const {
831  for (unsigned i = MI.getNumOperands(), e = TID.getNumOperands(); i != e; --i){
832    const MachineOperand &MO = MI.getOperand(i-1);
833    if (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR)
834      return 1 << ARMII::S_BitShift;
835  }
836  return 0;
837}
838
839void ARMCodeEmitter::emitDataProcessingInstruction(const MachineInstr &MI,
840                                                   unsigned ImplicitRd,
841                                                   unsigned ImplicitRn) {
842  const TargetInstrDesc &TID = MI.getDesc();
843
844  // Part of binary is determined by TableGn.
845  unsigned Binary = getBinaryCodeForInstr(MI);
846
847  // Set the conditional execution predicate
848  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
849
850  // Encode S bit if MI modifies CPSR.
851  Binary |= getAddrModeSBit(MI, TID);
852
853  // Encode register def if there is one.
854  unsigned NumDefs = TID.getNumDefs();
855  unsigned OpIdx = 0;
856  if (NumDefs)
857    Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
858  else if (ImplicitRd)
859    // Special handling for implicit use (e.g. PC).
860    Binary |= (getARMRegisterNumbering(ImplicitRd) << ARMII::RegRdShift);
861
862  if (TID.Opcode == ARM::MOVi16) {
863      // Get immediate from MI.
864      unsigned Lo16 = getMovi32Value(MI, MI.getOperand(OpIdx),
865                      ARM::reloc_arm_movw);
866      // Encode imm which is the same as in emitMOVi32immInstruction().
867      Binary |= Lo16 & 0xFFF;
868      Binary |= ((Lo16 >> 12) & 0xF) << 16;
869      emitWordLE(Binary);
870      return;
871  } else if(TID.Opcode == ARM::MOVTi16) {
872      unsigned Hi16 = (getMovi32Value(MI, MI.getOperand(OpIdx),
873                       ARM::reloc_arm_movt) >> 16);
874      Binary |= Hi16 & 0xFFF;
875      Binary |= ((Hi16 >> 12) & 0xF) << 16;
876      emitWordLE(Binary);
877      return;
878  } else if ((TID.Opcode == ARM::BFC) || (TID.Opcode == ARM::BFI)) {
879      uint32_t v = ~MI.getOperand(2).getImm();
880      int32_t lsb = CountTrailingZeros_32(v);
881      int32_t msb = (32 - CountLeadingZeros_32(v)) - 1;
882      // Instr{20-16} = msb, Instr{11-7} = lsb
883      Binary |= (msb & 0x1F) << 16;
884      Binary |= (lsb & 0x1F) << 7;
885      emitWordLE(Binary);
886      return;
887  } else if ((TID.Opcode == ARM::UBFX) || (TID.Opcode == ARM::SBFX)) {
888      // Encode Rn in Instr{0-3}
889      Binary |= getMachineOpValue(MI, OpIdx++);
890
891      uint32_t lsb = MI.getOperand(OpIdx++).getImm();
892      uint32_t widthm1 = MI.getOperand(OpIdx++).getImm() - 1;
893
894      // Instr{20-16} = widthm1, Instr{11-7} = lsb
895      Binary |= (widthm1 & 0x1F) << 16;
896      Binary |= (lsb & 0x1F) << 7;
897      emitWordLE(Binary);
898      return;
899  }
900
901  // If this is a two-address operand, skip it. e.g. MOVCCr operand 1.
902  if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
903    ++OpIdx;
904
905  // Encode first non-shifter register operand if there is one.
906  bool isUnary = TID.TSFlags & ARMII::UnaryDP;
907  if (!isUnary) {
908    if (ImplicitRn)
909      // Special handling for implicit use (e.g. PC).
910      Binary |= (getARMRegisterNumbering(ImplicitRn) << ARMII::RegRnShift);
911    else {
912      Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRnShift;
913      ++OpIdx;
914    }
915  }
916
917  // Encode shifter operand.
918  const MachineOperand &MO = MI.getOperand(OpIdx);
919  if ((TID.TSFlags & ARMII::FormMask) == ARMII::DPSoRegFrm) {
920    // Encode SoReg.
921    emitWordLE(Binary | getMachineSoRegOpValue(MI, TID, MO, OpIdx));
922    return;
923  }
924
925  if (MO.isReg()) {
926    // Encode register Rm.
927    emitWordLE(Binary | getARMRegisterNumbering(MO.getReg()));
928    return;
929  }
930
931  // Encode so_imm.
932  Binary |= getMachineSoImmOpValue((unsigned)MO.getImm());
933
934  emitWordLE(Binary);
935}
936
937void ARMCodeEmitter::emitLoadStoreInstruction(const MachineInstr &MI,
938                                              unsigned ImplicitRd,
939                                              unsigned ImplicitRn) {
940  const TargetInstrDesc &TID = MI.getDesc();
941  unsigned Form = TID.TSFlags & ARMII::FormMask;
942  bool IsPrePost = (TID.TSFlags & ARMII::IndexModeMask) != 0;
943
944  // Part of binary is determined by TableGn.
945  unsigned Binary = getBinaryCodeForInstr(MI);
946
947  // Set the conditional execution predicate
948  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
949
950  unsigned OpIdx = 0;
951
952  // Operand 0 of a pre- and post-indexed store is the address base
953  // writeback. Skip it.
954  bool Skipped = false;
955  if (IsPrePost && Form == ARMII::StFrm) {
956    ++OpIdx;
957    Skipped = true;
958  }
959
960  // Set first operand
961  if (ImplicitRd)
962    // Special handling for implicit use (e.g. PC).
963    Binary |= (getARMRegisterNumbering(ImplicitRd) << ARMII::RegRdShift);
964  else
965    Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
966
967  // Set second operand
968  if (ImplicitRn)
969    // Special handling for implicit use (e.g. PC).
970    Binary |= (getARMRegisterNumbering(ImplicitRn) << ARMII::RegRnShift);
971  else
972    Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
973
974  // If this is a two-address operand, skip it. e.g. LDR_PRE.
975  if (!Skipped && TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
976    ++OpIdx;
977
978  const MachineOperand &MO2 = MI.getOperand(OpIdx);
979  unsigned AM2Opc = (ImplicitRn == ARM::PC)
980    ? 0 : MI.getOperand(OpIdx+1).getImm();
981
982  // Set bit U(23) according to sign of immed value (positive or negative).
983  Binary |= ((ARM_AM::getAM2Op(AM2Opc) == ARM_AM::add ? 1 : 0) <<
984             ARMII::U_BitShift);
985  if (!MO2.getReg()) { // is immediate
986    if (ARM_AM::getAM2Offset(AM2Opc))
987      // Set the value of offset_12 field
988      Binary |= ARM_AM::getAM2Offset(AM2Opc);
989    emitWordLE(Binary);
990    return;
991  }
992
993  // Set bit I(25), because this is not in immediate encoding.
994  Binary |= 1 << ARMII::I_BitShift;
995  assert(TargetRegisterInfo::isPhysicalRegister(MO2.getReg()));
996  // Set bit[3:0] to the corresponding Rm register
997  Binary |= getARMRegisterNumbering(MO2.getReg());
998
999  // If this instr is in scaled register offset/index instruction, set
1000  // shift_immed(bit[11:7]) and shift(bit[6:5]) fields.
1001  if (unsigned ShImm = ARM_AM::getAM2Offset(AM2Opc)) {
1002    Binary |= getShiftOp(AM2Opc) << ARMII::ShiftImmShift;  // shift
1003    Binary |= ShImm              << ARMII::ShiftShift;     // shift_immed
1004  }
1005
1006  emitWordLE(Binary);
1007}
1008
1009void ARMCodeEmitter::emitMiscLoadStoreInstruction(const MachineInstr &MI,
1010                                                  unsigned ImplicitRn) {
1011  const TargetInstrDesc &TID = MI.getDesc();
1012  unsigned Form = TID.TSFlags & ARMII::FormMask;
1013  bool IsPrePost = (TID.TSFlags & ARMII::IndexModeMask) != 0;
1014
1015  // Part of binary is determined by TableGn.
1016  unsigned Binary = getBinaryCodeForInstr(MI);
1017
1018  // Set the conditional execution predicate
1019  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1020
1021  unsigned OpIdx = 0;
1022
1023  // Operand 0 of a pre- and post-indexed store is the address base
1024  // writeback. Skip it.
1025  bool Skipped = false;
1026  if (IsPrePost && Form == ARMII::StMiscFrm) {
1027    ++OpIdx;
1028    Skipped = true;
1029  }
1030
1031  // Set first operand
1032  Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1033
1034  // Skip LDRD and STRD's second operand.
1035  if (TID.Opcode == ARM::LDRD || TID.Opcode == ARM::STRD)
1036    ++OpIdx;
1037
1038  // Set second operand
1039  if (ImplicitRn)
1040    // Special handling for implicit use (e.g. PC).
1041    Binary |= (getARMRegisterNumbering(ImplicitRn) << ARMII::RegRnShift);
1042  else
1043    Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
1044
1045  // If this is a two-address operand, skip it. e.g. LDRH_POST.
1046  if (!Skipped && TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1047    ++OpIdx;
1048
1049  const MachineOperand &MO2 = MI.getOperand(OpIdx);
1050  unsigned AM3Opc = (ImplicitRn == ARM::PC)
1051    ? 0 : MI.getOperand(OpIdx+1).getImm();
1052
1053  // Set bit U(23) according to sign of immed value (positive or negative)
1054  Binary |= ((ARM_AM::getAM3Op(AM3Opc) == ARM_AM::add ? 1 : 0) <<
1055             ARMII::U_BitShift);
1056
1057  // If this instr is in register offset/index encoding, set bit[3:0]
1058  // to the corresponding Rm register.
1059  if (MO2.getReg()) {
1060    Binary |= getARMRegisterNumbering(MO2.getReg());
1061    emitWordLE(Binary);
1062    return;
1063  }
1064
1065  // This instr is in immediate offset/index encoding, set bit 22 to 1.
1066  Binary |= 1 << ARMII::AM3_I_BitShift;
1067  if (unsigned ImmOffs = ARM_AM::getAM3Offset(AM3Opc)) {
1068    // Set operands
1069    Binary |= (ImmOffs >> 4) << ARMII::ImmHiShift;  // immedH
1070    Binary |= (ImmOffs & 0xF);                      // immedL
1071  }
1072
1073  emitWordLE(Binary);
1074}
1075
1076static unsigned getAddrModeUPBits(unsigned Mode) {
1077  unsigned Binary = 0;
1078
1079  // Set addressing mode by modifying bits U(23) and P(24)
1080  // IA - Increment after  - bit U = 1 and bit P = 0
1081  // IB - Increment before - bit U = 1 and bit P = 1
1082  // DA - Decrement after  - bit U = 0 and bit P = 0
1083  // DB - Decrement before - bit U = 0 and bit P = 1
1084  switch (Mode) {
1085  default: llvm_unreachable("Unknown addressing sub-mode!");
1086  case ARM_AM::da:                                     break;
1087  case ARM_AM::db: Binary |= 0x1 << ARMII::P_BitShift; break;
1088  case ARM_AM::ia: Binary |= 0x1 << ARMII::U_BitShift; break;
1089  case ARM_AM::ib: Binary |= 0x3 << ARMII::U_BitShift; break;
1090  }
1091
1092  return Binary;
1093}
1094
1095void ARMCodeEmitter::emitLoadStoreMultipleInstruction(const MachineInstr &MI) {
1096  const TargetInstrDesc &TID = MI.getDesc();
1097  bool IsUpdating = (TID.TSFlags & ARMII::IndexModeMask) != 0;
1098
1099  // Part of binary is determined by TableGn.
1100  unsigned Binary = getBinaryCodeForInstr(MI);
1101
1102  // Set the conditional execution predicate
1103  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1104
1105  // Skip operand 0 of an instruction with base register update.
1106  unsigned OpIdx = 0;
1107  if (IsUpdating)
1108    ++OpIdx;
1109
1110  // Set base address operand
1111  Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
1112
1113  // Set addressing mode by modifying bits U(23) and P(24)
1114  const MachineOperand &MO = MI.getOperand(OpIdx++);
1115  Binary |= getAddrModeUPBits(ARM_AM::getAM4SubMode(MO.getImm()));
1116
1117  // Set bit W(21)
1118  if (IsUpdating)
1119    Binary |= 0x1 << ARMII::W_BitShift;
1120
1121  // Set registers
1122  for (unsigned i = OpIdx+2, e = MI.getNumOperands(); i != e; ++i) {
1123    const MachineOperand &MO = MI.getOperand(i);
1124    if (!MO.isReg() || MO.isImplicit())
1125      break;
1126    unsigned RegNum = getARMRegisterNumbering(MO.getReg());
1127    assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()) &&
1128           RegNum < 16);
1129    Binary |= 0x1 << RegNum;
1130  }
1131
1132  emitWordLE(Binary);
1133}
1134
1135void ARMCodeEmitter::emitMulFrmInstruction(const MachineInstr &MI) {
1136  const TargetInstrDesc &TID = MI.getDesc();
1137
1138  // Part of binary is determined by TableGn.
1139  unsigned Binary = getBinaryCodeForInstr(MI);
1140
1141  // Set the conditional execution predicate
1142  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1143
1144  // Encode S bit if MI modifies CPSR.
1145  Binary |= getAddrModeSBit(MI, TID);
1146
1147  // 32x32->64bit operations have two destination registers. The number
1148  // of register definitions will tell us if that's what we're dealing with.
1149  unsigned OpIdx = 0;
1150  if (TID.getNumDefs() == 2)
1151    Binary |= getMachineOpValue (MI, OpIdx++) << ARMII::RegRdLoShift;
1152
1153  // Encode Rd
1154  Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdHiShift;
1155
1156  // Encode Rm
1157  Binary |= getMachineOpValue(MI, OpIdx++);
1158
1159  // Encode Rs
1160  Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRsShift;
1161
1162  // Many multiple instructions (e.g. MLA) have three src operands. Encode
1163  // it as Rn (for multiply, that's in the same offset as RdLo.
1164  if (TID.getNumOperands() > OpIdx &&
1165      !TID.OpInfo[OpIdx].isPredicate() &&
1166      !TID.OpInfo[OpIdx].isOptionalDef())
1167    Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRdLoShift;
1168
1169  emitWordLE(Binary);
1170}
1171
1172void ARMCodeEmitter::emitExtendInstruction(const MachineInstr &MI) {
1173  const TargetInstrDesc &TID = MI.getDesc();
1174
1175  // Part of binary is determined by TableGn.
1176  unsigned Binary = getBinaryCodeForInstr(MI);
1177
1178  // Set the conditional execution predicate
1179  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1180
1181  unsigned OpIdx = 0;
1182
1183  // Encode Rd
1184  Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1185
1186  const MachineOperand &MO1 = MI.getOperand(OpIdx++);
1187  const MachineOperand &MO2 = MI.getOperand(OpIdx);
1188  if (MO2.isReg()) {
1189    // Two register operand form.
1190    // Encode Rn.
1191    Binary |= getMachineOpValue(MI, MO1) << ARMII::RegRnShift;
1192
1193    // Encode Rm.
1194    Binary |= getMachineOpValue(MI, MO2);
1195    ++OpIdx;
1196  } else {
1197    Binary |= getMachineOpValue(MI, MO1);
1198  }
1199
1200  // Encode rot imm (0, 8, 16, or 24) if it has a rotate immediate operand.
1201  if (MI.getOperand(OpIdx).isImm() &&
1202      !TID.OpInfo[OpIdx].isPredicate() &&
1203      !TID.OpInfo[OpIdx].isOptionalDef())
1204    Binary |= (getMachineOpValue(MI, OpIdx) / 8) << ARMII::ExtRotImmShift;
1205
1206  emitWordLE(Binary);
1207}
1208
1209void ARMCodeEmitter::emitMiscArithInstruction(const MachineInstr &MI) {
1210  const TargetInstrDesc &TID = MI.getDesc();
1211
1212  // Part of binary is determined by TableGn.
1213  unsigned Binary = getBinaryCodeForInstr(MI);
1214
1215  // Set the conditional execution predicate
1216  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1217
1218  unsigned OpIdx = 0;
1219
1220  // Encode Rd
1221  Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1222
1223  const MachineOperand &MO = MI.getOperand(OpIdx++);
1224  if (OpIdx == TID.getNumOperands() ||
1225      TID.OpInfo[OpIdx].isPredicate() ||
1226      TID.OpInfo[OpIdx].isOptionalDef()) {
1227    // Encode Rm and it's done.
1228    Binary |= getMachineOpValue(MI, MO);
1229    emitWordLE(Binary);
1230    return;
1231  }
1232
1233  // Encode Rn.
1234  Binary |= getMachineOpValue(MI, MO) << ARMII::RegRnShift;
1235
1236  // Encode Rm.
1237  Binary |= getMachineOpValue(MI, OpIdx++);
1238
1239  // Encode shift_imm.
1240  unsigned ShiftAmt = MI.getOperand(OpIdx).getImm();
1241  if (TID.Opcode == ARM::PKHTB) {
1242    assert(ShiftAmt != 0 && "PKHTB shift_imm is 0!");
1243    if (ShiftAmt == 32)
1244      ShiftAmt = 0;
1245  }
1246  assert(ShiftAmt < 32 && "shift_imm range is 0 to 31!");
1247  Binary |= ShiftAmt << ARMII::ShiftShift;
1248
1249  emitWordLE(Binary);
1250}
1251
1252void ARMCodeEmitter::emitSaturateInstruction(const MachineInstr &MI) {
1253  const TargetInstrDesc &TID = MI.getDesc();
1254
1255  // Part of binary is determined by TableGen.
1256  unsigned Binary = getBinaryCodeForInstr(MI);
1257
1258  // Set the conditional execution predicate
1259  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1260
1261  // Encode Rd
1262  Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
1263
1264  // Encode saturate bit position.
1265  unsigned Pos = MI.getOperand(1).getImm();
1266  if (TID.Opcode == ARM::SSAT || TID.Opcode == ARM::SSAT16)
1267    Pos -= 1;
1268  assert((Pos < 16 || (Pos < 32 &&
1269                       TID.Opcode != ARM::SSAT16 &&
1270                       TID.Opcode != ARM::USAT16)) &&
1271         "saturate bit position out of range");
1272  Binary |= Pos << 16;
1273
1274  // Encode Rm
1275  Binary |= getMachineOpValue(MI, 2);
1276
1277  // Encode shift_imm.
1278  if (TID.getNumOperands() == 4) {
1279    unsigned ShiftOp = MI.getOperand(3).getImm();
1280    ARM_AM::ShiftOpc Opc = ARM_AM::getSORegShOp(ShiftOp);
1281    if (Opc == ARM_AM::asr)
1282      Binary |= (1 << 6);
1283    unsigned ShiftAmt = MI.getOperand(3).getImm();
1284    if (ShiftAmt == 32 && Opc == ARM_AM::asr)
1285      ShiftAmt = 0;
1286    assert(ShiftAmt < 32 && "shift_imm range is 0 to 31!");
1287    Binary |= ShiftAmt << ARMII::ShiftShift;
1288  }
1289
1290  emitWordLE(Binary);
1291}
1292
1293void ARMCodeEmitter::emitBranchInstruction(const MachineInstr &MI) {
1294  const TargetInstrDesc &TID = MI.getDesc();
1295
1296  if (TID.Opcode == ARM::TPsoft) {
1297    llvm_unreachable("ARM::TPsoft FIXME"); // FIXME
1298  }
1299
1300  // Part of binary is determined by TableGn.
1301  unsigned Binary = getBinaryCodeForInstr(MI);
1302
1303  // Set the conditional execution predicate
1304  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1305
1306  // Set signed_immed_24 field
1307  Binary |= getMachineOpValue(MI, 0);
1308
1309  emitWordLE(Binary);
1310}
1311
1312void ARMCodeEmitter::emitInlineJumpTable(unsigned JTIndex) {
1313  // Remember the base address of the inline jump table.
1314  uintptr_t JTBase = MCE.getCurrentPCValue();
1315  JTI->addJumpTableBaseAddr(JTIndex, JTBase);
1316  DEBUG(errs() << "  ** Jump Table #" << JTIndex << " @ " << (void*)JTBase
1317               << '\n');
1318
1319  // Now emit the jump table entries.
1320  const std::vector<MachineBasicBlock*> &MBBs = (*MJTEs)[JTIndex].MBBs;
1321  for (unsigned i = 0, e = MBBs.size(); i != e; ++i) {
1322    if (IsPIC)
1323      // DestBB address - JT base.
1324      emitMachineBasicBlock(MBBs[i], ARM::reloc_arm_pic_jt, JTBase);
1325    else
1326      // Absolute DestBB address.
1327      emitMachineBasicBlock(MBBs[i], ARM::reloc_arm_absolute);
1328    emitWordLE(0);
1329  }
1330}
1331
1332void ARMCodeEmitter::emitMiscBranchInstruction(const MachineInstr &MI) {
1333  const TargetInstrDesc &TID = MI.getDesc();
1334
1335  // Handle jump tables.
1336  if (TID.Opcode == ARM::BR_JTr || TID.Opcode == ARM::BR_JTadd) {
1337    // First emit a ldr pc, [] instruction.
1338    emitDataProcessingInstruction(MI, ARM::PC);
1339
1340    // Then emit the inline jump table.
1341    unsigned JTIndex =
1342      (TID.Opcode == ARM::BR_JTr)
1343      ? MI.getOperand(1).getIndex() : MI.getOperand(2).getIndex();
1344    emitInlineJumpTable(JTIndex);
1345    return;
1346  } else if (TID.Opcode == ARM::BR_JTm) {
1347    // First emit a ldr pc, [] instruction.
1348    emitLoadStoreInstruction(MI, ARM::PC);
1349
1350    // Then emit the inline jump table.
1351    emitInlineJumpTable(MI.getOperand(3).getIndex());
1352    return;
1353  }
1354
1355  // Part of binary is determined by TableGn.
1356  unsigned Binary = getBinaryCodeForInstr(MI);
1357
1358  // Set the conditional execution predicate
1359  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1360
1361  if (TID.Opcode == ARM::BX_RET || TID.Opcode == ARM::MOVPCLR)
1362    // The return register is LR.
1363    Binary |= getARMRegisterNumbering(ARM::LR);
1364  else
1365    // otherwise, set the return register
1366    Binary |= getMachineOpValue(MI, 0);
1367
1368  emitWordLE(Binary);
1369}
1370
1371static unsigned encodeVFPRd(const MachineInstr &MI, unsigned OpIdx) {
1372  unsigned RegD = MI.getOperand(OpIdx).getReg();
1373  unsigned Binary = 0;
1374  bool isSPVFP = ARM::SPRRegisterClass->contains(RegD);
1375  RegD = getARMRegisterNumbering(RegD);
1376  if (!isSPVFP)
1377    Binary |=   RegD               << ARMII::RegRdShift;
1378  else {
1379    Binary |= ((RegD & 0x1E) >> 1) << ARMII::RegRdShift;
1380    Binary |=  (RegD & 0x01)       << ARMII::D_BitShift;
1381  }
1382  return Binary;
1383}
1384
1385static unsigned encodeVFPRn(const MachineInstr &MI, unsigned OpIdx) {
1386  unsigned RegN = MI.getOperand(OpIdx).getReg();
1387  unsigned Binary = 0;
1388  bool isSPVFP = ARM::SPRRegisterClass->contains(RegN);
1389  RegN = getARMRegisterNumbering(RegN);
1390  if (!isSPVFP)
1391    Binary |=   RegN               << ARMII::RegRnShift;
1392  else {
1393    Binary |= ((RegN & 0x1E) >> 1) << ARMII::RegRnShift;
1394    Binary |=  (RegN & 0x01)       << ARMII::N_BitShift;
1395  }
1396  return Binary;
1397}
1398
1399static unsigned encodeVFPRm(const MachineInstr &MI, unsigned OpIdx) {
1400  unsigned RegM = MI.getOperand(OpIdx).getReg();
1401  unsigned Binary = 0;
1402  bool isSPVFP = ARM::SPRRegisterClass->contains(RegM);
1403  RegM = getARMRegisterNumbering(RegM);
1404  if (!isSPVFP)
1405    Binary |=   RegM;
1406  else {
1407    Binary |= ((RegM & 0x1E) >> 1);
1408    Binary |=  (RegM & 0x01)       << ARMII::M_BitShift;
1409  }
1410  return Binary;
1411}
1412
1413void ARMCodeEmitter::emitVFPArithInstruction(const MachineInstr &MI) {
1414  const TargetInstrDesc &TID = MI.getDesc();
1415
1416  // Part of binary is determined by TableGn.
1417  unsigned Binary = getBinaryCodeForInstr(MI);
1418
1419  // Set the conditional execution predicate
1420  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1421
1422  unsigned OpIdx = 0;
1423  assert((Binary & ARMII::D_BitShift) == 0 &&
1424         (Binary & ARMII::N_BitShift) == 0 &&
1425         (Binary & ARMII::M_BitShift) == 0 && "VFP encoding bug!");
1426
1427  // Encode Dd / Sd.
1428  Binary |= encodeVFPRd(MI, OpIdx++);
1429
1430  // If this is a two-address operand, skip it, e.g. FMACD.
1431  if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1432    ++OpIdx;
1433
1434  // Encode Dn / Sn.
1435  if ((TID.TSFlags & ARMII::FormMask) == ARMII::VFPBinaryFrm)
1436    Binary |= encodeVFPRn(MI, OpIdx++);
1437
1438  if (OpIdx == TID.getNumOperands() ||
1439      TID.OpInfo[OpIdx].isPredicate() ||
1440      TID.OpInfo[OpIdx].isOptionalDef()) {
1441    // FCMPEZD etc. has only one operand.
1442    emitWordLE(Binary);
1443    return;
1444  }
1445
1446  // Encode Dm / Sm.
1447  Binary |= encodeVFPRm(MI, OpIdx);
1448
1449  emitWordLE(Binary);
1450}
1451
1452void ARMCodeEmitter::emitVFPConversionInstruction(const MachineInstr &MI) {
1453  const TargetInstrDesc &TID = MI.getDesc();
1454  unsigned Form = TID.TSFlags & ARMII::FormMask;
1455
1456  // Part of binary is determined by TableGn.
1457  unsigned Binary = getBinaryCodeForInstr(MI);
1458
1459  // Set the conditional execution predicate
1460  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1461
1462  switch (Form) {
1463  default: break;
1464  case ARMII::VFPConv1Frm:
1465  case ARMII::VFPConv2Frm:
1466  case ARMII::VFPConv3Frm:
1467    // Encode Dd / Sd.
1468    Binary |= encodeVFPRd(MI, 0);
1469    break;
1470  case ARMII::VFPConv4Frm:
1471    // Encode Dn / Sn.
1472    Binary |= encodeVFPRn(MI, 0);
1473    break;
1474  case ARMII::VFPConv5Frm:
1475    // Encode Dm / Sm.
1476    Binary |= encodeVFPRm(MI, 0);
1477    break;
1478  }
1479
1480  switch (Form) {
1481  default: break;
1482  case ARMII::VFPConv1Frm:
1483    // Encode Dm / Sm.
1484    Binary |= encodeVFPRm(MI, 1);
1485    break;
1486  case ARMII::VFPConv2Frm:
1487  case ARMII::VFPConv3Frm:
1488    // Encode Dn / Sn.
1489    Binary |= encodeVFPRn(MI, 1);
1490    break;
1491  case ARMII::VFPConv4Frm:
1492  case ARMII::VFPConv5Frm:
1493    // Encode Dd / Sd.
1494    Binary |= encodeVFPRd(MI, 1);
1495    break;
1496  }
1497
1498  if (Form == ARMII::VFPConv5Frm)
1499    // Encode Dn / Sn.
1500    Binary |= encodeVFPRn(MI, 2);
1501  else if (Form == ARMII::VFPConv3Frm)
1502    // Encode Dm / Sm.
1503    Binary |= encodeVFPRm(MI, 2);
1504
1505  emitWordLE(Binary);
1506}
1507
1508void ARMCodeEmitter::emitVFPLoadStoreInstruction(const MachineInstr &MI) {
1509  // Part of binary is determined by TableGn.
1510  unsigned Binary = getBinaryCodeForInstr(MI);
1511
1512  // Set the conditional execution predicate
1513  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1514
1515  unsigned OpIdx = 0;
1516
1517  // Encode Dd / Sd.
1518  Binary |= encodeVFPRd(MI, OpIdx++);
1519
1520  // Encode address base.
1521  const MachineOperand &Base = MI.getOperand(OpIdx++);
1522  Binary |= getMachineOpValue(MI, Base) << ARMII::RegRnShift;
1523
1524  // If there is a non-zero immediate offset, encode it.
1525  if (Base.isReg()) {
1526    const MachineOperand &Offset = MI.getOperand(OpIdx);
1527    if (unsigned ImmOffs = ARM_AM::getAM5Offset(Offset.getImm())) {
1528      if (ARM_AM::getAM5Op(Offset.getImm()) == ARM_AM::add)
1529        Binary |= 1 << ARMII::U_BitShift;
1530      Binary |= ImmOffs;
1531      emitWordLE(Binary);
1532      return;
1533    }
1534  }
1535
1536  // If immediate offset is omitted, default to +0.
1537  Binary |= 1 << ARMII::U_BitShift;
1538
1539  emitWordLE(Binary);
1540}
1541
1542void
1543ARMCodeEmitter::emitVFPLoadStoreMultipleInstruction(const MachineInstr &MI) {
1544  const TargetInstrDesc &TID = MI.getDesc();
1545  bool IsUpdating = (TID.TSFlags & ARMII::IndexModeMask) != 0;
1546
1547  // Part of binary is determined by TableGn.
1548  unsigned Binary = getBinaryCodeForInstr(MI);
1549
1550  // Set the conditional execution predicate
1551  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1552
1553  // Skip operand 0 of an instruction with base register update.
1554  unsigned OpIdx = 0;
1555  if (IsUpdating)
1556    ++OpIdx;
1557
1558  // Set base address operand
1559  Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
1560
1561  // Set addressing mode by modifying bits U(23) and P(24)
1562  const MachineOperand &MO = MI.getOperand(OpIdx++);
1563  Binary |= getAddrModeUPBits(ARM_AM::getAM4SubMode(MO.getImm()));
1564
1565  // Set bit W(21)
1566  if (IsUpdating)
1567    Binary |= 0x1 << ARMII::W_BitShift;
1568
1569  // First register is encoded in Dd.
1570  Binary |= encodeVFPRd(MI, OpIdx+2);
1571
1572  // Count the number of registers.
1573  unsigned NumRegs = 1;
1574  for (unsigned i = OpIdx+3, e = MI.getNumOperands(); i != e; ++i) {
1575    const MachineOperand &MO = MI.getOperand(i);
1576    if (!MO.isReg() || MO.isImplicit())
1577      break;
1578    ++NumRegs;
1579  }
1580  // Bit 8 will be set if <list> is consecutive 64-bit registers (e.g., D0)
1581  // Otherwise, it will be 0, in the case of 32-bit registers.
1582  if(Binary & 0x100)
1583    Binary |= NumRegs * 2;
1584  else
1585    Binary |= NumRegs;
1586
1587  emitWordLE(Binary);
1588}
1589
1590static unsigned encodeNEONRd(const MachineInstr &MI, unsigned OpIdx) {
1591  unsigned RegD = MI.getOperand(OpIdx).getReg();
1592  unsigned Binary = 0;
1593  RegD = getARMRegisterNumbering(RegD);
1594  Binary |= (RegD & 0xf) << ARMII::RegRdShift;
1595  Binary |= ((RegD >> 4) & 1) << ARMII::D_BitShift;
1596  return Binary;
1597}
1598
1599static unsigned encodeNEONRn(const MachineInstr &MI, unsigned OpIdx) {
1600  unsigned RegN = MI.getOperand(OpIdx).getReg();
1601  unsigned Binary = 0;
1602  RegN = getARMRegisterNumbering(RegN);
1603  Binary |= (RegN & 0xf) << ARMII::RegRnShift;
1604  Binary |= ((RegN >> 4) & 1) << ARMII::N_BitShift;
1605  return Binary;
1606}
1607
1608static unsigned encodeNEONRm(const MachineInstr &MI, unsigned OpIdx) {
1609  unsigned RegM = MI.getOperand(OpIdx).getReg();
1610  unsigned Binary = 0;
1611  RegM = getARMRegisterNumbering(RegM);
1612  Binary |= (RegM & 0xf);
1613  Binary |= ((RegM >> 4) & 1) << ARMII::M_BitShift;
1614  return Binary;
1615}
1616
1617/// convertNEONDataProcToThumb - Convert the ARM mode encoding for a NEON
1618/// data-processing instruction to the corresponding Thumb encoding.
1619static unsigned convertNEONDataProcToThumb(unsigned Binary) {
1620  assert((Binary & 0xfe000000) == 0xf2000000 &&
1621         "not an ARM NEON data-processing instruction");
1622  unsigned UBit = (Binary >> 24) & 1;
1623  return 0xef000000 | (UBit << 28) | (Binary & 0xffffff);
1624}
1625
1626void ARMCodeEmitter::emitNEONLaneInstruction(const MachineInstr &MI) {
1627  unsigned Binary = getBinaryCodeForInstr(MI);
1628
1629  unsigned RegTOpIdx, RegNOpIdx, LnOpIdx;
1630  const TargetInstrDesc &TID = MI.getDesc();
1631  if ((TID.TSFlags & ARMII::FormMask) == ARMII::NGetLnFrm) {
1632    RegTOpIdx = 0;
1633    RegNOpIdx = 1;
1634    LnOpIdx = 2;
1635  } else { // ARMII::NSetLnFrm
1636    RegTOpIdx = 2;
1637    RegNOpIdx = 0;
1638    LnOpIdx = 3;
1639  }
1640
1641  // Set the conditional execution predicate
1642  Binary |= (IsThumb ? ARMCC::AL : II->getPredicate(&MI)) << ARMII::CondShift;
1643
1644  unsigned RegT = MI.getOperand(RegTOpIdx).getReg();
1645  RegT = getARMRegisterNumbering(RegT);
1646  Binary |= (RegT << ARMII::RegRdShift);
1647  Binary |= encodeNEONRn(MI, RegNOpIdx);
1648
1649  unsigned LaneShift;
1650  if ((Binary & (1 << 22)) != 0)
1651    LaneShift = 0; // 8-bit elements
1652  else if ((Binary & (1 << 5)) != 0)
1653    LaneShift = 1; // 16-bit elements
1654  else
1655    LaneShift = 2; // 32-bit elements
1656
1657  unsigned Lane = MI.getOperand(LnOpIdx).getImm() << LaneShift;
1658  unsigned Opc1 = Lane >> 2;
1659  unsigned Opc2 = Lane & 3;
1660  assert((Opc1 & 3) == 0 && "out-of-range lane number operand");
1661  Binary |= (Opc1 << 21);
1662  Binary |= (Opc2 << 5);
1663
1664  emitWordLE(Binary);
1665}
1666
1667void ARMCodeEmitter::emitNEONDupInstruction(const MachineInstr &MI) {
1668  unsigned Binary = getBinaryCodeForInstr(MI);
1669
1670  // Set the conditional execution predicate
1671  Binary |= (IsThumb ? ARMCC::AL : II->getPredicate(&MI)) << ARMII::CondShift;
1672
1673  unsigned RegT = MI.getOperand(1).getReg();
1674  RegT = getARMRegisterNumbering(RegT);
1675  Binary |= (RegT << ARMII::RegRdShift);
1676  Binary |= encodeNEONRn(MI, 0);
1677  emitWordLE(Binary);
1678}
1679
1680void ARMCodeEmitter::emitNEON1RegModImmInstruction(const MachineInstr &MI) {
1681  unsigned Binary = getBinaryCodeForInstr(MI);
1682  // Destination register is encoded in Dd.
1683  Binary |= encodeNEONRd(MI, 0);
1684  // Immediate fields: Op, Cmode, I, Imm3, Imm4
1685  unsigned Imm = MI.getOperand(1).getImm();
1686  unsigned Op = (Imm >> 12) & 1;
1687  unsigned Cmode = (Imm >> 8) & 0xf;
1688  unsigned I = (Imm >> 7) & 1;
1689  unsigned Imm3 = (Imm >> 4) & 0x7;
1690  unsigned Imm4 = Imm & 0xf;
1691  Binary |= (I << 24) | (Imm3 << 16) | (Cmode << 8) | (Op << 5) | Imm4;
1692  if (IsThumb)
1693    Binary = convertNEONDataProcToThumb(Binary);
1694  emitWordLE(Binary);
1695}
1696
1697void ARMCodeEmitter::emitNEON2RegInstruction(const MachineInstr &MI) {
1698  const TargetInstrDesc &TID = MI.getDesc();
1699  unsigned Binary = getBinaryCodeForInstr(MI);
1700  // Destination register is encoded in Dd; source register in Dm.
1701  unsigned OpIdx = 0;
1702  Binary |= encodeNEONRd(MI, OpIdx++);
1703  if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1704    ++OpIdx;
1705  Binary |= encodeNEONRm(MI, OpIdx);
1706  if (IsThumb)
1707    Binary = convertNEONDataProcToThumb(Binary);
1708  // FIXME: This does not handle VDUPfdf or VDUPfqf.
1709  emitWordLE(Binary);
1710}
1711
1712void ARMCodeEmitter::emitNEON3RegInstruction(const MachineInstr &MI) {
1713  const TargetInstrDesc &TID = MI.getDesc();
1714  unsigned Binary = getBinaryCodeForInstr(MI);
1715  // Destination register is encoded in Dd; source registers in Dn and Dm.
1716  unsigned OpIdx = 0;
1717  Binary |= encodeNEONRd(MI, OpIdx++);
1718  if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1719    ++OpIdx;
1720  Binary |= encodeNEONRn(MI, OpIdx++);
1721  if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1722    ++OpIdx;
1723  Binary |= encodeNEONRm(MI, OpIdx);
1724  if (IsThumb)
1725    Binary = convertNEONDataProcToThumb(Binary);
1726  // FIXME: This does not handle VMOVDneon or VMOVQ.
1727  emitWordLE(Binary);
1728}
1729
1730#include "ARMGenCodeEmitter.inc"
1731