ARMCodeEmitter.cpp revision 453bbc3a0040eb095c89c4e5c055d7333eb865f3 
1//===-- ARM/ARMCodeEmitter.cpp - Convert ARM code to machine code ---------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the pass that transforms the ARM machine instructions into
11// relocatable machine code.
12//
13//===----------------------------------------------------------------------===//
14
15#define DEBUG_TYPE "arm-emitter"
16#include "ARM.h"
17#include "ARMAddressingModes.h"
18#include "ARMInstrInfo.h"
19#include "ARMRelocations.h"
20#include "ARMSubtarget.h"
21#include "ARMTargetMachine.h"
22#include "llvm/Function.h"
23#include "llvm/PassManager.h"
24#include "llvm/CodeGen/MachineCodeEmitter.h"
25#include "llvm/CodeGen/MachineFunctionPass.h"
26#include "llvm/CodeGen/MachineInstr.h"
27#include "llvm/CodeGen/Passes.h"
28#include "llvm/ADT/Statistic.h"
29#include "llvm/Support/Compiler.h"
30#include "llvm/Support/Debug.h"
31using namespace llvm;
32
33STATISTIC(NumEmitted, "Number of machine instructions emitted");
34
35namespace {
36  class VISIBILITY_HIDDEN ARMCodeEmitter : public MachineFunctionPass {
37    const ARMInstrInfo  *II;
38    const TargetData    *TD;
39    TargetMachine       &TM;
40    MachineCodeEmitter  &MCE;
41  public:
42    static char ID;
43    explicit ARMCodeEmitter(TargetMachine &tm, MachineCodeEmitter &mce)
44      : MachineFunctionPass(&ID), II(0), TD(0), TM(tm),
45      MCE(mce) {}
46    ARMCodeEmitter(TargetMachine &tm, MachineCodeEmitter &mce,
47            const ARMInstrInfo &ii, const TargetData &td)
48      : MachineFunctionPass(&ID), II(&ii), TD(&td), TM(tm),
49      MCE(mce) {}
50
51    bool runOnMachineFunction(MachineFunction &MF);
52
53    virtual const char *getPassName() const {
54      return "ARM Machine Code Emitter";
55    }
56
57    void emitInstruction(const MachineInstr &MI);
58
59  private:
60    unsigned getAddrModeNoneInstrBinary(const MachineInstr &MI,
61                                        const TargetInstrDesc &TID,
62                                        unsigned Binary);
63
64    unsigned getMachineSoRegOpValue(const MachineInstr &MI,
65                                    const TargetInstrDesc &TID,
66                                    unsigned OpIdx);
67
68    unsigned getAddrMode1SBit(const MachineInstr &MI,
69                              const TargetInstrDesc &TID) const;
70
71    unsigned getAddrMode1InstrBinary(const MachineInstr &MI,
72                                     const TargetInstrDesc &TID,
73                                     unsigned Binary);
74    unsigned getAddrMode2InstrBinary(const MachineInstr &MI,
75                                     const TargetInstrDesc &TID,
76                                     unsigned Binary);
77    unsigned getAddrMode3InstrBinary(const MachineInstr &MI,
78                                     const TargetInstrDesc &TID,
79                                     unsigned Binary);
80    unsigned getAddrMode4InstrBinary(const MachineInstr &MI,
81                                     const TargetInstrDesc &TID,
82                                     unsigned Binary);
83
84    /// getInstrBinary - Return binary encoding for the specified
85    /// machine instruction.
86    unsigned getInstrBinary(const MachineInstr &MI);
87
88    /// getBinaryCodeForInstr - This function, generated by the
89    /// CodeEmitterGenerator using TableGen, produces the binary encoding for
90    /// machine instructions.
91    ///
92    unsigned getBinaryCodeForInstr(const MachineInstr &MI);
93
94    /// getMachineOpValue - Return binary encoding of operand. If the machine
95    /// operand requires relocation, record the relocation and return zero.
96    unsigned getMachineOpValue(const MachineInstr &MI, unsigned OpIdx) {
97      return getMachineOpValue(MI, MI.getOperand(OpIdx));
98    }
99    unsigned getMachineOpValue(const MachineInstr &MI,
100                               const MachineOperand &MO);
101
102    /// getBaseOpcodeFor - Return the opcode value.
103    ///
104    unsigned getBaseOpcodeFor(const TargetInstrDesc &TID) const {
105      return (TID.TSFlags & ARMII::OpcodeMask) >> ARMII::OpcodeShift;
106    }
107
108    /// getShiftOp - Return the shift opcode (bit[6:5]) of the machine operand.
109    ///
110    unsigned getShiftOp(const MachineOperand &MO) const ;
111
112    /// Routines that handle operands which add machine relocations which are
113    /// fixed up by the JIT fixup stage.
114    void emitGlobalAddressForCall(GlobalValue *GV, bool DoesntNeedStub);
115    void emitExternalSymbolAddress(const char *ES, unsigned Reloc);
116    void emitConstPoolAddress(unsigned CPI, unsigned Reloc,
117                              int Disp = 0, unsigned PCAdj = 0 );
118    void emitJumpTableAddress(unsigned JTI, unsigned Reloc,
119                              unsigned PCAdj = 0);
120    void emitGlobalConstant(const Constant *CV);
121    void emitMachineBasicBlock(MachineBasicBlock *BB);
122  };
123  char ARMCodeEmitter::ID = 0;
124}
125
126/// createARMCodeEmitterPass - Return a pass that emits the collected ARM code
127/// to the specified MCE object.
128FunctionPass *llvm::createARMCodeEmitterPass(ARMTargetMachine &TM,
129                                             MachineCodeEmitter &MCE) {
130  return new ARMCodeEmitter(TM, MCE);
131}
132
133bool ARMCodeEmitter::runOnMachineFunction(MachineFunction &MF) {
134  assert((MF.getTarget().getRelocationModel() != Reloc::Default ||
135          MF.getTarget().getRelocationModel() != Reloc::Static) &&
136         "JIT relocation model must be set to static or default!");
137  II = ((ARMTargetMachine&)MF.getTarget()).getInstrInfo();
138  TD = ((ARMTargetMachine&)MF.getTarget()).getTargetData();
139
140  do {
141    DOUT << "JITTing function '" << MF.getFunction()->getName() << "'\n";
142    MCE.startFunction(MF);
143    for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();
144         MBB != E; ++MBB) {
145      MCE.StartMachineBasicBlock(MBB);
146      for (MachineBasicBlock::const_iterator I = MBB->begin(), E = MBB->end();
147           I != E; ++I)
148        emitInstruction(*I);
149    }
150  } while (MCE.finishFunction(MF));
151
152  return false;
153}
154
155/// getShiftOp - Return the shift opcode (bit[6:5]) of the machine operand.
156///
157unsigned ARMCodeEmitter::getShiftOp(const MachineOperand &MO) const {
158  switch (ARM_AM::getAM2ShiftOpc(MO.getImm())) {
159  default: assert(0 && "Unknown shift opc!");
160  case ARM_AM::asr: return 2;
161  case ARM_AM::lsl: return 0;
162  case ARM_AM::lsr: return 1;
163  case ARM_AM::ror:
164  case ARM_AM::rrx: return 3;
165  }
166  return 0;
167}
168
169/// getMachineOpValue - Return binary encoding of operand. If the machine
170/// operand requires relocation, record the relocation and return zero.
171unsigned ARMCodeEmitter::getMachineOpValue(const MachineInstr &MI,
172                                           const MachineOperand &MO) {
173  if (MO.isRegister())
174    return ARMRegisterInfo::getRegisterNumbering(MO.getReg());
175  else if (MO.isImmediate())
176    return static_cast<unsigned>(MO.getImm());
177  else if (MO.isGlobalAddress())
178    emitGlobalAddressForCall(MO.getGlobal(), false);
179  else if (MO.isExternalSymbol())
180    emitExternalSymbolAddress(MO.getSymbolName(), ARM::reloc_arm_relative);
181  else if (MO.isConstantPoolIndex())
182    emitConstPoolAddress(MO.getIndex(), ARM::reloc_arm_relative);
183  else if (MO.isJumpTableIndex())
184    emitJumpTableAddress(MO.getIndex(), ARM::reloc_arm_relative);
185  else if (MO.isMachineBasicBlock())
186    emitMachineBasicBlock(MO.getMBB());
187  else {
188    cerr << "ERROR: Unknown type of MachineOperand: " << MO << "\n";
189    abort();
190  }
191  return 0;
192}
193
194/// emitGlobalAddressForCall - Emit the specified address to the code stream
195/// assuming this is part of a function call, which is PC relative.
196///
197void ARMCodeEmitter::emitGlobalAddressForCall(GlobalValue *GV,
198                                              bool DoesntNeedStub) {
199  MCE.addRelocation(MachineRelocation::getGV(MCE.getCurrentPCOffset(),
200                                             ARM::reloc_arm_branch, GV, 0,
201                                             DoesntNeedStub));
202}
203
204/// emitExternalSymbolAddress - Arrange for the address of an external symbol to
205/// be emitted to the current location in the function, and allow it to be PC
206/// relative.
207void ARMCodeEmitter::emitExternalSymbolAddress(const char *ES, unsigned Reloc) {
208  MCE.addRelocation(MachineRelocation::getExtSym(MCE.getCurrentPCOffset(),
209                                                 Reloc, ES));
210}
211
212/// emitConstPoolAddress - Arrange for the address of an constant pool
213/// to be emitted to the current location in the function, and allow it to be PC
214/// relative.
215void ARMCodeEmitter::emitConstPoolAddress(unsigned CPI, unsigned Reloc,
216                                          int Disp /* = 0 */,
217                                          unsigned PCAdj /* = 0 */) {
218  MCE.addRelocation(MachineRelocation::getConstPool(MCE.getCurrentPCOffset(),
219                                                    Reloc, CPI, PCAdj));
220}
221
222/// emitJumpTableAddress - Arrange for the address of a jump table to
223/// be emitted to the current location in the function, and allow it to be PC
224/// relative.
225void ARMCodeEmitter::emitJumpTableAddress(unsigned JTI, unsigned Reloc,
226                                          unsigned PCAdj /* = 0 */) {
227  MCE.addRelocation(MachineRelocation::getJumpTable(MCE.getCurrentPCOffset(),
228                                                    Reloc, JTI, PCAdj));
229}
230
231/// emitMachineBasicBlock - Emit the specified address basic block.
232void ARMCodeEmitter::emitMachineBasicBlock(MachineBasicBlock *BB) {
233  MCE.addRelocation(MachineRelocation::getBB(MCE.getCurrentPCOffset(),
234                                             ARM::reloc_arm_branch, BB));
235}
236
237void ARMCodeEmitter::emitInstruction(const MachineInstr &MI) {
238  DOUT << MI;
239
240  NumEmitted++;  // Keep track of the # of mi's emitted
241  MCE.emitWordLE(getInstrBinary(MI));
242}
243
244unsigned ARMCodeEmitter::getAddrModeNoneInstrBinary(const MachineInstr &MI,
245                                                    const TargetInstrDesc &TID,
246                                                    unsigned Binary) {
247  switch (TID.TSFlags & ARMII::FormMask) {
248  default:
249    assert(0 && "Unknown instruction subtype!");
250    break;
251  case ARMII::Branch: {
252    // Set signed_immed_24 field
253    Binary |= getMachineOpValue(MI, 0);
254
255    // if it is a conditional branch, set cond field
256    if (TID.Opcode == ARM::Bcc) {
257      Binary &= 0x0FFFFFFF;                      // clear conditional field
258      Binary |= getMachineOpValue(MI, 1) << 28;  // set conditional field
259    }
260    break;
261  }
262  case ARMII::BranchMisc: {
263    // Set bit[19:8] to 0xFFF
264    Binary |= 0xfff << 8;
265    if (TID.Opcode == ARM::BX_RET)
266      Binary |= 0xe; // the return register is LR
267    else
268      // otherwise, set the return register
269      Binary |= getMachineOpValue(MI, 0);
270    break;
271  }
272  }
273
274  return Binary;
275}
276
277unsigned ARMCodeEmitter::getMachineSoRegOpValue(const MachineInstr &MI,
278                                                const TargetInstrDesc &TID,
279                                                unsigned OpIdx) {
280  // Set last operand (register Rm)
281  unsigned Binary = getMachineOpValue(MI, OpIdx);
282
283  const MachineOperand &MO1 = MI.getOperand(OpIdx + 1);
284  const MachineOperand &MO2 = MI.getOperand(OpIdx + 2);
285  ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm());
286
287  // Encode the shift opcode.
288  unsigned SBits = 0;
289  unsigned Rs = MO1.getReg();
290  if (Rs) {
291    // Set shift operand (bit[7:4]).
292    // LSL - 0001
293    // LSR - 0011
294    // ASR - 0101
295    // ROR - 0111
296    // RRX - 0110 and bit[11:8] clear.
297    switch (SOpc) {
298    default: assert(0 && "Unknown shift opc!");
299    case ARM_AM::lsl: SBits = 0x1; break;
300    case ARM_AM::lsr: SBits = 0x3; break;
301    case ARM_AM::asr: SBits = 0x5; break;
302    case ARM_AM::ror: SBits = 0x7; break;
303    case ARM_AM::rrx: SBits = 0x6; break;
304    }
305  } else {
306    // Set shift operand (bit[6:4]).
307    // LSL - 000
308    // LSR - 010
309    // ASR - 100
310    // ROR - 110
311    switch (SOpc) {
312    default: assert(0 && "Unknown shift opc!");
313    case ARM_AM::lsl: SBits = 0x0; break;
314    case ARM_AM::lsr: SBits = 0x2; break;
315    case ARM_AM::asr: SBits = 0x4; break;
316    case ARM_AM::ror: SBits = 0x6; break;
317    }
318  }
319  Binary |= SBits << 4;
320  if (SOpc == ARM_AM::rrx)
321    return Binary;
322
323  // Encode the shift operation Rs or shift_imm (except rrx).
324  if (Rs) {
325    // Encode Rs bit[11:8].
326    assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0);
327    return Binary |
328      (ARMRegisterInfo::getRegisterNumbering(Rs) << ARMII::RegRsShift);
329  }
330
331  // Encode shift_imm bit[11:7].
332  return Binary | ARM_AM::getSORegOffset(MO2.getImm()) << 7;
333}
334
335unsigned ARMCodeEmitter::getAddrMode1SBit(const MachineInstr &MI,
336                                          const TargetInstrDesc &TID) const {
337  for (unsigned i = MI.getNumOperands(), e = TID.getNumOperands(); i != e; --i){
338    const MachineOperand &MO = MI.getOperand(i-1);
339    if (MO.isRegister() && MO.isDef() && MO.getReg() == ARM::CPSR)
340      return 1 << ARMII::S_BitShift;
341  }
342  return 0;
343}
344
345unsigned ARMCodeEmitter::getAddrMode1InstrBinary(const MachineInstr &MI,
346                                                 const TargetInstrDesc &TID,
347                                                 unsigned Binary) {
348  unsigned Format = TID.TSFlags & ARMII::FormMask;
349  if (Format == ARMII::Pseudo)
350    abort(); // FIXME
351
352  // Encode S bit if MI modifies CPSR.
353  Binary |= getAddrMode1SBit(MI, TID);
354
355  // Encode register def if there is one.
356  unsigned NumDefs = TID.getNumDefs();
357  unsigned OpIdx = 0;
358  if (NumDefs) {
359    Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRdShift;
360    ++OpIdx;
361  }
362
363  // Encode first non-shifter register operand if ther is one.
364  bool isUnary = (Format == ARMII::DPRdMisc  ||
365                  Format == ARMII::DPRdIm    ||
366                  Format == ARMII::DPRdReg   ||
367                  Format == ARMII::DPRdSoReg ||
368                  Format == ARMII::DPRnIm    ||
369                  Format == ARMII::DPRnReg   ||
370                  Format == ARMII::DPRnSoReg);
371  if (!isUnary) {
372    Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRnShift;
373    ++OpIdx;
374  }
375
376  // Encode shifter operand.
377  bool HasSoReg = (Format == ARMII::DPRdSoReg ||
378                   Format == ARMII::DPRnSoReg ||
379                   Format == ARMII::DPRSoReg  ||
380                   Format == ARMII::DPRSoRegS);
381  if (HasSoReg)
382    // Encode SoReg.
383    return Binary | getMachineSoRegOpValue(MI, TID, OpIdx);
384
385  const MachineOperand &MO = MI.getOperand(OpIdx);
386  if (MO.isRegister())
387    // Encode register Rm.
388    return Binary | getMachineOpValue(MI, NumDefs + 1);
389
390  // Encode so_imm.
391  // Set bit I(25) to identify this is the immediate form of <shifter_op>
392  Binary |= 1 << ARMII::I_BitShift;
393  unsigned SoImm = MO.getImm();
394  // Encode rotate_imm.
395  Binary |= ARM_AM::getSOImmValRot(SoImm) << ARMII::RotImmShift;
396  // Encode immed_8.
397  Binary |= ARM_AM::getSOImmVal(SoImm);
398  return Binary;
399}
400
401unsigned ARMCodeEmitter::getAddrMode2InstrBinary(const MachineInstr &MI,
402                                                 const TargetInstrDesc &TID,
403                                                 unsigned Binary) {
404  // Set first operand
405  Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
406
407  // Set second operand
408  Binary |= getMachineOpValue(MI, 1) << ARMII::RegRnShift;
409
410  const MachineOperand &MO2 = MI.getOperand(2);
411  const MachineOperand &MO3 = MI.getOperand(3);
412
413  // Set bit U(23) according to sign of immed value (positive or negative).
414  Binary |= ((ARM_AM::getAM2Op(MO3.getImm()) == ARM_AM::add ? 1 : 0) <<
415             ARMII::U_BitShift);
416  if (!MO2.getReg()) { // is immediate
417    if (ARM_AM::getAM2Offset(MO3.getImm()))
418      // Set the value of offset_12 field
419      Binary |= ARM_AM::getAM2Offset(MO3.getImm());
420    return Binary;
421  }
422
423  // Set bit I(25), because this is not in immediate enconding.
424  Binary |= 1 << ARMII::I_BitShift;
425  assert(TargetRegisterInfo::isPhysicalRegister(MO2.getReg()));
426  // Set bit[3:0] to the corresponding Rm register
427  Binary |= ARMRegisterInfo::getRegisterNumbering(MO2.getReg());
428
429  // if this instr is in scaled register offset/index instruction, set
430  // shift_immed(bit[11:7]) and shift(bit[6:5]) fields.
431  if (unsigned ShImm = ARM_AM::getAM2Offset(MO3.getImm())) {
432    Binary |= getShiftOp(MO3) << 5;  // shift
433    Binary |= ShImm           << 7;  // shift_immed
434  }
435
436  return Binary;
437}
438
439unsigned ARMCodeEmitter::getAddrMode3InstrBinary(const MachineInstr &MI,
440                                                 const TargetInstrDesc &TID,
441                                                 unsigned Binary) {
442  // Set first operand
443  Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
444
445  // Set second operand
446  Binary |= getMachineOpValue(MI, 1) << ARMII::RegRnShift;
447
448  const MachineOperand &MO2 = MI.getOperand(2);
449  const MachineOperand &MO3 = MI.getOperand(3);
450
451  // Set bit U(23) according to sign of immed value (positive or negative)
452  Binary |= ((ARM_AM::getAM2Op(MO3.getImm()) == ARM_AM::add ? 1 : 0) <<
453             ARMII::U_BitShift);
454
455  // If this instr is in register offset/index encoding, set bit[3:0]
456  // to the corresponding Rm register.
457  if (MO2.getReg()) {
458    Binary |= ARMRegisterInfo::getRegisterNumbering(MO2.getReg());
459    return Binary;
460  }
461
462  // if this instr is in immediate offset/index encoding, set bit 22 to 1
463  if (unsigned ImmOffs = ARM_AM::getAM3Offset(MO3.getImm())) {
464    Binary |= 1 << 22;
465    // Set operands
466    Binary |= (ImmOffs >> 4) << 8;  // immedH
467    Binary |= (ImmOffs & ~0xF);     // immedL
468  }
469
470  return Binary;
471}
472
473unsigned ARMCodeEmitter::getAddrMode4InstrBinary(const MachineInstr &MI,
474                                                 const TargetInstrDesc &TID,
475                                                 unsigned Binary) {
476  // Set first operand
477  Binary |= getMachineOpValue(MI, 0) << ARMII::RegRnShift;
478
479  // Set addressing mode by modifying bits U(23) and P(24)
480  // IA - Increment after  - bit U = 1 and bit P = 0
481  // IB - Increment before - bit U = 1 and bit P = 1
482  // DA - Decrement after  - bit U = 0 and bit P = 0
483  // DB - Decrement before - bit U = 0 and bit P = 1
484  const MachineOperand &MO = MI.getOperand(1);
485  ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MO.getImm());
486  switch (Mode) {
487  default: assert(0 && "Unknown addressing sub-mode!");
488  case ARM_AM::da:                      break;
489  case ARM_AM::db: Binary |= 0x1 << 24; break;
490  case ARM_AM::ia: Binary |= 0x1 << 23; break;
491  case ARM_AM::ib: Binary |= 0x3 << 23; break;
492  }
493
494  // Set bit W(21)
495  if (ARM_AM::getAM4WBFlag(MO.getImm()))
496    Binary |= 0x1 << 21;
497
498  // Set registers
499  for (unsigned i = 4, e = MI.getNumOperands(); i != e; ++i) {
500    const MachineOperand &MO = MI.getOperand(i);
501    if (MO.isRegister() && MO.isImplicit())
502      continue;
503    unsigned RegNum = ARMRegisterInfo::getRegisterNumbering(MO.getReg());
504    assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()) &&
505           RegNum < 16);
506    Binary |= 0x1 << RegNum;
507  }
508
509  return Binary;
510}
511
512/// getInstrBinary - Return binary encoding for the specified
513/// machine instruction.
514unsigned ARMCodeEmitter::getInstrBinary(const MachineInstr &MI) {
515  // Part of binary is determined by TableGn.
516  unsigned Binary = getBinaryCodeForInstr(MI);
517
518  const TargetInstrDesc &TID = MI.getDesc();
519  switch (TID.TSFlags & ARMII::AddrModeMask) {
520  case ARMII::AddrModeNone:
521    return getAddrModeNoneInstrBinary(MI, TID, Binary);
522  case ARMII::AddrMode1:
523    return getAddrMode1InstrBinary(MI, TID, Binary);
524  case ARMII::AddrMode2:
525    return getAddrMode2InstrBinary(MI, TID, Binary);
526  case ARMII::AddrMode3:
527    return getAddrMode3InstrBinary(MI, TID, Binary);
528  case ARMII::AddrMode4:
529    return getAddrMode4InstrBinary(MI, TID, Binary);
530  }
531
532  abort();
533  return 0;
534}
535
536#include "ARMGenCodeEmitter.inc"
537