ARMCodeEmitter.cpp revision 4d03e416be8cf1f0f502118826b7cbaeec0b79b2
1//===-- ARM/ARMCodeEmitter.cpp - Convert ARM code to machine code ---------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the pass that transforms the ARM machine instructions into 11// relocatable machine code. 12// 13//===----------------------------------------------------------------------===// 14 15#define DEBUG_TYPE "jit" 16#include "ARM.h" 17#include "ARMAddressingModes.h" 18#include "ARMConstantPoolValue.h" 19#include "ARMInstrInfo.h" 20#include "ARMRelocations.h" 21#include "ARMSubtarget.h" 22#include "ARMTargetMachine.h" 23#include "llvm/Constants.h" 24#include "llvm/DerivedTypes.h" 25#include "llvm/Function.h" 26#include "llvm/PassManager.h" 27#include "llvm/CodeGen/JITCodeEmitter.h" 28#include "llvm/CodeGen/MachineConstantPool.h" 29#include "llvm/CodeGen/MachineFunctionPass.h" 30#include "llvm/CodeGen/MachineInstr.h" 31#include "llvm/CodeGen/MachineJumpTableInfo.h" 32#include "llvm/CodeGen/MachineModuleInfo.h" 33#include "llvm/CodeGen/Passes.h" 34#include "llvm/ADT/Statistic.h" 35#include "llvm/Support/Debug.h" 36#include "llvm/Support/ErrorHandling.h" 37#include "llvm/Support/raw_ostream.h" 38#ifndef NDEBUG 39#include <iomanip> 40#endif 41using namespace llvm; 42 43STATISTIC(NumEmitted, "Number of machine instructions emitted"); 44 45namespace { 46 47 class ARMCodeEmitter : public MachineFunctionPass { 48 ARMJITInfo *JTI; 49 const ARMInstrInfo *II; 50 const TargetData *TD; 51 const ARMSubtarget *Subtarget; 52 TargetMachine &TM; 53 JITCodeEmitter &MCE; 54 MachineModuleInfo *MMI; 55 const std::vector<MachineConstantPoolEntry> *MCPEs; 56 const std::vector<MachineJumpTableEntry> *MJTEs; 57 bool IsPIC; 58 bool IsThumb; 59 60 void getAnalysisUsage(AnalysisUsage &AU) const { 61 AU.addRequired<MachineModuleInfo>(); 62 MachineFunctionPass::getAnalysisUsage(AU); 63 } 64 65 static char ID; 66 public: 67 ARMCodeEmitter(TargetMachine &tm, JITCodeEmitter &mce) 68 : MachineFunctionPass(ID), JTI(0), 69 II((const ARMInstrInfo *)tm.getInstrInfo()), 70 TD(tm.getTargetData()), TM(tm), 71 MCE(mce), MCPEs(0), MJTEs(0), 72 IsPIC(TM.getRelocationModel() == Reloc::PIC_), IsThumb(false) {} 73 74 /// getBinaryCodeForInstr - This function, generated by the 75 /// CodeEmitterGenerator using TableGen, produces the binary encoding for 76 /// machine instructions. 77 unsigned getBinaryCodeForInstr(const MachineInstr &MI) const; 78 79 bool runOnMachineFunction(MachineFunction &MF); 80 81 virtual const char *getPassName() const { 82 return "ARM Machine Code Emitter"; 83 } 84 85 void emitInstruction(const MachineInstr &MI); 86 87 private: 88 89 void emitWordLE(unsigned Binary); 90 void emitDWordLE(uint64_t Binary); 91 void emitConstantToMemory(unsigned CPI, const Constant *CV); 92 void emitConstPoolInstruction(const MachineInstr &MI); 93 void emitMOVi32immInstruction(const MachineInstr &MI); 94 void emitMOVi2piecesInstruction(const MachineInstr &MI); 95 void emitLEApcrelInstruction(const MachineInstr &MI); 96 void emitLEApcrelJTInstruction(const MachineInstr &MI); 97 void emitPseudoMoveInstruction(const MachineInstr &MI); 98 void addPCLabel(unsigned LabelID); 99 void emitPseudoInstruction(const MachineInstr &MI); 100 unsigned getMachineSoRegOpValue(const MachineInstr &MI, 101 const TargetInstrDesc &TID, 102 const MachineOperand &MO, 103 unsigned OpIdx); 104 105 unsigned getMachineSoImmOpValue(unsigned SoImm); 106 unsigned getAddrModeSBit(const MachineInstr &MI, 107 const TargetInstrDesc &TID) const; 108 109 void emitDataProcessingInstruction(const MachineInstr &MI, 110 unsigned ImplicitRd = 0, 111 unsigned ImplicitRn = 0); 112 113 void emitLoadStoreInstruction(const MachineInstr &MI, 114 unsigned ImplicitRd = 0, 115 unsigned ImplicitRn = 0); 116 117 void emitMiscLoadStoreInstruction(const MachineInstr &MI, 118 unsigned ImplicitRn = 0); 119 120 void emitLoadStoreMultipleInstruction(const MachineInstr &MI); 121 122 void emitMulFrmInstruction(const MachineInstr &MI); 123 124 void emitExtendInstruction(const MachineInstr &MI); 125 126 void emitMiscArithInstruction(const MachineInstr &MI); 127 128 void emitSaturateInstruction(const MachineInstr &MI); 129 130 void emitBranchInstruction(const MachineInstr &MI); 131 132 void emitInlineJumpTable(unsigned JTIndex); 133 134 void emitMiscBranchInstruction(const MachineInstr &MI); 135 136 void emitVFPArithInstruction(const MachineInstr &MI); 137 138 void emitVFPConversionInstruction(const MachineInstr &MI); 139 140 void emitVFPLoadStoreInstruction(const MachineInstr &MI); 141 142 void emitVFPLoadStoreMultipleInstruction(const MachineInstr &MI); 143 144 void emitNEONLaneInstruction(const MachineInstr &MI); 145 void emitNEONDupInstruction(const MachineInstr &MI); 146 void emitNEON1RegModImmInstruction(const MachineInstr &MI); 147 void emitNEON2RegInstruction(const MachineInstr &MI); 148 void emitNEON3RegInstruction(const MachineInstr &MI); 149 150 /// getMachineOpValue - Return binary encoding of operand. If the machine 151 /// operand requires relocation, record the relocation and return zero. 152 unsigned getMachineOpValue(const MachineInstr &MI, 153 const MachineOperand &MO) const; 154 unsigned getMachineOpValue(const MachineInstr &MI, unsigned OpIdx) const { 155 return getMachineOpValue(MI, MI.getOperand(OpIdx)); 156 } 157 158 // FIXME: The legacy JIT ARMCodeEmitter doesn't rely on the the 159 // TableGen'erated getBinaryCodeForInstr() function to encode any 160 // operand values, instead querying getMachineOpValue() directly for 161 // each operand it needs to encode. Thus, any of the new encoder 162 // helper functions can simply return 0 as the values the return 163 // are already handled elsewhere. They are placeholders to allow this 164 // encoder to continue to function until the MC encoder is sufficiently 165 // far along that this one can be eliminated entirely. 166 unsigned NEONThumb2DataIPostEncoder(const MachineInstr &MI, unsigned Val) 167 const { return 0; } 168 unsigned NEONThumb2LoadStorePostEncoder(const MachineInstr &MI,unsigned Val) 169 const { return 0; } 170 unsigned NEONThumb2DupPostEncoder(const MachineInstr &MI,unsigned Val) 171 const { return 0; } 172 unsigned getBranchTargetOpValue(const MachineInstr &MI, unsigned Op) 173 const { return 0; } 174 unsigned getCCOutOpValue(const MachineInstr &MI, unsigned Op) 175 const { return 0; } 176 unsigned getSOImmOpValue(const MachineInstr &MI, unsigned Op) 177 const { return 0; } 178 unsigned getT2SOImmOpValue(const MachineInstr &MI, unsigned Op) 179 const { return 0; } 180 unsigned getSORegOpValue(const MachineInstr &MI, unsigned Op) 181 const { return 0; } 182 unsigned getT2SORegOpValue(const MachineInstr &MI, unsigned Op) 183 const { return 0; } 184 unsigned getRotImmOpValue(const MachineInstr &MI, unsigned Op) 185 const { return 0; } 186 unsigned getImmMinusOneOpValue(const MachineInstr &MI, unsigned Op) 187 const { return 0; } 188 unsigned getAddrMode6AddressOpValue(const MachineInstr &MI, unsigned Op) 189 const { return 0; } 190 unsigned getAddrMode6OffsetOpValue(const MachineInstr &MI, unsigned Op) 191 const { return 0; } 192 unsigned getBitfieldInvertedMaskOpValue(const MachineInstr &MI, 193 unsigned Op) const { return 0; } 194 uint32_t getLdStmModeOpValue(const MachineInstr &MI, unsigned OpIdx) 195 const {return 0; } 196 uint32_t getLdStSORegOpValue(const MachineInstr &MI, unsigned OpIdx) 197 const { return 0; } 198 199 unsigned getAddrModeImm12OpValue(const MachineInstr &MI, unsigned Op) 200 const { 201 // {17-13} = reg 202 // {12} = (U)nsigned (add == '1', sub == '0') 203 // {11-0} = imm12 204 const MachineOperand &MO = MI.getOperand(Op); 205 const MachineOperand &MO1 = MI.getOperand(Op + 1); 206 if (!MO.isReg()) { 207 emitConstPoolAddress(MO.getIndex(), ARM::reloc_arm_cp_entry); 208 return 0; 209 } 210 unsigned Reg = getARMRegisterNumbering(MO.getReg()); 211 int32_t Imm12 = MO1.getImm(); 212 uint32_t Binary; 213 Binary = Imm12 & 0xfff; 214 if (Imm12 >= 0) 215 Binary |= (1 << 12); 216 Binary |= (Reg << 13); 217 return Binary; 218 } 219 uint32_t getAddrMode2OpValue(const MachineInstr &MI, unsigned OpIdx) 220 const { return 0;} 221 uint32_t getAddrMode2OffsetOpValue(const MachineInstr &MI, unsigned OpIdx) 222 const { return 0;} 223 uint32_t getAddrMode3OffsetOpValue(const MachineInstr &MI, unsigned OpIdx) 224 const { return 0;} 225 uint32_t getAddrMode3OpValue(const MachineInstr &MI, unsigned Op) const 226 { return 0; } 227 uint32_t getAddrMode5OpValue(const MachineInstr &MI, unsigned Op) const { 228 // {12-9} = reg 229 // {8} = (U)nsigned (add == '1', sub == '0') 230 // {7-0} = imm12 231 const MachineOperand &MO = MI.getOperand(Op); 232 const MachineOperand &MO1 = MI.getOperand(Op + 1); 233 if (!MO.isReg()) { 234 emitConstPoolAddress(MO.getIndex(), ARM::reloc_arm_cp_entry); 235 return 0; 236 } 237 unsigned Reg = getARMRegisterNumbering(MO.getReg()); 238 int32_t Imm8 = MO1.getImm(); 239 uint32_t Binary; 240 Binary = Imm8 & 0xff; 241 if (Imm8 >= 0) 242 Binary |= (1 << 8); 243 Binary |= (Reg << 9); 244 return Binary; 245 } 246 unsigned getNEONVcvtImm32OpValue(const MachineInstr &MI, unsigned Op) 247 const { return 0; } 248 249 unsigned getRegisterListOpValue(const MachineInstr &MI, unsigned Op) 250 const { return 0; } 251 252 /// getMovi32Value - Return binary encoding of operand for movw/movt. If the 253 /// machine operand requires relocation, record the relocation and return 254 /// zero. 255 unsigned getMovi32Value(const MachineInstr &MI,const MachineOperand &MO, 256 unsigned Reloc); 257 258 /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value. 259 /// 260 unsigned getShiftOp(unsigned Imm) const ; 261 262 /// Routines that handle operands which add machine relocations which are 263 /// fixed up by the relocation stage. 264 void emitGlobalAddress(const GlobalValue *GV, unsigned Reloc, 265 bool MayNeedFarStub, bool Indirect, 266 intptr_t ACPV = 0) const; 267 void emitExternalSymbolAddress(const char *ES, unsigned Reloc) const; 268 void emitConstPoolAddress(unsigned CPI, unsigned Reloc) const; 269 void emitJumpTableAddress(unsigned JTIndex, unsigned Reloc) const; 270 void emitMachineBasicBlock(MachineBasicBlock *BB, unsigned Reloc, 271 intptr_t JTBase = 0) const; 272 }; 273} 274 275char ARMCodeEmitter::ID = 0; 276 277/// createARMJITCodeEmitterPass - Return a pass that emits the collected ARM 278/// code to the specified MCE object. 279FunctionPass *llvm::createARMJITCodeEmitterPass(ARMBaseTargetMachine &TM, 280 JITCodeEmitter &JCE) { 281 return new ARMCodeEmitter(TM, JCE); 282} 283 284bool ARMCodeEmitter::runOnMachineFunction(MachineFunction &MF) { 285 assert((MF.getTarget().getRelocationModel() != Reloc::Default || 286 MF.getTarget().getRelocationModel() != Reloc::Static) && 287 "JIT relocation model must be set to static or default!"); 288 JTI = ((ARMTargetMachine &)MF.getTarget()).getJITInfo(); 289 II = ((const ARMTargetMachine &)MF.getTarget()).getInstrInfo(); 290 TD = ((const ARMTargetMachine &)MF.getTarget()).getTargetData(); 291 Subtarget = &TM.getSubtarget<ARMSubtarget>(); 292 MCPEs = &MF.getConstantPool()->getConstants(); 293 MJTEs = 0; 294 if (MF.getJumpTableInfo()) MJTEs = &MF.getJumpTableInfo()->getJumpTables(); 295 IsPIC = TM.getRelocationModel() == Reloc::PIC_; 296 IsThumb = MF.getInfo<ARMFunctionInfo>()->isThumbFunction(); 297 JTI->Initialize(MF, IsPIC); 298 MMI = &getAnalysis<MachineModuleInfo>(); 299 MCE.setModuleInfo(MMI); 300 301 do { 302 DEBUG(errs() << "JITTing function '" 303 << MF.getFunction()->getName() << "'\n"); 304 MCE.startFunction(MF); 305 for (MachineFunction::iterator MBB = MF.begin(), E = MF.end(); 306 MBB != E; ++MBB) { 307 MCE.StartMachineBasicBlock(MBB); 308 for (MachineBasicBlock::const_iterator I = MBB->begin(), E = MBB->end(); 309 I != E; ++I) 310 emitInstruction(*I); 311 } 312 } while (MCE.finishFunction(MF)); 313 314 return false; 315} 316 317/// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value. 318/// 319unsigned ARMCodeEmitter::getShiftOp(unsigned Imm) const { 320 switch (ARM_AM::getAM2ShiftOpc(Imm)) { 321 default: llvm_unreachable("Unknown shift opc!"); 322 case ARM_AM::asr: return 2; 323 case ARM_AM::lsl: return 0; 324 case ARM_AM::lsr: return 1; 325 case ARM_AM::ror: 326 case ARM_AM::rrx: return 3; 327 } 328 return 0; 329} 330 331/// getMovi32Value - Return binary encoding of operand for movw/movt. If the 332/// machine operand requires relocation, record the relocation and return zero. 333unsigned ARMCodeEmitter::getMovi32Value(const MachineInstr &MI, 334 const MachineOperand &MO, 335 unsigned Reloc) { 336 assert(((Reloc == ARM::reloc_arm_movt) || (Reloc == ARM::reloc_arm_movw)) 337 && "Relocation to this function should be for movt or movw"); 338 339 if (MO.isImm()) 340 return static_cast<unsigned>(MO.getImm()); 341 else if (MO.isGlobal()) 342 emitGlobalAddress(MO.getGlobal(), Reloc, true, false); 343 else if (MO.isSymbol()) 344 emitExternalSymbolAddress(MO.getSymbolName(), Reloc); 345 else if (MO.isMBB()) 346 emitMachineBasicBlock(MO.getMBB(), Reloc); 347 else { 348#ifndef NDEBUG 349 errs() << MO; 350#endif 351 llvm_unreachable("Unsupported operand type for movw/movt"); 352 } 353 return 0; 354} 355 356/// getMachineOpValue - Return binary encoding of operand. If the machine 357/// operand requires relocation, record the relocation and return zero. 358unsigned ARMCodeEmitter::getMachineOpValue(const MachineInstr &MI, 359 const MachineOperand &MO) const { 360 if (MO.isReg()) 361 return getARMRegisterNumbering(MO.getReg()); 362 else if (MO.isImm()) 363 return static_cast<unsigned>(MO.getImm()); 364 else if (MO.isGlobal()) 365 emitGlobalAddress(MO.getGlobal(), ARM::reloc_arm_branch, true, false); 366 else if (MO.isSymbol()) 367 emitExternalSymbolAddress(MO.getSymbolName(), ARM::reloc_arm_branch); 368 else if (MO.isCPI()) { 369 const TargetInstrDesc &TID = MI.getDesc(); 370 // For VFP load, the immediate offset is multiplied by 4. 371 unsigned Reloc = ((TID.TSFlags & ARMII::FormMask) == ARMII::VFPLdStFrm) 372 ? ARM::reloc_arm_vfp_cp_entry : ARM::reloc_arm_cp_entry; 373 emitConstPoolAddress(MO.getIndex(), Reloc); 374 } else if (MO.isJTI()) 375 emitJumpTableAddress(MO.getIndex(), ARM::reloc_arm_relative); 376 else if (MO.isMBB()) 377 emitMachineBasicBlock(MO.getMBB(), ARM::reloc_arm_branch); 378 else { 379#ifndef NDEBUG 380 errs() << MO; 381#endif 382 llvm_unreachable(0); 383 } 384 return 0; 385} 386 387/// emitGlobalAddress - Emit the specified address to the code stream. 388/// 389void ARMCodeEmitter::emitGlobalAddress(const GlobalValue *GV, unsigned Reloc, 390 bool MayNeedFarStub, bool Indirect, 391 intptr_t ACPV) const { 392 MachineRelocation MR = Indirect 393 ? MachineRelocation::getIndirectSymbol(MCE.getCurrentPCOffset(), Reloc, 394 const_cast<GlobalValue *>(GV), 395 ACPV, MayNeedFarStub) 396 : MachineRelocation::getGV(MCE.getCurrentPCOffset(), Reloc, 397 const_cast<GlobalValue *>(GV), ACPV, 398 MayNeedFarStub); 399 MCE.addRelocation(MR); 400} 401 402/// emitExternalSymbolAddress - Arrange for the address of an external symbol to 403/// be emitted to the current location in the function, and allow it to be PC 404/// relative. 405void ARMCodeEmitter:: 406emitExternalSymbolAddress(const char *ES, unsigned Reloc) const { 407 MCE.addRelocation(MachineRelocation::getExtSym(MCE.getCurrentPCOffset(), 408 Reloc, ES)); 409} 410 411/// emitConstPoolAddress - Arrange for the address of an constant pool 412/// to be emitted to the current location in the function, and allow it to be PC 413/// relative. 414void ARMCodeEmitter::emitConstPoolAddress(unsigned CPI, unsigned Reloc) const { 415 // Tell JIT emitter we'll resolve the address. 416 MCE.addRelocation(MachineRelocation::getConstPool(MCE.getCurrentPCOffset(), 417 Reloc, CPI, 0, true)); 418} 419 420/// emitJumpTableAddress - Arrange for the address of a jump table to 421/// be emitted to the current location in the function, and allow it to be PC 422/// relative. 423void ARMCodeEmitter:: 424emitJumpTableAddress(unsigned JTIndex, unsigned Reloc) const { 425 MCE.addRelocation(MachineRelocation::getJumpTable(MCE.getCurrentPCOffset(), 426 Reloc, JTIndex, 0, true)); 427} 428 429/// emitMachineBasicBlock - Emit the specified address basic block. 430void ARMCodeEmitter::emitMachineBasicBlock(MachineBasicBlock *BB, 431 unsigned Reloc, 432 intptr_t JTBase) const { 433 MCE.addRelocation(MachineRelocation::getBB(MCE.getCurrentPCOffset(), 434 Reloc, BB, JTBase)); 435} 436 437void ARMCodeEmitter::emitWordLE(unsigned Binary) { 438 DEBUG(errs() << " 0x"; 439 errs().write_hex(Binary) << "\n"); 440 MCE.emitWordLE(Binary); 441} 442 443void ARMCodeEmitter::emitDWordLE(uint64_t Binary) { 444 DEBUG(errs() << " 0x"; 445 errs().write_hex(Binary) << "\n"); 446 MCE.emitDWordLE(Binary); 447} 448 449void ARMCodeEmitter::emitInstruction(const MachineInstr &MI) { 450 DEBUG(errs() << "JIT: " << (void*)MCE.getCurrentPCValue() << ":\t" << MI); 451 452 MCE.processDebugLoc(MI.getDebugLoc(), true); 453 454 ++NumEmitted; // Keep track of the # of mi's emitted 455 switch (MI.getDesc().TSFlags & ARMII::FormMask) { 456 default: { 457 llvm_unreachable("Unhandled instruction encoding format!"); 458 break; 459 } 460 case ARMII::Pseudo: 461 emitPseudoInstruction(MI); 462 break; 463 case ARMII::DPFrm: 464 case ARMII::DPSoRegFrm: 465 emitDataProcessingInstruction(MI); 466 break; 467 case ARMII::LdFrm: 468 case ARMII::StFrm: 469 emitLoadStoreInstruction(MI); 470 break; 471 case ARMII::LdMiscFrm: 472 case ARMII::StMiscFrm: 473 emitMiscLoadStoreInstruction(MI); 474 break; 475 case ARMII::LdStMulFrm: 476 emitLoadStoreMultipleInstruction(MI); 477 break; 478 case ARMII::MulFrm: 479 emitMulFrmInstruction(MI); 480 break; 481 case ARMII::ExtFrm: 482 emitExtendInstruction(MI); 483 break; 484 case ARMII::ArithMiscFrm: 485 emitMiscArithInstruction(MI); 486 break; 487 case ARMII::SatFrm: 488 emitSaturateInstruction(MI); 489 break; 490 case ARMII::BrFrm: 491 emitBranchInstruction(MI); 492 break; 493 case ARMII::BrMiscFrm: 494 emitMiscBranchInstruction(MI); 495 break; 496 // VFP instructions. 497 case ARMII::VFPUnaryFrm: 498 case ARMII::VFPBinaryFrm: 499 emitVFPArithInstruction(MI); 500 break; 501 case ARMII::VFPConv1Frm: 502 case ARMII::VFPConv2Frm: 503 case ARMII::VFPConv3Frm: 504 case ARMII::VFPConv4Frm: 505 case ARMII::VFPConv5Frm: 506 emitVFPConversionInstruction(MI); 507 break; 508 case ARMII::VFPLdStFrm: 509 emitVFPLoadStoreInstruction(MI); 510 break; 511 case ARMII::VFPLdStMulFrm: 512 emitVFPLoadStoreMultipleInstruction(MI); 513 break; 514 515 // NEON instructions. 516 case ARMII::NGetLnFrm: 517 case ARMII::NSetLnFrm: 518 emitNEONLaneInstruction(MI); 519 break; 520 case ARMII::NDupFrm: 521 emitNEONDupInstruction(MI); 522 break; 523 case ARMII::N1RegModImmFrm: 524 emitNEON1RegModImmInstruction(MI); 525 break; 526 case ARMII::N2RegFrm: 527 emitNEON2RegInstruction(MI); 528 break; 529 case ARMII::N3RegFrm: 530 emitNEON3RegInstruction(MI); 531 break; 532 } 533 MCE.processDebugLoc(MI.getDebugLoc(), false); 534} 535 536void ARMCodeEmitter::emitConstantToMemory(unsigned CPI, const Constant *C) { 537 DEBUG({ 538 errs() << " ** Constant pool #" << CPI << " @ " 539 << (void*)MCE.getCurrentPCValue() << " "; 540 if (const Function *F = dyn_cast<Function>(C)) 541 errs() << F->getName(); 542 else 543 errs() << *C; 544 errs() << '\n'; 545 }); 546 547 switch (C->getValueID()) { 548 default: { 549 llvm_unreachable("Unable to handle this constantpool entry!"); 550 break; 551 } 552 case Value::GlobalVariableVal: { 553 emitGlobalAddress(static_cast<const GlobalValue*>(C), 554 ARM::reloc_arm_absolute, isa<Function>(C), false); 555 emitWordLE(0); 556 break; 557 } 558 case Value::ConstantIntVal: { 559 const ConstantInt *CI = static_cast<const ConstantInt*>(C); 560 uint32_t Val = *(uint32_t*)CI->getValue().getRawData(); 561 emitWordLE(Val); 562 break; 563 } 564 case Value::ConstantFPVal: { 565 const ConstantFP *CFP = static_cast<const ConstantFP*>(C); 566 if (CFP->getType()->isFloatTy()) 567 emitWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue()); 568 else if (CFP->getType()->isDoubleTy()) 569 emitDWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue()); 570 else { 571 llvm_unreachable("Unable to handle this constantpool entry!"); 572 } 573 break; 574 } 575 case Value::ConstantArrayVal: { 576 const ConstantArray *CA = static_cast<const ConstantArray*>(C); 577 for (unsigned i = 0, e = CA->getNumOperands(); i != e; ++i) 578 emitConstantToMemory(CPI, CA->getOperand(i)); 579 break; 580 } 581 } 582 583 return; 584} 585 586void ARMCodeEmitter::emitConstPoolInstruction(const MachineInstr &MI) { 587 unsigned CPI = MI.getOperand(0).getImm(); // CP instruction index. 588 unsigned CPIndex = MI.getOperand(1).getIndex(); // Actual cp entry index. 589 const MachineConstantPoolEntry &MCPE = (*MCPEs)[CPIndex]; 590 591 // Remember the CONSTPOOL_ENTRY address for later relocation. 592 JTI->addConstantPoolEntryAddr(CPI, MCE.getCurrentPCValue()); 593 594 // Emit constpool island entry. In most cases, the actual values will be 595 // resolved and relocated after code emission. 596 if (MCPE.isMachineConstantPoolEntry()) { 597 ARMConstantPoolValue *ACPV = 598 static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal); 599 600 DEBUG(errs() << " ** ARM constant pool #" << CPI << " @ " 601 << (void*)MCE.getCurrentPCValue() << " " << *ACPV << '\n'); 602 603 assert(ACPV->isGlobalValue() && "unsupported constant pool value"); 604 const GlobalValue *GV = ACPV->getGV(); 605 if (GV) { 606 Reloc::Model RelocM = TM.getRelocationModel(); 607 emitGlobalAddress(GV, ARM::reloc_arm_machine_cp_entry, 608 isa<Function>(GV), 609 Subtarget->GVIsIndirectSymbol(GV, RelocM), 610 (intptr_t)ACPV); 611 } else { 612 emitExternalSymbolAddress(ACPV->getSymbol(), ARM::reloc_arm_absolute); 613 } 614 emitWordLE(0); 615 } else { 616 emitConstantToMemory(CPI, MCPE.Val.ConstVal); 617 } 618} 619 620void ARMCodeEmitter::emitMOVi32immInstruction(const MachineInstr &MI) { 621 const MachineOperand &MO0 = MI.getOperand(0); 622 const MachineOperand &MO1 = MI.getOperand(1); 623 624 // Emit the 'movw' instruction. 625 unsigned Binary = 0x30 << 20; // mov: Insts{27-20} = 0b00110000 626 627 unsigned Lo16 = getMovi32Value(MI, MO1, ARM::reloc_arm_movw) & 0xFFFF; 628 629 // Set the conditional execution predicate. 630 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 631 632 // Encode Rd. 633 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift; 634 635 // Encode imm16 as imm4:imm12 636 Binary |= Lo16 & 0xFFF; // Insts{11-0} = imm12 637 Binary |= ((Lo16 >> 12) & 0xF) << 16; // Insts{19-16} = imm4 638 emitWordLE(Binary); 639 640 unsigned Hi16 = getMovi32Value(MI, MO1, ARM::reloc_arm_movt) >> 16; 641 // Emit the 'movt' instruction. 642 Binary = 0x34 << 20; // movt: Insts{27-20} = 0b00110100 643 644 // Set the conditional execution predicate. 645 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 646 647 // Encode Rd. 648 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift; 649 650 // Encode imm16 as imm4:imm1, same as movw above. 651 Binary |= Hi16 & 0xFFF; 652 Binary |= ((Hi16 >> 12) & 0xF) << 16; 653 emitWordLE(Binary); 654} 655 656void ARMCodeEmitter::emitMOVi2piecesInstruction(const MachineInstr &MI) { 657 const MachineOperand &MO0 = MI.getOperand(0); 658 const MachineOperand &MO1 = MI.getOperand(1); 659 assert(MO1.isImm() && ARM_AM::isSOImmTwoPartVal(MO1.getImm()) && 660 "Not a valid so_imm value!"); 661 unsigned V1 = ARM_AM::getSOImmTwoPartFirst(MO1.getImm()); 662 unsigned V2 = ARM_AM::getSOImmTwoPartSecond(MO1.getImm()); 663 664 // Emit the 'mov' instruction. 665 unsigned Binary = 0xd << 21; // mov: Insts{24-21} = 0b1101 666 667 // Set the conditional execution predicate. 668 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 669 670 // Encode Rd. 671 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift; 672 673 // Encode so_imm. 674 // Set bit I(25) to identify this is the immediate form of <shifter_op> 675 Binary |= 1 << ARMII::I_BitShift; 676 Binary |= getMachineSoImmOpValue(V1); 677 emitWordLE(Binary); 678 679 // Now the 'orr' instruction. 680 Binary = 0xc << 21; // orr: Insts{24-21} = 0b1100 681 682 // Set the conditional execution predicate. 683 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 684 685 // Encode Rd. 686 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift; 687 688 // Encode Rn. 689 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRnShift; 690 691 // Encode so_imm. 692 // Set bit I(25) to identify this is the immediate form of <shifter_op> 693 Binary |= 1 << ARMII::I_BitShift; 694 Binary |= getMachineSoImmOpValue(V2); 695 emitWordLE(Binary); 696} 697 698void ARMCodeEmitter::emitLEApcrelInstruction(const MachineInstr &MI) { 699 // It's basically add r, pc, (LCPI - $+8) 700 const TargetInstrDesc &TID = MI.getDesc(); 701 702 unsigned Binary = 0; 703 704 // Set the conditional execution predicate 705 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 706 707 // Encode S bit if MI modifies CPSR. 708 Binary |= getAddrModeSBit(MI, TID); 709 710 // Encode Rd. 711 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift; 712 713 // Encode Rn which is PC. 714 Binary |= getARMRegisterNumbering(ARM::PC) << ARMII::RegRnShift; 715 716 // Encode the displacement which is a so_imm. 717 // Set bit I(25) to identify this is the immediate form of <shifter_op> 718 Binary |= 1 << ARMII::I_BitShift; 719 emitConstPoolAddress(MI.getOperand(1).getIndex(), ARM::reloc_arm_so_imm_cp_entry); 720 721 emitWordLE(Binary); 722} 723 724void ARMCodeEmitter::emitLEApcrelJTInstruction(const MachineInstr &MI) { 725 // It's basically add r, pc, (LJTI - $+8) 726 727 const TargetInstrDesc &TID = MI.getDesc(); 728 729 // Emit the 'add' instruction. 730 unsigned Binary = 0x4 << 21; // add: Insts{21-24} = 0b0100 731 732 // Set the conditional execution predicate 733 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 734 735 // Encode S bit if MI modifies CPSR. 736 Binary |= getAddrModeSBit(MI, TID); 737 738 // Encode Rd. 739 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift; 740 741 // Encode Rn which is PC. 742 Binary |= getARMRegisterNumbering(ARM::PC) << ARMII::RegRnShift; 743 744 // Encode the displacement. 745 Binary |= 1 << ARMII::I_BitShift; 746 emitJumpTableAddress(MI.getOperand(1).getIndex(), ARM::reloc_arm_jt_base); 747 748 emitWordLE(Binary); 749} 750 751void ARMCodeEmitter::emitPseudoMoveInstruction(const MachineInstr &MI) { 752 unsigned Opcode = MI.getDesc().Opcode; 753 754 // Part of binary is determined by TableGn. 755 unsigned Binary = getBinaryCodeForInstr(MI); 756 757 // Set the conditional execution predicate 758 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 759 760 // Encode S bit if MI modifies CPSR. 761 if (Opcode == ARM::MOVsrl_flag || Opcode == ARM::MOVsra_flag) 762 Binary |= 1 << ARMII::S_BitShift; 763 764 // Encode register def if there is one. 765 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift; 766 767 // Encode the shift operation. 768 switch (Opcode) { 769 default: break; 770 case ARM::RRX: 771 // rrx 772 Binary |= 0x6 << 4; 773 break; 774 case ARM::MOVsrl_flag: 775 // lsr #1 776 Binary |= (0x2 << 4) | (1 << 7); 777 break; 778 case ARM::MOVsra_flag: 779 // asr #1 780 Binary |= (0x4 << 4) | (1 << 7); 781 break; 782 } 783 784 // Encode register Rm. 785 Binary |= getMachineOpValue(MI, 1); 786 787 emitWordLE(Binary); 788} 789 790void ARMCodeEmitter::addPCLabel(unsigned LabelID) { 791 DEBUG(errs() << " ** LPC" << LabelID << " @ " 792 << (void*)MCE.getCurrentPCValue() << '\n'); 793 JTI->addPCLabelAddr(LabelID, MCE.getCurrentPCValue()); 794} 795 796void ARMCodeEmitter::emitPseudoInstruction(const MachineInstr &MI) { 797 unsigned Opcode = MI.getDesc().Opcode; 798 switch (Opcode) { 799 default: 800 llvm_unreachable("ARMCodeEmitter::emitPseudoInstruction"); 801 case ARM::BX: 802 case ARM::BMOVPCRX: 803 case ARM::BXr9: 804 case ARM::BMOVPCRXr9: { 805 // First emit mov lr, pc 806 unsigned Binary = 0x01a0e00f; 807 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 808 emitWordLE(Binary); 809 810 // and then emit the branch. 811 emitMiscBranchInstruction(MI); 812 break; 813 } 814 case TargetOpcode::INLINEASM: { 815 // We allow inline assembler nodes with empty bodies - they can 816 // implicitly define registers, which is ok for JIT. 817 if (MI.getOperand(0).getSymbolName()[0]) { 818 report_fatal_error("JIT does not support inline asm!"); 819 } 820 break; 821 } 822 case TargetOpcode::PROLOG_LABEL: 823 case TargetOpcode::EH_LABEL: 824 MCE.emitLabel(MI.getOperand(0).getMCSymbol()); 825 break; 826 case TargetOpcode::IMPLICIT_DEF: 827 case TargetOpcode::KILL: 828 // Do nothing. 829 break; 830 case ARM::CONSTPOOL_ENTRY: 831 emitConstPoolInstruction(MI); 832 break; 833 case ARM::PICADD: { 834 // Remember of the address of the PC label for relocation later. 835 addPCLabel(MI.getOperand(2).getImm()); 836 // PICADD is just an add instruction that implicitly read pc. 837 emitDataProcessingInstruction(MI, 0, ARM::PC); 838 break; 839 } 840 case ARM::PICLDR: 841 case ARM::PICLDRB: 842 case ARM::PICSTR: 843 case ARM::PICSTRB: { 844 // Remember of the address of the PC label for relocation later. 845 addPCLabel(MI.getOperand(2).getImm()); 846 // These are just load / store instructions that implicitly read pc. 847 emitLoadStoreInstruction(MI, 0, ARM::PC); 848 break; 849 } 850 case ARM::PICLDRH: 851 case ARM::PICLDRSH: 852 case ARM::PICLDRSB: 853 case ARM::PICSTRH: { 854 // Remember of the address of the PC label for relocation later. 855 addPCLabel(MI.getOperand(2).getImm()); 856 // These are just load / store instructions that implicitly read pc. 857 emitMiscLoadStoreInstruction(MI, ARM::PC); 858 break; 859 } 860 861 case ARM::MOVi32imm: 862 // Two instructions to materialize a constant. 863 if (Subtarget->hasV6T2Ops()) 864 emitMOVi32immInstruction(MI); 865 else 866 emitMOVi2piecesInstruction(MI); 867 break; 868 case ARM::LEApcrel: 869 // Materialize constantpool index address. 870 emitLEApcrelInstruction(MI); 871 break; 872 case ARM::LEApcrelJT: 873 // Materialize jumptable address. 874 emitLEApcrelJTInstruction(MI); 875 break; 876 case ARM::RRX: 877 case ARM::MOVsrl_flag: 878 case ARM::MOVsra_flag: 879 emitPseudoMoveInstruction(MI); 880 break; 881 } 882} 883 884unsigned ARMCodeEmitter::getMachineSoRegOpValue(const MachineInstr &MI, 885 const TargetInstrDesc &TID, 886 const MachineOperand &MO, 887 unsigned OpIdx) { 888 unsigned Binary = getMachineOpValue(MI, MO); 889 890 const MachineOperand &MO1 = MI.getOperand(OpIdx + 1); 891 const MachineOperand &MO2 = MI.getOperand(OpIdx + 2); 892 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm()); 893 894 // Encode the shift opcode. 895 unsigned SBits = 0; 896 unsigned Rs = MO1.getReg(); 897 if (Rs) { 898 // Set shift operand (bit[7:4]). 899 // LSL - 0001 900 // LSR - 0011 901 // ASR - 0101 902 // ROR - 0111 903 // RRX - 0110 and bit[11:8] clear. 904 switch (SOpc) { 905 default: llvm_unreachable("Unknown shift opc!"); 906 case ARM_AM::lsl: SBits = 0x1; break; 907 case ARM_AM::lsr: SBits = 0x3; break; 908 case ARM_AM::asr: SBits = 0x5; break; 909 case ARM_AM::ror: SBits = 0x7; break; 910 case ARM_AM::rrx: SBits = 0x6; break; 911 } 912 } else { 913 // Set shift operand (bit[6:4]). 914 // LSL - 000 915 // LSR - 010 916 // ASR - 100 917 // ROR - 110 918 switch (SOpc) { 919 default: llvm_unreachable("Unknown shift opc!"); 920 case ARM_AM::lsl: SBits = 0x0; break; 921 case ARM_AM::lsr: SBits = 0x2; break; 922 case ARM_AM::asr: SBits = 0x4; break; 923 case ARM_AM::ror: SBits = 0x6; break; 924 } 925 } 926 Binary |= SBits << 4; 927 if (SOpc == ARM_AM::rrx) 928 return Binary; 929 930 // Encode the shift operation Rs or shift_imm (except rrx). 931 if (Rs) { 932 // Encode Rs bit[11:8]. 933 assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0); 934 return Binary | (getARMRegisterNumbering(Rs) << ARMII::RegRsShift); 935 } 936 937 // Encode shift_imm bit[11:7]. 938 return Binary | ARM_AM::getSORegOffset(MO2.getImm()) << 7; 939} 940 941unsigned ARMCodeEmitter::getMachineSoImmOpValue(unsigned SoImm) { 942 int SoImmVal = ARM_AM::getSOImmVal(SoImm); 943 assert(SoImmVal != -1 && "Not a valid so_imm value!"); 944 945 // Encode rotate_imm. 946 unsigned Binary = (ARM_AM::getSOImmValRot((unsigned)SoImmVal) >> 1) 947 << ARMII::SoRotImmShift; 948 949 // Encode immed_8. 950 Binary |= ARM_AM::getSOImmValImm((unsigned)SoImmVal); 951 return Binary; 952} 953 954unsigned ARMCodeEmitter::getAddrModeSBit(const MachineInstr &MI, 955 const TargetInstrDesc &TID) const { 956 for (unsigned i = MI.getNumOperands(), e = TID.getNumOperands(); i >= e; --i){ 957 const MachineOperand &MO = MI.getOperand(i-1); 958 if (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR) 959 return 1 << ARMII::S_BitShift; 960 } 961 return 0; 962} 963 964void ARMCodeEmitter::emitDataProcessingInstruction(const MachineInstr &MI, 965 unsigned ImplicitRd, 966 unsigned ImplicitRn) { 967 const TargetInstrDesc &TID = MI.getDesc(); 968 969 // Part of binary is determined by TableGn. 970 unsigned Binary = getBinaryCodeForInstr(MI); 971 972 // Set the conditional execution predicate 973 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 974 975 // Encode S bit if MI modifies CPSR. 976 Binary |= getAddrModeSBit(MI, TID); 977 978 // Encode register def if there is one. 979 unsigned NumDefs = TID.getNumDefs(); 980 unsigned OpIdx = 0; 981 if (NumDefs) 982 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift; 983 else if (ImplicitRd) 984 // Special handling for implicit use (e.g. PC). 985 Binary |= (getARMRegisterNumbering(ImplicitRd) << ARMII::RegRdShift); 986 987 if (TID.Opcode == ARM::MOVi16) { 988 // Get immediate from MI. 989 unsigned Lo16 = getMovi32Value(MI, MI.getOperand(OpIdx), 990 ARM::reloc_arm_movw); 991 // Encode imm which is the same as in emitMOVi32immInstruction(). 992 Binary |= Lo16 & 0xFFF; 993 Binary |= ((Lo16 >> 12) & 0xF) << 16; 994 emitWordLE(Binary); 995 return; 996 } else if(TID.Opcode == ARM::MOVTi16) { 997 unsigned Hi16 = (getMovi32Value(MI, MI.getOperand(OpIdx), 998 ARM::reloc_arm_movt) >> 16); 999 Binary |= Hi16 & 0xFFF; 1000 Binary |= ((Hi16 >> 12) & 0xF) << 16; 1001 emitWordLE(Binary); 1002 return; 1003 } else if ((TID.Opcode == ARM::BFC) || (TID.Opcode == ARM::BFI)) { 1004 uint32_t v = ~MI.getOperand(2).getImm(); 1005 int32_t lsb = CountTrailingZeros_32(v); 1006 int32_t msb = (32 - CountLeadingZeros_32(v)) - 1; 1007 // Instr{20-16} = msb, Instr{11-7} = lsb 1008 Binary |= (msb & 0x1F) << 16; 1009 Binary |= (lsb & 0x1F) << 7; 1010 emitWordLE(Binary); 1011 return; 1012 } else if ((TID.Opcode == ARM::UBFX) || (TID.Opcode == ARM::SBFX)) { 1013 // Encode Rn in Instr{0-3} 1014 Binary |= getMachineOpValue(MI, OpIdx++); 1015 1016 uint32_t lsb = MI.getOperand(OpIdx++).getImm(); 1017 uint32_t widthm1 = MI.getOperand(OpIdx++).getImm() - 1; 1018 1019 // Instr{20-16} = widthm1, Instr{11-7} = lsb 1020 Binary |= (widthm1 & 0x1F) << 16; 1021 Binary |= (lsb & 0x1F) << 7; 1022 emitWordLE(Binary); 1023 return; 1024 } 1025 1026 // If this is a two-address operand, skip it. e.g. MOVCCr operand 1. 1027 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1) 1028 ++OpIdx; 1029 1030 // Encode first non-shifter register operand if there is one. 1031 bool isUnary = TID.TSFlags & ARMII::UnaryDP; 1032 if (!isUnary) { 1033 if (ImplicitRn) 1034 // Special handling for implicit use (e.g. PC). 1035 Binary |= (getARMRegisterNumbering(ImplicitRn) << ARMII::RegRnShift); 1036 else { 1037 Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRnShift; 1038 ++OpIdx; 1039 } 1040 } 1041 1042 // Encode shifter operand. 1043 const MachineOperand &MO = MI.getOperand(OpIdx); 1044 if ((TID.TSFlags & ARMII::FormMask) == ARMII::DPSoRegFrm) { 1045 // Encode SoReg. 1046 emitWordLE(Binary | getMachineSoRegOpValue(MI, TID, MO, OpIdx)); 1047 return; 1048 } 1049 1050 if (MO.isReg()) { 1051 // Encode register Rm. 1052 emitWordLE(Binary | getARMRegisterNumbering(MO.getReg())); 1053 return; 1054 } 1055 1056 // Encode so_imm. 1057 Binary |= getMachineSoImmOpValue((unsigned)MO.getImm()); 1058 1059 emitWordLE(Binary); 1060} 1061 1062void ARMCodeEmitter::emitLoadStoreInstruction(const MachineInstr &MI, 1063 unsigned ImplicitRd, 1064 unsigned ImplicitRn) { 1065 const TargetInstrDesc &TID = MI.getDesc(); 1066 unsigned Form = TID.TSFlags & ARMII::FormMask; 1067 bool IsPrePost = (TID.TSFlags & ARMII::IndexModeMask) != 0; 1068 1069 // Part of binary is determined by TableGn. 1070 unsigned Binary = getBinaryCodeForInstr(MI); 1071 1072 // If this is an LDRi12, STRi12 or LDRcp, nothing more needs be done. 1073 if (MI.getOpcode() == ARM::LDRi12 || MI.getOpcode() == ARM::LDRcp || 1074 MI.getOpcode() == ARM::STRi12) { 1075 emitWordLE(Binary); 1076 return; 1077 } 1078 1079 // Set the conditional execution predicate 1080 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1081 1082 unsigned OpIdx = 0; 1083 1084 // Operand 0 of a pre- and post-indexed store is the address base 1085 // writeback. Skip it. 1086 bool Skipped = false; 1087 if (IsPrePost && Form == ARMII::StFrm) { 1088 ++OpIdx; 1089 Skipped = true; 1090 } 1091 1092 // Set first operand 1093 if (ImplicitRd) 1094 // Special handling for implicit use (e.g. PC). 1095 Binary |= (getARMRegisterNumbering(ImplicitRd) << ARMII::RegRdShift); 1096 else 1097 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift; 1098 1099 // Set second operand 1100 if (ImplicitRn) 1101 // Special handling for implicit use (e.g. PC). 1102 Binary |= (getARMRegisterNumbering(ImplicitRn) << ARMII::RegRnShift); 1103 else 1104 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift; 1105 1106 // If this is a two-address operand, skip it. e.g. LDR_PRE. 1107 if (!Skipped && TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1) 1108 ++OpIdx; 1109 1110 const MachineOperand &MO2 = MI.getOperand(OpIdx); 1111 unsigned AM2Opc = (ImplicitRn == ARM::PC) 1112 ? 0 : MI.getOperand(OpIdx+1).getImm(); 1113 1114 // Set bit U(23) according to sign of immed value (positive or negative). 1115 Binary |= ((ARM_AM::getAM2Op(AM2Opc) == ARM_AM::add ? 1 : 0) << 1116 ARMII::U_BitShift); 1117 if (!MO2.getReg()) { // is immediate 1118 if (ARM_AM::getAM2Offset(AM2Opc)) 1119 // Set the value of offset_12 field 1120 Binary |= ARM_AM::getAM2Offset(AM2Opc); 1121 emitWordLE(Binary); 1122 return; 1123 } 1124 1125 // Set bit I(25), because this is not in immediate encoding. 1126 Binary |= 1 << ARMII::I_BitShift; 1127 assert(TargetRegisterInfo::isPhysicalRegister(MO2.getReg())); 1128 // Set bit[3:0] to the corresponding Rm register 1129 Binary |= getARMRegisterNumbering(MO2.getReg()); 1130 1131 // If this instr is in scaled register offset/index instruction, set 1132 // shift_immed(bit[11:7]) and shift(bit[6:5]) fields. 1133 if (unsigned ShImm = ARM_AM::getAM2Offset(AM2Opc)) { 1134 Binary |= getShiftOp(AM2Opc) << ARMII::ShiftImmShift; // shift 1135 Binary |= ShImm << ARMII::ShiftShift; // shift_immed 1136 } 1137 1138 emitWordLE(Binary); 1139} 1140 1141void ARMCodeEmitter::emitMiscLoadStoreInstruction(const MachineInstr &MI, 1142 unsigned ImplicitRn) { 1143 const TargetInstrDesc &TID = MI.getDesc(); 1144 unsigned Form = TID.TSFlags & ARMII::FormMask; 1145 bool IsPrePost = (TID.TSFlags & ARMII::IndexModeMask) != 0; 1146 1147 // Part of binary is determined by TableGn. 1148 unsigned Binary = getBinaryCodeForInstr(MI); 1149 1150 // Set the conditional execution predicate 1151 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1152 1153 unsigned OpIdx = 0; 1154 1155 // Operand 0 of a pre- and post-indexed store is the address base 1156 // writeback. Skip it. 1157 bool Skipped = false; 1158 if (IsPrePost && Form == ARMII::StMiscFrm) { 1159 ++OpIdx; 1160 Skipped = true; 1161 } 1162 1163 // Set first operand 1164 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift; 1165 1166 // Skip LDRD and STRD's second operand. 1167 if (TID.Opcode == ARM::LDRD || TID.Opcode == ARM::STRD) 1168 ++OpIdx; 1169 1170 // Set second operand 1171 if (ImplicitRn) 1172 // Special handling for implicit use (e.g. PC). 1173 Binary |= (getARMRegisterNumbering(ImplicitRn) << ARMII::RegRnShift); 1174 else 1175 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift; 1176 1177 // If this is a two-address operand, skip it. e.g. LDRH_POST. 1178 if (!Skipped && TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1) 1179 ++OpIdx; 1180 1181 const MachineOperand &MO2 = MI.getOperand(OpIdx); 1182 unsigned AM3Opc = (ImplicitRn == ARM::PC) 1183 ? 0 : MI.getOperand(OpIdx+1).getImm(); 1184 1185 // Set bit U(23) according to sign of immed value (positive or negative) 1186 Binary |= ((ARM_AM::getAM3Op(AM3Opc) == ARM_AM::add ? 1 : 0) << 1187 ARMII::U_BitShift); 1188 1189 // If this instr is in register offset/index encoding, set bit[3:0] 1190 // to the corresponding Rm register. 1191 if (MO2.getReg()) { 1192 Binary |= getARMRegisterNumbering(MO2.getReg()); 1193 emitWordLE(Binary); 1194 return; 1195 } 1196 1197 // This instr is in immediate offset/index encoding, set bit 22 to 1. 1198 Binary |= 1 << ARMII::AM3_I_BitShift; 1199 if (unsigned ImmOffs = ARM_AM::getAM3Offset(AM3Opc)) { 1200 // Set operands 1201 Binary |= (ImmOffs >> 4) << ARMII::ImmHiShift; // immedH 1202 Binary |= (ImmOffs & 0xF); // immedL 1203 } 1204 1205 emitWordLE(Binary); 1206} 1207 1208static unsigned getAddrModeUPBits(unsigned Mode) { 1209 unsigned Binary = 0; 1210 1211 // Set addressing mode by modifying bits U(23) and P(24) 1212 // IA - Increment after - bit U = 1 and bit P = 0 1213 // IB - Increment before - bit U = 1 and bit P = 1 1214 // DA - Decrement after - bit U = 0 and bit P = 0 1215 // DB - Decrement before - bit U = 0 and bit P = 1 1216 switch (Mode) { 1217 default: llvm_unreachable("Unknown addressing sub-mode!"); 1218 case ARM_AM::da: break; 1219 case ARM_AM::db: Binary |= 0x1 << ARMII::P_BitShift; break; 1220 case ARM_AM::ia: Binary |= 0x1 << ARMII::U_BitShift; break; 1221 case ARM_AM::ib: Binary |= 0x3 << ARMII::U_BitShift; break; 1222 } 1223 1224 return Binary; 1225} 1226 1227void ARMCodeEmitter::emitLoadStoreMultipleInstruction(const MachineInstr &MI) { 1228 const TargetInstrDesc &TID = MI.getDesc(); 1229 bool IsUpdating = (TID.TSFlags & ARMII::IndexModeMask) != 0; 1230 1231 // Part of binary is determined by TableGn. 1232 unsigned Binary = getBinaryCodeForInstr(MI); 1233 1234 // Set the conditional execution predicate 1235 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1236 1237 // Skip operand 0 of an instruction with base register update. 1238 unsigned OpIdx = 0; 1239 if (IsUpdating) 1240 ++OpIdx; 1241 1242 // Set base address operand 1243 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift; 1244 1245 // Set addressing mode by modifying bits U(23) and P(24) 1246 const MachineOperand &MO = MI.getOperand(OpIdx++); 1247 Binary |= getAddrModeUPBits(ARM_AM::getAM4SubMode(MO.getImm())); 1248 1249 // Set bit W(21) 1250 if (IsUpdating) 1251 Binary |= 0x1 << ARMII::W_BitShift; 1252 1253 // Set registers 1254 for (unsigned i = OpIdx+2, e = MI.getNumOperands(); i != e; ++i) { 1255 const MachineOperand &MO = MI.getOperand(i); 1256 if (!MO.isReg() || MO.isImplicit()) 1257 break; 1258 unsigned RegNum = getARMRegisterNumbering(MO.getReg()); 1259 assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()) && 1260 RegNum < 16); 1261 Binary |= 0x1 << RegNum; 1262 } 1263 1264 emitWordLE(Binary); 1265} 1266 1267void ARMCodeEmitter::emitMulFrmInstruction(const MachineInstr &MI) { 1268 const TargetInstrDesc &TID = MI.getDesc(); 1269 1270 // Part of binary is determined by TableGn. 1271 unsigned Binary = getBinaryCodeForInstr(MI); 1272 1273 // Set the conditional execution predicate 1274 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1275 1276 // Encode S bit if MI modifies CPSR. 1277 Binary |= getAddrModeSBit(MI, TID); 1278 1279 // 32x32->64bit operations have two destination registers. The number 1280 // of register definitions will tell us if that's what we're dealing with. 1281 unsigned OpIdx = 0; 1282 if (TID.getNumDefs() == 2) 1283 Binary |= getMachineOpValue (MI, OpIdx++) << ARMII::RegRdLoShift; 1284 1285 // Encode Rd 1286 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdHiShift; 1287 1288 // Encode Rm 1289 Binary |= getMachineOpValue(MI, OpIdx++); 1290 1291 // Encode Rs 1292 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRsShift; 1293 1294 // Many multiple instructions (e.g. MLA) have three src operands. Encode 1295 // it as Rn (for multiply, that's in the same offset as RdLo. 1296 if (TID.getNumOperands() > OpIdx && 1297 !TID.OpInfo[OpIdx].isPredicate() && 1298 !TID.OpInfo[OpIdx].isOptionalDef()) 1299 Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRdLoShift; 1300 1301 emitWordLE(Binary); 1302} 1303 1304void ARMCodeEmitter::emitExtendInstruction(const MachineInstr &MI) { 1305 const TargetInstrDesc &TID = MI.getDesc(); 1306 1307 // Part of binary is determined by TableGn. 1308 unsigned Binary = getBinaryCodeForInstr(MI); 1309 1310 // Set the conditional execution predicate 1311 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1312 1313 unsigned OpIdx = 0; 1314 1315 // Encode Rd 1316 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift; 1317 1318 const MachineOperand &MO1 = MI.getOperand(OpIdx++); 1319 const MachineOperand &MO2 = MI.getOperand(OpIdx); 1320 if (MO2.isReg()) { 1321 // Two register operand form. 1322 // Encode Rn. 1323 Binary |= getMachineOpValue(MI, MO1) << ARMII::RegRnShift; 1324 1325 // Encode Rm. 1326 Binary |= getMachineOpValue(MI, MO2); 1327 ++OpIdx; 1328 } else { 1329 Binary |= getMachineOpValue(MI, MO1); 1330 } 1331 1332 // Encode rot imm (0, 8, 16, or 24) if it has a rotate immediate operand. 1333 if (MI.getOperand(OpIdx).isImm() && 1334 !TID.OpInfo[OpIdx].isPredicate() && 1335 !TID.OpInfo[OpIdx].isOptionalDef()) 1336 Binary |= (getMachineOpValue(MI, OpIdx) / 8) << ARMII::ExtRotImmShift; 1337 1338 emitWordLE(Binary); 1339} 1340 1341void ARMCodeEmitter::emitMiscArithInstruction(const MachineInstr &MI) { 1342 const TargetInstrDesc &TID = MI.getDesc(); 1343 1344 // Part of binary is determined by TableGn. 1345 unsigned Binary = getBinaryCodeForInstr(MI); 1346 1347 // Set the conditional execution predicate 1348 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1349 1350 unsigned OpIdx = 0; 1351 1352 // Encode Rd 1353 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift; 1354 1355 const MachineOperand &MO = MI.getOperand(OpIdx++); 1356 if (OpIdx == TID.getNumOperands() || 1357 TID.OpInfo[OpIdx].isPredicate() || 1358 TID.OpInfo[OpIdx].isOptionalDef()) { 1359 // Encode Rm and it's done. 1360 Binary |= getMachineOpValue(MI, MO); 1361 emitWordLE(Binary); 1362 return; 1363 } 1364 1365 // Encode Rn. 1366 Binary |= getMachineOpValue(MI, MO) << ARMII::RegRnShift; 1367 1368 // Encode Rm. 1369 Binary |= getMachineOpValue(MI, OpIdx++); 1370 1371 // Encode shift_imm. 1372 unsigned ShiftAmt = MI.getOperand(OpIdx).getImm(); 1373 if (TID.Opcode == ARM::PKHTB) { 1374 assert(ShiftAmt != 0 && "PKHTB shift_imm is 0!"); 1375 if (ShiftAmt == 32) 1376 ShiftAmt = 0; 1377 } 1378 assert(ShiftAmt < 32 && "shift_imm range is 0 to 31!"); 1379 Binary |= ShiftAmt << ARMII::ShiftShift; 1380 1381 emitWordLE(Binary); 1382} 1383 1384void ARMCodeEmitter::emitSaturateInstruction(const MachineInstr &MI) { 1385 const TargetInstrDesc &TID = MI.getDesc(); 1386 1387 // Part of binary is determined by TableGen. 1388 unsigned Binary = getBinaryCodeForInstr(MI); 1389 1390 // Set the conditional execution predicate 1391 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1392 1393 // Encode Rd 1394 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift; 1395 1396 // Encode saturate bit position. 1397 unsigned Pos = MI.getOperand(1).getImm(); 1398 if (TID.Opcode == ARM::SSAT || TID.Opcode == ARM::SSAT16) 1399 Pos -= 1; 1400 assert((Pos < 16 || (Pos < 32 && 1401 TID.Opcode != ARM::SSAT16 && 1402 TID.Opcode != ARM::USAT16)) && 1403 "saturate bit position out of range"); 1404 Binary |= Pos << 16; 1405 1406 // Encode Rm 1407 Binary |= getMachineOpValue(MI, 2); 1408 1409 // Encode shift_imm. 1410 if (TID.getNumOperands() == 4) { 1411 unsigned ShiftOp = MI.getOperand(3).getImm(); 1412 ARM_AM::ShiftOpc Opc = ARM_AM::getSORegShOp(ShiftOp); 1413 if (Opc == ARM_AM::asr) 1414 Binary |= (1 << 6); 1415 unsigned ShiftAmt = MI.getOperand(3).getImm(); 1416 if (ShiftAmt == 32 && Opc == ARM_AM::asr) 1417 ShiftAmt = 0; 1418 assert(ShiftAmt < 32 && "shift_imm range is 0 to 31!"); 1419 Binary |= ShiftAmt << ARMII::ShiftShift; 1420 } 1421 1422 emitWordLE(Binary); 1423} 1424 1425void ARMCodeEmitter::emitBranchInstruction(const MachineInstr &MI) { 1426 const TargetInstrDesc &TID = MI.getDesc(); 1427 1428 if (TID.Opcode == ARM::TPsoft) { 1429 llvm_unreachable("ARM::TPsoft FIXME"); // FIXME 1430 } 1431 1432 // Part of binary is determined by TableGn. 1433 unsigned Binary = getBinaryCodeForInstr(MI); 1434 1435 // Set the conditional execution predicate 1436 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1437 1438 // Set signed_immed_24 field 1439 Binary |= getMachineOpValue(MI, 0); 1440 1441 emitWordLE(Binary); 1442} 1443 1444void ARMCodeEmitter::emitInlineJumpTable(unsigned JTIndex) { 1445 // Remember the base address of the inline jump table. 1446 uintptr_t JTBase = MCE.getCurrentPCValue(); 1447 JTI->addJumpTableBaseAddr(JTIndex, JTBase); 1448 DEBUG(errs() << " ** Jump Table #" << JTIndex << " @ " << (void*)JTBase 1449 << '\n'); 1450 1451 // Now emit the jump table entries. 1452 const std::vector<MachineBasicBlock*> &MBBs = (*MJTEs)[JTIndex].MBBs; 1453 for (unsigned i = 0, e = MBBs.size(); i != e; ++i) { 1454 if (IsPIC) 1455 // DestBB address - JT base. 1456 emitMachineBasicBlock(MBBs[i], ARM::reloc_arm_pic_jt, JTBase); 1457 else 1458 // Absolute DestBB address. 1459 emitMachineBasicBlock(MBBs[i], ARM::reloc_arm_absolute); 1460 emitWordLE(0); 1461 } 1462} 1463 1464void ARMCodeEmitter::emitMiscBranchInstruction(const MachineInstr &MI) { 1465 const TargetInstrDesc &TID = MI.getDesc(); 1466 1467 // Handle jump tables. 1468 if (TID.Opcode == ARM::BR_JTr || TID.Opcode == ARM::BR_JTadd) { 1469 // First emit a ldr pc, [] instruction. 1470 emitDataProcessingInstruction(MI, ARM::PC); 1471 1472 // Then emit the inline jump table. 1473 unsigned JTIndex = 1474 (TID.Opcode == ARM::BR_JTr) 1475 ? MI.getOperand(1).getIndex() : MI.getOperand(2).getIndex(); 1476 emitInlineJumpTable(JTIndex); 1477 return; 1478 } else if (TID.Opcode == ARM::BR_JTm) { 1479 // First emit a ldr pc, [] instruction. 1480 emitLoadStoreInstruction(MI, ARM::PC); 1481 1482 // Then emit the inline jump table. 1483 emitInlineJumpTable(MI.getOperand(3).getIndex()); 1484 return; 1485 } 1486 1487 // Part of binary is determined by TableGn. 1488 unsigned Binary = getBinaryCodeForInstr(MI); 1489 1490 // Set the conditional execution predicate 1491 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1492 1493 if (TID.Opcode == ARM::BX_RET || TID.Opcode == ARM::MOVPCLR) 1494 // The return register is LR. 1495 Binary |= getARMRegisterNumbering(ARM::LR); 1496 else 1497 // otherwise, set the return register 1498 Binary |= getMachineOpValue(MI, 0); 1499 1500 emitWordLE(Binary); 1501} 1502 1503static unsigned encodeVFPRd(const MachineInstr &MI, unsigned OpIdx) { 1504 unsigned RegD = MI.getOperand(OpIdx).getReg(); 1505 unsigned Binary = 0; 1506 bool isSPVFP = ARM::SPRRegisterClass->contains(RegD); 1507 RegD = getARMRegisterNumbering(RegD); 1508 if (!isSPVFP) { 1509 Binary |= (RegD & 0x0F) << ARMII::RegRdShift; 1510 Binary |= ((RegD & 0x10) >> 4) << ARMII::D_BitShift; 1511 } else { 1512 Binary |= ((RegD & 0x1E) >> 1) << ARMII::RegRdShift; 1513 Binary |= (RegD & 0x01) << ARMII::D_BitShift; 1514 } 1515 return Binary; 1516} 1517 1518static unsigned encodeVFPRn(const MachineInstr &MI, unsigned OpIdx) { 1519 unsigned RegN = MI.getOperand(OpIdx).getReg(); 1520 unsigned Binary = 0; 1521 bool isSPVFP = ARM::SPRRegisterClass->contains(RegN); 1522 RegN = getARMRegisterNumbering(RegN); 1523 if (!isSPVFP) { 1524 Binary |= (RegN & 0x0F) << ARMII::RegRnShift; 1525 Binary |= ((RegN & 0x10) >> 4) << ARMII::N_BitShift; 1526 } else { 1527 Binary |= ((RegN & 0x1E) >> 1) << ARMII::RegRnShift; 1528 Binary |= (RegN & 0x01) << ARMII::N_BitShift; 1529 } 1530 return Binary; 1531} 1532 1533static unsigned encodeVFPRm(const MachineInstr &MI, unsigned OpIdx) { 1534 unsigned RegM = MI.getOperand(OpIdx).getReg(); 1535 unsigned Binary = 0; 1536 bool isSPVFP = ARM::SPRRegisterClass->contains(RegM); 1537 RegM = getARMRegisterNumbering(RegM); 1538 if (!isSPVFP) { 1539 Binary |= (RegM & 0x0F); 1540 Binary |= ((RegM & 0x10) >> 4) << ARMII::M_BitShift; 1541 } else { 1542 Binary |= ((RegM & 0x1E) >> 1); 1543 Binary |= (RegM & 0x01) << ARMII::M_BitShift; 1544 } 1545 return Binary; 1546} 1547 1548void ARMCodeEmitter::emitVFPArithInstruction(const MachineInstr &MI) { 1549 const TargetInstrDesc &TID = MI.getDesc(); 1550 1551 // Part of binary is determined by TableGn. 1552 unsigned Binary = getBinaryCodeForInstr(MI); 1553 1554 // Set the conditional execution predicate 1555 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1556 1557 unsigned OpIdx = 0; 1558 assert((Binary & ARMII::D_BitShift) == 0 && 1559 (Binary & ARMII::N_BitShift) == 0 && 1560 (Binary & ARMII::M_BitShift) == 0 && "VFP encoding bug!"); 1561 1562 // Encode Dd / Sd. 1563 Binary |= encodeVFPRd(MI, OpIdx++); 1564 1565 // If this is a two-address operand, skip it, e.g. FMACD. 1566 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1) 1567 ++OpIdx; 1568 1569 // Encode Dn / Sn. 1570 if ((TID.TSFlags & ARMII::FormMask) == ARMII::VFPBinaryFrm) 1571 Binary |= encodeVFPRn(MI, OpIdx++); 1572 1573 if (OpIdx == TID.getNumOperands() || 1574 TID.OpInfo[OpIdx].isPredicate() || 1575 TID.OpInfo[OpIdx].isOptionalDef()) { 1576 // FCMPEZD etc. has only one operand. 1577 emitWordLE(Binary); 1578 return; 1579 } 1580 1581 // Encode Dm / Sm. 1582 Binary |= encodeVFPRm(MI, OpIdx); 1583 1584 emitWordLE(Binary); 1585} 1586 1587void ARMCodeEmitter::emitVFPConversionInstruction(const MachineInstr &MI) { 1588 const TargetInstrDesc &TID = MI.getDesc(); 1589 unsigned Form = TID.TSFlags & ARMII::FormMask; 1590 1591 // Part of binary is determined by TableGn. 1592 unsigned Binary = getBinaryCodeForInstr(MI); 1593 1594 // Set the conditional execution predicate 1595 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1596 1597 switch (Form) { 1598 default: break; 1599 case ARMII::VFPConv1Frm: 1600 case ARMII::VFPConv2Frm: 1601 case ARMII::VFPConv3Frm: 1602 // Encode Dd / Sd. 1603 Binary |= encodeVFPRd(MI, 0); 1604 break; 1605 case ARMII::VFPConv4Frm: 1606 // Encode Dn / Sn. 1607 Binary |= encodeVFPRn(MI, 0); 1608 break; 1609 case ARMII::VFPConv5Frm: 1610 // Encode Dm / Sm. 1611 Binary |= encodeVFPRm(MI, 0); 1612 break; 1613 } 1614 1615 switch (Form) { 1616 default: break; 1617 case ARMII::VFPConv1Frm: 1618 // Encode Dm / Sm. 1619 Binary |= encodeVFPRm(MI, 1); 1620 break; 1621 case ARMII::VFPConv2Frm: 1622 case ARMII::VFPConv3Frm: 1623 // Encode Dn / Sn. 1624 Binary |= encodeVFPRn(MI, 1); 1625 break; 1626 case ARMII::VFPConv4Frm: 1627 case ARMII::VFPConv5Frm: 1628 // Encode Dd / Sd. 1629 Binary |= encodeVFPRd(MI, 1); 1630 break; 1631 } 1632 1633 if (Form == ARMII::VFPConv5Frm) 1634 // Encode Dn / Sn. 1635 Binary |= encodeVFPRn(MI, 2); 1636 else if (Form == ARMII::VFPConv3Frm) 1637 // Encode Dm / Sm. 1638 Binary |= encodeVFPRm(MI, 2); 1639 1640 emitWordLE(Binary); 1641} 1642 1643void ARMCodeEmitter::emitVFPLoadStoreInstruction(const MachineInstr &MI) { 1644 // Part of binary is determined by TableGn. 1645 unsigned Binary = getBinaryCodeForInstr(MI); 1646 1647 // Set the conditional execution predicate 1648 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1649 1650 unsigned OpIdx = 0; 1651 1652 // Encode Dd / Sd. 1653 Binary |= encodeVFPRd(MI, OpIdx++); 1654 1655 // Encode address base. 1656 const MachineOperand &Base = MI.getOperand(OpIdx++); 1657 Binary |= getMachineOpValue(MI, Base) << ARMII::RegRnShift; 1658 1659 // If there is a non-zero immediate offset, encode it. 1660 if (Base.isReg()) { 1661 const MachineOperand &Offset = MI.getOperand(OpIdx); 1662 if (unsigned ImmOffs = ARM_AM::getAM5Offset(Offset.getImm())) { 1663 if (ARM_AM::getAM5Op(Offset.getImm()) == ARM_AM::add) 1664 Binary |= 1 << ARMII::U_BitShift; 1665 Binary |= ImmOffs; 1666 emitWordLE(Binary); 1667 return; 1668 } 1669 } 1670 1671 // If immediate offset is omitted, default to +0. 1672 Binary |= 1 << ARMII::U_BitShift; 1673 1674 emitWordLE(Binary); 1675} 1676 1677void 1678ARMCodeEmitter::emitVFPLoadStoreMultipleInstruction(const MachineInstr &MI) { 1679 const TargetInstrDesc &TID = MI.getDesc(); 1680 bool IsUpdating = (TID.TSFlags & ARMII::IndexModeMask) != 0; 1681 1682 // Part of binary is determined by TableGn. 1683 unsigned Binary = getBinaryCodeForInstr(MI); 1684 1685 // Set the conditional execution predicate 1686 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1687 1688 // Skip operand 0 of an instruction with base register update. 1689 unsigned OpIdx = 0; 1690 if (IsUpdating) 1691 ++OpIdx; 1692 1693 // Set base address operand 1694 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift; 1695 1696 // Set addressing mode by modifying bits U(23) and P(24) 1697 const MachineOperand &MO = MI.getOperand(OpIdx++); 1698 Binary |= getAddrModeUPBits(ARM_AM::getAM4SubMode(MO.getImm())); 1699 1700 // Set bit W(21) 1701 if (IsUpdating) 1702 Binary |= 0x1 << ARMII::W_BitShift; 1703 1704 // First register is encoded in Dd. 1705 Binary |= encodeVFPRd(MI, OpIdx+2); 1706 1707 // Count the number of registers. 1708 unsigned NumRegs = 1; 1709 for (unsigned i = OpIdx+3, e = MI.getNumOperands(); i != e; ++i) { 1710 const MachineOperand &MO = MI.getOperand(i); 1711 if (!MO.isReg() || MO.isImplicit()) 1712 break; 1713 ++NumRegs; 1714 } 1715 // Bit 8 will be set if <list> is consecutive 64-bit registers (e.g., D0) 1716 // Otherwise, it will be 0, in the case of 32-bit registers. 1717 if(Binary & 0x100) 1718 Binary |= NumRegs * 2; 1719 else 1720 Binary |= NumRegs; 1721 1722 emitWordLE(Binary); 1723} 1724 1725static unsigned encodeNEONRd(const MachineInstr &MI, unsigned OpIdx) { 1726 unsigned RegD = MI.getOperand(OpIdx).getReg(); 1727 unsigned Binary = 0; 1728 RegD = getARMRegisterNumbering(RegD); 1729 Binary |= (RegD & 0xf) << ARMII::RegRdShift; 1730 Binary |= ((RegD >> 4) & 1) << ARMII::D_BitShift; 1731 return Binary; 1732} 1733 1734static unsigned encodeNEONRn(const MachineInstr &MI, unsigned OpIdx) { 1735 unsigned RegN = MI.getOperand(OpIdx).getReg(); 1736 unsigned Binary = 0; 1737 RegN = getARMRegisterNumbering(RegN); 1738 Binary |= (RegN & 0xf) << ARMII::RegRnShift; 1739 Binary |= ((RegN >> 4) & 1) << ARMII::N_BitShift; 1740 return Binary; 1741} 1742 1743static unsigned encodeNEONRm(const MachineInstr &MI, unsigned OpIdx) { 1744 unsigned RegM = MI.getOperand(OpIdx).getReg(); 1745 unsigned Binary = 0; 1746 RegM = getARMRegisterNumbering(RegM); 1747 Binary |= (RegM & 0xf); 1748 Binary |= ((RegM >> 4) & 1) << ARMII::M_BitShift; 1749 return Binary; 1750} 1751 1752/// convertNEONDataProcToThumb - Convert the ARM mode encoding for a NEON 1753/// data-processing instruction to the corresponding Thumb encoding. 1754static unsigned convertNEONDataProcToThumb(unsigned Binary) { 1755 assert((Binary & 0xfe000000) == 0xf2000000 && 1756 "not an ARM NEON data-processing instruction"); 1757 unsigned UBit = (Binary >> 24) & 1; 1758 return 0xef000000 | (UBit << 28) | (Binary & 0xffffff); 1759} 1760 1761void ARMCodeEmitter::emitNEONLaneInstruction(const MachineInstr &MI) { 1762 unsigned Binary = getBinaryCodeForInstr(MI); 1763 1764 unsigned RegTOpIdx, RegNOpIdx, LnOpIdx; 1765 const TargetInstrDesc &TID = MI.getDesc(); 1766 if ((TID.TSFlags & ARMII::FormMask) == ARMII::NGetLnFrm) { 1767 RegTOpIdx = 0; 1768 RegNOpIdx = 1; 1769 LnOpIdx = 2; 1770 } else { // ARMII::NSetLnFrm 1771 RegTOpIdx = 2; 1772 RegNOpIdx = 0; 1773 LnOpIdx = 3; 1774 } 1775 1776 // Set the conditional execution predicate 1777 Binary |= (IsThumb ? ARMCC::AL : II->getPredicate(&MI)) << ARMII::CondShift; 1778 1779 unsigned RegT = MI.getOperand(RegTOpIdx).getReg(); 1780 RegT = getARMRegisterNumbering(RegT); 1781 Binary |= (RegT << ARMII::RegRdShift); 1782 Binary |= encodeNEONRn(MI, RegNOpIdx); 1783 1784 unsigned LaneShift; 1785 if ((Binary & (1 << 22)) != 0) 1786 LaneShift = 0; // 8-bit elements 1787 else if ((Binary & (1 << 5)) != 0) 1788 LaneShift = 1; // 16-bit elements 1789 else 1790 LaneShift = 2; // 32-bit elements 1791 1792 unsigned Lane = MI.getOperand(LnOpIdx).getImm() << LaneShift; 1793 unsigned Opc1 = Lane >> 2; 1794 unsigned Opc2 = Lane & 3; 1795 assert((Opc1 & 3) == 0 && "out-of-range lane number operand"); 1796 Binary |= (Opc1 << 21); 1797 Binary |= (Opc2 << 5); 1798 1799 emitWordLE(Binary); 1800} 1801 1802void ARMCodeEmitter::emitNEONDupInstruction(const MachineInstr &MI) { 1803 unsigned Binary = getBinaryCodeForInstr(MI); 1804 1805 // Set the conditional execution predicate 1806 Binary |= (IsThumb ? ARMCC::AL : II->getPredicate(&MI)) << ARMII::CondShift; 1807 1808 unsigned RegT = MI.getOperand(1).getReg(); 1809 RegT = getARMRegisterNumbering(RegT); 1810 Binary |= (RegT << ARMII::RegRdShift); 1811 Binary |= encodeNEONRn(MI, 0); 1812 emitWordLE(Binary); 1813} 1814 1815void ARMCodeEmitter::emitNEON1RegModImmInstruction(const MachineInstr &MI) { 1816 unsigned Binary = getBinaryCodeForInstr(MI); 1817 // Destination register is encoded in Dd. 1818 Binary |= encodeNEONRd(MI, 0); 1819 // Immediate fields: Op, Cmode, I, Imm3, Imm4 1820 unsigned Imm = MI.getOperand(1).getImm(); 1821 unsigned Op = (Imm >> 12) & 1; 1822 unsigned Cmode = (Imm >> 8) & 0xf; 1823 unsigned I = (Imm >> 7) & 1; 1824 unsigned Imm3 = (Imm >> 4) & 0x7; 1825 unsigned Imm4 = Imm & 0xf; 1826 Binary |= (I << 24) | (Imm3 << 16) | (Cmode << 8) | (Op << 5) | Imm4; 1827 if (IsThumb) 1828 Binary = convertNEONDataProcToThumb(Binary); 1829 emitWordLE(Binary); 1830} 1831 1832void ARMCodeEmitter::emitNEON2RegInstruction(const MachineInstr &MI) { 1833 const TargetInstrDesc &TID = MI.getDesc(); 1834 unsigned Binary = getBinaryCodeForInstr(MI); 1835 // Destination register is encoded in Dd; source register in Dm. 1836 unsigned OpIdx = 0; 1837 Binary |= encodeNEONRd(MI, OpIdx++); 1838 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1) 1839 ++OpIdx; 1840 Binary |= encodeNEONRm(MI, OpIdx); 1841 if (IsThumb) 1842 Binary = convertNEONDataProcToThumb(Binary); 1843 // FIXME: This does not handle VDUPfdf or VDUPfqf. 1844 emitWordLE(Binary); 1845} 1846 1847void ARMCodeEmitter::emitNEON3RegInstruction(const MachineInstr &MI) { 1848 const TargetInstrDesc &TID = MI.getDesc(); 1849 unsigned Binary = getBinaryCodeForInstr(MI); 1850 // Destination register is encoded in Dd; source registers in Dn and Dm. 1851 unsigned OpIdx = 0; 1852 Binary |= encodeNEONRd(MI, OpIdx++); 1853 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1) 1854 ++OpIdx; 1855 Binary |= encodeNEONRn(MI, OpIdx++); 1856 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1) 1857 ++OpIdx; 1858 Binary |= encodeNEONRm(MI, OpIdx); 1859 if (IsThumb) 1860 Binary = convertNEONDataProcToThumb(Binary); 1861 // FIXME: This does not handle VMOVDneon or VMOVQ. 1862 emitWordLE(Binary); 1863} 1864 1865#include "ARMGenCodeEmitter.inc" 1866