ARMCodeEmitter.cpp revision 570a9226913ebe1af04832b8fb3273c70b4ee152
1//===-- ARM/ARMCodeEmitter.cpp - Convert ARM code to machine code ---------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the pass that transforms the ARM machine instructions into 11// relocatable machine code. 12// 13//===----------------------------------------------------------------------===// 14 15#define DEBUG_TYPE "jit" 16#include "ARM.h" 17#include "ARMAddressingModes.h" 18#include "ARMConstantPoolValue.h" 19#include "ARMInstrInfo.h" 20#include "ARMRelocations.h" 21#include "ARMSubtarget.h" 22#include "ARMTargetMachine.h" 23#include "llvm/Constants.h" 24#include "llvm/DerivedTypes.h" 25#include "llvm/Function.h" 26#include "llvm/PassManager.h" 27#include "llvm/CodeGen/JITCodeEmitter.h" 28#include "llvm/CodeGen/MachineConstantPool.h" 29#include "llvm/CodeGen/MachineFunctionPass.h" 30#include "llvm/CodeGen/MachineInstr.h" 31#include "llvm/CodeGen/MachineJumpTableInfo.h" 32#include "llvm/CodeGen/MachineModuleInfo.h" 33#include "llvm/CodeGen/Passes.h" 34#include "llvm/ADT/Statistic.h" 35#include "llvm/Support/Debug.h" 36#include "llvm/Support/ErrorHandling.h" 37#include "llvm/Support/raw_ostream.h" 38#ifndef NDEBUG 39#include <iomanip> 40#endif 41using namespace llvm; 42 43STATISTIC(NumEmitted, "Number of machine instructions emitted"); 44 45namespace { 46 47 class ARMCodeEmitter : public MachineFunctionPass { 48 ARMJITInfo *JTI; 49 const ARMInstrInfo *II; 50 const TargetData *TD; 51 const ARMSubtarget *Subtarget; 52 TargetMachine &TM; 53 JITCodeEmitter &MCE; 54 MachineModuleInfo *MMI; 55 const std::vector<MachineConstantPoolEntry> *MCPEs; 56 const std::vector<MachineJumpTableEntry> *MJTEs; 57 bool IsPIC; 58 bool IsThumb; 59 60 void getAnalysisUsage(AnalysisUsage &AU) const { 61 AU.addRequired<MachineModuleInfo>(); 62 MachineFunctionPass::getAnalysisUsage(AU); 63 } 64 65 static char ID; 66 public: 67 ARMCodeEmitter(TargetMachine &tm, JITCodeEmitter &mce) 68 : MachineFunctionPass(ID), JTI(0), 69 II((const ARMInstrInfo *)tm.getInstrInfo()), 70 TD(tm.getTargetData()), TM(tm), 71 MCE(mce), MCPEs(0), MJTEs(0), 72 IsPIC(TM.getRelocationModel() == Reloc::PIC_), IsThumb(false) {} 73 74 /// getBinaryCodeForInstr - This function, generated by the 75 /// CodeEmitterGenerator using TableGen, produces the binary encoding for 76 /// machine instructions. 77 unsigned getBinaryCodeForInstr(const MachineInstr &MI) const; 78 79 bool runOnMachineFunction(MachineFunction &MF); 80 81 virtual const char *getPassName() const { 82 return "ARM Machine Code Emitter"; 83 } 84 85 void emitInstruction(const MachineInstr &MI); 86 87 private: 88 89 void emitWordLE(unsigned Binary); 90 void emitDWordLE(uint64_t Binary); 91 void emitConstPoolInstruction(const MachineInstr &MI); 92 void emitMOVi32immInstruction(const MachineInstr &MI); 93 void emitMOVi2piecesInstruction(const MachineInstr &MI); 94 void emitLEApcrelJTInstruction(const MachineInstr &MI); 95 void emitPseudoMoveInstruction(const MachineInstr &MI); 96 void addPCLabel(unsigned LabelID); 97 void emitPseudoInstruction(const MachineInstr &MI); 98 unsigned getMachineSoRegOpValue(const MachineInstr &MI, 99 const TargetInstrDesc &TID, 100 const MachineOperand &MO, 101 unsigned OpIdx); 102 103 unsigned getMachineSoImmOpValue(unsigned SoImm); 104 unsigned getAddrModeSBit(const MachineInstr &MI, 105 const TargetInstrDesc &TID) const; 106 107 void emitDataProcessingInstruction(const MachineInstr &MI, 108 unsigned ImplicitRd = 0, 109 unsigned ImplicitRn = 0); 110 111 void emitLoadStoreInstruction(const MachineInstr &MI, 112 unsigned ImplicitRd = 0, 113 unsigned ImplicitRn = 0); 114 115 void emitMiscLoadStoreInstruction(const MachineInstr &MI, 116 unsigned ImplicitRn = 0); 117 118 void emitLoadStoreMultipleInstruction(const MachineInstr &MI); 119 120 void emitMulFrmInstruction(const MachineInstr &MI); 121 122 void emitExtendInstruction(const MachineInstr &MI); 123 124 void emitMiscArithInstruction(const MachineInstr &MI); 125 126 void emitSaturateInstruction(const MachineInstr &MI); 127 128 void emitBranchInstruction(const MachineInstr &MI); 129 130 void emitInlineJumpTable(unsigned JTIndex); 131 132 void emitMiscBranchInstruction(const MachineInstr &MI); 133 134 void emitVFPArithInstruction(const MachineInstr &MI); 135 136 void emitVFPConversionInstruction(const MachineInstr &MI); 137 138 void emitVFPLoadStoreInstruction(const MachineInstr &MI); 139 140 void emitVFPLoadStoreMultipleInstruction(const MachineInstr &MI); 141 142 void emitNEONLaneInstruction(const MachineInstr &MI); 143 void emitNEONDupInstruction(const MachineInstr &MI); 144 void emitNEON1RegModImmInstruction(const MachineInstr &MI); 145 void emitNEON2RegInstruction(const MachineInstr &MI); 146 void emitNEON3RegInstruction(const MachineInstr &MI); 147 148 /// getMachineOpValue - Return binary encoding of operand. If the machine 149 /// operand requires relocation, record the relocation and return zero. 150 unsigned getMachineOpValue(const MachineInstr &MI, 151 const MachineOperand &MO) const; 152 unsigned getMachineOpValue(const MachineInstr &MI, unsigned OpIdx) const { 153 return getMachineOpValue(MI, MI.getOperand(OpIdx)); 154 } 155 156 // FIXME: The legacy JIT ARMCodeEmitter doesn't rely on the the 157 // TableGen'erated getBinaryCodeForInstr() function to encode any 158 // operand values, instead querying getMachineOpValue() directly for 159 // each operand it needs to encode. Thus, any of the new encoder 160 // helper functions can simply return 0 as the values the return 161 // are already handled elsewhere. They are placeholders to allow this 162 // encoder to continue to function until the MC encoder is sufficiently 163 // far along that this one can be eliminated entirely. 164 unsigned getCCOutOpValue(const MachineInstr &MI, unsigned Op) 165 const { return 0; } 166 unsigned getSOImmOpValue(const MachineInstr &MI, unsigned Op) 167 const { return 0; } 168 unsigned getSORegOpValue(const MachineInstr &MI, unsigned Op) 169 const { return 0; } 170 unsigned getRotImmOpValue(const MachineInstr &MI, unsigned Op) 171 const { return 0; } 172 unsigned getImmMinusOneOpValue(const MachineInstr &MI, unsigned Op) 173 const { return 0; } 174 unsigned getAddrMode6AddressOpValue(const MachineInstr &MI, unsigned Op) 175 const { return 0; } 176 unsigned getAddrMode6OffsetOpValue(const MachineInstr &MI, unsigned Op) 177 const { return 0; } 178 unsigned getBitfieldInvertedMaskOpValue(const MachineInstr &MI, 179 unsigned Op) const { return 0; } 180 uint32_t getLdStmModeOpValue(const MachineInstr &MI, unsigned OpIdx) 181 const {return 0; } 182 uint32_t getLdStSORegOpValue(const MachineInstr &MI, unsigned OpIdx) 183 const { return 0; } 184 185 unsigned getAddrModeImm12OpValue(const MachineInstr &MI, unsigned Op) 186 const { 187 // {17-13} = reg 188 // {12} = (U)nsigned (add == '1', sub == '0') 189 // {11-0} = imm12 190 const MachineOperand &MO = MI.getOperand(Op); 191 const MachineOperand &MO1 = MI.getOperand(Op + 1); 192 if (!MO.isReg()) { 193 emitConstPoolAddress(MO.getIndex(), ARM::reloc_arm_cp_entry); 194 return 0; 195 } 196 unsigned Reg = getARMRegisterNumbering(MO.getReg()); 197 int32_t Imm12 = MO1.getImm(); 198 uint32_t Binary; 199 Binary = Imm12 & 0xfff; 200 if (Imm12 >= 0) 201 Binary |= (1 << 12); 202 Binary |= (Reg << 13); 203 return Binary; 204 } 205 uint32_t getAddrMode3OpValue(const MachineInstr &MI, unsigned Op) const 206 { return 0; } 207 uint32_t getAddrMode5OpValue(const MachineInstr &MI, unsigned Op) const { 208 // {12-9} = reg 209 // {8} = (U)nsigned (add == '1', sub == '0') 210 // {7-0} = imm12 211 const MachineOperand &MO = MI.getOperand(Op); 212 const MachineOperand &MO1 = MI.getOperand(Op + 1); 213 if (!MO.isReg()) { 214 emitConstPoolAddress(MO.getIndex(), ARM::reloc_arm_cp_entry); 215 return 0; 216 } 217 unsigned Reg = getARMRegisterNumbering(MO.getReg()); 218 int32_t Imm8 = MO1.getImm(); 219 uint32_t Binary; 220 Binary = Imm8 & 0xff; 221 if (Imm8 >= 0) 222 Binary |= (1 << 8); 223 Binary |= (Reg << 9); 224 return Binary; 225 } 226 unsigned getNEONVcvtImm32OpValue(const MachineInstr &MI, unsigned Op) 227 const { return 0; } 228 229 unsigned getRegisterListOpValue(const MachineInstr &MI, unsigned Op) 230 const { return 0; } 231 232 /// getMovi32Value - Return binary encoding of operand for movw/movt. If the 233 /// machine operand requires relocation, record the relocation and return 234 /// zero. 235 unsigned getMovi32Value(const MachineInstr &MI,const MachineOperand &MO, 236 unsigned Reloc); 237 238 /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value. 239 /// 240 unsigned getShiftOp(unsigned Imm) const ; 241 242 /// Routines that handle operands which add machine relocations which are 243 /// fixed up by the relocation stage. 244 void emitGlobalAddress(const GlobalValue *GV, unsigned Reloc, 245 bool MayNeedFarStub, bool Indirect, 246 intptr_t ACPV = 0) const; 247 void emitExternalSymbolAddress(const char *ES, unsigned Reloc) const; 248 void emitConstPoolAddress(unsigned CPI, unsigned Reloc) const; 249 void emitJumpTableAddress(unsigned JTIndex, unsigned Reloc) const; 250 void emitMachineBasicBlock(MachineBasicBlock *BB, unsigned Reloc, 251 intptr_t JTBase = 0) const; 252 }; 253} 254 255char ARMCodeEmitter::ID = 0; 256 257/// createARMJITCodeEmitterPass - Return a pass that emits the collected ARM 258/// code to the specified MCE object. 259FunctionPass *llvm::createARMJITCodeEmitterPass(ARMBaseTargetMachine &TM, 260 JITCodeEmitter &JCE) { 261 return new ARMCodeEmitter(TM, JCE); 262} 263 264bool ARMCodeEmitter::runOnMachineFunction(MachineFunction &MF) { 265 assert((MF.getTarget().getRelocationModel() != Reloc::Default || 266 MF.getTarget().getRelocationModel() != Reloc::Static) && 267 "JIT relocation model must be set to static or default!"); 268 JTI = ((ARMTargetMachine &)MF.getTarget()).getJITInfo(); 269 II = ((const ARMTargetMachine &)MF.getTarget()).getInstrInfo(); 270 TD = ((const ARMTargetMachine &)MF.getTarget()).getTargetData(); 271 Subtarget = &TM.getSubtarget<ARMSubtarget>(); 272 MCPEs = &MF.getConstantPool()->getConstants(); 273 MJTEs = 0; 274 if (MF.getJumpTableInfo()) MJTEs = &MF.getJumpTableInfo()->getJumpTables(); 275 IsPIC = TM.getRelocationModel() == Reloc::PIC_; 276 IsThumb = MF.getInfo<ARMFunctionInfo>()->isThumbFunction(); 277 JTI->Initialize(MF, IsPIC); 278 MMI = &getAnalysis<MachineModuleInfo>(); 279 MCE.setModuleInfo(MMI); 280 281 do { 282 DEBUG(errs() << "JITTing function '" 283 << MF.getFunction()->getName() << "'\n"); 284 MCE.startFunction(MF); 285 for (MachineFunction::iterator MBB = MF.begin(), E = MF.end(); 286 MBB != E; ++MBB) { 287 MCE.StartMachineBasicBlock(MBB); 288 for (MachineBasicBlock::const_iterator I = MBB->begin(), E = MBB->end(); 289 I != E; ++I) 290 emitInstruction(*I); 291 } 292 } while (MCE.finishFunction(MF)); 293 294 return false; 295} 296 297/// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value. 298/// 299unsigned ARMCodeEmitter::getShiftOp(unsigned Imm) const { 300 switch (ARM_AM::getAM2ShiftOpc(Imm)) { 301 default: llvm_unreachable("Unknown shift opc!"); 302 case ARM_AM::asr: return 2; 303 case ARM_AM::lsl: return 0; 304 case ARM_AM::lsr: return 1; 305 case ARM_AM::ror: 306 case ARM_AM::rrx: return 3; 307 } 308 return 0; 309} 310 311/// getMovi32Value - Return binary encoding of operand for movw/movt. If the 312/// machine operand requires relocation, record the relocation and return zero. 313unsigned ARMCodeEmitter::getMovi32Value(const MachineInstr &MI, 314 const MachineOperand &MO, 315 unsigned Reloc) { 316 assert(((Reloc == ARM::reloc_arm_movt) || (Reloc == ARM::reloc_arm_movw)) 317 && "Relocation to this function should be for movt or movw"); 318 319 if (MO.isImm()) 320 return static_cast<unsigned>(MO.getImm()); 321 else if (MO.isGlobal()) 322 emitGlobalAddress(MO.getGlobal(), Reloc, true, false); 323 else if (MO.isSymbol()) 324 emitExternalSymbolAddress(MO.getSymbolName(), Reloc); 325 else if (MO.isMBB()) 326 emitMachineBasicBlock(MO.getMBB(), Reloc); 327 else { 328#ifndef NDEBUG 329 errs() << MO; 330#endif 331 llvm_unreachable("Unsupported operand type for movw/movt"); 332 } 333 return 0; 334} 335 336/// getMachineOpValue - Return binary encoding of operand. If the machine 337/// operand requires relocation, record the relocation and return zero. 338unsigned ARMCodeEmitter::getMachineOpValue(const MachineInstr &MI, 339 const MachineOperand &MO) const { 340 if (MO.isReg()) 341 return getARMRegisterNumbering(MO.getReg()); 342 else if (MO.isImm()) 343 return static_cast<unsigned>(MO.getImm()); 344 else if (MO.isGlobal()) 345 emitGlobalAddress(MO.getGlobal(), ARM::reloc_arm_branch, true, false); 346 else if (MO.isSymbol()) 347 emitExternalSymbolAddress(MO.getSymbolName(), ARM::reloc_arm_branch); 348 else if (MO.isCPI()) { 349 const TargetInstrDesc &TID = MI.getDesc(); 350 // For VFP load, the immediate offset is multiplied by 4. 351 unsigned Reloc = ((TID.TSFlags & ARMII::FormMask) == ARMII::VFPLdStFrm) 352 ? ARM::reloc_arm_vfp_cp_entry : ARM::reloc_arm_cp_entry; 353 emitConstPoolAddress(MO.getIndex(), Reloc); 354 } else if (MO.isJTI()) 355 emitJumpTableAddress(MO.getIndex(), ARM::reloc_arm_relative); 356 else if (MO.isMBB()) 357 emitMachineBasicBlock(MO.getMBB(), ARM::reloc_arm_branch); 358 else { 359#ifndef NDEBUG 360 errs() << MO; 361#endif 362 llvm_unreachable(0); 363 } 364 return 0; 365} 366 367/// emitGlobalAddress - Emit the specified address to the code stream. 368/// 369void ARMCodeEmitter::emitGlobalAddress(const GlobalValue *GV, unsigned Reloc, 370 bool MayNeedFarStub, bool Indirect, 371 intptr_t ACPV) const { 372 MachineRelocation MR = Indirect 373 ? MachineRelocation::getIndirectSymbol(MCE.getCurrentPCOffset(), Reloc, 374 const_cast<GlobalValue *>(GV), 375 ACPV, MayNeedFarStub) 376 : MachineRelocation::getGV(MCE.getCurrentPCOffset(), Reloc, 377 const_cast<GlobalValue *>(GV), ACPV, 378 MayNeedFarStub); 379 MCE.addRelocation(MR); 380} 381 382/// emitExternalSymbolAddress - Arrange for the address of an external symbol to 383/// be emitted to the current location in the function, and allow it to be PC 384/// relative. 385void ARMCodeEmitter:: 386emitExternalSymbolAddress(const char *ES, unsigned Reloc) const { 387 MCE.addRelocation(MachineRelocation::getExtSym(MCE.getCurrentPCOffset(), 388 Reloc, ES)); 389} 390 391/// emitConstPoolAddress - Arrange for the address of an constant pool 392/// to be emitted to the current location in the function, and allow it to be PC 393/// relative. 394void ARMCodeEmitter::emitConstPoolAddress(unsigned CPI, unsigned Reloc) const { 395 // Tell JIT emitter we'll resolve the address. 396 MCE.addRelocation(MachineRelocation::getConstPool(MCE.getCurrentPCOffset(), 397 Reloc, CPI, 0, true)); 398} 399 400/// emitJumpTableAddress - Arrange for the address of a jump table to 401/// be emitted to the current location in the function, and allow it to be PC 402/// relative. 403void ARMCodeEmitter:: 404emitJumpTableAddress(unsigned JTIndex, unsigned Reloc) const { 405 MCE.addRelocation(MachineRelocation::getJumpTable(MCE.getCurrentPCOffset(), 406 Reloc, JTIndex, 0, true)); 407} 408 409/// emitMachineBasicBlock - Emit the specified address basic block. 410void ARMCodeEmitter::emitMachineBasicBlock(MachineBasicBlock *BB, 411 unsigned Reloc, 412 intptr_t JTBase) const { 413 MCE.addRelocation(MachineRelocation::getBB(MCE.getCurrentPCOffset(), 414 Reloc, BB, JTBase)); 415} 416 417void ARMCodeEmitter::emitWordLE(unsigned Binary) { 418 DEBUG(errs() << " 0x"; 419 errs().write_hex(Binary) << "\n"); 420 MCE.emitWordLE(Binary); 421} 422 423void ARMCodeEmitter::emitDWordLE(uint64_t Binary) { 424 DEBUG(errs() << " 0x"; 425 errs().write_hex(Binary) << "\n"); 426 MCE.emitDWordLE(Binary); 427} 428 429void ARMCodeEmitter::emitInstruction(const MachineInstr &MI) { 430 DEBUG(errs() << "JIT: " << (void*)MCE.getCurrentPCValue() << ":\t" << MI); 431 432 MCE.processDebugLoc(MI.getDebugLoc(), true); 433 434 ++NumEmitted; // Keep track of the # of mi's emitted 435 switch (MI.getDesc().TSFlags & ARMII::FormMask) { 436 default: { 437 llvm_unreachable("Unhandled instruction encoding format!"); 438 break; 439 } 440 case ARMII::Pseudo: 441 emitPseudoInstruction(MI); 442 break; 443 case ARMII::DPFrm: 444 case ARMII::DPSoRegFrm: 445 emitDataProcessingInstruction(MI); 446 break; 447 case ARMII::LdFrm: 448 case ARMII::StFrm: 449 emitLoadStoreInstruction(MI); 450 break; 451 case ARMII::LdMiscFrm: 452 case ARMII::StMiscFrm: 453 emitMiscLoadStoreInstruction(MI); 454 break; 455 case ARMII::LdStMulFrm: 456 emitLoadStoreMultipleInstruction(MI); 457 break; 458 case ARMII::MulFrm: 459 emitMulFrmInstruction(MI); 460 break; 461 case ARMII::ExtFrm: 462 emitExtendInstruction(MI); 463 break; 464 case ARMII::ArithMiscFrm: 465 emitMiscArithInstruction(MI); 466 break; 467 case ARMII::SatFrm: 468 emitSaturateInstruction(MI); 469 break; 470 case ARMII::BrFrm: 471 emitBranchInstruction(MI); 472 break; 473 case ARMII::BrMiscFrm: 474 emitMiscBranchInstruction(MI); 475 break; 476 // VFP instructions. 477 case ARMII::VFPUnaryFrm: 478 case ARMII::VFPBinaryFrm: 479 emitVFPArithInstruction(MI); 480 break; 481 case ARMII::VFPConv1Frm: 482 case ARMII::VFPConv2Frm: 483 case ARMII::VFPConv3Frm: 484 case ARMII::VFPConv4Frm: 485 case ARMII::VFPConv5Frm: 486 emitVFPConversionInstruction(MI); 487 break; 488 case ARMII::VFPLdStFrm: 489 emitVFPLoadStoreInstruction(MI); 490 break; 491 case ARMII::VFPLdStMulFrm: 492 emitVFPLoadStoreMultipleInstruction(MI); 493 break; 494 495 // NEON instructions. 496 case ARMII::NGetLnFrm: 497 case ARMII::NSetLnFrm: 498 emitNEONLaneInstruction(MI); 499 break; 500 case ARMII::NDupFrm: 501 emitNEONDupInstruction(MI); 502 break; 503 case ARMII::N1RegModImmFrm: 504 emitNEON1RegModImmInstruction(MI); 505 break; 506 case ARMII::N2RegFrm: 507 emitNEON2RegInstruction(MI); 508 break; 509 case ARMII::N3RegFrm: 510 emitNEON3RegInstruction(MI); 511 break; 512 } 513 MCE.processDebugLoc(MI.getDebugLoc(), false); 514} 515 516void ARMCodeEmitter::emitConstPoolInstruction(const MachineInstr &MI) { 517 unsigned CPI = MI.getOperand(0).getImm(); // CP instruction index. 518 unsigned CPIndex = MI.getOperand(1).getIndex(); // Actual cp entry index. 519 const MachineConstantPoolEntry &MCPE = (*MCPEs)[CPIndex]; 520 521 // Remember the CONSTPOOL_ENTRY address for later relocation. 522 JTI->addConstantPoolEntryAddr(CPI, MCE.getCurrentPCValue()); 523 524 // Emit constpool island entry. In most cases, the actual values will be 525 // resolved and relocated after code emission. 526 if (MCPE.isMachineConstantPoolEntry()) { 527 ARMConstantPoolValue *ACPV = 528 static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal); 529 530 DEBUG(errs() << " ** ARM constant pool #" << CPI << " @ " 531 << (void*)MCE.getCurrentPCValue() << " " << *ACPV << '\n'); 532 533 assert(ACPV->isGlobalValue() && "unsupported constant pool value"); 534 const GlobalValue *GV = ACPV->getGV(); 535 if (GV) { 536 Reloc::Model RelocM = TM.getRelocationModel(); 537 emitGlobalAddress(GV, ARM::reloc_arm_machine_cp_entry, 538 isa<Function>(GV), 539 Subtarget->GVIsIndirectSymbol(GV, RelocM), 540 (intptr_t)ACPV); 541 } else { 542 emitExternalSymbolAddress(ACPV->getSymbol(), ARM::reloc_arm_absolute); 543 } 544 emitWordLE(0); 545 } else { 546 const Constant *CV = MCPE.Val.ConstVal; 547 548 DEBUG({ 549 errs() << " ** Constant pool #" << CPI << " @ " 550 << (void*)MCE.getCurrentPCValue() << " "; 551 if (const Function *F = dyn_cast<Function>(CV)) 552 errs() << F->getName(); 553 else 554 errs() << *CV; 555 errs() << '\n'; 556 }); 557 558 if (const GlobalValue *GV = dyn_cast<GlobalValue>(CV)) { 559 emitGlobalAddress(GV, ARM::reloc_arm_absolute, isa<Function>(GV), false); 560 emitWordLE(0); 561 } else if (const ConstantInt *CI = dyn_cast<ConstantInt>(CV)) { 562 uint32_t Val = uint32_t(*CI->getValue().getRawData()); 563 emitWordLE(Val); 564 } else if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CV)) { 565 if (CFP->getType()->isFloatTy()) 566 emitWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue()); 567 else if (CFP->getType()->isDoubleTy()) 568 emitDWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue()); 569 else { 570 llvm_unreachable("Unable to handle this constantpool entry!"); 571 } 572 } else { 573 llvm_unreachable("Unable to handle this constantpool entry!"); 574 } 575 } 576} 577 578void ARMCodeEmitter::emitMOVi32immInstruction(const MachineInstr &MI) { 579 const MachineOperand &MO0 = MI.getOperand(0); 580 const MachineOperand &MO1 = MI.getOperand(1); 581 582 // Emit the 'movw' instruction. 583 unsigned Binary = 0x30 << 20; // mov: Insts{27-20} = 0b00110000 584 585 unsigned Lo16 = getMovi32Value(MI, MO1, ARM::reloc_arm_movw) & 0xFFFF; 586 587 // Set the conditional execution predicate. 588 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 589 590 // Encode Rd. 591 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift; 592 593 // Encode imm16 as imm4:imm12 594 Binary |= Lo16 & 0xFFF; // Insts{11-0} = imm12 595 Binary |= ((Lo16 >> 12) & 0xF) << 16; // Insts{19-16} = imm4 596 emitWordLE(Binary); 597 598 unsigned Hi16 = getMovi32Value(MI, MO1, ARM::reloc_arm_movt) >> 16; 599 // Emit the 'movt' instruction. 600 Binary = 0x34 << 20; // movt: Insts{27-20} = 0b00110100 601 602 // Set the conditional execution predicate. 603 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 604 605 // Encode Rd. 606 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift; 607 608 // Encode imm16 as imm4:imm1, same as movw above. 609 Binary |= Hi16 & 0xFFF; 610 Binary |= ((Hi16 >> 12) & 0xF) << 16; 611 emitWordLE(Binary); 612} 613 614void ARMCodeEmitter::emitMOVi2piecesInstruction(const MachineInstr &MI) { 615 const MachineOperand &MO0 = MI.getOperand(0); 616 const MachineOperand &MO1 = MI.getOperand(1); 617 assert(MO1.isImm() && ARM_AM::isSOImmTwoPartVal(MO1.getImm()) && 618 "Not a valid so_imm value!"); 619 unsigned V1 = ARM_AM::getSOImmTwoPartFirst(MO1.getImm()); 620 unsigned V2 = ARM_AM::getSOImmTwoPartSecond(MO1.getImm()); 621 622 // Emit the 'mov' instruction. 623 unsigned Binary = 0xd << 21; // mov: Insts{24-21} = 0b1101 624 625 // Set the conditional execution predicate. 626 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 627 628 // Encode Rd. 629 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift; 630 631 // Encode so_imm. 632 // Set bit I(25) to identify this is the immediate form of <shifter_op> 633 Binary |= 1 << ARMII::I_BitShift; 634 Binary |= getMachineSoImmOpValue(V1); 635 emitWordLE(Binary); 636 637 // Now the 'orr' instruction. 638 Binary = 0xc << 21; // orr: Insts{24-21} = 0b1100 639 640 // Set the conditional execution predicate. 641 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 642 643 // Encode Rd. 644 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift; 645 646 // Encode Rn. 647 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRnShift; 648 649 // Encode so_imm. 650 // Set bit I(25) to identify this is the immediate form of <shifter_op> 651 Binary |= 1 << ARMII::I_BitShift; 652 Binary |= getMachineSoImmOpValue(V2); 653 emitWordLE(Binary); 654} 655 656void ARMCodeEmitter::emitLEApcrelJTInstruction(const MachineInstr &MI) { 657 // It's basically add r, pc, (LJTI - $+8) 658 659 const TargetInstrDesc &TID = MI.getDesc(); 660 661 // Emit the 'add' instruction. 662 unsigned Binary = 0x4 << 21; // add: Insts{24-31} = 0b0100 663 664 // Set the conditional execution predicate 665 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 666 667 // Encode S bit if MI modifies CPSR. 668 Binary |= getAddrModeSBit(MI, TID); 669 670 // Encode Rd. 671 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift; 672 673 // Encode Rn which is PC. 674 Binary |= getARMRegisterNumbering(ARM::PC) << ARMII::RegRnShift; 675 676 // Encode the displacement. 677 Binary |= 1 << ARMII::I_BitShift; 678 emitJumpTableAddress(MI.getOperand(1).getIndex(), ARM::reloc_arm_jt_base); 679 680 emitWordLE(Binary); 681} 682 683void ARMCodeEmitter::emitPseudoMoveInstruction(const MachineInstr &MI) { 684 unsigned Opcode = MI.getDesc().Opcode; 685 686 // Part of binary is determined by TableGn. 687 unsigned Binary = getBinaryCodeForInstr(MI); 688 689 // Set the conditional execution predicate 690 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 691 692 // Encode S bit if MI modifies CPSR. 693 if (Opcode == ARM::MOVsrl_flag || Opcode == ARM::MOVsra_flag) 694 Binary |= 1 << ARMII::S_BitShift; 695 696 // Encode register def if there is one. 697 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift; 698 699 // Encode the shift operation. 700 switch (Opcode) { 701 default: break; 702 case ARM::RRX: 703 // rrx 704 Binary |= 0x6 << 4; 705 break; 706 case ARM::MOVsrl_flag: 707 // lsr #1 708 Binary |= (0x2 << 4) | (1 << 7); 709 break; 710 case ARM::MOVsra_flag: 711 // asr #1 712 Binary |= (0x4 << 4) | (1 << 7); 713 break; 714 } 715 716 // Encode register Rm. 717 Binary |= getMachineOpValue(MI, 1); 718 719 emitWordLE(Binary); 720} 721 722void ARMCodeEmitter::addPCLabel(unsigned LabelID) { 723 DEBUG(errs() << " ** LPC" << LabelID << " @ " 724 << (void*)MCE.getCurrentPCValue() << '\n'); 725 JTI->addPCLabelAddr(LabelID, MCE.getCurrentPCValue()); 726} 727 728void ARMCodeEmitter::emitPseudoInstruction(const MachineInstr &MI) { 729 unsigned Opcode = MI.getDesc().Opcode; 730 switch (Opcode) { 731 default: 732 llvm_unreachable("ARMCodeEmitter::emitPseudoInstruction"); 733 case ARM::BX: 734 case ARM::BMOVPCRX: 735 case ARM::BXr9: 736 case ARM::BMOVPCRXr9: { 737 // First emit mov lr, pc 738 unsigned Binary = 0x01a0e00f; 739 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 740 emitWordLE(Binary); 741 742 // and then emit the branch. 743 emitMiscBranchInstruction(MI); 744 break; 745 } 746 case TargetOpcode::INLINEASM: { 747 // We allow inline assembler nodes with empty bodies - they can 748 // implicitly define registers, which is ok for JIT. 749 if (MI.getOperand(0).getSymbolName()[0]) { 750 report_fatal_error("JIT does not support inline asm!"); 751 } 752 break; 753 } 754 case TargetOpcode::PROLOG_LABEL: 755 case TargetOpcode::EH_LABEL: 756 MCE.emitLabel(MI.getOperand(0).getMCSymbol()); 757 break; 758 case TargetOpcode::IMPLICIT_DEF: 759 case TargetOpcode::KILL: 760 // Do nothing. 761 break; 762 case ARM::CONSTPOOL_ENTRY: 763 emitConstPoolInstruction(MI); 764 break; 765 case ARM::PICADD: { 766 // Remember of the address of the PC label for relocation later. 767 addPCLabel(MI.getOperand(2).getImm()); 768 // PICADD is just an add instruction that implicitly read pc. 769 emitDataProcessingInstruction(MI, 0, ARM::PC); 770 break; 771 } 772 case ARM::PICLDR: 773 case ARM::PICLDRB: 774 case ARM::PICSTR: 775 case ARM::PICSTRB: { 776 // Remember of the address of the PC label for relocation later. 777 addPCLabel(MI.getOperand(2).getImm()); 778 // These are just load / store instructions that implicitly read pc. 779 emitLoadStoreInstruction(MI, 0, ARM::PC); 780 break; 781 } 782 case ARM::PICLDRH: 783 case ARM::PICLDRSH: 784 case ARM::PICLDRSB: 785 case ARM::PICSTRH: { 786 // Remember of the address of the PC label for relocation later. 787 addPCLabel(MI.getOperand(2).getImm()); 788 // These are just load / store instructions that implicitly read pc. 789 emitMiscLoadStoreInstruction(MI, ARM::PC); 790 break; 791 } 792 793 case ARM::MOVi32imm: 794 emitMOVi32immInstruction(MI); 795 break; 796 797 case ARM::MOVi2pieces: 798 // Two instructions to materialize a constant. 799 emitMOVi2piecesInstruction(MI); 800 break; 801 case ARM::LEApcrelJT: 802 // Materialize jumptable address. 803 emitLEApcrelJTInstruction(MI); 804 break; 805 case ARM::RRX: 806 case ARM::MOVsrl_flag: 807 case ARM::MOVsra_flag: 808 emitPseudoMoveInstruction(MI); 809 break; 810 } 811} 812 813unsigned ARMCodeEmitter::getMachineSoRegOpValue(const MachineInstr &MI, 814 const TargetInstrDesc &TID, 815 const MachineOperand &MO, 816 unsigned OpIdx) { 817 unsigned Binary = getMachineOpValue(MI, MO); 818 819 const MachineOperand &MO1 = MI.getOperand(OpIdx + 1); 820 const MachineOperand &MO2 = MI.getOperand(OpIdx + 2); 821 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm()); 822 823 // Encode the shift opcode. 824 unsigned SBits = 0; 825 unsigned Rs = MO1.getReg(); 826 if (Rs) { 827 // Set shift operand (bit[7:4]). 828 // LSL - 0001 829 // LSR - 0011 830 // ASR - 0101 831 // ROR - 0111 832 // RRX - 0110 and bit[11:8] clear. 833 switch (SOpc) { 834 default: llvm_unreachable("Unknown shift opc!"); 835 case ARM_AM::lsl: SBits = 0x1; break; 836 case ARM_AM::lsr: SBits = 0x3; break; 837 case ARM_AM::asr: SBits = 0x5; break; 838 case ARM_AM::ror: SBits = 0x7; break; 839 case ARM_AM::rrx: SBits = 0x6; break; 840 } 841 } else { 842 // Set shift operand (bit[6:4]). 843 // LSL - 000 844 // LSR - 010 845 // ASR - 100 846 // ROR - 110 847 switch (SOpc) { 848 default: llvm_unreachable("Unknown shift opc!"); 849 case ARM_AM::lsl: SBits = 0x0; break; 850 case ARM_AM::lsr: SBits = 0x2; break; 851 case ARM_AM::asr: SBits = 0x4; break; 852 case ARM_AM::ror: SBits = 0x6; break; 853 } 854 } 855 Binary |= SBits << 4; 856 if (SOpc == ARM_AM::rrx) 857 return Binary; 858 859 // Encode the shift operation Rs or shift_imm (except rrx). 860 if (Rs) { 861 // Encode Rs bit[11:8]. 862 assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0); 863 return Binary | (getARMRegisterNumbering(Rs) << ARMII::RegRsShift); 864 } 865 866 // Encode shift_imm bit[11:7]. 867 return Binary | ARM_AM::getSORegOffset(MO2.getImm()) << 7; 868} 869 870unsigned ARMCodeEmitter::getMachineSoImmOpValue(unsigned SoImm) { 871 int SoImmVal = ARM_AM::getSOImmVal(SoImm); 872 assert(SoImmVal != -1 && "Not a valid so_imm value!"); 873 874 // Encode rotate_imm. 875 unsigned Binary = (ARM_AM::getSOImmValRot((unsigned)SoImmVal) >> 1) 876 << ARMII::SoRotImmShift; 877 878 // Encode immed_8. 879 Binary |= ARM_AM::getSOImmValImm((unsigned)SoImmVal); 880 return Binary; 881} 882 883unsigned ARMCodeEmitter::getAddrModeSBit(const MachineInstr &MI, 884 const TargetInstrDesc &TID) const { 885 for (unsigned i = MI.getNumOperands(), e = TID.getNumOperands(); i != e; --i){ 886 const MachineOperand &MO = MI.getOperand(i-1); 887 if (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR) 888 return 1 << ARMII::S_BitShift; 889 } 890 return 0; 891} 892 893void ARMCodeEmitter::emitDataProcessingInstruction(const MachineInstr &MI, 894 unsigned ImplicitRd, 895 unsigned ImplicitRn) { 896 const TargetInstrDesc &TID = MI.getDesc(); 897 898 // Part of binary is determined by TableGn. 899 unsigned Binary = getBinaryCodeForInstr(MI); 900 901 // Set the conditional execution predicate 902 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 903 904 // Encode S bit if MI modifies CPSR. 905 Binary |= getAddrModeSBit(MI, TID); 906 907 // Encode register def if there is one. 908 unsigned NumDefs = TID.getNumDefs(); 909 unsigned OpIdx = 0; 910 if (NumDefs) 911 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift; 912 else if (ImplicitRd) 913 // Special handling for implicit use (e.g. PC). 914 Binary |= (getARMRegisterNumbering(ImplicitRd) << ARMII::RegRdShift); 915 916 if (TID.Opcode == ARM::MOVi16) { 917 // Get immediate from MI. 918 unsigned Lo16 = getMovi32Value(MI, MI.getOperand(OpIdx), 919 ARM::reloc_arm_movw); 920 // Encode imm which is the same as in emitMOVi32immInstruction(). 921 Binary |= Lo16 & 0xFFF; 922 Binary |= ((Lo16 >> 12) & 0xF) << 16; 923 emitWordLE(Binary); 924 return; 925 } else if(TID.Opcode == ARM::MOVTi16) { 926 unsigned Hi16 = (getMovi32Value(MI, MI.getOperand(OpIdx), 927 ARM::reloc_arm_movt) >> 16); 928 Binary |= Hi16 & 0xFFF; 929 Binary |= ((Hi16 >> 12) & 0xF) << 16; 930 emitWordLE(Binary); 931 return; 932 } else if ((TID.Opcode == ARM::BFC) || (TID.Opcode == ARM::BFI)) { 933 uint32_t v = ~MI.getOperand(2).getImm(); 934 int32_t lsb = CountTrailingZeros_32(v); 935 int32_t msb = (32 - CountLeadingZeros_32(v)) - 1; 936 // Instr{20-16} = msb, Instr{11-7} = lsb 937 Binary |= (msb & 0x1F) << 16; 938 Binary |= (lsb & 0x1F) << 7; 939 emitWordLE(Binary); 940 return; 941 } else if ((TID.Opcode == ARM::UBFX) || (TID.Opcode == ARM::SBFX)) { 942 // Encode Rn in Instr{0-3} 943 Binary |= getMachineOpValue(MI, OpIdx++); 944 945 uint32_t lsb = MI.getOperand(OpIdx++).getImm(); 946 uint32_t widthm1 = MI.getOperand(OpIdx++).getImm() - 1; 947 948 // Instr{20-16} = widthm1, Instr{11-7} = lsb 949 Binary |= (widthm1 & 0x1F) << 16; 950 Binary |= (lsb & 0x1F) << 7; 951 emitWordLE(Binary); 952 return; 953 } 954 955 // If this is a two-address operand, skip it. e.g. MOVCCr operand 1. 956 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1) 957 ++OpIdx; 958 959 // Encode first non-shifter register operand if there is one. 960 bool isUnary = TID.TSFlags & ARMII::UnaryDP; 961 if (!isUnary) { 962 if (ImplicitRn) 963 // Special handling for implicit use (e.g. PC). 964 Binary |= (getARMRegisterNumbering(ImplicitRn) << ARMII::RegRnShift); 965 else { 966 Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRnShift; 967 ++OpIdx; 968 } 969 } 970 971 // Encode shifter operand. 972 const MachineOperand &MO = MI.getOperand(OpIdx); 973 if ((TID.TSFlags & ARMII::FormMask) == ARMII::DPSoRegFrm) { 974 // Encode SoReg. 975 emitWordLE(Binary | getMachineSoRegOpValue(MI, TID, MO, OpIdx)); 976 return; 977 } 978 979 if (MO.isReg()) { 980 // Encode register Rm. 981 emitWordLE(Binary | getARMRegisterNumbering(MO.getReg())); 982 return; 983 } 984 985 // Encode so_imm. 986 Binary |= getMachineSoImmOpValue((unsigned)MO.getImm()); 987 988 emitWordLE(Binary); 989} 990 991void ARMCodeEmitter::emitLoadStoreInstruction(const MachineInstr &MI, 992 unsigned ImplicitRd, 993 unsigned ImplicitRn) { 994 const TargetInstrDesc &TID = MI.getDesc(); 995 unsigned Form = TID.TSFlags & ARMII::FormMask; 996 bool IsPrePost = (TID.TSFlags & ARMII::IndexModeMask) != 0; 997 998 // Part of binary is determined by TableGn. 999 unsigned Binary = getBinaryCodeForInstr(MI); 1000 1001 // If this is an LDRi12, STRi12 or LDRcp, nothing more needs be done. 1002 if (MI.getOpcode() == ARM::LDRi12 || MI.getOpcode() == ARM::LDRcp || 1003 MI.getOpcode() == ARM::STRi12) { 1004 emitWordLE(Binary); 1005 return; 1006 } 1007 1008 // Set the conditional execution predicate 1009 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1010 1011 unsigned OpIdx = 0; 1012 1013 // Operand 0 of a pre- and post-indexed store is the address base 1014 // writeback. Skip it. 1015 bool Skipped = false; 1016 if (IsPrePost && Form == ARMII::StFrm) { 1017 ++OpIdx; 1018 Skipped = true; 1019 } 1020 1021 // Set first operand 1022 if (ImplicitRd) 1023 // Special handling for implicit use (e.g. PC). 1024 Binary |= (getARMRegisterNumbering(ImplicitRd) << ARMII::RegRdShift); 1025 else 1026 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift; 1027 1028 // Set second operand 1029 if (ImplicitRn) 1030 // Special handling for implicit use (e.g. PC). 1031 Binary |= (getARMRegisterNumbering(ImplicitRn) << ARMII::RegRnShift); 1032 else 1033 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift; 1034 1035 // If this is a two-address operand, skip it. e.g. LDR_PRE. 1036 if (!Skipped && TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1) 1037 ++OpIdx; 1038 1039 const MachineOperand &MO2 = MI.getOperand(OpIdx); 1040 unsigned AM2Opc = (ImplicitRn == ARM::PC) 1041 ? 0 : MI.getOperand(OpIdx+1).getImm(); 1042 1043 // Set bit U(23) according to sign of immed value (positive or negative). 1044 Binary |= ((ARM_AM::getAM2Op(AM2Opc) == ARM_AM::add ? 1 : 0) << 1045 ARMII::U_BitShift); 1046 if (!MO2.getReg()) { // is immediate 1047 if (ARM_AM::getAM2Offset(AM2Opc)) 1048 // Set the value of offset_12 field 1049 Binary |= ARM_AM::getAM2Offset(AM2Opc); 1050 emitWordLE(Binary); 1051 return; 1052 } 1053 1054 // Set bit I(25), because this is not in immediate encoding. 1055 Binary |= 1 << ARMII::I_BitShift; 1056 assert(TargetRegisterInfo::isPhysicalRegister(MO2.getReg())); 1057 // Set bit[3:0] to the corresponding Rm register 1058 Binary |= getARMRegisterNumbering(MO2.getReg()); 1059 1060 // If this instr is in scaled register offset/index instruction, set 1061 // shift_immed(bit[11:7]) and shift(bit[6:5]) fields. 1062 if (unsigned ShImm = ARM_AM::getAM2Offset(AM2Opc)) { 1063 Binary |= getShiftOp(AM2Opc) << ARMII::ShiftImmShift; // shift 1064 Binary |= ShImm << ARMII::ShiftShift; // shift_immed 1065 } 1066 1067 emitWordLE(Binary); 1068} 1069 1070void ARMCodeEmitter::emitMiscLoadStoreInstruction(const MachineInstr &MI, 1071 unsigned ImplicitRn) { 1072 const TargetInstrDesc &TID = MI.getDesc(); 1073 unsigned Form = TID.TSFlags & ARMII::FormMask; 1074 bool IsPrePost = (TID.TSFlags & ARMII::IndexModeMask) != 0; 1075 1076 // Part of binary is determined by TableGn. 1077 unsigned Binary = getBinaryCodeForInstr(MI); 1078 1079 // Set the conditional execution predicate 1080 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1081 1082 unsigned OpIdx = 0; 1083 1084 // Operand 0 of a pre- and post-indexed store is the address base 1085 // writeback. Skip it. 1086 bool Skipped = false; 1087 if (IsPrePost && Form == ARMII::StMiscFrm) { 1088 ++OpIdx; 1089 Skipped = true; 1090 } 1091 1092 // Set first operand 1093 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift; 1094 1095 // Skip LDRD and STRD's second operand. 1096 if (TID.Opcode == ARM::LDRD || TID.Opcode == ARM::STRD) 1097 ++OpIdx; 1098 1099 // Set second operand 1100 if (ImplicitRn) 1101 // Special handling for implicit use (e.g. PC). 1102 Binary |= (getARMRegisterNumbering(ImplicitRn) << ARMII::RegRnShift); 1103 else 1104 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift; 1105 1106 // If this is a two-address operand, skip it. e.g. LDRH_POST. 1107 if (!Skipped && TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1) 1108 ++OpIdx; 1109 1110 const MachineOperand &MO2 = MI.getOperand(OpIdx); 1111 unsigned AM3Opc = (ImplicitRn == ARM::PC) 1112 ? 0 : MI.getOperand(OpIdx+1).getImm(); 1113 1114 // Set bit U(23) according to sign of immed value (positive or negative) 1115 Binary |= ((ARM_AM::getAM3Op(AM3Opc) == ARM_AM::add ? 1 : 0) << 1116 ARMII::U_BitShift); 1117 1118 // If this instr is in register offset/index encoding, set bit[3:0] 1119 // to the corresponding Rm register. 1120 if (MO2.getReg()) { 1121 Binary |= getARMRegisterNumbering(MO2.getReg()); 1122 emitWordLE(Binary); 1123 return; 1124 } 1125 1126 // This instr is in immediate offset/index encoding, set bit 22 to 1. 1127 Binary |= 1 << ARMII::AM3_I_BitShift; 1128 if (unsigned ImmOffs = ARM_AM::getAM3Offset(AM3Opc)) { 1129 // Set operands 1130 Binary |= (ImmOffs >> 4) << ARMII::ImmHiShift; // immedH 1131 Binary |= (ImmOffs & 0xF); // immedL 1132 } 1133 1134 emitWordLE(Binary); 1135} 1136 1137static unsigned getAddrModeUPBits(unsigned Mode) { 1138 unsigned Binary = 0; 1139 1140 // Set addressing mode by modifying bits U(23) and P(24) 1141 // IA - Increment after - bit U = 1 and bit P = 0 1142 // IB - Increment before - bit U = 1 and bit P = 1 1143 // DA - Decrement after - bit U = 0 and bit P = 0 1144 // DB - Decrement before - bit U = 0 and bit P = 1 1145 switch (Mode) { 1146 default: llvm_unreachable("Unknown addressing sub-mode!"); 1147 case ARM_AM::da: break; 1148 case ARM_AM::db: Binary |= 0x1 << ARMII::P_BitShift; break; 1149 case ARM_AM::ia: Binary |= 0x1 << ARMII::U_BitShift; break; 1150 case ARM_AM::ib: Binary |= 0x3 << ARMII::U_BitShift; break; 1151 } 1152 1153 return Binary; 1154} 1155 1156void ARMCodeEmitter::emitLoadStoreMultipleInstruction(const MachineInstr &MI) { 1157 const TargetInstrDesc &TID = MI.getDesc(); 1158 bool IsUpdating = (TID.TSFlags & ARMII::IndexModeMask) != 0; 1159 1160 // Part of binary is determined by TableGn. 1161 unsigned Binary = getBinaryCodeForInstr(MI); 1162 1163 // Set the conditional execution predicate 1164 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1165 1166 // Skip operand 0 of an instruction with base register update. 1167 unsigned OpIdx = 0; 1168 if (IsUpdating) 1169 ++OpIdx; 1170 1171 // Set base address operand 1172 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift; 1173 1174 // Set addressing mode by modifying bits U(23) and P(24) 1175 const MachineOperand &MO = MI.getOperand(OpIdx++); 1176 Binary |= getAddrModeUPBits(ARM_AM::getAM4SubMode(MO.getImm())); 1177 1178 // Set bit W(21) 1179 if (IsUpdating) 1180 Binary |= 0x1 << ARMII::W_BitShift; 1181 1182 // Set registers 1183 for (unsigned i = OpIdx+2, e = MI.getNumOperands(); i != e; ++i) { 1184 const MachineOperand &MO = MI.getOperand(i); 1185 if (!MO.isReg() || MO.isImplicit()) 1186 break; 1187 unsigned RegNum = getARMRegisterNumbering(MO.getReg()); 1188 assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()) && 1189 RegNum < 16); 1190 Binary |= 0x1 << RegNum; 1191 } 1192 1193 emitWordLE(Binary); 1194} 1195 1196void ARMCodeEmitter::emitMulFrmInstruction(const MachineInstr &MI) { 1197 const TargetInstrDesc &TID = MI.getDesc(); 1198 1199 // Part of binary is determined by TableGn. 1200 unsigned Binary = getBinaryCodeForInstr(MI); 1201 1202 // Set the conditional execution predicate 1203 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1204 1205 // Encode S bit if MI modifies CPSR. 1206 Binary |= getAddrModeSBit(MI, TID); 1207 1208 // 32x32->64bit operations have two destination registers. The number 1209 // of register definitions will tell us if that's what we're dealing with. 1210 unsigned OpIdx = 0; 1211 if (TID.getNumDefs() == 2) 1212 Binary |= getMachineOpValue (MI, OpIdx++) << ARMII::RegRdLoShift; 1213 1214 // Encode Rd 1215 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdHiShift; 1216 1217 // Encode Rm 1218 Binary |= getMachineOpValue(MI, OpIdx++); 1219 1220 // Encode Rs 1221 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRsShift; 1222 1223 // Many multiple instructions (e.g. MLA) have three src operands. Encode 1224 // it as Rn (for multiply, that's in the same offset as RdLo. 1225 if (TID.getNumOperands() > OpIdx && 1226 !TID.OpInfo[OpIdx].isPredicate() && 1227 !TID.OpInfo[OpIdx].isOptionalDef()) 1228 Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRdLoShift; 1229 1230 emitWordLE(Binary); 1231} 1232 1233void ARMCodeEmitter::emitExtendInstruction(const MachineInstr &MI) { 1234 const TargetInstrDesc &TID = MI.getDesc(); 1235 1236 // Part of binary is determined by TableGn. 1237 unsigned Binary = getBinaryCodeForInstr(MI); 1238 1239 // Set the conditional execution predicate 1240 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1241 1242 unsigned OpIdx = 0; 1243 1244 // Encode Rd 1245 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift; 1246 1247 const MachineOperand &MO1 = MI.getOperand(OpIdx++); 1248 const MachineOperand &MO2 = MI.getOperand(OpIdx); 1249 if (MO2.isReg()) { 1250 // Two register operand form. 1251 // Encode Rn. 1252 Binary |= getMachineOpValue(MI, MO1) << ARMII::RegRnShift; 1253 1254 // Encode Rm. 1255 Binary |= getMachineOpValue(MI, MO2); 1256 ++OpIdx; 1257 } else { 1258 Binary |= getMachineOpValue(MI, MO1); 1259 } 1260 1261 // Encode rot imm (0, 8, 16, or 24) if it has a rotate immediate operand. 1262 if (MI.getOperand(OpIdx).isImm() && 1263 !TID.OpInfo[OpIdx].isPredicate() && 1264 !TID.OpInfo[OpIdx].isOptionalDef()) 1265 Binary |= (getMachineOpValue(MI, OpIdx) / 8) << ARMII::ExtRotImmShift; 1266 1267 emitWordLE(Binary); 1268} 1269 1270void ARMCodeEmitter::emitMiscArithInstruction(const MachineInstr &MI) { 1271 const TargetInstrDesc &TID = MI.getDesc(); 1272 1273 // Part of binary is determined by TableGn. 1274 unsigned Binary = getBinaryCodeForInstr(MI); 1275 1276 // Set the conditional execution predicate 1277 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1278 1279 unsigned OpIdx = 0; 1280 1281 // Encode Rd 1282 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift; 1283 1284 const MachineOperand &MO = MI.getOperand(OpIdx++); 1285 if (OpIdx == TID.getNumOperands() || 1286 TID.OpInfo[OpIdx].isPredicate() || 1287 TID.OpInfo[OpIdx].isOptionalDef()) { 1288 // Encode Rm and it's done. 1289 Binary |= getMachineOpValue(MI, MO); 1290 emitWordLE(Binary); 1291 return; 1292 } 1293 1294 // Encode Rn. 1295 Binary |= getMachineOpValue(MI, MO) << ARMII::RegRnShift; 1296 1297 // Encode Rm. 1298 Binary |= getMachineOpValue(MI, OpIdx++); 1299 1300 // Encode shift_imm. 1301 unsigned ShiftAmt = MI.getOperand(OpIdx).getImm(); 1302 if (TID.Opcode == ARM::PKHTB) { 1303 assert(ShiftAmt != 0 && "PKHTB shift_imm is 0!"); 1304 if (ShiftAmt == 32) 1305 ShiftAmt = 0; 1306 } 1307 assert(ShiftAmt < 32 && "shift_imm range is 0 to 31!"); 1308 Binary |= ShiftAmt << ARMII::ShiftShift; 1309 1310 emitWordLE(Binary); 1311} 1312 1313void ARMCodeEmitter::emitSaturateInstruction(const MachineInstr &MI) { 1314 const TargetInstrDesc &TID = MI.getDesc(); 1315 1316 // Part of binary is determined by TableGen. 1317 unsigned Binary = getBinaryCodeForInstr(MI); 1318 1319 // Set the conditional execution predicate 1320 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1321 1322 // Encode Rd 1323 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift; 1324 1325 // Encode saturate bit position. 1326 unsigned Pos = MI.getOperand(1).getImm(); 1327 if (TID.Opcode == ARM::SSAT || TID.Opcode == ARM::SSAT16) 1328 Pos -= 1; 1329 assert((Pos < 16 || (Pos < 32 && 1330 TID.Opcode != ARM::SSAT16 && 1331 TID.Opcode != ARM::USAT16)) && 1332 "saturate bit position out of range"); 1333 Binary |= Pos << 16; 1334 1335 // Encode Rm 1336 Binary |= getMachineOpValue(MI, 2); 1337 1338 // Encode shift_imm. 1339 if (TID.getNumOperands() == 4) { 1340 unsigned ShiftOp = MI.getOperand(3).getImm(); 1341 ARM_AM::ShiftOpc Opc = ARM_AM::getSORegShOp(ShiftOp); 1342 if (Opc == ARM_AM::asr) 1343 Binary |= (1 << 6); 1344 unsigned ShiftAmt = MI.getOperand(3).getImm(); 1345 if (ShiftAmt == 32 && Opc == ARM_AM::asr) 1346 ShiftAmt = 0; 1347 assert(ShiftAmt < 32 && "shift_imm range is 0 to 31!"); 1348 Binary |= ShiftAmt << ARMII::ShiftShift; 1349 } 1350 1351 emitWordLE(Binary); 1352} 1353 1354void ARMCodeEmitter::emitBranchInstruction(const MachineInstr &MI) { 1355 const TargetInstrDesc &TID = MI.getDesc(); 1356 1357 if (TID.Opcode == ARM::TPsoft) { 1358 llvm_unreachable("ARM::TPsoft FIXME"); // FIXME 1359 } 1360 1361 // Part of binary is determined by TableGn. 1362 unsigned Binary = getBinaryCodeForInstr(MI); 1363 1364 // Set the conditional execution predicate 1365 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1366 1367 // Set signed_immed_24 field 1368 Binary |= getMachineOpValue(MI, 0); 1369 1370 emitWordLE(Binary); 1371} 1372 1373void ARMCodeEmitter::emitInlineJumpTable(unsigned JTIndex) { 1374 // Remember the base address of the inline jump table. 1375 uintptr_t JTBase = MCE.getCurrentPCValue(); 1376 JTI->addJumpTableBaseAddr(JTIndex, JTBase); 1377 DEBUG(errs() << " ** Jump Table #" << JTIndex << " @ " << (void*)JTBase 1378 << '\n'); 1379 1380 // Now emit the jump table entries. 1381 const std::vector<MachineBasicBlock*> &MBBs = (*MJTEs)[JTIndex].MBBs; 1382 for (unsigned i = 0, e = MBBs.size(); i != e; ++i) { 1383 if (IsPIC) 1384 // DestBB address - JT base. 1385 emitMachineBasicBlock(MBBs[i], ARM::reloc_arm_pic_jt, JTBase); 1386 else 1387 // Absolute DestBB address. 1388 emitMachineBasicBlock(MBBs[i], ARM::reloc_arm_absolute); 1389 emitWordLE(0); 1390 } 1391} 1392 1393void ARMCodeEmitter::emitMiscBranchInstruction(const MachineInstr &MI) { 1394 const TargetInstrDesc &TID = MI.getDesc(); 1395 1396 // Handle jump tables. 1397 if (TID.Opcode == ARM::BR_JTr || TID.Opcode == ARM::BR_JTadd) { 1398 // First emit a ldr pc, [] instruction. 1399 emitDataProcessingInstruction(MI, ARM::PC); 1400 1401 // Then emit the inline jump table. 1402 unsigned JTIndex = 1403 (TID.Opcode == ARM::BR_JTr) 1404 ? MI.getOperand(1).getIndex() : MI.getOperand(2).getIndex(); 1405 emitInlineJumpTable(JTIndex); 1406 return; 1407 } else if (TID.Opcode == ARM::BR_JTm) { 1408 // First emit a ldr pc, [] instruction. 1409 emitLoadStoreInstruction(MI, ARM::PC); 1410 1411 // Then emit the inline jump table. 1412 emitInlineJumpTable(MI.getOperand(3).getIndex()); 1413 return; 1414 } 1415 1416 // Part of binary is determined by TableGn. 1417 unsigned Binary = getBinaryCodeForInstr(MI); 1418 1419 // Set the conditional execution predicate 1420 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1421 1422 if (TID.Opcode == ARM::BX_RET || TID.Opcode == ARM::MOVPCLR) 1423 // The return register is LR. 1424 Binary |= getARMRegisterNumbering(ARM::LR); 1425 else 1426 // otherwise, set the return register 1427 Binary |= getMachineOpValue(MI, 0); 1428 1429 emitWordLE(Binary); 1430} 1431 1432static unsigned encodeVFPRd(const MachineInstr &MI, unsigned OpIdx) { 1433 unsigned RegD = MI.getOperand(OpIdx).getReg(); 1434 unsigned Binary = 0; 1435 bool isSPVFP = ARM::SPRRegisterClass->contains(RegD); 1436 RegD = getARMRegisterNumbering(RegD); 1437 if (!isSPVFP) 1438 Binary |= RegD << ARMII::RegRdShift; 1439 else { 1440 Binary |= ((RegD & 0x1E) >> 1) << ARMII::RegRdShift; 1441 Binary |= (RegD & 0x01) << ARMII::D_BitShift; 1442 } 1443 return Binary; 1444} 1445 1446static unsigned encodeVFPRn(const MachineInstr &MI, unsigned OpIdx) { 1447 unsigned RegN = MI.getOperand(OpIdx).getReg(); 1448 unsigned Binary = 0; 1449 bool isSPVFP = ARM::SPRRegisterClass->contains(RegN); 1450 RegN = getARMRegisterNumbering(RegN); 1451 if (!isSPVFP) 1452 Binary |= RegN << ARMII::RegRnShift; 1453 else { 1454 Binary |= ((RegN & 0x1E) >> 1) << ARMII::RegRnShift; 1455 Binary |= (RegN & 0x01) << ARMII::N_BitShift; 1456 } 1457 return Binary; 1458} 1459 1460static unsigned encodeVFPRm(const MachineInstr &MI, unsigned OpIdx) { 1461 unsigned RegM = MI.getOperand(OpIdx).getReg(); 1462 unsigned Binary = 0; 1463 bool isSPVFP = ARM::SPRRegisterClass->contains(RegM); 1464 RegM = getARMRegisterNumbering(RegM); 1465 if (!isSPVFP) 1466 Binary |= RegM; 1467 else { 1468 Binary |= ((RegM & 0x1E) >> 1); 1469 Binary |= (RegM & 0x01) << ARMII::M_BitShift; 1470 } 1471 return Binary; 1472} 1473 1474void ARMCodeEmitter::emitVFPArithInstruction(const MachineInstr &MI) { 1475 const TargetInstrDesc &TID = MI.getDesc(); 1476 1477 // Part of binary is determined by TableGn. 1478 unsigned Binary = getBinaryCodeForInstr(MI); 1479 1480 // Set the conditional execution predicate 1481 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1482 1483 unsigned OpIdx = 0; 1484 assert((Binary & ARMII::D_BitShift) == 0 && 1485 (Binary & ARMII::N_BitShift) == 0 && 1486 (Binary & ARMII::M_BitShift) == 0 && "VFP encoding bug!"); 1487 1488 // Encode Dd / Sd. 1489 Binary |= encodeVFPRd(MI, OpIdx++); 1490 1491 // If this is a two-address operand, skip it, e.g. FMACD. 1492 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1) 1493 ++OpIdx; 1494 1495 // Encode Dn / Sn. 1496 if ((TID.TSFlags & ARMII::FormMask) == ARMII::VFPBinaryFrm) 1497 Binary |= encodeVFPRn(MI, OpIdx++); 1498 1499 if (OpIdx == TID.getNumOperands() || 1500 TID.OpInfo[OpIdx].isPredicate() || 1501 TID.OpInfo[OpIdx].isOptionalDef()) { 1502 // FCMPEZD etc. has only one operand. 1503 emitWordLE(Binary); 1504 return; 1505 } 1506 1507 // Encode Dm / Sm. 1508 Binary |= encodeVFPRm(MI, OpIdx); 1509 1510 emitWordLE(Binary); 1511} 1512 1513void ARMCodeEmitter::emitVFPConversionInstruction(const MachineInstr &MI) { 1514 const TargetInstrDesc &TID = MI.getDesc(); 1515 unsigned Form = TID.TSFlags & ARMII::FormMask; 1516 1517 // Part of binary is determined by TableGn. 1518 unsigned Binary = getBinaryCodeForInstr(MI); 1519 1520 // Set the conditional execution predicate 1521 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1522 1523 switch (Form) { 1524 default: break; 1525 case ARMII::VFPConv1Frm: 1526 case ARMII::VFPConv2Frm: 1527 case ARMII::VFPConv3Frm: 1528 // Encode Dd / Sd. 1529 Binary |= encodeVFPRd(MI, 0); 1530 break; 1531 case ARMII::VFPConv4Frm: 1532 // Encode Dn / Sn. 1533 Binary |= encodeVFPRn(MI, 0); 1534 break; 1535 case ARMII::VFPConv5Frm: 1536 // Encode Dm / Sm. 1537 Binary |= encodeVFPRm(MI, 0); 1538 break; 1539 } 1540 1541 switch (Form) { 1542 default: break; 1543 case ARMII::VFPConv1Frm: 1544 // Encode Dm / Sm. 1545 Binary |= encodeVFPRm(MI, 1); 1546 break; 1547 case ARMII::VFPConv2Frm: 1548 case ARMII::VFPConv3Frm: 1549 // Encode Dn / Sn. 1550 Binary |= encodeVFPRn(MI, 1); 1551 break; 1552 case ARMII::VFPConv4Frm: 1553 case ARMII::VFPConv5Frm: 1554 // Encode Dd / Sd. 1555 Binary |= encodeVFPRd(MI, 1); 1556 break; 1557 } 1558 1559 if (Form == ARMII::VFPConv5Frm) 1560 // Encode Dn / Sn. 1561 Binary |= encodeVFPRn(MI, 2); 1562 else if (Form == ARMII::VFPConv3Frm) 1563 // Encode Dm / Sm. 1564 Binary |= encodeVFPRm(MI, 2); 1565 1566 emitWordLE(Binary); 1567} 1568 1569void ARMCodeEmitter::emitVFPLoadStoreInstruction(const MachineInstr &MI) { 1570 // Part of binary is determined by TableGn. 1571 unsigned Binary = getBinaryCodeForInstr(MI); 1572 1573 // Set the conditional execution predicate 1574 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1575 1576 unsigned OpIdx = 0; 1577 1578 // Encode Dd / Sd. 1579 Binary |= encodeVFPRd(MI, OpIdx++); 1580 1581 // Encode address base. 1582 const MachineOperand &Base = MI.getOperand(OpIdx++); 1583 Binary |= getMachineOpValue(MI, Base) << ARMII::RegRnShift; 1584 1585 // If there is a non-zero immediate offset, encode it. 1586 if (Base.isReg()) { 1587 const MachineOperand &Offset = MI.getOperand(OpIdx); 1588 if (unsigned ImmOffs = ARM_AM::getAM5Offset(Offset.getImm())) { 1589 if (ARM_AM::getAM5Op(Offset.getImm()) == ARM_AM::add) 1590 Binary |= 1 << ARMII::U_BitShift; 1591 Binary |= ImmOffs; 1592 emitWordLE(Binary); 1593 return; 1594 } 1595 } 1596 1597 // If immediate offset is omitted, default to +0. 1598 Binary |= 1 << ARMII::U_BitShift; 1599 1600 emitWordLE(Binary); 1601} 1602 1603void 1604ARMCodeEmitter::emitVFPLoadStoreMultipleInstruction(const MachineInstr &MI) { 1605 const TargetInstrDesc &TID = MI.getDesc(); 1606 bool IsUpdating = (TID.TSFlags & ARMII::IndexModeMask) != 0; 1607 1608 // Part of binary is determined by TableGn. 1609 unsigned Binary = getBinaryCodeForInstr(MI); 1610 1611 // Set the conditional execution predicate 1612 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1613 1614 // Skip operand 0 of an instruction with base register update. 1615 unsigned OpIdx = 0; 1616 if (IsUpdating) 1617 ++OpIdx; 1618 1619 // Set base address operand 1620 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift; 1621 1622 // Set addressing mode by modifying bits U(23) and P(24) 1623 const MachineOperand &MO = MI.getOperand(OpIdx++); 1624 Binary |= getAddrModeUPBits(ARM_AM::getAM4SubMode(MO.getImm())); 1625 1626 // Set bit W(21) 1627 if (IsUpdating) 1628 Binary |= 0x1 << ARMII::W_BitShift; 1629 1630 // First register is encoded in Dd. 1631 Binary |= encodeVFPRd(MI, OpIdx+2); 1632 1633 // Count the number of registers. 1634 unsigned NumRegs = 1; 1635 for (unsigned i = OpIdx+3, e = MI.getNumOperands(); i != e; ++i) { 1636 const MachineOperand &MO = MI.getOperand(i); 1637 if (!MO.isReg() || MO.isImplicit()) 1638 break; 1639 ++NumRegs; 1640 } 1641 // Bit 8 will be set if <list> is consecutive 64-bit registers (e.g., D0) 1642 // Otherwise, it will be 0, in the case of 32-bit registers. 1643 if(Binary & 0x100) 1644 Binary |= NumRegs * 2; 1645 else 1646 Binary |= NumRegs; 1647 1648 emitWordLE(Binary); 1649} 1650 1651static unsigned encodeNEONRd(const MachineInstr &MI, unsigned OpIdx) { 1652 unsigned RegD = MI.getOperand(OpIdx).getReg(); 1653 unsigned Binary = 0; 1654 RegD = getARMRegisterNumbering(RegD); 1655 Binary |= (RegD & 0xf) << ARMII::RegRdShift; 1656 Binary |= ((RegD >> 4) & 1) << ARMII::D_BitShift; 1657 return Binary; 1658} 1659 1660static unsigned encodeNEONRn(const MachineInstr &MI, unsigned OpIdx) { 1661 unsigned RegN = MI.getOperand(OpIdx).getReg(); 1662 unsigned Binary = 0; 1663 RegN = getARMRegisterNumbering(RegN); 1664 Binary |= (RegN & 0xf) << ARMII::RegRnShift; 1665 Binary |= ((RegN >> 4) & 1) << ARMII::N_BitShift; 1666 return Binary; 1667} 1668 1669static unsigned encodeNEONRm(const MachineInstr &MI, unsigned OpIdx) { 1670 unsigned RegM = MI.getOperand(OpIdx).getReg(); 1671 unsigned Binary = 0; 1672 RegM = getARMRegisterNumbering(RegM); 1673 Binary |= (RegM & 0xf); 1674 Binary |= ((RegM >> 4) & 1) << ARMII::M_BitShift; 1675 return Binary; 1676} 1677 1678/// convertNEONDataProcToThumb - Convert the ARM mode encoding for a NEON 1679/// data-processing instruction to the corresponding Thumb encoding. 1680static unsigned convertNEONDataProcToThumb(unsigned Binary) { 1681 assert((Binary & 0xfe000000) == 0xf2000000 && 1682 "not an ARM NEON data-processing instruction"); 1683 unsigned UBit = (Binary >> 24) & 1; 1684 return 0xef000000 | (UBit << 28) | (Binary & 0xffffff); 1685} 1686 1687void ARMCodeEmitter::emitNEONLaneInstruction(const MachineInstr &MI) { 1688 unsigned Binary = getBinaryCodeForInstr(MI); 1689 1690 unsigned RegTOpIdx, RegNOpIdx, LnOpIdx; 1691 const TargetInstrDesc &TID = MI.getDesc(); 1692 if ((TID.TSFlags & ARMII::FormMask) == ARMII::NGetLnFrm) { 1693 RegTOpIdx = 0; 1694 RegNOpIdx = 1; 1695 LnOpIdx = 2; 1696 } else { // ARMII::NSetLnFrm 1697 RegTOpIdx = 2; 1698 RegNOpIdx = 0; 1699 LnOpIdx = 3; 1700 } 1701 1702 // Set the conditional execution predicate 1703 Binary |= (IsThumb ? ARMCC::AL : II->getPredicate(&MI)) << ARMII::CondShift; 1704 1705 unsigned RegT = MI.getOperand(RegTOpIdx).getReg(); 1706 RegT = getARMRegisterNumbering(RegT); 1707 Binary |= (RegT << ARMII::RegRdShift); 1708 Binary |= encodeNEONRn(MI, RegNOpIdx); 1709 1710 unsigned LaneShift; 1711 if ((Binary & (1 << 22)) != 0) 1712 LaneShift = 0; // 8-bit elements 1713 else if ((Binary & (1 << 5)) != 0) 1714 LaneShift = 1; // 16-bit elements 1715 else 1716 LaneShift = 2; // 32-bit elements 1717 1718 unsigned Lane = MI.getOperand(LnOpIdx).getImm() << LaneShift; 1719 unsigned Opc1 = Lane >> 2; 1720 unsigned Opc2 = Lane & 3; 1721 assert((Opc1 & 3) == 0 && "out-of-range lane number operand"); 1722 Binary |= (Opc1 << 21); 1723 Binary |= (Opc2 << 5); 1724 1725 emitWordLE(Binary); 1726} 1727 1728void ARMCodeEmitter::emitNEONDupInstruction(const MachineInstr &MI) { 1729 unsigned Binary = getBinaryCodeForInstr(MI); 1730 1731 // Set the conditional execution predicate 1732 Binary |= (IsThumb ? ARMCC::AL : II->getPredicate(&MI)) << ARMII::CondShift; 1733 1734 unsigned RegT = MI.getOperand(1).getReg(); 1735 RegT = getARMRegisterNumbering(RegT); 1736 Binary |= (RegT << ARMII::RegRdShift); 1737 Binary |= encodeNEONRn(MI, 0); 1738 emitWordLE(Binary); 1739} 1740 1741void ARMCodeEmitter::emitNEON1RegModImmInstruction(const MachineInstr &MI) { 1742 unsigned Binary = getBinaryCodeForInstr(MI); 1743 // Destination register is encoded in Dd. 1744 Binary |= encodeNEONRd(MI, 0); 1745 // Immediate fields: Op, Cmode, I, Imm3, Imm4 1746 unsigned Imm = MI.getOperand(1).getImm(); 1747 unsigned Op = (Imm >> 12) & 1; 1748 unsigned Cmode = (Imm >> 8) & 0xf; 1749 unsigned I = (Imm >> 7) & 1; 1750 unsigned Imm3 = (Imm >> 4) & 0x7; 1751 unsigned Imm4 = Imm & 0xf; 1752 Binary |= (I << 24) | (Imm3 << 16) | (Cmode << 8) | (Op << 5) | Imm4; 1753 if (IsThumb) 1754 Binary = convertNEONDataProcToThumb(Binary); 1755 emitWordLE(Binary); 1756} 1757 1758void ARMCodeEmitter::emitNEON2RegInstruction(const MachineInstr &MI) { 1759 const TargetInstrDesc &TID = MI.getDesc(); 1760 unsigned Binary = getBinaryCodeForInstr(MI); 1761 // Destination register is encoded in Dd; source register in Dm. 1762 unsigned OpIdx = 0; 1763 Binary |= encodeNEONRd(MI, OpIdx++); 1764 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1) 1765 ++OpIdx; 1766 Binary |= encodeNEONRm(MI, OpIdx); 1767 if (IsThumb) 1768 Binary = convertNEONDataProcToThumb(Binary); 1769 // FIXME: This does not handle VDUPfdf or VDUPfqf. 1770 emitWordLE(Binary); 1771} 1772 1773void ARMCodeEmitter::emitNEON3RegInstruction(const MachineInstr &MI) { 1774 const TargetInstrDesc &TID = MI.getDesc(); 1775 unsigned Binary = getBinaryCodeForInstr(MI); 1776 // Destination register is encoded in Dd; source registers in Dn and Dm. 1777 unsigned OpIdx = 0; 1778 Binary |= encodeNEONRd(MI, OpIdx++); 1779 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1) 1780 ++OpIdx; 1781 Binary |= encodeNEONRn(MI, OpIdx++); 1782 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1) 1783 ++OpIdx; 1784 Binary |= encodeNEONRm(MI, OpIdx); 1785 if (IsThumb) 1786 Binary = convertNEONDataProcToThumb(Binary); 1787 // FIXME: This does not handle VMOVDneon or VMOVQ. 1788 emitWordLE(Binary); 1789} 1790 1791#include "ARMGenCodeEmitter.inc" 1792