ARMCodeEmitter.cpp revision 57dac88f775c1191a98cff89abd1f7ad33df5e29 
1//===-- ARM/ARMCodeEmitter.cpp - Convert ARM code to machine code ---------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the pass that transforms the ARM machine instructions into
11// relocatable machine code.
12//
13//===----------------------------------------------------------------------===//
14
15#define DEBUG_TYPE "jit"
16#include "ARM.h"
17#include "ARMAddressingModes.h"
18#include "ARMConstantPoolValue.h"
19#include "ARMInstrInfo.h"
20#include "ARMRelocations.h"
21#include "ARMSubtarget.h"
22#include "ARMTargetMachine.h"
23#include "llvm/Constants.h"
24#include "llvm/DerivedTypes.h"
25#include "llvm/Function.h"
26#include "llvm/PassManager.h"
27#include "llvm/CodeGen/JITCodeEmitter.h"
28#include "llvm/CodeGen/MachineConstantPool.h"
29#include "llvm/CodeGen/MachineFunctionPass.h"
30#include "llvm/CodeGen/MachineInstr.h"
31#include "llvm/CodeGen/MachineJumpTableInfo.h"
32#include "llvm/CodeGen/MachineModuleInfo.h"
33#include "llvm/CodeGen/Passes.h"
34#include "llvm/ADT/Statistic.h"
35#include "llvm/Support/Debug.h"
36#include "llvm/Support/ErrorHandling.h"
37#include "llvm/Support/raw_ostream.h"
38#ifndef NDEBUG
39#include <iomanip>
40#endif
41using namespace llvm;
42
43STATISTIC(NumEmitted, "Number of machine instructions emitted");
44
45namespace {
46
47  class ARMCodeEmitter : public MachineFunctionPass {
48    ARMJITInfo                *JTI;
49    const ARMInstrInfo        *II;
50    const TargetData          *TD;
51    const ARMSubtarget        *Subtarget;
52    TargetMachine             &TM;
53    JITCodeEmitter            &MCE;
54    MachineModuleInfo *MMI;
55    const std::vector<MachineConstantPoolEntry> *MCPEs;
56    const std::vector<MachineJumpTableEntry> *MJTEs;
57    bool IsPIC;
58    bool IsThumb;
59
60    void getAnalysisUsage(AnalysisUsage &AU) const {
61      AU.addRequired<MachineModuleInfo>();
62      MachineFunctionPass::getAnalysisUsage(AU);
63    }
64
65    static char ID;
66  public:
67    ARMCodeEmitter(TargetMachine &tm, JITCodeEmitter &mce)
68      : MachineFunctionPass(ID), JTI(0),
69        II((const ARMInstrInfo *)tm.getInstrInfo()),
70        TD(tm.getTargetData()), TM(tm),
71        MCE(mce), MCPEs(0), MJTEs(0),
72        IsPIC(TM.getRelocationModel() == Reloc::PIC_), IsThumb(false) {}
73
74    /// getBinaryCodeForInstr - This function, generated by the
75    /// CodeEmitterGenerator using TableGen, produces the binary encoding for
76    /// machine instructions.
77    unsigned getBinaryCodeForInstr(const MachineInstr &MI) const;
78
79    bool runOnMachineFunction(MachineFunction &MF);
80
81    virtual const char *getPassName() const {
82      return "ARM Machine Code Emitter";
83    }
84
85    void emitInstruction(const MachineInstr &MI);
86
87  private:
88
89    void emitWordLE(unsigned Binary);
90    void emitDWordLE(uint64_t Binary);
91    void emitConstPoolInstruction(const MachineInstr &MI);
92    void emitMOVi32immInstruction(const MachineInstr &MI);
93    void emitMOVi2piecesInstruction(const MachineInstr &MI);
94    void emitLEApcrelJTInstruction(const MachineInstr &MI);
95    void emitPseudoMoveInstruction(const MachineInstr &MI);
96    void addPCLabel(unsigned LabelID);
97    void emitPseudoInstruction(const MachineInstr &MI);
98    unsigned getMachineSoRegOpValue(const MachineInstr &MI,
99                                    const TargetInstrDesc &TID,
100                                    const MachineOperand &MO,
101                                    unsigned OpIdx);
102
103    unsigned getMachineSoImmOpValue(unsigned SoImm);
104    unsigned getAddrModeSBit(const MachineInstr &MI,
105                             const TargetInstrDesc &TID) const;
106
107    void emitDataProcessingInstruction(const MachineInstr &MI,
108                                       unsigned ImplicitRd = 0,
109                                       unsigned ImplicitRn = 0);
110
111    void emitLoadStoreInstruction(const MachineInstr &MI,
112                                  unsigned ImplicitRd = 0,
113                                  unsigned ImplicitRn = 0);
114
115    void emitMiscLoadStoreInstruction(const MachineInstr &MI,
116                                      unsigned ImplicitRn = 0);
117
118    void emitLoadStoreMultipleInstruction(const MachineInstr &MI);
119
120    void emitMulFrmInstruction(const MachineInstr &MI);
121
122    void emitExtendInstruction(const MachineInstr &MI);
123
124    void emitMiscArithInstruction(const MachineInstr &MI);
125
126    void emitSaturateInstruction(const MachineInstr &MI);
127
128    void emitBranchInstruction(const MachineInstr &MI);
129
130    void emitInlineJumpTable(unsigned JTIndex);
131
132    void emitMiscBranchInstruction(const MachineInstr &MI);
133
134    void emitVFPArithInstruction(const MachineInstr &MI);
135
136    void emitVFPConversionInstruction(const MachineInstr &MI);
137
138    void emitVFPLoadStoreInstruction(const MachineInstr &MI);
139
140    void emitVFPLoadStoreMultipleInstruction(const MachineInstr &MI);
141
142    void emitNEONLaneInstruction(const MachineInstr &MI);
143    void emitNEONDupInstruction(const MachineInstr &MI);
144    void emitNEON1RegModImmInstruction(const MachineInstr &MI);
145    void emitNEON2RegInstruction(const MachineInstr &MI);
146    void emitNEON3RegInstruction(const MachineInstr &MI);
147
148    /// getMachineOpValue - Return binary encoding of operand. If the machine
149    /// operand requires relocation, record the relocation and return zero.
150    unsigned getMachineOpValue(const MachineInstr &MI,
151                               const MachineOperand &MO) const;
152    unsigned getMachineOpValue(const MachineInstr &MI, unsigned OpIdx) const {
153      return getMachineOpValue(MI, MI.getOperand(OpIdx));
154    }
155
156    // FIXME: The legacy JIT ARMCodeEmitter doesn't rely on the the
157    //  TableGen'erated getBinaryCodeForInstr() function to encode any
158    //  operand values, instead querying getMachineOpValue() directly for
159    //  each operand it needs to encode. Thus, any of the new encoder
160    //  helper functions can simply return 0 as the values the return
161    //  are already handled elsewhere. They are placeholders to allow this
162    //  encoder to continue to function until the MC encoder is sufficiently
163    //  far along that this one can be eliminated entirely.
164    unsigned NEONThumb2DataIPostEncoder(const MachineInstr &MI, unsigned Val)
165      const { return 0; }
166    unsigned NEONThumb2LoadStorePostEncoder(const MachineInstr &MI,unsigned Val)
167      const { return 0; }
168    unsigned getBranchTargetOpValue(const MachineInstr &MI, unsigned Op)
169      const { return 0; }
170    unsigned getCCOutOpValue(const MachineInstr &MI, unsigned Op)
171      const { return 0; }
172    unsigned getSOImmOpValue(const MachineInstr &MI, unsigned Op)
173      const { return 0; }
174    unsigned getSORegOpValue(const MachineInstr &MI, unsigned Op)
175      const { return 0; }
176    unsigned getRotImmOpValue(const MachineInstr &MI, unsigned Op)
177      const { return 0; }
178    unsigned getImmMinusOneOpValue(const MachineInstr &MI, unsigned Op)
179      const { return 0; }
180    unsigned getAddrMode6AddressOpValue(const MachineInstr &MI, unsigned Op)
181      const { return 0; }
182    unsigned getAddrMode6OffsetOpValue(const MachineInstr &MI, unsigned Op)
183      const { return 0; }
184    unsigned getBitfieldInvertedMaskOpValue(const MachineInstr &MI,
185                                            unsigned Op) const { return 0; }
186    uint32_t getLdStmModeOpValue(const MachineInstr &MI, unsigned OpIdx)
187      const {return 0; }
188    uint32_t getLdStSORegOpValue(const MachineInstr &MI, unsigned OpIdx)
189      const { return 0; }
190
191    unsigned getAddrModeImm12OpValue(const MachineInstr &MI, unsigned Op)
192      const {
193      // {17-13} = reg
194      // {12}    = (U)nsigned (add == '1', sub == '0')
195      // {11-0}  = imm12
196      const MachineOperand &MO  = MI.getOperand(Op);
197      const MachineOperand &MO1 = MI.getOperand(Op + 1);
198      if (!MO.isReg()) {
199        emitConstPoolAddress(MO.getIndex(), ARM::reloc_arm_cp_entry);
200        return 0;
201      }
202      unsigned Reg = getARMRegisterNumbering(MO.getReg());
203      int32_t Imm12 = MO1.getImm();
204      uint32_t Binary;
205      Binary = Imm12 & 0xfff;
206      if (Imm12 >= 0)
207        Binary |= (1 << 12);
208      Binary |= (Reg << 13);
209      return Binary;
210    }
211    uint32_t getAddrMode3OffsetOpValue(const MachineInstr &MI, unsigned OpIdx)
212      const { return 0;}
213    uint32_t getAddrMode3OpValue(const MachineInstr &MI, unsigned Op) const
214      { return 0; }
215    uint32_t getAddrMode5OpValue(const MachineInstr &MI, unsigned Op) const {
216      // {12-9}  = reg
217      // {8}     = (U)nsigned (add == '1', sub == '0')
218      // {7-0}   = imm12
219      const MachineOperand &MO  = MI.getOperand(Op);
220      const MachineOperand &MO1 = MI.getOperand(Op + 1);
221      if (!MO.isReg()) {
222        emitConstPoolAddress(MO.getIndex(), ARM::reloc_arm_cp_entry);
223        return 0;
224      }
225      unsigned Reg = getARMRegisterNumbering(MO.getReg());
226      int32_t Imm8 = MO1.getImm();
227      uint32_t Binary;
228      Binary = Imm8 & 0xff;
229      if (Imm8 >= 0)
230        Binary |= (1 << 8);
231      Binary |= (Reg << 9);
232      return Binary;
233    }
234    unsigned getNEONVcvtImm32OpValue(const MachineInstr &MI, unsigned Op)
235      const { return 0; }
236
237    unsigned getRegisterListOpValue(const MachineInstr &MI, unsigned Op)
238      const { return 0; }
239
240    /// getMovi32Value - Return binary encoding of operand for movw/movt. If the
241    /// machine operand requires relocation, record the relocation and return
242    /// zero.
243    unsigned getMovi32Value(const MachineInstr &MI,const MachineOperand &MO,
244                            unsigned Reloc);
245
246    /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
247    ///
248    unsigned getShiftOp(unsigned Imm) const ;
249
250    /// Routines that handle operands which add machine relocations which are
251    /// fixed up by the relocation stage.
252    void emitGlobalAddress(const GlobalValue *GV, unsigned Reloc,
253                           bool MayNeedFarStub,  bool Indirect,
254                           intptr_t ACPV = 0) const;
255    void emitExternalSymbolAddress(const char *ES, unsigned Reloc) const;
256    void emitConstPoolAddress(unsigned CPI, unsigned Reloc) const;
257    void emitJumpTableAddress(unsigned JTIndex, unsigned Reloc) const;
258    void emitMachineBasicBlock(MachineBasicBlock *BB, unsigned Reloc,
259                               intptr_t JTBase = 0) const;
260  };
261}
262
263char ARMCodeEmitter::ID = 0;
264
265/// createARMJITCodeEmitterPass - Return a pass that emits the collected ARM
266/// code to the specified MCE object.
267FunctionPass *llvm::createARMJITCodeEmitterPass(ARMBaseTargetMachine &TM,
268                                                JITCodeEmitter &JCE) {
269  return new ARMCodeEmitter(TM, JCE);
270}
271
272bool ARMCodeEmitter::runOnMachineFunction(MachineFunction &MF) {
273  assert((MF.getTarget().getRelocationModel() != Reloc::Default ||
274          MF.getTarget().getRelocationModel() != Reloc::Static) &&
275         "JIT relocation model must be set to static or default!");
276  JTI = ((ARMTargetMachine &)MF.getTarget()).getJITInfo();
277  II = ((const ARMTargetMachine &)MF.getTarget()).getInstrInfo();
278  TD = ((const ARMTargetMachine &)MF.getTarget()).getTargetData();
279  Subtarget = &TM.getSubtarget<ARMSubtarget>();
280  MCPEs = &MF.getConstantPool()->getConstants();
281  MJTEs = 0;
282  if (MF.getJumpTableInfo()) MJTEs = &MF.getJumpTableInfo()->getJumpTables();
283  IsPIC = TM.getRelocationModel() == Reloc::PIC_;
284  IsThumb = MF.getInfo<ARMFunctionInfo>()->isThumbFunction();
285  JTI->Initialize(MF, IsPIC);
286  MMI = &getAnalysis<MachineModuleInfo>();
287  MCE.setModuleInfo(MMI);
288
289  do {
290    DEBUG(errs() << "JITTing function '"
291          << MF.getFunction()->getName() << "'\n");
292    MCE.startFunction(MF);
293    for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();
294         MBB != E; ++MBB) {
295      MCE.StartMachineBasicBlock(MBB);
296      for (MachineBasicBlock::const_iterator I = MBB->begin(), E = MBB->end();
297           I != E; ++I)
298        emitInstruction(*I);
299    }
300  } while (MCE.finishFunction(MF));
301
302  return false;
303}
304
305/// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
306///
307unsigned ARMCodeEmitter::getShiftOp(unsigned Imm) const {
308  switch (ARM_AM::getAM2ShiftOpc(Imm)) {
309  default: llvm_unreachable("Unknown shift opc!");
310  case ARM_AM::asr: return 2;
311  case ARM_AM::lsl: return 0;
312  case ARM_AM::lsr: return 1;
313  case ARM_AM::ror:
314  case ARM_AM::rrx: return 3;
315  }
316  return 0;
317}
318
319/// getMovi32Value - Return binary encoding of operand for movw/movt. If the
320/// machine operand requires relocation, record the relocation and return zero.
321unsigned ARMCodeEmitter::getMovi32Value(const MachineInstr &MI,
322                                        const MachineOperand &MO,
323                                        unsigned Reloc) {
324  assert(((Reloc == ARM::reloc_arm_movt) || (Reloc == ARM::reloc_arm_movw))
325      && "Relocation to this function should be for movt or movw");
326
327  if (MO.isImm())
328    return static_cast<unsigned>(MO.getImm());
329  else if (MO.isGlobal())
330    emitGlobalAddress(MO.getGlobal(), Reloc, true, false);
331  else if (MO.isSymbol())
332    emitExternalSymbolAddress(MO.getSymbolName(), Reloc);
333  else if (MO.isMBB())
334    emitMachineBasicBlock(MO.getMBB(), Reloc);
335  else {
336#ifndef NDEBUG
337    errs() << MO;
338#endif
339    llvm_unreachable("Unsupported operand type for movw/movt");
340  }
341  return 0;
342}
343
344/// getMachineOpValue - Return binary encoding of operand. If the machine
345/// operand requires relocation, record the relocation and return zero.
346unsigned ARMCodeEmitter::getMachineOpValue(const MachineInstr &MI,
347                                           const MachineOperand &MO) const {
348  if (MO.isReg())
349    return getARMRegisterNumbering(MO.getReg());
350  else if (MO.isImm())
351    return static_cast<unsigned>(MO.getImm());
352  else if (MO.isGlobal())
353    emitGlobalAddress(MO.getGlobal(), ARM::reloc_arm_branch, true, false);
354  else if (MO.isSymbol())
355    emitExternalSymbolAddress(MO.getSymbolName(), ARM::reloc_arm_branch);
356  else if (MO.isCPI()) {
357    const TargetInstrDesc &TID = MI.getDesc();
358    // For VFP load, the immediate offset is multiplied by 4.
359    unsigned Reloc =  ((TID.TSFlags & ARMII::FormMask) == ARMII::VFPLdStFrm)
360      ? ARM::reloc_arm_vfp_cp_entry : ARM::reloc_arm_cp_entry;
361    emitConstPoolAddress(MO.getIndex(), Reloc);
362  } else if (MO.isJTI())
363    emitJumpTableAddress(MO.getIndex(), ARM::reloc_arm_relative);
364  else if (MO.isMBB())
365    emitMachineBasicBlock(MO.getMBB(), ARM::reloc_arm_branch);
366  else {
367#ifndef NDEBUG
368    errs() << MO;
369#endif
370    llvm_unreachable(0);
371  }
372  return 0;
373}
374
375/// emitGlobalAddress - Emit the specified address to the code stream.
376///
377void ARMCodeEmitter::emitGlobalAddress(const GlobalValue *GV, unsigned Reloc,
378                                       bool MayNeedFarStub, bool Indirect,
379                                       intptr_t ACPV) const {
380  MachineRelocation MR = Indirect
381    ? MachineRelocation::getIndirectSymbol(MCE.getCurrentPCOffset(), Reloc,
382                                           const_cast<GlobalValue *>(GV),
383                                           ACPV, MayNeedFarStub)
384    : MachineRelocation::getGV(MCE.getCurrentPCOffset(), Reloc,
385                               const_cast<GlobalValue *>(GV), ACPV,
386                               MayNeedFarStub);
387  MCE.addRelocation(MR);
388}
389
390/// emitExternalSymbolAddress - Arrange for the address of an external symbol to
391/// be emitted to the current location in the function, and allow it to be PC
392/// relative.
393void ARMCodeEmitter::
394emitExternalSymbolAddress(const char *ES, unsigned Reloc) const {
395  MCE.addRelocation(MachineRelocation::getExtSym(MCE.getCurrentPCOffset(),
396                                                 Reloc, ES));
397}
398
399/// emitConstPoolAddress - Arrange for the address of an constant pool
400/// to be emitted to the current location in the function, and allow it to be PC
401/// relative.
402void ARMCodeEmitter::emitConstPoolAddress(unsigned CPI, unsigned Reloc) const {
403  // Tell JIT emitter we'll resolve the address.
404  MCE.addRelocation(MachineRelocation::getConstPool(MCE.getCurrentPCOffset(),
405                                                    Reloc, CPI, 0, true));
406}
407
408/// emitJumpTableAddress - Arrange for the address of a jump table to
409/// be emitted to the current location in the function, and allow it to be PC
410/// relative.
411void ARMCodeEmitter::
412emitJumpTableAddress(unsigned JTIndex, unsigned Reloc) const {
413  MCE.addRelocation(MachineRelocation::getJumpTable(MCE.getCurrentPCOffset(),
414                                                    Reloc, JTIndex, 0, true));
415}
416
417/// emitMachineBasicBlock - Emit the specified address basic block.
418void ARMCodeEmitter::emitMachineBasicBlock(MachineBasicBlock *BB,
419                                           unsigned Reloc,
420                                           intptr_t JTBase) const {
421  MCE.addRelocation(MachineRelocation::getBB(MCE.getCurrentPCOffset(),
422                                             Reloc, BB, JTBase));
423}
424
425void ARMCodeEmitter::emitWordLE(unsigned Binary) {
426  DEBUG(errs() << "  0x";
427        errs().write_hex(Binary) << "\n");
428  MCE.emitWordLE(Binary);
429}
430
431void ARMCodeEmitter::emitDWordLE(uint64_t Binary) {
432  DEBUG(errs() << "  0x";
433        errs().write_hex(Binary) << "\n");
434  MCE.emitDWordLE(Binary);
435}
436
437void ARMCodeEmitter::emitInstruction(const MachineInstr &MI) {
438  DEBUG(errs() << "JIT: " << (void*)MCE.getCurrentPCValue() << ":\t" << MI);
439
440  MCE.processDebugLoc(MI.getDebugLoc(), true);
441
442  ++NumEmitted;  // Keep track of the # of mi's emitted
443  switch (MI.getDesc().TSFlags & ARMII::FormMask) {
444  default: {
445    llvm_unreachable("Unhandled instruction encoding format!");
446    break;
447  }
448  case ARMII::Pseudo:
449    emitPseudoInstruction(MI);
450    break;
451  case ARMII::DPFrm:
452  case ARMII::DPSoRegFrm:
453    emitDataProcessingInstruction(MI);
454    break;
455  case ARMII::LdFrm:
456  case ARMII::StFrm:
457    emitLoadStoreInstruction(MI);
458    break;
459  case ARMII::LdMiscFrm:
460  case ARMII::StMiscFrm:
461    emitMiscLoadStoreInstruction(MI);
462    break;
463  case ARMII::LdStMulFrm:
464    emitLoadStoreMultipleInstruction(MI);
465    break;
466  case ARMII::MulFrm:
467    emitMulFrmInstruction(MI);
468    break;
469  case ARMII::ExtFrm:
470    emitExtendInstruction(MI);
471    break;
472  case ARMII::ArithMiscFrm:
473    emitMiscArithInstruction(MI);
474    break;
475  case ARMII::SatFrm:
476    emitSaturateInstruction(MI);
477    break;
478  case ARMII::BrFrm:
479    emitBranchInstruction(MI);
480    break;
481  case ARMII::BrMiscFrm:
482    emitMiscBranchInstruction(MI);
483    break;
484  // VFP instructions.
485  case ARMII::VFPUnaryFrm:
486  case ARMII::VFPBinaryFrm:
487    emitVFPArithInstruction(MI);
488    break;
489  case ARMII::VFPConv1Frm:
490  case ARMII::VFPConv2Frm:
491  case ARMII::VFPConv3Frm:
492  case ARMII::VFPConv4Frm:
493  case ARMII::VFPConv5Frm:
494    emitVFPConversionInstruction(MI);
495    break;
496  case ARMII::VFPLdStFrm:
497    emitVFPLoadStoreInstruction(MI);
498    break;
499  case ARMII::VFPLdStMulFrm:
500    emitVFPLoadStoreMultipleInstruction(MI);
501    break;
502
503  // NEON instructions.
504  case ARMII::NGetLnFrm:
505  case ARMII::NSetLnFrm:
506    emitNEONLaneInstruction(MI);
507    break;
508  case ARMII::NDupFrm:
509    emitNEONDupInstruction(MI);
510    break;
511  case ARMII::N1RegModImmFrm:
512    emitNEON1RegModImmInstruction(MI);
513    break;
514  case ARMII::N2RegFrm:
515    emitNEON2RegInstruction(MI);
516    break;
517  case ARMII::N3RegFrm:
518    emitNEON3RegInstruction(MI);
519    break;
520  }
521  MCE.processDebugLoc(MI.getDebugLoc(), false);
522}
523
524void ARMCodeEmitter::emitConstPoolInstruction(const MachineInstr &MI) {
525  unsigned CPI = MI.getOperand(0).getImm();       // CP instruction index.
526  unsigned CPIndex = MI.getOperand(1).getIndex(); // Actual cp entry index.
527  const MachineConstantPoolEntry &MCPE = (*MCPEs)[CPIndex];
528
529  // Remember the CONSTPOOL_ENTRY address for later relocation.
530  JTI->addConstantPoolEntryAddr(CPI, MCE.getCurrentPCValue());
531
532  // Emit constpool island entry. In most cases, the actual values will be
533  // resolved and relocated after code emission.
534  if (MCPE.isMachineConstantPoolEntry()) {
535    ARMConstantPoolValue *ACPV =
536      static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal);
537
538    DEBUG(errs() << "  ** ARM constant pool #" << CPI << " @ "
539          << (void*)MCE.getCurrentPCValue() << " " << *ACPV << '\n');
540
541    assert(ACPV->isGlobalValue() && "unsupported constant pool value");
542    const GlobalValue *GV = ACPV->getGV();
543    if (GV) {
544      Reloc::Model RelocM = TM.getRelocationModel();
545      emitGlobalAddress(GV, ARM::reloc_arm_machine_cp_entry,
546                        isa<Function>(GV),
547                        Subtarget->GVIsIndirectSymbol(GV, RelocM),
548                        (intptr_t)ACPV);
549     } else  {
550      emitExternalSymbolAddress(ACPV->getSymbol(), ARM::reloc_arm_absolute);
551    }
552    emitWordLE(0);
553  } else {
554    const Constant *CV = MCPE.Val.ConstVal;
555
556    DEBUG({
557        errs() << "  ** Constant pool #" << CPI << " @ "
558               << (void*)MCE.getCurrentPCValue() << " ";
559        if (const Function *F = dyn_cast<Function>(CV))
560          errs() << F->getName();
561        else
562          errs() << *CV;
563        errs() << '\n';
564      });
565
566    if (const GlobalValue *GV = dyn_cast<GlobalValue>(CV)) {
567      emitGlobalAddress(GV, ARM::reloc_arm_absolute, isa<Function>(GV), false);
568      emitWordLE(0);
569    } else if (const ConstantInt *CI = dyn_cast<ConstantInt>(CV)) {
570      uint32_t Val = uint32_t(*CI->getValue().getRawData());
571      emitWordLE(Val);
572    } else if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CV)) {
573      if (CFP->getType()->isFloatTy())
574        emitWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue());
575      else if (CFP->getType()->isDoubleTy())
576        emitDWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue());
577      else {
578        llvm_unreachable("Unable to handle this constantpool entry!");
579      }
580    } else {
581      llvm_unreachable("Unable to handle this constantpool entry!");
582    }
583  }
584}
585
586void ARMCodeEmitter::emitMOVi32immInstruction(const MachineInstr &MI) {
587  const MachineOperand &MO0 = MI.getOperand(0);
588  const MachineOperand &MO1 = MI.getOperand(1);
589
590  // Emit the 'movw' instruction.
591  unsigned Binary = 0x30 << 20;  // mov: Insts{27-20} = 0b00110000
592
593  unsigned Lo16 = getMovi32Value(MI, MO1, ARM::reloc_arm_movw) & 0xFFFF;
594
595  // Set the conditional execution predicate.
596  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
597
598  // Encode Rd.
599  Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
600
601  // Encode imm16 as imm4:imm12
602  Binary |= Lo16 & 0xFFF; // Insts{11-0} = imm12
603  Binary |= ((Lo16 >> 12) & 0xF) << 16; // Insts{19-16} = imm4
604  emitWordLE(Binary);
605
606  unsigned Hi16 = getMovi32Value(MI, MO1, ARM::reloc_arm_movt) >> 16;
607  // Emit the 'movt' instruction.
608  Binary = 0x34 << 20; // movt: Insts{27-20} = 0b00110100
609
610  // Set the conditional execution predicate.
611  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
612
613  // Encode Rd.
614  Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
615
616  // Encode imm16 as imm4:imm1, same as movw above.
617  Binary |= Hi16 & 0xFFF;
618  Binary |= ((Hi16 >> 12) & 0xF) << 16;
619  emitWordLE(Binary);
620}
621
622void ARMCodeEmitter::emitMOVi2piecesInstruction(const MachineInstr &MI) {
623  const MachineOperand &MO0 = MI.getOperand(0);
624  const MachineOperand &MO1 = MI.getOperand(1);
625  assert(MO1.isImm() && ARM_AM::isSOImmTwoPartVal(MO1.getImm()) &&
626                                                  "Not a valid so_imm value!");
627  unsigned V1 = ARM_AM::getSOImmTwoPartFirst(MO1.getImm());
628  unsigned V2 = ARM_AM::getSOImmTwoPartSecond(MO1.getImm());
629
630  // Emit the 'mov' instruction.
631  unsigned Binary = 0xd << 21;  // mov: Insts{24-21} = 0b1101
632
633  // Set the conditional execution predicate.
634  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
635
636  // Encode Rd.
637  Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
638
639  // Encode so_imm.
640  // Set bit I(25) to identify this is the immediate form of <shifter_op>
641  Binary |= 1 << ARMII::I_BitShift;
642  Binary |= getMachineSoImmOpValue(V1);
643  emitWordLE(Binary);
644
645  // Now the 'orr' instruction.
646  Binary = 0xc << 21;  // orr: Insts{24-21} = 0b1100
647
648  // Set the conditional execution predicate.
649  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
650
651  // Encode Rd.
652  Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
653
654  // Encode Rn.
655  Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRnShift;
656
657  // Encode so_imm.
658  // Set bit I(25) to identify this is the immediate form of <shifter_op>
659  Binary |= 1 << ARMII::I_BitShift;
660  Binary |= getMachineSoImmOpValue(V2);
661  emitWordLE(Binary);
662}
663
664void ARMCodeEmitter::emitLEApcrelJTInstruction(const MachineInstr &MI) {
665  // It's basically add r, pc, (LJTI - $+8)
666
667  const TargetInstrDesc &TID = MI.getDesc();
668
669  // Emit the 'add' instruction.
670  unsigned Binary = 0x4 << 21;  // add: Insts{24-31} = 0b0100
671
672  // Set the conditional execution predicate
673  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
674
675  // Encode S bit if MI modifies CPSR.
676  Binary |= getAddrModeSBit(MI, TID);
677
678  // Encode Rd.
679  Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
680
681  // Encode Rn which is PC.
682  Binary |= getARMRegisterNumbering(ARM::PC) << ARMII::RegRnShift;
683
684  // Encode the displacement.
685  Binary |= 1 << ARMII::I_BitShift;
686  emitJumpTableAddress(MI.getOperand(1).getIndex(), ARM::reloc_arm_jt_base);
687
688  emitWordLE(Binary);
689}
690
691void ARMCodeEmitter::emitPseudoMoveInstruction(const MachineInstr &MI) {
692  unsigned Opcode = MI.getDesc().Opcode;
693
694  // Part of binary is determined by TableGn.
695  unsigned Binary = getBinaryCodeForInstr(MI);
696
697  // Set the conditional execution predicate
698  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
699
700  // Encode S bit if MI modifies CPSR.
701  if (Opcode == ARM::MOVsrl_flag || Opcode == ARM::MOVsra_flag)
702    Binary |= 1 << ARMII::S_BitShift;
703
704  // Encode register def if there is one.
705  Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
706
707  // Encode the shift operation.
708  switch (Opcode) {
709  default: break;
710  case ARM::RRX:
711    // rrx
712    Binary |= 0x6 << 4;
713    break;
714  case ARM::MOVsrl_flag:
715    // lsr #1
716    Binary |= (0x2 << 4) | (1 << 7);
717    break;
718  case ARM::MOVsra_flag:
719    // asr #1
720    Binary |= (0x4 << 4) | (1 << 7);
721    break;
722  }
723
724  // Encode register Rm.
725  Binary |= getMachineOpValue(MI, 1);
726
727  emitWordLE(Binary);
728}
729
730void ARMCodeEmitter::addPCLabel(unsigned LabelID) {
731  DEBUG(errs() << "  ** LPC" << LabelID << " @ "
732        << (void*)MCE.getCurrentPCValue() << '\n');
733  JTI->addPCLabelAddr(LabelID, MCE.getCurrentPCValue());
734}
735
736void ARMCodeEmitter::emitPseudoInstruction(const MachineInstr &MI) {
737  unsigned Opcode = MI.getDesc().Opcode;
738  switch (Opcode) {
739  default:
740    llvm_unreachable("ARMCodeEmitter::emitPseudoInstruction");
741  case ARM::BX:
742  case ARM::BMOVPCRX:
743  case ARM::BXr9:
744  case ARM::BMOVPCRXr9: {
745    // First emit mov lr, pc
746    unsigned Binary = 0x01a0e00f;
747    Binary |= II->getPredicate(&MI) << ARMII::CondShift;
748    emitWordLE(Binary);
749
750    // and then emit the branch.
751    emitMiscBranchInstruction(MI);
752    break;
753  }
754  case TargetOpcode::INLINEASM: {
755    // We allow inline assembler nodes with empty bodies - they can
756    // implicitly define registers, which is ok for JIT.
757    if (MI.getOperand(0).getSymbolName()[0]) {
758      report_fatal_error("JIT does not support inline asm!");
759    }
760    break;
761  }
762  case TargetOpcode::PROLOG_LABEL:
763  case TargetOpcode::EH_LABEL:
764    MCE.emitLabel(MI.getOperand(0).getMCSymbol());
765    break;
766  case TargetOpcode::IMPLICIT_DEF:
767  case TargetOpcode::KILL:
768    // Do nothing.
769    break;
770  case ARM::CONSTPOOL_ENTRY:
771    emitConstPoolInstruction(MI);
772    break;
773  case ARM::PICADD: {
774    // Remember of the address of the PC label for relocation later.
775    addPCLabel(MI.getOperand(2).getImm());
776    // PICADD is just an add instruction that implicitly read pc.
777    emitDataProcessingInstruction(MI, 0, ARM::PC);
778    break;
779  }
780  case ARM::PICLDR:
781  case ARM::PICLDRB:
782  case ARM::PICSTR:
783  case ARM::PICSTRB: {
784    // Remember of the address of the PC label for relocation later.
785    addPCLabel(MI.getOperand(2).getImm());
786    // These are just load / store instructions that implicitly read pc.
787    emitLoadStoreInstruction(MI, 0, ARM::PC);
788    break;
789  }
790  case ARM::PICLDRH:
791  case ARM::PICLDRSH:
792  case ARM::PICLDRSB:
793  case ARM::PICSTRH: {
794    // Remember of the address of the PC label for relocation later.
795    addPCLabel(MI.getOperand(2).getImm());
796    // These are just load / store instructions that implicitly read pc.
797    emitMiscLoadStoreInstruction(MI, ARM::PC);
798    break;
799  }
800
801  case ARM::MOVi32imm:
802    emitMOVi32immInstruction(MI);
803    break;
804
805  case ARM::MOVi2pieces:
806    // Two instructions to materialize a constant.
807    emitMOVi2piecesInstruction(MI);
808    break;
809  case ARM::LEApcrelJT:
810    // Materialize jumptable address.
811    emitLEApcrelJTInstruction(MI);
812    break;
813  case ARM::RRX:
814  case ARM::MOVsrl_flag:
815  case ARM::MOVsra_flag:
816    emitPseudoMoveInstruction(MI);
817    break;
818  }
819}
820
821unsigned ARMCodeEmitter::getMachineSoRegOpValue(const MachineInstr &MI,
822                                                const TargetInstrDesc &TID,
823                                                const MachineOperand &MO,
824                                                unsigned OpIdx) {
825  unsigned Binary = getMachineOpValue(MI, MO);
826
827  const MachineOperand &MO1 = MI.getOperand(OpIdx + 1);
828  const MachineOperand &MO2 = MI.getOperand(OpIdx + 2);
829  ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm());
830
831  // Encode the shift opcode.
832  unsigned SBits = 0;
833  unsigned Rs = MO1.getReg();
834  if (Rs) {
835    // Set shift operand (bit[7:4]).
836    // LSL - 0001
837    // LSR - 0011
838    // ASR - 0101
839    // ROR - 0111
840    // RRX - 0110 and bit[11:8] clear.
841    switch (SOpc) {
842    default: llvm_unreachable("Unknown shift opc!");
843    case ARM_AM::lsl: SBits = 0x1; break;
844    case ARM_AM::lsr: SBits = 0x3; break;
845    case ARM_AM::asr: SBits = 0x5; break;
846    case ARM_AM::ror: SBits = 0x7; break;
847    case ARM_AM::rrx: SBits = 0x6; break;
848    }
849  } else {
850    // Set shift operand (bit[6:4]).
851    // LSL - 000
852    // LSR - 010
853    // ASR - 100
854    // ROR - 110
855    switch (SOpc) {
856    default: llvm_unreachable("Unknown shift opc!");
857    case ARM_AM::lsl: SBits = 0x0; break;
858    case ARM_AM::lsr: SBits = 0x2; break;
859    case ARM_AM::asr: SBits = 0x4; break;
860    case ARM_AM::ror: SBits = 0x6; break;
861    }
862  }
863  Binary |= SBits << 4;
864  if (SOpc == ARM_AM::rrx)
865    return Binary;
866
867  // Encode the shift operation Rs or shift_imm (except rrx).
868  if (Rs) {
869    // Encode Rs bit[11:8].
870    assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0);
871    return Binary | (getARMRegisterNumbering(Rs) << ARMII::RegRsShift);
872  }
873
874  // Encode shift_imm bit[11:7].
875  return Binary | ARM_AM::getSORegOffset(MO2.getImm()) << 7;
876}
877
878unsigned ARMCodeEmitter::getMachineSoImmOpValue(unsigned SoImm) {
879  int SoImmVal = ARM_AM::getSOImmVal(SoImm);
880  assert(SoImmVal != -1 && "Not a valid so_imm value!");
881
882  // Encode rotate_imm.
883  unsigned Binary = (ARM_AM::getSOImmValRot((unsigned)SoImmVal) >> 1)
884    << ARMII::SoRotImmShift;
885
886  // Encode immed_8.
887  Binary |= ARM_AM::getSOImmValImm((unsigned)SoImmVal);
888  return Binary;
889}
890
891unsigned ARMCodeEmitter::getAddrModeSBit(const MachineInstr &MI,
892                                         const TargetInstrDesc &TID) const {
893  for (unsigned i = MI.getNumOperands(), e = TID.getNumOperands(); i != e; --i){
894    const MachineOperand &MO = MI.getOperand(i-1);
895    if (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR)
896      return 1 << ARMII::S_BitShift;
897  }
898  return 0;
899}
900
901void ARMCodeEmitter::emitDataProcessingInstruction(const MachineInstr &MI,
902                                                   unsigned ImplicitRd,
903                                                   unsigned ImplicitRn) {
904  const TargetInstrDesc &TID = MI.getDesc();
905
906  // Part of binary is determined by TableGn.
907  unsigned Binary = getBinaryCodeForInstr(MI);
908
909  // Set the conditional execution predicate
910  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
911
912  // Encode S bit if MI modifies CPSR.
913  Binary |= getAddrModeSBit(MI, TID);
914
915  // Encode register def if there is one.
916  unsigned NumDefs = TID.getNumDefs();
917  unsigned OpIdx = 0;
918  if (NumDefs)
919    Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
920  else if (ImplicitRd)
921    // Special handling for implicit use (e.g. PC).
922    Binary |= (getARMRegisterNumbering(ImplicitRd) << ARMII::RegRdShift);
923
924  if (TID.Opcode == ARM::MOVi16) {
925      // Get immediate from MI.
926      unsigned Lo16 = getMovi32Value(MI, MI.getOperand(OpIdx),
927                      ARM::reloc_arm_movw);
928      // Encode imm which is the same as in emitMOVi32immInstruction().
929      Binary |= Lo16 & 0xFFF;
930      Binary |= ((Lo16 >> 12) & 0xF) << 16;
931      emitWordLE(Binary);
932      return;
933  } else if(TID.Opcode == ARM::MOVTi16) {
934      unsigned Hi16 = (getMovi32Value(MI, MI.getOperand(OpIdx),
935                       ARM::reloc_arm_movt) >> 16);
936      Binary |= Hi16 & 0xFFF;
937      Binary |= ((Hi16 >> 12) & 0xF) << 16;
938      emitWordLE(Binary);
939      return;
940  } else if ((TID.Opcode == ARM::BFC) || (TID.Opcode == ARM::BFI)) {
941      uint32_t v = ~MI.getOperand(2).getImm();
942      int32_t lsb = CountTrailingZeros_32(v);
943      int32_t msb = (32 - CountLeadingZeros_32(v)) - 1;
944      // Instr{20-16} = msb, Instr{11-7} = lsb
945      Binary |= (msb & 0x1F) << 16;
946      Binary |= (lsb & 0x1F) << 7;
947      emitWordLE(Binary);
948      return;
949  } else if ((TID.Opcode == ARM::UBFX) || (TID.Opcode == ARM::SBFX)) {
950      // Encode Rn in Instr{0-3}
951      Binary |= getMachineOpValue(MI, OpIdx++);
952
953      uint32_t lsb = MI.getOperand(OpIdx++).getImm();
954      uint32_t widthm1 = MI.getOperand(OpIdx++).getImm() - 1;
955
956      // Instr{20-16} = widthm1, Instr{11-7} = lsb
957      Binary |= (widthm1 & 0x1F) << 16;
958      Binary |= (lsb & 0x1F) << 7;
959      emitWordLE(Binary);
960      return;
961  }
962
963  // If this is a two-address operand, skip it. e.g. MOVCCr operand 1.
964  if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
965    ++OpIdx;
966
967  // Encode first non-shifter register operand if there is one.
968  bool isUnary = TID.TSFlags & ARMII::UnaryDP;
969  if (!isUnary) {
970    if (ImplicitRn)
971      // Special handling for implicit use (e.g. PC).
972      Binary |= (getARMRegisterNumbering(ImplicitRn) << ARMII::RegRnShift);
973    else {
974      Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRnShift;
975      ++OpIdx;
976    }
977  }
978
979  // Encode shifter operand.
980  const MachineOperand &MO = MI.getOperand(OpIdx);
981  if ((TID.TSFlags & ARMII::FormMask) == ARMII::DPSoRegFrm) {
982    // Encode SoReg.
983    emitWordLE(Binary | getMachineSoRegOpValue(MI, TID, MO, OpIdx));
984    return;
985  }
986
987  if (MO.isReg()) {
988    // Encode register Rm.
989    emitWordLE(Binary | getARMRegisterNumbering(MO.getReg()));
990    return;
991  }
992
993  // Encode so_imm.
994  Binary |= getMachineSoImmOpValue((unsigned)MO.getImm());
995
996  emitWordLE(Binary);
997}
998
999void ARMCodeEmitter::emitLoadStoreInstruction(const MachineInstr &MI,
1000                                              unsigned ImplicitRd,
1001                                              unsigned ImplicitRn) {
1002  const TargetInstrDesc &TID = MI.getDesc();
1003  unsigned Form = TID.TSFlags & ARMII::FormMask;
1004  bool IsPrePost = (TID.TSFlags & ARMII::IndexModeMask) != 0;
1005
1006  // Part of binary is determined by TableGn.
1007  unsigned Binary = getBinaryCodeForInstr(MI);
1008
1009  // If this is an LDRi12, STRi12 or LDRcp, nothing more needs be done.
1010  if (MI.getOpcode() == ARM::LDRi12 || MI.getOpcode() == ARM::LDRcp ||
1011      MI.getOpcode() == ARM::STRi12) {
1012    emitWordLE(Binary);
1013    return;
1014  }
1015
1016  // Set the conditional execution predicate
1017  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1018
1019  unsigned OpIdx = 0;
1020
1021  // Operand 0 of a pre- and post-indexed store is the address base
1022  // writeback. Skip it.
1023  bool Skipped = false;
1024  if (IsPrePost && Form == ARMII::StFrm) {
1025    ++OpIdx;
1026    Skipped = true;
1027  }
1028
1029  // Set first operand
1030  if (ImplicitRd)
1031    // Special handling for implicit use (e.g. PC).
1032    Binary |= (getARMRegisterNumbering(ImplicitRd) << ARMII::RegRdShift);
1033  else
1034    Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1035
1036  // Set second operand
1037  if (ImplicitRn)
1038    // Special handling for implicit use (e.g. PC).
1039    Binary |= (getARMRegisterNumbering(ImplicitRn) << ARMII::RegRnShift);
1040  else
1041    Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
1042
1043  // If this is a two-address operand, skip it. e.g. LDR_PRE.
1044  if (!Skipped && TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1045    ++OpIdx;
1046
1047  const MachineOperand &MO2 = MI.getOperand(OpIdx);
1048  unsigned AM2Opc = (ImplicitRn == ARM::PC)
1049    ? 0 : MI.getOperand(OpIdx+1).getImm();
1050
1051  // Set bit U(23) according to sign of immed value (positive or negative).
1052  Binary |= ((ARM_AM::getAM2Op(AM2Opc) == ARM_AM::add ? 1 : 0) <<
1053             ARMII::U_BitShift);
1054  if (!MO2.getReg()) { // is immediate
1055    if (ARM_AM::getAM2Offset(AM2Opc))
1056      // Set the value of offset_12 field
1057      Binary |= ARM_AM::getAM2Offset(AM2Opc);
1058    emitWordLE(Binary);
1059    return;
1060  }
1061
1062  // Set bit I(25), because this is not in immediate encoding.
1063  Binary |= 1 << ARMII::I_BitShift;
1064  assert(TargetRegisterInfo::isPhysicalRegister(MO2.getReg()));
1065  // Set bit[3:0] to the corresponding Rm register
1066  Binary |= getARMRegisterNumbering(MO2.getReg());
1067
1068  // If this instr is in scaled register offset/index instruction, set
1069  // shift_immed(bit[11:7]) and shift(bit[6:5]) fields.
1070  if (unsigned ShImm = ARM_AM::getAM2Offset(AM2Opc)) {
1071    Binary |= getShiftOp(AM2Opc) << ARMII::ShiftImmShift;  // shift
1072    Binary |= ShImm              << ARMII::ShiftShift;     // shift_immed
1073  }
1074
1075  emitWordLE(Binary);
1076}
1077
1078void ARMCodeEmitter::emitMiscLoadStoreInstruction(const MachineInstr &MI,
1079                                                  unsigned ImplicitRn) {
1080  const TargetInstrDesc &TID = MI.getDesc();
1081  unsigned Form = TID.TSFlags & ARMII::FormMask;
1082  bool IsPrePost = (TID.TSFlags & ARMII::IndexModeMask) != 0;
1083
1084  // Part of binary is determined by TableGn.
1085  unsigned Binary = getBinaryCodeForInstr(MI);
1086
1087  // Set the conditional execution predicate
1088  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1089
1090  unsigned OpIdx = 0;
1091
1092  // Operand 0 of a pre- and post-indexed store is the address base
1093  // writeback. Skip it.
1094  bool Skipped = false;
1095  if (IsPrePost && Form == ARMII::StMiscFrm) {
1096    ++OpIdx;
1097    Skipped = true;
1098  }
1099
1100  // Set first operand
1101  Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1102
1103  // Skip LDRD and STRD's second operand.
1104  if (TID.Opcode == ARM::LDRD || TID.Opcode == ARM::STRD)
1105    ++OpIdx;
1106
1107  // Set second operand
1108  if (ImplicitRn)
1109    // Special handling for implicit use (e.g. PC).
1110    Binary |= (getARMRegisterNumbering(ImplicitRn) << ARMII::RegRnShift);
1111  else
1112    Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
1113
1114  // If this is a two-address operand, skip it. e.g. LDRH_POST.
1115  if (!Skipped && TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1116    ++OpIdx;
1117
1118  const MachineOperand &MO2 = MI.getOperand(OpIdx);
1119  unsigned AM3Opc = (ImplicitRn == ARM::PC)
1120    ? 0 : MI.getOperand(OpIdx+1).getImm();
1121
1122  // Set bit U(23) according to sign of immed value (positive or negative)
1123  Binary |= ((ARM_AM::getAM3Op(AM3Opc) == ARM_AM::add ? 1 : 0) <<
1124             ARMII::U_BitShift);
1125
1126  // If this instr is in register offset/index encoding, set bit[3:0]
1127  // to the corresponding Rm register.
1128  if (MO2.getReg()) {
1129    Binary |= getARMRegisterNumbering(MO2.getReg());
1130    emitWordLE(Binary);
1131    return;
1132  }
1133
1134  // This instr is in immediate offset/index encoding, set bit 22 to 1.
1135  Binary |= 1 << ARMII::AM3_I_BitShift;
1136  if (unsigned ImmOffs = ARM_AM::getAM3Offset(AM3Opc)) {
1137    // Set operands
1138    Binary |= (ImmOffs >> 4) << ARMII::ImmHiShift;  // immedH
1139    Binary |= (ImmOffs & 0xF);                      // immedL
1140  }
1141
1142  emitWordLE(Binary);
1143}
1144
1145static unsigned getAddrModeUPBits(unsigned Mode) {
1146  unsigned Binary = 0;
1147
1148  // Set addressing mode by modifying bits U(23) and P(24)
1149  // IA - Increment after  - bit U = 1 and bit P = 0
1150  // IB - Increment before - bit U = 1 and bit P = 1
1151  // DA - Decrement after  - bit U = 0 and bit P = 0
1152  // DB - Decrement before - bit U = 0 and bit P = 1
1153  switch (Mode) {
1154  default: llvm_unreachable("Unknown addressing sub-mode!");
1155  case ARM_AM::da:                                     break;
1156  case ARM_AM::db: Binary |= 0x1 << ARMII::P_BitShift; break;
1157  case ARM_AM::ia: Binary |= 0x1 << ARMII::U_BitShift; break;
1158  case ARM_AM::ib: Binary |= 0x3 << ARMII::U_BitShift; break;
1159  }
1160
1161  return Binary;
1162}
1163
1164void ARMCodeEmitter::emitLoadStoreMultipleInstruction(const MachineInstr &MI) {
1165  const TargetInstrDesc &TID = MI.getDesc();
1166  bool IsUpdating = (TID.TSFlags & ARMII::IndexModeMask) != 0;
1167
1168  // Part of binary is determined by TableGn.
1169  unsigned Binary = getBinaryCodeForInstr(MI);
1170
1171  // Set the conditional execution predicate
1172  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1173
1174  // Skip operand 0 of an instruction with base register update.
1175  unsigned OpIdx = 0;
1176  if (IsUpdating)
1177    ++OpIdx;
1178
1179  // Set base address operand
1180  Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
1181
1182  // Set addressing mode by modifying bits U(23) and P(24)
1183  const MachineOperand &MO = MI.getOperand(OpIdx++);
1184  Binary |= getAddrModeUPBits(ARM_AM::getAM4SubMode(MO.getImm()));
1185
1186  // Set bit W(21)
1187  if (IsUpdating)
1188    Binary |= 0x1 << ARMII::W_BitShift;
1189
1190  // Set registers
1191  for (unsigned i = OpIdx+2, e = MI.getNumOperands(); i != e; ++i) {
1192    const MachineOperand &MO = MI.getOperand(i);
1193    if (!MO.isReg() || MO.isImplicit())
1194      break;
1195    unsigned RegNum = getARMRegisterNumbering(MO.getReg());
1196    assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()) &&
1197           RegNum < 16);
1198    Binary |= 0x1 << RegNum;
1199  }
1200
1201  emitWordLE(Binary);
1202}
1203
1204void ARMCodeEmitter::emitMulFrmInstruction(const MachineInstr &MI) {
1205  const TargetInstrDesc &TID = MI.getDesc();
1206
1207  // Part of binary is determined by TableGn.
1208  unsigned Binary = getBinaryCodeForInstr(MI);
1209
1210  // Set the conditional execution predicate
1211  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1212
1213  // Encode S bit if MI modifies CPSR.
1214  Binary |= getAddrModeSBit(MI, TID);
1215
1216  // 32x32->64bit operations have two destination registers. The number
1217  // of register definitions will tell us if that's what we're dealing with.
1218  unsigned OpIdx = 0;
1219  if (TID.getNumDefs() == 2)
1220    Binary |= getMachineOpValue (MI, OpIdx++) << ARMII::RegRdLoShift;
1221
1222  // Encode Rd
1223  Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdHiShift;
1224
1225  // Encode Rm
1226  Binary |= getMachineOpValue(MI, OpIdx++);
1227
1228  // Encode Rs
1229  Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRsShift;
1230
1231  // Many multiple instructions (e.g. MLA) have three src operands. Encode
1232  // it as Rn (for multiply, that's in the same offset as RdLo.
1233  if (TID.getNumOperands() > OpIdx &&
1234      !TID.OpInfo[OpIdx].isPredicate() &&
1235      !TID.OpInfo[OpIdx].isOptionalDef())
1236    Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRdLoShift;
1237
1238  emitWordLE(Binary);
1239}
1240
1241void ARMCodeEmitter::emitExtendInstruction(const MachineInstr &MI) {
1242  const TargetInstrDesc &TID = MI.getDesc();
1243
1244  // Part of binary is determined by TableGn.
1245  unsigned Binary = getBinaryCodeForInstr(MI);
1246
1247  // Set the conditional execution predicate
1248  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1249
1250  unsigned OpIdx = 0;
1251
1252  // Encode Rd
1253  Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1254
1255  const MachineOperand &MO1 = MI.getOperand(OpIdx++);
1256  const MachineOperand &MO2 = MI.getOperand(OpIdx);
1257  if (MO2.isReg()) {
1258    // Two register operand form.
1259    // Encode Rn.
1260    Binary |= getMachineOpValue(MI, MO1) << ARMII::RegRnShift;
1261
1262    // Encode Rm.
1263    Binary |= getMachineOpValue(MI, MO2);
1264    ++OpIdx;
1265  } else {
1266    Binary |= getMachineOpValue(MI, MO1);
1267  }
1268
1269  // Encode rot imm (0, 8, 16, or 24) if it has a rotate immediate operand.
1270  if (MI.getOperand(OpIdx).isImm() &&
1271      !TID.OpInfo[OpIdx].isPredicate() &&
1272      !TID.OpInfo[OpIdx].isOptionalDef())
1273    Binary |= (getMachineOpValue(MI, OpIdx) / 8) << ARMII::ExtRotImmShift;
1274
1275  emitWordLE(Binary);
1276}
1277
1278void ARMCodeEmitter::emitMiscArithInstruction(const MachineInstr &MI) {
1279  const TargetInstrDesc &TID = MI.getDesc();
1280
1281  // Part of binary is determined by TableGn.
1282  unsigned Binary = getBinaryCodeForInstr(MI);
1283
1284  // Set the conditional execution predicate
1285  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1286
1287  unsigned OpIdx = 0;
1288
1289  // Encode Rd
1290  Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1291
1292  const MachineOperand &MO = MI.getOperand(OpIdx++);
1293  if (OpIdx == TID.getNumOperands() ||
1294      TID.OpInfo[OpIdx].isPredicate() ||
1295      TID.OpInfo[OpIdx].isOptionalDef()) {
1296    // Encode Rm and it's done.
1297    Binary |= getMachineOpValue(MI, MO);
1298    emitWordLE(Binary);
1299    return;
1300  }
1301
1302  // Encode Rn.
1303  Binary |= getMachineOpValue(MI, MO) << ARMII::RegRnShift;
1304
1305  // Encode Rm.
1306  Binary |= getMachineOpValue(MI, OpIdx++);
1307
1308  // Encode shift_imm.
1309  unsigned ShiftAmt = MI.getOperand(OpIdx).getImm();
1310  if (TID.Opcode == ARM::PKHTB) {
1311    assert(ShiftAmt != 0 && "PKHTB shift_imm is 0!");
1312    if (ShiftAmt == 32)
1313      ShiftAmt = 0;
1314  }
1315  assert(ShiftAmt < 32 && "shift_imm range is 0 to 31!");
1316  Binary |= ShiftAmt << ARMII::ShiftShift;
1317
1318  emitWordLE(Binary);
1319}
1320
1321void ARMCodeEmitter::emitSaturateInstruction(const MachineInstr &MI) {
1322  const TargetInstrDesc &TID = MI.getDesc();
1323
1324  // Part of binary is determined by TableGen.
1325  unsigned Binary = getBinaryCodeForInstr(MI);
1326
1327  // Set the conditional execution predicate
1328  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1329
1330  // Encode Rd
1331  Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
1332
1333  // Encode saturate bit position.
1334  unsigned Pos = MI.getOperand(1).getImm();
1335  if (TID.Opcode == ARM::SSAT || TID.Opcode == ARM::SSAT16)
1336    Pos -= 1;
1337  assert((Pos < 16 || (Pos < 32 &&
1338                       TID.Opcode != ARM::SSAT16 &&
1339                       TID.Opcode != ARM::USAT16)) &&
1340         "saturate bit position out of range");
1341  Binary |= Pos << 16;
1342
1343  // Encode Rm
1344  Binary |= getMachineOpValue(MI, 2);
1345
1346  // Encode shift_imm.
1347  if (TID.getNumOperands() == 4) {
1348    unsigned ShiftOp = MI.getOperand(3).getImm();
1349    ARM_AM::ShiftOpc Opc = ARM_AM::getSORegShOp(ShiftOp);
1350    if (Opc == ARM_AM::asr)
1351      Binary |= (1 << 6);
1352    unsigned ShiftAmt = MI.getOperand(3).getImm();
1353    if (ShiftAmt == 32 && Opc == ARM_AM::asr)
1354      ShiftAmt = 0;
1355    assert(ShiftAmt < 32 && "shift_imm range is 0 to 31!");
1356    Binary |= ShiftAmt << ARMII::ShiftShift;
1357  }
1358
1359  emitWordLE(Binary);
1360}
1361
1362void ARMCodeEmitter::emitBranchInstruction(const MachineInstr &MI) {
1363  const TargetInstrDesc &TID = MI.getDesc();
1364
1365  if (TID.Opcode == ARM::TPsoft) {
1366    llvm_unreachable("ARM::TPsoft FIXME"); // FIXME
1367  }
1368
1369  // Part of binary is determined by TableGn.
1370  unsigned Binary = getBinaryCodeForInstr(MI);
1371
1372  // Set the conditional execution predicate
1373  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1374
1375  // Set signed_immed_24 field
1376  Binary |= getMachineOpValue(MI, 0);
1377
1378  emitWordLE(Binary);
1379}
1380
1381void ARMCodeEmitter::emitInlineJumpTable(unsigned JTIndex) {
1382  // Remember the base address of the inline jump table.
1383  uintptr_t JTBase = MCE.getCurrentPCValue();
1384  JTI->addJumpTableBaseAddr(JTIndex, JTBase);
1385  DEBUG(errs() << "  ** Jump Table #" << JTIndex << " @ " << (void*)JTBase
1386               << '\n');
1387
1388  // Now emit the jump table entries.
1389  const std::vector<MachineBasicBlock*> &MBBs = (*MJTEs)[JTIndex].MBBs;
1390  for (unsigned i = 0, e = MBBs.size(); i != e; ++i) {
1391    if (IsPIC)
1392      // DestBB address - JT base.
1393      emitMachineBasicBlock(MBBs[i], ARM::reloc_arm_pic_jt, JTBase);
1394    else
1395      // Absolute DestBB address.
1396      emitMachineBasicBlock(MBBs[i], ARM::reloc_arm_absolute);
1397    emitWordLE(0);
1398  }
1399}
1400
1401void ARMCodeEmitter::emitMiscBranchInstruction(const MachineInstr &MI) {
1402  const TargetInstrDesc &TID = MI.getDesc();
1403
1404  // Handle jump tables.
1405  if (TID.Opcode == ARM::BR_JTr || TID.Opcode == ARM::BR_JTadd) {
1406    // First emit a ldr pc, [] instruction.
1407    emitDataProcessingInstruction(MI, ARM::PC);
1408
1409    // Then emit the inline jump table.
1410    unsigned JTIndex =
1411      (TID.Opcode == ARM::BR_JTr)
1412      ? MI.getOperand(1).getIndex() : MI.getOperand(2).getIndex();
1413    emitInlineJumpTable(JTIndex);
1414    return;
1415  } else if (TID.Opcode == ARM::BR_JTm) {
1416    // First emit a ldr pc, [] instruction.
1417    emitLoadStoreInstruction(MI, ARM::PC);
1418
1419    // Then emit the inline jump table.
1420    emitInlineJumpTable(MI.getOperand(3).getIndex());
1421    return;
1422  }
1423
1424  // Part of binary is determined by TableGn.
1425  unsigned Binary = getBinaryCodeForInstr(MI);
1426
1427  // Set the conditional execution predicate
1428  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1429
1430  if (TID.Opcode == ARM::BX_RET || TID.Opcode == ARM::MOVPCLR)
1431    // The return register is LR.
1432    Binary |= getARMRegisterNumbering(ARM::LR);
1433  else
1434    // otherwise, set the return register
1435    Binary |= getMachineOpValue(MI, 0);
1436
1437  emitWordLE(Binary);
1438}
1439
1440static unsigned encodeVFPRd(const MachineInstr &MI, unsigned OpIdx) {
1441  unsigned RegD = MI.getOperand(OpIdx).getReg();
1442  unsigned Binary = 0;
1443  bool isSPVFP = ARM::SPRRegisterClass->contains(RegD);
1444  RegD = getARMRegisterNumbering(RegD);
1445  if (!isSPVFP)
1446    Binary |=   RegD               << ARMII::RegRdShift;
1447  else {
1448    Binary |= ((RegD & 0x1E) >> 1) << ARMII::RegRdShift;
1449    Binary |=  (RegD & 0x01)       << ARMII::D_BitShift;
1450  }
1451  return Binary;
1452}
1453
1454static unsigned encodeVFPRn(const MachineInstr &MI, unsigned OpIdx) {
1455  unsigned RegN = MI.getOperand(OpIdx).getReg();
1456  unsigned Binary = 0;
1457  bool isSPVFP = ARM::SPRRegisterClass->contains(RegN);
1458  RegN = getARMRegisterNumbering(RegN);
1459  if (!isSPVFP)
1460    Binary |=   RegN               << ARMII::RegRnShift;
1461  else {
1462    Binary |= ((RegN & 0x1E) >> 1) << ARMII::RegRnShift;
1463    Binary |=  (RegN & 0x01)       << ARMII::N_BitShift;
1464  }
1465  return Binary;
1466}
1467
1468static unsigned encodeVFPRm(const MachineInstr &MI, unsigned OpIdx) {
1469  unsigned RegM = MI.getOperand(OpIdx).getReg();
1470  unsigned Binary = 0;
1471  bool isSPVFP = ARM::SPRRegisterClass->contains(RegM);
1472  RegM = getARMRegisterNumbering(RegM);
1473  if (!isSPVFP)
1474    Binary |=   RegM;
1475  else {
1476    Binary |= ((RegM & 0x1E) >> 1);
1477    Binary |=  (RegM & 0x01)       << ARMII::M_BitShift;
1478  }
1479  return Binary;
1480}
1481
1482void ARMCodeEmitter::emitVFPArithInstruction(const MachineInstr &MI) {
1483  const TargetInstrDesc &TID = MI.getDesc();
1484
1485  // Part of binary is determined by TableGn.
1486  unsigned Binary = getBinaryCodeForInstr(MI);
1487
1488  // Set the conditional execution predicate
1489  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1490
1491  unsigned OpIdx = 0;
1492  assert((Binary & ARMII::D_BitShift) == 0 &&
1493         (Binary & ARMII::N_BitShift) == 0 &&
1494         (Binary & ARMII::M_BitShift) == 0 && "VFP encoding bug!");
1495
1496  // Encode Dd / Sd.
1497  Binary |= encodeVFPRd(MI, OpIdx++);
1498
1499  // If this is a two-address operand, skip it, e.g. FMACD.
1500  if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1501    ++OpIdx;
1502
1503  // Encode Dn / Sn.
1504  if ((TID.TSFlags & ARMII::FormMask) == ARMII::VFPBinaryFrm)
1505    Binary |= encodeVFPRn(MI, OpIdx++);
1506
1507  if (OpIdx == TID.getNumOperands() ||
1508      TID.OpInfo[OpIdx].isPredicate() ||
1509      TID.OpInfo[OpIdx].isOptionalDef()) {
1510    // FCMPEZD etc. has only one operand.
1511    emitWordLE(Binary);
1512    return;
1513  }
1514
1515  // Encode Dm / Sm.
1516  Binary |= encodeVFPRm(MI, OpIdx);
1517
1518  emitWordLE(Binary);
1519}
1520
1521void ARMCodeEmitter::emitVFPConversionInstruction(const MachineInstr &MI) {
1522  const TargetInstrDesc &TID = MI.getDesc();
1523  unsigned Form = TID.TSFlags & ARMII::FormMask;
1524
1525  // Part of binary is determined by TableGn.
1526  unsigned Binary = getBinaryCodeForInstr(MI);
1527
1528  // Set the conditional execution predicate
1529  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1530
1531  switch (Form) {
1532  default: break;
1533  case ARMII::VFPConv1Frm:
1534  case ARMII::VFPConv2Frm:
1535  case ARMII::VFPConv3Frm:
1536    // Encode Dd / Sd.
1537    Binary |= encodeVFPRd(MI, 0);
1538    break;
1539  case ARMII::VFPConv4Frm:
1540    // Encode Dn / Sn.
1541    Binary |= encodeVFPRn(MI, 0);
1542    break;
1543  case ARMII::VFPConv5Frm:
1544    // Encode Dm / Sm.
1545    Binary |= encodeVFPRm(MI, 0);
1546    break;
1547  }
1548
1549  switch (Form) {
1550  default: break;
1551  case ARMII::VFPConv1Frm:
1552    // Encode Dm / Sm.
1553    Binary |= encodeVFPRm(MI, 1);
1554    break;
1555  case ARMII::VFPConv2Frm:
1556  case ARMII::VFPConv3Frm:
1557    // Encode Dn / Sn.
1558    Binary |= encodeVFPRn(MI, 1);
1559    break;
1560  case ARMII::VFPConv4Frm:
1561  case ARMII::VFPConv5Frm:
1562    // Encode Dd / Sd.
1563    Binary |= encodeVFPRd(MI, 1);
1564    break;
1565  }
1566
1567  if (Form == ARMII::VFPConv5Frm)
1568    // Encode Dn / Sn.
1569    Binary |= encodeVFPRn(MI, 2);
1570  else if (Form == ARMII::VFPConv3Frm)
1571    // Encode Dm / Sm.
1572    Binary |= encodeVFPRm(MI, 2);
1573
1574  emitWordLE(Binary);
1575}
1576
1577void ARMCodeEmitter::emitVFPLoadStoreInstruction(const MachineInstr &MI) {
1578  // Part of binary is determined by TableGn.
1579  unsigned Binary = getBinaryCodeForInstr(MI);
1580
1581  // Set the conditional execution predicate
1582  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1583
1584  unsigned OpIdx = 0;
1585
1586  // Encode Dd / Sd.
1587  Binary |= encodeVFPRd(MI, OpIdx++);
1588
1589  // Encode address base.
1590  const MachineOperand &Base = MI.getOperand(OpIdx++);
1591  Binary |= getMachineOpValue(MI, Base) << ARMII::RegRnShift;
1592
1593  // If there is a non-zero immediate offset, encode it.
1594  if (Base.isReg()) {
1595    const MachineOperand &Offset = MI.getOperand(OpIdx);
1596    if (unsigned ImmOffs = ARM_AM::getAM5Offset(Offset.getImm())) {
1597      if (ARM_AM::getAM5Op(Offset.getImm()) == ARM_AM::add)
1598        Binary |= 1 << ARMII::U_BitShift;
1599      Binary |= ImmOffs;
1600      emitWordLE(Binary);
1601      return;
1602    }
1603  }
1604
1605  // If immediate offset is omitted, default to +0.
1606  Binary |= 1 << ARMII::U_BitShift;
1607
1608  emitWordLE(Binary);
1609}
1610
1611void
1612ARMCodeEmitter::emitVFPLoadStoreMultipleInstruction(const MachineInstr &MI) {
1613  const TargetInstrDesc &TID = MI.getDesc();
1614  bool IsUpdating = (TID.TSFlags & ARMII::IndexModeMask) != 0;
1615
1616  // Part of binary is determined by TableGn.
1617  unsigned Binary = getBinaryCodeForInstr(MI);
1618
1619  // Set the conditional execution predicate
1620  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1621
1622  // Skip operand 0 of an instruction with base register update.
1623  unsigned OpIdx = 0;
1624  if (IsUpdating)
1625    ++OpIdx;
1626
1627  // Set base address operand
1628  Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
1629
1630  // Set addressing mode by modifying bits U(23) and P(24)
1631  const MachineOperand &MO = MI.getOperand(OpIdx++);
1632  Binary |= getAddrModeUPBits(ARM_AM::getAM4SubMode(MO.getImm()));
1633
1634  // Set bit W(21)
1635  if (IsUpdating)
1636    Binary |= 0x1 << ARMII::W_BitShift;
1637
1638  // First register is encoded in Dd.
1639  Binary |= encodeVFPRd(MI, OpIdx+2);
1640
1641  // Count the number of registers.
1642  unsigned NumRegs = 1;
1643  for (unsigned i = OpIdx+3, e = MI.getNumOperands(); i != e; ++i) {
1644    const MachineOperand &MO = MI.getOperand(i);
1645    if (!MO.isReg() || MO.isImplicit())
1646      break;
1647    ++NumRegs;
1648  }
1649  // Bit 8 will be set if <list> is consecutive 64-bit registers (e.g., D0)
1650  // Otherwise, it will be 0, in the case of 32-bit registers.
1651  if(Binary & 0x100)
1652    Binary |= NumRegs * 2;
1653  else
1654    Binary |= NumRegs;
1655
1656  emitWordLE(Binary);
1657}
1658
1659static unsigned encodeNEONRd(const MachineInstr &MI, unsigned OpIdx) {
1660  unsigned RegD = MI.getOperand(OpIdx).getReg();
1661  unsigned Binary = 0;
1662  RegD = getARMRegisterNumbering(RegD);
1663  Binary |= (RegD & 0xf) << ARMII::RegRdShift;
1664  Binary |= ((RegD >> 4) & 1) << ARMII::D_BitShift;
1665  return Binary;
1666}
1667
1668static unsigned encodeNEONRn(const MachineInstr &MI, unsigned OpIdx) {
1669  unsigned RegN = MI.getOperand(OpIdx).getReg();
1670  unsigned Binary = 0;
1671  RegN = getARMRegisterNumbering(RegN);
1672  Binary |= (RegN & 0xf) << ARMII::RegRnShift;
1673  Binary |= ((RegN >> 4) & 1) << ARMII::N_BitShift;
1674  return Binary;
1675}
1676
1677static unsigned encodeNEONRm(const MachineInstr &MI, unsigned OpIdx) {
1678  unsigned RegM = MI.getOperand(OpIdx).getReg();
1679  unsigned Binary = 0;
1680  RegM = getARMRegisterNumbering(RegM);
1681  Binary |= (RegM & 0xf);
1682  Binary |= ((RegM >> 4) & 1) << ARMII::M_BitShift;
1683  return Binary;
1684}
1685
1686/// convertNEONDataProcToThumb - Convert the ARM mode encoding for a NEON
1687/// data-processing instruction to the corresponding Thumb encoding.
1688static unsigned convertNEONDataProcToThumb(unsigned Binary) {
1689  assert((Binary & 0xfe000000) == 0xf2000000 &&
1690         "not an ARM NEON data-processing instruction");
1691  unsigned UBit = (Binary >> 24) & 1;
1692  return 0xef000000 | (UBit << 28) | (Binary & 0xffffff);
1693}
1694
1695void ARMCodeEmitter::emitNEONLaneInstruction(const MachineInstr &MI) {
1696  unsigned Binary = getBinaryCodeForInstr(MI);
1697
1698  unsigned RegTOpIdx, RegNOpIdx, LnOpIdx;
1699  const TargetInstrDesc &TID = MI.getDesc();
1700  if ((TID.TSFlags & ARMII::FormMask) == ARMII::NGetLnFrm) {
1701    RegTOpIdx = 0;
1702    RegNOpIdx = 1;
1703    LnOpIdx = 2;
1704  } else { // ARMII::NSetLnFrm
1705    RegTOpIdx = 2;
1706    RegNOpIdx = 0;
1707    LnOpIdx = 3;
1708  }
1709
1710  // Set the conditional execution predicate
1711  Binary |= (IsThumb ? ARMCC::AL : II->getPredicate(&MI)) << ARMII::CondShift;
1712
1713  unsigned RegT = MI.getOperand(RegTOpIdx).getReg();
1714  RegT = getARMRegisterNumbering(RegT);
1715  Binary |= (RegT << ARMII::RegRdShift);
1716  Binary |= encodeNEONRn(MI, RegNOpIdx);
1717
1718  unsigned LaneShift;
1719  if ((Binary & (1 << 22)) != 0)
1720    LaneShift = 0; // 8-bit elements
1721  else if ((Binary & (1 << 5)) != 0)
1722    LaneShift = 1; // 16-bit elements
1723  else
1724    LaneShift = 2; // 32-bit elements
1725
1726  unsigned Lane = MI.getOperand(LnOpIdx).getImm() << LaneShift;
1727  unsigned Opc1 = Lane >> 2;
1728  unsigned Opc2 = Lane & 3;
1729  assert((Opc1 & 3) == 0 && "out-of-range lane number operand");
1730  Binary |= (Opc1 << 21);
1731  Binary |= (Opc2 << 5);
1732
1733  emitWordLE(Binary);
1734}
1735
1736void ARMCodeEmitter::emitNEONDupInstruction(const MachineInstr &MI) {
1737  unsigned Binary = getBinaryCodeForInstr(MI);
1738
1739  // Set the conditional execution predicate
1740  Binary |= (IsThumb ? ARMCC::AL : II->getPredicate(&MI)) << ARMII::CondShift;
1741
1742  unsigned RegT = MI.getOperand(1).getReg();
1743  RegT = getARMRegisterNumbering(RegT);
1744  Binary |= (RegT << ARMII::RegRdShift);
1745  Binary |= encodeNEONRn(MI, 0);
1746  emitWordLE(Binary);
1747}
1748
1749void ARMCodeEmitter::emitNEON1RegModImmInstruction(const MachineInstr &MI) {
1750  unsigned Binary = getBinaryCodeForInstr(MI);
1751  // Destination register is encoded in Dd.
1752  Binary |= encodeNEONRd(MI, 0);
1753  // Immediate fields: Op, Cmode, I, Imm3, Imm4
1754  unsigned Imm = MI.getOperand(1).getImm();
1755  unsigned Op = (Imm >> 12) & 1;
1756  unsigned Cmode = (Imm >> 8) & 0xf;
1757  unsigned I = (Imm >> 7) & 1;
1758  unsigned Imm3 = (Imm >> 4) & 0x7;
1759  unsigned Imm4 = Imm & 0xf;
1760  Binary |= (I << 24) | (Imm3 << 16) | (Cmode << 8) | (Op << 5) | Imm4;
1761  if (IsThumb)
1762    Binary = convertNEONDataProcToThumb(Binary);
1763  emitWordLE(Binary);
1764}
1765
1766void ARMCodeEmitter::emitNEON2RegInstruction(const MachineInstr &MI) {
1767  const TargetInstrDesc &TID = MI.getDesc();
1768  unsigned Binary = getBinaryCodeForInstr(MI);
1769  // Destination register is encoded in Dd; source register in Dm.
1770  unsigned OpIdx = 0;
1771  Binary |= encodeNEONRd(MI, OpIdx++);
1772  if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1773    ++OpIdx;
1774  Binary |= encodeNEONRm(MI, OpIdx);
1775  if (IsThumb)
1776    Binary = convertNEONDataProcToThumb(Binary);
1777  // FIXME: This does not handle VDUPfdf or VDUPfqf.
1778  emitWordLE(Binary);
1779}
1780
1781void ARMCodeEmitter::emitNEON3RegInstruction(const MachineInstr &MI) {
1782  const TargetInstrDesc &TID = MI.getDesc();
1783  unsigned Binary = getBinaryCodeForInstr(MI);
1784  // Destination register is encoded in Dd; source registers in Dn and Dm.
1785  unsigned OpIdx = 0;
1786  Binary |= encodeNEONRd(MI, OpIdx++);
1787  if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1788    ++OpIdx;
1789  Binary |= encodeNEONRn(MI, OpIdx++);
1790  if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1791    ++OpIdx;
1792  Binary |= encodeNEONRm(MI, OpIdx);
1793  if (IsThumb)
1794    Binary = convertNEONDataProcToThumb(Binary);
1795  // FIXME: This does not handle VMOVDneon or VMOVQ.
1796  emitWordLE(Binary);
1797}
1798
1799#include "ARMGenCodeEmitter.inc"
1800